drivers/net/ethernet/mellanox/mlx5/core/en_rx.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/prefetch.h>
  34 #include <linux/ip.h>
  35 #include <linux/ipv6.h>
  36 #include <linux/tcp.h>
  37 #include <net/busy_poll.h>
  38 #include <net/ip6_checksum.h>
  39 #include <net/page_pool.h>
  40 #include <net/inet_ecn.h>
  41 #include "en.h"
  42 #include "en_tc.h"
  43 #include "eswitch.h"
  44 #include "en_rep.h"
  45 #include "ipoib/ipoib.h"
  46 #include "en_accel/ipsec_rxtx.h"
  47 #include "en_accel/tls_rxtx.h"
  48 #include "lib/clock.h"
  49 #include "en/xdp.h"
  50
  51 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config)
  52 {
  53         return config->rx_filter == HWTSTAMP_FILTER_ALL;
  54 }
  55
  56 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
  57                                        void *data)
  58 {
  59         u32 ci = mlx5_cqwq_ctr2ix(&cq->wq, cqcc);
  60
  61         memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
  62 }
  63
  64 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
  65                                          struct mlx5e_cq *cq, u32 cqcc)
  66 {
  67         mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
  68         cq->decmprs_left        = be32_to_cpu(cq->title.byte_cnt);
  69         cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
  70         rq->stats->cqe_compress_blks++;
  71 }
  72
  73 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
  74 {
  75         mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
  76         cq->mini_arr_idx = 0;
  77 }
  78
  79 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
  80 {
  81         struct mlx5_cqwq *wq = &cq->wq;
  82
  83         u8  op_own = mlx5_cqwq_get_ctr_wrap_cnt(wq, cqcc) & 1;
  84         u32 ci     = mlx5_cqwq_ctr2ix(wq, cqcc);
  85         u32 wq_sz  = mlx5_cqwq_get_size(wq);
  86         u32 ci_top = min_t(u32, wq_sz, ci + n);
  87
  88         for (; ci < ci_top; ci++, n--) {
  89                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
  90
  91                 cqe->op_own = op_own;
  92         }
  93
  94         if (unlikely(ci == wq_sz)) {
  95                 op_own = !op_own;
  96                 for (ci = 0; ci < n; ci++) {
  97                         struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
  98
  99                         cqe->op_own = op_own;
 100                 }
 101         }
 102 }
 103
 104 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
 105                                         struct mlx5e_cq *cq, u32 cqcc)
 106 {
 107         cq->title.byte_cnt     = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
 108         cq->title.check_sum    = cq->mini_arr[cq->mini_arr_idx].checksum;
 109         cq->title.op_own      &= 0xf0;
 110         cq->title.op_own      |= 0x01 & (cqcc >> cq->wq.fbc.log_sz);
 111         cq->title.wqe_counter  = cpu_to_be16(cq->decmprs_wqe_counter);
 112
 113         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 114                 cq->decmprs_wqe_counter +=
 115                         mpwrq_get_cqe_consumed_strides(&cq->title);
 116         else
 117                 cq->decmprs_wqe_counter =
 118                         mlx5_wq_cyc_ctr2ix(&rq->wqe.wq, cq->decmprs_wqe_counter + 1);
 119 }
 120
 121 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
 122                                                 struct mlx5e_cq *cq, u32 cqcc)
 123 {
 124         mlx5e_decompress_cqe(rq, cq, cqcc);
 125         cq->title.rss_hash_type   = 0;
 126         cq->title.rss_hash_result = 0;
 127 }
 128
 129 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
 130                                              struct mlx5e_cq *cq,
 131                                              int update_owner_only,
 132                                              int budget_rem)
 133 {
 134         u32 cqcc = cq->wq.cc + update_owner_only;
 135         u32 cqe_count;
 136         u32 i;
 137
 138         cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
 139
 140         for (i = update_owner_only; i < cqe_count;
 141              i++, cq->mini_arr_idx++, cqcc++) {
 142                 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
 143                         mlx5e_read_mini_arr_slot(cq, cqcc);
 144
 145                 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
 146                 rq->handle_rx_cqe(rq, &cq->title);
 147         }
 148         mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
 149         cq->wq.cc = cqcc;
 150         cq->decmprs_left -= cqe_count;
 151         rq->stats->cqe_compress_pkts += cqe_count;
 152
 153         return cqe_count;
 154 }
 155
 156 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
 157                                               struct mlx5e_cq *cq,
 158                                               int budget_rem)
 159 {
 160         mlx5e_read_title_slot(rq, cq, cq->wq.cc);
 161         mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
 162         mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
 163         rq->handle_rx_cqe(rq, &cq->title);
 164         cq->mini_arr_idx++;
 165
 166         return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
 167 }
 168
 169 static inline bool mlx5e_page_is_reserved(struct page *page)
 170 {
 171         return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id();
 172 }
 173
 174 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
 175                                       struct mlx5e_dma_info *dma_info)
 176 {
 177         struct mlx5e_page_cache *cache = &rq->page_cache;
 178         u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
 179         struct mlx5e_rq_stats *stats = rq->stats;
 180
 181         if (tail_next == cache->head) {
 182                 stats->cache_full++;
 183                 return false;
 184         }
 185
 186         if (unlikely(mlx5e_page_is_reserved(dma_info->page))) {
 187                 stats->cache_waive++;
 188                 return false;
 189         }
 190
 191         cache->page_cache[cache->tail] = *dma_info;
 192         cache->tail = tail_next;
 193         return true;
 194 }
 195
 196 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
 197                                       struct mlx5e_dma_info *dma_info)
 198 {
 199         struct mlx5e_page_cache *cache = &rq->page_cache;
 200         struct mlx5e_rq_stats *stats = rq->stats;
 201
 202         if (unlikely(cache->head == cache->tail)) {
 203                 stats->cache_empty++;
 204                 return false;
 205         }
 206
 207         if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
 208                 stats->cache_busy++;
 209                 return false;
 210         }
 211
 212         *dma_info = cache->page_cache[cache->head];
 213         cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
 214         stats->cache_reuse++;
 215
 216         dma_sync_single_for_device(rq->pdev, dma_info->addr,
 217                                    PAGE_SIZE,
 218                                    DMA_FROM_DEVICE);
 219         return true;
 220 }
 221
 222 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq,
 223                                           struct mlx5e_dma_info *dma_info)
 224 {
 225         if (mlx5e_rx_cache_get(rq, dma_info))
 226                 return 0;
 227
 228         dma_info->page = page_pool_dev_alloc_pages(rq->page_pool);
 229         if (unlikely(!dma_info->page))
 230                 return -ENOMEM;
 231
 232         dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
 233                                       PAGE_SIZE, rq->buff.map_dir);
 234         if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
 235                 put_page(dma_info->page);
 236                 dma_info->page = NULL;
 237                 return -ENOMEM;
 238         }
 239
 240         return 0;
 241 }
 242
 243 void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info)
 244 {
 245         dma_unmap_page(rq->pdev, dma_info->addr, PAGE_SIZE, rq->buff.map_dir);
 246 }
 247
 248 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
 249                         bool recycle)
 250 {
 251         if (likely(recycle)) {
 252                 if (mlx5e_rx_cache_put(rq, dma_info))
 253                         return;
 254
 255                 mlx5e_page_dma_unmap(rq, dma_info);
 256                 page_pool_recycle_direct(rq->page_pool, dma_info->page);
 257         } else {
 258                 mlx5e_page_dma_unmap(rq, dma_info);
 259                 put_page(dma_info->page);
 260         }
 261 }
 262
 263 static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq,
 264                                     struct mlx5e_wqe_frag_info *frag)
 265 {
 266         int err = 0;
 267
 268         if (!frag->offset)
 269                 /* On first frag (offset == 0), replenish page (dma_info actually).
 270                  * Other frags that point to the same dma_info (with a different
 271                  * offset) should just use the new one without replenishing again
 272                  * by themselves.
 273                  */
 274                 err = mlx5e_page_alloc_mapped(rq, frag->di);
 275
 276         return err;
 277 }
 278
 279 static inline void mlx5e_put_rx_frag(struct mlx5e_rq *rq,
 280                                      struct mlx5e_wqe_frag_info *frag,
 281                                      bool recycle)
 282 {
 283         if (frag->last_in_page)
 284                 mlx5e_page_release(rq, frag->di, recycle);
 285 }
 286
 287 static inline struct mlx5e_wqe_frag_info *get_frag(struct mlx5e_rq *rq, u16 ix)
 288 {
 289         return &rq->wqe.frags[ix << rq->wqe.info.log_num_frags];
 290 }
 291
 292 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe_cyc *wqe,
 293                               u16 ix)
 294 {
 295         struct mlx5e_wqe_frag_info *frag = get_frag(rq, ix);
 296         int err;
 297         int i;
 298
 299         for (i = 0; i < rq->wqe.info.num_frags; i++, frag++) {
 300                 err = mlx5e_get_rx_frag(rq, frag);
 301                 if (unlikely(err))
 302                         goto free_frags;
 303
 304                 wqe->data[i].addr = cpu_to_be64(frag->di->addr +
 305                                                 frag->offset + rq->buff.headroom);
 306         }
 307
 308         return 0;
 309
 310 free_frags:
 311         while (--i >= 0)
 312                 mlx5e_put_rx_frag(rq, --frag, true);
 313
 314         return err;
 315 }
 316
 317 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
 318                                      struct mlx5e_wqe_frag_info *wi,
 319                                      bool recycle)
 320 {
 321         int i;
 322
 323         for (i = 0; i < rq->wqe.info.num_frags; i++, wi++)
 324                 mlx5e_put_rx_frag(rq, wi, recycle);
 325 }
 326
 327 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
 328 {
 329         struct mlx5e_wqe_frag_info *wi = get_frag(rq, ix);
 330
 331         mlx5e_free_rx_wqe(rq, wi, false);
 332 }
 333
 334 static int mlx5e_alloc_rx_wqes(struct mlx5e_rq *rq, u16 ix, u8 wqe_bulk)
 335 {
 336         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 337         int err;
 338         int i;
 339
 340         for (i = 0; i < wqe_bulk; i++) {
 341                 struct mlx5e_rx_wqe_cyc *wqe = mlx5_wq_cyc_get_wqe(wq, ix + i);
 342
 343                 err = mlx5e_alloc_rx_wqe(rq, wqe, ix + i);
 344                 if (unlikely(err))
 345                         goto free_wqes;
 346         }
 347
 348         return 0;
 349
 350 free_wqes:
 351         while (--i >= 0)
 352                 mlx5e_dealloc_rx_wqe(rq, ix + i);
 353
 354         return err;
 355 }
 356
 357 static inline void
 358 mlx5e_add_skb_frag(struct mlx5e_rq *rq, struct sk_buff *skb,
 359                    struct mlx5e_dma_info *di, u32 frag_offset, u32 len,
 360                    unsigned int truesize)
 361 {
 362         dma_sync_single_for_cpu(rq->pdev,
 363                                 di->addr + frag_offset,
 364                                 len, DMA_FROM_DEVICE);
 365         page_ref_inc(di->page);
 366         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
 367                         di->page, frag_offset, len, truesize);
 368 }
 369
 370 static inline void
 371 mlx5e_copy_skb_header(struct device *pdev, struct sk_buff *skb,
 372                       struct mlx5e_dma_info *dma_info,
 373                       int offset_from, int offset_to, u32 headlen)
 374 {
 375         const void *from = page_address(dma_info->page) + offset_from;
 376         /* Aligning len to sizeof(long) optimizes memcpy performance */
 377         unsigned int len = ALIGN(headlen, sizeof(long));
 378
 379         dma_sync_single_for_cpu(pdev, dma_info->addr + offset_from, len,
 380                                 DMA_FROM_DEVICE);
 381         skb_copy_to_linear_data_offset(skb, offset_to, from, len);
 382 }
 383
 384 static inline void
 385 mlx5e_copy_skb_header_mpwqe(struct device *pdev,
 386                             struct sk_buff *skb,
 387                             struct mlx5e_dma_info *dma_info,
 388                             u32 offset, u32 headlen)
 389 {
 390         u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
 391
 392         mlx5e_copy_skb_header(pdev, skb, dma_info, offset, 0, headlen_pg);
 393
 394         if (unlikely(offset + headlen > PAGE_SIZE)) {
 395                 dma_info++;
 396                 mlx5e_copy_skb_header(pdev, skb, dma_info, 0, headlen_pg,
 397                                       headlen - headlen_pg);
 398         }
 399 }
 400
 401 static void
 402 mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, bool recycle)
 403 {
 404         const bool no_xdp_xmit =
 405                 bitmap_empty(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
 406         struct mlx5e_dma_info *dma_info = wi->umr.dma_info;
 407         int i;
 408
 409         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++)
 410                 if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap))
 411                         mlx5e_page_release(rq, &dma_info[i], recycle);
 412 }
 413
 414 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)
 415 {
 416         struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 417         struct mlx5e_rx_wqe_ll *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
 418
 419         rq->mpwqe.umr_in_progress = false;
 420
 421         mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
 422
 423         /* ensure wqes are visible to device before updating doorbell record */
 424         dma_wmb();
 425
 426         mlx5_wq_ll_update_db_record(wq);
 427 }
 428
 429 static inline u16 mlx5e_icosq_wrap_cnt(struct mlx5e_icosq *sq)
 430 {
 431         return sq->pc >> MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
 432 }
 433
 434 static inline void mlx5e_fill_icosq_frag_edge(struct mlx5e_icosq *sq,
 435                                               struct mlx5_wq_cyc *wq,
 436                                               u16 pi, u16 nnops)
 437 {
 438         struct mlx5e_sq_wqe_info *edge_wi, *wi = &sq->db.ico_wqe[pi];
 439
 440         edge_wi = wi + nnops;
 441
 442         /* fill sq frag edge with nops to avoid wqe wrapping two pages */
 443         for (; wi < edge_wi; wi++) {
 444                 wi->opcode = MLX5_OPCODE_NOP;
 445                 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
 446         }
 447 }
 448
 449 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 450 {
 451         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 452         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
 453         struct mlx5e_icosq *sq = &rq->channel->icosq;
 454         struct mlx5_wq_cyc *wq = &sq->wq;
 455         struct mlx5e_umr_wqe *umr_wqe;
 456         u16 xlt_offset = ix << (MLX5E_LOG_ALIGNED_MPWQE_PPW - 1);
 457         u16 pi, contig_wqebbs_room;
 458         int err;
 459         int i;
 460
 461         pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
 462         contig_wqebbs_room = mlx5_wq_cyc_get_contig_wqebbs(wq, pi);
 463         if (unlikely(contig_wqebbs_room < MLX5E_UMR_WQEBBS)) {
 464                 mlx5e_fill_icosq_frag_edge(sq, wq, pi, contig_wqebbs_room);
 465                 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
 466         }
 467
 468         umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi);
 469         if (unlikely(mlx5e_icosq_wrap_cnt(sq) < 2))
 470                 memcpy(umr_wqe, &rq->mpwqe.umr_wqe,
 471                        offsetof(struct mlx5e_umr_wqe, inline_mtts));
 472
 473         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
 474                 err = mlx5e_page_alloc_mapped(rq, dma_info);
 475                 if (unlikely(err))
 476                         goto err_unmap;
 477                 umr_wqe->inline_mtts[i].ptag = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
 478         }
 479
 480         bitmap_zero(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
 481         wi->consumed_strides = 0;
 482
 483         rq->mpwqe.umr_in_progress = true;
 484
 485         umr_wqe->ctrl.opmod_idx_opcode =
 486                 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
 487                             MLX5_OPCODE_UMR);
 488         umr_wqe->uctrl.xlt_offset = cpu_to_be16(xlt_offset);
 489
 490         sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
 491         sq->pc += MLX5E_UMR_WQEBBS;
 492         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &umr_wqe->ctrl);
 493
 494         return 0;
 495
 496 err_unmap:
 497         while (--i >= 0) {
 498                 dma_info--;
 499                 mlx5e_page_release(rq, dma_info, true);
 500         }
 501         rq->stats->buff_alloc_err++;
 502
 503         return err;
 504 }
 505
 506 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 507 {
 508         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 509         /* Don't recycle, this function is called on rq/netdev close */
 510         mlx5e_free_rx_mpwqe(rq, wi, false);
 511 }
 512
 513 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
 514 {
 515         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 516         u8 wqe_bulk;
 517         int err;
 518
 519         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
 520                 return false;
 521
 522         wqe_bulk = rq->wqe.info.wqe_bulk;
 523
 524         if (mlx5_wq_cyc_missing(wq) < wqe_bulk)
 525                 return false;
 526
 527         do {
 528                 u16 head = mlx5_wq_cyc_get_head(wq);
 529
 530                 err = mlx5e_alloc_rx_wqes(rq, head, wqe_bulk);
 531                 if (unlikely(err)) {
 532                         rq->stats->buff_alloc_err++;
 533                         break;
 534                 }
 535
 536                 mlx5_wq_cyc_push_n(wq, wqe_bulk);
 537         } while (mlx5_wq_cyc_missing(wq) >= wqe_bulk);
 538
 539         /* ensure wqes are visible to device before updating doorbell record */
 540         dma_wmb();
 541
 542         mlx5_wq_cyc_update_db_record(wq);
 543
 544         return !!err;
 545 }
 546
 547 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq,
 548                                              struct mlx5e_icosq *sq,
 549                                              struct mlx5e_rq *rq,
 550                                              struct mlx5_cqe64 *cqe)
 551 {
 552         struct mlx5_wq_cyc *wq = &sq->wq;
 553         u16 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
 554         struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci];
 555
 556         mlx5_cqwq_pop(&cq->wq);
 557
 558         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) {
 559                 netdev_WARN_ONCE(cq->channel->netdev,
 560                                  "Bad OP in ICOSQ CQE: 0x%x\n", cqe->op_own);
 561                 return;
 562         }
 563
 564         if (likely(icowi->opcode == MLX5_OPCODE_UMR)) {
 565                 mlx5e_post_rx_mpwqe(rq);
 566                 return;
 567         }
 568
 569         if (unlikely(icowi->opcode != MLX5_OPCODE_NOP))
 570                 netdev_WARN_ONCE(cq->channel->netdev,
 571                                  "Bad OPCODE in ICOSQ WQE info: 0x%x\n", icowi->opcode);
 572 }
 573
 574 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq)
 575 {
 576         struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
 577         struct mlx5_cqe64 *cqe;
 578
 579         if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
 580                 return;
 581
 582         cqe = mlx5_cqwq_get_cqe(&cq->wq);
 583         if (likely(!cqe))
 584                 return;
 585
 586         /* by design, there's only a single cqe */
 587         mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe);
 588
 589         mlx5_cqwq_update_db_record(&cq->wq);
 590 }
 591
 592 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
 593 {
 594         struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 595
 596         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
 597                 return false;
 598
 599         mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq);
 600
 601         if (mlx5_wq_ll_is_full(wq))
 602                 return false;
 603
 604         if (!rq->mpwqe.umr_in_progress)
 605                 mlx5e_alloc_rx_mpwqe(rq, wq->head);
 606         else
 607                 rq->stats->congst_umr += mlx5_wq_ll_missing(wq) > 2;
 608
 609         return false;
 610 }
 611
 612 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp)
 613 {
 614         u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
 615         u8 tcp_ack     = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
 616                          (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
 617
 618         tcp->check                      = 0;
 619         tcp->psh                        = get_cqe_lro_tcppsh(cqe);
 620
 621         if (tcp_ack) {
 622                 tcp->ack                = 1;
 623                 tcp->ack_seq            = cqe->lro_ack_seq_num;
 624                 tcp->window             = cqe->lro_tcp_win;
 625         }
 626 }
 627
 628 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
 629                                  u32 cqe_bcnt)
 630 {
 631         struct ethhdr   *eth = (struct ethhdr *)(skb->data);
 632         struct tcphdr   *tcp;
 633         int network_depth = 0;
 634         __wsum check;
 635         __be16 proto;
 636         u16 tot_len;
 637         void *ip_p;
 638
 639         proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
 640
 641         tot_len = cqe_bcnt - network_depth;
 642         ip_p = skb->data + network_depth;
 643
 644         if (proto == htons(ETH_P_IP)) {
 645                 struct iphdr *ipv4 = ip_p;
 646
 647                 tcp = ip_p + sizeof(struct iphdr);
 648                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
 649
 650                 ipv4->ttl               = cqe->lro_min_ttl;
 651                 ipv4->tot_len           = cpu_to_be16(tot_len);
 652                 ipv4->check             = 0;
 653                 ipv4->check             = ip_fast_csum((unsigned char *)ipv4,
 654                                                        ipv4->ihl);
 655
 656                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
 657                 check = csum_partial(tcp, tcp->doff * 4,
 658                                      csum_unfold((__force __sum16)cqe->check_sum));
 659                 /* Almost done, don't forget the pseudo header */
 660                 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr,
 661                                                tot_len - sizeof(struct iphdr),
 662                                                IPPROTO_TCP, check);
 663         } else {
 664                 u16 payload_len = tot_len - sizeof(struct ipv6hdr);
 665                 struct ipv6hdr *ipv6 = ip_p;
 666
 667                 tcp = ip_p + sizeof(struct ipv6hdr);
 668                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
 669
 670                 ipv6->hop_limit         = cqe->lro_min_ttl;
 671                 ipv6->payload_len       = cpu_to_be16(payload_len);
 672
 673                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
 674                 check = csum_partial(tcp, tcp->doff * 4,
 675                                      csum_unfold((__force __sum16)cqe->check_sum));
 676                 /* Almost done, don't forget the pseudo header */
 677                 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len,
 678                                              IPPROTO_TCP, check);
 679         }
 680 }
 681
 682 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
 683                                       struct sk_buff *skb)
 684 {
 685         u8 cht = cqe->rss_hash_type;
 686         int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
 687                  (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
 688                                             PKT_HASH_TYPE_NONE;
 689         skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
 690 }
 691
 692 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth,
 693                                         __be16 *proto)
 694 {
 695         *proto = ((struct ethhdr *)skb->data)->h_proto;
 696         *proto = __vlan_get_protocol(skb, *proto, network_depth);
 697         return (*proto == htons(ETH_P_IP) || *proto == htons(ETH_P_IPV6));
 698 }
 699
 700 static inline void mlx5e_enable_ecn(struct mlx5e_rq *rq, struct sk_buff *skb)
 701 {
 702         int network_depth = 0;
 703         __be16 proto;
 704         void *ip;
 705         int rc;
 706
 707         if (unlikely(!is_last_ethertype_ip(skb, &network_depth, &proto)))
 708                 return;
 709
 710         ip = skb->data + network_depth;
 711         rc = ((proto == htons(ETH_P_IP)) ? IP_ECN_set_ce((struct iphdr *)ip) :
 712                                          IP6_ECN_set_ce(skb, (struct ipv6hdr *)ip));
 713
 714         rq->stats->ecn_mark += !!rc;
 715 }
 716
 717 static u32 mlx5e_get_fcs(const struct sk_buff *skb)
 718 {
 719         const void *fcs_bytes;
 720         u32 _fcs_bytes;
 721
 722         fcs_bytes = skb_header_pointer(skb, skb->len - ETH_FCS_LEN,
 723                                        ETH_FCS_LEN, &_fcs_bytes);
 724
 725         return __get_unaligned_cpu32(fcs_bytes);
 726 }
 727
 728 static u8 get_ip_proto(struct sk_buff *skb, int network_depth, __be16 proto)
 729 {
 730         void *ip_p = skb->data + network_depth;
 731
 732         return (proto == htons(ETH_P_IP)) ? ((struct iphdr *)ip_p)->protocol :
 733                                             ((struct ipv6hdr *)ip_p)->nexthdr;
 734 }
 735
 736 #define short_frame(size) ((size) <= ETH_ZLEN + ETH_FCS_LEN)
 737
 738 static inline void mlx5e_handle_csum(struct net_device *netdev,
 739                                      struct mlx5_cqe64 *cqe,
 740                                      struct mlx5e_rq *rq,
 741                                      struct sk_buff *skb,
 742                                      bool   lro)
 743 {
 744         struct mlx5e_rq_stats *stats = rq->stats;
 745         int network_depth = 0;
 746         __be16 proto;
 747
 748         if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
 749                 goto csum_none;
 750
 751         if (lro) {
 752                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 753                 stats->csum_unnecessary++;
 754                 return;
 755         }
 756
 757         /* True when explicitly set via priv flag, or XDP prog is loaded */
 758         if (test_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state))
 759                 goto csum_unnecessary;
 760
 761         /* CQE csum doesn't cover padding octets in short ethernet
 762          * frames. And the pad field is appended prior to calculating
 763          * and appending the FCS field.
 764          *
 765          * Detecting these padded frames requires to verify and parse
 766          * IP headers, so we simply force all those small frames to be
 767          * CHECKSUM_UNNECESSARY even if they are not padded.
 768          */
 769         if (short_frame(skb->len))
 770                 goto csum_unnecessary;
 771
 772         if (likely(is_last_ethertype_ip(skb, &network_depth, &proto))) {
 773                 if (unlikely(get_ip_proto(skb, network_depth, proto) == IPPROTO_SCTP))
 774                         goto csum_unnecessary;
 775
 776                 skb->ip_summed = CHECKSUM_COMPLETE;
 777                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
 778                 if (network_depth > ETH_HLEN)
 779                         /* CQE csum is calculated from the IP header and does
 780                          * not cover VLAN headers (if present). This will add
 781                          * the checksum manually.
 782                          */
 783                         skb->csum = csum_partial(skb->data + ETH_HLEN,
 784                                                  network_depth - ETH_HLEN,
 785                                                  skb->csum);
 786                 if (unlikely(netdev->features & NETIF_F_RXFCS))
 787                         skb->csum = csum_block_add(skb->csum,
 788                                                    (__force __wsum)mlx5e_get_fcs(skb),
 789                                                    skb->len - ETH_FCS_LEN);
 790                 stats->csum_complete++;
 791                 return;
 792         }
 793
 794 csum_unnecessary:
 795         if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
 796                    (cqe->hds_ip_ext & CQE_L4_OK))) {
 797                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 798                 if (cqe_is_tunneled(cqe)) {
 799                         skb->csum_level = 1;
 800                         skb->encapsulation = 1;
 801                         stats->csum_unnecessary_inner++;
 802                         return;
 803                 }
 804                 stats->csum_unnecessary++;
 805                 return;
 806         }
 807 csum_none:
 808         skb->ip_summed = CHECKSUM_NONE;
 809         stats->csum_none++;
 810 }
 811
 812 #define MLX5E_CE_BIT_MASK 0x80
 813
 814 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
 815                                       u32 cqe_bcnt,
 816                                       struct mlx5e_rq *rq,
 817                                       struct sk_buff *skb)
 818 {
 819         u8 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
 820         struct mlx5e_rq_stats *stats = rq->stats;
 821         struct net_device *netdev = rq->netdev;
 822
 823         skb->mac_len = ETH_HLEN;
 824
 825 #ifdef CONFIG_MLX5_EN_TLS
 826         mlx5e_tls_handle_rx_skb(netdev, skb, &cqe_bcnt);
 827 #endif
 828
 829         if (lro_num_seg > 1) {
 830                 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
 831                 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
 832                 /* Subtract one since we already counted this as one
 833                  * "regular" packet in mlx5e_complete_rx_cqe()
 834                  */
 835                 stats->packets += lro_num_seg - 1;
 836                 stats->lro_packets++;
 837                 stats->lro_bytes += cqe_bcnt;
 838         }
 839
 840         if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp)))
 841                 skb_hwtstamps(skb)->hwtstamp =
 842                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
 843
 844         skb_record_rx_queue(skb, rq->ix);
 845
 846         if (likely(netdev->features & NETIF_F_RXHASH))
 847                 mlx5e_skb_set_hash(cqe, skb);
 848
 849         if (cqe_has_vlan(cqe)) {
 850                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
 851                                        be16_to_cpu(cqe->vlan_info));
 852                 stats->removed_vlan_packets++;
 853         }
 854
 855         skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
 856
 857         mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
 858         /* checking CE bit in cqe - MSB in ml_path field */
 859         if (unlikely(cqe->ml_path & MLX5E_CE_BIT_MASK))
 860                 mlx5e_enable_ecn(rq, skb);
 861
 862         skb->protocol = eth_type_trans(skb, netdev);
 863 }
 864
 865 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
 866                                          struct mlx5_cqe64 *cqe,
 867                                          u32 cqe_bcnt,
 868                                          struct sk_buff *skb)
 869 {
 870         struct mlx5e_rq_stats *stats = rq->stats;
 871
 872         stats->packets++;
 873         stats->bytes += cqe_bcnt;
 874         mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
 875 }
 876
 877 static inline
 878 struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va,
 879                                        u32 frag_size, u16 headroom,
 880                                        u32 cqe_bcnt)
 881 {
 882         struct sk_buff *skb = build_skb(va, frag_size);
 883
 884         if (unlikely(!skb)) {
 885                 rq->stats->buff_alloc_err++;
 886                 return NULL;
 887         }
 888
 889         skb_reserve(skb, headroom);
 890         skb_put(skb, cqe_bcnt);
 891
 892         return skb;
 893 }
 894
 895 struct sk_buff *
 896 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
 897                           struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
 898 {
 899         struct mlx5e_dma_info *di = wi->di;
 900         u16 rx_headroom = rq->buff.headroom;
 901         struct sk_buff *skb;
 902         void *va, *data;
 903         bool consumed;
 904         u32 frag_size;
 905
 906         va             = page_address(di->page) + wi->offset;
 907         data           = va + rx_headroom;
 908         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
 909
 910         dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset,
 911                                       frag_size, DMA_FROM_DEVICE);
 912         prefetchw(va); /* xdp_frame data area */
 913         prefetch(data);
 914
 915         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
 916                 rq->stats->wqe_err++;
 917                 return NULL;
 918         }
 919
 920         rcu_read_lock();
 921         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt);
 922         rcu_read_unlock();
 923         if (consumed)
 924                 return NULL; /* page/packet was consumed by XDP */
 925
 926         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt);
 927         if (unlikely(!skb))
 928                 return NULL;
 929
 930         /* queue up for recycling/reuse */
 931         page_ref_inc(di->page);
 932
 933         return skb;
 934 }
 935
 936 struct sk_buff *
 937 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
 938                              struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
 939 {
 940         struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 941         struct mlx5e_wqe_frag_info *head_wi = wi;
 942         u16 headlen      = min_t(u32, MLX5E_RX_MAX_HEAD, cqe_bcnt);
 943         u16 frag_headlen = headlen;
 944         u16 byte_cnt     = cqe_bcnt - headlen;
 945         struct sk_buff *skb;
 946
 947         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
 948                 rq->stats->wqe_err++;
 949                 return NULL;
 950         }
 951
 952         /* XDP is not supported in this configuration, as incoming packets
 953          * might spread among multiple pages.
 954          */
 955         skb = napi_alloc_skb(rq->cq.napi,
 956                              ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
 957         if (unlikely(!skb)) {
 958                 rq->stats->buff_alloc_err++;
 959                 return NULL;
 960         }
 961
 962         prefetchw(skb->data);
 963
 964         while (byte_cnt) {
 965                 u16 frag_consumed_bytes =
 966                         min_t(u16, frag_info->frag_size - frag_headlen, byte_cnt);
 967
 968                 mlx5e_add_skb_frag(rq, skb, wi->di, wi->offset + frag_headlen,
 969                                    frag_consumed_bytes, frag_info->frag_stride);
 970                 byte_cnt -= frag_consumed_bytes;
 971                 frag_headlen = 0;
 972                 frag_info++;
 973                 wi++;
 974         }
 975
 976         /* copy header */
 977         mlx5e_copy_skb_header(rq->pdev, skb, head_wi->di, head_wi->offset,
 978                               0, headlen);
 979         /* skb linear part was allocated with headlen and aligned to long */
 980         skb->tail += headlen;
 981         skb->len  += headlen;
 982
 983         return skb;
 984 }
 985
 986 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
 987 {
 988         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 989         struct mlx5e_wqe_frag_info *wi;
 990         struct sk_buff *skb;
 991         u32 cqe_bcnt;
 992         u16 ci;
 993
 994         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
 995         wi       = get_frag(rq, ci);
 996         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
 997
 998         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
 999         if (!skb) {
1000                 /* probably for XDP */
1001                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1002                         /* do not return page to cache,
1003                          * it will be returned on XDP_TX completion.
1004                          */
1005                         goto wq_cyc_pop;
1006                 }
1007                 goto free_wqe;
1008         }
1009
1010         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1011         napi_gro_receive(rq->cq.napi, skb);
1012
1013 free_wqe:
1014         mlx5e_free_rx_wqe(rq, wi, true);
1015 wq_cyc_pop:
1016         mlx5_wq_cyc_pop(wq);
1017 }
1018
1019 #ifdef CONFIG_MLX5_ESWITCH
1020 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1021 {
1022         struct net_device *netdev = rq->netdev;
1023         struct mlx5e_priv *priv = netdev_priv(netdev);
1024         struct mlx5e_rep_priv *rpriv  = priv->ppriv;
1025         struct mlx5_eswitch_rep *rep = rpriv->rep;
1026         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1027         struct mlx5e_wqe_frag_info *wi;
1028         struct sk_buff *skb;
1029         u32 cqe_bcnt;
1030         u16 ci;
1031
1032         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1033         wi       = get_frag(rq, ci);
1034         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1035
1036         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1037         if (!skb) {
1038                 /* probably for XDP */
1039                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1040                         /* do not return page to cache,
1041                          * it will be returned on XDP_TX completion.
1042                          */
1043                         goto wq_cyc_pop;
1044                 }
1045                 goto free_wqe;
1046         }
1047
1048         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1049
1050         if (rep->vlan && skb_vlan_tag_present(skb))
1051                 skb_vlan_pop(skb);
1052
1053         napi_gro_receive(rq->cq.napi, skb);
1054
1055 free_wqe:
1056         mlx5e_free_rx_wqe(rq, wi, true);
1057 wq_cyc_pop:
1058         mlx5_wq_cyc_pop(wq);
1059 }
1060 #endif
1061
1062 struct sk_buff *
1063 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1064                                    u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1065 {
1066         u16 headlen = min_t(u16, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1067         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1068         u32 frag_offset    = head_offset + headlen;
1069         u32 byte_cnt       = cqe_bcnt - headlen;
1070         struct mlx5e_dma_info *head_di = di;
1071         struct sk_buff *skb;
1072
1073         skb = napi_alloc_skb(rq->cq.napi,
1074                              ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1075         if (unlikely(!skb)) {
1076                 rq->stats->buff_alloc_err++;
1077                 return NULL;
1078         }
1079
1080         prefetchw(skb->data);
1081
1082         if (unlikely(frag_offset >= PAGE_SIZE)) {
1083                 di++;
1084                 frag_offset -= PAGE_SIZE;
1085         }
1086
1087         while (byte_cnt) {
1088                 u32 pg_consumed_bytes =
1089                         min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
1090                 unsigned int truesize =
1091                         ALIGN(pg_consumed_bytes, BIT(rq->mpwqe.log_stride_sz));
1092
1093                 mlx5e_add_skb_frag(rq, skb, di, frag_offset,
1094                                    pg_consumed_bytes, truesize);
1095                 byte_cnt -= pg_consumed_bytes;
1096                 frag_offset = 0;
1097                 di++;
1098         }
1099         /* copy header */
1100         mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, head_di,
1101                                     head_offset, headlen);
1102         /* skb linear part was allocated with headlen and aligned to long */
1103         skb->tail += headlen;
1104         skb->len  += headlen;
1105
1106         return skb;
1107 }
1108
1109 struct sk_buff *
1110 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1111                                 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1112 {
1113         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1114         u16 rx_headroom = rq->buff.headroom;
1115         u32 cqe_bcnt32 = cqe_bcnt;
1116         struct sk_buff *skb;
1117         void *va, *data;
1118         u32 frag_size;
1119         bool consumed;
1120
1121         /* Check packet size. Note LRO doesn't use linear SKB */
1122         if (unlikely(cqe_bcnt > rq->hw_mtu)) {
1123                 rq->stats->oversize_pkts_sw_drop++;
1124                 return NULL;
1125         }
1126
1127         va             = page_address(di->page) + head_offset;
1128         data           = va + rx_headroom;
1129         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32);
1130
1131         dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset,
1132                                       frag_size, DMA_FROM_DEVICE);
1133         prefetchw(va); /* xdp_frame data area */
1134         prefetch(data);
1135
1136         rcu_read_lock();
1137         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt32);
1138         rcu_read_unlock();
1139         if (consumed) {
1140                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags))
1141                         __set_bit(page_idx, wi->xdp_xmit_bitmap); /* non-atomic */
1142                 return NULL; /* page/packet was consumed by XDP */
1143         }
1144
1145         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt32);
1146         if (unlikely(!skb))
1147                 return NULL;
1148
1149         /* queue up for recycling/reuse */
1150         page_ref_inc(di->page);
1151
1152         return skb;
1153 }
1154
1155 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1156 {
1157         u16 cstrides       = mpwrq_get_cqe_consumed_strides(cqe);
1158         u16 wqe_id         = be16_to_cpu(cqe->wqe_id);
1159         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1160         u16 stride_ix      = mpwrq_get_cqe_stride_index(cqe);
1161         u32 wqe_offset     = stride_ix << rq->mpwqe.log_stride_sz;
1162         u32 head_offset    = wqe_offset & (PAGE_SIZE - 1);
1163         u32 page_idx       = wqe_offset >> PAGE_SHIFT;
1164         struct mlx5e_rx_wqe_ll *wqe;
1165         struct mlx5_wq_ll *wq;
1166         struct sk_buff *skb;
1167         u16 cqe_bcnt;
1168
1169         wi->consumed_strides += cstrides;
1170
1171         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1172                 rq->stats->wqe_err++;
1173                 goto mpwrq_cqe_out;
1174         }
1175
1176         if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1177                 struct mlx5e_rq_stats *stats = rq->stats;
1178
1179                 stats->mpwqe_filler_cqes++;
1180                 stats->mpwqe_filler_strides += cstrides;
1181                 goto mpwrq_cqe_out;
1182         }
1183
1184         cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1185
1186         skb = rq->mpwqe.skb_from_cqe_mpwrq(rq, wi, cqe_bcnt, head_offset,
1187                                            page_idx);
1188         if (!skb)
1189                 goto mpwrq_cqe_out;
1190
1191         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1192         napi_gro_receive(rq->cq.napi, skb);
1193
1194 mpwrq_cqe_out:
1195         if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1196                 return;
1197
1198         wq  = &rq->mpwqe.wq;
1199         wqe = mlx5_wq_ll_get_wqe(wq, wqe_id);
1200         mlx5e_free_rx_mpwqe(rq, wi, true);
1201         mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1202 }
1203
1204 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1205 {
1206         struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1207         struct mlx5e_xdpsq *xdpsq = &rq->xdpsq;
1208         struct mlx5_cqe64 *cqe;
1209         int work_done = 0;
1210
1211         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
1212                 return 0;
1213
1214         if (cq->decmprs_left)
1215                 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
1216
1217         cqe = mlx5_cqwq_get_cqe(&cq->wq);
1218         if (!cqe) {
1219                 if (unlikely(work_done))
1220                         goto out;
1221                 return 0;
1222         }
1223
1224         do {
1225                 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1226                         work_done +=
1227                                 mlx5e_decompress_cqes_start(rq, cq,
1228                                                             budget - work_done);
1229                         continue;
1230                 }
1231
1232                 mlx5_cqwq_pop(&cq->wq);
1233
1234                 rq->handle_rx_cqe(rq, cqe);
1235         } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1236
1237 out:
1238         if (xdpsq->doorbell) {
1239                 mlx5e_xmit_xdp_doorbell(xdpsq);
1240                 xdpsq->doorbell = false;
1241         }
1242
1243         if (xdpsq->redirect_flush) {
1244                 xdp_do_flush_map();
1245                 xdpsq->redirect_flush = false;
1246         }
1247
1248         mlx5_cqwq_update_db_record(&cq->wq);
1249
1250         /* ensure cq space is freed before enabling more cqes */
1251         wmb();
1252
1253         return work_done;
1254 }
1255
1256 #ifdef CONFIG_MLX5_CORE_IPOIB
1257
1258 #define MLX5_IB_GRH_DGID_OFFSET 24
1259 #define MLX5_GID_SIZE           16
1260
1261 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1262                                          struct mlx5_cqe64 *cqe,
1263                                          u32 cqe_bcnt,
1264                                          struct sk_buff *skb)
1265 {
1266         struct mlx5e_rq_stats *stats = rq->stats;
1267         struct hwtstamp_config *tstamp;
1268         struct net_device *netdev;
1269         struct mlx5e_priv *priv;
1270         char *pseudo_header;
1271         u32 qpn;
1272         u8 *dgid;
1273         u8 g;
1274
1275         qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff;
1276         netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn);
1277
1278         /* No mapping present, cannot process SKB. This might happen if a child
1279          * interface is going down while having unprocessed CQEs on parent RQ
1280          */
1281         if (unlikely(!netdev)) {
1282                 /* TODO: add drop counters support */
1283                 skb->dev = NULL;
1284                 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn);
1285                 return;
1286         }
1287
1288         priv = mlx5i_epriv(netdev);
1289         tstamp = &priv->tstamp;
1290
1291         g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
1292         dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1293         if ((!g) || dgid[0] != 0xff)
1294                 skb->pkt_type = PACKET_HOST;
1295         else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1296                 skb->pkt_type = PACKET_BROADCAST;
1297         else
1298                 skb->pkt_type = PACKET_MULTICAST;
1299
1300         /* TODO: IB/ipoib: Allow mcast packets from other VFs
1301          * 68996a6e760e5c74654723eeb57bf65628ae87f4
1302          */
1303
1304         skb_pull(skb, MLX5_IB_GRH_BYTES);
1305
1306         skb->protocol = *((__be16 *)(skb->data));
1307
1308         skb->ip_summed = CHECKSUM_COMPLETE;
1309         skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1310
1311         if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1312                 skb_hwtstamps(skb)->hwtstamp =
1313                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1314
1315         skb_record_rx_queue(skb, rq->ix);
1316
1317         if (likely(netdev->features & NETIF_F_RXHASH))
1318                 mlx5e_skb_set_hash(cqe, skb);
1319
1320         /* 20 bytes of ipoib header and 4 for encap existing */
1321         pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1322         memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1323         skb_reset_mac_header(skb);
1324         skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1325
1326         skb->dev = netdev;
1327
1328         stats->csum_complete++;
1329         stats->packets++;
1330         stats->bytes += cqe_bcnt;
1331 }
1332
1333 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1334 {
1335         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1336         struct mlx5e_wqe_frag_info *wi;
1337         struct sk_buff *skb;
1338         u32 cqe_bcnt;
1339         u16 ci;
1340
1341         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1342         wi       = get_frag(rq, ci);
1343         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1344
1345         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1346         if (!skb)
1347                 goto wq_free_wqe;
1348
1349         mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1350         if (unlikely(!skb->dev)) {
1351                 dev_kfree_skb_any(skb);
1352                 goto wq_free_wqe;
1353         }
1354         napi_gro_receive(rq->cq.napi, skb);
1355
1356 wq_free_wqe:
1357         mlx5e_free_rx_wqe(rq, wi, true);
1358         mlx5_wq_cyc_pop(wq);
1359 }
1360
1361 #endif /* CONFIG_MLX5_CORE_IPOIB */
1362
1363 #ifdef CONFIG_MLX5_EN_IPSEC
1364
1365 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1366 {
1367         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1368         struct mlx5e_wqe_frag_info *wi;
1369         struct sk_buff *skb;
1370         u32 cqe_bcnt;
1371         u16 ci;
1372
1373         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1374         wi       = get_frag(rq, ci);
1375         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1376
1377         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1378         if (unlikely(!skb)) {
1379                 /* a DROP, save the page-reuse checks */
1380                 mlx5e_free_rx_wqe(rq, wi, true);
1381                 goto wq_cyc_pop;
1382         }
1383         skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb, &cqe_bcnt);
1384         if (unlikely(!skb)) {
1385                 mlx5e_free_rx_wqe(rq, wi, true);
1386                 goto wq_cyc_pop;
1387         }
1388
1389         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1390         napi_gro_receive(rq->cq.napi, skb);
1391
1392         mlx5e_free_rx_wqe(rq, wi, true);
1393 wq_cyc_pop:
1394         mlx5_wq_cyc_pop(wq);
1395 }
1396
1397 #endif /* CONFIG_MLX5_EN_IPSEC */