2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/prefetch.h>
35 #include <linux/ipv6.h>
36 #include <linux/tcp.h>
37 #include <net/busy_poll.h>
38 #include <net/ip6_checksum.h>
39 #include <net/page_pool.h>
44 #include "ipoib/ipoib.h"
45 #include "en_accel/ipsec_rxtx.h"
46 #include "en_accel/tls_rxtx.h"
47 #include "lib/clock.h"
50 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config)
52 return config->rx_filter == HWTSTAMP_FILTER_ALL;
55 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
58 u32 ci = mlx5_cqwq_ctr2ix(&cq->wq, cqcc);
60 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
63 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
64 struct mlx5e_cq *cq, u32 cqcc)
66 mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
67 cq->decmprs_left = be32_to_cpu(cq->title.byte_cnt);
68 cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
69 rq->stats->cqe_compress_blks++;
72 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
74 mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
78 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
80 struct mlx5_cqwq *wq = &cq->wq;
82 u8 op_own = mlx5_cqwq_get_ctr_wrap_cnt(wq, cqcc) & 1;
83 u32 ci = mlx5_cqwq_ctr2ix(wq, cqcc);
84 u32 wq_sz = mlx5_cqwq_get_size(wq);
85 u32 ci_top = min_t(u32, wq_sz, ci + n);
87 for (; ci < ci_top; ci++, n--) {
88 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
93 if (unlikely(ci == wq_sz)) {
95 for (ci = 0; ci < n; ci++) {
96 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
103 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
104 struct mlx5e_cq *cq, u32 cqcc)
106 cq->title.byte_cnt = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
107 cq->title.check_sum = cq->mini_arr[cq->mini_arr_idx].checksum;
108 cq->title.op_own &= 0xf0;
109 cq->title.op_own |= 0x01 & (cqcc >> cq->wq.fbc.log_sz);
110 cq->title.wqe_counter = cpu_to_be16(cq->decmprs_wqe_counter);
112 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
113 cq->decmprs_wqe_counter +=
114 mpwrq_get_cqe_consumed_strides(&cq->title);
116 cq->decmprs_wqe_counter =
117 mlx5_wq_cyc_ctr2ix(&rq->wqe.wq, cq->decmprs_wqe_counter + 1);
120 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
121 struct mlx5e_cq *cq, u32 cqcc)
123 mlx5e_decompress_cqe(rq, cq, cqcc);
124 cq->title.rss_hash_type = 0;
125 cq->title.rss_hash_result = 0;
128 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
130 int update_owner_only,
133 u32 cqcc = cq->wq.cc + update_owner_only;
137 cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
139 for (i = update_owner_only; i < cqe_count;
140 i++, cq->mini_arr_idx++, cqcc++) {
141 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
142 mlx5e_read_mini_arr_slot(cq, cqcc);
144 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
145 rq->handle_rx_cqe(rq, &cq->title);
147 mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
149 cq->decmprs_left -= cqe_count;
150 rq->stats->cqe_compress_pkts += cqe_count;
155 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
159 mlx5e_read_title_slot(rq, cq, cq->wq.cc);
160 mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
161 mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
162 rq->handle_rx_cqe(rq, &cq->title);
165 return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
168 static inline bool mlx5e_page_is_reserved(struct page *page)
170 return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id();
173 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
174 struct mlx5e_dma_info *dma_info)
176 struct mlx5e_page_cache *cache = &rq->page_cache;
177 u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
178 struct mlx5e_rq_stats *stats = rq->stats;
180 if (tail_next == cache->head) {
185 if (unlikely(mlx5e_page_is_reserved(dma_info->page))) {
186 stats->cache_waive++;
190 cache->page_cache[cache->tail] = *dma_info;
191 cache->tail = tail_next;
195 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
196 struct mlx5e_dma_info *dma_info)
198 struct mlx5e_page_cache *cache = &rq->page_cache;
199 struct mlx5e_rq_stats *stats = rq->stats;
201 if (unlikely(cache->head == cache->tail)) {
202 stats->cache_empty++;
206 if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
211 *dma_info = cache->page_cache[cache->head];
212 cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
213 stats->cache_reuse++;
215 dma_sync_single_for_device(rq->pdev, dma_info->addr,
221 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq,
222 struct mlx5e_dma_info *dma_info)
224 if (mlx5e_rx_cache_get(rq, dma_info))
227 dma_info->page = page_pool_dev_alloc_pages(rq->page_pool);
228 if (unlikely(!dma_info->page))
231 dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
232 PAGE_SIZE, rq->buff.map_dir);
233 if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
234 put_page(dma_info->page);
235 dma_info->page = NULL;
242 void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info)
244 dma_unmap_page(rq->pdev, dma_info->addr, PAGE_SIZE, rq->buff.map_dir);
247 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
250 if (likely(recycle)) {
251 if (mlx5e_rx_cache_put(rq, dma_info))
254 mlx5e_page_dma_unmap(rq, dma_info);
255 page_pool_recycle_direct(rq->page_pool, dma_info->page);
257 mlx5e_page_dma_unmap(rq, dma_info);
258 put_page(dma_info->page);
262 static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq,
263 struct mlx5e_wqe_frag_info *frag)
268 /* On first frag (offset == 0), replenish page (dma_info actually).
269 * Other frags that point to the same dma_info (with a different
270 * offset) should just use the new one without replenishing again
273 err = mlx5e_page_alloc_mapped(rq, frag->di);
278 static inline void mlx5e_put_rx_frag(struct mlx5e_rq *rq,
279 struct mlx5e_wqe_frag_info *frag,
282 if (frag->last_in_page)
283 mlx5e_page_release(rq, frag->di, recycle);
286 static inline struct mlx5e_wqe_frag_info *get_frag(struct mlx5e_rq *rq, u16 ix)
288 return &rq->wqe.frags[ix << rq->wqe.info.log_num_frags];
291 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe_cyc *wqe,
294 struct mlx5e_wqe_frag_info *frag = get_frag(rq, ix);
298 for (i = 0; i < rq->wqe.info.num_frags; i++, frag++) {
299 err = mlx5e_get_rx_frag(rq, frag);
303 wqe->data[i].addr = cpu_to_be64(frag->di->addr +
304 frag->offset + rq->buff.headroom);
311 mlx5e_put_rx_frag(rq, --frag, true);
316 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
317 struct mlx5e_wqe_frag_info *wi,
322 for (i = 0; i < rq->wqe.info.num_frags; i++, wi++)
323 mlx5e_put_rx_frag(rq, wi, recycle);
326 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
328 struct mlx5e_wqe_frag_info *wi = get_frag(rq, ix);
330 mlx5e_free_rx_wqe(rq, wi, false);
333 static int mlx5e_alloc_rx_wqes(struct mlx5e_rq *rq, u16 ix, u8 wqe_bulk)
335 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
339 for (i = 0; i < wqe_bulk; i++) {
340 struct mlx5e_rx_wqe_cyc *wqe = mlx5_wq_cyc_get_wqe(wq, ix + i);
342 err = mlx5e_alloc_rx_wqe(rq, wqe, ix + i);
351 mlx5e_dealloc_rx_wqe(rq, ix + i);
357 mlx5e_add_skb_frag(struct mlx5e_rq *rq, struct sk_buff *skb,
358 struct mlx5e_dma_info *di, u32 frag_offset, u32 len,
359 unsigned int truesize)
361 dma_sync_single_for_cpu(rq->pdev,
362 di->addr + frag_offset,
363 len, DMA_FROM_DEVICE);
364 page_ref_inc(di->page);
365 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
366 di->page, frag_offset, len, truesize);
370 mlx5e_copy_skb_header(struct device *pdev, struct sk_buff *skb,
371 struct mlx5e_dma_info *dma_info,
372 int offset_from, int offset_to, u32 headlen)
374 const void *from = page_address(dma_info->page) + offset_from;
375 /* Aligning len to sizeof(long) optimizes memcpy performance */
376 unsigned int len = ALIGN(headlen, sizeof(long));
378 dma_sync_single_for_cpu(pdev, dma_info->addr + offset_from, len,
380 skb_copy_to_linear_data_offset(skb, offset_to, from, len);
384 mlx5e_copy_skb_header_mpwqe(struct device *pdev,
386 struct mlx5e_dma_info *dma_info,
387 u32 offset, u32 headlen)
389 u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
391 mlx5e_copy_skb_header(pdev, skb, dma_info, offset, 0, headlen_pg);
393 if (unlikely(offset + headlen > PAGE_SIZE)) {
395 mlx5e_copy_skb_header(pdev, skb, dma_info, 0, headlen_pg,
396 headlen - headlen_pg);
401 mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, bool recycle)
403 const bool no_xdp_xmit =
404 bitmap_empty(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
405 struct mlx5e_dma_info *dma_info = wi->umr.dma_info;
408 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++)
409 if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap))
410 mlx5e_page_release(rq, &dma_info[i], recycle);
413 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)
415 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
416 struct mlx5e_rx_wqe_ll *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
418 rq->mpwqe.umr_in_progress = false;
420 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
422 /* ensure wqes are visible to device before updating doorbell record */
425 mlx5_wq_ll_update_db_record(wq);
428 static inline u16 mlx5e_icosq_wrap_cnt(struct mlx5e_icosq *sq)
430 return sq->pc >> MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
433 static inline void mlx5e_fill_icosq_frag_edge(struct mlx5e_icosq *sq,
434 struct mlx5_wq_cyc *wq,
437 struct mlx5e_sq_wqe_info *edge_wi, *wi = &sq->db.ico_wqe[pi];
439 edge_wi = wi + nnops;
441 /* fill sq frag edge with nops to avoid wqe wrapping two pages */
442 for (; wi < edge_wi; wi++) {
443 wi->opcode = MLX5_OPCODE_NOP;
444 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
448 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
450 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
451 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
452 struct mlx5e_icosq *sq = &rq->channel->icosq;
453 struct mlx5_wq_cyc *wq = &sq->wq;
454 struct mlx5e_umr_wqe *umr_wqe;
455 u16 xlt_offset = ix << (MLX5E_LOG_ALIGNED_MPWQE_PPW - 1);
456 u16 pi, contig_wqebbs_room;
460 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
461 contig_wqebbs_room = mlx5_wq_cyc_get_contig_wqebbs(wq, pi);
462 if (unlikely(contig_wqebbs_room < MLX5E_UMR_WQEBBS)) {
463 mlx5e_fill_icosq_frag_edge(sq, wq, pi, contig_wqebbs_room);
464 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
467 umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi);
468 if (unlikely(mlx5e_icosq_wrap_cnt(sq) < 2))
469 memcpy(umr_wqe, &rq->mpwqe.umr_wqe,
470 offsetof(struct mlx5e_umr_wqe, inline_mtts));
472 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
473 err = mlx5e_page_alloc_mapped(rq, dma_info);
476 umr_wqe->inline_mtts[i].ptag = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
479 bitmap_zero(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
480 wi->consumed_strides = 0;
482 rq->mpwqe.umr_in_progress = true;
484 umr_wqe->ctrl.opmod_idx_opcode =
485 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
487 umr_wqe->uctrl.xlt_offset = cpu_to_be16(xlt_offset);
489 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
490 sq->pc += MLX5E_UMR_WQEBBS;
491 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &umr_wqe->ctrl);
498 mlx5e_page_release(rq, dma_info, true);
500 rq->stats->buff_alloc_err++;
505 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
507 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
508 /* Don't recycle, this function is called on rq/netdev close */
509 mlx5e_free_rx_mpwqe(rq, wi, false);
512 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
514 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
518 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
521 wqe_bulk = rq->wqe.info.wqe_bulk;
523 if (mlx5_wq_cyc_missing(wq) < wqe_bulk)
527 u16 head = mlx5_wq_cyc_get_head(wq);
529 err = mlx5e_alloc_rx_wqes(rq, head, wqe_bulk);
531 rq->stats->buff_alloc_err++;
535 mlx5_wq_cyc_push_n(wq, wqe_bulk);
536 } while (mlx5_wq_cyc_missing(wq) >= wqe_bulk);
538 /* ensure wqes are visible to device before updating doorbell record */
541 mlx5_wq_cyc_update_db_record(wq);
546 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq,
547 struct mlx5e_icosq *sq,
549 struct mlx5_cqe64 *cqe)
551 struct mlx5_wq_cyc *wq = &sq->wq;
552 u16 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
553 struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci];
555 mlx5_cqwq_pop(&cq->wq);
557 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) {
558 netdev_WARN_ONCE(cq->channel->netdev,
559 "Bad OP in ICOSQ CQE: 0x%x\n", cqe->op_own);
563 if (likely(icowi->opcode == MLX5_OPCODE_UMR)) {
564 mlx5e_post_rx_mpwqe(rq);
568 if (unlikely(icowi->opcode != MLX5_OPCODE_NOP))
569 netdev_WARN_ONCE(cq->channel->netdev,
570 "Bad OPCODE in ICOSQ WQE info: 0x%x\n", icowi->opcode);
573 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq)
575 struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
576 struct mlx5_cqe64 *cqe;
578 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
581 cqe = mlx5_cqwq_get_cqe(&cq->wq);
585 /* by design, there's only a single cqe */
586 mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe);
588 mlx5_cqwq_update_db_record(&cq->wq);
591 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
593 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
595 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
598 mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq);
600 if (mlx5_wq_ll_is_full(wq))
603 if (!rq->mpwqe.umr_in_progress)
604 mlx5e_alloc_rx_mpwqe(rq, wq->head);
606 rq->stats->congst_umr += mlx5_wq_ll_missing(wq) > 2;
611 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp)
613 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
614 u8 tcp_ack = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
615 (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
618 tcp->psh = get_cqe_lro_tcppsh(cqe);
622 tcp->ack_seq = cqe->lro_ack_seq_num;
623 tcp->window = cqe->lro_tcp_win;
627 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
630 struct ethhdr *eth = (struct ethhdr *)(skb->data);
632 int network_depth = 0;
638 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
640 tot_len = cqe_bcnt - network_depth;
641 ip_p = skb->data + network_depth;
643 if (proto == htons(ETH_P_IP)) {
644 struct iphdr *ipv4 = ip_p;
646 tcp = ip_p + sizeof(struct iphdr);
647 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
649 ipv4->ttl = cqe->lro_min_ttl;
650 ipv4->tot_len = cpu_to_be16(tot_len);
652 ipv4->check = ip_fast_csum((unsigned char *)ipv4,
655 mlx5e_lro_update_tcp_hdr(cqe, tcp);
656 check = csum_partial(tcp, tcp->doff * 4,
657 csum_unfold((__force __sum16)cqe->check_sum));
658 /* Almost done, don't forget the pseudo header */
659 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr,
660 tot_len - sizeof(struct iphdr),
663 u16 payload_len = tot_len - sizeof(struct ipv6hdr);
664 struct ipv6hdr *ipv6 = ip_p;
666 tcp = ip_p + sizeof(struct ipv6hdr);
667 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
669 ipv6->hop_limit = cqe->lro_min_ttl;
670 ipv6->payload_len = cpu_to_be16(payload_len);
672 mlx5e_lro_update_tcp_hdr(cqe, tcp);
673 check = csum_partial(tcp, tcp->doff * 4,
674 csum_unfold((__force __sum16)cqe->check_sum));
675 /* Almost done, don't forget the pseudo header */
676 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len,
681 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
684 u8 cht = cqe->rss_hash_type;
685 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
686 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
688 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
691 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth)
693 __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto;
695 ethertype = __vlan_get_protocol(skb, ethertype, network_depth);
696 return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6));
699 static u32 mlx5e_get_fcs(const struct sk_buff *skb)
701 const void *fcs_bytes;
704 fcs_bytes = skb_header_pointer(skb, skb->len - ETH_FCS_LEN,
705 ETH_FCS_LEN, &_fcs_bytes);
707 return __get_unaligned_cpu32(fcs_bytes);
710 #define short_frame(size) ((size) <= ETH_ZLEN + ETH_FCS_LEN)
712 static inline void mlx5e_handle_csum(struct net_device *netdev,
713 struct mlx5_cqe64 *cqe,
718 struct mlx5e_rq_stats *stats = rq->stats;
719 int network_depth = 0;
721 if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
725 skb->ip_summed = CHECKSUM_UNNECESSARY;
726 stats->csum_unnecessary++;
730 /* CQE csum doesn't cover padding octets in short ethernet
731 * frames. And the pad field is appended prior to calculating
732 * and appending the FCS field.
734 * Detecting these padded frames requires to verify and parse
735 * IP headers, so we simply force all those small frames to be
736 * CHECKSUM_UNNECESSARY even if they are not padded.
738 if (short_frame(skb->len))
739 goto csum_unnecessary;
741 if (likely(is_last_ethertype_ip(skb, &network_depth))) {
742 skb->ip_summed = CHECKSUM_COMPLETE;
743 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
744 if (network_depth > ETH_HLEN)
745 /* CQE csum is calculated from the IP header and does
746 * not cover VLAN headers (if present). This will add
747 * the checksum manually.
749 skb->csum = csum_partial(skb->data + ETH_HLEN,
750 network_depth - ETH_HLEN,
752 if (unlikely(netdev->features & NETIF_F_RXFCS))
753 skb->csum = csum_block_add(skb->csum,
754 (__force __wsum)mlx5e_get_fcs(skb),
755 skb->len - ETH_FCS_LEN);
756 stats->csum_complete++;
761 if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
762 (cqe->hds_ip_ext & CQE_L4_OK))) {
763 skb->ip_summed = CHECKSUM_UNNECESSARY;
764 if (cqe_is_tunneled(cqe)) {
766 skb->encapsulation = 1;
767 stats->csum_unnecessary_inner++;
770 stats->csum_unnecessary++;
774 skb->ip_summed = CHECKSUM_NONE;
778 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
783 u8 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
784 struct mlx5e_rq_stats *stats = rq->stats;
785 struct net_device *netdev = rq->netdev;
787 skb->mac_len = ETH_HLEN;
789 #ifdef CONFIG_MLX5_EN_TLS
790 mlx5e_tls_handle_rx_skb(netdev, skb, &cqe_bcnt);
793 if (lro_num_seg > 1) {
794 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
795 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
796 /* Subtract one since we already counted this as one
797 * "regular" packet in mlx5e_complete_rx_cqe()
799 stats->packets += lro_num_seg - 1;
800 stats->lro_packets++;
801 stats->lro_bytes += cqe_bcnt;
804 if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp)))
805 skb_hwtstamps(skb)->hwtstamp =
806 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
808 skb_record_rx_queue(skb, rq->ix);
810 if (likely(netdev->features & NETIF_F_RXHASH))
811 mlx5e_skb_set_hash(cqe, skb);
813 if (cqe_has_vlan(cqe)) {
814 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
815 be16_to_cpu(cqe->vlan_info));
816 stats->removed_vlan_packets++;
819 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
821 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
822 skb->protocol = eth_type_trans(skb, netdev);
825 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
826 struct mlx5_cqe64 *cqe,
830 struct mlx5e_rq_stats *stats = rq->stats;
833 stats->bytes += cqe_bcnt;
834 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
838 struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va,
839 u32 frag_size, u16 headroom,
842 struct sk_buff *skb = build_skb(va, frag_size);
844 if (unlikely(!skb)) {
845 rq->stats->buff_alloc_err++;
849 skb_reserve(skb, headroom);
850 skb_put(skb, cqe_bcnt);
856 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
857 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
859 struct mlx5e_dma_info *di = wi->di;
860 u16 rx_headroom = rq->buff.headroom;
866 va = page_address(di->page) + wi->offset;
867 data = va + rx_headroom;
868 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
870 dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset,
871 frag_size, DMA_FROM_DEVICE);
872 prefetchw(va); /* xdp_frame data area */
875 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
876 rq->stats->wqe_err++;
881 consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt);
884 return NULL; /* page/packet was consumed by XDP */
886 skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt);
890 /* queue up for recycling/reuse */
891 page_ref_inc(di->page);
897 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
898 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
900 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
901 struct mlx5e_wqe_frag_info *head_wi = wi;
902 u16 headlen = min_t(u32, MLX5E_RX_MAX_HEAD, cqe_bcnt);
903 u16 frag_headlen = headlen;
904 u16 byte_cnt = cqe_bcnt - headlen;
907 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
908 rq->stats->wqe_err++;
912 /* XDP is not supported in this configuration, as incoming packets
913 * might spread among multiple pages.
915 skb = napi_alloc_skb(rq->cq.napi,
916 ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
917 if (unlikely(!skb)) {
918 rq->stats->buff_alloc_err++;
922 prefetchw(skb->data);
925 u16 frag_consumed_bytes =
926 min_t(u16, frag_info->frag_size - frag_headlen, byte_cnt);
928 mlx5e_add_skb_frag(rq, skb, wi->di, wi->offset + frag_headlen,
929 frag_consumed_bytes, frag_info->frag_stride);
930 byte_cnt -= frag_consumed_bytes;
937 mlx5e_copy_skb_header(rq->pdev, skb, head_wi->di, head_wi->offset,
939 /* skb linear part was allocated with headlen and aligned to long */
940 skb->tail += headlen;
946 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
948 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
949 struct mlx5e_wqe_frag_info *wi;
954 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
955 wi = get_frag(rq, ci);
956 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
958 skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
960 /* probably for XDP */
961 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
962 /* do not return page to cache,
963 * it will be returned on XDP_TX completion.
970 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
971 napi_gro_receive(rq->cq.napi, skb);
974 mlx5e_free_rx_wqe(rq, wi, true);
979 #ifdef CONFIG_MLX5_ESWITCH
980 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
982 struct net_device *netdev = rq->netdev;
983 struct mlx5e_priv *priv = netdev_priv(netdev);
984 struct mlx5e_rep_priv *rpriv = priv->ppriv;
985 struct mlx5_eswitch_rep *rep = rpriv->rep;
986 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
987 struct mlx5e_wqe_frag_info *wi;
992 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
993 wi = get_frag(rq, ci);
994 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
996 skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
998 /* probably for XDP */
999 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1000 /* do not return page to cache,
1001 * it will be returned on XDP_TX completion.
1008 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1010 if (rep->vlan && skb_vlan_tag_present(skb))
1013 napi_gro_receive(rq->cq.napi, skb);
1016 mlx5e_free_rx_wqe(rq, wi, true);
1018 mlx5_wq_cyc_pop(wq);
1023 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1024 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1026 u16 headlen = min_t(u16, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1027 struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1028 u32 frag_offset = head_offset + headlen;
1029 u32 byte_cnt = cqe_bcnt - headlen;
1030 struct mlx5e_dma_info *head_di = di;
1031 struct sk_buff *skb;
1033 skb = napi_alloc_skb(rq->cq.napi,
1034 ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1035 if (unlikely(!skb)) {
1036 rq->stats->buff_alloc_err++;
1040 prefetchw(skb->data);
1042 if (unlikely(frag_offset >= PAGE_SIZE)) {
1044 frag_offset -= PAGE_SIZE;
1048 u32 pg_consumed_bytes =
1049 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
1050 unsigned int truesize =
1051 ALIGN(pg_consumed_bytes, BIT(rq->mpwqe.log_stride_sz));
1053 mlx5e_add_skb_frag(rq, skb, di, frag_offset,
1054 pg_consumed_bytes, truesize);
1055 byte_cnt -= pg_consumed_bytes;
1060 mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, head_di,
1061 head_offset, headlen);
1062 /* skb linear part was allocated with headlen and aligned to long */
1063 skb->tail += headlen;
1064 skb->len += headlen;
1070 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1071 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1073 struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1074 u16 rx_headroom = rq->buff.headroom;
1075 u32 cqe_bcnt32 = cqe_bcnt;
1076 struct sk_buff *skb;
1081 /* Check packet size. Note LRO doesn't use linear SKB */
1082 if (unlikely(cqe_bcnt > rq->hw_mtu)) {
1083 rq->stats->oversize_pkts_sw_drop++;
1087 va = page_address(di->page) + head_offset;
1088 data = va + rx_headroom;
1089 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32);
1091 dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset,
1092 frag_size, DMA_FROM_DEVICE);
1093 prefetchw(va); /* xdp_frame data area */
1097 consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt32);
1100 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags))
1101 __set_bit(page_idx, wi->xdp_xmit_bitmap); /* non-atomic */
1102 return NULL; /* page/packet was consumed by XDP */
1105 skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt32);
1109 /* queue up for recycling/reuse */
1110 page_ref_inc(di->page);
1115 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1117 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe);
1118 u16 wqe_id = be16_to_cpu(cqe->wqe_id);
1119 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1120 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe);
1121 u32 wqe_offset = stride_ix << rq->mpwqe.log_stride_sz;
1122 u32 head_offset = wqe_offset & (PAGE_SIZE - 1);
1123 u32 page_idx = wqe_offset >> PAGE_SHIFT;
1124 struct mlx5e_rx_wqe_ll *wqe;
1125 struct mlx5_wq_ll *wq;
1126 struct sk_buff *skb;
1129 wi->consumed_strides += cstrides;
1131 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1132 rq->stats->wqe_err++;
1136 if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1137 struct mlx5e_rq_stats *stats = rq->stats;
1139 stats->mpwqe_filler_cqes++;
1140 stats->mpwqe_filler_strides += cstrides;
1144 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1146 skb = rq->mpwqe.skb_from_cqe_mpwrq(rq, wi, cqe_bcnt, head_offset,
1151 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1152 napi_gro_receive(rq->cq.napi, skb);
1155 if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1159 wqe = mlx5_wq_ll_get_wqe(wq, wqe_id);
1160 mlx5e_free_rx_mpwqe(rq, wi, true);
1161 mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1164 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1166 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1167 struct mlx5e_xdpsq *xdpsq = &rq->xdpsq;
1168 struct mlx5_cqe64 *cqe;
1171 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
1174 if (cq->decmprs_left)
1175 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
1177 cqe = mlx5_cqwq_get_cqe(&cq->wq);
1179 if (unlikely(work_done))
1185 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1187 mlx5e_decompress_cqes_start(rq, cq,
1188 budget - work_done);
1192 mlx5_cqwq_pop(&cq->wq);
1194 rq->handle_rx_cqe(rq, cqe);
1195 } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1198 if (xdpsq->doorbell) {
1199 mlx5e_xmit_xdp_doorbell(xdpsq);
1200 xdpsq->doorbell = false;
1203 if (xdpsq->redirect_flush) {
1205 xdpsq->redirect_flush = false;
1208 mlx5_cqwq_update_db_record(&cq->wq);
1210 /* ensure cq space is freed before enabling more cqes */
1216 #ifdef CONFIG_MLX5_CORE_IPOIB
1218 #define MLX5_IB_GRH_DGID_OFFSET 24
1219 #define MLX5_GID_SIZE 16
1221 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1222 struct mlx5_cqe64 *cqe,
1224 struct sk_buff *skb)
1226 struct mlx5e_rq_stats *stats = rq->stats;
1227 struct hwtstamp_config *tstamp;
1228 struct net_device *netdev;
1229 struct mlx5e_priv *priv;
1230 char *pseudo_header;
1235 qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff;
1236 netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn);
1238 /* No mapping present, cannot process SKB. This might happen if a child
1239 * interface is going down while having unprocessed CQEs on parent RQ
1241 if (unlikely(!netdev)) {
1242 /* TODO: add drop counters support */
1244 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn);
1248 priv = mlx5i_epriv(netdev);
1249 tstamp = &priv->tstamp;
1251 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
1252 dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1253 if ((!g) || dgid[0] != 0xff)
1254 skb->pkt_type = PACKET_HOST;
1255 else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1256 skb->pkt_type = PACKET_BROADCAST;
1258 skb->pkt_type = PACKET_MULTICAST;
1260 /* TODO: IB/ipoib: Allow mcast packets from other VFs
1261 * 68996a6e760e5c74654723eeb57bf65628ae87f4
1264 skb_pull(skb, MLX5_IB_GRH_BYTES);
1266 skb->protocol = *((__be16 *)(skb->data));
1268 skb->ip_summed = CHECKSUM_COMPLETE;
1269 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1271 if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1272 skb_hwtstamps(skb)->hwtstamp =
1273 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1275 skb_record_rx_queue(skb, rq->ix);
1277 if (likely(netdev->features & NETIF_F_RXHASH))
1278 mlx5e_skb_set_hash(cqe, skb);
1280 /* 20 bytes of ipoib header and 4 for encap existing */
1281 pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1282 memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1283 skb_reset_mac_header(skb);
1284 skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1288 stats->csum_complete++;
1290 stats->bytes += cqe_bcnt;
1293 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1295 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1296 struct mlx5e_wqe_frag_info *wi;
1297 struct sk_buff *skb;
1301 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1302 wi = get_frag(rq, ci);
1303 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1305 skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1309 mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1310 if (unlikely(!skb->dev)) {
1311 dev_kfree_skb_any(skb);
1314 napi_gro_receive(rq->cq.napi, skb);
1317 mlx5e_free_rx_wqe(rq, wi, true);
1318 mlx5_wq_cyc_pop(wq);
1321 #endif /* CONFIG_MLX5_CORE_IPOIB */
1323 #ifdef CONFIG_MLX5_EN_IPSEC
1325 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1327 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1328 struct mlx5e_wqe_frag_info *wi;
1329 struct sk_buff *skb;
1333 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1334 wi = get_frag(rq, ci);
1335 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1337 skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1338 if (unlikely(!skb)) {
1339 /* a DROP, save the page-reuse checks */
1340 mlx5e_free_rx_wqe(rq, wi, true);
1343 skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb, &cqe_bcnt);
1344 if (unlikely(!skb)) {
1345 mlx5e_free_rx_wqe(rq, wi, true);
1349 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1350 napi_gro_receive(rq->cq.napi, skb);
1352 mlx5e_free_rx_wqe(rq, wi, true);
1354 mlx5_wq_cyc_pop(wq);
1357 #endif /* CONFIG_MLX5_EN_IPSEC */