2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/prefetch.h>
35 #include <linux/ipv6.h>
36 #include <linux/tcp.h>
37 #include <net/busy_poll.h>
38 #include <net/ip6_checksum.h>
39 #include <net/page_pool.h>
40 #include <net/inet_ecn.h>
45 #include "ipoib/ipoib.h"
46 #include "en_accel/ipsec_rxtx.h"
47 #include "en_accel/tls_rxtx.h"
48 #include "lib/clock.h"
51 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config)
53 return config->rx_filter == HWTSTAMP_FILTER_ALL;
56 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
59 u32 ci = mlx5_cqwq_ctr2ix(&cq->wq, cqcc);
61 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
64 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
65 struct mlx5e_cq *cq, u32 cqcc)
67 mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
68 cq->decmprs_left = be32_to_cpu(cq->title.byte_cnt);
69 cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
70 rq->stats->cqe_compress_blks++;
73 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
75 mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
79 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
81 struct mlx5_cqwq *wq = &cq->wq;
83 u8 op_own = mlx5_cqwq_get_ctr_wrap_cnt(wq, cqcc) & 1;
84 u32 ci = mlx5_cqwq_ctr2ix(wq, cqcc);
85 u32 wq_sz = mlx5_cqwq_get_size(wq);
86 u32 ci_top = min_t(u32, wq_sz, ci + n);
88 for (; ci < ci_top; ci++, n--) {
89 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
94 if (unlikely(ci == wq_sz)) {
96 for (ci = 0; ci < n; ci++) {
97 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
104 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
105 struct mlx5e_cq *cq, u32 cqcc)
107 cq->title.byte_cnt = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
108 cq->title.check_sum = cq->mini_arr[cq->mini_arr_idx].checksum;
109 cq->title.op_own &= 0xf0;
110 cq->title.op_own |= 0x01 & (cqcc >> cq->wq.fbc.log_sz);
111 cq->title.wqe_counter = cpu_to_be16(cq->decmprs_wqe_counter);
113 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
114 cq->decmprs_wqe_counter +=
115 mpwrq_get_cqe_consumed_strides(&cq->title);
117 cq->decmprs_wqe_counter =
118 mlx5_wq_cyc_ctr2ix(&rq->wqe.wq, cq->decmprs_wqe_counter + 1);
121 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
122 struct mlx5e_cq *cq, u32 cqcc)
124 mlx5e_decompress_cqe(rq, cq, cqcc);
125 cq->title.rss_hash_type = 0;
126 cq->title.rss_hash_result = 0;
129 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
131 int update_owner_only,
134 u32 cqcc = cq->wq.cc + update_owner_only;
138 cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
140 for (i = update_owner_only; i < cqe_count;
141 i++, cq->mini_arr_idx++, cqcc++) {
142 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
143 mlx5e_read_mini_arr_slot(cq, cqcc);
145 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
146 rq->handle_rx_cqe(rq, &cq->title);
148 mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
150 cq->decmprs_left -= cqe_count;
151 rq->stats->cqe_compress_pkts += cqe_count;
156 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
160 mlx5e_read_title_slot(rq, cq, cq->wq.cc);
161 mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
162 mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
163 rq->handle_rx_cqe(rq, &cq->title);
166 return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
169 static inline bool mlx5e_page_is_reserved(struct page *page)
171 return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id();
174 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
175 struct mlx5e_dma_info *dma_info)
177 struct mlx5e_page_cache *cache = &rq->page_cache;
178 u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
179 struct mlx5e_rq_stats *stats = rq->stats;
181 if (tail_next == cache->head) {
186 if (unlikely(mlx5e_page_is_reserved(dma_info->page))) {
187 stats->cache_waive++;
191 cache->page_cache[cache->tail] = *dma_info;
192 cache->tail = tail_next;
196 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
197 struct mlx5e_dma_info *dma_info)
199 struct mlx5e_page_cache *cache = &rq->page_cache;
200 struct mlx5e_rq_stats *stats = rq->stats;
202 if (unlikely(cache->head == cache->tail)) {
203 stats->cache_empty++;
207 if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
212 *dma_info = cache->page_cache[cache->head];
213 cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
214 stats->cache_reuse++;
216 dma_sync_single_for_device(rq->pdev, dma_info->addr,
222 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq,
223 struct mlx5e_dma_info *dma_info)
225 if (mlx5e_rx_cache_get(rq, dma_info))
228 dma_info->page = page_pool_dev_alloc_pages(rq->page_pool);
229 if (unlikely(!dma_info->page))
232 dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
233 PAGE_SIZE, rq->buff.map_dir);
234 if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
235 put_page(dma_info->page);
236 dma_info->page = NULL;
243 void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info)
245 dma_unmap_page(rq->pdev, dma_info->addr, PAGE_SIZE, rq->buff.map_dir);
248 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
251 if (likely(recycle)) {
252 if (mlx5e_rx_cache_put(rq, dma_info))
255 mlx5e_page_dma_unmap(rq, dma_info);
256 page_pool_recycle_direct(rq->page_pool, dma_info->page);
258 mlx5e_page_dma_unmap(rq, dma_info);
259 put_page(dma_info->page);
263 static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq,
264 struct mlx5e_wqe_frag_info *frag)
269 /* On first frag (offset == 0), replenish page (dma_info actually).
270 * Other frags that point to the same dma_info (with a different
271 * offset) should just use the new one without replenishing again
274 err = mlx5e_page_alloc_mapped(rq, frag->di);
279 static inline void mlx5e_put_rx_frag(struct mlx5e_rq *rq,
280 struct mlx5e_wqe_frag_info *frag,
283 if (frag->last_in_page)
284 mlx5e_page_release(rq, frag->di, recycle);
287 static inline struct mlx5e_wqe_frag_info *get_frag(struct mlx5e_rq *rq, u16 ix)
289 return &rq->wqe.frags[ix << rq->wqe.info.log_num_frags];
292 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe_cyc *wqe,
295 struct mlx5e_wqe_frag_info *frag = get_frag(rq, ix);
299 for (i = 0; i < rq->wqe.info.num_frags; i++, frag++) {
300 err = mlx5e_get_rx_frag(rq, frag);
304 wqe->data[i].addr = cpu_to_be64(frag->di->addr +
305 frag->offset + rq->buff.headroom);
312 mlx5e_put_rx_frag(rq, --frag, true);
317 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
318 struct mlx5e_wqe_frag_info *wi,
323 for (i = 0; i < rq->wqe.info.num_frags; i++, wi++)
324 mlx5e_put_rx_frag(rq, wi, recycle);
327 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
329 struct mlx5e_wqe_frag_info *wi = get_frag(rq, ix);
331 mlx5e_free_rx_wqe(rq, wi, false);
334 static int mlx5e_alloc_rx_wqes(struct mlx5e_rq *rq, u16 ix, u8 wqe_bulk)
336 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
340 for (i = 0; i < wqe_bulk; i++) {
341 struct mlx5e_rx_wqe_cyc *wqe = mlx5_wq_cyc_get_wqe(wq, ix + i);
343 err = mlx5e_alloc_rx_wqe(rq, wqe, ix + i);
352 mlx5e_dealloc_rx_wqe(rq, ix + i);
358 mlx5e_add_skb_frag(struct mlx5e_rq *rq, struct sk_buff *skb,
359 struct mlx5e_dma_info *di, u32 frag_offset, u32 len,
360 unsigned int truesize)
362 dma_sync_single_for_cpu(rq->pdev,
363 di->addr + frag_offset,
364 len, DMA_FROM_DEVICE);
365 page_ref_inc(di->page);
366 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
367 di->page, frag_offset, len, truesize);
371 mlx5e_copy_skb_header(struct device *pdev, struct sk_buff *skb,
372 struct mlx5e_dma_info *dma_info,
373 int offset_from, int offset_to, u32 headlen)
375 const void *from = page_address(dma_info->page) + offset_from;
376 /* Aligning len to sizeof(long) optimizes memcpy performance */
377 unsigned int len = ALIGN(headlen, sizeof(long));
379 dma_sync_single_for_cpu(pdev, dma_info->addr + offset_from, len,
381 skb_copy_to_linear_data_offset(skb, offset_to, from, len);
385 mlx5e_copy_skb_header_mpwqe(struct device *pdev,
387 struct mlx5e_dma_info *dma_info,
388 u32 offset, u32 headlen)
390 u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
392 mlx5e_copy_skb_header(pdev, skb, dma_info, offset, 0, headlen_pg);
394 if (unlikely(offset + headlen > PAGE_SIZE)) {
396 mlx5e_copy_skb_header(pdev, skb, dma_info, 0, headlen_pg,
397 headlen - headlen_pg);
402 mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, bool recycle)
404 const bool no_xdp_xmit =
405 bitmap_empty(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
406 struct mlx5e_dma_info *dma_info = wi->umr.dma_info;
409 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++)
410 if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap))
411 mlx5e_page_release(rq, &dma_info[i], recycle);
414 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)
416 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
417 struct mlx5e_rx_wqe_ll *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
419 rq->mpwqe.umr_in_progress = false;
421 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
423 /* ensure wqes are visible to device before updating doorbell record */
426 mlx5_wq_ll_update_db_record(wq);
429 static inline u16 mlx5e_icosq_wrap_cnt(struct mlx5e_icosq *sq)
431 return sq->pc >> MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
434 static inline void mlx5e_fill_icosq_frag_edge(struct mlx5e_icosq *sq,
435 struct mlx5_wq_cyc *wq,
438 struct mlx5e_sq_wqe_info *edge_wi, *wi = &sq->db.ico_wqe[pi];
440 edge_wi = wi + nnops;
442 /* fill sq frag edge with nops to avoid wqe wrapping two pages */
443 for (; wi < edge_wi; wi++) {
444 wi->opcode = MLX5_OPCODE_NOP;
445 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
449 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
451 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
452 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
453 struct mlx5e_icosq *sq = &rq->channel->icosq;
454 struct mlx5_wq_cyc *wq = &sq->wq;
455 struct mlx5e_umr_wqe *umr_wqe;
456 u16 xlt_offset = ix << (MLX5E_LOG_ALIGNED_MPWQE_PPW - 1);
457 u16 pi, contig_wqebbs_room;
461 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
462 contig_wqebbs_room = mlx5_wq_cyc_get_contig_wqebbs(wq, pi);
463 if (unlikely(contig_wqebbs_room < MLX5E_UMR_WQEBBS)) {
464 mlx5e_fill_icosq_frag_edge(sq, wq, pi, contig_wqebbs_room);
465 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
468 umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi);
469 if (unlikely(mlx5e_icosq_wrap_cnt(sq) < 2))
470 memcpy(umr_wqe, &rq->mpwqe.umr_wqe,
471 offsetof(struct mlx5e_umr_wqe, inline_mtts));
473 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
474 err = mlx5e_page_alloc_mapped(rq, dma_info);
477 umr_wqe->inline_mtts[i].ptag = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
480 bitmap_zero(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
481 wi->consumed_strides = 0;
483 rq->mpwqe.umr_in_progress = true;
485 umr_wqe->ctrl.opmod_idx_opcode =
486 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
488 umr_wqe->uctrl.xlt_offset = cpu_to_be16(xlt_offset);
490 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
491 sq->pc += MLX5E_UMR_WQEBBS;
492 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &umr_wqe->ctrl);
499 mlx5e_page_release(rq, dma_info, true);
501 rq->stats->buff_alloc_err++;
506 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
508 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
509 /* Don't recycle, this function is called on rq/netdev close */
510 mlx5e_free_rx_mpwqe(rq, wi, false);
513 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
515 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
519 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
522 wqe_bulk = rq->wqe.info.wqe_bulk;
524 if (mlx5_wq_cyc_missing(wq) < wqe_bulk)
528 u16 head = mlx5_wq_cyc_get_head(wq);
530 err = mlx5e_alloc_rx_wqes(rq, head, wqe_bulk);
532 rq->stats->buff_alloc_err++;
536 mlx5_wq_cyc_push_n(wq, wqe_bulk);
537 } while (mlx5_wq_cyc_missing(wq) >= wqe_bulk);
539 /* ensure wqes are visible to device before updating doorbell record */
542 mlx5_wq_cyc_update_db_record(wq);
547 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq,
548 struct mlx5e_icosq *sq,
550 struct mlx5_cqe64 *cqe)
552 struct mlx5_wq_cyc *wq = &sq->wq;
553 u16 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
554 struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci];
556 mlx5_cqwq_pop(&cq->wq);
558 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) {
559 netdev_WARN_ONCE(cq->channel->netdev,
560 "Bad OP in ICOSQ CQE: 0x%x\n", cqe->op_own);
564 if (likely(icowi->opcode == MLX5_OPCODE_UMR)) {
565 mlx5e_post_rx_mpwqe(rq);
569 if (unlikely(icowi->opcode != MLX5_OPCODE_NOP))
570 netdev_WARN_ONCE(cq->channel->netdev,
571 "Bad OPCODE in ICOSQ WQE info: 0x%x\n", icowi->opcode);
574 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq)
576 struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
577 struct mlx5_cqe64 *cqe;
579 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
582 cqe = mlx5_cqwq_get_cqe(&cq->wq);
586 /* by design, there's only a single cqe */
587 mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe);
589 mlx5_cqwq_update_db_record(&cq->wq);
592 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
594 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
596 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
599 mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq);
601 if (mlx5_wq_ll_is_full(wq))
604 if (!rq->mpwqe.umr_in_progress)
605 mlx5e_alloc_rx_mpwqe(rq, wq->head);
607 rq->stats->congst_umr += mlx5_wq_ll_missing(wq) > 2;
612 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp)
614 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
615 u8 tcp_ack = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
616 (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
619 tcp->psh = get_cqe_lro_tcppsh(cqe);
623 tcp->ack_seq = cqe->lro_ack_seq_num;
624 tcp->window = cqe->lro_tcp_win;
628 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
631 struct ethhdr *eth = (struct ethhdr *)(skb->data);
633 int network_depth = 0;
639 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
641 tot_len = cqe_bcnt - network_depth;
642 ip_p = skb->data + network_depth;
644 if (proto == htons(ETH_P_IP)) {
645 struct iphdr *ipv4 = ip_p;
647 tcp = ip_p + sizeof(struct iphdr);
648 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
650 ipv4->ttl = cqe->lro_min_ttl;
651 ipv4->tot_len = cpu_to_be16(tot_len);
653 ipv4->check = ip_fast_csum((unsigned char *)ipv4,
656 mlx5e_lro_update_tcp_hdr(cqe, tcp);
657 check = csum_partial(tcp, tcp->doff * 4,
658 csum_unfold((__force __sum16)cqe->check_sum));
659 /* Almost done, don't forget the pseudo header */
660 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr,
661 tot_len - sizeof(struct iphdr),
664 u16 payload_len = tot_len - sizeof(struct ipv6hdr);
665 struct ipv6hdr *ipv6 = ip_p;
667 tcp = ip_p + sizeof(struct ipv6hdr);
668 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
670 ipv6->hop_limit = cqe->lro_min_ttl;
671 ipv6->payload_len = cpu_to_be16(payload_len);
673 mlx5e_lro_update_tcp_hdr(cqe, tcp);
674 check = csum_partial(tcp, tcp->doff * 4,
675 csum_unfold((__force __sum16)cqe->check_sum));
676 /* Almost done, don't forget the pseudo header */
677 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len,
682 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
685 u8 cht = cqe->rss_hash_type;
686 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
687 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
689 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
692 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth,
695 *proto = ((struct ethhdr *)skb->data)->h_proto;
696 *proto = __vlan_get_protocol(skb, *proto, network_depth);
697 return (*proto == htons(ETH_P_IP) || *proto == htons(ETH_P_IPV6));
700 static inline void mlx5e_enable_ecn(struct mlx5e_rq *rq, struct sk_buff *skb)
702 int network_depth = 0;
707 if (unlikely(!is_last_ethertype_ip(skb, &network_depth, &proto)))
710 ip = skb->data + network_depth;
711 rc = ((proto == htons(ETH_P_IP)) ? IP_ECN_set_ce((struct iphdr *)ip) :
712 IP6_ECN_set_ce(skb, (struct ipv6hdr *)ip));
714 rq->stats->ecn_mark += !!rc;
717 static u32 mlx5e_get_fcs(const struct sk_buff *skb)
719 const void *fcs_bytes;
722 fcs_bytes = skb_header_pointer(skb, skb->len - ETH_FCS_LEN,
723 ETH_FCS_LEN, &_fcs_bytes);
725 return __get_unaligned_cpu32(fcs_bytes);
728 static u8 get_ip_proto(struct sk_buff *skb, int network_depth, __be16 proto)
730 void *ip_p = skb->data + network_depth;
732 return (proto == htons(ETH_P_IP)) ? ((struct iphdr *)ip_p)->protocol :
733 ((struct ipv6hdr *)ip_p)->nexthdr;
736 #define short_frame(size) ((size) <= ETH_ZLEN + ETH_FCS_LEN)
738 static inline void mlx5e_handle_csum(struct net_device *netdev,
739 struct mlx5_cqe64 *cqe,
744 struct mlx5e_rq_stats *stats = rq->stats;
745 int network_depth = 0;
748 if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
752 skb->ip_summed = CHECKSUM_UNNECESSARY;
753 stats->csum_unnecessary++;
757 /* CQE csum doesn't cover padding octets in short ethernet
758 * frames. And the pad field is appended prior to calculating
759 * and appending the FCS field.
761 * Detecting these padded frames requires to verify and parse
762 * IP headers, so we simply force all those small frames to be
763 * CHECKSUM_UNNECESSARY even if they are not padded.
765 if (short_frame(skb->len))
766 goto csum_unnecessary;
768 if (likely(is_last_ethertype_ip(skb, &network_depth, &proto))) {
769 if (unlikely(get_ip_proto(skb, network_depth, proto) == IPPROTO_SCTP))
770 goto csum_unnecessary;
772 skb->ip_summed = CHECKSUM_COMPLETE;
773 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
774 if (network_depth > ETH_HLEN)
775 /* CQE csum is calculated from the IP header and does
776 * not cover VLAN headers (if present). This will add
777 * the checksum manually.
779 skb->csum = csum_partial(skb->data + ETH_HLEN,
780 network_depth - ETH_HLEN,
782 if (unlikely(netdev->features & NETIF_F_RXFCS))
783 skb->csum = csum_block_add(skb->csum,
784 (__force __wsum)mlx5e_get_fcs(skb),
785 skb->len - ETH_FCS_LEN);
786 stats->csum_complete++;
791 if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
792 (cqe->hds_ip_ext & CQE_L4_OK))) {
793 skb->ip_summed = CHECKSUM_UNNECESSARY;
794 if (cqe_is_tunneled(cqe)) {
796 skb->encapsulation = 1;
797 stats->csum_unnecessary_inner++;
800 stats->csum_unnecessary++;
804 skb->ip_summed = CHECKSUM_NONE;
808 #define MLX5E_CE_BIT_MASK 0x80
810 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
815 u8 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
816 struct mlx5e_rq_stats *stats = rq->stats;
817 struct net_device *netdev = rq->netdev;
819 skb->mac_len = ETH_HLEN;
821 #ifdef CONFIG_MLX5_EN_TLS
822 mlx5e_tls_handle_rx_skb(netdev, skb, &cqe_bcnt);
825 if (lro_num_seg > 1) {
826 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
827 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
828 /* Subtract one since we already counted this as one
829 * "regular" packet in mlx5e_complete_rx_cqe()
831 stats->packets += lro_num_seg - 1;
832 stats->lro_packets++;
833 stats->lro_bytes += cqe_bcnt;
836 if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp)))
837 skb_hwtstamps(skb)->hwtstamp =
838 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
840 skb_record_rx_queue(skb, rq->ix);
842 if (likely(netdev->features & NETIF_F_RXHASH))
843 mlx5e_skb_set_hash(cqe, skb);
845 if (cqe_has_vlan(cqe)) {
846 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
847 be16_to_cpu(cqe->vlan_info));
848 stats->removed_vlan_packets++;
851 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
853 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
854 /* checking CE bit in cqe - MSB in ml_path field */
855 if (unlikely(cqe->ml_path & MLX5E_CE_BIT_MASK))
856 mlx5e_enable_ecn(rq, skb);
858 skb->protocol = eth_type_trans(skb, netdev);
861 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
862 struct mlx5_cqe64 *cqe,
866 struct mlx5e_rq_stats *stats = rq->stats;
869 stats->bytes += cqe_bcnt;
870 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
874 struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va,
875 u32 frag_size, u16 headroom,
878 struct sk_buff *skb = build_skb(va, frag_size);
880 if (unlikely(!skb)) {
881 rq->stats->buff_alloc_err++;
885 skb_reserve(skb, headroom);
886 skb_put(skb, cqe_bcnt);
892 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
893 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
895 struct mlx5e_dma_info *di = wi->di;
896 u16 rx_headroom = rq->buff.headroom;
902 va = page_address(di->page) + wi->offset;
903 data = va + rx_headroom;
904 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
906 dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset,
907 frag_size, DMA_FROM_DEVICE);
908 prefetchw(va); /* xdp_frame data area */
911 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
912 rq->stats->wqe_err++;
917 consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt);
920 return NULL; /* page/packet was consumed by XDP */
922 skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt);
926 /* queue up for recycling/reuse */
927 page_ref_inc(di->page);
933 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
934 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
936 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
937 struct mlx5e_wqe_frag_info *head_wi = wi;
938 u16 headlen = min_t(u32, MLX5E_RX_MAX_HEAD, cqe_bcnt);
939 u16 frag_headlen = headlen;
940 u16 byte_cnt = cqe_bcnt - headlen;
943 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
944 rq->stats->wqe_err++;
948 /* XDP is not supported in this configuration, as incoming packets
949 * might spread among multiple pages.
951 skb = napi_alloc_skb(rq->cq.napi,
952 ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
953 if (unlikely(!skb)) {
954 rq->stats->buff_alloc_err++;
958 prefetchw(skb->data);
961 u16 frag_consumed_bytes =
962 min_t(u16, frag_info->frag_size - frag_headlen, byte_cnt);
964 mlx5e_add_skb_frag(rq, skb, wi->di, wi->offset + frag_headlen,
965 frag_consumed_bytes, frag_info->frag_stride);
966 byte_cnt -= frag_consumed_bytes;
973 mlx5e_copy_skb_header(rq->pdev, skb, head_wi->di, head_wi->offset,
975 /* skb linear part was allocated with headlen and aligned to long */
976 skb->tail += headlen;
982 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
984 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
985 struct mlx5e_wqe_frag_info *wi;
990 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
991 wi = get_frag(rq, ci);
992 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
994 skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
996 /* probably for XDP */
997 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
998 /* do not return page to cache,
999 * it will be returned on XDP_TX completion.
1006 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1007 napi_gro_receive(rq->cq.napi, skb);
1010 mlx5e_free_rx_wqe(rq, wi, true);
1012 mlx5_wq_cyc_pop(wq);
1015 #ifdef CONFIG_MLX5_ESWITCH
1016 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1018 struct net_device *netdev = rq->netdev;
1019 struct mlx5e_priv *priv = netdev_priv(netdev);
1020 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1021 struct mlx5_eswitch_rep *rep = rpriv->rep;
1022 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1023 struct mlx5e_wqe_frag_info *wi;
1024 struct sk_buff *skb;
1028 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1029 wi = get_frag(rq, ci);
1030 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1032 skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1034 /* probably for XDP */
1035 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1036 /* do not return page to cache,
1037 * it will be returned on XDP_TX completion.
1044 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1046 if (rep->vlan && skb_vlan_tag_present(skb))
1049 napi_gro_receive(rq->cq.napi, skb);
1052 mlx5e_free_rx_wqe(rq, wi, true);
1054 mlx5_wq_cyc_pop(wq);
1059 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1060 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1062 u16 headlen = min_t(u16, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1063 struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1064 u32 frag_offset = head_offset + headlen;
1065 u32 byte_cnt = cqe_bcnt - headlen;
1066 struct mlx5e_dma_info *head_di = di;
1067 struct sk_buff *skb;
1069 skb = napi_alloc_skb(rq->cq.napi,
1070 ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1071 if (unlikely(!skb)) {
1072 rq->stats->buff_alloc_err++;
1076 prefetchw(skb->data);
1078 if (unlikely(frag_offset >= PAGE_SIZE)) {
1080 frag_offset -= PAGE_SIZE;
1084 u32 pg_consumed_bytes =
1085 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
1086 unsigned int truesize =
1087 ALIGN(pg_consumed_bytes, BIT(rq->mpwqe.log_stride_sz));
1089 mlx5e_add_skb_frag(rq, skb, di, frag_offset,
1090 pg_consumed_bytes, truesize);
1091 byte_cnt -= pg_consumed_bytes;
1096 mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, head_di,
1097 head_offset, headlen);
1098 /* skb linear part was allocated with headlen and aligned to long */
1099 skb->tail += headlen;
1100 skb->len += headlen;
1106 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1107 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1109 struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1110 u16 rx_headroom = rq->buff.headroom;
1111 u32 cqe_bcnt32 = cqe_bcnt;
1112 struct sk_buff *skb;
1117 /* Check packet size. Note LRO doesn't use linear SKB */
1118 if (unlikely(cqe_bcnt > rq->hw_mtu)) {
1119 rq->stats->oversize_pkts_sw_drop++;
1123 va = page_address(di->page) + head_offset;
1124 data = va + rx_headroom;
1125 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32);
1127 dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset,
1128 frag_size, DMA_FROM_DEVICE);
1129 prefetchw(va); /* xdp_frame data area */
1133 consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt32);
1136 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags))
1137 __set_bit(page_idx, wi->xdp_xmit_bitmap); /* non-atomic */
1138 return NULL; /* page/packet was consumed by XDP */
1141 skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt32);
1145 /* queue up for recycling/reuse */
1146 page_ref_inc(di->page);
1151 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1153 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe);
1154 u16 wqe_id = be16_to_cpu(cqe->wqe_id);
1155 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1156 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe);
1157 u32 wqe_offset = stride_ix << rq->mpwqe.log_stride_sz;
1158 u32 head_offset = wqe_offset & (PAGE_SIZE - 1);
1159 u32 page_idx = wqe_offset >> PAGE_SHIFT;
1160 struct mlx5e_rx_wqe_ll *wqe;
1161 struct mlx5_wq_ll *wq;
1162 struct sk_buff *skb;
1165 wi->consumed_strides += cstrides;
1167 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1168 rq->stats->wqe_err++;
1172 if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1173 struct mlx5e_rq_stats *stats = rq->stats;
1175 stats->mpwqe_filler_cqes++;
1176 stats->mpwqe_filler_strides += cstrides;
1180 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1182 skb = rq->mpwqe.skb_from_cqe_mpwrq(rq, wi, cqe_bcnt, head_offset,
1187 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1188 napi_gro_receive(rq->cq.napi, skb);
1191 if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1195 wqe = mlx5_wq_ll_get_wqe(wq, wqe_id);
1196 mlx5e_free_rx_mpwqe(rq, wi, true);
1197 mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1200 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1202 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1203 struct mlx5e_xdpsq *xdpsq = &rq->xdpsq;
1204 struct mlx5_cqe64 *cqe;
1207 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
1210 if (cq->decmprs_left)
1211 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
1213 cqe = mlx5_cqwq_get_cqe(&cq->wq);
1215 if (unlikely(work_done))
1221 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1223 mlx5e_decompress_cqes_start(rq, cq,
1224 budget - work_done);
1228 mlx5_cqwq_pop(&cq->wq);
1230 rq->handle_rx_cqe(rq, cqe);
1231 } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1234 if (xdpsq->doorbell) {
1235 mlx5e_xmit_xdp_doorbell(xdpsq);
1236 xdpsq->doorbell = false;
1239 if (xdpsq->redirect_flush) {
1241 xdpsq->redirect_flush = false;
1244 mlx5_cqwq_update_db_record(&cq->wq);
1246 /* ensure cq space is freed before enabling more cqes */
1252 #ifdef CONFIG_MLX5_CORE_IPOIB
1254 #define MLX5_IB_GRH_DGID_OFFSET 24
1255 #define MLX5_GID_SIZE 16
1257 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1258 struct mlx5_cqe64 *cqe,
1260 struct sk_buff *skb)
1262 struct mlx5e_rq_stats *stats = rq->stats;
1263 struct hwtstamp_config *tstamp;
1264 struct net_device *netdev;
1265 struct mlx5e_priv *priv;
1266 char *pseudo_header;
1271 qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff;
1272 netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn);
1274 /* No mapping present, cannot process SKB. This might happen if a child
1275 * interface is going down while having unprocessed CQEs on parent RQ
1277 if (unlikely(!netdev)) {
1278 /* TODO: add drop counters support */
1280 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn);
1284 priv = mlx5i_epriv(netdev);
1285 tstamp = &priv->tstamp;
1287 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
1288 dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1289 if ((!g) || dgid[0] != 0xff)
1290 skb->pkt_type = PACKET_HOST;
1291 else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1292 skb->pkt_type = PACKET_BROADCAST;
1294 skb->pkt_type = PACKET_MULTICAST;
1296 /* TODO: IB/ipoib: Allow mcast packets from other VFs
1297 * 68996a6e760e5c74654723eeb57bf65628ae87f4
1300 skb_pull(skb, MLX5_IB_GRH_BYTES);
1302 skb->protocol = *((__be16 *)(skb->data));
1304 skb->ip_summed = CHECKSUM_COMPLETE;
1305 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1307 if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1308 skb_hwtstamps(skb)->hwtstamp =
1309 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1311 skb_record_rx_queue(skb, rq->ix);
1313 if (likely(netdev->features & NETIF_F_RXHASH))
1314 mlx5e_skb_set_hash(cqe, skb);
1316 /* 20 bytes of ipoib header and 4 for encap existing */
1317 pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1318 memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1319 skb_reset_mac_header(skb);
1320 skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1324 stats->csum_complete++;
1326 stats->bytes += cqe_bcnt;
1329 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1331 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1332 struct mlx5e_wqe_frag_info *wi;
1333 struct sk_buff *skb;
1337 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1338 wi = get_frag(rq, ci);
1339 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1341 skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1345 mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1346 if (unlikely(!skb->dev)) {
1347 dev_kfree_skb_any(skb);
1350 napi_gro_receive(rq->cq.napi, skb);
1353 mlx5e_free_rx_wqe(rq, wi, true);
1354 mlx5_wq_cyc_pop(wq);
1357 #endif /* CONFIG_MLX5_CORE_IPOIB */
1359 #ifdef CONFIG_MLX5_EN_IPSEC
1361 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1363 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1364 struct mlx5e_wqe_frag_info *wi;
1365 struct sk_buff *skb;
1369 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1370 wi = get_frag(rq, ci);
1371 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1373 skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1374 if (unlikely(!skb)) {
1375 /* a DROP, save the page-reuse checks */
1376 mlx5e_free_rx_wqe(rq, wi, true);
1379 skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb, &cqe_bcnt);
1380 if (unlikely(!skb)) {
1381 mlx5e_free_rx_wqe(rq, wi, true);
1385 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1386 napi_gro_receive(rq->cq.napi, skb);
1388 mlx5e_free_rx_wqe(rq, wi, true);
1390 mlx5_wq_cyc_pop(wq);
1393 #endif /* CONFIG_MLX5_EN_IPSEC */