2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/ipv6.h>
35 #include <linux/tcp.h>
36 #include <net/ip6_checksum.h>
37 #include <net/page_pool.h>
38 #include <net/inet_ecn.h>
44 #include "en/rep/tc.h"
45 #include "ipoib/ipoib.h"
46 #include "accel/ipsec.h"
47 #include "fpga/ipsec.h"
48 #include "en_accel/ipsec_rxtx.h"
49 #include "en_accel/tls_rxtx.h"
51 #include "en/xsk/rx.h"
52 #include "en/health.h"
53 #include "en/params.h"
55 #include "en/devlink.h"
57 static struct sk_buff *
58 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
59 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
60 static struct sk_buff *
61 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
62 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
63 static void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
64 static void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
66 const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic = {
67 .handle_rx_cqe = mlx5e_handle_rx_cqe,
68 .handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
71 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config)
73 return config->rx_filter == HWTSTAMP_FILTER_ALL;
76 static inline void mlx5e_read_cqe_slot(struct mlx5_cqwq *wq,
79 u32 ci = mlx5_cqwq_ctr2ix(wq, cqcc);
81 memcpy(data, mlx5_cqwq_get_wqe(wq, ci), sizeof(struct mlx5_cqe64));
84 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
88 struct mlx5e_cq_decomp *cqd = &rq->cqd;
89 struct mlx5_cqe64 *title = &cqd->title;
91 mlx5e_read_cqe_slot(wq, cqcc, title);
92 cqd->left = be32_to_cpu(title->byte_cnt);
93 cqd->wqe_counter = be16_to_cpu(title->wqe_counter);
94 rq->stats->cqe_compress_blks++;
97 static inline void mlx5e_read_mini_arr_slot(struct mlx5_cqwq *wq,
98 struct mlx5e_cq_decomp *cqd,
101 mlx5e_read_cqe_slot(wq, cqcc, cqd->mini_arr);
102 cqd->mini_arr_idx = 0;
105 static inline void mlx5e_cqes_update_owner(struct mlx5_cqwq *wq, int n)
108 u8 op_own = mlx5_cqwq_get_ctr_wrap_cnt(wq, cqcc) & 1;
109 u32 ci = mlx5_cqwq_ctr2ix(wq, cqcc);
110 u32 wq_sz = mlx5_cqwq_get_size(wq);
111 u32 ci_top = min_t(u32, wq_sz, ci + n);
113 for (; ci < ci_top; ci++, n--) {
114 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci);
116 cqe->op_own = op_own;
119 if (unlikely(ci == wq_sz)) {
121 for (ci = 0; ci < n; ci++) {
122 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci);
124 cqe->op_own = op_own;
129 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
130 struct mlx5_cqwq *wq,
133 struct mlx5e_cq_decomp *cqd = &rq->cqd;
134 struct mlx5_mini_cqe8 *mini_cqe = &cqd->mini_arr[cqd->mini_arr_idx];
135 struct mlx5_cqe64 *title = &cqd->title;
137 title->byte_cnt = mini_cqe->byte_cnt;
138 title->check_sum = mini_cqe->checksum;
139 title->op_own &= 0xf0;
140 title->op_own |= 0x01 & (cqcc >> wq->fbc.log_sz);
142 /* state bit set implies linked-list striding RQ wq type and
143 * HW stride index capability supported
145 if (test_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &rq->state)) {
146 title->wqe_counter = mini_cqe->stridx;
150 /* HW stride index capability not supported */
151 title->wqe_counter = cpu_to_be16(cqd->wqe_counter);
152 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
153 cqd->wqe_counter += mpwrq_get_cqe_consumed_strides(title);
156 mlx5_wq_cyc_ctr2ix(&rq->wqe.wq, cqd->wqe_counter + 1);
159 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
160 struct mlx5_cqwq *wq,
163 struct mlx5e_cq_decomp *cqd = &rq->cqd;
165 mlx5e_decompress_cqe(rq, wq, cqcc);
166 cqd->title.rss_hash_type = 0;
167 cqd->title.rss_hash_result = 0;
170 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
171 struct mlx5_cqwq *wq,
172 int update_owner_only,
175 struct mlx5e_cq_decomp *cqd = &rq->cqd;
176 u32 cqcc = wq->cc + update_owner_only;
180 cqe_count = min_t(u32, cqd->left, budget_rem);
182 for (i = update_owner_only; i < cqe_count;
183 i++, cqd->mini_arr_idx++, cqcc++) {
184 if (cqd->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
185 mlx5e_read_mini_arr_slot(wq, cqd, cqcc);
187 mlx5e_decompress_cqe_no_hash(rq, wq, cqcc);
188 INDIRECT_CALL_2(rq->handle_rx_cqe, mlx5e_handle_rx_cqe_mpwrq,
189 mlx5e_handle_rx_cqe, rq, &cqd->title);
191 mlx5e_cqes_update_owner(wq, cqcc - wq->cc);
193 cqd->left -= cqe_count;
194 rq->stats->cqe_compress_pkts += cqe_count;
199 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
200 struct mlx5_cqwq *wq,
203 struct mlx5e_cq_decomp *cqd = &rq->cqd;
206 mlx5e_read_title_slot(rq, wq, cc);
207 mlx5e_read_mini_arr_slot(wq, cqd, cc + 1);
208 mlx5e_decompress_cqe(rq, wq, cc);
209 INDIRECT_CALL_2(rq->handle_rx_cqe, mlx5e_handle_rx_cqe_mpwrq,
210 mlx5e_handle_rx_cqe, rq, &cqd->title);
213 return mlx5e_decompress_cqes_cont(rq, wq, 1, budget_rem) - 1;
216 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
217 struct mlx5e_dma_info *dma_info)
219 struct mlx5e_page_cache *cache = &rq->page_cache;
220 u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
221 struct mlx5e_rq_stats *stats = rq->stats;
223 if (tail_next == cache->head) {
228 if (!dev_page_is_reusable(dma_info->page)) {
229 stats->cache_waive++;
233 cache->page_cache[cache->tail] = *dma_info;
234 cache->tail = tail_next;
238 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
239 struct mlx5e_dma_info *dma_info)
241 struct mlx5e_page_cache *cache = &rq->page_cache;
242 struct mlx5e_rq_stats *stats = rq->stats;
244 if (unlikely(cache->head == cache->tail)) {
245 stats->cache_empty++;
249 if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
254 *dma_info = cache->page_cache[cache->head];
255 cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
256 stats->cache_reuse++;
258 dma_sync_single_for_device(rq->pdev, dma_info->addr,
264 static inline int mlx5e_page_alloc_pool(struct mlx5e_rq *rq,
265 struct mlx5e_dma_info *dma_info)
267 if (mlx5e_rx_cache_get(rq, dma_info))
270 dma_info->page = page_pool_dev_alloc_pages(rq->page_pool);
271 if (unlikely(!dma_info->page))
274 dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
275 PAGE_SIZE, rq->buff.map_dir);
276 if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
277 page_pool_recycle_direct(rq->page_pool, dma_info->page);
278 dma_info->page = NULL;
285 static inline int mlx5e_page_alloc(struct mlx5e_rq *rq,
286 struct mlx5e_dma_info *dma_info)
289 return mlx5e_xsk_page_alloc_pool(rq, dma_info);
291 return mlx5e_page_alloc_pool(rq, dma_info);
294 void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info)
296 dma_unmap_page(rq->pdev, dma_info->addr, PAGE_SIZE, rq->buff.map_dir);
299 void mlx5e_page_release_dynamic(struct mlx5e_rq *rq,
300 struct mlx5e_dma_info *dma_info,
303 if (likely(recycle)) {
304 if (mlx5e_rx_cache_put(rq, dma_info))
307 mlx5e_page_dma_unmap(rq, dma_info);
308 page_pool_recycle_direct(rq->page_pool, dma_info->page);
310 mlx5e_page_dma_unmap(rq, dma_info);
311 page_pool_release_page(rq->page_pool, dma_info->page);
312 put_page(dma_info->page);
316 static inline void mlx5e_page_release(struct mlx5e_rq *rq,
317 struct mlx5e_dma_info *dma_info,
321 /* The `recycle` parameter is ignored, and the page is always
322 * put into the Reuse Ring, because there is no way to return
323 * the page to the userspace when the interface goes down.
325 xsk_buff_free(dma_info->xsk);
327 mlx5e_page_release_dynamic(rq, dma_info, recycle);
330 static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq,
331 struct mlx5e_wqe_frag_info *frag)
336 /* On first frag (offset == 0), replenish page (dma_info actually).
337 * Other frags that point to the same dma_info (with a different
338 * offset) should just use the new one without replenishing again
341 err = mlx5e_page_alloc(rq, frag->di);
346 static inline void mlx5e_put_rx_frag(struct mlx5e_rq *rq,
347 struct mlx5e_wqe_frag_info *frag,
350 if (frag->last_in_page)
351 mlx5e_page_release(rq, frag->di, recycle);
354 static inline struct mlx5e_wqe_frag_info *get_frag(struct mlx5e_rq *rq, u16 ix)
356 return &rq->wqe.frags[ix << rq->wqe.info.log_num_frags];
359 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe_cyc *wqe,
362 struct mlx5e_wqe_frag_info *frag = get_frag(rq, ix);
366 for (i = 0; i < rq->wqe.info.num_frags; i++, frag++) {
367 err = mlx5e_get_rx_frag(rq, frag);
371 wqe->data[i].addr = cpu_to_be64(frag->di->addr +
372 frag->offset + rq->buff.headroom);
379 mlx5e_put_rx_frag(rq, --frag, true);
384 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
385 struct mlx5e_wqe_frag_info *wi,
390 for (i = 0; i < rq->wqe.info.num_frags; i++, wi++)
391 mlx5e_put_rx_frag(rq, wi, recycle);
394 static void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
396 struct mlx5e_wqe_frag_info *wi = get_frag(rq, ix);
398 mlx5e_free_rx_wqe(rq, wi, false);
401 static int mlx5e_alloc_rx_wqes(struct mlx5e_rq *rq, u16 ix, u8 wqe_bulk)
403 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
408 int pages_desired = wqe_bulk << rq->wqe.info.log_num_frags;
410 /* Check in advance that we have enough frames, instead of
411 * allocating one-by-one, failing and moving frames to the
414 if (unlikely(!xsk_buff_can_alloc(rq->xsk_pool, pages_desired)))
418 for (i = 0; i < wqe_bulk; i++) {
419 struct mlx5e_rx_wqe_cyc *wqe = mlx5_wq_cyc_get_wqe(wq, ix + i);
421 err = mlx5e_alloc_rx_wqe(rq, wqe, ix + i);
430 mlx5e_dealloc_rx_wqe(rq, ix + i);
436 mlx5e_add_skb_frag(struct mlx5e_rq *rq, struct sk_buff *skb,
437 struct mlx5e_dma_info *di, u32 frag_offset, u32 len,
438 unsigned int truesize)
440 dma_sync_single_for_cpu(rq->pdev,
441 di->addr + frag_offset,
442 len, DMA_FROM_DEVICE);
443 page_ref_inc(di->page);
444 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
445 di->page, frag_offset, len, truesize);
449 mlx5e_copy_skb_header(struct device *pdev, struct sk_buff *skb,
450 struct mlx5e_dma_info *dma_info,
451 int offset_from, u32 headlen)
453 const void *from = page_address(dma_info->page) + offset_from;
454 /* Aligning len to sizeof(long) optimizes memcpy performance */
455 unsigned int len = ALIGN(headlen, sizeof(long));
457 dma_sync_single_for_cpu(pdev, dma_info->addr + offset_from, len,
459 skb_copy_to_linear_data(skb, from, len);
463 mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, bool recycle)
466 struct mlx5e_dma_info *dma_info = wi->umr.dma_info;
469 /* A common case for AF_XDP. */
470 if (bitmap_full(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE))
473 no_xdp_xmit = bitmap_empty(wi->xdp_xmit_bitmap,
474 MLX5_MPWRQ_PAGES_PER_WQE);
476 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++)
477 if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap))
478 mlx5e_page_release(rq, &dma_info[i], recycle);
481 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq, u8 n)
483 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
486 u16 next_wqe_index = mlx5_wq_ll_get_wqe_next_ix(wq, wq->head);
488 mlx5_wq_ll_push(wq, next_wqe_index);
491 /* ensure wqes are visible to device before updating doorbell record */
494 mlx5_wq_ll_update_db_record(wq);
497 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
499 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
500 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
501 struct mlx5e_icosq *sq = rq->icosq;
502 struct mlx5_wq_cyc *wq = &sq->wq;
503 struct mlx5e_umr_wqe *umr_wqe;
508 /* Check in advance that we have enough frames, instead of allocating
509 * one-by-one, failing and moving frames to the Reuse Ring.
512 unlikely(!xsk_buff_can_alloc(rq->xsk_pool, MLX5_MPWRQ_PAGES_PER_WQE))) {
517 pi = mlx5e_icosq_get_next_pi(sq, MLX5E_UMR_WQEBBS);
518 umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi);
519 memcpy(umr_wqe, &rq->mpwqe.umr_wqe, offsetof(struct mlx5e_umr_wqe, inline_mtts));
521 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
522 err = mlx5e_page_alloc(rq, dma_info);
525 umr_wqe->inline_mtts[i].ptag = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
528 bitmap_zero(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
529 wi->consumed_strides = 0;
531 umr_wqe->ctrl.opmod_idx_opcode =
532 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
534 umr_wqe->uctrl.xlt_offset =
535 cpu_to_be16(MLX5_ALIGNED_MTTS_OCTW(MLX5E_REQUIRED_MTTS(ix)));
537 sq->db.wqe_info[pi] = (struct mlx5e_icosq_wqe_info) {
538 .wqe_type = MLX5E_ICOSQ_WQE_UMR_RX,
539 .num_wqebbs = MLX5E_UMR_WQEBBS,
543 sq->pc += MLX5E_UMR_WQEBBS;
545 sq->doorbell_cseg = &umr_wqe->ctrl;
552 mlx5e_page_release(rq, dma_info, true);
556 rq->stats->buff_alloc_err++;
561 static void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
563 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
564 /* Don't recycle, this function is called on rq/netdev close */
565 mlx5e_free_rx_mpwqe(rq, wi, false);
568 INDIRECT_CALLABLE_SCOPE bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
570 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
574 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
577 wqe_bulk = rq->wqe.info.wqe_bulk;
579 if (mlx5_wq_cyc_missing(wq) < wqe_bulk)
583 page_pool_nid_changed(rq->page_pool, numa_mem_id());
586 u16 head = mlx5_wq_cyc_get_head(wq);
588 err = mlx5e_alloc_rx_wqes(rq, head, wqe_bulk);
590 rq->stats->buff_alloc_err++;
594 mlx5_wq_cyc_push_n(wq, wqe_bulk);
595 } while (mlx5_wq_cyc_missing(wq) >= wqe_bulk);
597 /* ensure wqes are visible to device before updating doorbell record */
600 mlx5_wq_cyc_update_db_record(wq);
605 void mlx5e_free_icosq_descs(struct mlx5e_icosq *sq)
611 while (sqcc != sq->pc) {
612 struct mlx5e_icosq_wqe_info *wi;
615 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
616 wi = &sq->db.wqe_info[ci];
617 sqcc += wi->num_wqebbs;
618 #ifdef CONFIG_MLX5_EN_TLS
619 switch (wi->wqe_type) {
620 case MLX5E_ICOSQ_WQE_SET_PSV_TLS:
621 mlx5e_ktls_handle_ctx_completion(wi);
623 case MLX5E_ICOSQ_WQE_GET_PSV_TLS:
624 mlx5e_ktls_handle_get_psv_completion(wi, sq);
632 int mlx5e_poll_ico_cq(struct mlx5e_cq *cq)
634 struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
635 struct mlx5_cqe64 *cqe;
639 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
642 cqe = mlx5_cqwq_get_cqe(&cq->wq);
646 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
647 * otherwise a cq overrun may occur
656 mlx5_cqwq_pop(&cq->wq);
658 wqe_counter = be16_to_cpu(cqe->wqe_counter);
661 struct mlx5e_icosq_wqe_info *wi;
664 last_wqe = (sqcc == wqe_counter);
666 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
667 wi = &sq->db.wqe_info[ci];
668 sqcc += wi->num_wqebbs;
670 if (last_wqe && unlikely(get_cqe_opcode(cqe) != MLX5_CQE_REQ)) {
671 netdev_WARN_ONCE(cq->netdev,
672 "Bad OP in ICOSQ CQE: 0x%x\n",
673 get_cqe_opcode(cqe));
674 mlx5e_dump_error_cqe(&sq->cq, sq->sqn,
675 (struct mlx5_err_cqe *)cqe);
676 mlx5_wq_cyc_wqe_dump(&sq->wq, ci, wi->num_wqebbs);
677 if (!test_and_set_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state))
678 queue_work(cq->priv->wq, &sq->recover_work);
682 switch (wi->wqe_type) {
683 case MLX5E_ICOSQ_WQE_UMR_RX:
684 wi->umr.rq->mpwqe.umr_completed++;
686 case MLX5E_ICOSQ_WQE_NOP:
688 #ifdef CONFIG_MLX5_EN_TLS
689 case MLX5E_ICOSQ_WQE_UMR_TLS:
691 case MLX5E_ICOSQ_WQE_SET_PSV_TLS:
692 mlx5e_ktls_handle_ctx_completion(wi);
694 case MLX5E_ICOSQ_WQE_GET_PSV_TLS:
695 mlx5e_ktls_handle_get_psv_completion(wi, sq);
699 netdev_WARN_ONCE(cq->netdev,
700 "Bad WQE type in ICOSQ WQE info: 0x%x\n",
704 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
708 mlx5_cqwq_update_db_record(&cq->wq);
713 INDIRECT_CALLABLE_SCOPE bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
715 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
716 u8 umr_completed = rq->mpwqe.umr_completed;
717 struct mlx5e_icosq *sq = rq->icosq;
722 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
726 mlx5e_post_rx_mpwqe(rq, umr_completed);
727 rq->mpwqe.umr_in_progress -= umr_completed;
728 rq->mpwqe.umr_completed = 0;
731 missing = mlx5_wq_ll_missing(wq) - rq->mpwqe.umr_in_progress;
733 if (unlikely(rq->mpwqe.umr_in_progress > rq->mpwqe.umr_last_bulk))
734 rq->stats->congst_umr++;
736 #define UMR_WQE_BULK (2)
737 if (likely(missing < UMR_WQE_BULK))
741 page_pool_nid_changed(rq->page_pool, numa_mem_id());
743 head = rq->mpwqe.actual_wq_head;
746 alloc_err = mlx5e_alloc_rx_mpwqe(rq, head);
748 if (unlikely(alloc_err))
750 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
753 rq->mpwqe.umr_last_bulk = missing - i;
754 if (sq->doorbell_cseg) {
755 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, sq->doorbell_cseg);
756 sq->doorbell_cseg = NULL;
759 rq->mpwqe.umr_in_progress += rq->mpwqe.umr_last_bulk;
760 rq->mpwqe.actual_wq_head = head;
762 /* If XSK Fill Ring doesn't have enough frames, report the error, so
763 * that one of the actions can be performed:
764 * 1. If need_wakeup is used, signal that the application has to kick
765 * the driver when it refills the Fill Ring.
766 * 2. Otherwise, busy poll by rescheduling the NAPI poll.
768 if (unlikely(alloc_err == -ENOMEM && rq->xsk_pool))
774 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp)
776 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
777 u8 tcp_ack = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
778 (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
781 tcp->psh = get_cqe_lro_tcppsh(cqe);
785 tcp->ack_seq = cqe->lro_ack_seq_num;
786 tcp->window = cqe->lro_tcp_win;
790 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
793 struct ethhdr *eth = (struct ethhdr *)(skb->data);
795 int network_depth = 0;
801 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
803 tot_len = cqe_bcnt - network_depth;
804 ip_p = skb->data + network_depth;
806 if (proto == htons(ETH_P_IP)) {
807 struct iphdr *ipv4 = ip_p;
809 tcp = ip_p + sizeof(struct iphdr);
810 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
812 ipv4->ttl = cqe->lro_min_ttl;
813 ipv4->tot_len = cpu_to_be16(tot_len);
815 ipv4->check = ip_fast_csum((unsigned char *)ipv4,
818 mlx5e_lro_update_tcp_hdr(cqe, tcp);
819 check = csum_partial(tcp, tcp->doff * 4,
820 csum_unfold((__force __sum16)cqe->check_sum));
821 /* Almost done, don't forget the pseudo header */
822 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr,
823 tot_len - sizeof(struct iphdr),
826 u16 payload_len = tot_len - sizeof(struct ipv6hdr);
827 struct ipv6hdr *ipv6 = ip_p;
829 tcp = ip_p + sizeof(struct ipv6hdr);
830 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
832 ipv6->hop_limit = cqe->lro_min_ttl;
833 ipv6->payload_len = cpu_to_be16(payload_len);
835 mlx5e_lro_update_tcp_hdr(cqe, tcp);
836 check = csum_partial(tcp, tcp->doff * 4,
837 csum_unfold((__force __sum16)cqe->check_sum));
838 /* Almost done, don't forget the pseudo header */
839 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len,
844 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
847 u8 cht = cqe->rss_hash_type;
848 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
849 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
851 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
854 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth,
857 *proto = ((struct ethhdr *)skb->data)->h_proto;
858 *proto = __vlan_get_protocol(skb, *proto, network_depth);
860 if (*proto == htons(ETH_P_IP))
861 return pskb_may_pull(skb, *network_depth + sizeof(struct iphdr));
863 if (*proto == htons(ETH_P_IPV6))
864 return pskb_may_pull(skb, *network_depth + sizeof(struct ipv6hdr));
869 static inline void mlx5e_enable_ecn(struct mlx5e_rq *rq, struct sk_buff *skb)
871 int network_depth = 0;
876 if (unlikely(!is_last_ethertype_ip(skb, &network_depth, &proto)))
879 ip = skb->data + network_depth;
880 rc = ((proto == htons(ETH_P_IP)) ? IP_ECN_set_ce((struct iphdr *)ip) :
881 IP6_ECN_set_ce(skb, (struct ipv6hdr *)ip));
883 rq->stats->ecn_mark += !!rc;
886 static u8 get_ip_proto(struct sk_buff *skb, int network_depth, __be16 proto)
888 void *ip_p = skb->data + network_depth;
890 return (proto == htons(ETH_P_IP)) ? ((struct iphdr *)ip_p)->protocol :
891 ((struct ipv6hdr *)ip_p)->nexthdr;
894 #define short_frame(size) ((size) <= ETH_ZLEN + ETH_FCS_LEN)
896 #define MAX_PADDING 8
899 tail_padding_csum_slow(struct sk_buff *skb, int offset, int len,
900 struct mlx5e_rq_stats *stats)
902 stats->csum_complete_tail_slow++;
903 skb->csum = csum_block_add(skb->csum,
904 skb_checksum(skb, offset, len, 0),
909 tail_padding_csum(struct sk_buff *skb, int offset,
910 struct mlx5e_rq_stats *stats)
912 u8 tail_padding[MAX_PADDING];
913 int len = skb->len - offset;
916 if (unlikely(len > MAX_PADDING)) {
917 tail_padding_csum_slow(skb, offset, len, stats);
921 tail = skb_header_pointer(skb, offset, len, tail_padding);
922 if (unlikely(!tail)) {
923 tail_padding_csum_slow(skb, offset, len, stats);
927 stats->csum_complete_tail++;
928 skb->csum = csum_block_add(skb->csum, csum_partial(tail, len, 0), offset);
932 mlx5e_skb_csum_fixup(struct sk_buff *skb, int network_depth, __be16 proto,
933 struct mlx5e_rq_stats *stats)
939 /* Fixup vlan headers, if any */
940 if (network_depth > ETH_HLEN)
941 /* CQE csum is calculated from the IP header and does
942 * not cover VLAN headers (if present). This will add
943 * the checksum manually.
945 skb->csum = csum_partial(skb->data + ETH_HLEN,
946 network_depth - ETH_HLEN,
949 /* Fixup tail padding, if any */
951 case htons(ETH_P_IP):
952 ip4 = (struct iphdr *)(skb->data + network_depth);
953 pkt_len = network_depth + ntohs(ip4->tot_len);
955 case htons(ETH_P_IPV6):
956 ip6 = (struct ipv6hdr *)(skb->data + network_depth);
957 pkt_len = network_depth + sizeof(*ip6) + ntohs(ip6->payload_len);
963 if (likely(pkt_len >= skb->len))
966 tail_padding_csum(skb, pkt_len, stats);
969 static inline void mlx5e_handle_csum(struct net_device *netdev,
970 struct mlx5_cqe64 *cqe,
975 struct mlx5e_rq_stats *stats = rq->stats;
976 int network_depth = 0;
979 if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
983 skb->ip_summed = CHECKSUM_UNNECESSARY;
984 stats->csum_unnecessary++;
988 /* True when explicitly set via priv flag, or XDP prog is loaded */
989 if (test_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state))
990 goto csum_unnecessary;
992 /* CQE csum doesn't cover padding octets in short ethernet
993 * frames. And the pad field is appended prior to calculating
994 * and appending the FCS field.
996 * Detecting these padded frames requires to verify and parse
997 * IP headers, so we simply force all those small frames to be
998 * CHECKSUM_UNNECESSARY even if they are not padded.
1000 if (short_frame(skb->len))
1001 goto csum_unnecessary;
1003 if (likely(is_last_ethertype_ip(skb, &network_depth, &proto))) {
1004 u8 ipproto = get_ip_proto(skb, network_depth, proto);
1006 if (unlikely(ipproto == IPPROTO_SCTP))
1007 goto csum_unnecessary;
1009 if (unlikely(mlx5_ipsec_is_rx_flow(cqe)))
1012 stats->csum_complete++;
1013 skb->ip_summed = CHECKSUM_COMPLETE;
1014 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1016 if (test_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state))
1017 return; /* CQE csum covers all received bytes */
1019 /* csum might need some fixups ...*/
1020 mlx5e_skb_csum_fixup(skb, network_depth, proto, stats);
1025 if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
1026 (cqe->hds_ip_ext & CQE_L4_OK))) {
1027 skb->ip_summed = CHECKSUM_UNNECESSARY;
1028 if (cqe_is_tunneled(cqe)) {
1029 skb->csum_level = 1;
1030 skb->encapsulation = 1;
1031 stats->csum_unnecessary_inner++;
1034 stats->csum_unnecessary++;
1038 skb->ip_summed = CHECKSUM_NONE;
1042 #define MLX5E_CE_BIT_MASK 0x80
1044 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
1046 struct mlx5e_rq *rq,
1047 struct sk_buff *skb)
1049 u8 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
1050 struct mlx5e_rq_stats *stats = rq->stats;
1051 struct net_device *netdev = rq->netdev;
1053 skb->mac_len = ETH_HLEN;
1055 mlx5e_tls_handle_rx_skb(rq, skb, cqe, &cqe_bcnt);
1057 if (unlikely(mlx5_ipsec_is_rx_flow(cqe)))
1058 mlx5e_ipsec_offload_handle_rx_skb(netdev, skb, cqe);
1060 if (lro_num_seg > 1) {
1061 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
1062 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
1063 /* Subtract one since we already counted this as one
1064 * "regular" packet in mlx5e_complete_rx_cqe()
1066 stats->packets += lro_num_seg - 1;
1067 stats->lro_packets++;
1068 stats->lro_bytes += cqe_bcnt;
1071 if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp)))
1072 skb_hwtstamps(skb)->hwtstamp = mlx5e_cqe_ts_to_ns(rq->ptp_cyc2time,
1073 rq->clock, get_cqe_ts(cqe));
1074 skb_record_rx_queue(skb, rq->ix);
1076 if (likely(netdev->features & NETIF_F_RXHASH))
1077 mlx5e_skb_set_hash(cqe, skb);
1079 if (cqe_has_vlan(cqe)) {
1080 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1081 be16_to_cpu(cqe->vlan_info));
1082 stats->removed_vlan_packets++;
1085 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
1087 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
1088 /* checking CE bit in cqe - MSB in ml_path field */
1089 if (unlikely(cqe->ml_path & MLX5E_CE_BIT_MASK))
1090 mlx5e_enable_ecn(rq, skb);
1092 skb->protocol = eth_type_trans(skb, netdev);
1094 if (unlikely(mlx5e_skb_is_multicast(skb)))
1095 stats->mcast_packets++;
1098 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
1099 struct mlx5_cqe64 *cqe,
1101 struct sk_buff *skb)
1103 struct mlx5e_rq_stats *stats = rq->stats;
1106 stats->bytes += cqe_bcnt;
1107 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
1111 struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va,
1112 u32 frag_size, u16 headroom,
1115 struct sk_buff *skb = build_skb(va, frag_size);
1117 if (unlikely(!skb)) {
1118 rq->stats->buff_alloc_err++;
1122 skb_reserve(skb, headroom);
1123 skb_put(skb, cqe_bcnt);
1128 static void mlx5e_fill_xdp_buff(struct mlx5e_rq *rq, void *va, u16 headroom,
1129 u32 len, struct xdp_buff *xdp)
1131 xdp_init_buff(xdp, rq->buff.frame0_sz, &rq->xdp_rxq);
1132 xdp_prepare_buff(xdp, va, headroom, len, false);
1135 static struct sk_buff *
1136 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
1137 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
1139 struct mlx5e_dma_info *di = wi->di;
1140 u16 rx_headroom = rq->buff.headroom;
1141 struct xdp_buff xdp;
1142 struct sk_buff *skb;
1146 va = page_address(di->page) + wi->offset;
1147 data = va + rx_headroom;
1148 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
1150 dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset,
1151 frag_size, DMA_FROM_DEVICE);
1152 net_prefetchw(va); /* xdp_frame data area */
1155 mlx5e_fill_xdp_buff(rq, va, rx_headroom, cqe_bcnt, &xdp);
1156 if (mlx5e_xdp_handle(rq, di, &cqe_bcnt, &xdp))
1157 return NULL; /* page/packet was consumed by XDP */
1159 rx_headroom = xdp.data - xdp.data_hard_start;
1160 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
1161 skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt);
1165 /* queue up for recycling/reuse */
1166 page_ref_inc(di->page);
1171 static struct sk_buff *
1172 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
1173 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
1175 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
1176 struct mlx5e_wqe_frag_info *head_wi = wi;
1177 u16 headlen = min_t(u32, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1178 u16 frag_headlen = headlen;
1179 u16 byte_cnt = cqe_bcnt - headlen;
1180 struct sk_buff *skb;
1182 /* XDP is not supported in this configuration, as incoming packets
1183 * might spread among multiple pages.
1185 skb = napi_alloc_skb(rq->cq.napi,
1186 ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1187 if (unlikely(!skb)) {
1188 rq->stats->buff_alloc_err++;
1192 net_prefetchw(skb->data);
1195 u16 frag_consumed_bytes =
1196 min_t(u16, frag_info->frag_size - frag_headlen, byte_cnt);
1198 mlx5e_add_skb_frag(rq, skb, wi->di, wi->offset + frag_headlen,
1199 frag_consumed_bytes, frag_info->frag_stride);
1200 byte_cnt -= frag_consumed_bytes;
1207 mlx5e_copy_skb_header(rq->pdev, skb, head_wi->di, head_wi->offset, headlen);
1208 /* skb linear part was allocated with headlen and aligned to long */
1209 skb->tail += headlen;
1210 skb->len += headlen;
1215 static void trigger_report(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1217 struct mlx5_err_cqe *err_cqe = (struct mlx5_err_cqe *)cqe;
1218 struct mlx5e_priv *priv = rq->priv;
1220 if (cqe_syndrome_needs_recover(err_cqe->syndrome) &&
1221 !test_and_set_bit(MLX5E_RQ_STATE_RECOVERING, &rq->state)) {
1222 mlx5e_dump_error_cqe(&rq->cq, rq->rqn, err_cqe);
1223 queue_work(priv->wq, &rq->recover_work);
1227 static void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1229 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1230 struct mlx5e_wqe_frag_info *wi;
1231 struct sk_buff *skb;
1235 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1236 wi = get_frag(rq, ci);
1237 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1239 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1240 trigger_report(rq, cqe);
1241 rq->stats->wqe_err++;
1245 skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1246 mlx5e_skb_from_cqe_linear,
1247 mlx5e_skb_from_cqe_nonlinear,
1248 rq, cqe, wi, cqe_bcnt);
1250 /* probably for XDP */
1251 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1252 /* do not return page to cache,
1253 * it will be returned on XDP_TX completion.
1260 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1262 if (mlx5e_cqe_regb_chain(cqe))
1263 if (!mlx5e_tc_update_skb(cqe, skb)) {
1264 dev_kfree_skb_any(skb);
1268 napi_gro_receive(rq->cq.napi, skb);
1271 mlx5e_free_rx_wqe(rq, wi, true);
1273 mlx5_wq_cyc_pop(wq);
1276 #ifdef CONFIG_MLX5_ESWITCH
1277 static void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1279 struct net_device *netdev = rq->netdev;
1280 struct mlx5e_priv *priv = netdev_priv(netdev);
1281 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1282 struct mlx5_eswitch_rep *rep = rpriv->rep;
1283 struct mlx5e_tc_update_priv tc_priv = {};
1284 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1285 struct mlx5e_wqe_frag_info *wi;
1286 struct sk_buff *skb;
1290 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1291 wi = get_frag(rq, ci);
1292 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1294 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1295 rq->stats->wqe_err++;
1299 skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1300 mlx5e_skb_from_cqe_linear,
1301 mlx5e_skb_from_cqe_nonlinear,
1302 rq, cqe, wi, cqe_bcnt);
1304 /* probably for XDP */
1305 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1306 /* do not return page to cache,
1307 * it will be returned on XDP_TX completion.
1314 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1316 if (rep->vlan && skb_vlan_tag_present(skb))
1319 if (unlikely(!mlx5_ipsec_is_rx_flow(cqe) &&
1320 !mlx5e_rep_tc_update_skb(cqe, skb, &tc_priv))) {
1321 dev_kfree_skb_any(skb);
1325 napi_gro_receive(rq->cq.napi, skb);
1327 mlx5_rep_tc_post_napi_receive(&tc_priv);
1330 mlx5e_free_rx_wqe(rq, wi, true);
1332 mlx5_wq_cyc_pop(wq);
1335 static void mlx5e_handle_rx_cqe_mpwrq_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1337 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe);
1338 u16 wqe_id = be16_to_cpu(cqe->wqe_id);
1339 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1340 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe);
1341 u32 wqe_offset = stride_ix << rq->mpwqe.log_stride_sz;
1342 u32 head_offset = wqe_offset & (PAGE_SIZE - 1);
1343 u32 page_idx = wqe_offset >> PAGE_SHIFT;
1344 struct mlx5e_tc_update_priv tc_priv = {};
1345 struct mlx5e_rx_wqe_ll *wqe;
1346 struct mlx5_wq_ll *wq;
1347 struct sk_buff *skb;
1350 wi->consumed_strides += cstrides;
1352 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1353 trigger_report(rq, cqe);
1354 rq->stats->wqe_err++;
1358 if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1359 struct mlx5e_rq_stats *stats = rq->stats;
1361 stats->mpwqe_filler_cqes++;
1362 stats->mpwqe_filler_strides += cstrides;
1366 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1368 skb = INDIRECT_CALL_2(rq->mpwqe.skb_from_cqe_mpwrq,
1369 mlx5e_skb_from_cqe_mpwrq_linear,
1370 mlx5e_skb_from_cqe_mpwrq_nonlinear,
1371 rq, wi, cqe_bcnt, head_offset, page_idx);
1375 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1377 if (unlikely(!mlx5_ipsec_is_rx_flow(cqe) &&
1378 !mlx5e_rep_tc_update_skb(cqe, skb, &tc_priv))) {
1379 dev_kfree_skb_any(skb);
1383 napi_gro_receive(rq->cq.napi, skb);
1385 mlx5_rep_tc_post_napi_receive(&tc_priv);
1388 if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1392 wqe = mlx5_wq_ll_get_wqe(wq, wqe_id);
1393 mlx5e_free_rx_mpwqe(rq, wi, true);
1394 mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1397 const struct mlx5e_rx_handlers mlx5e_rx_handlers_rep = {
1398 .handle_rx_cqe = mlx5e_handle_rx_cqe_rep,
1399 .handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq_rep,
1403 static struct sk_buff *
1404 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1405 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1407 u16 headlen = min_t(u16, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1408 struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1409 u32 frag_offset = head_offset + headlen;
1410 u32 byte_cnt = cqe_bcnt - headlen;
1411 struct mlx5e_dma_info *head_di = di;
1412 struct sk_buff *skb;
1414 skb = napi_alloc_skb(rq->cq.napi,
1415 ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1416 if (unlikely(!skb)) {
1417 rq->stats->buff_alloc_err++;
1421 net_prefetchw(skb->data);
1423 if (unlikely(frag_offset >= PAGE_SIZE)) {
1425 frag_offset -= PAGE_SIZE;
1429 u32 pg_consumed_bytes =
1430 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
1431 unsigned int truesize =
1432 ALIGN(pg_consumed_bytes, BIT(rq->mpwqe.log_stride_sz));
1434 mlx5e_add_skb_frag(rq, skb, di, frag_offset,
1435 pg_consumed_bytes, truesize);
1436 byte_cnt -= pg_consumed_bytes;
1441 mlx5e_copy_skb_header(rq->pdev, skb, head_di, head_offset, headlen);
1442 /* skb linear part was allocated with headlen and aligned to long */
1443 skb->tail += headlen;
1444 skb->len += headlen;
1449 static struct sk_buff *
1450 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1451 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1453 struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1454 u16 rx_headroom = rq->buff.headroom;
1455 u32 cqe_bcnt32 = cqe_bcnt;
1456 struct xdp_buff xdp;
1457 struct sk_buff *skb;
1461 /* Check packet size. Note LRO doesn't use linear SKB */
1462 if (unlikely(cqe_bcnt > rq->hw_mtu)) {
1463 rq->stats->oversize_pkts_sw_drop++;
1467 va = page_address(di->page) + head_offset;
1468 data = va + rx_headroom;
1469 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32);
1471 dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset,
1472 frag_size, DMA_FROM_DEVICE);
1473 net_prefetchw(va); /* xdp_frame data area */
1476 mlx5e_fill_xdp_buff(rq, va, rx_headroom, cqe_bcnt32, &xdp);
1477 if (mlx5e_xdp_handle(rq, di, &cqe_bcnt32, &xdp)) {
1478 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags))
1479 __set_bit(page_idx, wi->xdp_xmit_bitmap); /* non-atomic */
1480 return NULL; /* page/packet was consumed by XDP */
1483 rx_headroom = xdp.data - xdp.data_hard_start;
1484 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32);
1485 skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt32);
1489 /* queue up for recycling/reuse */
1490 page_ref_inc(di->page);
1495 static void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1497 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe);
1498 u16 wqe_id = be16_to_cpu(cqe->wqe_id);
1499 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1500 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe);
1501 u32 wqe_offset = stride_ix << rq->mpwqe.log_stride_sz;
1502 u32 head_offset = wqe_offset & (PAGE_SIZE - 1);
1503 u32 page_idx = wqe_offset >> PAGE_SHIFT;
1504 struct mlx5e_rx_wqe_ll *wqe;
1505 struct mlx5_wq_ll *wq;
1506 struct sk_buff *skb;
1509 wi->consumed_strides += cstrides;
1511 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1512 trigger_report(rq, cqe);
1513 rq->stats->wqe_err++;
1517 if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1518 struct mlx5e_rq_stats *stats = rq->stats;
1520 stats->mpwqe_filler_cqes++;
1521 stats->mpwqe_filler_strides += cstrides;
1525 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1527 skb = INDIRECT_CALL_2(rq->mpwqe.skb_from_cqe_mpwrq,
1528 mlx5e_skb_from_cqe_mpwrq_linear,
1529 mlx5e_skb_from_cqe_mpwrq_nonlinear,
1530 rq, wi, cqe_bcnt, head_offset, page_idx);
1534 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1536 if (mlx5e_cqe_regb_chain(cqe))
1537 if (!mlx5e_tc_update_skb(cqe, skb)) {
1538 dev_kfree_skb_any(skb);
1542 napi_gro_receive(rq->cq.napi, skb);
1545 if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1549 wqe = mlx5_wq_ll_get_wqe(wq, wqe_id);
1550 mlx5e_free_rx_mpwqe(rq, wi, true);
1551 mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1554 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1556 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1557 struct mlx5_cqwq *cqwq = &cq->wq;
1558 struct mlx5_cqe64 *cqe;
1561 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
1565 work_done += mlx5e_decompress_cqes_cont(rq, cqwq, 0, budget);
1566 if (work_done >= budget)
1570 cqe = mlx5_cqwq_get_cqe(cqwq);
1572 if (unlikely(work_done))
1578 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1580 mlx5e_decompress_cqes_start(rq, cqwq,
1581 budget - work_done);
1585 mlx5_cqwq_pop(cqwq);
1587 INDIRECT_CALL_2(rq->handle_rx_cqe, mlx5e_handle_rx_cqe_mpwrq,
1588 mlx5e_handle_rx_cqe, rq, cqe);
1589 } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(cqwq)));
1592 if (rcu_access_pointer(rq->xdp_prog))
1593 mlx5e_xdp_rx_poll_complete(rq);
1595 mlx5_cqwq_update_db_record(cqwq);
1597 /* ensure cq space is freed before enabling more cqes */
1603 #ifdef CONFIG_MLX5_CORE_IPOIB
1605 #define MLX5_IB_GRH_SGID_OFFSET 8
1606 #define MLX5_IB_GRH_DGID_OFFSET 24
1607 #define MLX5_GID_SIZE 16
1609 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1610 struct mlx5_cqe64 *cqe,
1612 struct sk_buff *skb)
1614 struct hwtstamp_config *tstamp;
1615 struct mlx5e_rq_stats *stats;
1616 struct net_device *netdev;
1617 struct mlx5e_priv *priv;
1618 char *pseudo_header;
1624 qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff;
1625 netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn);
1627 /* No mapping present, cannot process SKB. This might happen if a child
1628 * interface is going down while having unprocessed CQEs on parent RQ
1630 if (unlikely(!netdev)) {
1631 /* TODO: add drop counters support */
1633 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn);
1637 priv = mlx5i_epriv(netdev);
1638 tstamp = &priv->tstamp;
1639 stats = &priv->channel_stats[rq->ix].rq;
1641 flags_rqpn = be32_to_cpu(cqe->flags_rqpn);
1642 g = (flags_rqpn >> 28) & 3;
1643 dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1644 if ((!g) || dgid[0] != 0xff)
1645 skb->pkt_type = PACKET_HOST;
1646 else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1647 skb->pkt_type = PACKET_BROADCAST;
1649 skb->pkt_type = PACKET_MULTICAST;
1651 /* Drop packets that this interface sent, ie multicast packets
1652 * that the HCA has replicated.
1654 if (g && (qpn == (flags_rqpn & 0xffffff)) &&
1655 (memcmp(netdev->dev_addr + 4, skb->data + MLX5_IB_GRH_SGID_OFFSET,
1656 MLX5_GID_SIZE) == 0)) {
1661 skb_pull(skb, MLX5_IB_GRH_BYTES);
1663 skb->protocol = *((__be16 *)(skb->data));
1665 if (netdev->features & NETIF_F_RXCSUM) {
1666 skb->ip_summed = CHECKSUM_COMPLETE;
1667 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1668 stats->csum_complete++;
1670 skb->ip_summed = CHECKSUM_NONE;
1674 if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1675 skb_hwtstamps(skb)->hwtstamp = mlx5e_cqe_ts_to_ns(rq->ptp_cyc2time,
1676 rq->clock, get_cqe_ts(cqe));
1677 skb_record_rx_queue(skb, rq->ix);
1679 if (likely(netdev->features & NETIF_F_RXHASH))
1680 mlx5e_skb_set_hash(cqe, skb);
1682 /* 20 bytes of ipoib header and 4 for encap existing */
1683 pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1684 memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1685 skb_reset_mac_header(skb);
1686 skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1691 stats->bytes += cqe_bcnt;
1694 static void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1696 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1697 struct mlx5e_wqe_frag_info *wi;
1698 struct sk_buff *skb;
1702 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1703 wi = get_frag(rq, ci);
1704 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1706 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1707 rq->stats->wqe_err++;
1711 skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1712 mlx5e_skb_from_cqe_linear,
1713 mlx5e_skb_from_cqe_nonlinear,
1714 rq, cqe, wi, cqe_bcnt);
1718 mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1719 if (unlikely(!skb->dev)) {
1720 dev_kfree_skb_any(skb);
1723 napi_gro_receive(rq->cq.napi, skb);
1726 mlx5e_free_rx_wqe(rq, wi, true);
1727 mlx5_wq_cyc_pop(wq);
1730 const struct mlx5e_rx_handlers mlx5i_rx_handlers = {
1731 .handle_rx_cqe = mlx5i_handle_rx_cqe,
1732 .handle_rx_cqe_mpwqe = NULL, /* Not supported */
1734 #endif /* CONFIG_MLX5_CORE_IPOIB */
1736 #ifdef CONFIG_MLX5_EN_IPSEC
1738 static void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1740 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1741 struct mlx5e_wqe_frag_info *wi;
1742 struct sk_buff *skb;
1746 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1747 wi = get_frag(rq, ci);
1748 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1750 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1751 rq->stats->wqe_err++;
1755 skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1756 mlx5e_skb_from_cqe_linear,
1757 mlx5e_skb_from_cqe_nonlinear,
1758 rq, cqe, wi, cqe_bcnt);
1759 if (unlikely(!skb)) /* a DROP, save the page-reuse checks */
1762 skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb, &cqe_bcnt);
1766 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1767 napi_gro_receive(rq->cq.napi, skb);
1770 mlx5e_free_rx_wqe(rq, wi, true);
1771 mlx5_wq_cyc_pop(wq);
1774 #endif /* CONFIG_MLX5_EN_IPSEC */
1776 int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk)
1778 struct net_device *netdev = rq->netdev;
1779 struct mlx5_core_dev *mdev = rq->mdev;
1780 struct mlx5e_priv *priv = rq->priv;
1782 switch (rq->wq_type) {
1783 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1784 rq->mpwqe.skb_from_cqe_mpwrq = xsk ?
1785 mlx5e_xsk_skb_from_cqe_mpwrq_linear :
1786 mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ?
1787 mlx5e_skb_from_cqe_mpwrq_linear :
1788 mlx5e_skb_from_cqe_mpwrq_nonlinear;
1789 rq->post_wqes = mlx5e_post_rx_mpwqes;
1790 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
1792 rq->handle_rx_cqe = priv->profile->rx_handlers->handle_rx_cqe_mpwqe;
1793 if (mlx5_fpga_is_ipsec_device(mdev)) {
1794 netdev_err(netdev, "MPWQE RQ with Innova IPSec offload not supported\n");
1797 if (!rq->handle_rx_cqe) {
1798 netdev_err(netdev, "RX handler of MPWQE RQ is not set\n");
1802 default: /* MLX5_WQ_TYPE_CYCLIC */
1803 rq->wqe.skb_from_cqe = xsk ?
1804 mlx5e_xsk_skb_from_cqe_linear :
1805 mlx5e_rx_is_linear_skb(params, NULL) ?
1806 mlx5e_skb_from_cqe_linear :
1807 mlx5e_skb_from_cqe_nonlinear;
1808 rq->post_wqes = mlx5e_post_rx_wqes;
1809 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
1811 #ifdef CONFIG_MLX5_EN_IPSEC
1812 if ((mlx5_fpga_ipsec_device_caps(mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) &&
1814 rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
1817 rq->handle_rx_cqe = priv->profile->rx_handlers->handle_rx_cqe;
1818 if (!rq->handle_rx_cqe) {
1819 netdev_err(netdev, "RX handler of RQ is not set\n");
1827 static void mlx5e_trap_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1829 struct mlx5e_priv *priv = netdev_priv(rq->netdev);
1830 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1831 struct mlx5e_wqe_frag_info *wi;
1832 struct devlink_port *dl_port;
1833 struct sk_buff *skb;
1838 trap_id = get_cqe_flow_tag(cqe);
1839 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1840 wi = get_frag(rq, ci);
1841 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1843 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1844 rq->stats->wqe_err++;
1848 skb = mlx5e_skb_from_cqe_nonlinear(rq, cqe, wi, cqe_bcnt);
1852 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1853 skb_push(skb, ETH_HLEN);
1855 dl_port = mlx5e_devlink_get_dl_port(priv);
1856 mlx5_devlink_trap_report(rq->mdev, trap_id, skb, dl_port);
1857 dev_kfree_skb_any(skb);
1860 mlx5e_free_rx_wqe(rq, wi, false);
1861 mlx5_wq_cyc_pop(wq);
1864 void mlx5e_rq_set_trap_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params)
1866 rq->wqe.skb_from_cqe = mlx5e_rx_is_linear_skb(params, NULL) ?
1867 mlx5e_skb_from_cqe_linear :
1868 mlx5e_skb_from_cqe_nonlinear;
1869 rq->post_wqes = mlx5e_post_rx_wqes;
1870 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
1871 rq->handle_rx_cqe = mlx5e_trap_handle_rx_cqe;