drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <net/geneve.h>
  38 #include <linux/bpf.h>
  39 #include <linux/if_bridge.h>
  40 #include <net/page_pool.h>
  41 #include <net/xdp_sock_drv.h>
  42 #include "eswitch.h"
  43 #include "en.h"
  44 #include "en/txrx.h"
  45 #include "en_tc.h"
  46 #include "en_rep.h"
  47 #include "en_accel/ipsec.h"
  48 #include "en_accel/en_accel.h"
  49 #include "en_accel/tls.h"
  50 #include "accel/ipsec.h"
  51 #include "accel/tls.h"
  52 #include "lib/vxlan.h"
  53 #include "lib/clock.h"
  54 #include "en/port.h"
  55 #include "en/xdp.h"
  56 #include "lib/eq.h"
  57 #include "en/monitor_stats.h"
  58 #include "en/health.h"
  59 #include "en/params.h"
  60 #include "en/xsk/pool.h"
  61 #include "en/xsk/setup.h"
  62 #include "en/xsk/rx.h"
  63 #include "en/xsk/tx.h"
  64 #include "en/hv_vhca_stats.h"
  65 #include "en/devlink.h"
  66 #include "lib/mlx5.h"
  67 #include "en/ptp.h"
  68 #include "qos.h"
  69 #include "en/trap.h"
  70 #include "fpga/ipsec.h"
  71
  72 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  73 {
  74         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  75                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  76                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  77         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  78         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  79
  80         if (!striding_rq_umr)
  81                 return false;
  82         if (!inline_umr) {
  83                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  84                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  85                 return false;
  86         }
  87         return true;
  88 }
  89
  90 void mlx5e_update_carrier(struct mlx5e_priv *priv)
  91 {
  92         struct mlx5_core_dev *mdev = priv->mdev;
  93         u8 port_state;
  94         bool up;
  95
  96         port_state = mlx5_query_vport_state(mdev,
  97                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
  98                                             0);
  99
 100         up = port_state == VPORT_STATE_UP;
 101         if (up == netif_carrier_ok(priv->netdev))
 102                 netif_carrier_event(priv->netdev);
 103         if (up) {
 104                 netdev_info(priv->netdev, "Link up\n");
 105                 netif_carrier_on(priv->netdev);
 106         } else {
 107                 netdev_info(priv->netdev, "Link down\n");
 108                 netif_carrier_off(priv->netdev);
 109         }
 110 }
 111
 112 static void mlx5e_update_carrier_work(struct work_struct *work)
 113 {
 114         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 115                                                update_carrier_work);
 116
 117         mutex_lock(&priv->state_lock);
 118         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 119                 if (priv->profile->update_carrier)
 120                         priv->profile->update_carrier(priv);
 121         mutex_unlock(&priv->state_lock);
 122 }
 123
 124 static void mlx5e_update_stats_work(struct work_struct *work)
 125 {
 126         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 127                                                update_stats_work);
 128
 129         mutex_lock(&priv->state_lock);
 130         priv->profile->update_stats(priv);
 131         mutex_unlock(&priv->state_lock);
 132 }
 133
 134 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 135 {
 136         if (!priv->profile->update_stats)
 137                 return;
 138
 139         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 140                 return;
 141
 142         queue_work(priv->wq, &priv->update_stats_work);
 143 }
 144
 145 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
 146 {
 147         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
 148         struct mlx5_eqe   *eqe = data;
 149
 150         if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
 151                 return NOTIFY_DONE;
 152
 153         switch (eqe->sub_type) {
 154         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 155         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 156                 queue_work(priv->wq, &priv->update_carrier_work);
 157                 break;
 158         default:
 159                 return NOTIFY_DONE;
 160         }
 161
 162         return NOTIFY_OK;
 163 }
 164
 165 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 166 {
 167         priv->events_nb.notifier_call = async_event;
 168         mlx5_notifier_register(priv->mdev, &priv->events_nb);
 169 }
 170
 171 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 172 {
 173         mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
 174 }
 175
 176 static int blocking_event(struct notifier_block *nb, unsigned long event, void *data)
 177 {
 178         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, blocking_events_nb);
 179         int err;
 180
 181         switch (event) {
 182         case MLX5_DRIVER_EVENT_TYPE_TRAP:
 183                 err = mlx5e_handle_trap_event(priv, data);
 184                 break;
 185         default:
 186                 netdev_warn(priv->netdev, "Sync event: Unknown event %ld\n", event);
 187                 err = -EINVAL;
 188         }
 189         return err;
 190 }
 191
 192 static void mlx5e_enable_blocking_events(struct mlx5e_priv *priv)
 193 {
 194         priv->blocking_events_nb.notifier_call = blocking_event;
 195         mlx5_blocking_notifier_register(priv->mdev, &priv->blocking_events_nb);
 196 }
 197
 198 static void mlx5e_disable_blocking_events(struct mlx5e_priv *priv)
 199 {
 200         mlx5_blocking_notifier_unregister(priv->mdev, &priv->blocking_events_nb);
 201 }
 202
 203 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 204                                        struct mlx5e_icosq *sq,
 205                                        struct mlx5e_umr_wqe *wqe)
 206 {
 207         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 208         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 209         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 210
 211         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 212                                       ds_cnt);
 213         cseg->umr_mkey  = rq->mkey_be;
 214
 215         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 216         ucseg->xlt_octowords =
 217                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 218         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 219 }
 220
 221 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, int node)
 222 {
 223         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 224
 225         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 226                                                   sizeof(*rq->mpwqe.info)),
 227                                        GFP_KERNEL, node);
 228         if (!rq->mpwqe.info)
 229                 return -ENOMEM;
 230
 231         mlx5e_build_umr_wqe(rq, rq->icosq, &rq->mpwqe.umr_wqe);
 232
 233         return 0;
 234 }
 235
 236 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 237                                  u64 npages, u8 page_shift,
 238                                  struct mlx5_core_mkey *umr_mkey,
 239                                  dma_addr_t filler_addr)
 240 {
 241         struct mlx5_mtt *mtt;
 242         int inlen;
 243         void *mkc;
 244         u32 *in;
 245         int err;
 246         int i;
 247
 248         inlen = MLX5_ST_SZ_BYTES(create_mkey_in) + sizeof(*mtt) * npages;
 249
 250         in = kvzalloc(inlen, GFP_KERNEL);
 251         if (!in)
 252                 return -ENOMEM;
 253
 254         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 255
 256         MLX5_SET(mkc, mkc, free, 1);
 257         MLX5_SET(mkc, mkc, umr_en, 1);
 258         MLX5_SET(mkc, mkc, lw, 1);
 259         MLX5_SET(mkc, mkc, lr, 1);
 260         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 261         mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
 262         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 263         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
 264         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 265         MLX5_SET(mkc, mkc, translations_octword_size,
 266                  MLX5_MTT_OCTW(npages));
 267         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 268         MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
 269                  MLX5_MTT_OCTW(npages));
 270
 271         /* Initialize the mkey with all MTTs pointing to a default
 272          * page (filler_addr). When the channels are activated, UMR
 273          * WQEs will redirect the RX WQEs to the actual memory from
 274          * the RQ's pool, while the gaps (wqe_overflow) remain mapped
 275          * to the default page.
 276          */
 277         mtt = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
 278         for (i = 0 ; i < npages ; i++)
 279                 mtt[i].ptag = cpu_to_be64(filler_addr);
 280
 281         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 282
 283         kvfree(in);
 284         return err;
 285 }
 286
 287 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 288 {
 289         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 290
 291         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey,
 292                                      rq->wqe_overflow.addr);
 293 }
 294
 295 static u64 mlx5e_get_mpwqe_offset(u16 wqe_ix)
 296 {
 297         return MLX5E_REQUIRED_MTTS(wqe_ix) << PAGE_SHIFT;
 298 }
 299
 300 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 301 {
 302         struct mlx5e_wqe_frag_info next_frag = {};
 303         struct mlx5e_wqe_frag_info *prev = NULL;
 304         int i;
 305
 306         next_frag.di = &rq->wqe.di[0];
 307
 308         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 309                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 310                 struct mlx5e_wqe_frag_info *frag =
 311                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 312                 int f;
 313
 314                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 315                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 316                                 next_frag.di++;
 317                                 next_frag.offset = 0;
 318                                 if (prev)
 319                                         prev->last_in_page = true;
 320                         }
 321                         *frag = next_frag;
 322
 323                         /* prepare next */
 324                         next_frag.offset += frag_info[f].frag_stride;
 325                         prev = frag;
 326                 }
 327         }
 328
 329         if (prev)
 330                 prev->last_in_page = true;
 331 }
 332
 333 int mlx5e_init_di_list(struct mlx5e_rq *rq, int wq_sz, int node)
 334 {
 335         int len = wq_sz << rq->wqe.info.log_num_frags;
 336
 337         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)), GFP_KERNEL, node);
 338         if (!rq->wqe.di)
 339                 return -ENOMEM;
 340
 341         mlx5e_init_frags_partition(rq);
 342
 343         return 0;
 344 }
 345
 346 void mlx5e_free_di_list(struct mlx5e_rq *rq)
 347 {
 348         kvfree(rq->wqe.di);
 349 }
 350
 351 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
 352 {
 353         struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
 354
 355         mlx5e_reporter_rq_cqe_err(rq);
 356 }
 357
 358 static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
 359 {
 360         rq->wqe_overflow.page = alloc_page(GFP_KERNEL);
 361         if (!rq->wqe_overflow.page)
 362                 return -ENOMEM;
 363
 364         rq->wqe_overflow.addr = dma_map_page(rq->pdev, rq->wqe_overflow.page, 0,
 365                                              PAGE_SIZE, rq->buff.map_dir);
 366         if (dma_mapping_error(rq->pdev, rq->wqe_overflow.addr)) {
 367                 __free_page(rq->wqe_overflow.page);
 368                 return -ENOMEM;
 369         }
 370         return 0;
 371 }
 372
 373 static void mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
 374 {
 375          dma_unmap_page(rq->pdev, rq->wqe_overflow.addr, PAGE_SIZE,
 376                         rq->buff.map_dir);
 377          __free_page(rq->wqe_overflow.page);
 378 }
 379
 380 static int mlx5e_init_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
 381                              struct mlx5e_rq *rq)
 382 {
 383         struct mlx5_core_dev *mdev = c->mdev;
 384         int err;
 385
 386         rq->wq_type      = params->rq_wq_type;
 387         rq->pdev         = c->pdev;
 388         rq->netdev       = c->netdev;
 389         rq->priv         = c->priv;
 390         rq->tstamp       = c->tstamp;
 391         rq->clock        = &mdev->clock;
 392         rq->icosq        = &c->icosq;
 393         rq->ix           = c->ix;
 394         rq->mdev         = mdev;
 395         rq->hw_mtu       = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 396         rq->xdpsq        = &c->rq_xdpsq;
 397         rq->stats        = &c->priv->channel_stats[c->ix].rq;
 398         rq->ptp_cyc2time = mlx5_rq_ts_translator(mdev);
 399         err = mlx5e_rq_set_handlers(rq, params, NULL);
 400         if (err)
 401                 return err;
 402
 403         return xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix, 0);
 404 }
 405
 406 static int mlx5e_alloc_rq(struct mlx5e_params *params,
 407                           struct mlx5e_xsk_param *xsk,
 408                           struct mlx5e_rq_param *rqp,
 409                           int node, struct mlx5e_rq *rq)
 410 {
 411         struct page_pool_params pp_params = { 0 };
 412         struct mlx5_core_dev *mdev = rq->mdev;
 413         void *rqc = rqp->rqc;
 414         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 415         u32 pool_size;
 416         int wq_sz;
 417         int err;
 418         int i;
 419
 420         rqp->wq.db_numa_node = node;
 421         INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
 422
 423         if (params->xdp_prog)
 424                 bpf_prog_inc(params->xdp_prog);
 425         RCU_INIT_POINTER(rq->xdp_prog, params->xdp_prog);
 426
 427         rq->buff.map_dir = params->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 428         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
 429         pool_size = 1 << params->log_rq_mtu_frames;
 430
 431         switch (rq->wq_type) {
 432         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 433                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 434                                         &rq->wq_ctrl);
 435                 if (err)
 436                         goto err_rq_xdp_prog;
 437
 438                 err = mlx5e_alloc_mpwqe_rq_drop_page(rq);
 439                 if (err)
 440                         goto err_rq_wq_destroy;
 441
 442                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 443
 444                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 445
 446                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
 447                         mlx5e_mpwqe_get_log_rq_size(params, xsk);
 448
 449                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
 450                 rq->mpwqe.num_strides =
 451                         BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
 452
 453                 rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz);
 454
 455                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 456                 if (err)
 457                         goto err_rq_drop_page;
 458                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 459
 460                 err = mlx5e_rq_alloc_mpwqe_info(rq, node);
 461                 if (err)
 462                         goto err_rq_mkey;
 463                 break;
 464         default: /* MLX5_WQ_TYPE_CYCLIC */
 465                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 466                                          &rq->wq_ctrl);
 467                 if (err)
 468                         goto err_rq_xdp_prog;
 469
 470                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 471
 472                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 473
 474                 rq->wqe.info = rqp->frags_info;
 475                 rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride;
 476
 477                 rq->wqe.frags =
 478                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 479                                         (wq_sz << rq->wqe.info.log_num_frags)),
 480                                       GFP_KERNEL, node);
 481                 if (!rq->wqe.frags) {
 482                         err = -ENOMEM;
 483                         goto err_rq_wq_destroy;
 484                 }
 485
 486                 err = mlx5e_init_di_list(rq, wq_sz, node);
 487                 if (err)
 488                         goto err_rq_frags;
 489
 490                 rq->mkey_be = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey.key);
 491         }
 492
 493         if (xsk) {
 494                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 495                                                  MEM_TYPE_XSK_BUFF_POOL, NULL);
 496                 xsk_pool_set_rxq_info(rq->xsk_pool, &rq->xdp_rxq);
 497         } else {
 498                 /* Create a page_pool and register it with rxq */
 499                 pp_params.order     = 0;
 500                 pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 501                 pp_params.pool_size = pool_size;
 502                 pp_params.nid       = node;
 503                 pp_params.dev       = rq->pdev;
 504                 pp_params.dma_dir   = rq->buff.map_dir;
 505
 506                 /* page_pool can be used even when there is no rq->xdp_prog,
 507                  * given page_pool does not handle DMA mapping there is no
 508                  * required state to clear. And page_pool gracefully handle
 509                  * elevated refcnt.
 510                  */
 511                 rq->page_pool = page_pool_create(&pp_params);
 512                 if (IS_ERR(rq->page_pool)) {
 513                         err = PTR_ERR(rq->page_pool);
 514                         rq->page_pool = NULL;
 515                         goto err_free_by_rq_type;
 516                 }
 517                 if (xdp_rxq_info_is_reg(&rq->xdp_rxq))
 518                         err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 519                                                          MEM_TYPE_PAGE_POOL, rq->page_pool);
 520         }
 521         if (err)
 522                 goto err_free_by_rq_type;
 523
 524         for (i = 0; i < wq_sz; i++) {
 525                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 526                         struct mlx5e_rx_wqe_ll *wqe =
 527                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 528                         u32 byte_count =
 529                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 530                         u64 dma_offset = mlx5e_get_mpwqe_offset(i);
 531
 532                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 533                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 534                         wqe->data[0].lkey = rq->mkey_be;
 535                 } else {
 536                         struct mlx5e_rx_wqe_cyc *wqe =
 537                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 538                         int f;
 539
 540                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 541                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 542                                         MLX5_HW_START_PADDING;
 543
 544                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 545                                 wqe->data[f].lkey = rq->mkey_be;
 546                         }
 547                         /* check if num_frags is not a pow of two */
 548                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 549                                 wqe->data[f].byte_count = 0;
 550                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 551                                 wqe->data[f].addr = 0;
 552                         }
 553                 }
 554         }
 555
 556         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 557
 558         switch (params->rx_cq_moderation.cq_period_mode) {
 559         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 560                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 561                 break;
 562         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 563         default:
 564                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 565         }
 566
 567         rq->page_cache.head = 0;
 568         rq->page_cache.tail = 0;
 569
 570         return 0;
 571
 572 err_free_by_rq_type:
 573         switch (rq->wq_type) {
 574         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 575                 kvfree(rq->mpwqe.info);
 576 err_rq_mkey:
 577                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 578 err_rq_drop_page:
 579                 mlx5e_free_mpwqe_rq_drop_page(rq);
 580                 break;
 581         default: /* MLX5_WQ_TYPE_CYCLIC */
 582                 mlx5e_free_di_list(rq);
 583 err_rq_frags:
 584                 kvfree(rq->wqe.frags);
 585         }
 586 err_rq_wq_destroy:
 587         mlx5_wq_destroy(&rq->wq_ctrl);
 588 err_rq_xdp_prog:
 589         if (params->xdp_prog)
 590                 bpf_prog_put(params->xdp_prog);
 591
 592         return err;
 593 }
 594
 595 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 596 {
 597         struct bpf_prog *old_prog;
 598         int i;
 599
 600         if (xdp_rxq_info_is_reg(&rq->xdp_rxq)) {
 601                 old_prog = rcu_dereference_protected(rq->xdp_prog,
 602                                                      lockdep_is_held(&rq->priv->state_lock));
 603                 if (old_prog)
 604                         bpf_prog_put(old_prog);
 605         }
 606
 607         switch (rq->wq_type) {
 608         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 609                 kvfree(rq->mpwqe.info);
 610                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 611                 mlx5e_free_mpwqe_rq_drop_page(rq);
 612                 break;
 613         default: /* MLX5_WQ_TYPE_CYCLIC */
 614                 kvfree(rq->wqe.frags);
 615                 mlx5e_free_di_list(rq);
 616         }
 617
 618         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 619              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 620                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 621
 622                 /* With AF_XDP, page_cache is not used, so this loop is not
 623                  * entered, and it's safe to call mlx5e_page_release_dynamic
 624                  * directly.
 625                  */
 626                 mlx5e_page_release_dynamic(rq, dma_info, false);
 627         }
 628
 629         xdp_rxq_info_unreg(&rq->xdp_rxq);
 630         page_pool_destroy(rq->page_pool);
 631         mlx5_wq_destroy(&rq->wq_ctrl);
 632 }
 633
 634 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 635 {
 636         struct mlx5_core_dev *mdev = rq->mdev;
 637         u8 ts_format;
 638         void *in;
 639         void *rqc;
 640         void *wq;
 641         int inlen;
 642         int err;
 643
 644         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 645                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 646         in = kvzalloc(inlen, GFP_KERNEL);
 647         if (!in)
 648                 return -ENOMEM;
 649
 650         ts_format = mlx5_is_real_time_rq(mdev) ?
 651                             MLX5_TIMESTAMP_FORMAT_REAL_TIME :
 652                             MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
 653         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 654         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 655
 656         memcpy(rqc, param->rqc, sizeof(param->rqc));
 657
 658         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 659         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 660         MLX5_SET(rqc,  rqc, ts_format,          ts_format);
 661         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 662                                                 MLX5_ADAPTER_PAGE_SHIFT);
 663         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 664
 665         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 666                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 667
 668         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 669
 670         kvfree(in);
 671
 672         return err;
 673 }
 674
 675 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
 676 {
 677         struct mlx5_core_dev *mdev = rq->mdev;
 678
 679         void *in;
 680         void *rqc;
 681         int inlen;
 682         int err;
 683
 684         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 685         in = kvzalloc(inlen, GFP_KERNEL);
 686         if (!in)
 687                 return -ENOMEM;
 688
 689         if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY)
 690                 mlx5e_rqwq_reset(rq);
 691
 692         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 693
 694         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 695         MLX5_SET(rqc, rqc, state, next_state);
 696
 697         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 698
 699         kvfree(in);
 700
 701         return err;
 702 }
 703
 704 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 705 {
 706         struct mlx5_core_dev *mdev = rq->mdev;
 707
 708         void *in;
 709         void *rqc;
 710         int inlen;
 711         int err;
 712
 713         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 714         in = kvzalloc(inlen, GFP_KERNEL);
 715         if (!in)
 716                 return -ENOMEM;
 717
 718         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 719
 720         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 721         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 722                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 723         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 724         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 725
 726         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 727
 728         kvfree(in);
 729
 730         return err;
 731 }
 732
 733 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 734 {
 735         struct mlx5_core_dev *mdev = rq->mdev;
 736         void *in;
 737         void *rqc;
 738         int inlen;
 739         int err;
 740
 741         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 742         in = kvzalloc(inlen, GFP_KERNEL);
 743         if (!in)
 744                 return -ENOMEM;
 745
 746         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 747
 748         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 749         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 750                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 751         MLX5_SET(rqc, rqc, vsd, vsd);
 752         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 753
 754         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 755
 756         kvfree(in);
 757
 758         return err;
 759 }
 760
 761 void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 762 {
 763         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 764 }
 765
 766 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 767 {
 768         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 769
 770         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 771
 772         do {
 773                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 774                         return 0;
 775
 776                 msleep(20);
 777         } while (time_before(jiffies, exp_time));
 778
 779         netdev_warn(rq->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 780                     rq->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 781
 782         mlx5e_reporter_rx_timeout(rq);
 783         return -ETIMEDOUT;
 784 }
 785
 786 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq *rq)
 787 {
 788         struct mlx5_wq_ll *wq;
 789         u16 head;
 790         int i;
 791
 792         if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 793                 return;
 794
 795         wq = &rq->mpwqe.wq;
 796         head = wq->head;
 797
 798         /* Outstanding UMR WQEs (in progress) start at wq->head */
 799         for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
 800                 rq->dealloc_wqe(rq, head);
 801                 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 802         }
 803
 804         rq->mpwqe.actual_wq_head = wq->head;
 805         rq->mpwqe.umr_in_progress = 0;
 806         rq->mpwqe.umr_completed = 0;
 807 }
 808
 809 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 810 {
 811         __be16 wqe_ix_be;
 812         u16 wqe_ix;
 813
 814         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 815                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 816
 817                 mlx5e_free_rx_in_progress_descs(rq);
 818
 819                 while (!mlx5_wq_ll_is_empty(wq)) {
 820                         struct mlx5e_rx_wqe_ll *wqe;
 821
 822                         wqe_ix_be = *wq->tail_next;
 823                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 824                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 825                         rq->dealloc_wqe(rq, wqe_ix);
 826                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 827                                        &wqe->next.next_wqe_index);
 828                 }
 829         } else {
 830                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 831
 832                 while (!mlx5_wq_cyc_is_empty(wq)) {
 833                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
 834                         rq->dealloc_wqe(rq, wqe_ix);
 835                         mlx5_wq_cyc_pop(wq);
 836                 }
 837         }
 838
 839 }
 840
 841 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
 842                   struct mlx5e_xsk_param *xsk, int node,
 843                   struct mlx5e_rq *rq)
 844 {
 845         struct mlx5_core_dev *mdev = rq->mdev;
 846         int err;
 847
 848         err = mlx5e_alloc_rq(params, xsk, param, node, rq);
 849         if (err)
 850                 return err;
 851
 852         err = mlx5e_create_rq(rq, param);
 853         if (err)
 854                 goto err_free_rq;
 855
 856         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 857         if (err)
 858                 goto err_destroy_rq;
 859
 860         if (mlx5e_is_tls_on(rq->priv) && !mlx5e_accel_is_ktls_device(mdev))
 861                 __set_bit(MLX5E_RQ_STATE_FPGA_TLS, &rq->state); /* must be FPGA */
 862
 863         if (MLX5_CAP_ETH(mdev, cqe_checksum_full))
 864                 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state);
 865
 866         if (params->rx_dim_enabled)
 867                 __set_bit(MLX5E_RQ_STATE_AM, &rq->state);
 868
 869         /* We disable csum_complete when XDP is enabled since
 870          * XDP programs might manipulate packets which will render
 871          * skb->checksum incorrect.
 872          */
 873         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || params->xdp_prog)
 874                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state);
 875
 876         /* For CQE compression on striding RQ, use stride index provided by
 877          * HW if capability is supported.
 878          */
 879         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) &&
 880             MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index))
 881                 __set_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &rq->state);
 882
 883         return 0;
 884
 885 err_destroy_rq:
 886         mlx5e_destroy_rq(rq);
 887 err_free_rq:
 888         mlx5e_free_rq(rq);
 889
 890         return err;
 891 }
 892
 893 void mlx5e_activate_rq(struct mlx5e_rq *rq)
 894 {
 895         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 896         if (rq->icosq) {
 897                 mlx5e_trigger_irq(rq->icosq);
 898         } else {
 899                 local_bh_disable();
 900                 napi_schedule(rq->cq.napi);
 901                 local_bh_enable();
 902         }
 903 }
 904
 905 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 906 {
 907         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 908         synchronize_net(); /* Sync with NAPI to prevent mlx5e_post_rx_wqes. */
 909 }
 910
 911 void mlx5e_close_rq(struct mlx5e_rq *rq)
 912 {
 913         cancel_work_sync(&rq->dim.work);
 914         if (rq->icosq)
 915                 cancel_work_sync(&rq->icosq->recover_work);
 916         cancel_work_sync(&rq->recover_work);
 917         mlx5e_destroy_rq(rq);
 918         mlx5e_free_rx_descs(rq);
 919         mlx5e_free_rq(rq);
 920 }
 921
 922 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 923 {
 924         kvfree(sq->db.xdpi_fifo.xi);
 925         kvfree(sq->db.wqe_info);
 926 }
 927
 928 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
 929 {
 930         struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
 931         int wq_sz        = mlx5_wq_cyc_get_size(&sq->wq);
 932         int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 933
 934         xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq,
 935                                       GFP_KERNEL, numa);
 936         if (!xdpi_fifo->xi)
 937                 return -ENOMEM;
 938
 939         xdpi_fifo->pc   = &sq->xdpi_fifo_pc;
 940         xdpi_fifo->cc   = &sq->xdpi_fifo_cc;
 941         xdpi_fifo->mask = dsegs_per_wq - 1;
 942
 943         return 0;
 944 }
 945
 946 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 947 {
 948         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 949         int err;
 950
 951         sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz,
 952                                         GFP_KERNEL, numa);
 953         if (!sq->db.wqe_info)
 954                 return -ENOMEM;
 955
 956         err = mlx5e_alloc_xdpsq_fifo(sq, numa);
 957         if (err) {
 958                 mlx5e_free_xdpsq_db(sq);
 959                 return err;
 960         }
 961
 962         return 0;
 963 }
 964
 965 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 966                              struct mlx5e_params *params,
 967                              struct xsk_buff_pool *xsk_pool,
 968                              struct mlx5e_sq_param *param,
 969                              struct mlx5e_xdpsq *sq,
 970                              bool is_redirect)
 971 {
 972         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 973         struct mlx5_core_dev *mdev = c->mdev;
 974         struct mlx5_wq_cyc *wq = &sq->wq;
 975         int err;
 976
 977         sq->pdev      = c->pdev;
 978         sq->mkey_be   = c->mkey_be;
 979         sq->channel   = c;
 980         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
 981         sq->min_inline_mode = params->tx_min_inline_mode;
 982         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 983         sq->xsk_pool  = xsk_pool;
 984
 985         sq->stats = sq->xsk_pool ?
 986                 &c->priv->channel_stats[c->ix].xsksq :
 987                 is_redirect ?
 988                         &c->priv->channel_stats[c->ix].xdpsq :
 989                         &c->priv->channel_stats[c->ix].rq_xdpsq;
 990
 991         param->wq.db_numa_node = cpu_to_node(c->cpu);
 992         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
 993         if (err)
 994                 return err;
 995         wq->db = &wq->db[MLX5_SND_DBR];
 996
 997         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
 998         if (err)
 999                 goto err_sq_wq_destroy;
1000
1001         return 0;
1002
1003 err_sq_wq_destroy:
1004         mlx5_wq_destroy(&sq->wq_ctrl);
1005
1006         return err;
1007 }
1008
1009 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1010 {
1011         mlx5e_free_xdpsq_db(sq);
1012         mlx5_wq_destroy(&sq->wq_ctrl);
1013 }
1014
1015 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1016 {
1017         kvfree(sq->db.wqe_info);
1018 }
1019
1020 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1021 {
1022         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1023         size_t size;
1024
1025         size = array_size(wq_sz, sizeof(*sq->db.wqe_info));
1026         sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1027         if (!sq->db.wqe_info)
1028                 return -ENOMEM;
1029
1030         return 0;
1031 }
1032
1033 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1034 {
1035         struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1036                                               recover_work);
1037
1038         mlx5e_reporter_icosq_cqe_err(sq);
1039 }
1040
1041 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1042                              struct mlx5e_sq_param *param,
1043                              struct mlx5e_icosq *sq)
1044 {
1045         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1046         struct mlx5_core_dev *mdev = c->mdev;
1047         struct mlx5_wq_cyc *wq = &sq->wq;
1048         int err;
1049
1050         sq->channel   = c;
1051         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1052         sq->reserved_room = param->stop_room;
1053
1054         param->wq.db_numa_node = cpu_to_node(c->cpu);
1055         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1056         if (err)
1057                 return err;
1058         wq->db = &wq->db[MLX5_SND_DBR];
1059
1060         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1061         if (err)
1062                 goto err_sq_wq_destroy;
1063
1064         INIT_WORK(&sq->recover_work, mlx5e_icosq_err_cqe_work);
1065
1066         return 0;
1067
1068 err_sq_wq_destroy:
1069         mlx5_wq_destroy(&sq->wq_ctrl);
1070
1071         return err;
1072 }
1073
1074 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1075 {
1076         mlx5e_free_icosq_db(sq);
1077         mlx5_wq_destroy(&sq->wq_ctrl);
1078 }
1079
1080 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1081 {
1082         kvfree(sq->db.wqe_info);
1083         kvfree(sq->db.skb_fifo.fifo);
1084         kvfree(sq->db.dma_fifo);
1085 }
1086
1087 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1088 {
1089         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1090         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1091
1092         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1093                                                    sizeof(*sq->db.dma_fifo)),
1094                                         GFP_KERNEL, numa);
1095         sq->db.skb_fifo.fifo = kvzalloc_node(array_size(df_sz,
1096                                                         sizeof(*sq->db.skb_fifo.fifo)),
1097                                         GFP_KERNEL, numa);
1098         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1099                                                    sizeof(*sq->db.wqe_info)),
1100                                         GFP_KERNEL, numa);
1101         if (!sq->db.dma_fifo || !sq->db.skb_fifo.fifo || !sq->db.wqe_info) {
1102                 mlx5e_free_txqsq_db(sq);
1103                 return -ENOMEM;
1104         }
1105
1106         sq->dma_fifo_mask = df_sz - 1;
1107
1108         sq->db.skb_fifo.pc   = &sq->skb_fifo_pc;
1109         sq->db.skb_fifo.cc   = &sq->skb_fifo_cc;
1110         sq->db.skb_fifo.mask = df_sz - 1;
1111
1112         return 0;
1113 }
1114
1115 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1116                              int txq_ix,
1117                              struct mlx5e_params *params,
1118                              struct mlx5e_sq_param *param,
1119                              struct mlx5e_txqsq *sq,
1120                              int tc)
1121 {
1122         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1123         struct mlx5_core_dev *mdev = c->mdev;
1124         struct mlx5_wq_cyc *wq = &sq->wq;
1125         int err;
1126
1127         sq->pdev      = c->pdev;
1128         sq->tstamp    = c->tstamp;
1129         sq->clock     = &mdev->clock;
1130         sq->mkey_be   = c->mkey_be;
1131         sq->netdev    = c->netdev;
1132         sq->mdev      = c->mdev;
1133         sq->priv      = c->priv;
1134         sq->ch_ix     = c->ix;
1135         sq->txq_ix    = txq_ix;
1136         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1137         sq->min_inline_mode = params->tx_min_inline_mode;
1138         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1139         INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1140         if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1141                 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1142         if (MLX5_IPSEC_DEV(c->priv->mdev))
1143                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1144         if (param->is_mpw)
1145                 set_bit(MLX5E_SQ_STATE_MPWQE, &sq->state);
1146         sq->stop_room = param->stop_room;
1147         sq->ptp_cyc2time = mlx5_sq_ts_translator(mdev);
1148
1149         param->wq.db_numa_node = cpu_to_node(c->cpu);
1150         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1151         if (err)
1152                 return err;
1153         wq->db    = &wq->db[MLX5_SND_DBR];
1154
1155         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1156         if (err)
1157                 goto err_sq_wq_destroy;
1158
1159         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1160         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1161
1162         return 0;
1163
1164 err_sq_wq_destroy:
1165         mlx5_wq_destroy(&sq->wq_ctrl);
1166
1167         return err;
1168 }
1169
1170 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1171 {
1172         mlx5e_free_txqsq_db(sq);
1173         mlx5_wq_destroy(&sq->wq_ctrl);
1174 }
1175
1176 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1177                            struct mlx5e_sq_param *param,
1178                            struct mlx5e_create_sq_param *csp,
1179                            u32 *sqn)
1180 {
1181         u8 ts_format;
1182         void *in;
1183         void *sqc;
1184         void *wq;
1185         int inlen;
1186         int err;
1187
1188         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1189                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1190         in = kvzalloc(inlen, GFP_KERNEL);
1191         if (!in)
1192                 return -ENOMEM;
1193
1194         ts_format = mlx5_is_real_time_sq(mdev) ?
1195                             MLX5_TIMESTAMP_FORMAT_REAL_TIME :
1196                             MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
1197         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1198         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1199
1200         memcpy(sqc, param->sqc, sizeof(param->sqc));
1201         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1202         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1203         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1204         MLX5_SET(sqc,  sqc, ts_cqe_to_dest_cqn, csp->ts_cqe_to_dest_cqn);
1205         MLX5_SET(sqc,  sqc, ts_format, ts_format);
1206
1207
1208         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1209                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1210
1211         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1212         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1213
1214         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1215         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.hw_objs.bfreg.index);
1216         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1217                                           MLX5_ADAPTER_PAGE_SHIFT);
1218         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1219
1220         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1221                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1222
1223         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1224
1225         kvfree(in);
1226
1227         return err;
1228 }
1229
1230 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1231                     struct mlx5e_modify_sq_param *p)
1232 {
1233         u64 bitmask = 0;
1234         void *in;
1235         void *sqc;
1236         int inlen;
1237         int err;
1238
1239         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1240         in = kvzalloc(inlen, GFP_KERNEL);
1241         if (!in)
1242                 return -ENOMEM;
1243
1244         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1245
1246         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1247         MLX5_SET(sqc, sqc, state, p->next_state);
1248         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1249                 bitmask |= 1;
1250                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1251         }
1252         if (p->qos_update && p->next_state == MLX5_SQC_STATE_RDY) {
1253                 bitmask |= 1 << 2;
1254                 MLX5_SET(sqc, sqc, qos_queue_group_id, p->qos_queue_group_id);
1255         }
1256         MLX5_SET64(modify_sq_in, in, modify_bitmask, bitmask);
1257
1258         err = mlx5_core_modify_sq(mdev, sqn, in);
1259
1260         kvfree(in);
1261
1262         return err;
1263 }
1264
1265 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1266 {
1267         mlx5_core_destroy_sq(mdev, sqn);
1268 }
1269
1270 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1271                         struct mlx5e_sq_param *param,
1272                         struct mlx5e_create_sq_param *csp,
1273                         u16 qos_queue_group_id,
1274                         u32 *sqn)
1275 {
1276         struct mlx5e_modify_sq_param msp = {0};
1277         int err;
1278
1279         err = mlx5e_create_sq(mdev, param, csp, sqn);
1280         if (err)
1281                 return err;
1282
1283         msp.curr_state = MLX5_SQC_STATE_RST;
1284         msp.next_state = MLX5_SQC_STATE_RDY;
1285         if (qos_queue_group_id) {
1286                 msp.qos_update = true;
1287                 msp.qos_queue_group_id = qos_queue_group_id;
1288         }
1289         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1290         if (err)
1291                 mlx5e_destroy_sq(mdev, *sqn);
1292
1293         return err;
1294 }
1295
1296 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1297                                 struct mlx5e_txqsq *sq, u32 rate);
1298
1299 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1300                      struct mlx5e_params *params, struct mlx5e_sq_param *param,
1301                      struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id, u16 qos_qid)
1302 {
1303         struct mlx5e_create_sq_param csp = {};
1304         u32 tx_rate;
1305         int err;
1306
1307         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1308         if (err)
1309                 return err;
1310
1311         if (qos_queue_group_id)
1312                 sq->stats = c->priv->htb.qos_sq_stats[qos_qid];
1313         else
1314                 sq->stats = &c->priv->channel_stats[c->ix].sq[tc];
1315
1316         csp.tisn            = tisn;
1317         csp.tis_lst_sz      = 1;
1318         csp.cqn             = sq->cq.mcq.cqn;
1319         csp.wq_ctrl         = &sq->wq_ctrl;
1320         csp.min_inline_mode = sq->min_inline_mode;
1321         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, qos_queue_group_id, &sq->sqn);
1322         if (err)
1323                 goto err_free_txqsq;
1324
1325         tx_rate = c->priv->tx_rates[sq->txq_ix];
1326         if (tx_rate)
1327                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1328
1329         if (params->tx_dim_enabled)
1330                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1331
1332         return 0;
1333
1334 err_free_txqsq:
1335         mlx5e_free_txqsq(sq);
1336
1337         return err;
1338 }
1339
1340 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1341 {
1342         sq->txq = netdev_get_tx_queue(sq->netdev, sq->txq_ix);
1343         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1344         netdev_tx_reset_queue(sq->txq);
1345         netif_tx_start_queue(sq->txq);
1346 }
1347
1348 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1349 {
1350         __netif_tx_lock_bh(txq);
1351         netif_tx_stop_queue(txq);
1352         __netif_tx_unlock_bh(txq);
1353 }
1354
1355 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1356 {
1357         struct mlx5_wq_cyc *wq = &sq->wq;
1358
1359         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1360         synchronize_net(); /* Sync with NAPI to prevent netif_tx_wake_queue. */
1361
1362         mlx5e_tx_disable_queue(sq->txq);
1363
1364         /* last doorbell out, godspeed .. */
1365         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1366                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1367                 struct mlx5e_tx_wqe *nop;
1368
1369                 sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) {
1370                         .num_wqebbs = 1,
1371                 };
1372
1373                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1374                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1375         }
1376 }
1377
1378 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1379 {
1380         struct mlx5_core_dev *mdev = sq->mdev;
1381         struct mlx5_rate_limit rl = {0};
1382
1383         cancel_work_sync(&sq->dim.work);
1384         cancel_work_sync(&sq->recover_work);
1385         mlx5e_destroy_sq(mdev, sq->sqn);
1386         if (sq->rate_limit) {
1387                 rl.rate = sq->rate_limit;
1388                 mlx5_rl_remove_rate(mdev, &rl);
1389         }
1390         mlx5e_free_txqsq_descs(sq);
1391         mlx5e_free_txqsq(sq);
1392 }
1393
1394 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1395 {
1396         struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1397                                               recover_work);
1398
1399         mlx5e_reporter_tx_err_cqe(sq);
1400 }
1401
1402 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1403                      struct mlx5e_sq_param *param, struct mlx5e_icosq *sq)
1404 {
1405         struct mlx5e_create_sq_param csp = {};
1406         int err;
1407
1408         err = mlx5e_alloc_icosq(c, param, sq);
1409         if (err)
1410                 return err;
1411
1412         csp.cqn             = sq->cq.mcq.cqn;
1413         csp.wq_ctrl         = &sq->wq_ctrl;
1414         csp.min_inline_mode = params->tx_min_inline_mode;
1415         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1416         if (err)
1417                 goto err_free_icosq;
1418
1419         if (param->is_tls) {
1420                 sq->ktls_resync = mlx5e_ktls_rx_resync_create_resp_list();
1421                 if (IS_ERR(sq->ktls_resync)) {
1422                         err = PTR_ERR(sq->ktls_resync);
1423                         goto err_destroy_icosq;
1424                 }
1425         }
1426         return 0;
1427
1428 err_destroy_icosq:
1429         mlx5e_destroy_sq(c->mdev, sq->sqn);
1430 err_free_icosq:
1431         mlx5e_free_icosq(sq);
1432
1433         return err;
1434 }
1435
1436 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1437 {
1438         set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1439 }
1440
1441 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1442 {
1443         clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1444         synchronize_net(); /* Sync with NAPI. */
1445 }
1446
1447 void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1448 {
1449         struct mlx5e_channel *c = sq->channel;
1450
1451         if (sq->ktls_resync)
1452                 mlx5e_ktls_rx_resync_destroy_resp_list(sq->ktls_resync);
1453         mlx5e_destroy_sq(c->mdev, sq->sqn);
1454         mlx5e_free_icosq_descs(sq);
1455         mlx5e_free_icosq(sq);
1456 }
1457
1458 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1459                      struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1460                      struct mlx5e_xdpsq *sq, bool is_redirect)
1461 {
1462         struct mlx5e_create_sq_param csp = {};
1463         int err;
1464
1465         err = mlx5e_alloc_xdpsq(c, params, xsk_pool, param, sq, is_redirect);
1466         if (err)
1467                 return err;
1468
1469         csp.tis_lst_sz      = 1;
1470         csp.tisn            = c->priv->tisn[c->lag_port][0]; /* tc = 0 */
1471         csp.cqn             = sq->cq.mcq.cqn;
1472         csp.wq_ctrl         = &sq->wq_ctrl;
1473         csp.min_inline_mode = sq->min_inline_mode;
1474         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1475         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1476         if (err)
1477                 goto err_free_xdpsq;
1478
1479         mlx5e_set_xmit_fp(sq, param->is_mpw);
1480
1481         if (!param->is_mpw) {
1482                 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1483                 unsigned int inline_hdr_sz = 0;
1484                 int i;
1485
1486                 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1487                         inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1488                         ds_cnt++;
1489                 }
1490
1491                 /* Pre initialize fixed WQE fields */
1492                 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1493                         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1494                         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1495                         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1496                         struct mlx5_wqe_data_seg *dseg;
1497
1498                         sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) {
1499                                 .num_wqebbs = 1,
1500                                 .num_pkts   = 1,
1501                         };
1502
1503                         cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1504                         eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1505
1506                         dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1507                         dseg->lkey = sq->mkey_be;
1508                 }
1509         }
1510
1511         return 0;
1512
1513 err_free_xdpsq:
1514         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1515         mlx5e_free_xdpsq(sq);
1516
1517         return err;
1518 }
1519
1520 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1521 {
1522         struct mlx5e_channel *c = sq->channel;
1523
1524         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1525         synchronize_net(); /* Sync with NAPI. */
1526
1527         mlx5e_destroy_sq(c->mdev, sq->sqn);
1528         mlx5e_free_xdpsq_descs(sq);
1529         mlx5e_free_xdpsq(sq);
1530 }
1531
1532 static int mlx5e_alloc_cq_common(struct mlx5e_priv *priv,
1533                                  struct mlx5e_cq_param *param,
1534                                  struct mlx5e_cq *cq)
1535 {
1536         struct mlx5_core_dev *mdev = priv->mdev;
1537         struct mlx5_core_cq *mcq = &cq->mcq;
1538         int err;
1539         u32 i;
1540
1541         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1542                                &cq->wq_ctrl);
1543         if (err)
1544                 return err;
1545
1546         mcq->cqe_sz     = 64;
1547         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1548         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1549         *mcq->set_ci_db = 0;
1550         *mcq->arm_db    = 0;
1551         mcq->vector     = param->eq_ix;
1552         mcq->comp       = mlx5e_completion_event;
1553         mcq->event      = mlx5e_cq_error_event;
1554
1555         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1556                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1557
1558                 cqe->op_own = 0xf1;
1559         }
1560
1561         cq->mdev = mdev;
1562         cq->netdev = priv->netdev;
1563         cq->priv = priv;
1564
1565         return 0;
1566 }
1567
1568 static int mlx5e_alloc_cq(struct mlx5e_priv *priv,
1569                           struct mlx5e_cq_param *param,
1570                           struct mlx5e_create_cq_param *ccp,
1571                           struct mlx5e_cq *cq)
1572 {
1573         int err;
1574
1575         param->wq.buf_numa_node = ccp->node;
1576         param->wq.db_numa_node  = ccp->node;
1577         param->eq_ix            = ccp->ix;
1578
1579         err = mlx5e_alloc_cq_common(priv, param, cq);
1580
1581         cq->napi     = ccp->napi;
1582         cq->ch_stats = ccp->ch_stats;
1583
1584         return err;
1585 }
1586
1587 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1588 {
1589         mlx5_wq_destroy(&cq->wq_ctrl);
1590 }
1591
1592 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1593 {
1594         u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1595         struct mlx5_core_dev *mdev = cq->mdev;
1596         struct mlx5_core_cq *mcq = &cq->mcq;
1597
1598         void *in;
1599         void *cqc;
1600         int inlen;
1601         int eqn;
1602         int err;
1603
1604         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn);
1605         if (err)
1606                 return err;
1607
1608         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1609                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1610         in = kvzalloc(inlen, GFP_KERNEL);
1611         if (!in)
1612                 return -ENOMEM;
1613
1614         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1615
1616         memcpy(cqc, param->cqc, sizeof(param->cqc));
1617
1618         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1619                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1620
1621         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1622         MLX5_SET(cqc,   cqc, c_eqn_or_apu_element, eqn);
1623         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1624         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1625                                             MLX5_ADAPTER_PAGE_SHIFT);
1626         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1627
1628         err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1629
1630         kvfree(in);
1631
1632         if (err)
1633                 return err;
1634
1635         mlx5e_cq_arm(cq);
1636
1637         return 0;
1638 }
1639
1640 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1641 {
1642         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1643 }
1644
1645 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,
1646                   struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
1647                   struct mlx5e_cq *cq)
1648 {
1649         struct mlx5_core_dev *mdev = priv->mdev;
1650         int err;
1651
1652         err = mlx5e_alloc_cq(priv, param, ccp, cq);
1653         if (err)
1654                 return err;
1655
1656         err = mlx5e_create_cq(cq, param);
1657         if (err)
1658                 goto err_free_cq;
1659
1660         if (MLX5_CAP_GEN(mdev, cq_moderation))
1661                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1662         return 0;
1663
1664 err_free_cq:
1665         mlx5e_free_cq(cq);
1666
1667         return err;
1668 }
1669
1670 void mlx5e_close_cq(struct mlx5e_cq *cq)
1671 {
1672         mlx5e_destroy_cq(cq);
1673         mlx5e_free_cq(cq);
1674 }
1675
1676 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1677                              struct mlx5e_params *params,
1678                              struct mlx5e_create_cq_param *ccp,
1679                              struct mlx5e_channel_param *cparam)
1680 {
1681         int err;
1682         int tc;
1683
1684         for (tc = 0; tc < c->num_tc; tc++) {
1685                 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->txq_sq.cqp,
1686                                     ccp, &c->sq[tc].cq);
1687                 if (err)
1688                         goto err_close_tx_cqs;
1689         }
1690
1691         return 0;
1692
1693 err_close_tx_cqs:
1694         for (tc--; tc >= 0; tc--)
1695                 mlx5e_close_cq(&c->sq[tc].cq);
1696
1697         return err;
1698 }
1699
1700 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1701 {
1702         int tc;
1703
1704         for (tc = 0; tc < c->num_tc; tc++)
1705                 mlx5e_close_cq(&c->sq[tc].cq);
1706 }
1707
1708 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1709                           struct mlx5e_params *params,
1710                           struct mlx5e_channel_param *cparam)
1711 {
1712         int err, tc;
1713
1714         for (tc = 0; tc < mlx5e_get_dcb_num_tc(params); tc++) {
1715                 int txq_ix = c->ix + tc * params->num_channels;
1716
1717                 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
1718                                        params, &cparam->txq_sq, &c->sq[tc], tc, 0, 0);
1719                 if (err)
1720                         goto err_close_sqs;
1721         }
1722
1723         return 0;
1724
1725 err_close_sqs:
1726         for (tc--; tc >= 0; tc--)
1727                 mlx5e_close_txqsq(&c->sq[tc]);
1728
1729         return err;
1730 }
1731
1732 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1733 {
1734         int tc;
1735
1736         for (tc = 0; tc < c->num_tc; tc++)
1737                 mlx5e_close_txqsq(&c->sq[tc]);
1738 }
1739
1740 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1741                                 struct mlx5e_txqsq *sq, u32 rate)
1742 {
1743         struct mlx5e_priv *priv = netdev_priv(dev);
1744         struct mlx5_core_dev *mdev = priv->mdev;
1745         struct mlx5e_modify_sq_param msp = {0};
1746         struct mlx5_rate_limit rl = {0};
1747         u16 rl_index = 0;
1748         int err;
1749
1750         if (rate == sq->rate_limit)
1751                 /* nothing to do */
1752                 return 0;
1753
1754         if (sq->rate_limit) {
1755                 rl.rate = sq->rate_limit;
1756                 /* remove current rl index to free space to next ones */
1757                 mlx5_rl_remove_rate(mdev, &rl);
1758         }
1759
1760         sq->rate_limit = 0;
1761
1762         if (rate) {
1763                 rl.rate = rate;
1764                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1765                 if (err) {
1766                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1767                                    rate, err);
1768                         return err;
1769                 }
1770         }
1771
1772         msp.curr_state = MLX5_SQC_STATE_RDY;
1773         msp.next_state = MLX5_SQC_STATE_RDY;
1774         msp.rl_index   = rl_index;
1775         msp.rl_update  = true;
1776         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1777         if (err) {
1778                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1779                            rate, err);
1780                 /* remove the rate from the table */
1781                 if (rate)
1782                         mlx5_rl_remove_rate(mdev, &rl);
1783                 return err;
1784         }
1785
1786         sq->rate_limit = rate;
1787         return 0;
1788 }
1789
1790 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1791 {
1792         struct mlx5e_priv *priv = netdev_priv(dev);
1793         struct mlx5_core_dev *mdev = priv->mdev;
1794         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1795         int err = 0;
1796
1797         if (!mlx5_rl_is_supported(mdev)) {
1798                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1799                 return -EINVAL;
1800         }
1801
1802         /* rate is given in Mb/sec, HW config is in Kb/sec */
1803         rate = rate << 10;
1804
1805         /* Check whether rate in valid range, 0 is always valid */
1806         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1807                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1808                 return -ERANGE;
1809         }
1810
1811         mutex_lock(&priv->state_lock);
1812         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1813                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1814         if (!err)
1815                 priv->tx_rates[index] = rate;
1816         mutex_unlock(&priv->state_lock);
1817
1818         return err;
1819 }
1820
1821 static int mlx5e_open_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
1822                              struct mlx5e_rq_param *rq_params)
1823 {
1824         int err;
1825
1826         err = mlx5e_init_rxq_rq(c, params, &c->rq);
1827         if (err)
1828                 return err;
1829
1830         return mlx5e_open_rq(params, rq_params, NULL, cpu_to_node(c->cpu), &c->rq);
1831 }
1832
1833 static int mlx5e_open_queues(struct mlx5e_channel *c,
1834                              struct mlx5e_params *params,
1835                              struct mlx5e_channel_param *cparam)
1836 {
1837         struct dim_cq_moder icocq_moder = {0, 0};
1838         struct mlx5e_create_cq_param ccp;
1839         int err;
1840
1841         mlx5e_build_create_cq_param(&ccp, c);
1842
1843         err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->async_icosq.cqp, &ccp,
1844                             &c->async_icosq.cq);
1845         if (err)
1846                 return err;
1847
1848         err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->icosq.cqp, &ccp,
1849                             &c->icosq.cq);
1850         if (err)
1851                 goto err_close_async_icosq_cq;
1852
1853         err = mlx5e_open_tx_cqs(c, params, &ccp, cparam);
1854         if (err)
1855                 goto err_close_icosq_cq;
1856
1857         err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp, &ccp,
1858                             &c->xdpsq.cq);
1859         if (err)
1860                 goto err_close_tx_cqs;
1861
1862         err = mlx5e_open_cq(c->priv, params->rx_cq_moderation, &cparam->rq.cqp, &ccp,
1863                             &c->rq.cq);
1864         if (err)
1865                 goto err_close_xdp_tx_cqs;
1866
1867         err = c->xdp ? mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp,
1868                                      &ccp, &c->rq_xdpsq.cq) : 0;
1869         if (err)
1870                 goto err_close_rx_cq;
1871
1872         spin_lock_init(&c->async_icosq_lock);
1873
1874         err = mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq);
1875         if (err)
1876                 goto err_close_xdpsq_cq;
1877
1878         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1879         if (err)
1880                 goto err_close_async_icosq;
1881
1882         err = mlx5e_open_sqs(c, params, cparam);
1883         if (err)
1884                 goto err_close_icosq;
1885
1886         err = mlx5e_open_rxq_rq(c, params, &cparam->rq);
1887         if (err)
1888                 goto err_close_sqs;
1889
1890         if (c->xdp) {
1891                 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
1892                                        &c->rq_xdpsq, false);
1893                 if (err)
1894                         goto err_close_rq;
1895         }
1896
1897         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
1898         if (err)
1899                 goto err_close_xdp_sq;
1900
1901         return 0;
1902
1903 err_close_xdp_sq:
1904         if (c->xdp)
1905                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1906
1907 err_close_rq:
1908         mlx5e_close_rq(&c->rq);
1909
1910 err_close_sqs:
1911         mlx5e_close_sqs(c);
1912
1913 err_close_icosq:
1914         mlx5e_close_icosq(&c->icosq);
1915
1916 err_close_async_icosq:
1917         mlx5e_close_icosq(&c->async_icosq);
1918
1919 err_close_xdpsq_cq:
1920         if (c->xdp)
1921                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1922
1923 err_close_rx_cq:
1924         mlx5e_close_cq(&c->rq.cq);
1925
1926 err_close_xdp_tx_cqs:
1927         mlx5e_close_cq(&c->xdpsq.cq);
1928
1929 err_close_tx_cqs:
1930         mlx5e_close_tx_cqs(c);
1931
1932 err_close_icosq_cq:
1933         mlx5e_close_cq(&c->icosq.cq);
1934
1935 err_close_async_icosq_cq:
1936         mlx5e_close_cq(&c->async_icosq.cq);
1937
1938         return err;
1939 }
1940
1941 static void mlx5e_close_queues(struct mlx5e_channel *c)
1942 {
1943         mlx5e_close_xdpsq(&c->xdpsq);
1944         if (c->xdp)
1945                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1946         mlx5e_close_rq(&c->rq);
1947         mlx5e_close_sqs(c);
1948         mlx5e_close_icosq(&c->icosq);
1949         mlx5e_close_icosq(&c->async_icosq);
1950         if (c->xdp)
1951                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1952         mlx5e_close_cq(&c->rq.cq);
1953         mlx5e_close_cq(&c->xdpsq.cq);
1954         mlx5e_close_tx_cqs(c);
1955         mlx5e_close_cq(&c->icosq.cq);
1956         mlx5e_close_cq(&c->async_icosq.cq);
1957 }
1958
1959 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
1960 {
1961         u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
1962
1963         return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
1964 }
1965
1966 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1967                               struct mlx5e_params *params,
1968                               struct mlx5e_channel_param *cparam,
1969                               struct xsk_buff_pool *xsk_pool,
1970                               struct mlx5e_channel **cp)
1971 {
1972         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1973         struct net_device *netdev = priv->netdev;
1974         struct mlx5e_xsk_param xsk;
1975         struct mlx5e_channel *c;
1976         unsigned int irq;
1977         int err;
1978
1979         err = mlx5_vector2irqn(priv->mdev, ix, &irq);
1980         if (err)
1981                 return err;
1982
1983         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1984         if (!c)
1985                 return -ENOMEM;
1986
1987         c->priv     = priv;
1988         c->mdev     = priv->mdev;
1989         c->tstamp   = &priv->tstamp;
1990         c->ix       = ix;
1991         c->cpu      = cpu;
1992         c->pdev     = mlx5_core_dma_dev(priv->mdev);
1993         c->netdev   = priv->netdev;
1994         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.hw_objs.mkey.key);
1995         c->num_tc   = mlx5e_get_dcb_num_tc(params);
1996         c->xdp      = !!params->xdp_prog;
1997         c->stats    = &priv->channel_stats[ix].ch;
1998         c->aff_mask = irq_get_effective_affinity_mask(irq);
1999         c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
2000
2001         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
2002
2003         err = mlx5e_open_queues(c, params, cparam);
2004         if (unlikely(err))
2005                 goto err_napi_del;
2006
2007         if (xsk_pool) {
2008                 mlx5e_build_xsk_param(xsk_pool, &xsk);
2009                 err = mlx5e_open_xsk(priv, params, &xsk, xsk_pool, c);
2010                 if (unlikely(err))
2011                         goto err_close_queues;
2012         }
2013
2014         *cp = c;
2015
2016         return 0;
2017
2018 err_close_queues:
2019         mlx5e_close_queues(c);
2020
2021 err_napi_del:
2022         netif_napi_del(&c->napi);
2023
2024         kvfree(c);
2025
2026         return err;
2027 }
2028
2029 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2030 {
2031         int tc;
2032
2033         napi_enable(&c->napi);
2034
2035         for (tc = 0; tc < c->num_tc; tc++)
2036                 mlx5e_activate_txqsq(&c->sq[tc]);
2037         mlx5e_activate_icosq(&c->icosq);
2038         mlx5e_activate_icosq(&c->async_icosq);
2039         mlx5e_activate_rq(&c->rq);
2040
2041         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2042                 mlx5e_activate_xsk(c);
2043 }
2044
2045 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2046 {
2047         int tc;
2048
2049         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2050                 mlx5e_deactivate_xsk(c);
2051
2052         mlx5e_deactivate_rq(&c->rq);
2053         mlx5e_deactivate_icosq(&c->async_icosq);
2054         mlx5e_deactivate_icosq(&c->icosq);
2055         for (tc = 0; tc < c->num_tc; tc++)
2056                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2057         mlx5e_qos_deactivate_queues(c);
2058
2059         napi_disable(&c->napi);
2060 }
2061
2062 static void mlx5e_close_channel(struct mlx5e_channel *c)
2063 {
2064         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2065                 mlx5e_close_xsk(c);
2066         mlx5e_close_queues(c);
2067         mlx5e_qos_close_queues(c);
2068         netif_napi_del(&c->napi);
2069
2070         kvfree(c);
2071 }
2072
2073 int mlx5e_open_channels(struct mlx5e_priv *priv,
2074                         struct mlx5e_channels *chs)
2075 {
2076         struct mlx5e_channel_param *cparam;
2077         int err = -ENOMEM;
2078         int i;
2079
2080         chs->num = chs->params.num_channels;
2081
2082         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2083         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2084         if (!chs->c || !cparam)
2085                 goto err_free;
2086
2087         err = mlx5e_build_channel_param(priv->mdev, &chs->params, priv->q_counter, cparam);
2088         if (err)
2089                 goto err_free;
2090
2091         for (i = 0; i < chs->num; i++) {
2092                 struct xsk_buff_pool *xsk_pool = NULL;
2093
2094                 if (chs->params.xdp_prog)
2095                         xsk_pool = mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, i);
2096
2097                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, xsk_pool, &chs->c[i]);
2098                 if (err)
2099                         goto err_close_channels;
2100         }
2101
2102         if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS) || chs->params.ptp_rx) {
2103                 err = mlx5e_ptp_open(priv, &chs->params, chs->c[0]->lag_port, &chs->ptp);
2104                 if (err)
2105                         goto err_close_channels;
2106         }
2107
2108         err = mlx5e_qos_open_queues(priv, chs);
2109         if (err)
2110                 goto err_close_ptp;
2111
2112         mlx5e_health_channels_update(priv);
2113         kvfree(cparam);
2114         return 0;
2115
2116 err_close_ptp:
2117         if (chs->ptp)
2118                 mlx5e_ptp_close(chs->ptp);
2119
2120 err_close_channels:
2121         for (i--; i >= 0; i--)
2122                 mlx5e_close_channel(chs->c[i]);
2123
2124 err_free:
2125         kfree(chs->c);
2126         kvfree(cparam);
2127         chs->num = 0;
2128         return err;
2129 }
2130
2131 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2132 {
2133         int i;
2134
2135         for (i = 0; i < chs->num; i++)
2136                 mlx5e_activate_channel(chs->c[i]);
2137
2138         if (chs->ptp)
2139                 mlx5e_ptp_activate_channel(chs->ptp);
2140 }
2141
2142 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2143
2144 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2145 {
2146         int err = 0;
2147         int i;
2148
2149         for (i = 0; i < chs->num; i++) {
2150                 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2151
2152                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2153
2154                 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2155                  * doesn't provide any Fill Ring entries at the setup stage.
2156                  */
2157         }
2158
2159         return err ? -ETIMEDOUT : 0;
2160 }
2161
2162 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2163 {
2164         int i;
2165
2166         if (chs->ptp)
2167                 mlx5e_ptp_deactivate_channel(chs->ptp);
2168
2169         for (i = 0; i < chs->num; i++)
2170                 mlx5e_deactivate_channel(chs->c[i]);
2171 }
2172
2173 void mlx5e_close_channels(struct mlx5e_channels *chs)
2174 {
2175         int i;
2176
2177         if (chs->ptp) {
2178                 mlx5e_ptp_close(chs->ptp);
2179                 chs->ptp = NULL;
2180         }
2181         for (i = 0; i < chs->num; i++)
2182                 mlx5e_close_channel(chs->c[i]);
2183
2184         kfree(chs->c);
2185         chs->num = 0;
2186 }
2187
2188 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2189 {
2190         struct mlx5e_rx_res *res = priv->rx_res;
2191         struct mlx5e_lro_param lro_param;
2192
2193         lro_param = mlx5e_get_lro_param(&priv->channels.params);
2194
2195         return mlx5e_rx_res_lro_set_param(res, &lro_param);
2196 }
2197
2198 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_lro);
2199
2200 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2201                          struct mlx5e_params *params, u16 mtu)
2202 {
2203         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2204         int err;
2205
2206         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2207         if (err)
2208                 return err;
2209
2210         /* Update vport context MTU */
2211         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2212         return 0;
2213 }
2214
2215 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2216                             struct mlx5e_params *params, u16 *mtu)
2217 {
2218         u16 hw_mtu = 0;
2219         int err;
2220
2221         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2222         if (err || !hw_mtu) /* fallback to port oper mtu */
2223                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2224
2225         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2226 }
2227
2228 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2229 {
2230         struct mlx5e_params *params = &priv->channels.params;
2231         struct net_device *netdev = priv->netdev;
2232         struct mlx5_core_dev *mdev = priv->mdev;
2233         u16 mtu;
2234         int err;
2235
2236         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2237         if (err)
2238                 return err;
2239
2240         mlx5e_query_mtu(mdev, params, &mtu);
2241         if (mtu != params->sw_mtu)
2242                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2243                             __func__, mtu, params->sw_mtu);
2244
2245         params->sw_mtu = mtu;
2246         return 0;
2247 }
2248
2249 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu);
2250
2251 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2252 {
2253         struct mlx5e_params *params = &priv->channels.params;
2254         struct net_device *netdev   = priv->netdev;
2255         struct mlx5_core_dev *mdev  = priv->mdev;
2256         u16 max_mtu;
2257
2258         /* MTU range: 68 - hw-specific max */
2259         netdev->min_mtu = ETH_MIN_MTU;
2260
2261         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2262         netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2263                                 ETH_MAX_MTU);
2264 }
2265
2266 static int mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc,
2267                                 struct tc_mqprio_qopt_offload *mqprio)
2268 {
2269         int tc, err;
2270
2271         netdev_reset_tc(netdev);
2272
2273         if (ntc == 1)
2274                 return 0;
2275
2276         err = netdev_set_num_tc(netdev, ntc);
2277         if (err) {
2278                 netdev_WARN(netdev, "netdev_set_num_tc failed (%d), ntc = %d\n", err, ntc);
2279                 return err;
2280         }
2281
2282         for (tc = 0; tc < ntc; tc++) {
2283                 u16 count, offset;
2284
2285                 /* For DCB mode, map netdev TCs to offset 0
2286                  * We have our own UP to TXQ mapping for QoS
2287                  */
2288                 count = mqprio ? mqprio->qopt.count[tc] : nch;
2289                 offset = mqprio ? mqprio->qopt.offset[tc] : 0;
2290                 netdev_set_tc_queue(netdev, tc, count, offset);
2291         }
2292
2293         return 0;
2294 }
2295
2296 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv)
2297 {
2298         int qos_queues, nch, ntc, num_txqs, err;
2299
2300         qos_queues = mlx5e_qos_cur_leaf_nodes(priv);
2301
2302         nch = priv->channels.params.num_channels;
2303         ntc = mlx5e_get_dcb_num_tc(&priv->channels.params);
2304         num_txqs = nch * ntc + qos_queues;
2305         if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_PORT_TS))
2306                 num_txqs += ntc;
2307
2308         mlx5e_dbg(DRV, priv, "Setting num_txqs %d\n", num_txqs);
2309         err = netif_set_real_num_tx_queues(priv->netdev, num_txqs);
2310         if (err)
2311                 netdev_warn(priv->netdev, "netif_set_real_num_tx_queues failed, %d\n", err);
2312
2313         return err;
2314 }
2315
2316 static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv)
2317 {
2318         struct net_device *netdev = priv->netdev;
2319         int old_num_txqs, old_ntc;
2320         int num_rxqs, nch, ntc;
2321         int err;
2322
2323         old_num_txqs = netdev->real_num_tx_queues;
2324         old_ntc = netdev->num_tc ? : 1;
2325
2326         nch = priv->channels.params.num_channels;
2327         ntc = mlx5e_get_dcb_num_tc(&priv->channels.params);
2328         num_rxqs = nch * priv->profile->rq_groups;
2329
2330         err = mlx5e_netdev_set_tcs(netdev, nch, ntc, NULL);
2331         if (err)
2332                 goto err_out;
2333         err = mlx5e_update_tx_netdev_queues(priv);
2334         if (err)
2335                 goto err_tcs;
2336         err = netif_set_real_num_rx_queues(netdev, num_rxqs);
2337         if (err) {
2338                 netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err);
2339                 goto err_txqs;
2340         }
2341
2342         return 0;
2343
2344 err_txqs:
2345         /* netif_set_real_num_rx_queues could fail only when nch increased. Only
2346          * one of nch and ntc is changed in this function. That means, the call
2347          * to netif_set_real_num_tx_queues below should not fail, because it
2348          * decreases the number of TX queues.
2349          */
2350         WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs));
2351
2352 err_tcs:
2353         mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc, NULL);
2354 err_out:
2355         return err;
2356 }
2357
2358 static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv,
2359                                            struct mlx5e_params *params)
2360 {
2361         struct mlx5_core_dev *mdev = priv->mdev;
2362         int num_comp_vectors, ix, irq;
2363
2364         num_comp_vectors = mlx5_comp_vectors_count(mdev);
2365
2366         for (ix = 0; ix < params->num_channels; ix++) {
2367                 cpumask_clear(priv->scratchpad.cpumask);
2368
2369                 for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) {
2370                         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(mdev, irq));
2371
2372                         cpumask_set_cpu(cpu, priv->scratchpad.cpumask);
2373                 }
2374
2375                 netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix);
2376         }
2377 }
2378
2379 int mlx5e_num_channels_changed(struct mlx5e_priv *priv)
2380 {
2381         u16 count = priv->channels.params.num_channels;
2382         int err;
2383
2384         err = mlx5e_update_netdev_queues(priv);
2385         if (err)
2386                 return err;
2387
2388         mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params);
2389
2390         /* This function may be called on attach, before priv->rx_res is created. */
2391         if (!netif_is_rxfh_configured(priv->netdev) && priv->rx_res)
2392                 mlx5e_rx_res_rss_set_indir_uniform(priv->rx_res, count);
2393
2394         return 0;
2395 }
2396
2397 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed);
2398
2399 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv)
2400 {
2401         int i, ch, tc, num_tc;
2402
2403         ch = priv->channels.num;
2404         num_tc = mlx5e_get_dcb_num_tc(&priv->channels.params);
2405
2406         for (i = 0; i < ch; i++) {
2407                 for (tc = 0; tc < num_tc; tc++) {
2408                         struct mlx5e_channel *c = priv->channels.c[i];
2409                         struct mlx5e_txqsq *sq = &c->sq[tc];
2410
2411                         priv->txq2sq[sq->txq_ix] = sq;
2412                         priv->channel_tc2realtxq[i][tc] = i + tc * ch;
2413                 }
2414         }
2415
2416         if (!priv->channels.ptp)
2417                 return;
2418
2419         if (!test_bit(MLX5E_PTP_STATE_TX, priv->channels.ptp->state))
2420                 return;
2421
2422         for (tc = 0; tc < num_tc; tc++) {
2423                 struct mlx5e_ptp *c = priv->channels.ptp;
2424                 struct mlx5e_txqsq *sq = &c->ptpsq[tc].txqsq;
2425
2426                 priv->txq2sq[sq->txq_ix] = sq;
2427                 priv->port_ptp_tc2realtxq[tc] = priv->num_tc_x_num_ch + tc;
2428         }
2429 }
2430
2431 static void mlx5e_update_num_tc_x_num_ch(struct mlx5e_priv *priv)
2432 {
2433         /* Sync with mlx5e_select_queue. */
2434         WRITE_ONCE(priv->num_tc_x_num_ch,
2435                    mlx5e_get_dcb_num_tc(&priv->channels.params) * priv->channels.num);
2436 }
2437
2438 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2439 {
2440         mlx5e_update_num_tc_x_num_ch(priv);
2441         mlx5e_build_txq_maps(priv);
2442         mlx5e_activate_channels(&priv->channels);
2443         mlx5e_qos_activate_queues(priv);
2444         mlx5e_xdp_tx_enable(priv);
2445         netif_tx_start_all_queues(priv->netdev);
2446
2447         if (mlx5e_is_vport_rep(priv))
2448                 mlx5e_add_sqs_fwd_rules(priv);
2449
2450         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2451
2452         if (priv->rx_res)
2453                 mlx5e_rx_res_channels_activate(priv->rx_res, &priv->channels);
2454 }
2455
2456 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2457 {
2458         if (priv->rx_res)
2459                 mlx5e_rx_res_channels_deactivate(priv->rx_res);
2460
2461         if (mlx5e_is_vport_rep(priv))
2462                 mlx5e_remove_sqs_fwd_rules(priv);
2463
2464         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2465          * polling for inactive tx queues.
2466          */
2467         netif_tx_stop_all_queues(priv->netdev);
2468         netif_tx_disable(priv->netdev);
2469         mlx5e_xdp_tx_disable(priv);
2470         mlx5e_deactivate_channels(&priv->channels);
2471 }
2472
2473 static int mlx5e_switch_priv_params(struct mlx5e_priv *priv,
2474                                     struct mlx5e_params *new_params,
2475                                     mlx5e_fp_preactivate preactivate,
2476                                     void *context)
2477 {
2478         struct mlx5e_params old_params;
2479
2480         old_params = priv->channels.params;
2481         priv->channels.params = *new_params;
2482
2483         if (preactivate) {
2484                 int err;
2485
2486                 err = preactivate(priv, context);
2487                 if (err) {
2488                         priv->channels.params = old_params;
2489                         return err;
2490                 }
2491         }
2492
2493         return 0;
2494 }
2495
2496 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2497                                       struct mlx5e_channels *new_chs,
2498                                       mlx5e_fp_preactivate preactivate,
2499                                       void *context)
2500 {
2501         struct net_device *netdev = priv->netdev;
2502         struct mlx5e_channels old_chs;
2503         int carrier_ok;
2504         int err = 0;
2505
2506         carrier_ok = netif_carrier_ok(netdev);
2507         netif_carrier_off(netdev);
2508
2509         mlx5e_deactivate_priv_channels(priv);
2510
2511         old_chs = priv->channels;
2512         priv->channels = *new_chs;
2513
2514         /* New channels are ready to roll, call the preactivate hook if needed
2515          * to modify HW settings or update kernel parameters.
2516          */
2517         if (preactivate) {
2518                 err = preactivate(priv, context);
2519                 if (err) {
2520                         priv->channels = old_chs;
2521                         goto out;
2522                 }
2523         }
2524
2525         mlx5e_close_channels(&old_chs);
2526         priv->profile->update_rx(priv);
2527
2528 out:
2529         mlx5e_activate_priv_channels(priv);
2530
2531         /* return carrier back if needed */
2532         if (carrier_ok)
2533                 netif_carrier_on(netdev);
2534
2535         return err;
2536 }
2537
2538 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
2539                              struct mlx5e_params *params,
2540                              mlx5e_fp_preactivate preactivate,
2541                              void *context, bool reset)
2542 {
2543         struct mlx5e_channels new_chs = {};
2544         int err;
2545
2546         reset &= test_bit(MLX5E_STATE_OPENED, &priv->state);
2547         if (!reset)
2548                 return mlx5e_switch_priv_params(priv, params, preactivate, context);
2549
2550         new_chs.params = *params;
2551         err = mlx5e_open_channels(priv, &new_chs);
2552         if (err)
2553                 return err;
2554         err = mlx5e_switch_priv_channels(priv, &new_chs, preactivate, context);
2555         if (err)
2556                 mlx5e_close_channels(&new_chs);
2557
2558         return err;
2559 }
2560
2561 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
2562 {
2563         return mlx5e_safe_switch_params(priv, &priv->channels.params, NULL, NULL, true);
2564 }
2565
2566 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2567 {
2568         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2569         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2570 }
2571
2572 static void mlx5e_modify_admin_state(struct mlx5_core_dev *mdev,
2573                                      enum mlx5_port_status state)
2574 {
2575         struct mlx5_eswitch *esw = mdev->priv.eswitch;
2576         int vport_admin_state;
2577
2578         mlx5_set_port_admin_status(mdev, state);
2579
2580         if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS ||
2581             !MLX5_CAP_GEN(mdev, uplink_follow))
2582                 return;
2583
2584         if (state == MLX5_PORT_UP)
2585                 vport_admin_state = MLX5_VPORT_ADMIN_STATE_AUTO;
2586         else
2587                 vport_admin_state = MLX5_VPORT_ADMIN_STATE_DOWN;
2588
2589         mlx5_eswitch_set_vport_state(esw, MLX5_VPORT_UPLINK, vport_admin_state);
2590 }
2591
2592 int mlx5e_open_locked(struct net_device *netdev)
2593 {
2594         struct mlx5e_priv *priv = netdev_priv(netdev);
2595         int err;
2596
2597         set_bit(MLX5E_STATE_OPENED, &priv->state);
2598
2599         err = mlx5e_open_channels(priv, &priv->channels);
2600         if (err)
2601                 goto err_clear_state_opened_flag;
2602
2603         priv->profile->update_rx(priv);
2604         mlx5e_activate_priv_channels(priv);
2605         mlx5e_apply_traps(priv, true);
2606         if (priv->profile->update_carrier)
2607                 priv->profile->update_carrier(priv);
2608
2609         mlx5e_queue_update_stats(priv);
2610         return 0;
2611
2612 err_clear_state_opened_flag:
2613         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2614         return err;
2615 }
2616
2617 int mlx5e_open(struct net_device *netdev)
2618 {
2619         struct mlx5e_priv *priv = netdev_priv(netdev);
2620         int err;
2621
2622         mutex_lock(&priv->state_lock);
2623         err = mlx5e_open_locked(netdev);
2624         if (!err)
2625                 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_UP);
2626         mutex_unlock(&priv->state_lock);
2627
2628         return err;
2629 }
2630
2631 int mlx5e_close_locked(struct net_device *netdev)
2632 {
2633         struct mlx5e_priv *priv = netdev_priv(netdev);
2634
2635         /* May already be CLOSED in case a previous configuration operation
2636          * (e.g RX/TX queue size change) that involves close&open failed.
2637          */
2638         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2639                 return 0;
2640
2641         mlx5e_apply_traps(priv, false);
2642         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2643
2644         netif_carrier_off(priv->netdev);
2645         mlx5e_deactivate_priv_channels(priv);
2646         mlx5e_close_channels(&priv->channels);
2647
2648         return 0;
2649 }
2650
2651 int mlx5e_close(struct net_device *netdev)
2652 {
2653         struct mlx5e_priv *priv = netdev_priv(netdev);
2654         int err;
2655
2656         if (!netif_device_present(netdev))
2657                 return -ENODEV;
2658
2659         mutex_lock(&priv->state_lock);
2660         mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_DOWN);
2661         err = mlx5e_close_locked(netdev);
2662         mutex_unlock(&priv->state_lock);
2663
2664         return err;
2665 }
2666
2667 static void mlx5e_free_drop_rq(struct mlx5e_rq *rq)
2668 {
2669         mlx5_wq_destroy(&rq->wq_ctrl);
2670 }
2671
2672 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2673                                struct mlx5e_rq *rq,
2674                                struct mlx5e_rq_param *param)
2675 {
2676         void *rqc = param->rqc;
2677         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2678         int err;
2679
2680         param->wq.db_numa_node = param->wq.buf_numa_node;
2681
2682         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
2683                                  &rq->wq_ctrl);
2684         if (err)
2685                 return err;
2686
2687         /* Mark as unused given "Drop-RQ" packets never reach XDP */
2688         xdp_rxq_info_unused(&rq->xdp_rxq);
2689
2690         rq->mdev = mdev;
2691
2692         return 0;
2693 }
2694
2695 static int mlx5e_alloc_drop_cq(struct mlx5e_priv *priv,
2696                                struct mlx5e_cq *cq,
2697                                struct mlx5e_cq_param *param)
2698 {
2699         struct mlx5_core_dev *mdev = priv->mdev;
2700
2701         param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
2702         param->wq.db_numa_node  = dev_to_node(mlx5_core_dma_dev(mdev));
2703
2704         return mlx5e_alloc_cq_common(priv, param, cq);
2705 }
2706
2707 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
2708                        struct mlx5e_rq *drop_rq)
2709 {
2710         struct mlx5_core_dev *mdev = priv->mdev;
2711         struct mlx5e_cq_param cq_param = {};
2712         struct mlx5e_rq_param rq_param = {};
2713         struct mlx5e_cq *cq = &drop_rq->cq;
2714         int err;
2715
2716         mlx5e_build_drop_rq_param(mdev, priv->drop_rq_q_counter, &rq_param);
2717
2718         err = mlx5e_alloc_drop_cq(priv, cq, &cq_param);
2719         if (err)
2720                 return err;
2721
2722         err = mlx5e_create_cq(cq, &cq_param);
2723         if (err)
2724                 goto err_free_cq;
2725
2726         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
2727         if (err)
2728                 goto err_destroy_cq;
2729
2730         err = mlx5e_create_rq(drop_rq, &rq_param);
2731         if (err)
2732                 goto err_free_rq;
2733
2734         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
2735         if (err)
2736                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
2737
2738         return 0;
2739
2740 err_free_rq:
2741         mlx5e_free_drop_rq(drop_rq);
2742
2743 err_destroy_cq:
2744         mlx5e_destroy_cq(cq);
2745
2746 err_free_cq:
2747         mlx5e_free_cq(cq);
2748
2749         return err;
2750 }
2751
2752 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
2753 {
2754         mlx5e_destroy_rq(drop_rq);
2755         mlx5e_free_drop_rq(drop_rq);
2756         mlx5e_destroy_cq(&drop_rq->cq);
2757         mlx5e_free_cq(&drop_rq->cq);
2758 }
2759
2760 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
2761 {
2762         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2763
2764         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.hw_objs.td.tdn);
2765
2766         if (MLX5_GET(tisc, tisc, tls_en))
2767                 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.hw_objs.pdn);
2768
2769         if (mlx5_lag_is_lacp_owner(mdev))
2770                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2771
2772         return mlx5_core_create_tis(mdev, in, tisn);
2773 }
2774
2775 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
2776 {
2777         mlx5_core_destroy_tis(mdev, tisn);
2778 }
2779
2780 void mlx5e_destroy_tises(struct mlx5e_priv *priv)
2781 {
2782         int tc, i;
2783
2784         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++)
2785                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2786                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
2787 }
2788
2789 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
2790 {
2791         return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
2792 }
2793
2794 int mlx5e_create_tises(struct mlx5e_priv *priv)
2795 {
2796         int tc, i;
2797         int err;
2798
2799         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) {
2800                 for (tc = 0; tc < priv->profile->max_tc; tc++) {
2801                         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
2802                         void *tisc;
2803
2804                         tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2805
2806                         MLX5_SET(tisc, tisc, prio, tc << 1);
2807
2808                         if (mlx5e_lag_should_assign_affinity(priv->mdev))
2809                                 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
2810
2811                         err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]);
2812                         if (err)
2813                                 goto err_close_tises;
2814                 }
2815         }
2816
2817         return 0;
2818
2819 err_close_tises:
2820         for (; i >= 0; i--) {
2821                 for (tc--; tc >= 0; tc--)
2822                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
2823                 tc = priv->profile->max_tc;
2824         }
2825
2826         return err;
2827 }
2828
2829 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2830 {
2831         mlx5e_destroy_tises(priv);
2832 }
2833
2834 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
2835 {
2836         int err = 0;
2837         int i;
2838
2839         for (i = 0; i < chs->num; i++) {
2840                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
2841                 if (err)
2842                         return err;
2843         }
2844
2845         return 0;
2846 }
2847
2848 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
2849 {
2850         int err;
2851         int i;
2852
2853         for (i = 0; i < chs->num; i++) {
2854                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
2855                 if (err)
2856                         return err;
2857         }
2858         if (chs->ptp && test_bit(MLX5E_PTP_STATE_RX, chs->ptp->state))
2859                 return mlx5e_modify_rq_vsd(&chs->ptp->rq, vsd);
2860
2861         return 0;
2862 }
2863
2864 static int mlx5e_setup_tc_mqprio_dcb(struct mlx5e_priv *priv,
2865                                      struct tc_mqprio_qopt *mqprio)
2866 {
2867         struct mlx5e_params new_params;
2868         u8 tc = mqprio->num_tc;
2869         int err;
2870
2871         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
2872
2873         if (tc && tc != MLX5E_MAX_NUM_TC)
2874                 return -EINVAL;
2875
2876         new_params = priv->channels.params;
2877         new_params.mqprio.mode = TC_MQPRIO_MODE_DCB;
2878         new_params.mqprio.num_tc = tc ? tc : 1;
2879
2880         err = mlx5e_safe_switch_params(priv, &new_params,
2881                                        mlx5e_num_channels_changed_ctx, NULL, true);
2882
2883         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
2884                                     mlx5e_get_dcb_num_tc(&priv->channels.params));
2885         return err;
2886 }
2887
2888 static int mlx5e_mqprio_channel_validate(struct mlx5e_priv *priv,
2889                                          struct tc_mqprio_qopt_offload *mqprio)
2890 {
2891         struct net_device *netdev = priv->netdev;
2892         int agg_count = 0;
2893         int i;
2894
2895         if (mqprio->qopt.offset[0] != 0 || mqprio->qopt.num_tc < 1 ||
2896             mqprio->qopt.num_tc > MLX5E_MAX_NUM_MQPRIO_CH_TC)
2897                 return -EINVAL;
2898
2899         for (i = 0; i < mqprio->qopt.num_tc; i++) {
2900                 if (!mqprio->qopt.count[i]) {
2901                         netdev_err(netdev, "Zero size for queue-group (%d) is not supported\n", i);
2902                         return -EINVAL;
2903                 }
2904                 if (mqprio->min_rate[i]) {
2905                         netdev_err(netdev, "Min tx rate is not supported\n");
2906                         return -EINVAL;
2907                 }
2908                 if (mqprio->max_rate[i]) {
2909                         netdev_err(netdev, "Max tx rate is not supported\n");
2910                         return -EINVAL;
2911                 }
2912
2913                 if (mqprio->qopt.offset[i] != agg_count) {
2914                         netdev_err(netdev, "Discontinuous queues config is not supported\n");
2915                         return -EINVAL;
2916                 }
2917                 agg_count += mqprio->qopt.count[i];
2918         }
2919
2920         if (priv->channels.params.num_channels < agg_count) {
2921                 netdev_err(netdev, "Num of queues (%d) exceeds available (%d)\n",
2922                            agg_count, priv->channels.params.num_channels);
2923                 return -EINVAL;
2924         }
2925
2926         return 0;
2927 }
2928
2929 static int mlx5e_mqprio_channel_set_tcs_ctx(struct mlx5e_priv *priv, void *ctx)
2930 {
2931         struct tc_mqprio_qopt_offload *mqprio = (struct tc_mqprio_qopt_offload *)ctx;
2932         struct net_device *netdev = priv->netdev;
2933         u8 num_tc;
2934
2935         if (priv->channels.params.mqprio.mode != TC_MQPRIO_MODE_CHANNEL)
2936                 return -EINVAL;
2937
2938         num_tc = priv->channels.params.mqprio.num_tc;
2939         mlx5e_netdev_set_tcs(netdev, 0, num_tc, mqprio);
2940
2941         return 0;
2942 }
2943
2944 static int mlx5e_setup_tc_mqprio_channel(struct mlx5e_priv *priv,
2945                                          struct tc_mqprio_qopt_offload *mqprio)
2946 {
2947         struct mlx5e_params new_params;
2948         int err;
2949
2950         err = mlx5e_mqprio_channel_validate(priv, mqprio);
2951         if (err)
2952                 return err;
2953
2954         new_params = priv->channels.params;
2955         new_params.mqprio.mode = TC_MQPRIO_MODE_CHANNEL;
2956         new_params.mqprio.num_tc = mqprio->qopt.num_tc;
2957         err = mlx5e_safe_switch_params(priv, &new_params,
2958                                        mlx5e_mqprio_channel_set_tcs_ctx, mqprio, true);
2959
2960         return err;
2961 }
2962
2963 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
2964                                  struct tc_mqprio_qopt_offload *mqprio)
2965 {
2966         /* MQPRIO is another toplevel qdisc that can't be attached
2967          * simultaneously with the offloaded HTB.
2968          */
2969         if (WARN_ON(priv->htb.maj_id))
2970                 return -EINVAL;
2971
2972         switch (mqprio->mode) {
2973         case TC_MQPRIO_MODE_DCB:
2974                 return mlx5e_setup_tc_mqprio_dcb(priv, &mqprio->qopt);
2975         case TC_MQPRIO_MODE_CHANNEL:
2976                 return mlx5e_setup_tc_mqprio_channel(priv, mqprio);
2977         default:
2978                 return -EOPNOTSUPP;
2979         }
2980 }
2981
2982 static int mlx5e_setup_tc_htb(struct mlx5e_priv *priv, struct tc_htb_qopt_offload *htb)
2983 {
2984         int res;
2985
2986         switch (htb->command) {
2987         case TC_HTB_CREATE:
2988                 return mlx5e_htb_root_add(priv, htb->parent_classid, htb->classid,
2989                                           htb->extack);
2990         case TC_HTB_DESTROY:
2991                 return mlx5e_htb_root_del(priv);
2992         case TC_HTB_LEAF_ALLOC_QUEUE:
2993                 res = mlx5e_htb_leaf_alloc_queue(priv, htb->classid, htb->parent_classid,
2994                                                  htb->rate, htb->ceil, htb->extack);
2995                 if (res < 0)
2996                         return res;
2997                 htb->qid = res;
2998                 return 0;
2999         case TC_HTB_LEAF_TO_INNER:
3000                 return mlx5e_htb_leaf_to_inner(priv, htb->parent_classid, htb->classid,
3001                                                htb->rate, htb->ceil, htb->extack);
3002         case TC_HTB_LEAF_DEL:
3003                 return mlx5e_htb_leaf_del(priv, &htb->classid, htb->extack);
3004         case TC_HTB_LEAF_DEL_LAST:
3005         case TC_HTB_LEAF_DEL_LAST_FORCE:
3006                 return mlx5e_htb_leaf_del_last(priv, htb->classid,
3007                                                htb->command == TC_HTB_LEAF_DEL_LAST_FORCE,
3008                                                htb->extack);
3009         case TC_HTB_NODE_MODIFY:
3010                 return mlx5e_htb_node_modify(priv, htb->classid, htb->rate, htb->ceil,
3011                                              htb->extack);
3012         case TC_HTB_LEAF_QUERY_QUEUE:
3013                 res = mlx5e_get_txq_by_classid(priv, htb->classid);
3014                 if (res < 0)
3015                         return res;
3016                 htb->qid = res;
3017                 return 0;
3018         default:
3019                 return -EOPNOTSUPP;
3020         }
3021 }
3022
3023 static LIST_HEAD(mlx5e_block_cb_list);
3024
3025 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3026                           void *type_data)
3027 {
3028         struct mlx5e_priv *priv = netdev_priv(dev);
3029         bool tc_unbind = false;
3030         int err;
3031
3032         if (type == TC_SETUP_BLOCK &&
3033             ((struct flow_block_offload *)type_data)->command == FLOW_BLOCK_UNBIND)
3034                 tc_unbind = true;
3035
3036         if (!netif_device_present(dev) && !tc_unbind)
3037                 return -ENODEV;
3038
3039         switch (type) {
3040         case TC_SETUP_BLOCK: {
3041                 struct flow_block_offload *f = type_data;
3042
3043                 f->unlocked_driver_cb = true;
3044                 return flow_block_cb_setup_simple(type_data,
3045                                                   &mlx5e_block_cb_list,
3046                                                   mlx5e_setup_tc_block_cb,
3047                                                   priv, priv, true);
3048         }
3049         case TC_SETUP_QDISC_MQPRIO:
3050                 mutex_lock(&priv->state_lock);
3051                 err = mlx5e_setup_tc_mqprio(priv, type_data);
3052                 mutex_unlock(&priv->state_lock);
3053                 return err;
3054         case TC_SETUP_QDISC_HTB:
3055                 mutex_lock(&priv->state_lock);
3056                 err = mlx5e_setup_tc_htb(priv, type_data);
3057                 mutex_unlock(&priv->state_lock);
3058                 return err;
3059         default:
3060                 return -EOPNOTSUPP;
3061         }
3062 }
3063
3064 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3065 {
3066         int i;
3067
3068         for (i = 0; i < priv->max_nch; i++) {
3069                 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3070                 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3071                 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3072                 int j;
3073
3074                 s->rx_packets   += rq_stats->packets + xskrq_stats->packets;
3075                 s->rx_bytes     += rq_stats->bytes + xskrq_stats->bytes;
3076                 s->multicast    += rq_stats->mcast_packets + xskrq_stats->mcast_packets;
3077
3078                 for (j = 0; j < priv->max_opened_tc; j++) {
3079                         struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3080
3081                         s->tx_packets    += sq_stats->packets;
3082                         s->tx_bytes      += sq_stats->bytes;
3083                         s->tx_dropped    += sq_stats->dropped;
3084                 }
3085         }
3086         if (priv->tx_ptp_opened) {
3087                 for (i = 0; i < priv->max_opened_tc; i++) {
3088                         struct mlx5e_sq_stats *sq_stats = &priv->ptp_stats.sq[i];
3089
3090                         s->tx_packets    += sq_stats->packets;
3091                         s->tx_bytes      += sq_stats->bytes;
3092                         s->tx_dropped    += sq_stats->dropped;
3093                 }
3094         }
3095         if (priv->rx_ptp_opened) {
3096                 struct mlx5e_rq_stats *rq_stats = &priv->ptp_stats.rq;
3097
3098                 s->rx_packets   += rq_stats->packets;
3099                 s->rx_bytes     += rq_stats->bytes;
3100                 s->multicast    += rq_stats->mcast_packets;
3101         }
3102 }
3103
3104 void
3105 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3106 {
3107         struct mlx5e_priv *priv = netdev_priv(dev);
3108         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3109
3110         if (!netif_device_present(dev))
3111                 return;
3112
3113         /* In switchdev mode, monitor counters doesn't monitor
3114          * rx/tx stats of 802_3. The update stats mechanism
3115          * should keep the 802_3 layout counters updated
3116          */
3117         if (!mlx5e_monitor_counter_supported(priv) ||
3118             mlx5e_is_uplink_rep(priv)) {
3119                 /* update HW stats in background for next time */
3120                 mlx5e_queue_update_stats(priv);
3121         }
3122
3123         if (mlx5e_is_uplink_rep(priv)) {
3124                 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3125
3126                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3127                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3128                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3129                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3130
3131                 /* vport multicast also counts packets that are dropped due to steering
3132                  * or rx out of buffer
3133                  */
3134                 stats->multicast = VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3135         } else {
3136                 mlx5e_fold_sw_stats64(priv, stats);
3137         }
3138
3139         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3140
3141         stats->rx_length_errors =
3142                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3143                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3144                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3145         stats->rx_crc_errors =
3146                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3147         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3148         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3149         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3150                            stats->rx_frame_errors;
3151         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3152 }
3153
3154 static void mlx5e_nic_set_rx_mode(struct mlx5e_priv *priv)
3155 {
3156         if (mlx5e_is_uplink_rep(priv))
3157                 return; /* no rx mode for uplink rep */
3158
3159         queue_work(priv->wq, &priv->set_rx_mode_work);
3160 }
3161
3162 static void mlx5e_set_rx_mode(struct net_device *dev)
3163 {
3164         struct mlx5e_priv *priv = netdev_priv(dev);
3165
3166         mlx5e_nic_set_rx_mode(priv);
3167 }
3168
3169 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3170 {
3171         struct mlx5e_priv *priv = netdev_priv(netdev);
3172         struct sockaddr *saddr = addr;
3173
3174         if (!is_valid_ether_addr(saddr->sa_data))
3175                 return -EADDRNOTAVAIL;
3176
3177         netif_addr_lock_bh(netdev);
3178         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3179         netif_addr_unlock_bh(netdev);
3180
3181         mlx5e_nic_set_rx_mode(priv);
3182
3183         return 0;
3184 }
3185
3186 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3187         do {                                            \
3188                 if (enable)                             \
3189                         *features |= feature;           \
3190                 else                                    \
3191                         *features &= ~feature;          \
3192         } while (0)
3193
3194 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3195
3196 static int set_feature_lro(struct net_device *netdev, bool enable)
3197 {
3198         struct mlx5e_priv *priv = netdev_priv(netdev);
3199         struct mlx5_core_dev *mdev = priv->mdev;
3200         struct mlx5e_params *cur_params;
3201         struct mlx5e_params new_params;
3202         bool reset = true;
3203         int err = 0;
3204
3205         mutex_lock(&priv->state_lock);
3206
3207         if (enable && priv->xsk.refcnt) {
3208                 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%u XSKs are active)\n",
3209                             priv->xsk.refcnt);
3210                 err = -EINVAL;
3211                 goto out;
3212         }
3213
3214         cur_params = &priv->channels.params;
3215         if (enable && !MLX5E_GET_PFLAG(cur_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3216                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3217                 err = -EINVAL;
3218                 goto out;
3219         }
3220
3221         new_params = *cur_params;
3222         new_params.lro_en = enable;
3223
3224         if (cur_params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3225                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, cur_params, NULL) ==
3226                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_params, NULL))
3227                         reset = false;
3228         }
3229
3230         err = mlx5e_safe_switch_params(priv, &new_params,
3231                                        mlx5e_modify_tirs_lro_ctx, NULL, reset);
3232 out:
3233         mutex_unlock(&priv->state_lock);
3234         return err;
3235 }
3236
3237 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3238 {
3239         struct mlx5e_priv *priv = netdev_priv(netdev);
3240
3241         if (enable)
3242                 mlx5e_enable_cvlan_filter(priv);
3243         else
3244                 mlx5e_disable_cvlan_filter(priv);
3245
3246         return 0;
3247 }
3248
3249 static int set_feature_hw_tc(struct net_device *netdev, bool enable)
3250 {
3251         struct mlx5e_priv *priv = netdev_priv(netdev);
3252
3253 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3254         if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) {
3255                 netdev_err(netdev,
3256                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3257                 return -EINVAL;
3258         }
3259 #endif
3260
3261         if (!enable && priv->htb.maj_id) {
3262                 netdev_err(netdev, "Active HTB offload, can't turn hw_tc_offload off\n");
3263                 return -EINVAL;
3264         }
3265
3266         return 0;
3267 }
3268
3269 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3270 {
3271         struct mlx5e_priv *priv = netdev_priv(netdev);
3272         struct mlx5_core_dev *mdev = priv->mdev;
3273
3274         return mlx5_set_port_fcs(mdev, !enable);
3275 }
3276
3277 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3278 {
3279         struct mlx5e_priv *priv = netdev_priv(netdev);
3280         int err;
3281
3282         mutex_lock(&priv->state_lock);
3283
3284         priv->channels.params.scatter_fcs_en = enable;
3285         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3286         if (err)
3287                 priv->channels.params.scatter_fcs_en = !enable;
3288
3289         mutex_unlock(&priv->state_lock);
3290
3291         return err;
3292 }
3293
3294 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3295 {
3296         struct mlx5e_priv *priv = netdev_priv(netdev);
3297         int err = 0;
3298
3299         mutex_lock(&priv->state_lock);
3300
3301         priv->channels.params.vlan_strip_disable = !enable;
3302         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3303                 goto unlock;
3304
3305         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3306         if (err)
3307                 priv->channels.params.vlan_strip_disable = enable;
3308
3309 unlock:
3310         mutex_unlock(&priv->state_lock);
3311
3312         return err;
3313 }
3314
3315 #ifdef CONFIG_MLX5_EN_ARFS
3316 static int set_feature_arfs(struct net_device *netdev, bool enable)
3317 {
3318         struct mlx5e_priv *priv = netdev_priv(netdev);
3319         int err;
3320
3321         if (enable)
3322                 err = mlx5e_arfs_enable(priv);
3323         else
3324                 err = mlx5e_arfs_disable(priv);
3325
3326         return err;
3327 }
3328 #endif
3329
3330 static int mlx5e_handle_feature(struct net_device *netdev,
3331                                 netdev_features_t *features,
3332                                 netdev_features_t wanted_features,
3333                                 netdev_features_t feature,
3334                                 mlx5e_feature_handler feature_handler)
3335 {
3336         netdev_features_t changes = wanted_features ^ netdev->features;
3337         bool enable = !!(wanted_features & feature);
3338         int err;
3339
3340         if (!(changes & feature))
3341                 return 0;
3342
3343         err = feature_handler(netdev, enable);
3344         if (err) {
3345                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3346                            enable ? "Enable" : "Disable", &feature, err);
3347                 return err;
3348         }
3349
3350         MLX5E_SET_FEATURE(features, feature, enable);
3351         return 0;
3352 }
3353
3354 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3355 {
3356         netdev_features_t oper_features = netdev->features;
3357         int err = 0;
3358
3359 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3360         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3361
3362         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3363         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3364                                     set_feature_cvlan_filter);
3365         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_hw_tc);
3366         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3367         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3368         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3369 #ifdef CONFIG_MLX5_EN_ARFS
3370         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3371 #endif
3372         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TLS_RX, mlx5e_ktls_set_feature_rx);
3373
3374         if (err) {
3375                 netdev->features = oper_features;
3376                 return -EINVAL;
3377         }
3378
3379         return 0;
3380 }
3381
3382 static netdev_features_t mlx5e_fix_uplink_rep_features(struct net_device *netdev,
3383                                                        netdev_features_t features)
3384 {
3385         features &= ~NETIF_F_HW_TLS_RX;
3386         if (netdev->features & NETIF_F_HW_TLS_RX)
3387                 netdev_warn(netdev, "Disabling hw_tls_rx, not supported in switchdev mode\n");
3388
3389         features &= ~NETIF_F_HW_TLS_TX;
3390         if (netdev->features & NETIF_F_HW_TLS_TX)
3391                 netdev_warn(netdev, "Disabling hw_tls_tx, not supported in switchdev mode\n");
3392
3393         features &= ~NETIF_F_NTUPLE;
3394         if (netdev->features & NETIF_F_NTUPLE)
3395                 netdev_warn(netdev, "Disabling ntuple, not supported in switchdev mode\n");
3396
3397         return features;
3398 }
3399
3400 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3401                                             netdev_features_t features)
3402 {
3403         struct mlx5e_priv *priv = netdev_priv(netdev);
3404         struct mlx5e_params *params;
3405
3406         mutex_lock(&priv->state_lock);
3407         params = &priv->channels.params;
3408         if (!priv->fs.vlan ||
3409             !bitmap_empty(mlx5e_vlan_get_active_svlans(priv->fs.vlan), VLAN_N_VID)) {
3410                 /* HW strips the outer C-tag header, this is a problem
3411                  * for S-tag traffic.
3412                  */
3413                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3414                 if (!params->vlan_strip_disable)
3415                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3416         }
3417
3418         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3419                 if (features & NETIF_F_LRO) {
3420                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3421                         features &= ~NETIF_F_LRO;
3422                 }
3423         }
3424
3425         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3426                 features &= ~NETIF_F_RXHASH;
3427                 if (netdev->features & NETIF_F_RXHASH)
3428                         netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3429         }
3430
3431         if (mlx5e_is_uplink_rep(priv))
3432                 features = mlx5e_fix_uplink_rep_features(netdev, features);
3433
3434         mutex_unlock(&priv->state_lock);
3435
3436         return features;
3437 }
3438
3439 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3440                                    struct mlx5e_channels *chs,
3441                                    struct mlx5e_params *new_params,
3442                                    struct mlx5_core_dev *mdev)
3443 {
3444         u16 ix;
3445
3446         for (ix = 0; ix < chs->params.num_channels; ix++) {
3447                 struct xsk_buff_pool *xsk_pool =
3448                         mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, ix);
3449                 struct mlx5e_xsk_param xsk;
3450
3451                 if (!xsk_pool)
3452                         continue;
3453
3454                 mlx5e_build_xsk_param(xsk_pool, &xsk);
3455
3456                 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3457                         u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3458                         int max_mtu_frame, max_mtu_page, max_mtu;
3459
3460                         /* Two criteria must be met:
3461                          * 1. HW MTU + all headrooms <= XSK frame size.
3462                          * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
3463                          */
3464                         max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
3465                         max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
3466                         max_mtu = min(max_mtu_frame, max_mtu_page);
3467
3468                         netdev_err(netdev, "MTU %d is too big for an XSK running on channel %u. Try MTU <= %d\n",
3469                                    new_params->sw_mtu, ix, max_mtu);
3470                         return false;
3471                 }
3472         }
3473
3474         return true;
3475 }
3476
3477 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3478                      mlx5e_fp_preactivate preactivate)
3479 {
3480         struct mlx5e_priv *priv = netdev_priv(netdev);
3481         struct mlx5e_params new_params;
3482         struct mlx5e_params *params;
3483         bool reset = true;
3484         int err = 0;
3485
3486         mutex_lock(&priv->state_lock);
3487
3488         params = &priv->channels.params;
3489
3490         new_params = *params;
3491         new_params.sw_mtu = new_mtu;
3492         err = mlx5e_validate_params(priv->mdev, &new_params);
3493         if (err)
3494                 goto out;
3495
3496         if (params->xdp_prog &&
3497             !mlx5e_rx_is_linear_skb(&new_params, NULL)) {
3498                 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3499                            new_mtu, mlx5e_xdp_max_mtu(params, NULL));
3500                 err = -EINVAL;
3501                 goto out;
3502         }
3503
3504         if (priv->xsk.refcnt &&
3505             !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
3506                                     &new_params, priv->mdev)) {
3507                 err = -EINVAL;
3508                 goto out;
3509         }
3510
3511         if (params->lro_en)
3512                 reset = false;
3513
3514         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3515                 bool is_linear_old = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, params, NULL);
3516                 bool is_linear_new = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
3517                                                                   &new_params, NULL);
3518                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
3519                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_params, NULL);
3520
3521                 /* Always reset in linear mode - hw_mtu is used in data path.
3522                  * Check that the mode was non-linear and didn't change.
3523                  * If XSK is active, XSK RQs are linear.
3524                  */
3525                 if (!is_linear_old && !is_linear_new && !priv->xsk.refcnt &&
3526                     ppw_old == ppw_new)
3527                         reset = false;
3528         }
3529
3530         err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, reset);
3531
3532 out:
3533         netdev->mtu = params->sw_mtu;
3534         mutex_unlock(&priv->state_lock);
3535         return err;
3536 }
3537
3538 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3539 {
3540         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx);
3541 }
3542
3543 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx)
3544 {
3545         bool set  = *(bool *)ctx;
3546
3547         return mlx5e_ptp_rx_manage_fs(priv, set);
3548 }
3549
3550 static int mlx5e_hwstamp_config_no_ptp_rx(struct mlx5e_priv *priv, bool rx_filter)
3551 {
3552         bool rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
3553         int err;
3554
3555         if (!rx_filter)
3556                 /* Reset CQE compression to Admin default */
3557                 return mlx5e_modify_rx_cqe_compression_locked(priv, rx_cqe_compress_def);
3558
3559         if (!MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
3560                 return 0;
3561
3562         /* Disable CQE compression */
3563         netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
3564         err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3565         if (err)
3566                 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3567
3568         return err;
3569 }
3570
3571 static int mlx5e_hwstamp_config_ptp_rx(struct mlx5e_priv *priv, bool ptp_rx)
3572 {
3573         struct mlx5e_params new_params;
3574
3575         if (ptp_rx == priv->channels.params.ptp_rx)
3576                 return 0;
3577
3578         new_params = priv->channels.params;
3579         new_params.ptp_rx = ptp_rx;
3580         return mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx,
3581                                         &new_params.ptp_rx, true);
3582 }
3583
3584 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3585 {
3586         struct hwtstamp_config config;
3587         bool rx_cqe_compress_def;
3588         bool ptp_rx;
3589         int err;
3590
3591         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3592             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
3593                 return -EOPNOTSUPP;
3594
3595         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3596                 return -EFAULT;
3597
3598         /* TX HW timestamp */
3599         switch (config.tx_type) {
3600         case HWTSTAMP_TX_OFF:
3601         case HWTSTAMP_TX_ON:
3602                 break;
3603         default:
3604                 return -ERANGE;
3605         }
3606
3607         mutex_lock(&priv->state_lock);
3608         rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
3609
3610         /* RX HW timestamp */
3611         switch (config.rx_filter) {
3612         case HWTSTAMP_FILTER_NONE:
3613                 ptp_rx = false;
3614                 break;
3615         case HWTSTAMP_FILTER_ALL:
3616         case HWTSTAMP_FILTER_SOME:
3617         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3618         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3619         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3620         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3621         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3622         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3623         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3624         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3625         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3626         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3627         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3628         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3629         case HWTSTAMP_FILTER_NTP_ALL:
3630                 config.rx_filter = HWTSTAMP_FILTER_ALL;
3631                 /* ptp_rx is set if both HW TS is set and CQE
3632                  * compression is set
3633                  */
3634                 ptp_rx = rx_cqe_compress_def;
3635                 break;
3636         default:
3637                 err = -ERANGE;
3638                 goto err_unlock;
3639         }
3640
3641         if (!priv->profile->rx_ptp_support)
3642                 err = mlx5e_hwstamp_config_no_ptp_rx(priv,
3643                                                      config.rx_filter != HWTSTAMP_FILTER_NONE);
3644         else
3645                 err = mlx5e_hwstamp_config_ptp_rx(priv, ptp_rx);
3646         if (err)
3647                 goto err_unlock;
3648
3649         memcpy(&priv->tstamp, &config, sizeof(config));
3650         mutex_unlock(&priv->state_lock);
3651
3652         /* might need to fix some features */
3653         netdev_update_features(priv->netdev);
3654
3655         return copy_to_user(ifr->ifr_data, &config,
3656                             sizeof(config)) ? -EFAULT : 0;
3657 err_unlock:
3658         mutex_unlock(&priv->state_lock);
3659         return err;
3660 }
3661
3662 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3663 {
3664         struct hwtstamp_config *cfg = &priv->tstamp;
3665
3666         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3667                 return -EOPNOTSUPP;
3668
3669         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3670 }
3671
3672 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3673 {
3674         struct mlx5e_priv *priv = netdev_priv(dev);
3675
3676         switch (cmd) {
3677         case SIOCSHWTSTAMP:
3678                 return mlx5e_hwstamp_set(priv, ifr);
3679         case SIOCGHWTSTAMP:
3680                 return mlx5e_hwstamp_get(priv, ifr);
3681         default:
3682                 return -EOPNOTSUPP;
3683         }
3684 }
3685
3686 #ifdef CONFIG_MLX5_ESWITCH
3687 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3688 {
3689         struct mlx5e_priv *priv = netdev_priv(dev);
3690         struct mlx5_core_dev *mdev = priv->mdev;
3691
3692         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3693 }
3694
3695 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3696                              __be16 vlan_proto)
3697 {
3698         struct mlx5e_priv *priv = netdev_priv(dev);
3699         struct mlx5_core_dev *mdev = priv->mdev;
3700
3701         if (vlan_proto != htons(ETH_P_8021Q))
3702                 return -EPROTONOSUPPORT;
3703
3704         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3705                                            vlan, qos);
3706 }
3707
3708 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3709 {
3710         struct mlx5e_priv *priv = netdev_priv(dev);
3711         struct mlx5_core_dev *mdev = priv->mdev;
3712
3713         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3714 }
3715
3716 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3717 {
3718         struct mlx5e_priv *priv = netdev_priv(dev);
3719         struct mlx5_core_dev *mdev = priv->mdev;
3720
3721         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3722 }
3723
3724 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3725                       int max_tx_rate)
3726 {
3727         struct mlx5e_priv *priv = netdev_priv(dev);
3728         struct mlx5_core_dev *mdev = priv->mdev;
3729
3730         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3731                                            max_tx_rate, min_tx_rate);
3732 }
3733
3734 static int mlx5_vport_link2ifla(u8 esw_link)
3735 {
3736         switch (esw_link) {
3737         case MLX5_VPORT_ADMIN_STATE_DOWN:
3738                 return IFLA_VF_LINK_STATE_DISABLE;
3739         case MLX5_VPORT_ADMIN_STATE_UP:
3740                 return IFLA_VF_LINK_STATE_ENABLE;
3741         }
3742         return IFLA_VF_LINK_STATE_AUTO;
3743 }
3744
3745 static int mlx5_ifla_link2vport(u8 ifla_link)
3746 {
3747         switch (ifla_link) {
3748         case IFLA_VF_LINK_STATE_DISABLE:
3749                 return MLX5_VPORT_ADMIN_STATE_DOWN;
3750         case IFLA_VF_LINK_STATE_ENABLE:
3751                 return MLX5_VPORT_ADMIN_STATE_UP;
3752         }
3753         return MLX5_VPORT_ADMIN_STATE_AUTO;
3754 }
3755
3756 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3757                                    int link_state)
3758 {
3759         struct mlx5e_priv *priv = netdev_priv(dev);
3760         struct mlx5_core_dev *mdev = priv->mdev;
3761
3762         if (mlx5e_is_uplink_rep(priv))
3763                 return -EOPNOTSUPP;
3764
3765         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3766                                             mlx5_ifla_link2vport(link_state));
3767 }
3768
3769 int mlx5e_get_vf_config(struct net_device *dev,
3770                         int vf, struct ifla_vf_info *ivi)
3771 {
3772         struct mlx5e_priv *priv = netdev_priv(dev);
3773         struct mlx5_core_dev *mdev = priv->mdev;
3774         int err;
3775
3776         if (!netif_device_present(dev))
3777                 return -EOPNOTSUPP;
3778
3779         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3780         if (err)
3781                 return err;
3782         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3783         return 0;
3784 }
3785
3786 int mlx5e_get_vf_stats(struct net_device *dev,
3787                        int vf, struct ifla_vf_stats *vf_stats)
3788 {
3789         struct mlx5e_priv *priv = netdev_priv(dev);
3790         struct mlx5_core_dev *mdev = priv->mdev;
3791
3792         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3793                                             vf_stats);
3794 }
3795
3796 static bool
3797 mlx5e_has_offload_stats(const struct net_device *dev, int attr_id)
3798 {
3799         struct mlx5e_priv *priv = netdev_priv(dev);
3800
3801         if (!netif_device_present(dev))
3802                 return false;
3803
3804         if (!mlx5e_is_uplink_rep(priv))
3805                 return false;
3806
3807         return mlx5e_rep_has_offload_stats(dev, attr_id);
3808 }
3809
3810 static int
3811 mlx5e_get_offload_stats(int attr_id, const struct net_device *dev,
3812                         void *sp)
3813 {
3814         struct mlx5e_priv *priv = netdev_priv(dev);
3815
3816         if (!mlx5e_is_uplink_rep(priv))
3817                 return -EOPNOTSUPP;
3818
3819         return mlx5e_rep_get_offload_stats(attr_id, dev, sp);
3820 }
3821 #endif
3822
3823 static bool mlx5e_tunnel_proto_supported_tx(struct mlx5_core_dev *mdev, u8 proto_type)
3824 {
3825         switch (proto_type) {
3826         case IPPROTO_GRE:
3827                 return MLX5_CAP_ETH(mdev, tunnel_stateless_gre);
3828         case IPPROTO_IPIP:
3829         case IPPROTO_IPV6:
3830                 return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) ||
3831                         MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_tx));
3832         default:
3833                 return false;
3834         }
3835 }
3836
3837 static bool mlx5e_gre_tunnel_inner_proto_offload_supported(struct mlx5_core_dev *mdev,
3838                                                            struct sk_buff *skb)
3839 {
3840         switch (skb->inner_protocol) {
3841         case htons(ETH_P_IP):
3842         case htons(ETH_P_IPV6):
3843         case htons(ETH_P_TEB):
3844                 return true;
3845         case htons(ETH_P_MPLS_UC):
3846         case htons(ETH_P_MPLS_MC):
3847                 return MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre);
3848         }
3849         return false;
3850 }
3851
3852 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
3853                                                      struct sk_buff *skb,
3854                                                      netdev_features_t features)
3855 {
3856         unsigned int offset = 0;
3857         struct udphdr *udph;
3858         u8 proto;
3859         u16 port;
3860
3861         switch (vlan_get_protocol(skb)) {
3862         case htons(ETH_P_IP):
3863                 proto = ip_hdr(skb)->protocol;
3864                 break;
3865         case htons(ETH_P_IPV6):
3866                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
3867                 break;
3868         default:
3869                 goto out;
3870         }
3871
3872         switch (proto) {
3873         case IPPROTO_GRE:
3874                 if (mlx5e_gre_tunnel_inner_proto_offload_supported(priv->mdev, skb))
3875                         return features;
3876                 break;
3877         case IPPROTO_IPIP:
3878         case IPPROTO_IPV6:
3879                 if (mlx5e_tunnel_proto_supported_tx(priv->mdev, IPPROTO_IPIP))
3880                         return features;
3881                 break;
3882         case IPPROTO_UDP:
3883                 udph = udp_hdr(skb);
3884                 port = be16_to_cpu(udph->dest);
3885
3886                 /* Verify if UDP port is being offloaded by HW */
3887                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
3888                         return features;
3889
3890 #if IS_ENABLED(CONFIG_GENEVE)
3891                 /* Support Geneve offload for default UDP port */
3892                 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
3893                         return features;
3894 #endif
3895                 break;
3896 #ifdef CONFIG_MLX5_EN_IPSEC
3897         case IPPROTO_ESP:
3898                 return mlx5e_ipsec_feature_check(skb, features);
3899 #endif
3900         }
3901
3902 out:
3903         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3904         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3905 }
3906
3907 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3908                                        struct net_device *netdev,
3909                                        netdev_features_t features)
3910 {
3911         struct mlx5e_priv *priv = netdev_priv(netdev);
3912
3913         features = vlan_features_check(skb, features);
3914         features = vxlan_features_check(skb, features);
3915
3916         /* Validate if the tunneled packet is being offloaded by HW */
3917         if (skb->encapsulation &&
3918             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3919                 return mlx5e_tunnel_features_check(priv, skb, features);
3920
3921         return features;
3922 }
3923
3924 static void mlx5e_tx_timeout_work(struct work_struct *work)
3925 {
3926         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
3927                                                tx_timeout_work);
3928         struct net_device *netdev = priv->netdev;
3929         int i;
3930
3931         rtnl_lock();
3932         mutex_lock(&priv->state_lock);
3933
3934         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3935                 goto unlock;
3936
3937         for (i = 0; i < netdev->real_num_tx_queues; i++) {
3938                 struct netdev_queue *dev_queue =
3939                         netdev_get_tx_queue(netdev, i);
3940                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3941
3942                 if (!netif_xmit_stopped(dev_queue))
3943                         continue;
3944
3945                 if (mlx5e_reporter_tx_timeout(sq))
3946                 /* break if tried to reopened channels */
3947                         break;
3948         }
3949
3950 unlock:
3951         mutex_unlock(&priv->state_lock);
3952         rtnl_unlock();
3953 }
3954
3955 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue)
3956 {
3957         struct mlx5e_priv *priv = netdev_priv(dev);
3958
3959         netdev_err(dev, "TX timeout detected\n");
3960         queue_work(priv->wq, &priv->tx_timeout_work);
3961 }
3962
3963 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
3964 {
3965         struct net_device *netdev = priv->netdev;
3966         struct mlx5e_params new_params;
3967
3968         if (priv->channels.params.lro_en) {
3969                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3970                 return -EINVAL;
3971         }
3972
3973         if (mlx5_fpga_is_ipsec_device(priv->mdev)) {
3974                 netdev_warn(netdev,
3975                             "XDP is not available on Innova cards with IPsec support\n");
3976                 return -EINVAL;
3977         }
3978
3979         new_params = priv->channels.params;
3980         new_params.xdp_prog = prog;
3981
3982         /* No XSK params: AF_XDP can't be enabled yet at the point of setting
3983          * the XDP program.
3984          */
3985         if (!mlx5e_rx_is_linear_skb(&new_params, NULL)) {
3986                 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
3987                             new_params.sw_mtu,
3988                             mlx5e_xdp_max_mtu(&new_params, NULL));
3989                 return -EINVAL;
3990         }
3991
3992         return 0;
3993 }
3994
3995 static void mlx5e_rq_replace_xdp_prog(struct mlx5e_rq *rq, struct bpf_prog *prog)
3996 {
3997         struct bpf_prog *old_prog;
3998
3999         old_prog = rcu_replace_pointer(rq->xdp_prog, prog,
4000                                        lockdep_is_held(&rq->priv->state_lock));
4001         if (old_prog)
4002                 bpf_prog_put(old_prog);
4003 }
4004
4005 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4006 {
4007         struct mlx5e_priv *priv = netdev_priv(netdev);
4008         struct mlx5e_params new_params;
4009         struct bpf_prog *old_prog;
4010         int err = 0;
4011         bool reset;
4012         int i;
4013
4014         mutex_lock(&priv->state_lock);
4015
4016         if (prog) {
4017                 err = mlx5e_xdp_allowed(priv, prog);
4018                 if (err)
4019                         goto unlock;
4020         }
4021
4022         /* no need for full reset when exchanging programs */
4023         reset = (!priv->channels.params.xdp_prog || !prog);
4024
4025         new_params = priv->channels.params;
4026         new_params.xdp_prog = prog;
4027         if (reset)
4028                 mlx5e_set_rq_type(priv->mdev, &new_params);
4029         old_prog = priv->channels.params.xdp_prog;
4030
4031         err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
4032         if (err)
4033                 goto unlock;
4034
4035         if (old_prog)
4036                 bpf_prog_put(old_prog);
4037
4038         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4039                 goto unlock;
4040
4041         /* exchanging programs w/o reset, we update ref counts on behalf
4042          * of the channels RQs here.
4043          */
4044         bpf_prog_add(prog, priv->channels.num);
4045         for (i = 0; i < priv->channels.num; i++) {
4046                 struct mlx5e_channel *c = priv->channels.c[i];
4047
4048                 mlx5e_rq_replace_xdp_prog(&c->rq, prog);
4049                 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) {
4050                         bpf_prog_inc(prog);
4051                         mlx5e_rq_replace_xdp_prog(&c->xskrq, prog);
4052                 }
4053         }
4054
4055 unlock:
4056         mutex_unlock(&priv->state_lock);
4057         return err;
4058 }
4059
4060 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4061 {
4062         switch (xdp->command) {
4063         case XDP_SETUP_PROG:
4064                 return mlx5e_xdp_set(dev, xdp->prog);
4065         case XDP_SETUP_XSK_POOL:
4066                 return mlx5e_xsk_setup_pool(dev, xdp->xsk.pool,
4067                                             xdp->xsk.queue_id);
4068         default:
4069                 return -EINVAL;
4070         }
4071 }
4072
4073 #ifdef CONFIG_MLX5_ESWITCH
4074 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4075                                 struct net_device *dev, u32 filter_mask,
4076                                 int nlflags)
4077 {
4078         struct mlx5e_priv *priv = netdev_priv(dev);
4079         struct mlx5_core_dev *mdev = priv->mdev;
4080         u8 mode, setting;
4081         int err;
4082
4083         err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4084         if (err)
4085                 return err;
4086         mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4087         return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4088                                        mode,
4089                                        0, 0, nlflags, filter_mask, NULL);
4090 }
4091
4092 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4093                                 u16 flags, struct netlink_ext_ack *extack)
4094 {
4095         struct mlx5e_priv *priv = netdev_priv(dev);
4096         struct mlx5_core_dev *mdev = priv->mdev;
4097         struct nlattr *attr, *br_spec;
4098         u16 mode = BRIDGE_MODE_UNDEF;
4099         u8 setting;
4100         int rem;
4101
4102         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4103         if (!br_spec)
4104                 return -EINVAL;
4105
4106         nla_for_each_nested(attr, br_spec, rem) {
4107                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4108                         continue;
4109
4110                 if (nla_len(attr) < sizeof(mode))
4111                         return -EINVAL;
4112
4113                 mode = nla_get_u16(attr);
4114                 if (mode > BRIDGE_MODE_VEPA)
4115                         return -EINVAL;
4116
4117                 break;
4118         }
4119
4120         if (mode == BRIDGE_MODE_UNDEF)
4121                 return -EINVAL;
4122
4123         setting = (mode == BRIDGE_MODE_VEPA) ?  1 : 0;
4124         return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4125 }
4126 #endif
4127
4128 const struct net_device_ops mlx5e_netdev_ops = {
4129         .ndo_open                = mlx5e_open,
4130         .ndo_stop                = mlx5e_close,
4131         .ndo_start_xmit          = mlx5e_xmit,
4132         .ndo_setup_tc            = mlx5e_setup_tc,
4133         .ndo_select_queue        = mlx5e_select_queue,
4134         .ndo_get_stats64         = mlx5e_get_stats,
4135         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4136         .ndo_set_mac_address     = mlx5e_set_mac,
4137         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4138         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4139         .ndo_set_features        = mlx5e_set_features,
4140         .ndo_fix_features        = mlx5e_fix_features,
4141         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4142         .ndo_eth_ioctl            = mlx5e_ioctl,
4143         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4144         .ndo_features_check      = mlx5e_features_check,
4145         .ndo_tx_timeout          = mlx5e_tx_timeout,
4146         .ndo_bpf                 = mlx5e_xdp,
4147         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4148         .ndo_xsk_wakeup          = mlx5e_xsk_wakeup,
4149 #ifdef CONFIG_MLX5_EN_ARFS
4150         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4151 #endif
4152 #ifdef CONFIG_MLX5_ESWITCH
4153         .ndo_bridge_setlink      = mlx5e_bridge_setlink,
4154         .ndo_bridge_getlink      = mlx5e_bridge_getlink,
4155
4156         /* SRIOV E-Switch NDOs */
4157         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4158         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4159         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4160         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4161         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4162         .ndo_get_vf_config       = mlx5e_get_vf_config,
4163         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4164         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4165         .ndo_has_offload_stats   = mlx5e_has_offload_stats,
4166         .ndo_get_offload_stats   = mlx5e_get_offload_stats,
4167 #endif
4168         .ndo_get_devlink_port    = mlx5e_get_devlink_port,
4169 };
4170
4171 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4172 {
4173         int i;
4174
4175         /* The supported periods are organized in ascending order */
4176         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4177                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4178                         break;
4179
4180         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4181 }
4182
4183 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu)
4184 {
4185         struct mlx5e_params *params = &priv->channels.params;
4186         struct mlx5_core_dev *mdev = priv->mdev;
4187         u8 rx_cq_period_mode;
4188
4189         priv->max_nch = mlx5e_calc_max_nch(priv, priv->profile);
4190
4191         params->sw_mtu = mtu;
4192         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4193         params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2,
4194                                      priv->max_nch);
4195         params->mqprio.num_tc = 1;
4196
4197         /* Set an initial non-zero value, so that mlx5e_select_queue won't
4198          * divide by zero if called before first activating channels.
4199          */
4200         priv->num_tc_x_num_ch = params->num_channels * params->mqprio.num_tc;
4201
4202         /* SQ */
4203         params->log_sq_size = is_kdump_kernel() ?
4204                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4205                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4206         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
4207
4208         /* XDP SQ */
4209         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
4210
4211         /* set CQE compression */
4212         params->rx_cqe_compress_def = false;
4213         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4214             MLX5_CAP_GEN(mdev, vport_group_manager))
4215                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4216
4217         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4218         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4219
4220         /* RQ */
4221         mlx5e_build_rq_params(mdev, params);
4222
4223         /* HW LRO */
4224         if (MLX5_CAP_ETH(mdev, lro_cap) &&
4225             params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4226                 /* No XSK params: checking the availability of striding RQ in general. */
4227                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4228                         params->lro_en = !slow_pci_heuristic(mdev);
4229         }
4230         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4231
4232         /* CQ moderation params */
4233         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4234                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4235                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4236         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4237         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4238         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4239         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4240
4241         /* TX inline */
4242         mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
4243
4244         params->tunneled_offload_en = mlx5_tunnel_inner_ft_supported(mdev);
4245
4246         /* AF_XDP */
4247         params->xsk = xsk;
4248
4249         /* Do not update netdev->features directly in here
4250          * on mlx5e_attach_netdev() we will call mlx5e_update_features()
4251          * To update netdev->features please modify mlx5e_fix_features()
4252          */
4253 }
4254
4255 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4256 {
4257         struct mlx5e_priv *priv = netdev_priv(netdev);
4258
4259         mlx5_query_mac_address(priv->mdev, netdev->dev_addr);
4260         if (is_zero_ether_addr(netdev->dev_addr) &&
4261             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4262                 eth_hw_addr_random(netdev);
4263                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4264         }
4265 }
4266
4267 static int mlx5e_vxlan_set_port(struct net_device *netdev, unsigned int table,
4268                                 unsigned int entry, struct udp_tunnel_info *ti)
4269 {
4270         struct mlx5e_priv *priv = netdev_priv(netdev);
4271
4272         return mlx5_vxlan_add_port(priv->mdev->vxlan, ntohs(ti->port));
4273 }
4274
4275 static int mlx5e_vxlan_unset_port(struct net_device *netdev, unsigned int table,
4276                                   unsigned int entry, struct udp_tunnel_info *ti)
4277 {
4278         struct mlx5e_priv *priv = netdev_priv(netdev);
4279
4280         return mlx5_vxlan_del_port(priv->mdev->vxlan, ntohs(ti->port));
4281 }
4282
4283 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv)
4284 {
4285         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4286                 return;
4287
4288         priv->nic_info.set_port = mlx5e_vxlan_set_port;
4289         priv->nic_info.unset_port = mlx5e_vxlan_unset_port;
4290         priv->nic_info.flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
4291                                 UDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN;
4292         priv->nic_info.tables[0].tunnel_types = UDP_TUNNEL_TYPE_VXLAN;
4293         /* Don't count the space hard-coded to the IANA port */
4294         priv->nic_info.tables[0].n_entries =
4295                 mlx5_vxlan_max_udp_ports(priv->mdev) - 1;
4296
4297         priv->netdev->udp_tunnel_nic_info = &priv->nic_info;
4298 }
4299
4300 static bool mlx5e_tunnel_any_tx_proto_supported(struct mlx5_core_dev *mdev)
4301 {
4302         int tt;
4303
4304         for (tt = 0; tt < MLX5_NUM_TUNNEL_TT; tt++) {
4305                 if (mlx5e_tunnel_proto_supported_tx(mdev, mlx5_get_proto_by_tunnel_type(tt)))
4306                         return true;
4307         }
4308         return (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev));
4309 }
4310
4311 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4312 {
4313         struct mlx5e_priv *priv = netdev_priv(netdev);
4314         struct mlx5_core_dev *mdev = priv->mdev;
4315         bool fcs_supported;
4316         bool fcs_enabled;
4317
4318         SET_NETDEV_DEV(netdev, mdev->device);
4319
4320         netdev->netdev_ops = &mlx5e_netdev_ops;
4321
4322         mlx5e_dcbnl_build_netdev(netdev);
4323
4324         netdev->watchdog_timeo    = 15 * HZ;
4325
4326         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4327
4328         netdev->vlan_features    |= NETIF_F_SG;
4329         netdev->vlan_features    |= NETIF_F_HW_CSUM;
4330         netdev->vlan_features    |= NETIF_F_GRO;
4331         netdev->vlan_features    |= NETIF_F_TSO;
4332         netdev->vlan_features    |= NETIF_F_TSO6;
4333         netdev->vlan_features    |= NETIF_F_RXCSUM;
4334         netdev->vlan_features    |= NETIF_F_RXHASH;
4335
4336         netdev->mpls_features    |= NETIF_F_SG;
4337         netdev->mpls_features    |= NETIF_F_HW_CSUM;
4338         netdev->mpls_features    |= NETIF_F_TSO;
4339         netdev->mpls_features    |= NETIF_F_TSO6;
4340
4341         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4342         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4343
4344         /* Tunneled LRO is not supported in the driver, and the same RQs are
4345          * shared between inner and outer TIRs, so the driver can't disable LRO
4346          * for inner TIRs while having it enabled for outer TIRs. Due to this,
4347          * block LRO altogether if the firmware declares tunneled LRO support.
4348          */
4349         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4350             !MLX5_CAP_ETH(mdev, tunnel_lro_vxlan) &&
4351             !MLX5_CAP_ETH(mdev, tunnel_lro_gre) &&
4352             mlx5e_check_fragmented_striding_rq_cap(mdev))
4353                 netdev->vlan_features    |= NETIF_F_LRO;
4354
4355         netdev->hw_features       = netdev->vlan_features;
4356         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4357         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4358         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4359         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4360
4361         if (mlx5e_tunnel_any_tx_proto_supported(mdev)) {
4362                 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4363                 netdev->hw_enc_features |= NETIF_F_TSO;
4364                 netdev->hw_enc_features |= NETIF_F_TSO6;
4365                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4366         }
4367
4368         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4369                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL;
4370                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
4371                 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL;
4372         }
4373
4374         if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_GRE)) {
4375                 netdev->hw_features     |= NETIF_F_GSO_GRE;
4376                 netdev->hw_enc_features |= NETIF_F_GSO_GRE;
4377                 netdev->gso_partial_features |= NETIF_F_GSO_GRE;
4378         }
4379
4380         if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_IPIP)) {
4381                 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
4382                                        NETIF_F_GSO_IPXIP6;
4383                 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
4384                                            NETIF_F_GSO_IPXIP6;
4385                 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
4386                                                 NETIF_F_GSO_IPXIP6;
4387         }
4388
4389         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4390         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4391         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4392         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4393
4394         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4395
4396         if (fcs_supported)
4397                 netdev->hw_features |= NETIF_F_RXALL;
4398
4399         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4400                 netdev->hw_features |= NETIF_F_RXFCS;
4401
4402         if (mlx5_qos_is_supported(mdev))
4403                 netdev->hw_features |= NETIF_F_HW_TC;
4404
4405         netdev->features          = netdev->hw_features;
4406
4407         /* Defaults */
4408         if (fcs_enabled)
4409                 netdev->features  &= ~NETIF_F_RXALL;
4410         netdev->features  &= ~NETIF_F_LRO;
4411         netdev->features  &= ~NETIF_F_RXFCS;
4412
4413 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4414         if (FT_CAP(flow_modify_en) &&
4415             FT_CAP(modify_root) &&
4416             FT_CAP(identified_miss_table_mode) &&
4417             FT_CAP(flow_table_modify)) {
4418 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
4419                 netdev->hw_features      |= NETIF_F_HW_TC;
4420 #endif
4421 #ifdef CONFIG_MLX5_EN_ARFS
4422                 netdev->hw_features      |= NETIF_F_NTUPLE;
4423 #endif
4424         }
4425
4426         netdev->features         |= NETIF_F_HIGHDMA;
4427         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4428
4429         netdev->priv_flags       |= IFF_UNICAST_FLT;
4430
4431         mlx5e_set_netdev_dev_addr(netdev);
4432         mlx5e_ipsec_build_netdev(priv);
4433         mlx5e_tls_build_netdev(priv);
4434 }
4435
4436 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4437 {
4438         u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {};
4439         u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {};
4440         struct mlx5_core_dev *mdev = priv->mdev;
4441         int err;
4442
4443         MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
4444         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4445         if (!err)
4446                 priv->q_counter =
4447                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4448
4449         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4450         if (!err)
4451                 priv->drop_rq_q_counter =
4452                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4453 }
4454
4455 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4456 {
4457         u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {};
4458
4459         MLX5_SET(dealloc_q_counter_in, in, opcode,
4460                  MLX5_CMD_OP_DEALLOC_Q_COUNTER);
4461         if (priv->q_counter) {
4462                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4463                          priv->q_counter);
4464                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4465         }
4466
4467         if (priv->drop_rq_q_counter) {
4468                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4469                          priv->drop_rq_q_counter);
4470                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4471         }
4472 }
4473
4474 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4475                           struct net_device *netdev)
4476 {
4477         struct mlx5e_priv *priv = netdev_priv(netdev);
4478         int err;
4479
4480         mlx5e_build_nic_params(priv, &priv->xsk, netdev->mtu);
4481         mlx5e_vxlan_set_netdev_info(priv);
4482
4483         mlx5e_timestamp_init(priv);
4484
4485         err = mlx5e_ipsec_init(priv);
4486         if (err)
4487                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4488
4489         err = mlx5e_tls_init(priv);
4490         if (err)
4491                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4492
4493         mlx5e_health_create_reporters(priv);
4494         return 0;
4495 }
4496
4497 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4498 {
4499         mlx5e_health_destroy_reporters(priv);
4500         mlx5e_tls_cleanup(priv);
4501         mlx5e_ipsec_cleanup(priv);
4502 }
4503
4504 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4505 {
4506         struct mlx5_core_dev *mdev = priv->mdev;
4507         enum mlx5e_rx_res_features features;
4508         struct mlx5e_lro_param lro_param;
4509         int err;
4510
4511         priv->rx_res = mlx5e_rx_res_alloc();
4512         if (!priv->rx_res)
4513                 return -ENOMEM;
4514
4515         mlx5e_create_q_counters(priv);
4516
4517         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4518         if (err) {
4519                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4520                 goto err_destroy_q_counters;
4521         }
4522
4523         features = MLX5E_RX_RES_FEATURE_XSK | MLX5E_RX_RES_FEATURE_PTP;
4524         if (priv->channels.params.tunneled_offload_en)
4525                 features |= MLX5E_RX_RES_FEATURE_INNER_FT;
4526         lro_param = mlx5e_get_lro_param(&priv->channels.params);
4527         err = mlx5e_rx_res_init(priv->rx_res, priv->mdev, features,
4528                                 priv->max_nch, priv->drop_rq.rqn, &lro_param,
4529                                 priv->channels.params.num_channels);
4530         if (err)
4531                 goto err_close_drop_rq;
4532
4533         err = mlx5e_create_flow_steering(priv);
4534         if (err) {
4535                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4536                 goto err_destroy_rx_res;
4537         }
4538
4539         err = mlx5e_tc_nic_init(priv);
4540         if (err)
4541                 goto err_destroy_flow_steering;
4542
4543         err = mlx5e_accel_init_rx(priv);
4544         if (err)
4545                 goto err_tc_nic_cleanup;
4546
4547 #ifdef CONFIG_MLX5_EN_ARFS
4548         priv->netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(priv->mdev);
4549 #endif
4550
4551         return 0;
4552
4553 err_tc_nic_cleanup:
4554         mlx5e_tc_nic_cleanup(priv);
4555 err_destroy_flow_steering:
4556         mlx5e_destroy_flow_steering(priv);
4557 err_destroy_rx_res:
4558         mlx5e_rx_res_destroy(priv->rx_res);
4559 err_close_drop_rq:
4560         mlx5e_close_drop_rq(&priv->drop_rq);
4561 err_destroy_q_counters:
4562         mlx5e_destroy_q_counters(priv);
4563         mlx5e_rx_res_free(priv->rx_res);
4564         priv->rx_res = NULL;
4565         return err;
4566 }
4567
4568 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4569 {
4570         mlx5e_accel_cleanup_rx(priv);
4571         mlx5e_tc_nic_cleanup(priv);
4572         mlx5e_destroy_flow_steering(priv);
4573         mlx5e_rx_res_destroy(priv->rx_res);
4574         mlx5e_close_drop_rq(&priv->drop_rq);
4575         mlx5e_destroy_q_counters(priv);
4576         mlx5e_rx_res_free(priv->rx_res);
4577         priv->rx_res = NULL;
4578 }
4579
4580 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4581 {
4582         int err;
4583
4584         err = mlx5e_create_tises(priv);
4585         if (err) {
4586                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4587                 return err;
4588         }
4589
4590         mlx5e_dcbnl_initialize(priv);
4591         return 0;
4592 }
4593
4594 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4595 {
4596         struct net_device *netdev = priv->netdev;
4597         struct mlx5_core_dev *mdev = priv->mdev;
4598
4599         mlx5e_init_l2_addr(priv);
4600
4601         /* Marking the link as currently not needed by the Driver */
4602         if (!netif_running(netdev))
4603                 mlx5e_modify_admin_state(mdev, MLX5_PORT_DOWN);
4604
4605         mlx5e_set_netdev_mtu_boundaries(priv);
4606         mlx5e_set_dev_port_mtu(priv);
4607
4608         mlx5_lag_add_netdev(mdev, netdev);
4609
4610         mlx5e_enable_async_events(priv);
4611         mlx5e_enable_blocking_events(priv);
4612         if (mlx5e_monitor_counter_supported(priv))
4613                 mlx5e_monitor_counter_init(priv);
4614
4615         mlx5e_hv_vhca_stats_create(priv);
4616         if (netdev->reg_state != NETREG_REGISTERED)
4617                 return;
4618         mlx5e_dcbnl_init_app(priv);
4619
4620         mlx5e_nic_set_rx_mode(priv);
4621
4622         rtnl_lock();
4623         if (netif_running(netdev))
4624                 mlx5e_open(netdev);
4625         udp_tunnel_nic_reset_ntf(priv->netdev);
4626         netif_device_attach(netdev);
4627         rtnl_unlock();
4628 }
4629
4630 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4631 {
4632         struct mlx5_core_dev *mdev = priv->mdev;
4633
4634         if (priv->netdev->reg_state == NETREG_REGISTERED)
4635                 mlx5e_dcbnl_delete_app(priv);
4636
4637         rtnl_lock();
4638         if (netif_running(priv->netdev))
4639                 mlx5e_close(priv->netdev);
4640         netif_device_detach(priv->netdev);
4641         rtnl_unlock();
4642
4643         mlx5e_nic_set_rx_mode(priv);
4644
4645         mlx5e_hv_vhca_stats_destroy(priv);
4646         if (mlx5e_monitor_counter_supported(priv))
4647                 mlx5e_monitor_counter_cleanup(priv);
4648
4649         mlx5e_disable_blocking_events(priv);
4650         if (priv->en_trap) {
4651                 mlx5e_deactivate_trap(priv);
4652                 mlx5e_close_trap(priv->en_trap);
4653                 priv->en_trap = NULL;
4654         }
4655         mlx5e_disable_async_events(priv);
4656         mlx5_lag_remove_netdev(mdev, priv->netdev);
4657         mlx5_vxlan_reset_to_default(mdev->vxlan);
4658 }
4659
4660 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
4661 {
4662         return mlx5e_refresh_tirs(priv, false, false);
4663 }
4664
4665 static const struct mlx5e_profile mlx5e_nic_profile = {
4666         .init              = mlx5e_nic_init,
4667         .cleanup           = mlx5e_nic_cleanup,
4668         .init_rx           = mlx5e_init_nic_rx,
4669         .cleanup_rx        = mlx5e_cleanup_nic_rx,
4670         .init_tx           = mlx5e_init_nic_tx,
4671         .cleanup_tx        = mlx5e_cleanup_nic_tx,
4672         .enable            = mlx5e_nic_enable,
4673         .disable           = mlx5e_nic_disable,
4674         .update_rx         = mlx5e_update_nic_rx,
4675         .update_stats      = mlx5e_stats_update_ndo_stats,
4676         .update_carrier    = mlx5e_update_carrier,
4677         .rx_handlers       = &mlx5e_rx_handlers_nic,
4678         .max_tc            = MLX5E_MAX_NUM_TC,
4679         .rq_groups         = MLX5E_NUM_RQ_GROUPS(XSK),
4680         .stats_grps        = mlx5e_nic_stats_grps,
4681         .stats_grps_num    = mlx5e_nic_stats_grps_num,
4682         .rx_ptp_support    = true,
4683 };
4684
4685 /* mlx5e generic netdev management API (move to en_common.c) */
4686 int mlx5e_priv_init(struct mlx5e_priv *priv,
4687                     struct net_device *netdev,
4688                     struct mlx5_core_dev *mdev)
4689 {
4690         /* priv init */
4691         priv->mdev        = mdev;
4692         priv->netdev      = netdev;
4693         priv->msglevel    = MLX5E_MSG_LEVEL;
4694         priv->max_opened_tc = 1;
4695
4696         if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL))
4697                 return -ENOMEM;
4698
4699         mutex_init(&priv->state_lock);
4700         hash_init(priv->htb.qos_tc2node);
4701         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4702         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4703         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
4704         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4705
4706         priv->wq = create_singlethread_workqueue("mlx5e");
4707         if (!priv->wq)
4708                 goto err_free_cpumask;
4709
4710         return 0;
4711
4712 err_free_cpumask:
4713         free_cpumask_var(priv->scratchpad.cpumask);
4714
4715         return -ENOMEM;
4716 }
4717
4718 void mlx5e_priv_cleanup(struct mlx5e_priv *priv)
4719 {
4720         int i;
4721
4722         /* bail if change profile failed and also rollback failed */
4723         if (!priv->mdev)
4724                 return;
4725
4726         destroy_workqueue(priv->wq);
4727         free_cpumask_var(priv->scratchpad.cpumask);
4728
4729         for (i = 0; i < priv->htb.max_qos_sqs; i++)
4730                 kfree(priv->htb.qos_sq_stats[i]);
4731         kvfree(priv->htb.qos_sq_stats);
4732
4733         memset(priv, 0, sizeof(*priv));
4734 }
4735
4736 struct net_device *
4737 mlx5e_create_netdev(struct mlx5_core_dev *mdev, unsigned int txqs, unsigned int rxqs)
4738 {
4739         struct net_device *netdev;
4740         int err;
4741
4742         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), txqs, rxqs);
4743         if (!netdev) {
4744                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4745                 return NULL;
4746         }
4747
4748         err = mlx5e_priv_init(netdev_priv(netdev), netdev, mdev);
4749         if (err) {
4750                 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
4751                 goto err_free_netdev;
4752         }
4753
4754         netif_carrier_off(netdev);
4755         dev_net_set(netdev, mlx5_core_net(mdev));
4756
4757         return netdev;
4758
4759 err_free_netdev:
4760         free_netdev(netdev);
4761
4762         return NULL;
4763 }
4764
4765 static void mlx5e_update_features(struct net_device *netdev)
4766 {
4767         if (netdev->reg_state != NETREG_REGISTERED)
4768                 return; /* features will be updated on netdev registration */
4769
4770         rtnl_lock();
4771         netdev_update_features(netdev);
4772         rtnl_unlock();
4773 }
4774
4775 static void mlx5e_reset_channels(struct net_device *netdev)
4776 {
4777         netdev_reset_tc(netdev);
4778 }
4779
4780 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
4781 {
4782         const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED;
4783         const struct mlx5e_profile *profile = priv->profile;
4784         int max_nch;
4785         int err;
4786
4787         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
4788
4789         /* max number of channels may have changed */
4790         max_nch = mlx5e_get_max_num_channels(priv->mdev);
4791         if (priv->channels.params.num_channels > max_nch) {
4792                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
4793                 /* Reducing the number of channels - RXFH has to be reset, and
4794                  * mlx5e_num_channels_changed below will build the RQT.
4795                  */
4796                 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED;
4797                 priv->channels.params.num_channels = max_nch;
4798         }
4799         /* 1. Set the real number of queues in the kernel the first time.
4800          * 2. Set our default XPS cpumask.
4801          * 3. Build the RQT.
4802          *
4803          * rtnl_lock is required by netif_set_real_num_*_queues in case the
4804          * netdev has been registered by this point (if this function was called
4805          * in the reload or resume flow).
4806          */
4807         if (take_rtnl)
4808                 rtnl_lock();
4809         err = mlx5e_num_channels_changed(priv);
4810         if (take_rtnl)
4811                 rtnl_unlock();
4812         if (err)
4813                 goto out;
4814
4815         err = profile->init_tx(priv);
4816         if (err)
4817                 goto out;
4818
4819         err = profile->init_rx(priv);
4820         if (err)
4821                 goto err_cleanup_tx;
4822
4823         if (profile->enable)
4824                 profile->enable(priv);
4825
4826         mlx5e_update_features(priv->netdev);
4827
4828         return 0;
4829
4830 err_cleanup_tx:
4831         profile->cleanup_tx(priv);
4832
4833 out:
4834         mlx5e_reset_channels(priv->netdev);
4835         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
4836         cancel_work_sync(&priv->update_stats_work);
4837         return err;
4838 }
4839
4840 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
4841 {
4842         const struct mlx5e_profile *profile = priv->profile;
4843
4844         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
4845
4846         if (profile->disable)
4847                 profile->disable(priv);
4848         flush_workqueue(priv->wq);
4849
4850         profile->cleanup_rx(priv);
4851         profile->cleanup_tx(priv);
4852         mlx5e_reset_channels(priv->netdev);
4853         cancel_work_sync(&priv->update_stats_work);
4854 }
4855
4856 static int
4857 mlx5e_netdev_attach_profile(struct net_device *netdev, struct mlx5_core_dev *mdev,
4858                             const struct mlx5e_profile *new_profile, void *new_ppriv)
4859 {
4860         struct mlx5e_priv *priv = netdev_priv(netdev);
4861         int err;
4862
4863         err = mlx5e_priv_init(priv, netdev, mdev);
4864         if (err) {
4865                 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
4866                 return err;
4867         }
4868         netif_carrier_off(netdev);
4869         priv->profile = new_profile;
4870         priv->ppriv = new_ppriv;
4871         err = new_profile->init(priv->mdev, priv->netdev);
4872         if (err)
4873                 goto priv_cleanup;
4874         err = mlx5e_attach_netdev(priv);
4875         if (err)
4876                 goto profile_cleanup;
4877         return err;
4878
4879 profile_cleanup:
4880         new_profile->cleanup(priv);
4881 priv_cleanup:
4882         mlx5e_priv_cleanup(priv);
4883         return err;
4884 }
4885
4886 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
4887                                 const struct mlx5e_profile *new_profile, void *new_ppriv)
4888 {
4889         unsigned int new_max_nch = mlx5e_calc_max_nch(priv, new_profile);
4890         const struct mlx5e_profile *orig_profile = priv->profile;
4891         struct net_device *netdev = priv->netdev;
4892         struct mlx5_core_dev *mdev = priv->mdev;
4893         void *orig_ppriv = priv->ppriv;
4894         int err, rollback_err;
4895
4896         /* sanity */
4897         if (new_max_nch != priv->max_nch) {
4898                 netdev_warn(netdev, "%s: Replacing profile with different max channels\n",
4899                             __func__);
4900                 return -EINVAL;
4901         }
4902
4903         /* cleanup old profile */
4904         mlx5e_detach_netdev(priv);
4905         priv->profile->cleanup(priv);
4906         mlx5e_priv_cleanup(priv);
4907
4908         err = mlx5e_netdev_attach_profile(netdev, mdev, new_profile, new_ppriv);
4909         if (err) { /* roll back to original profile */
4910                 netdev_warn(netdev, "%s: new profile init failed, %d\n", __func__, err);
4911                 goto rollback;
4912         }
4913
4914         return 0;
4915
4916 rollback:
4917         rollback_err = mlx5e_netdev_attach_profile(netdev, mdev, orig_profile, orig_ppriv);
4918         if (rollback_err)
4919                 netdev_err(netdev, "%s: failed to rollback to orig profile, %d\n",
4920                            __func__, rollback_err);
4921         return err;
4922 }
4923
4924 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv)
4925 {
4926         mlx5e_netdev_change_profile(priv, &mlx5e_nic_profile, NULL);
4927 }
4928
4929 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
4930 {
4931         struct net_device *netdev = priv->netdev;
4932
4933         mlx5e_priv_cleanup(priv);
4934         free_netdev(netdev);
4935 }
4936
4937 static int mlx5e_resume(struct auxiliary_device *adev)
4938 {
4939         struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
4940         struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
4941         struct net_device *netdev = priv->netdev;
4942         struct mlx5_core_dev *mdev = edev->mdev;
4943         int err;
4944
4945         if (netif_device_present(netdev))
4946                 return 0;
4947
4948         err = mlx5e_create_mdev_resources(mdev);
4949         if (err)
4950                 return err;
4951
4952         err = mlx5e_attach_netdev(priv);
4953         if (err) {
4954                 mlx5e_destroy_mdev_resources(mdev);
4955                 return err;
4956         }
4957
4958         return 0;
4959 }
4960
4961 static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state)
4962 {
4963         struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
4964         struct net_device *netdev = priv->netdev;
4965         struct mlx5_core_dev *mdev = priv->mdev;
4966
4967         if (!netif_device_present(netdev))
4968                 return -ENODEV;
4969
4970         mlx5e_detach_netdev(priv);
4971         mlx5e_destroy_mdev_resources(mdev);
4972         return 0;
4973 }
4974
4975 static int mlx5e_probe(struct auxiliary_device *adev,
4976                        const struct auxiliary_device_id *id)
4977 {
4978         struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
4979         const struct mlx5e_profile *profile = &mlx5e_nic_profile;
4980         struct mlx5_core_dev *mdev = edev->mdev;
4981         struct net_device *netdev;
4982         pm_message_t state = {};
4983         unsigned int txqs, rxqs, ptp_txqs = 0;
4984         struct mlx5e_priv *priv;
4985         int qos_sqs = 0;
4986         int err;
4987         int nch;
4988
4989         if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn))
4990                 ptp_txqs = profile->max_tc;
4991
4992         if (mlx5_qos_is_supported(mdev))
4993                 qos_sqs = mlx5e_qos_max_leaf_nodes(mdev);
4994
4995         nch = mlx5e_get_max_num_channels(mdev);
4996         txqs = nch * profile->max_tc + ptp_txqs + qos_sqs;
4997         rxqs = nch * profile->rq_groups;
4998         netdev = mlx5e_create_netdev(mdev, txqs, rxqs);
4999         if (!netdev) {
5000                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5001                 return -ENOMEM;
5002         }
5003
5004         mlx5e_build_nic_netdev(netdev);
5005
5006         priv = netdev_priv(netdev);
5007         dev_set_drvdata(&adev->dev, priv);
5008
5009         priv->profile = profile;
5010         priv->ppriv = NULL;
5011
5012         err = mlx5e_devlink_port_register(priv);
5013         if (err) {
5014                 mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err);
5015                 goto err_destroy_netdev;
5016         }
5017
5018         err = profile->init(mdev, netdev);
5019         if (err) {
5020                 mlx5_core_err(mdev, "mlx5e_nic_profile init failed, %d\n", err);
5021                 goto err_devlink_cleanup;
5022         }
5023
5024         err = mlx5e_resume(adev);
5025         if (err) {
5026                 mlx5_core_err(mdev, "mlx5e_resume failed, %d\n", err);
5027                 goto err_profile_cleanup;
5028         }
5029
5030         err = register_netdev(netdev);
5031         if (err) {
5032                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5033                 goto err_resume;
5034         }
5035
5036         mlx5e_devlink_port_type_eth_set(priv);
5037
5038         mlx5e_dcbnl_init_app(priv);
5039         mlx5_uplink_netdev_set(mdev, netdev);
5040         return 0;
5041
5042 err_resume:
5043         mlx5e_suspend(adev, state);
5044 err_profile_cleanup:
5045         profile->cleanup(priv);
5046 err_devlink_cleanup:
5047         mlx5e_devlink_port_unregister(priv);
5048 err_destroy_netdev:
5049         mlx5e_destroy_netdev(priv);
5050         return err;
5051 }
5052
5053 static void mlx5e_remove(struct auxiliary_device *adev)
5054 {
5055         struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5056         pm_message_t state = {};
5057
5058         mlx5e_dcbnl_delete_app(priv);
5059         unregister_netdev(priv->netdev);
5060         mlx5e_suspend(adev, state);
5061         priv->profile->cleanup(priv);
5062         mlx5e_devlink_port_unregister(priv);
5063         mlx5e_destroy_netdev(priv);
5064 }
5065
5066 static const struct auxiliary_device_id mlx5e_id_table[] = {
5067         { .name = MLX5_ADEV_NAME ".eth", },
5068         {},
5069 };
5070
5071 MODULE_DEVICE_TABLE(auxiliary, mlx5e_id_table);
5072
5073 static struct auxiliary_driver mlx5e_driver = {
5074         .name = "eth",
5075         .probe = mlx5e_probe,
5076         .remove = mlx5e_remove,
5077         .suspend = mlx5e_suspend,
5078         .resume = mlx5e_resume,
5079         .id_table = mlx5e_id_table,
5080 };
5081
5082 int mlx5e_init(void)
5083 {
5084         int ret;
5085
5086         mlx5e_ipsec_build_inverse_table();
5087         mlx5e_build_ptys2ethtool_map();
5088         ret = auxiliary_driver_register(&mlx5e_driver);
5089         if (ret)
5090                 return ret;
5091
5092         ret = mlx5e_rep_init();
5093         if (ret)
5094                 auxiliary_driver_unregister(&mlx5e_driver);
5095         return ret;
5096 }
5097
5098 void mlx5e_cleanup(void)
5099 {
5100         mlx5e_rep_cleanup();
5101         auxiliary_driver_unregister(&mlx5e_driver);
5102 }