drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <net/geneve.h>
  38 #include <linux/bpf.h>
  39 #include <linux/if_bridge.h>
  40 #include <linux/filter.h>
  41 #include <net/page_pool.h>
  42 #include <net/xdp_sock_drv.h>
  43 #include "eswitch.h"
  44 #include "en.h"
  45 #include "en/txrx.h"
  46 #include "en_tc.h"
  47 #include "en_rep.h"
  48 #include "en_accel/ipsec.h"
  49 #include "en_accel/en_accel.h"
  50 #include "en_accel/ktls.h"
  51 #include "en_accel/ipsec_offload.h"
  52 #include "lib/vxlan.h"
  53 #include "lib/clock.h"
  54 #include "en/port.h"
  55 #include "en/xdp.h"
  56 #include "lib/eq.h"
  57 #include "en/monitor_stats.h"
  58 #include "en/health.h"
  59 #include "en/params.h"
  60 #include "en/xsk/pool.h"
  61 #include "en/xsk/setup.h"
  62 #include "en/xsk/rx.h"
  63 #include "en/xsk/tx.h"
  64 #include "en/hv_vhca_stats.h"
  65 #include "en/devlink.h"
  66 #include "lib/mlx5.h"
  67 #include "en/ptp.h"
  68 #include "qos.h"
  69 #include "en/trap.h"
  70
  71 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  72 {
  73         bool striding_rq_umr, inline_umr;
  74         u16 max_wqe_sz_cap;
  75
  76         striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) && MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  77                           MLX5_CAP_ETH(mdev, reg_umr_sq);
  78         max_wqe_sz_cap = mlx5e_get_max_sq_wqebbs(mdev) * MLX5_SEND_WQE_BB;
  79         inline_umr = max_wqe_sz_cap >= MLX5E_UMR_WQE_INLINE_SZ;
  80         if (!striding_rq_umr)
  81                 return false;
  82         if (!inline_umr) {
  83                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  84                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  85                 return false;
  86         }
  87         return true;
  88 }
  89
  90 void mlx5e_update_carrier(struct mlx5e_priv *priv)
  91 {
  92         struct mlx5_core_dev *mdev = priv->mdev;
  93         u8 port_state;
  94         bool up;
  95
  96         port_state = mlx5_query_vport_state(mdev,
  97                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
  98                                             0);
  99
 100         up = port_state == VPORT_STATE_UP;
 101         if (up == netif_carrier_ok(priv->netdev))
 102                 netif_carrier_event(priv->netdev);
 103         if (up) {
 104                 netdev_info(priv->netdev, "Link up\n");
 105                 netif_carrier_on(priv->netdev);
 106         } else {
 107                 netdev_info(priv->netdev, "Link down\n");
 108                 netif_carrier_off(priv->netdev);
 109         }
 110 }
 111
 112 static void mlx5e_update_carrier_work(struct work_struct *work)
 113 {
 114         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 115                                                update_carrier_work);
 116
 117         mutex_lock(&priv->state_lock);
 118         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 119                 if (priv->profile->update_carrier)
 120                         priv->profile->update_carrier(priv);
 121         mutex_unlock(&priv->state_lock);
 122 }
 123
 124 static void mlx5e_update_stats_work(struct work_struct *work)
 125 {
 126         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 127                                                update_stats_work);
 128
 129         mutex_lock(&priv->state_lock);
 130         priv->profile->update_stats(priv);
 131         mutex_unlock(&priv->state_lock);
 132 }
 133
 134 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 135 {
 136         if (!priv->profile->update_stats)
 137                 return;
 138
 139         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 140                 return;
 141
 142         queue_work(priv->wq, &priv->update_stats_work);
 143 }
 144
 145 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
 146 {
 147         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
 148         struct mlx5_eqe   *eqe = data;
 149
 150         if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
 151                 return NOTIFY_DONE;
 152
 153         switch (eqe->sub_type) {
 154         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 155         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 156                 queue_work(priv->wq, &priv->update_carrier_work);
 157                 break;
 158         default:
 159                 return NOTIFY_DONE;
 160         }
 161
 162         return NOTIFY_OK;
 163 }
 164
 165 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 166 {
 167         priv->events_nb.notifier_call = async_event;
 168         mlx5_notifier_register(priv->mdev, &priv->events_nb);
 169 }
 170
 171 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 172 {
 173         mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
 174 }
 175
 176 static int blocking_event(struct notifier_block *nb, unsigned long event, void *data)
 177 {
 178         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, blocking_events_nb);
 179         int err;
 180
 181         switch (event) {
 182         case MLX5_DRIVER_EVENT_TYPE_TRAP:
 183                 err = mlx5e_handle_trap_event(priv, data);
 184                 break;
 185         default:
 186                 netdev_warn(priv->netdev, "Sync event: Unknown event %ld\n", event);
 187                 err = -EINVAL;
 188         }
 189         return err;
 190 }
 191
 192 static void mlx5e_enable_blocking_events(struct mlx5e_priv *priv)
 193 {
 194         priv->blocking_events_nb.notifier_call = blocking_event;
 195         mlx5_blocking_notifier_register(priv->mdev, &priv->blocking_events_nb);
 196 }
 197
 198 static void mlx5e_disable_blocking_events(struct mlx5e_priv *priv)
 199 {
 200         mlx5_blocking_notifier_unregister(priv->mdev, &priv->blocking_events_nb);
 201 }
 202
 203 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 204                                        struct mlx5e_icosq *sq,
 205                                        struct mlx5e_umr_wqe *wqe)
 206 {
 207         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 208         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 209         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 210
 211         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 212                                       ds_cnt);
 213         cseg->umr_mkey  = rq->mkey_be;
 214
 215         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 216         ucseg->xlt_octowords =
 217                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 218         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 219 }
 220
 221 static int mlx5e_rq_shampo_hd_alloc(struct mlx5e_rq *rq, int node)
 222 {
 223         rq->mpwqe.shampo = kvzalloc_node(sizeof(*rq->mpwqe.shampo),
 224                                          GFP_KERNEL, node);
 225         if (!rq->mpwqe.shampo)
 226                 return -ENOMEM;
 227         return 0;
 228 }
 229
 230 static void mlx5e_rq_shampo_hd_free(struct mlx5e_rq *rq)
 231 {
 232         kvfree(rq->mpwqe.shampo);
 233 }
 234
 235 static int mlx5e_rq_shampo_hd_info_alloc(struct mlx5e_rq *rq, int node)
 236 {
 237         struct mlx5e_shampo_hd *shampo = rq->mpwqe.shampo;
 238
 239         shampo->bitmap = bitmap_zalloc_node(shampo->hd_per_wq, GFP_KERNEL,
 240                                             node);
 241         if (!shampo->bitmap)
 242                 return -ENOMEM;
 243
 244         shampo->info = kvzalloc_node(array_size(shampo->hd_per_wq,
 245                                                 sizeof(*shampo->info)),
 246                                      GFP_KERNEL, node);
 247         if (!shampo->info) {
 248                 kvfree(shampo->bitmap);
 249                 return -ENOMEM;
 250         }
 251         return 0;
 252 }
 253
 254 static void mlx5e_rq_shampo_hd_info_free(struct mlx5e_rq *rq)
 255 {
 256         kvfree(rq->mpwqe.shampo->bitmap);
 257         kvfree(rq->mpwqe.shampo->info);
 258 }
 259
 260 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, int node)
 261 {
 262         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 263
 264         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 265                                                   sizeof(*rq->mpwqe.info)),
 266                                        GFP_KERNEL, node);
 267         if (!rq->mpwqe.info)
 268                 return -ENOMEM;
 269
 270         mlx5e_build_umr_wqe(rq, rq->icosq, &rq->mpwqe.umr_wqe);
 271
 272         return 0;
 273 }
 274
 275 static int mlx5e_create_umr_mtt_mkey(struct mlx5_core_dev *mdev,
 276                                      u64 npages, u8 page_shift, u32 *umr_mkey,
 277                                      dma_addr_t filler_addr)
 278 {
 279         struct mlx5_mtt *mtt;
 280         int inlen;
 281         void *mkc;
 282         u32 *in;
 283         int err;
 284         int i;
 285
 286         inlen = MLX5_ST_SZ_BYTES(create_mkey_in) + sizeof(*mtt) * npages;
 287
 288         in = kvzalloc(inlen, GFP_KERNEL);
 289         if (!in)
 290                 return -ENOMEM;
 291
 292         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 293
 294         MLX5_SET(mkc, mkc, free, 1);
 295         MLX5_SET(mkc, mkc, umr_en, 1);
 296         MLX5_SET(mkc, mkc, lw, 1);
 297         MLX5_SET(mkc, mkc, lr, 1);
 298         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 299         mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
 300         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 301         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
 302         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 303         MLX5_SET(mkc, mkc, translations_octword_size,
 304                  MLX5_MTT_OCTW(npages));
 305         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 306         MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
 307                  MLX5_MTT_OCTW(npages));
 308
 309         /* Initialize the mkey with all MTTs pointing to a default
 310          * page (filler_addr). When the channels are activated, UMR
 311          * WQEs will redirect the RX WQEs to the actual memory from
 312          * the RQ's pool, while the gaps (wqe_overflow) remain mapped
 313          * to the default page.
 314          */
 315         mtt = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
 316         for (i = 0 ; i < npages ; i++)
 317                 mtt[i].ptag = cpu_to_be64(filler_addr);
 318
 319         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 320
 321         kvfree(in);
 322         return err;
 323 }
 324
 325 static int mlx5e_create_umr_klm_mkey(struct mlx5_core_dev *mdev,
 326                                      u64 nentries,
 327                                      u32 *umr_mkey)
 328 {
 329         int inlen;
 330         void *mkc;
 331         u32 *in;
 332         int err;
 333
 334         inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 335
 336         in = kvzalloc(inlen, GFP_KERNEL);
 337         if (!in)
 338                 return -ENOMEM;
 339
 340         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 341
 342         MLX5_SET(mkc, mkc, free, 1);
 343         MLX5_SET(mkc, mkc, umr_en, 1);
 344         MLX5_SET(mkc, mkc, lw, 1);
 345         MLX5_SET(mkc, mkc, lr, 1);
 346         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_KLMS);
 347         mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
 348         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 349         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
 350         MLX5_SET(mkc, mkc, translations_octword_size, nentries);
 351         MLX5_SET(mkc, mkc, length64, 1);
 352         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 353
 354         kvfree(in);
 355         return err;
 356 }
 357
 358 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 359 {
 360         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 361
 362         return mlx5e_create_umr_mtt_mkey(mdev, num_mtts, PAGE_SHIFT,
 363                                          &rq->umr_mkey, rq->wqe_overflow.addr);
 364 }
 365
 366 static int mlx5e_create_rq_hd_umr_mkey(struct mlx5_core_dev *mdev,
 367                                        struct mlx5e_rq *rq)
 368 {
 369         u32 max_klm_size = BIT(MLX5_CAP_GEN(mdev, log_max_klm_list_size));
 370
 371         if (max_klm_size < rq->mpwqe.shampo->hd_per_wq) {
 372                 mlx5_core_err(mdev, "max klm list size 0x%x is smaller than shampo header buffer list size 0x%x\n",
 373                               max_klm_size, rq->mpwqe.shampo->hd_per_wq);
 374                 return -EINVAL;
 375         }
 376         return mlx5e_create_umr_klm_mkey(mdev, rq->mpwqe.shampo->hd_per_wq,
 377                                          &rq->mpwqe.shampo->mkey);
 378 }
 379
 380 static u64 mlx5e_get_mpwqe_offset(u16 wqe_ix)
 381 {
 382         return MLX5E_REQUIRED_MTTS(wqe_ix) << PAGE_SHIFT;
 383 }
 384
 385 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 386 {
 387         struct mlx5e_wqe_frag_info next_frag = {};
 388         struct mlx5e_wqe_frag_info *prev = NULL;
 389         int i;
 390
 391         next_frag.di = &rq->wqe.di[0];
 392
 393         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 394                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 395                 struct mlx5e_wqe_frag_info *frag =
 396                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 397                 int f;
 398
 399                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 400                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 401                                 next_frag.di++;
 402                                 next_frag.offset = 0;
 403                                 if (prev)
 404                                         prev->last_in_page = true;
 405                         }
 406                         *frag = next_frag;
 407
 408                         /* prepare next */
 409                         next_frag.offset += frag_info[f].frag_stride;
 410                         prev = frag;
 411                 }
 412         }
 413
 414         if (prev)
 415                 prev->last_in_page = true;
 416 }
 417
 418 int mlx5e_init_di_list(struct mlx5e_rq *rq, int wq_sz, int node)
 419 {
 420         int len = wq_sz << rq->wqe.info.log_num_frags;
 421
 422         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)), GFP_KERNEL, node);
 423         if (!rq->wqe.di)
 424                 return -ENOMEM;
 425
 426         mlx5e_init_frags_partition(rq);
 427
 428         return 0;
 429 }
 430
 431 void mlx5e_free_di_list(struct mlx5e_rq *rq)
 432 {
 433         kvfree(rq->wqe.di);
 434 }
 435
 436 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
 437 {
 438         struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
 439
 440         mlx5e_reporter_rq_cqe_err(rq);
 441 }
 442
 443 static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
 444 {
 445         rq->wqe_overflow.page = alloc_page(GFP_KERNEL);
 446         if (!rq->wqe_overflow.page)
 447                 return -ENOMEM;
 448
 449         rq->wqe_overflow.addr = dma_map_page(rq->pdev, rq->wqe_overflow.page, 0,
 450                                              PAGE_SIZE, rq->buff.map_dir);
 451         if (dma_mapping_error(rq->pdev, rq->wqe_overflow.addr)) {
 452                 __free_page(rq->wqe_overflow.page);
 453                 return -ENOMEM;
 454         }
 455         return 0;
 456 }
 457
 458 static void mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
 459 {
 460          dma_unmap_page(rq->pdev, rq->wqe_overflow.addr, PAGE_SIZE,
 461                         rq->buff.map_dir);
 462          __free_page(rq->wqe_overflow.page);
 463 }
 464
 465 static int mlx5e_init_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
 466                              struct mlx5e_rq *rq)
 467 {
 468         struct mlx5_core_dev *mdev = c->mdev;
 469         int err;
 470
 471         rq->wq_type      = params->rq_wq_type;
 472         rq->pdev         = c->pdev;
 473         rq->netdev       = c->netdev;
 474         rq->priv         = c->priv;
 475         rq->tstamp       = c->tstamp;
 476         rq->clock        = &mdev->clock;
 477         rq->icosq        = &c->icosq;
 478         rq->ix           = c->ix;
 479         rq->mdev         = mdev;
 480         rq->hw_mtu       = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 481         rq->xdpsq        = &c->rq_xdpsq;
 482         rq->stats        = &c->priv->channel_stats[c->ix]->rq;
 483         rq->ptp_cyc2time = mlx5_rq_ts_translator(mdev);
 484         err = mlx5e_rq_set_handlers(rq, params, NULL);
 485         if (err)
 486                 return err;
 487
 488         return xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix, 0);
 489 }
 490
 491 static int mlx5_rq_shampo_alloc(struct mlx5_core_dev *mdev,
 492                                 struct mlx5e_params *params,
 493                                 struct mlx5e_rq_param *rqp,
 494                                 struct mlx5e_rq *rq,
 495                                 u32 *pool_size,
 496                                 int node)
 497 {
 498         void *wqc = MLX5_ADDR_OF(rqc, rqp->rqc, wq);
 499         int wq_size;
 500         int err;
 501
 502         if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
 503                 return 0;
 504         err = mlx5e_rq_shampo_hd_alloc(rq, node);
 505         if (err)
 506                 goto out;
 507         rq->mpwqe.shampo->hd_per_wq =
 508                 mlx5e_shampo_hd_per_wq(mdev, params, rqp);
 509         err = mlx5e_create_rq_hd_umr_mkey(mdev, rq);
 510         if (err)
 511                 goto err_shampo_hd;
 512         err = mlx5e_rq_shampo_hd_info_alloc(rq, node);
 513         if (err)
 514                 goto err_shampo_info;
 515         rq->hw_gro_data = kvzalloc_node(sizeof(*rq->hw_gro_data), GFP_KERNEL, node);
 516         if (!rq->hw_gro_data) {
 517                 err = -ENOMEM;
 518                 goto err_hw_gro_data;
 519         }
 520         rq->mpwqe.shampo->key =
 521                 cpu_to_be32(rq->mpwqe.shampo->mkey);
 522         rq->mpwqe.shampo->hd_per_wqe =
 523                 mlx5e_shampo_hd_per_wqe(mdev, params, rqp);
 524         wq_size = BIT(MLX5_GET(wq, wqc, log_wq_sz));
 525         *pool_size += (rq->mpwqe.shampo->hd_per_wqe * wq_size) /
 526                      MLX5E_SHAMPO_WQ_HEADER_PER_PAGE;
 527         return 0;
 528
 529 err_hw_gro_data:
 530         mlx5e_rq_shampo_hd_info_free(rq);
 531 err_shampo_info:
 532         mlx5_core_destroy_mkey(mdev, rq->mpwqe.shampo->mkey);
 533 err_shampo_hd:
 534         mlx5e_rq_shampo_hd_free(rq);
 535 out:
 536         return err;
 537 }
 538
 539 static void mlx5e_rq_free_shampo(struct mlx5e_rq *rq)
 540 {
 541         if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
 542                 return;
 543
 544         kvfree(rq->hw_gro_data);
 545         mlx5e_rq_shampo_hd_info_free(rq);
 546         mlx5_core_destroy_mkey(rq->mdev, rq->mpwqe.shampo->mkey);
 547         mlx5e_rq_shampo_hd_free(rq);
 548 }
 549
 550 static int mlx5e_alloc_rq(struct mlx5e_params *params,
 551                           struct mlx5e_xsk_param *xsk,
 552                           struct mlx5e_rq_param *rqp,
 553                           int node, struct mlx5e_rq *rq)
 554 {
 555         struct page_pool_params pp_params = { 0 };
 556         struct mlx5_core_dev *mdev = rq->mdev;
 557         void *rqc = rqp->rqc;
 558         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 559         u32 pool_size;
 560         int wq_sz;
 561         int err;
 562         int i;
 563
 564         rqp->wq.db_numa_node = node;
 565         INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
 566
 567         if (params->xdp_prog)
 568                 bpf_prog_inc(params->xdp_prog);
 569         RCU_INIT_POINTER(rq->xdp_prog, params->xdp_prog);
 570
 571         rq->buff.map_dir = params->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 572         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
 573         pool_size = 1 << params->log_rq_mtu_frames;
 574
 575         switch (rq->wq_type) {
 576         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 577                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 578                                         &rq->wq_ctrl);
 579                 if (err)
 580                         goto err_rq_xdp_prog;
 581
 582                 err = mlx5e_alloc_mpwqe_rq_drop_page(rq);
 583                 if (err)
 584                         goto err_rq_wq_destroy;
 585
 586                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 587
 588                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 589
 590                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
 591                         mlx5e_mpwqe_get_log_rq_size(params, xsk);
 592
 593                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
 594                 rq->mpwqe.num_strides =
 595                         BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
 596                 rq->mpwqe.min_wqe_bulk = mlx5e_mpwqe_get_min_wqe_bulk(wq_sz);
 597
 598                 rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz);
 599
 600                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 601                 if (err)
 602                         goto err_rq_drop_page;
 603                 rq->mkey_be = cpu_to_be32(rq->umr_mkey);
 604
 605                 err = mlx5e_rq_alloc_mpwqe_info(rq, node);
 606                 if (err)
 607                         goto err_rq_mkey;
 608
 609                 err = mlx5_rq_shampo_alloc(mdev, params, rqp, rq, &pool_size, node);
 610                 if (err)
 611                         goto err_free_by_rq_type;
 612
 613                 break;
 614         default: /* MLX5_WQ_TYPE_CYCLIC */
 615                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 616                                          &rq->wq_ctrl);
 617                 if (err)
 618                         goto err_rq_xdp_prog;
 619
 620                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 621
 622                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 623
 624                 rq->wqe.info = rqp->frags_info;
 625                 rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride;
 626
 627                 rq->wqe.frags =
 628                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 629                                         (wq_sz << rq->wqe.info.log_num_frags)),
 630                                       GFP_KERNEL, node);
 631                 if (!rq->wqe.frags) {
 632                         err = -ENOMEM;
 633                         goto err_rq_wq_destroy;
 634                 }
 635
 636                 err = mlx5e_init_di_list(rq, wq_sz, node);
 637                 if (err)
 638                         goto err_rq_frags;
 639
 640                 rq->mkey_be = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey);
 641         }
 642
 643         if (xsk) {
 644                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 645                                                  MEM_TYPE_XSK_BUFF_POOL, NULL);
 646                 xsk_pool_set_rxq_info(rq->xsk_pool, &rq->xdp_rxq);
 647         } else {
 648                 /* Create a page_pool and register it with rxq */
 649                 pp_params.order     = 0;
 650                 pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 651                 pp_params.pool_size = pool_size;
 652                 pp_params.nid       = node;
 653                 pp_params.dev       = rq->pdev;
 654                 pp_params.dma_dir   = rq->buff.map_dir;
 655
 656                 /* page_pool can be used even when there is no rq->xdp_prog,
 657                  * given page_pool does not handle DMA mapping there is no
 658                  * required state to clear. And page_pool gracefully handle
 659                  * elevated refcnt.
 660                  */
 661                 rq->page_pool = page_pool_create(&pp_params);
 662                 if (IS_ERR(rq->page_pool)) {
 663                         err = PTR_ERR(rq->page_pool);
 664                         rq->page_pool = NULL;
 665                         goto err_free_shampo;
 666                 }
 667                 if (xdp_rxq_info_is_reg(&rq->xdp_rxq))
 668                         err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 669                                                          MEM_TYPE_PAGE_POOL, rq->page_pool);
 670         }
 671         if (err)
 672                 goto err_free_shampo;
 673
 674         for (i = 0; i < wq_sz; i++) {
 675                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 676                         struct mlx5e_rx_wqe_ll *wqe =
 677                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 678                         u32 byte_count =
 679                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 680                         u64 dma_offset = mlx5e_get_mpwqe_offset(i);
 681                         u16 headroom = test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state) ?
 682                                        0 : rq->buff.headroom;
 683
 684                         wqe->data[0].addr = cpu_to_be64(dma_offset + headroom);
 685                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 686                         wqe->data[0].lkey = rq->mkey_be;
 687                 } else {
 688                         struct mlx5e_rx_wqe_cyc *wqe =
 689                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 690                         int f;
 691
 692                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 693                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 694                                         MLX5_HW_START_PADDING;
 695
 696                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 697                                 wqe->data[f].lkey = rq->mkey_be;
 698                         }
 699                         /* check if num_frags is not a pow of two */
 700                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 701                                 wqe->data[f].byte_count = 0;
 702                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 703                                 wqe->data[f].addr = 0;
 704                         }
 705                 }
 706         }
 707
 708         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 709
 710         switch (params->rx_cq_moderation.cq_period_mode) {
 711         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 712                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 713                 break;
 714         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 715         default:
 716                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 717         }
 718
 719         rq->page_cache.head = 0;
 720         rq->page_cache.tail = 0;
 721
 722         return 0;
 723
 724 err_free_shampo:
 725         mlx5e_rq_free_shampo(rq);
 726 err_free_by_rq_type:
 727         switch (rq->wq_type) {
 728         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 729                 kvfree(rq->mpwqe.info);
 730 err_rq_mkey:
 731                 mlx5_core_destroy_mkey(mdev, rq->umr_mkey);
 732 err_rq_drop_page:
 733                 mlx5e_free_mpwqe_rq_drop_page(rq);
 734                 break;
 735         default: /* MLX5_WQ_TYPE_CYCLIC */
 736                 mlx5e_free_di_list(rq);
 737 err_rq_frags:
 738                 kvfree(rq->wqe.frags);
 739         }
 740 err_rq_wq_destroy:
 741         mlx5_wq_destroy(&rq->wq_ctrl);
 742 err_rq_xdp_prog:
 743         if (params->xdp_prog)
 744                 bpf_prog_put(params->xdp_prog);
 745
 746         return err;
 747 }
 748
 749 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 750 {
 751         struct bpf_prog *old_prog;
 752         int i;
 753
 754         if (xdp_rxq_info_is_reg(&rq->xdp_rxq)) {
 755                 old_prog = rcu_dereference_protected(rq->xdp_prog,
 756                                                      lockdep_is_held(&rq->priv->state_lock));
 757                 if (old_prog)
 758                         bpf_prog_put(old_prog);
 759         }
 760
 761         switch (rq->wq_type) {
 762         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 763                 kvfree(rq->mpwqe.info);
 764                 mlx5_core_destroy_mkey(rq->mdev, rq->umr_mkey);
 765                 mlx5e_free_mpwqe_rq_drop_page(rq);
 766                 mlx5e_rq_free_shampo(rq);
 767                 break;
 768         default: /* MLX5_WQ_TYPE_CYCLIC */
 769                 kvfree(rq->wqe.frags);
 770                 mlx5e_free_di_list(rq);
 771         }
 772
 773         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 774              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 775                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 776
 777                 /* With AF_XDP, page_cache is not used, so this loop is not
 778                  * entered, and it's safe to call mlx5e_page_release_dynamic
 779                  * directly.
 780                  */
 781                 mlx5e_page_release_dynamic(rq, dma_info->page, false);
 782         }
 783
 784         xdp_rxq_info_unreg(&rq->xdp_rxq);
 785         page_pool_destroy(rq->page_pool);
 786         mlx5_wq_destroy(&rq->wq_ctrl);
 787 }
 788
 789 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 790 {
 791         struct mlx5_core_dev *mdev = rq->mdev;
 792         u8 ts_format;
 793         void *in;
 794         void *rqc;
 795         void *wq;
 796         int inlen;
 797         int err;
 798
 799         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 800                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 801         in = kvzalloc(inlen, GFP_KERNEL);
 802         if (!in)
 803                 return -ENOMEM;
 804
 805         ts_format = mlx5_is_real_time_rq(mdev) ?
 806                             MLX5_TIMESTAMP_FORMAT_REAL_TIME :
 807                             MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
 808         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 809         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 810
 811         memcpy(rqc, param->rqc, sizeof(param->rqc));
 812
 813         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 814         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 815         MLX5_SET(rqc,  rqc, ts_format,          ts_format);
 816         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 817                                                 MLX5_ADAPTER_PAGE_SHIFT);
 818         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 819
 820         if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) {
 821                 MLX5_SET(wq, wq, log_headers_buffer_entry_num,
 822                          order_base_2(rq->mpwqe.shampo->hd_per_wq));
 823                 MLX5_SET(wq, wq, headers_mkey, rq->mpwqe.shampo->mkey);
 824         }
 825
 826         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 827                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 828
 829         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 830
 831         kvfree(in);
 832
 833         return err;
 834 }
 835
 836 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
 837 {
 838         struct mlx5_core_dev *mdev = rq->mdev;
 839
 840         void *in;
 841         void *rqc;
 842         int inlen;
 843         int err;
 844
 845         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 846         in = kvzalloc(inlen, GFP_KERNEL);
 847         if (!in)
 848                 return -ENOMEM;
 849
 850         if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY)
 851                 mlx5e_rqwq_reset(rq);
 852
 853         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 854
 855         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 856         MLX5_SET(rqc, rqc, state, next_state);
 857
 858         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 859
 860         kvfree(in);
 861
 862         return err;
 863 }
 864
 865 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 866 {
 867         struct mlx5_core_dev *mdev = rq->mdev;
 868
 869         void *in;
 870         void *rqc;
 871         int inlen;
 872         int err;
 873
 874         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 875         in = kvzalloc(inlen, GFP_KERNEL);
 876         if (!in)
 877                 return -ENOMEM;
 878
 879         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 880
 881         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 882         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 883                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 884         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 885         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 886
 887         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 888
 889         kvfree(in);
 890
 891         return err;
 892 }
 893
 894 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 895 {
 896         struct mlx5_core_dev *mdev = rq->mdev;
 897         void *in;
 898         void *rqc;
 899         int inlen;
 900         int err;
 901
 902         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 903         in = kvzalloc(inlen, GFP_KERNEL);
 904         if (!in)
 905                 return -ENOMEM;
 906
 907         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 908
 909         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 910         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 911                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 912         MLX5_SET(rqc, rqc, vsd, vsd);
 913         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 914
 915         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 916
 917         kvfree(in);
 918
 919         return err;
 920 }
 921
 922 void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 923 {
 924         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 925 }
 926
 927 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 928 {
 929         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 930
 931         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 932
 933         do {
 934                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 935                         return 0;
 936
 937                 msleep(20);
 938         } while (time_before(jiffies, exp_time));
 939
 940         netdev_warn(rq->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 941                     rq->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 942
 943         mlx5e_reporter_rx_timeout(rq);
 944         return -ETIMEDOUT;
 945 }
 946
 947 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq *rq)
 948 {
 949         struct mlx5_wq_ll *wq;
 950         u16 head;
 951         int i;
 952
 953         if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 954                 return;
 955
 956         wq = &rq->mpwqe.wq;
 957         head = wq->head;
 958
 959         /* Outstanding UMR WQEs (in progress) start at wq->head */
 960         for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
 961                 rq->dealloc_wqe(rq, head);
 962                 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 963         }
 964
 965         if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) {
 966                 u16 len;
 967
 968                 len = (rq->mpwqe.shampo->pi - rq->mpwqe.shampo->ci) &
 969                       (rq->mpwqe.shampo->hd_per_wq - 1);
 970                 mlx5e_shampo_dealloc_hd(rq, len, rq->mpwqe.shampo->ci, false);
 971                 rq->mpwqe.shampo->pi = rq->mpwqe.shampo->ci;
 972         }
 973
 974         rq->mpwqe.actual_wq_head = wq->head;
 975         rq->mpwqe.umr_in_progress = 0;
 976         rq->mpwqe.umr_completed = 0;
 977 }
 978
 979 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 980 {
 981         __be16 wqe_ix_be;
 982         u16 wqe_ix;
 983
 984         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 985                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 986
 987                 mlx5e_free_rx_in_progress_descs(rq);
 988
 989                 while (!mlx5_wq_ll_is_empty(wq)) {
 990                         struct mlx5e_rx_wqe_ll *wqe;
 991
 992                         wqe_ix_be = *wq->tail_next;
 993                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 994                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 995                         rq->dealloc_wqe(rq, wqe_ix);
 996                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 997                                        &wqe->next.next_wqe_index);
 998                 }
 999
1000                 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
1001                         mlx5e_shampo_dealloc_hd(rq, rq->mpwqe.shampo->hd_per_wq,
1002                                                 0, true);
1003         } else {
1004                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1005
1006                 while (!mlx5_wq_cyc_is_empty(wq)) {
1007                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
1008                         rq->dealloc_wqe(rq, wqe_ix);
1009                         mlx5_wq_cyc_pop(wq);
1010                 }
1011         }
1012
1013 }
1014
1015 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
1016                   struct mlx5e_xsk_param *xsk, int node,
1017                   struct mlx5e_rq *rq)
1018 {
1019         struct mlx5_core_dev *mdev = rq->mdev;
1020         int err;
1021
1022         if (params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO)
1023                 __set_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state);
1024
1025         err = mlx5e_alloc_rq(params, xsk, param, node, rq);
1026         if (err)
1027                 return err;
1028
1029         err = mlx5e_create_rq(rq, param);
1030         if (err)
1031                 goto err_free_rq;
1032
1033         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1034         if (err)
1035                 goto err_destroy_rq;
1036
1037         if (MLX5_CAP_ETH(mdev, cqe_checksum_full))
1038                 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state);
1039
1040         if (params->rx_dim_enabled)
1041                 __set_bit(MLX5E_RQ_STATE_AM, &rq->state);
1042
1043         /* We disable csum_complete when XDP is enabled since
1044          * XDP programs might manipulate packets which will render
1045          * skb->checksum incorrect.
1046          */
1047         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || params->xdp_prog)
1048                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state);
1049
1050         /* For CQE compression on striding RQ, use stride index provided by
1051          * HW if capability is supported.
1052          */
1053         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) &&
1054             MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index))
1055                 __set_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &rq->state);
1056
1057         return 0;
1058
1059 err_destroy_rq:
1060         mlx5e_destroy_rq(rq);
1061 err_free_rq:
1062         mlx5e_free_rq(rq);
1063
1064         return err;
1065 }
1066
1067 void mlx5e_activate_rq(struct mlx5e_rq *rq)
1068 {
1069         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
1070         if (rq->icosq) {
1071                 mlx5e_trigger_irq(rq->icosq);
1072         } else {
1073                 local_bh_disable();
1074                 napi_schedule(rq->cq.napi);
1075                 local_bh_enable();
1076         }
1077 }
1078
1079 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
1080 {
1081         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
1082         synchronize_net(); /* Sync with NAPI to prevent mlx5e_post_rx_wqes. */
1083 }
1084
1085 void mlx5e_close_rq(struct mlx5e_rq *rq)
1086 {
1087         cancel_work_sync(&rq->dim.work);
1088         cancel_work_sync(&rq->recover_work);
1089         mlx5e_destroy_rq(rq);
1090         mlx5e_free_rx_descs(rq);
1091         mlx5e_free_rq(rq);
1092 }
1093
1094 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
1095 {
1096         kvfree(sq->db.xdpi_fifo.xi);
1097         kvfree(sq->db.wqe_info);
1098 }
1099
1100 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
1101 {
1102         struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
1103         int wq_sz        = mlx5_wq_cyc_get_size(&sq->wq);
1104         int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1105         size_t size;
1106
1107         size = array_size(sizeof(*xdpi_fifo->xi), dsegs_per_wq);
1108         xdpi_fifo->xi = kvzalloc_node(size, GFP_KERNEL, numa);
1109         if (!xdpi_fifo->xi)
1110                 return -ENOMEM;
1111
1112         xdpi_fifo->pc   = &sq->xdpi_fifo_pc;
1113         xdpi_fifo->cc   = &sq->xdpi_fifo_cc;
1114         xdpi_fifo->mask = dsegs_per_wq - 1;
1115
1116         return 0;
1117 }
1118
1119 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
1120 {
1121         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1122         size_t size;
1123         int err;
1124
1125         size = array_size(sizeof(*sq->db.wqe_info), wq_sz);
1126         sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1127         if (!sq->db.wqe_info)
1128                 return -ENOMEM;
1129
1130         err = mlx5e_alloc_xdpsq_fifo(sq, numa);
1131         if (err) {
1132                 mlx5e_free_xdpsq_db(sq);
1133                 return err;
1134         }
1135
1136         return 0;
1137 }
1138
1139 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
1140                              struct mlx5e_params *params,
1141                              struct xsk_buff_pool *xsk_pool,
1142                              struct mlx5e_sq_param *param,
1143                              struct mlx5e_xdpsq *sq,
1144                              bool is_redirect)
1145 {
1146         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1147         struct mlx5_core_dev *mdev = c->mdev;
1148         struct mlx5_wq_cyc *wq = &sq->wq;
1149         int err;
1150
1151         sq->pdev      = c->pdev;
1152         sq->mkey_be   = c->mkey_be;
1153         sq->channel   = c;
1154         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1155         sq->min_inline_mode = params->tx_min_inline_mode;
1156         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1157         sq->xsk_pool  = xsk_pool;
1158
1159         sq->stats = sq->xsk_pool ?
1160                 &c->priv->channel_stats[c->ix]->xsksq :
1161                 is_redirect ?
1162                         &c->priv->channel_stats[c->ix]->xdpsq :
1163                         &c->priv->channel_stats[c->ix]->rq_xdpsq;
1164         sq->max_sq_wqebbs = mlx5e_get_max_sq_wqebbs(mdev);
1165         sq->stop_room = MLX5E_STOP_ROOM(sq->max_sq_wqebbs);
1166         sq->max_sq_mpw_wqebbs = mlx5e_get_sw_max_sq_mpw_wqebbs(sq->max_sq_wqebbs);
1167
1168         param->wq.db_numa_node = cpu_to_node(c->cpu);
1169         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1170         if (err)
1171                 return err;
1172         wq->db = &wq->db[MLX5_SND_DBR];
1173
1174         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1175         if (err)
1176                 goto err_sq_wq_destroy;
1177
1178         return 0;
1179
1180 err_sq_wq_destroy:
1181         mlx5_wq_destroy(&sq->wq_ctrl);
1182
1183         return err;
1184 }
1185
1186 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1187 {
1188         mlx5e_free_xdpsq_db(sq);
1189         mlx5_wq_destroy(&sq->wq_ctrl);
1190 }
1191
1192 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1193 {
1194         kvfree(sq->db.wqe_info);
1195 }
1196
1197 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1198 {
1199         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1200         size_t size;
1201
1202         size = array_size(wq_sz, sizeof(*sq->db.wqe_info));
1203         sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1204         if (!sq->db.wqe_info)
1205                 return -ENOMEM;
1206
1207         return 0;
1208 }
1209
1210 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1211 {
1212         struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1213                                               recover_work);
1214
1215         mlx5e_reporter_icosq_cqe_err(sq);
1216 }
1217
1218 static void mlx5e_async_icosq_err_cqe_work(struct work_struct *recover_work)
1219 {
1220         struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1221                                               recover_work);
1222
1223         /* Not implemented yet. */
1224
1225         netdev_warn(sq->channel->netdev, "async_icosq recovery is not implemented\n");
1226 }
1227
1228 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1229                              struct mlx5e_sq_param *param,
1230                              struct mlx5e_icosq *sq,
1231                              work_func_t recover_work_func)
1232 {
1233         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1234         struct mlx5_core_dev *mdev = c->mdev;
1235         struct mlx5_wq_cyc *wq = &sq->wq;
1236         int err;
1237
1238         sq->channel   = c;
1239         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1240         sq->reserved_room = param->stop_room;
1241         sq->max_sq_wqebbs = mlx5e_get_max_sq_wqebbs(mdev);
1242
1243         param->wq.db_numa_node = cpu_to_node(c->cpu);
1244         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1245         if (err)
1246                 return err;
1247         wq->db = &wq->db[MLX5_SND_DBR];
1248
1249         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1250         if (err)
1251                 goto err_sq_wq_destroy;
1252
1253         INIT_WORK(&sq->recover_work, recover_work_func);
1254
1255         return 0;
1256
1257 err_sq_wq_destroy:
1258         mlx5_wq_destroy(&sq->wq_ctrl);
1259
1260         return err;
1261 }
1262
1263 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1264 {
1265         mlx5e_free_icosq_db(sq);
1266         mlx5_wq_destroy(&sq->wq_ctrl);
1267 }
1268
1269 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1270 {
1271         kvfree(sq->db.wqe_info);
1272         kvfree(sq->db.skb_fifo.fifo);
1273         kvfree(sq->db.dma_fifo);
1274 }
1275
1276 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1277 {
1278         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1279         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1280
1281         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1282                                                    sizeof(*sq->db.dma_fifo)),
1283                                         GFP_KERNEL, numa);
1284         sq->db.skb_fifo.fifo = kvzalloc_node(array_size(df_sz,
1285                                                         sizeof(*sq->db.skb_fifo.fifo)),
1286                                         GFP_KERNEL, numa);
1287         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1288                                                    sizeof(*sq->db.wqe_info)),
1289                                         GFP_KERNEL, numa);
1290         if (!sq->db.dma_fifo || !sq->db.skb_fifo.fifo || !sq->db.wqe_info) {
1291                 mlx5e_free_txqsq_db(sq);
1292                 return -ENOMEM;
1293         }
1294
1295         sq->dma_fifo_mask = df_sz - 1;
1296
1297         sq->db.skb_fifo.pc   = &sq->skb_fifo_pc;
1298         sq->db.skb_fifo.cc   = &sq->skb_fifo_cc;
1299         sq->db.skb_fifo.mask = df_sz - 1;
1300
1301         return 0;
1302 }
1303
1304 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1305                              int txq_ix,
1306                              struct mlx5e_params *params,
1307                              struct mlx5e_sq_param *param,
1308                              struct mlx5e_txqsq *sq,
1309                              int tc)
1310 {
1311         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1312         struct mlx5_core_dev *mdev = c->mdev;
1313         struct mlx5_wq_cyc *wq = &sq->wq;
1314         int err;
1315
1316         sq->pdev      = c->pdev;
1317         sq->clock     = &mdev->clock;
1318         sq->mkey_be   = c->mkey_be;
1319         sq->netdev    = c->netdev;
1320         sq->mdev      = c->mdev;
1321         sq->priv      = c->priv;
1322         sq->ch_ix     = c->ix;
1323         sq->txq_ix    = txq_ix;
1324         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1325         sq->min_inline_mode = params->tx_min_inline_mode;
1326         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1327         sq->max_sq_wqebbs = mlx5e_get_max_sq_wqebbs(mdev);
1328         sq->max_sq_mpw_wqebbs = mlx5e_get_sw_max_sq_mpw_wqebbs(sq->max_sq_wqebbs);
1329         INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1330         if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1331                 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1332         if (mlx5_ipsec_device_caps(c->priv->mdev))
1333                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1334         if (param->is_mpw)
1335                 set_bit(MLX5E_SQ_STATE_MPWQE, &sq->state);
1336         sq->stop_room = param->stop_room;
1337         sq->ptp_cyc2time = mlx5_sq_ts_translator(mdev);
1338
1339         param->wq.db_numa_node = cpu_to_node(c->cpu);
1340         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1341         if (err)
1342                 return err;
1343         wq->db    = &wq->db[MLX5_SND_DBR];
1344
1345         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1346         if (err)
1347                 goto err_sq_wq_destroy;
1348
1349         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1350         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1351
1352         return 0;
1353
1354 err_sq_wq_destroy:
1355         mlx5_wq_destroy(&sq->wq_ctrl);
1356
1357         return err;
1358 }
1359
1360 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1361 {
1362         mlx5e_free_txqsq_db(sq);
1363         mlx5_wq_destroy(&sq->wq_ctrl);
1364 }
1365
1366 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1367                            struct mlx5e_sq_param *param,
1368                            struct mlx5e_create_sq_param *csp,
1369                            u32 *sqn)
1370 {
1371         u8 ts_format;
1372         void *in;
1373         void *sqc;
1374         void *wq;
1375         int inlen;
1376         int err;
1377
1378         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1379                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1380         in = kvzalloc(inlen, GFP_KERNEL);
1381         if (!in)
1382                 return -ENOMEM;
1383
1384         ts_format = mlx5_is_real_time_sq(mdev) ?
1385                             MLX5_TIMESTAMP_FORMAT_REAL_TIME :
1386                             MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
1387         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1388         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1389
1390         memcpy(sqc, param->sqc, sizeof(param->sqc));
1391         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1392         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1393         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1394         MLX5_SET(sqc,  sqc, ts_cqe_to_dest_cqn, csp->ts_cqe_to_dest_cqn);
1395         MLX5_SET(sqc,  sqc, ts_format, ts_format);
1396
1397
1398         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1399                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1400
1401         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1402         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1403
1404         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1405         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.hw_objs.bfreg.index);
1406         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1407                                           MLX5_ADAPTER_PAGE_SHIFT);
1408         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1409
1410         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1411                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1412
1413         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1414
1415         kvfree(in);
1416
1417         return err;
1418 }
1419
1420 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1421                     struct mlx5e_modify_sq_param *p)
1422 {
1423         u64 bitmask = 0;
1424         void *in;
1425         void *sqc;
1426         int inlen;
1427         int err;
1428
1429         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1430         in = kvzalloc(inlen, GFP_KERNEL);
1431         if (!in)
1432                 return -ENOMEM;
1433
1434         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1435
1436         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1437         MLX5_SET(sqc, sqc, state, p->next_state);
1438         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1439                 bitmask |= 1;
1440                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1441         }
1442         if (p->qos_update && p->next_state == MLX5_SQC_STATE_RDY) {
1443                 bitmask |= 1 << 2;
1444                 MLX5_SET(sqc, sqc, qos_queue_group_id, p->qos_queue_group_id);
1445         }
1446         MLX5_SET64(modify_sq_in, in, modify_bitmask, bitmask);
1447
1448         err = mlx5_core_modify_sq(mdev, sqn, in);
1449
1450         kvfree(in);
1451
1452         return err;
1453 }
1454
1455 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1456 {
1457         mlx5_core_destroy_sq(mdev, sqn);
1458 }
1459
1460 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1461                         struct mlx5e_sq_param *param,
1462                         struct mlx5e_create_sq_param *csp,
1463                         u16 qos_queue_group_id,
1464                         u32 *sqn)
1465 {
1466         struct mlx5e_modify_sq_param msp = {0};
1467         int err;
1468
1469         err = mlx5e_create_sq(mdev, param, csp, sqn);
1470         if (err)
1471                 return err;
1472
1473         msp.curr_state = MLX5_SQC_STATE_RST;
1474         msp.next_state = MLX5_SQC_STATE_RDY;
1475         if (qos_queue_group_id) {
1476                 msp.qos_update = true;
1477                 msp.qos_queue_group_id = qos_queue_group_id;
1478         }
1479         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1480         if (err)
1481                 mlx5e_destroy_sq(mdev, *sqn);
1482
1483         return err;
1484 }
1485
1486 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1487                                 struct mlx5e_txqsq *sq, u32 rate);
1488
1489 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1490                      struct mlx5e_params *params, struct mlx5e_sq_param *param,
1491                      struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id,
1492                      struct mlx5e_sq_stats *sq_stats)
1493 {
1494         struct mlx5e_create_sq_param csp = {};
1495         u32 tx_rate;
1496         int err;
1497
1498         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1499         if (err)
1500                 return err;
1501
1502         sq->stats = sq_stats;
1503
1504         csp.tisn            = tisn;
1505         csp.tis_lst_sz      = 1;
1506         csp.cqn             = sq->cq.mcq.cqn;
1507         csp.wq_ctrl         = &sq->wq_ctrl;
1508         csp.min_inline_mode = sq->min_inline_mode;
1509         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, qos_queue_group_id, &sq->sqn);
1510         if (err)
1511                 goto err_free_txqsq;
1512
1513         tx_rate = c->priv->tx_rates[sq->txq_ix];
1514         if (tx_rate)
1515                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1516
1517         if (params->tx_dim_enabled)
1518                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1519
1520         return 0;
1521
1522 err_free_txqsq:
1523         mlx5e_free_txqsq(sq);
1524
1525         return err;
1526 }
1527
1528 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1529 {
1530         sq->txq = netdev_get_tx_queue(sq->netdev, sq->txq_ix);
1531         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1532         netdev_tx_reset_queue(sq->txq);
1533         netif_tx_start_queue(sq->txq);
1534 }
1535
1536 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1537 {
1538         __netif_tx_lock_bh(txq);
1539         netif_tx_stop_queue(txq);
1540         __netif_tx_unlock_bh(txq);
1541 }
1542
1543 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1544 {
1545         struct mlx5_wq_cyc *wq = &sq->wq;
1546
1547         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1548         synchronize_net(); /* Sync with NAPI to prevent netif_tx_wake_queue. */
1549
1550         mlx5e_tx_disable_queue(sq->txq);
1551
1552         /* last doorbell out, godspeed .. */
1553         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1554                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1555                 struct mlx5e_tx_wqe *nop;
1556
1557                 sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) {
1558                         .num_wqebbs = 1,
1559                 };
1560
1561                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1562                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1563         }
1564 }
1565
1566 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1567 {
1568         struct mlx5_core_dev *mdev = sq->mdev;
1569         struct mlx5_rate_limit rl = {0};
1570
1571         cancel_work_sync(&sq->dim.work);
1572         cancel_work_sync(&sq->recover_work);
1573         mlx5e_destroy_sq(mdev, sq->sqn);
1574         if (sq->rate_limit) {
1575                 rl.rate = sq->rate_limit;
1576                 mlx5_rl_remove_rate(mdev, &rl);
1577         }
1578         mlx5e_free_txqsq_descs(sq);
1579         mlx5e_free_txqsq(sq);
1580 }
1581
1582 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1583 {
1584         struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1585                                               recover_work);
1586
1587         mlx5e_reporter_tx_err_cqe(sq);
1588 }
1589
1590 static int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1591                             struct mlx5e_sq_param *param, struct mlx5e_icosq *sq,
1592                             work_func_t recover_work_func)
1593 {
1594         struct mlx5e_create_sq_param csp = {};
1595         int err;
1596
1597         err = mlx5e_alloc_icosq(c, param, sq, recover_work_func);
1598         if (err)
1599                 return err;
1600
1601         csp.cqn             = sq->cq.mcq.cqn;
1602         csp.wq_ctrl         = &sq->wq_ctrl;
1603         csp.min_inline_mode = params->tx_min_inline_mode;
1604         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1605         if (err)
1606                 goto err_free_icosq;
1607
1608         if (param->is_tls) {
1609                 sq->ktls_resync = mlx5e_ktls_rx_resync_create_resp_list();
1610                 if (IS_ERR(sq->ktls_resync)) {
1611                         err = PTR_ERR(sq->ktls_resync);
1612                         goto err_destroy_icosq;
1613                 }
1614         }
1615         return 0;
1616
1617 err_destroy_icosq:
1618         mlx5e_destroy_sq(c->mdev, sq->sqn);
1619 err_free_icosq:
1620         mlx5e_free_icosq(sq);
1621
1622         return err;
1623 }
1624
1625 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1626 {
1627         set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1628 }
1629
1630 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1631 {
1632         clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1633         synchronize_net(); /* Sync with NAPI. */
1634 }
1635
1636 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1637 {
1638         struct mlx5e_channel *c = sq->channel;
1639
1640         if (sq->ktls_resync)
1641                 mlx5e_ktls_rx_resync_destroy_resp_list(sq->ktls_resync);
1642         mlx5e_destroy_sq(c->mdev, sq->sqn);
1643         mlx5e_free_icosq_descs(sq);
1644         mlx5e_free_icosq(sq);
1645 }
1646
1647 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1648                      struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1649                      struct mlx5e_xdpsq *sq, bool is_redirect)
1650 {
1651         struct mlx5e_create_sq_param csp = {};
1652         int err;
1653
1654         err = mlx5e_alloc_xdpsq(c, params, xsk_pool, param, sq, is_redirect);
1655         if (err)
1656                 return err;
1657
1658         csp.tis_lst_sz      = 1;
1659         csp.tisn            = c->priv->tisn[c->lag_port][0]; /* tc = 0 */
1660         csp.cqn             = sq->cq.mcq.cqn;
1661         csp.wq_ctrl         = &sq->wq_ctrl;
1662         csp.min_inline_mode = sq->min_inline_mode;
1663         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1664
1665         /* Don't enable multi buffer on XDP_REDIRECT SQ, as it's not yet
1666          * supported by upstream, and there is no defined trigger to allow
1667          * transmitting redirected multi-buffer frames.
1668          */
1669         if (param->is_xdp_mb && !is_redirect)
1670                 set_bit(MLX5E_SQ_STATE_XDP_MULTIBUF, &sq->state);
1671
1672         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1673         if (err)
1674                 goto err_free_xdpsq;
1675
1676         mlx5e_set_xmit_fp(sq, param->is_mpw);
1677
1678         if (!param->is_mpw && !test_bit(MLX5E_SQ_STATE_XDP_MULTIBUF, &sq->state)) {
1679                 unsigned int ds_cnt = MLX5E_TX_WQE_EMPTY_DS_COUNT + 1;
1680                 unsigned int inline_hdr_sz = 0;
1681                 int i;
1682
1683                 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1684                         inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1685                         ds_cnt++;
1686                 }
1687
1688                 /* Pre initialize fixed WQE fields */
1689                 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1690                         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1691                         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1692                         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1693                         struct mlx5_wqe_data_seg *dseg;
1694
1695                         sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) {
1696                                 .num_wqebbs = 1,
1697                                 .num_pkts   = 1,
1698                         };
1699
1700                         cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1701                         eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1702
1703                         dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1704                         dseg->lkey = sq->mkey_be;
1705                 }
1706         }
1707
1708         return 0;
1709
1710 err_free_xdpsq:
1711         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1712         mlx5e_free_xdpsq(sq);
1713
1714         return err;
1715 }
1716
1717 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1718 {
1719         struct mlx5e_channel *c = sq->channel;
1720
1721         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1722         synchronize_net(); /* Sync with NAPI. */
1723
1724         mlx5e_destroy_sq(c->mdev, sq->sqn);
1725         mlx5e_free_xdpsq_descs(sq);
1726         mlx5e_free_xdpsq(sq);
1727 }
1728
1729 static int mlx5e_alloc_cq_common(struct mlx5e_priv *priv,
1730                                  struct mlx5e_cq_param *param,
1731                                  struct mlx5e_cq *cq)
1732 {
1733         struct mlx5_core_dev *mdev = priv->mdev;
1734         struct mlx5_core_cq *mcq = &cq->mcq;
1735         int err;
1736         u32 i;
1737
1738         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1739                                &cq->wq_ctrl);
1740         if (err)
1741                 return err;
1742
1743         mcq->cqe_sz     = 64;
1744         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1745         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1746         *mcq->set_ci_db = 0;
1747         *mcq->arm_db    = 0;
1748         mcq->vector     = param->eq_ix;
1749         mcq->comp       = mlx5e_completion_event;
1750         mcq->event      = mlx5e_cq_error_event;
1751
1752         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1753                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1754
1755                 cqe->op_own = 0xf1;
1756         }
1757
1758         cq->mdev = mdev;
1759         cq->netdev = priv->netdev;
1760         cq->priv = priv;
1761
1762         return 0;
1763 }
1764
1765 static int mlx5e_alloc_cq(struct mlx5e_priv *priv,
1766                           struct mlx5e_cq_param *param,
1767                           struct mlx5e_create_cq_param *ccp,
1768                           struct mlx5e_cq *cq)
1769 {
1770         int err;
1771
1772         param->wq.buf_numa_node = ccp->node;
1773         param->wq.db_numa_node  = ccp->node;
1774         param->eq_ix            = ccp->ix;
1775
1776         err = mlx5e_alloc_cq_common(priv, param, cq);
1777
1778         cq->napi     = ccp->napi;
1779         cq->ch_stats = ccp->ch_stats;
1780
1781         return err;
1782 }
1783
1784 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1785 {
1786         mlx5_wq_destroy(&cq->wq_ctrl);
1787 }
1788
1789 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1790 {
1791         u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1792         struct mlx5_core_dev *mdev = cq->mdev;
1793         struct mlx5_core_cq *mcq = &cq->mcq;
1794
1795         void *in;
1796         void *cqc;
1797         int inlen;
1798         int eqn;
1799         int err;
1800
1801         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn);
1802         if (err)
1803                 return err;
1804
1805         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1806                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1807         in = kvzalloc(inlen, GFP_KERNEL);
1808         if (!in)
1809                 return -ENOMEM;
1810
1811         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1812
1813         memcpy(cqc, param->cqc, sizeof(param->cqc));
1814
1815         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1816                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1817
1818         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1819         MLX5_SET(cqc,   cqc, c_eqn_or_apu_element, eqn);
1820         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1821         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1822                                             MLX5_ADAPTER_PAGE_SHIFT);
1823         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1824
1825         err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1826
1827         kvfree(in);
1828
1829         if (err)
1830                 return err;
1831
1832         mlx5e_cq_arm(cq);
1833
1834         return 0;
1835 }
1836
1837 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1838 {
1839         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1840 }
1841
1842 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,
1843                   struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
1844                   struct mlx5e_cq *cq)
1845 {
1846         struct mlx5_core_dev *mdev = priv->mdev;
1847         int err;
1848
1849         err = mlx5e_alloc_cq(priv, param, ccp, cq);
1850         if (err)
1851                 return err;
1852
1853         err = mlx5e_create_cq(cq, param);
1854         if (err)
1855                 goto err_free_cq;
1856
1857         if (MLX5_CAP_GEN(mdev, cq_moderation))
1858                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1859         return 0;
1860
1861 err_free_cq:
1862         mlx5e_free_cq(cq);
1863
1864         return err;
1865 }
1866
1867 void mlx5e_close_cq(struct mlx5e_cq *cq)
1868 {
1869         mlx5e_destroy_cq(cq);
1870         mlx5e_free_cq(cq);
1871 }
1872
1873 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1874                              struct mlx5e_params *params,
1875                              struct mlx5e_create_cq_param *ccp,
1876                              struct mlx5e_channel_param *cparam)
1877 {
1878         int err;
1879         int tc;
1880
1881         for (tc = 0; tc < c->num_tc; tc++) {
1882                 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->txq_sq.cqp,
1883                                     ccp, &c->sq[tc].cq);
1884                 if (err)
1885                         goto err_close_tx_cqs;
1886         }
1887
1888         return 0;
1889
1890 err_close_tx_cqs:
1891         for (tc--; tc >= 0; tc--)
1892                 mlx5e_close_cq(&c->sq[tc].cq);
1893
1894         return err;
1895 }
1896
1897 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1898 {
1899         int tc;
1900
1901         for (tc = 0; tc < c->num_tc; tc++)
1902                 mlx5e_close_cq(&c->sq[tc].cq);
1903 }
1904
1905 static int mlx5e_mqprio_txq_to_tc(struct netdev_tc_txq *tc_to_txq, unsigned int txq)
1906 {
1907         int tc;
1908
1909         for (tc = 0; tc < TC_MAX_QUEUE; tc++)
1910                 if (txq - tc_to_txq[tc].offset < tc_to_txq[tc].count)
1911                         return tc;
1912
1913         WARN(1, "Unexpected TCs configuration. No match found for txq %u", txq);
1914         return -ENOENT;
1915 }
1916
1917 static int mlx5e_txq_get_qos_node_hw_id(struct mlx5e_params *params, int txq_ix,
1918                                         u32 *hw_id)
1919 {
1920         int tc;
1921
1922         if (params->mqprio.mode != TC_MQPRIO_MODE_CHANNEL ||
1923             !params->mqprio.channel.rl) {
1924                 *hw_id = 0;
1925                 return 0;
1926         }
1927
1928         tc = mlx5e_mqprio_txq_to_tc(params->mqprio.tc_to_txq, txq_ix);
1929         if (tc < 0)
1930                 return tc;
1931
1932         return mlx5e_mqprio_rl_get_node_hw_id(params->mqprio.channel.rl, tc, hw_id);
1933 }
1934
1935 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1936                           struct mlx5e_params *params,
1937                           struct mlx5e_channel_param *cparam)
1938 {
1939         int err, tc;
1940
1941         for (tc = 0; tc < mlx5e_get_dcb_num_tc(params); tc++) {
1942                 int txq_ix = c->ix + tc * params->num_channels;
1943                 u32 qos_queue_group_id;
1944
1945                 err = mlx5e_txq_get_qos_node_hw_id(params, txq_ix, &qos_queue_group_id);
1946                 if (err)
1947                         goto err_close_sqs;
1948
1949                 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
1950                                        params, &cparam->txq_sq, &c->sq[tc], tc,
1951                                        qos_queue_group_id,
1952                                        &c->priv->channel_stats[c->ix]->sq[tc]);
1953                 if (err)
1954                         goto err_close_sqs;
1955         }
1956
1957         return 0;
1958
1959 err_close_sqs:
1960         for (tc--; tc >= 0; tc--)
1961                 mlx5e_close_txqsq(&c->sq[tc]);
1962
1963         return err;
1964 }
1965
1966 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1967 {
1968         int tc;
1969
1970         for (tc = 0; tc < c->num_tc; tc++)
1971                 mlx5e_close_txqsq(&c->sq[tc]);
1972 }
1973
1974 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1975                                 struct mlx5e_txqsq *sq, u32 rate)
1976 {
1977         struct mlx5e_priv *priv = netdev_priv(dev);
1978         struct mlx5_core_dev *mdev = priv->mdev;
1979         struct mlx5e_modify_sq_param msp = {0};
1980         struct mlx5_rate_limit rl = {0};
1981         u16 rl_index = 0;
1982         int err;
1983
1984         if (rate == sq->rate_limit)
1985                 /* nothing to do */
1986                 return 0;
1987
1988         if (sq->rate_limit) {
1989                 rl.rate = sq->rate_limit;
1990                 /* remove current rl index to free space to next ones */
1991                 mlx5_rl_remove_rate(mdev, &rl);
1992         }
1993
1994         sq->rate_limit = 0;
1995
1996         if (rate) {
1997                 rl.rate = rate;
1998                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1999                 if (err) {
2000                         netdev_err(dev, "Failed configuring rate %u: %d\n",
2001                                    rate, err);
2002                         return err;
2003                 }
2004         }
2005
2006         msp.curr_state = MLX5_SQC_STATE_RDY;
2007         msp.next_state = MLX5_SQC_STATE_RDY;
2008         msp.rl_index   = rl_index;
2009         msp.rl_update  = true;
2010         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
2011         if (err) {
2012                 netdev_err(dev, "Failed configuring rate %u: %d\n",
2013                            rate, err);
2014                 /* remove the rate from the table */
2015                 if (rate)
2016                         mlx5_rl_remove_rate(mdev, &rl);
2017                 return err;
2018         }
2019
2020         sq->rate_limit = rate;
2021         return 0;
2022 }
2023
2024 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
2025 {
2026         struct mlx5e_priv *priv = netdev_priv(dev);
2027         struct mlx5_core_dev *mdev = priv->mdev;
2028         struct mlx5e_txqsq *sq = priv->txq2sq[index];
2029         int err = 0;
2030
2031         if (!mlx5_rl_is_supported(mdev)) {
2032                 netdev_err(dev, "Rate limiting is not supported on this device\n");
2033                 return -EINVAL;
2034         }
2035
2036         /* rate is given in Mb/sec, HW config is in Kb/sec */
2037         rate = rate << 10;
2038
2039         /* Check whether rate in valid range, 0 is always valid */
2040         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
2041                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
2042                 return -ERANGE;
2043         }
2044
2045         mutex_lock(&priv->state_lock);
2046         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
2047                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
2048         if (!err)
2049                 priv->tx_rates[index] = rate;
2050         mutex_unlock(&priv->state_lock);
2051
2052         return err;
2053 }
2054
2055 static int mlx5e_open_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
2056                              struct mlx5e_rq_param *rq_params)
2057 {
2058         int err;
2059
2060         err = mlx5e_init_rxq_rq(c, params, &c->rq);
2061         if (err)
2062                 return err;
2063
2064         return mlx5e_open_rq(params, rq_params, NULL, cpu_to_node(c->cpu), &c->rq);
2065 }
2066
2067 static int mlx5e_open_queues(struct mlx5e_channel *c,
2068                              struct mlx5e_params *params,
2069                              struct mlx5e_channel_param *cparam)
2070 {
2071         struct dim_cq_moder icocq_moder = {0, 0};
2072         struct mlx5e_create_cq_param ccp;
2073         int err;
2074
2075         mlx5e_build_create_cq_param(&ccp, c);
2076
2077         err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->async_icosq.cqp, &ccp,
2078                             &c->async_icosq.cq);
2079         if (err)
2080                 return err;
2081
2082         err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->icosq.cqp, &ccp,
2083                             &c->icosq.cq);
2084         if (err)
2085                 goto err_close_async_icosq_cq;
2086
2087         err = mlx5e_open_tx_cqs(c, params, &ccp, cparam);
2088         if (err)
2089                 goto err_close_icosq_cq;
2090
2091         err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp, &ccp,
2092                             &c->xdpsq.cq);
2093         if (err)
2094                 goto err_close_tx_cqs;
2095
2096         err = mlx5e_open_cq(c->priv, params->rx_cq_moderation, &cparam->rq.cqp, &ccp,
2097                             &c->rq.cq);
2098         if (err)
2099                 goto err_close_xdp_tx_cqs;
2100
2101         err = c->xdp ? mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp,
2102                                      &ccp, &c->rq_xdpsq.cq) : 0;
2103         if (err)
2104                 goto err_close_rx_cq;
2105
2106         spin_lock_init(&c->async_icosq_lock);
2107
2108         err = mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq,
2109                                mlx5e_async_icosq_err_cqe_work);
2110         if (err)
2111                 goto err_close_xdpsq_cq;
2112
2113         mutex_init(&c->icosq_recovery_lock);
2114
2115         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq,
2116                                mlx5e_icosq_err_cqe_work);
2117         if (err)
2118                 goto err_close_async_icosq;
2119
2120         err = mlx5e_open_sqs(c, params, cparam);
2121         if (err)
2122                 goto err_close_icosq;
2123
2124         err = mlx5e_open_rxq_rq(c, params, &cparam->rq);
2125         if (err)
2126                 goto err_close_sqs;
2127
2128         if (c->xdp) {
2129                 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
2130                                        &c->rq_xdpsq, false);
2131                 if (err)
2132                         goto err_close_rq;
2133         }
2134
2135         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
2136         if (err)
2137                 goto err_close_xdp_sq;
2138
2139         return 0;
2140
2141 err_close_xdp_sq:
2142         if (c->xdp)
2143                 mlx5e_close_xdpsq(&c->rq_xdpsq);
2144
2145 err_close_rq:
2146         mlx5e_close_rq(&c->rq);
2147
2148 err_close_sqs:
2149         mlx5e_close_sqs(c);
2150
2151 err_close_icosq:
2152         mlx5e_close_icosq(&c->icosq);
2153
2154 err_close_async_icosq:
2155         mlx5e_close_icosq(&c->async_icosq);
2156
2157 err_close_xdpsq_cq:
2158         if (c->xdp)
2159                 mlx5e_close_cq(&c->rq_xdpsq.cq);
2160
2161 err_close_rx_cq:
2162         mlx5e_close_cq(&c->rq.cq);
2163
2164 err_close_xdp_tx_cqs:
2165         mlx5e_close_cq(&c->xdpsq.cq);
2166
2167 err_close_tx_cqs:
2168         mlx5e_close_tx_cqs(c);
2169
2170 err_close_icosq_cq:
2171         mlx5e_close_cq(&c->icosq.cq);
2172
2173 err_close_async_icosq_cq:
2174         mlx5e_close_cq(&c->async_icosq.cq);
2175
2176         return err;
2177 }
2178
2179 static void mlx5e_close_queues(struct mlx5e_channel *c)
2180 {
2181         mlx5e_close_xdpsq(&c->xdpsq);
2182         if (c->xdp)
2183                 mlx5e_close_xdpsq(&c->rq_xdpsq);
2184         /* The same ICOSQ is used for UMRs for both RQ and XSKRQ. */
2185         cancel_work_sync(&c->icosq.recover_work);
2186         mlx5e_close_rq(&c->rq);
2187         mlx5e_close_sqs(c);
2188         mlx5e_close_icosq(&c->icosq);
2189         mutex_destroy(&c->icosq_recovery_lock);
2190         mlx5e_close_icosq(&c->async_icosq);
2191         if (c->xdp)
2192                 mlx5e_close_cq(&c->rq_xdpsq.cq);
2193         mlx5e_close_cq(&c->rq.cq);
2194         mlx5e_close_cq(&c->xdpsq.cq);
2195         mlx5e_close_tx_cqs(c);
2196         mlx5e_close_cq(&c->icosq.cq);
2197         mlx5e_close_cq(&c->async_icosq.cq);
2198 }
2199
2200 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
2201 {
2202         u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
2203
2204         return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
2205 }
2206
2207 static int mlx5e_channel_stats_alloc(struct mlx5e_priv *priv, int ix, int cpu)
2208 {
2209         if (ix > priv->stats_nch)  {
2210                 netdev_warn(priv->netdev, "Unexpected channel stats index %d > %d\n", ix,
2211                             priv->stats_nch);
2212                 return -EINVAL;
2213         }
2214
2215         if (priv->channel_stats[ix])
2216                 return 0;
2217
2218         /* Asymmetric dynamic memory allocation.
2219          * Freed in mlx5e_priv_arrays_free, not on channel closure.
2220          */
2221         mlx5e_dbg(DRV, priv, "Creating channel stats %d\n", ix);
2222         priv->channel_stats[ix] = kvzalloc_node(sizeof(**priv->channel_stats),
2223                                                 GFP_KERNEL, cpu_to_node(cpu));
2224         if (!priv->channel_stats[ix])
2225                 return -ENOMEM;
2226         priv->stats_nch++;
2227
2228         return 0;
2229 }
2230
2231 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
2232                               struct mlx5e_params *params,
2233                               struct mlx5e_channel_param *cparam,
2234                               struct xsk_buff_pool *xsk_pool,
2235                               struct mlx5e_channel **cp)
2236 {
2237         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
2238         struct net_device *netdev = priv->netdev;
2239         struct mlx5e_xsk_param xsk;
2240         struct mlx5e_channel *c;
2241         unsigned int irq;
2242         int err;
2243
2244         err = mlx5_vector2irqn(priv->mdev, ix, &irq);
2245         if (err)
2246                 return err;
2247
2248         err = mlx5e_channel_stats_alloc(priv, ix, cpu);
2249         if (err)
2250                 return err;
2251
2252         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
2253         if (!c)
2254                 return -ENOMEM;
2255
2256         c->priv     = priv;
2257         c->mdev     = priv->mdev;
2258         c->tstamp   = &priv->tstamp;
2259         c->ix       = ix;
2260         c->cpu      = cpu;
2261         c->pdev     = mlx5_core_dma_dev(priv->mdev);
2262         c->netdev   = priv->netdev;
2263         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.hw_objs.mkey);
2264         c->num_tc   = mlx5e_get_dcb_num_tc(params);
2265         c->xdp      = !!params->xdp_prog;
2266         c->stats    = &priv->channel_stats[ix]->ch;
2267         c->aff_mask = irq_get_effective_affinity_mask(irq);
2268         c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
2269
2270         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
2271
2272         err = mlx5e_open_queues(c, params, cparam);
2273         if (unlikely(err))
2274                 goto err_napi_del;
2275
2276         if (xsk_pool) {
2277                 mlx5e_build_xsk_param(xsk_pool, &xsk);
2278                 err = mlx5e_open_xsk(priv, params, &xsk, xsk_pool, c);
2279                 if (unlikely(err))
2280                         goto err_close_queues;
2281         }
2282
2283         *cp = c;
2284
2285         return 0;
2286
2287 err_close_queues:
2288         mlx5e_close_queues(c);
2289
2290 err_napi_del:
2291         netif_napi_del(&c->napi);
2292
2293         kvfree(c);
2294
2295         return err;
2296 }
2297
2298 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2299 {
2300         int tc;
2301
2302         napi_enable(&c->napi);
2303
2304         for (tc = 0; tc < c->num_tc; tc++)
2305                 mlx5e_activate_txqsq(&c->sq[tc]);
2306         mlx5e_activate_icosq(&c->icosq);
2307         mlx5e_activate_icosq(&c->async_icosq);
2308         mlx5e_activate_rq(&c->rq);
2309
2310         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2311                 mlx5e_activate_xsk(c);
2312 }
2313
2314 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2315 {
2316         int tc;
2317
2318         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2319                 mlx5e_deactivate_xsk(c);
2320
2321         mlx5e_deactivate_rq(&c->rq);
2322         mlx5e_deactivate_icosq(&c->async_icosq);
2323         mlx5e_deactivate_icosq(&c->icosq);
2324         for (tc = 0; tc < c->num_tc; tc++)
2325                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2326         mlx5e_qos_deactivate_queues(c);
2327
2328         napi_disable(&c->napi);
2329 }
2330
2331 static void mlx5e_close_channel(struct mlx5e_channel *c)
2332 {
2333         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2334                 mlx5e_close_xsk(c);
2335         mlx5e_close_queues(c);
2336         mlx5e_qos_close_queues(c);
2337         netif_napi_del(&c->napi);
2338
2339         kvfree(c);
2340 }
2341
2342 int mlx5e_open_channels(struct mlx5e_priv *priv,
2343                         struct mlx5e_channels *chs)
2344 {
2345         struct mlx5e_channel_param *cparam;
2346         int err = -ENOMEM;
2347         int i;
2348
2349         chs->num = chs->params.num_channels;
2350
2351         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2352         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2353         if (!chs->c || !cparam)
2354                 goto err_free;
2355
2356         err = mlx5e_build_channel_param(priv->mdev, &chs->params, priv->q_counter, cparam);
2357         if (err)
2358                 goto err_free;
2359
2360         for (i = 0; i < chs->num; i++) {
2361                 struct xsk_buff_pool *xsk_pool = NULL;
2362
2363                 if (chs->params.xdp_prog)
2364                         xsk_pool = mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, i);
2365
2366                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, xsk_pool, &chs->c[i]);
2367                 if (err)
2368                         goto err_close_channels;
2369         }
2370
2371         if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS) || chs->params.ptp_rx) {
2372                 err = mlx5e_ptp_open(priv, &chs->params, chs->c[0]->lag_port, &chs->ptp);
2373                 if (err)
2374                         goto err_close_channels;
2375         }
2376
2377         err = mlx5e_qos_open_queues(priv, chs);
2378         if (err)
2379                 goto err_close_ptp;
2380
2381         mlx5e_health_channels_update(priv);
2382         kvfree(cparam);
2383         return 0;
2384
2385 err_close_ptp:
2386         if (chs->ptp)
2387                 mlx5e_ptp_close(chs->ptp);
2388
2389 err_close_channels:
2390         for (i--; i >= 0; i--)
2391                 mlx5e_close_channel(chs->c[i]);
2392
2393 err_free:
2394         kfree(chs->c);
2395         kvfree(cparam);
2396         chs->num = 0;
2397         return err;
2398 }
2399
2400 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2401 {
2402         int i;
2403
2404         for (i = 0; i < chs->num; i++)
2405                 mlx5e_activate_channel(chs->c[i]);
2406
2407         if (chs->ptp)
2408                 mlx5e_ptp_activate_channel(chs->ptp);
2409 }
2410
2411 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2412
2413 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2414 {
2415         int err = 0;
2416         int i;
2417
2418         for (i = 0; i < chs->num; i++) {
2419                 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2420
2421                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2422
2423                 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2424                  * doesn't provide any Fill Ring entries at the setup stage.
2425                  */
2426         }
2427
2428         return err ? -ETIMEDOUT : 0;
2429 }
2430
2431 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2432 {
2433         int i;
2434
2435         if (chs->ptp)
2436                 mlx5e_ptp_deactivate_channel(chs->ptp);
2437
2438         for (i = 0; i < chs->num; i++)
2439                 mlx5e_deactivate_channel(chs->c[i]);
2440 }
2441
2442 void mlx5e_close_channels(struct mlx5e_channels *chs)
2443 {
2444         int i;
2445
2446         if (chs->ptp) {
2447                 mlx5e_ptp_close(chs->ptp);
2448                 chs->ptp = NULL;
2449         }
2450         for (i = 0; i < chs->num; i++)
2451                 mlx5e_close_channel(chs->c[i]);
2452
2453         kfree(chs->c);
2454         chs->num = 0;
2455 }
2456
2457 static int mlx5e_modify_tirs_packet_merge(struct mlx5e_priv *priv)
2458 {
2459         struct mlx5e_rx_res *res = priv->rx_res;
2460
2461         return mlx5e_rx_res_packet_merge_set_param(res, &priv->channels.params.packet_merge);
2462 }
2463
2464 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_packet_merge);
2465
2466 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2467                          struct mlx5e_params *params, u16 mtu)
2468 {
2469         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2470         int err;
2471
2472         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2473         if (err)
2474                 return err;
2475
2476         /* Update vport context MTU */
2477         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2478         return 0;
2479 }
2480
2481 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2482                             struct mlx5e_params *params, u16 *mtu)
2483 {
2484         u16 hw_mtu = 0;
2485         int err;
2486
2487         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2488         if (err || !hw_mtu) /* fallback to port oper mtu */
2489                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2490
2491         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2492 }
2493
2494 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2495 {
2496         struct mlx5e_params *params = &priv->channels.params;
2497         struct net_device *netdev = priv->netdev;
2498         struct mlx5_core_dev *mdev = priv->mdev;
2499         u16 mtu;
2500         int err;
2501
2502         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2503         if (err)
2504                 return err;
2505
2506         mlx5e_query_mtu(mdev, params, &mtu);
2507         if (mtu != params->sw_mtu)
2508                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2509                             __func__, mtu, params->sw_mtu);
2510
2511         params->sw_mtu = mtu;
2512         return 0;
2513 }
2514
2515 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu);
2516
2517 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2518 {
2519         struct mlx5e_params *params = &priv->channels.params;
2520         struct net_device *netdev   = priv->netdev;
2521         struct mlx5_core_dev *mdev  = priv->mdev;
2522         u16 max_mtu;
2523
2524         /* MTU range: 68 - hw-specific max */
2525         netdev->min_mtu = ETH_MIN_MTU;
2526
2527         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2528         netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2529                                 ETH_MAX_MTU);
2530 }
2531
2532 static int mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc,
2533                                 struct netdev_tc_txq *tc_to_txq)
2534 {
2535         int tc, err;
2536
2537         netdev_reset_tc(netdev);
2538
2539         if (ntc == 1)
2540                 return 0;
2541
2542         err = netdev_set_num_tc(netdev, ntc);
2543         if (err) {
2544                 netdev_WARN(netdev, "netdev_set_num_tc failed (%d), ntc = %d\n", err, ntc);
2545                 return err;
2546         }
2547
2548         for (tc = 0; tc < ntc; tc++) {
2549                 u16 count, offset;
2550
2551                 count = tc_to_txq[tc].count;
2552                 offset = tc_to_txq[tc].offset;
2553                 netdev_set_tc_queue(netdev, tc, count, offset);
2554         }
2555
2556         return 0;
2557 }
2558
2559 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv)
2560 {
2561         int qos_queues, nch, ntc, num_txqs, err;
2562
2563         qos_queues = mlx5e_qos_cur_leaf_nodes(priv);
2564
2565         nch = priv->channels.params.num_channels;
2566         ntc = mlx5e_get_dcb_num_tc(&priv->channels.params);
2567         num_txqs = nch * ntc + qos_queues;
2568         if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_PORT_TS))
2569                 num_txqs += ntc;
2570
2571         mlx5e_dbg(DRV, priv, "Setting num_txqs %d\n", num_txqs);
2572         err = netif_set_real_num_tx_queues(priv->netdev, num_txqs);
2573         if (err)
2574                 netdev_warn(priv->netdev, "netif_set_real_num_tx_queues failed, %d\n", err);
2575
2576         return err;
2577 }
2578
2579 static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv)
2580 {
2581         struct netdev_tc_txq old_tc_to_txq[TC_MAX_QUEUE], *tc_to_txq;
2582         struct net_device *netdev = priv->netdev;
2583         int old_num_txqs, old_ntc;
2584         int num_rxqs, nch, ntc;
2585         int err;
2586         int i;
2587
2588         old_num_txqs = netdev->real_num_tx_queues;
2589         old_ntc = netdev->num_tc ? : 1;
2590         for (i = 0; i < ARRAY_SIZE(old_tc_to_txq); i++)
2591                 old_tc_to_txq[i] = netdev->tc_to_txq[i];
2592
2593         nch = priv->channels.params.num_channels;
2594         ntc = priv->channels.params.mqprio.num_tc;
2595         num_rxqs = nch * priv->profile->rq_groups;
2596         tc_to_txq = priv->channels.params.mqprio.tc_to_txq;
2597
2598         err = mlx5e_netdev_set_tcs(netdev, nch, ntc, tc_to_txq);
2599         if (err)
2600                 goto err_out;
2601         err = mlx5e_update_tx_netdev_queues(priv);
2602         if (err)
2603                 goto err_tcs;
2604         err = netif_set_real_num_rx_queues(netdev, num_rxqs);
2605         if (err) {
2606                 netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err);
2607                 goto err_txqs;
2608         }
2609         if (priv->mqprio_rl != priv->channels.params.mqprio.channel.rl) {
2610                 if (priv->mqprio_rl) {
2611                         mlx5e_mqprio_rl_cleanup(priv->mqprio_rl);
2612                         mlx5e_mqprio_rl_free(priv->mqprio_rl);
2613                 }
2614                 priv->mqprio_rl = priv->channels.params.mqprio.channel.rl;
2615         }
2616
2617         return 0;
2618
2619 err_txqs:
2620         /* netif_set_real_num_rx_queues could fail only when nch increased. Only
2621          * one of nch and ntc is changed in this function. That means, the call
2622          * to netif_set_real_num_tx_queues below should not fail, because it
2623          * decreases the number of TX queues.
2624          */
2625         WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs));
2626
2627 err_tcs:
2628         WARN_ON_ONCE(mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc,
2629                                           old_tc_to_txq));
2630 err_out:
2631         return err;
2632 }
2633
2634 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_update_netdev_queues);
2635
2636 static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv,
2637                                            struct mlx5e_params *params)
2638 {
2639         struct mlx5_core_dev *mdev = priv->mdev;
2640         int num_comp_vectors, ix, irq;
2641
2642         num_comp_vectors = mlx5_comp_vectors_count(mdev);
2643
2644         for (ix = 0; ix < params->num_channels; ix++) {
2645                 cpumask_clear(priv->scratchpad.cpumask);
2646
2647                 for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) {
2648                         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(mdev, irq));
2649
2650                         cpumask_set_cpu(cpu, priv->scratchpad.cpumask);
2651                 }
2652
2653                 netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix);
2654         }
2655 }
2656
2657 static int mlx5e_num_channels_changed(struct mlx5e_priv *priv)
2658 {
2659         u16 count = priv->channels.params.num_channels;
2660         int err;
2661
2662         err = mlx5e_update_netdev_queues(priv);
2663         if (err)
2664                 return err;
2665
2666         mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params);
2667
2668         /* This function may be called on attach, before priv->rx_res is created. */
2669         if (!netif_is_rxfh_configured(priv->netdev) && priv->rx_res)
2670                 mlx5e_rx_res_rss_set_indir_uniform(priv->rx_res, count);
2671
2672         return 0;
2673 }
2674
2675 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed);
2676
2677 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv)
2678 {
2679         int i, ch, tc, num_tc;
2680
2681         ch = priv->channels.num;
2682         num_tc = mlx5e_get_dcb_num_tc(&priv->channels.params);
2683
2684         for (i = 0; i < ch; i++) {
2685                 for (tc = 0; tc < num_tc; tc++) {
2686                         struct mlx5e_channel *c = priv->channels.c[i];
2687                         struct mlx5e_txqsq *sq = &c->sq[tc];
2688
2689                         priv->txq2sq[sq->txq_ix] = sq;
2690                 }
2691         }
2692
2693         if (!priv->channels.ptp)
2694                 goto out;
2695
2696         if (!test_bit(MLX5E_PTP_STATE_TX, priv->channels.ptp->state))
2697                 goto out;
2698
2699         for (tc = 0; tc < num_tc; tc++) {
2700                 struct mlx5e_ptp *c = priv->channels.ptp;
2701                 struct mlx5e_txqsq *sq = &c->ptpsq[tc].txqsq;
2702
2703                 priv->txq2sq[sq->txq_ix] = sq;
2704         }
2705
2706 out:
2707         /* Make the change to txq2sq visible before the queue is started.
2708          * As mlx5e_xmit runs under a spinlock, there is an implicit ACQUIRE,
2709          * which pairs with this barrier.
2710          */
2711         smp_wmb();
2712 }
2713
2714 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2715 {
2716         mlx5e_build_txq_maps(priv);
2717         mlx5e_activate_channels(&priv->channels);
2718         mlx5e_qos_activate_queues(priv);
2719         mlx5e_xdp_tx_enable(priv);
2720
2721         /* dev_watchdog() wants all TX queues to be started when the carrier is
2722          * OK, including the ones in range real_num_tx_queues..num_tx_queues-1.
2723          * Make it happy to avoid TX timeout false alarms.
2724          */
2725         netif_tx_start_all_queues(priv->netdev);
2726
2727         if (mlx5e_is_vport_rep(priv))
2728                 mlx5e_add_sqs_fwd_rules(priv);
2729
2730         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2731
2732         if (priv->rx_res)
2733                 mlx5e_rx_res_channels_activate(priv->rx_res, &priv->channels);
2734 }
2735
2736 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2737 {
2738         if (priv->rx_res)
2739                 mlx5e_rx_res_channels_deactivate(priv->rx_res);
2740
2741         if (mlx5e_is_vport_rep(priv))
2742                 mlx5e_remove_sqs_fwd_rules(priv);
2743
2744         /* The results of ndo_select_queue are unreliable, while netdev config
2745          * is being changed (real_num_tx_queues, num_tc). Stop all queues to
2746          * prevent ndo_start_xmit from being called, so that it can assume that
2747          * the selected queue is always valid.
2748          */
2749         netif_tx_disable(priv->netdev);
2750
2751         mlx5e_xdp_tx_disable(priv);
2752         mlx5e_deactivate_channels(&priv->channels);
2753 }
2754
2755 static int mlx5e_switch_priv_params(struct mlx5e_priv *priv,
2756                                     struct mlx5e_params *new_params,
2757                                     mlx5e_fp_preactivate preactivate,
2758                                     void *context)
2759 {
2760         struct mlx5e_params old_params;
2761
2762         old_params = priv->channels.params;
2763         priv->channels.params = *new_params;
2764
2765         if (preactivate) {
2766                 int err;
2767
2768                 err = preactivate(priv, context);
2769                 if (err) {
2770                         priv->channels.params = old_params;
2771                         return err;
2772                 }
2773         }
2774
2775         return 0;
2776 }
2777
2778 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2779                                       struct mlx5e_channels *new_chs,
2780                                       mlx5e_fp_preactivate preactivate,
2781                                       void *context)
2782 {
2783         struct net_device *netdev = priv->netdev;
2784         struct mlx5e_channels old_chs;
2785         int carrier_ok;
2786         int err = 0;
2787
2788         carrier_ok = netif_carrier_ok(netdev);
2789         netif_carrier_off(netdev);
2790
2791         mlx5e_deactivate_priv_channels(priv);
2792
2793         old_chs = priv->channels;
2794         priv->channels = *new_chs;
2795
2796         /* New channels are ready to roll, call the preactivate hook if needed
2797          * to modify HW settings or update kernel parameters.
2798          */
2799         if (preactivate) {
2800                 err = preactivate(priv, context);
2801                 if (err) {
2802                         priv->channels = old_chs;
2803                         goto out;
2804                 }
2805         }
2806
2807         mlx5e_close_channels(&old_chs);
2808         priv->profile->update_rx(priv);
2809
2810         mlx5e_selq_apply(&priv->selq);
2811 out:
2812         mlx5e_activate_priv_channels(priv);
2813
2814         /* return carrier back if needed */
2815         if (carrier_ok)
2816                 netif_carrier_on(netdev);
2817
2818         return err;
2819 }
2820
2821 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
2822                              struct mlx5e_params *params,
2823                              mlx5e_fp_preactivate preactivate,
2824                              void *context, bool reset)
2825 {
2826         struct mlx5e_channels new_chs = {};
2827         int err;
2828
2829         reset &= test_bit(MLX5E_STATE_OPENED, &priv->state);
2830         if (!reset)
2831                 return mlx5e_switch_priv_params(priv, params, preactivate, context);
2832
2833         new_chs.params = *params;
2834
2835         mlx5e_selq_prepare(&priv->selq, &new_chs.params, !!priv->htb.maj_id);
2836
2837         err = mlx5e_open_channels(priv, &new_chs);
2838         if (err)
2839                 goto err_cancel_selq;
2840
2841         err = mlx5e_switch_priv_channels(priv, &new_chs, preactivate, context);
2842         if (err)
2843                 goto err_close;
2844
2845         return 0;
2846
2847 err_close:
2848         mlx5e_close_channels(&new_chs);
2849
2850 err_cancel_selq:
2851         mlx5e_selq_cancel(&priv->selq);
2852         return err;
2853 }
2854
2855 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
2856 {
2857         return mlx5e_safe_switch_params(priv, &priv->channels.params, NULL, NULL, true);
2858 }
2859
2860 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2861 {
2862         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2863         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2864 }
2865
2866 static void mlx5e_modify_admin_state(struct mlx5_core_dev *mdev,
2867                                      enum mlx5_port_status state)
2868 {
2869         struct mlx5_eswitch *esw = mdev->priv.eswitch;
2870         int vport_admin_state;
2871
2872         mlx5_set_port_admin_status(mdev, state);
2873
2874         if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS ||
2875             !MLX5_CAP_GEN(mdev, uplink_follow))
2876                 return;
2877
2878         if (state == MLX5_PORT_UP)
2879                 vport_admin_state = MLX5_VPORT_ADMIN_STATE_AUTO;
2880         else
2881                 vport_admin_state = MLX5_VPORT_ADMIN_STATE_DOWN;
2882
2883         mlx5_eswitch_set_vport_state(esw, MLX5_VPORT_UPLINK, vport_admin_state);
2884 }
2885
2886 int mlx5e_open_locked(struct net_device *netdev)
2887 {
2888         struct mlx5e_priv *priv = netdev_priv(netdev);
2889         int err;
2890
2891         mlx5e_selq_prepare(&priv->selq, &priv->channels.params, !!priv->htb.maj_id);
2892
2893         set_bit(MLX5E_STATE_OPENED, &priv->state);
2894
2895         err = mlx5e_open_channels(priv, &priv->channels);
2896         if (err)
2897                 goto err_clear_state_opened_flag;
2898
2899         priv->profile->update_rx(priv);
2900         mlx5e_selq_apply(&priv->selq);
2901         mlx5e_activate_priv_channels(priv);
2902         mlx5e_apply_traps(priv, true);
2903         if (priv->profile->update_carrier)
2904                 priv->profile->update_carrier(priv);
2905
2906         mlx5e_queue_update_stats(priv);
2907         return 0;
2908
2909 err_clear_state_opened_flag:
2910         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2911         mlx5e_selq_cancel(&priv->selq);
2912         return err;
2913 }
2914
2915 int mlx5e_open(struct net_device *netdev)
2916 {
2917         struct mlx5e_priv *priv = netdev_priv(netdev);
2918         int err;
2919
2920         mutex_lock(&priv->state_lock);
2921         err = mlx5e_open_locked(netdev);
2922         if (!err)
2923                 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_UP);
2924         mutex_unlock(&priv->state_lock);
2925
2926         return err;
2927 }
2928
2929 int mlx5e_close_locked(struct net_device *netdev)
2930 {
2931         struct mlx5e_priv *priv = netdev_priv(netdev);
2932
2933         /* May already be CLOSED in case a previous configuration operation
2934          * (e.g RX/TX queue size change) that involves close&open failed.
2935          */
2936         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2937                 return 0;
2938
2939         mlx5e_apply_traps(priv, false);
2940         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2941
2942         netif_carrier_off(priv->netdev);
2943         mlx5e_deactivate_priv_channels(priv);
2944         mlx5e_close_channels(&priv->channels);
2945
2946         return 0;
2947 }
2948
2949 int mlx5e_close(struct net_device *netdev)
2950 {
2951         struct mlx5e_priv *priv = netdev_priv(netdev);
2952         int err;
2953
2954         if (!netif_device_present(netdev))
2955                 return -ENODEV;
2956
2957         mutex_lock(&priv->state_lock);
2958         mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_DOWN);
2959         err = mlx5e_close_locked(netdev);
2960         mutex_unlock(&priv->state_lock);
2961
2962         return err;
2963 }
2964
2965 static void mlx5e_free_drop_rq(struct mlx5e_rq *rq)
2966 {
2967         mlx5_wq_destroy(&rq->wq_ctrl);
2968 }
2969
2970 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2971                                struct mlx5e_rq *rq,
2972                                struct mlx5e_rq_param *param)
2973 {
2974         void *rqc = param->rqc;
2975         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2976         int err;
2977
2978         param->wq.db_numa_node = param->wq.buf_numa_node;
2979
2980         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
2981                                  &rq->wq_ctrl);
2982         if (err)
2983                 return err;
2984
2985         /* Mark as unused given "Drop-RQ" packets never reach XDP */
2986         xdp_rxq_info_unused(&rq->xdp_rxq);
2987
2988         rq->mdev = mdev;
2989
2990         return 0;
2991 }
2992
2993 static int mlx5e_alloc_drop_cq(struct mlx5e_priv *priv,
2994                                struct mlx5e_cq *cq,
2995                                struct mlx5e_cq_param *param)
2996 {
2997         struct mlx5_core_dev *mdev = priv->mdev;
2998
2999         param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
3000         param->wq.db_numa_node  = dev_to_node(mlx5_core_dma_dev(mdev));
3001
3002         return mlx5e_alloc_cq_common(priv, param, cq);
3003 }
3004
3005 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3006                        struct mlx5e_rq *drop_rq)
3007 {
3008         struct mlx5_core_dev *mdev = priv->mdev;
3009         struct mlx5e_cq_param cq_param = {};
3010         struct mlx5e_rq_param rq_param = {};
3011         struct mlx5e_cq *cq = &drop_rq->cq;
3012         int err;
3013
3014         mlx5e_build_drop_rq_param(mdev, priv->drop_rq_q_counter, &rq_param);
3015
3016         err = mlx5e_alloc_drop_cq(priv, cq, &cq_param);
3017         if (err)
3018                 return err;
3019
3020         err = mlx5e_create_cq(cq, &cq_param);
3021         if (err)
3022                 goto err_free_cq;
3023
3024         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3025         if (err)
3026                 goto err_destroy_cq;
3027
3028         err = mlx5e_create_rq(drop_rq, &rq_param);
3029         if (err)
3030                 goto err_free_rq;
3031
3032         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3033         if (err)
3034                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3035
3036         return 0;
3037
3038 err_free_rq:
3039         mlx5e_free_drop_rq(drop_rq);
3040
3041 err_destroy_cq:
3042         mlx5e_destroy_cq(cq);
3043
3044 err_free_cq:
3045         mlx5e_free_cq(cq);
3046
3047         return err;
3048 }
3049
3050 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3051 {
3052         mlx5e_destroy_rq(drop_rq);
3053         mlx5e_free_drop_rq(drop_rq);
3054         mlx5e_destroy_cq(&drop_rq->cq);
3055         mlx5e_free_cq(&drop_rq->cq);
3056 }
3057
3058 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
3059 {
3060         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3061
3062         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.hw_objs.td.tdn);
3063
3064         if (MLX5_GET(tisc, tisc, tls_en))
3065                 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.hw_objs.pdn);
3066
3067         if (mlx5_lag_is_lacp_owner(mdev))
3068                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3069
3070         return mlx5_core_create_tis(mdev, in, tisn);
3071 }
3072
3073 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3074 {
3075         mlx5_core_destroy_tis(mdev, tisn);
3076 }
3077
3078 void mlx5e_destroy_tises(struct mlx5e_priv *priv)
3079 {
3080         int tc, i;
3081
3082         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++)
3083                 for (tc = 0; tc < priv->profile->max_tc; tc++)
3084                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3085 }
3086
3087 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
3088 {
3089         return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
3090 }
3091
3092 int mlx5e_create_tises(struct mlx5e_priv *priv)
3093 {
3094         int tc, i;
3095         int err;
3096
3097         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) {
3098                 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3099                         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3100                         void *tisc;
3101
3102                         tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3103
3104                         MLX5_SET(tisc, tisc, prio, tc << 1);
3105
3106                         if (mlx5e_lag_should_assign_affinity(priv->mdev))
3107                                 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
3108
3109                         err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]);
3110                         if (err)
3111                                 goto err_close_tises;
3112                 }
3113         }
3114
3115         return 0;
3116
3117 err_close_tises:
3118         for (; i >= 0; i--) {
3119                 for (tc--; tc >= 0; tc--)
3120                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3121                 tc = priv->profile->max_tc;
3122         }
3123
3124         return err;
3125 }
3126
3127 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3128 {
3129         mlx5e_destroy_tises(priv);
3130 }
3131
3132 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3133 {
3134         int err = 0;
3135         int i;
3136
3137         for (i = 0; i < chs->num; i++) {
3138                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3139                 if (err)
3140                         return err;
3141         }
3142
3143         return 0;
3144 }
3145
3146 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3147 {
3148         int err;
3149         int i;
3150
3151         for (i = 0; i < chs->num; i++) {
3152                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3153                 if (err)
3154                         return err;
3155         }
3156         if (chs->ptp && test_bit(MLX5E_PTP_STATE_RX, chs->ptp->state))
3157                 return mlx5e_modify_rq_vsd(&chs->ptp->rq, vsd);
3158
3159         return 0;
3160 }
3161
3162 static void mlx5e_mqprio_build_default_tc_to_txq(struct netdev_tc_txq *tc_to_txq,
3163                                                  int ntc, int nch)
3164 {
3165         int tc;
3166
3167         memset(tc_to_txq, 0, sizeof(*tc_to_txq) * TC_MAX_QUEUE);
3168
3169         /* Map netdev TCs to offset 0.
3170          * We have our own UP to TXQ mapping for DCB mode of QoS
3171          */
3172         for (tc = 0; tc < ntc; tc++) {
3173                 tc_to_txq[tc] = (struct netdev_tc_txq) {
3174                         .count = nch,
3175                         .offset = 0,
3176                 };
3177         }
3178 }
3179
3180 static void mlx5e_mqprio_build_tc_to_txq(struct netdev_tc_txq *tc_to_txq,
3181                                          struct tc_mqprio_qopt *qopt)
3182 {
3183         int tc;
3184
3185         for (tc = 0; tc < TC_MAX_QUEUE; tc++) {
3186                 tc_to_txq[tc] = (struct netdev_tc_txq) {
3187                         .count = qopt->count[tc],
3188                         .offset = qopt->offset[tc],
3189                 };
3190         }
3191 }
3192
3193 static void mlx5e_params_mqprio_dcb_set(struct mlx5e_params *params, u8 num_tc)
3194 {
3195         params->mqprio.mode = TC_MQPRIO_MODE_DCB;
3196         params->mqprio.num_tc = num_tc;
3197         params->mqprio.channel.rl = NULL;
3198         mlx5e_mqprio_build_default_tc_to_txq(params->mqprio.tc_to_txq, num_tc,
3199                                              params->num_channels);
3200 }
3201
3202 static void mlx5e_params_mqprio_channel_set(struct mlx5e_params *params,
3203                                             struct tc_mqprio_qopt *qopt,
3204                                             struct mlx5e_mqprio_rl *rl)
3205 {
3206         params->mqprio.mode = TC_MQPRIO_MODE_CHANNEL;
3207         params->mqprio.num_tc = qopt->num_tc;
3208         params->mqprio.channel.rl = rl;
3209         mlx5e_mqprio_build_tc_to_txq(params->mqprio.tc_to_txq, qopt);
3210 }
3211
3212 static void mlx5e_params_mqprio_reset(struct mlx5e_params *params)
3213 {
3214         mlx5e_params_mqprio_dcb_set(params, 1);
3215 }
3216
3217 static int mlx5e_setup_tc_mqprio_dcb(struct mlx5e_priv *priv,
3218                                      struct tc_mqprio_qopt *mqprio)
3219 {
3220         struct mlx5e_params new_params;
3221         u8 tc = mqprio->num_tc;
3222         int err;
3223
3224         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3225
3226         if (tc && tc != MLX5E_MAX_NUM_TC)
3227                 return -EINVAL;
3228
3229         new_params = priv->channels.params;
3230         mlx5e_params_mqprio_dcb_set(&new_params, tc ? tc : 1);
3231
3232         err = mlx5e_safe_switch_params(priv, &new_params,
3233                                        mlx5e_num_channels_changed_ctx, NULL, true);
3234
3235         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3236                                     mlx5e_get_dcb_num_tc(&priv->channels.params));
3237         return err;
3238 }
3239
3240 static int mlx5e_mqprio_channel_validate(struct mlx5e_priv *priv,
3241                                          struct tc_mqprio_qopt_offload *mqprio)
3242 {
3243         struct net_device *netdev = priv->netdev;
3244         struct mlx5e_ptp *ptp_channel;
3245         int agg_count = 0;
3246         int i;
3247
3248         ptp_channel = priv->channels.ptp;
3249         if (ptp_channel && test_bit(MLX5E_PTP_STATE_TX, ptp_channel->state)) {
3250                 netdev_err(netdev,
3251                            "Cannot activate MQPRIO mode channel since it conflicts with TX port TS\n");
3252                 return -EINVAL;
3253         }
3254
3255         if (mqprio->qopt.offset[0] != 0 || mqprio->qopt.num_tc < 1 ||
3256             mqprio->qopt.num_tc > MLX5E_MAX_NUM_MQPRIO_CH_TC)
3257                 return -EINVAL;
3258
3259         for (i = 0; i < mqprio->qopt.num_tc; i++) {
3260                 if (!mqprio->qopt.count[i]) {
3261                         netdev_err(netdev, "Zero size for queue-group (%d) is not supported\n", i);
3262                         return -EINVAL;
3263                 }
3264                 if (mqprio->min_rate[i]) {
3265                         netdev_err(netdev, "Min tx rate is not supported\n");
3266                         return -EINVAL;
3267                 }
3268
3269                 if (mqprio->max_rate[i]) {
3270                         int err;
3271
3272                         err = mlx5e_qos_bytes_rate_check(priv->mdev, mqprio->max_rate[i]);
3273                         if (err)
3274                                 return err;
3275                 }
3276
3277                 if (mqprio->qopt.offset[i] != agg_count) {
3278                         netdev_err(netdev, "Discontinuous queues config is not supported\n");
3279                         return -EINVAL;
3280                 }
3281                 agg_count += mqprio->qopt.count[i];
3282         }
3283
3284         if (priv->channels.params.num_channels != agg_count) {
3285                 netdev_err(netdev, "Num of queues (%d) does not match available (%d)\n",
3286                            agg_count, priv->channels.params.num_channels);
3287                 return -EINVAL;
3288         }
3289
3290         return 0;
3291 }
3292
3293 static bool mlx5e_mqprio_rate_limit(struct tc_mqprio_qopt_offload *mqprio)
3294 {
3295         int tc;
3296
3297         for (tc = 0; tc < mqprio->qopt.num_tc; tc++)
3298                 if (mqprio->max_rate[tc])
3299                         return true;
3300         return false;
3301 }
3302
3303 static int mlx5e_setup_tc_mqprio_channel(struct mlx5e_priv *priv,
3304                                          struct tc_mqprio_qopt_offload *mqprio)
3305 {
3306         mlx5e_fp_preactivate preactivate;
3307         struct mlx5e_params new_params;
3308         struct mlx5e_mqprio_rl *rl;
3309         bool nch_changed;
3310         int err;
3311
3312         err = mlx5e_mqprio_channel_validate(priv, mqprio);
3313         if (err)
3314                 return err;
3315
3316         rl = NULL;
3317         if (mlx5e_mqprio_rate_limit(mqprio)) {
3318                 rl = mlx5e_mqprio_rl_alloc();
3319                 if (!rl)
3320                         return -ENOMEM;
3321                 err = mlx5e_mqprio_rl_init(rl, priv->mdev, mqprio->qopt.num_tc,
3322                                            mqprio->max_rate);
3323                 if (err) {
3324                         mlx5e_mqprio_rl_free(rl);
3325                         return err;
3326                 }
3327         }
3328
3329         new_params = priv->channels.params;
3330         mlx5e_params_mqprio_channel_set(&new_params, &mqprio->qopt, rl);
3331
3332         nch_changed = mlx5e_get_dcb_num_tc(&priv->channels.params) > 1;
3333         preactivate = nch_changed ? mlx5e_num_channels_changed_ctx :
3334                 mlx5e_update_netdev_queues_ctx;
3335         err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, true);
3336         if (err && rl) {
3337                 mlx5e_mqprio_rl_cleanup(rl);
3338                 mlx5e_mqprio_rl_free(rl);
3339         }
3340
3341         return err;
3342 }
3343
3344 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3345                                  struct tc_mqprio_qopt_offload *mqprio)
3346 {
3347         /* MQPRIO is another toplevel qdisc that can't be attached
3348          * simultaneously with the offloaded HTB.
3349          */
3350         if (WARN_ON(priv->htb.maj_id))
3351                 return -EINVAL;
3352
3353         switch (mqprio->mode) {
3354         case TC_MQPRIO_MODE_DCB:
3355                 return mlx5e_setup_tc_mqprio_dcb(priv, &mqprio->qopt);
3356         case TC_MQPRIO_MODE_CHANNEL:
3357                 return mlx5e_setup_tc_mqprio_channel(priv, mqprio);
3358         default:
3359                 return -EOPNOTSUPP;
3360         }
3361 }
3362
3363 static int mlx5e_setup_tc_htb(struct mlx5e_priv *priv, struct tc_htb_qopt_offload *htb)
3364 {
3365         int res;
3366
3367         switch (htb->command) {
3368         case TC_HTB_CREATE:
3369                 return mlx5e_htb_root_add(priv, htb->parent_classid, htb->classid,
3370                                           htb->extack);
3371         case TC_HTB_DESTROY:
3372                 return mlx5e_htb_root_del(priv);
3373         case TC_HTB_LEAF_ALLOC_QUEUE:
3374                 res = mlx5e_htb_leaf_alloc_queue(priv, htb->classid, htb->parent_classid,
3375                                                  htb->rate, htb->ceil, htb->extack);
3376                 if (res < 0)
3377                         return res;
3378                 htb->qid = res;
3379                 return 0;
3380         case TC_HTB_LEAF_TO_INNER:
3381                 return mlx5e_htb_leaf_to_inner(priv, htb->parent_classid, htb->classid,
3382                                                htb->rate, htb->ceil, htb->extack);
3383         case TC_HTB_LEAF_DEL:
3384                 return mlx5e_htb_leaf_del(priv, &htb->classid, htb->extack);
3385         case TC_HTB_LEAF_DEL_LAST:
3386         case TC_HTB_LEAF_DEL_LAST_FORCE:
3387                 return mlx5e_htb_leaf_del_last(priv, htb->classid,
3388                                                htb->command == TC_HTB_LEAF_DEL_LAST_FORCE,
3389                                                htb->extack);
3390         case TC_HTB_NODE_MODIFY:
3391                 return mlx5e_htb_node_modify(priv, htb->classid, htb->rate, htb->ceil,
3392                                              htb->extack);
3393         case TC_HTB_LEAF_QUERY_QUEUE:
3394                 res = mlx5e_get_txq_by_classid(priv, htb->classid);
3395                 if (res < 0)
3396                         return res;
3397                 htb->qid = res;
3398                 return 0;
3399         default:
3400                 return -EOPNOTSUPP;
3401         }
3402 }
3403
3404 static LIST_HEAD(mlx5e_block_cb_list);
3405
3406 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3407                           void *type_data)
3408 {
3409         struct mlx5e_priv *priv = netdev_priv(dev);
3410         bool tc_unbind = false;
3411         int err;
3412
3413         if (type == TC_SETUP_BLOCK &&
3414             ((struct flow_block_offload *)type_data)->command == FLOW_BLOCK_UNBIND)
3415                 tc_unbind = true;
3416
3417         if (!netif_device_present(dev) && !tc_unbind)
3418                 return -ENODEV;
3419
3420         switch (type) {
3421         case TC_SETUP_BLOCK: {
3422                 struct flow_block_offload *f = type_data;
3423
3424                 f->unlocked_driver_cb = true;
3425                 return flow_block_cb_setup_simple(type_data,
3426                                                   &mlx5e_block_cb_list,
3427                                                   mlx5e_setup_tc_block_cb,
3428                                                   priv, priv, true);
3429         }
3430         case TC_SETUP_QDISC_MQPRIO:
3431                 mutex_lock(&priv->state_lock);
3432                 err = mlx5e_setup_tc_mqprio(priv, type_data);
3433                 mutex_unlock(&priv->state_lock);
3434                 return err;
3435         case TC_SETUP_QDISC_HTB:
3436                 mutex_lock(&priv->state_lock);
3437                 err = mlx5e_setup_tc_htb(priv, type_data);
3438                 mutex_unlock(&priv->state_lock);
3439                 return err;
3440         default:
3441                 return -EOPNOTSUPP;
3442         }
3443 }
3444
3445 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3446 {
3447         int i;
3448
3449         for (i = 0; i < priv->stats_nch; i++) {
3450                 struct mlx5e_channel_stats *channel_stats = priv->channel_stats[i];
3451                 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3452                 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3453                 int j;
3454
3455                 s->rx_packets   += rq_stats->packets + xskrq_stats->packets;
3456                 s->rx_bytes     += rq_stats->bytes + xskrq_stats->bytes;
3457                 s->multicast    += rq_stats->mcast_packets + xskrq_stats->mcast_packets;
3458
3459                 for (j = 0; j < priv->max_opened_tc; j++) {
3460                         struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3461
3462                         s->tx_packets    += sq_stats->packets;
3463                         s->tx_bytes      += sq_stats->bytes;
3464                         s->tx_dropped    += sq_stats->dropped;
3465                 }
3466         }
3467         if (priv->tx_ptp_opened) {
3468                 for (i = 0; i < priv->max_opened_tc; i++) {
3469                         struct mlx5e_sq_stats *sq_stats = &priv->ptp_stats.sq[i];
3470
3471                         s->tx_packets    += sq_stats->packets;
3472                         s->tx_bytes      += sq_stats->bytes;
3473                         s->tx_dropped    += sq_stats->dropped;
3474                 }
3475         }
3476         if (priv->rx_ptp_opened) {
3477                 struct mlx5e_rq_stats *rq_stats = &priv->ptp_stats.rq;
3478
3479                 s->rx_packets   += rq_stats->packets;
3480                 s->rx_bytes     += rq_stats->bytes;
3481                 s->multicast    += rq_stats->mcast_packets;
3482         }
3483 }
3484
3485 void
3486 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3487 {
3488         struct mlx5e_priv *priv = netdev_priv(dev);
3489         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3490
3491         if (!netif_device_present(dev))
3492                 return;
3493
3494         /* In switchdev mode, monitor counters doesn't monitor
3495          * rx/tx stats of 802_3. The update stats mechanism
3496          * should keep the 802_3 layout counters updated
3497          */
3498         if (!mlx5e_monitor_counter_supported(priv) ||
3499             mlx5e_is_uplink_rep(priv)) {
3500                 /* update HW stats in background for next time */
3501                 mlx5e_queue_update_stats(priv);
3502         }
3503
3504         if (mlx5e_is_uplink_rep(priv)) {
3505                 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3506
3507                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3508                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3509                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3510                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3511
3512                 /* vport multicast also counts packets that are dropped due to steering
3513                  * or rx out of buffer
3514                  */
3515                 stats->multicast = VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3516         } else {
3517                 mlx5e_fold_sw_stats64(priv, stats);
3518         }
3519
3520         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3521
3522         stats->rx_length_errors =
3523                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3524                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3525                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3526         stats->rx_crc_errors =
3527                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3528         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3529         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3530         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3531                            stats->rx_frame_errors;
3532         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3533 }
3534
3535 static void mlx5e_nic_set_rx_mode(struct mlx5e_priv *priv)
3536 {
3537         if (mlx5e_is_uplink_rep(priv))
3538                 return; /* no rx mode for uplink rep */
3539
3540         queue_work(priv->wq, &priv->set_rx_mode_work);
3541 }
3542
3543 static void mlx5e_set_rx_mode(struct net_device *dev)
3544 {
3545         struct mlx5e_priv *priv = netdev_priv(dev);
3546
3547         mlx5e_nic_set_rx_mode(priv);
3548 }
3549
3550 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3551 {
3552         struct mlx5e_priv *priv = netdev_priv(netdev);
3553         struct sockaddr *saddr = addr;
3554
3555         if (!is_valid_ether_addr(saddr->sa_data))
3556                 return -EADDRNOTAVAIL;
3557
3558         netif_addr_lock_bh(netdev);
3559         eth_hw_addr_set(netdev, saddr->sa_data);
3560         netif_addr_unlock_bh(netdev);
3561
3562         mlx5e_nic_set_rx_mode(priv);
3563
3564         return 0;
3565 }
3566
3567 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3568         do {                                            \
3569                 if (enable)                             \
3570                         *features |= feature;           \
3571                 else                                    \
3572                         *features &= ~feature;          \
3573         } while (0)
3574
3575 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3576
3577 static int set_feature_lro(struct net_device *netdev, bool enable)
3578 {
3579         struct mlx5e_priv *priv = netdev_priv(netdev);
3580         struct mlx5_core_dev *mdev = priv->mdev;
3581         struct mlx5e_params *cur_params;
3582         struct mlx5e_params new_params;
3583         bool reset = true;
3584         int err = 0;
3585
3586         mutex_lock(&priv->state_lock);
3587
3588         if (enable && priv->xsk.refcnt) {
3589                 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%u XSKs are active)\n",
3590                             priv->xsk.refcnt);
3591                 err = -EINVAL;
3592                 goto out;
3593         }
3594
3595         cur_params = &priv->channels.params;
3596         if (enable && !MLX5E_GET_PFLAG(cur_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3597                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3598                 err = -EINVAL;
3599                 goto out;
3600         }
3601
3602         new_params = *cur_params;
3603
3604         if (enable)
3605                 new_params.packet_merge.type = MLX5E_PACKET_MERGE_LRO;
3606         else if (new_params.packet_merge.type == MLX5E_PACKET_MERGE_LRO)
3607                 new_params.packet_merge.type = MLX5E_PACKET_MERGE_NONE;
3608         else
3609                 goto out;
3610
3611         if (!(cur_params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO &&
3612               new_params.packet_merge.type == MLX5E_PACKET_MERGE_LRO)) {
3613                 if (cur_params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3614                         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, cur_params, NULL) ==
3615                             mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_params, NULL))
3616                                 reset = false;
3617                 }
3618         }
3619
3620         err = mlx5e_safe_switch_params(priv, &new_params,
3621                                        mlx5e_modify_tirs_packet_merge_ctx, NULL, reset);
3622 out:
3623         mutex_unlock(&priv->state_lock);
3624         return err;
3625 }
3626
3627 static int set_feature_hw_gro(struct net_device *netdev, bool enable)
3628 {
3629         struct mlx5e_priv *priv = netdev_priv(netdev);
3630         struct mlx5e_params new_params;
3631         bool reset = true;
3632         int err = 0;
3633
3634         mutex_lock(&priv->state_lock);
3635         new_params = priv->channels.params;
3636
3637         if (enable) {
3638                 new_params.packet_merge.type = MLX5E_PACKET_MERGE_SHAMPO;
3639                 new_params.packet_merge.shampo.match_criteria_type =
3640                         MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED;
3641                 new_params.packet_merge.shampo.alignment_granularity =
3642                         MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE;
3643         } else if (new_params.packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) {
3644                 new_params.packet_merge.type = MLX5E_PACKET_MERGE_NONE;
3645         } else {
3646                 goto out;
3647         }
3648
3649         err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
3650 out:
3651         mutex_unlock(&priv->state_lock);
3652         return err;
3653 }
3654
3655 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3656 {
3657         struct mlx5e_priv *priv = netdev_priv(netdev);
3658
3659         if (enable)
3660                 mlx5e_enable_cvlan_filter(priv);
3661         else
3662                 mlx5e_disable_cvlan_filter(priv);
3663
3664         return 0;
3665 }
3666
3667 static int set_feature_hw_tc(struct net_device *netdev, bool enable)
3668 {
3669         struct mlx5e_priv *priv = netdev_priv(netdev);
3670
3671 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3672         if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) {
3673                 netdev_err(netdev,
3674                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3675                 return -EINVAL;
3676         }
3677 #endif
3678
3679         if (!enable && priv->htb.maj_id) {
3680                 netdev_err(netdev, "Active HTB offload, can't turn hw_tc_offload off\n");
3681                 return -EINVAL;
3682         }
3683
3684         return 0;
3685 }
3686
3687 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3688 {
3689         struct mlx5e_priv *priv = netdev_priv(netdev);
3690         struct mlx5_core_dev *mdev = priv->mdev;
3691
3692         return mlx5_set_port_fcs(mdev, !enable);
3693 }
3694
3695 static int mlx5e_set_rx_port_ts(struct mlx5_core_dev *mdev, bool enable)
3696 {
3697         u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {};
3698         bool supported, curr_state;
3699         int err;
3700
3701         if (!MLX5_CAP_GEN(mdev, ports_check))
3702                 return 0;
3703
3704         err = mlx5_query_ports_check(mdev, in, sizeof(in));
3705         if (err)
3706                 return err;
3707
3708         supported = MLX5_GET(pcmr_reg, in, rx_ts_over_crc_cap);
3709         curr_state = MLX5_GET(pcmr_reg, in, rx_ts_over_crc);
3710
3711         if (!supported || enable == curr_state)
3712                 return 0;
3713
3714         MLX5_SET(pcmr_reg, in, local_port, 1);
3715         MLX5_SET(pcmr_reg, in, rx_ts_over_crc, enable);
3716
3717         return mlx5_set_ports_check(mdev, in, sizeof(in));
3718 }
3719
3720 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3721 {
3722         struct mlx5e_priv *priv = netdev_priv(netdev);
3723         struct mlx5e_channels *chs = &priv->channels;
3724         struct mlx5_core_dev *mdev = priv->mdev;
3725         int err;
3726
3727         mutex_lock(&priv->state_lock);
3728
3729         if (enable) {
3730                 err = mlx5e_set_rx_port_ts(mdev, false);
3731                 if (err)
3732                         goto out;
3733
3734                 chs->params.scatter_fcs_en = true;
3735                 err = mlx5e_modify_channels_scatter_fcs(chs, true);
3736                 if (err) {
3737                         chs->params.scatter_fcs_en = false;
3738                         mlx5e_set_rx_port_ts(mdev, true);
3739                 }
3740         } else {
3741                 chs->params.scatter_fcs_en = false;
3742                 err = mlx5e_modify_channels_scatter_fcs(chs, false);
3743                 if (err) {
3744                         chs->params.scatter_fcs_en = true;
3745                         goto out;
3746                 }
3747                 err = mlx5e_set_rx_port_ts(mdev, true);
3748                 if (err) {
3749                         mlx5_core_warn(mdev, "Failed to set RX port timestamp %d\n", err);
3750                         err = 0;
3751                 }
3752         }
3753
3754 out:
3755         mutex_unlock(&priv->state_lock);
3756         return err;
3757 }
3758
3759 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3760 {
3761         struct mlx5e_priv *priv = netdev_priv(netdev);
3762         int err = 0;
3763
3764         mutex_lock(&priv->state_lock);
3765
3766         priv->channels.params.vlan_strip_disable = !enable;
3767         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3768                 goto unlock;
3769
3770         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3771         if (err)
3772                 priv->channels.params.vlan_strip_disable = enable;
3773
3774 unlock:
3775         mutex_unlock(&priv->state_lock);
3776
3777         return err;
3778 }
3779
3780 #ifdef CONFIG_MLX5_EN_ARFS
3781 static int set_feature_arfs(struct net_device *netdev, bool enable)
3782 {
3783         struct mlx5e_priv *priv = netdev_priv(netdev);
3784         int err;
3785
3786         if (enable)
3787                 err = mlx5e_arfs_enable(priv);
3788         else
3789                 err = mlx5e_arfs_disable(priv);
3790
3791         return err;
3792 }
3793 #endif
3794
3795 static int mlx5e_handle_feature(struct net_device *netdev,
3796                                 netdev_features_t *features,
3797                                 netdev_features_t feature,
3798                                 mlx5e_feature_handler feature_handler)
3799 {
3800         netdev_features_t changes = *features ^ netdev->features;
3801         bool enable = !!(*features & feature);
3802         int err;
3803
3804         if (!(changes & feature))
3805                 return 0;
3806
3807         err = feature_handler(netdev, enable);
3808         if (err) {
3809                 MLX5E_SET_FEATURE(features, feature, !enable);
3810                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3811                            enable ? "Enable" : "Disable", &feature, err);
3812                 return err;
3813         }
3814
3815         return 0;
3816 }
3817
3818 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3819 {
3820         netdev_features_t oper_features = features;
3821         int err = 0;
3822
3823 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3824         mlx5e_handle_feature(netdev, &oper_features, feature, handler)
3825
3826         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3827         err |= MLX5E_HANDLE_FEATURE(NETIF_F_GRO_HW, set_feature_hw_gro);
3828         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3829                                     set_feature_cvlan_filter);
3830         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_hw_tc);
3831         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3832         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3833         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3834 #ifdef CONFIG_MLX5_EN_ARFS
3835         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3836 #endif
3837         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TLS_RX, mlx5e_ktls_set_feature_rx);
3838
3839         if (err) {
3840                 netdev->features = oper_features;
3841                 return -EINVAL;
3842         }
3843
3844         return 0;
3845 }
3846
3847 static netdev_features_t mlx5e_fix_uplink_rep_features(struct net_device *netdev,
3848                                                        netdev_features_t features)
3849 {
3850         features &= ~NETIF_F_HW_TLS_RX;
3851         if (netdev->features & NETIF_F_HW_TLS_RX)
3852                 netdev_warn(netdev, "Disabling hw_tls_rx, not supported in switchdev mode\n");
3853
3854         features &= ~NETIF_F_HW_TLS_TX;
3855         if (netdev->features & NETIF_F_HW_TLS_TX)
3856                 netdev_warn(netdev, "Disabling hw_tls_tx, not supported in switchdev mode\n");
3857
3858         features &= ~NETIF_F_NTUPLE;
3859         if (netdev->features & NETIF_F_NTUPLE)
3860                 netdev_warn(netdev, "Disabling ntuple, not supported in switchdev mode\n");
3861
3862         features &= ~NETIF_F_GRO_HW;
3863         if (netdev->features & NETIF_F_GRO_HW)
3864                 netdev_warn(netdev, "Disabling HW_GRO, not supported in switchdev mode\n");
3865
3866         return features;
3867 }
3868
3869 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3870                                             netdev_features_t features)
3871 {
3872         struct mlx5e_priv *priv = netdev_priv(netdev);
3873         struct mlx5e_params *params;
3874
3875         mutex_lock(&priv->state_lock);
3876         params = &priv->channels.params;
3877         if (!priv->fs.vlan ||
3878             !bitmap_empty(mlx5e_vlan_get_active_svlans(priv->fs.vlan), VLAN_N_VID)) {
3879                 /* HW strips the outer C-tag header, this is a problem
3880                  * for S-tag traffic.
3881                  */
3882                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3883                 if (!params->vlan_strip_disable)
3884                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3885         }
3886
3887         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3888                 if (features & NETIF_F_LRO) {
3889                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3890                         features &= ~NETIF_F_LRO;
3891                 }
3892                 if (features & NETIF_F_GRO_HW) {
3893                         netdev_warn(netdev, "Disabling HW-GRO, not supported in legacy RQ\n");
3894                         features &= ~NETIF_F_GRO_HW;
3895                 }
3896         }
3897
3898         if (params->xdp_prog) {
3899                 if (features & NETIF_F_LRO) {
3900                         netdev_warn(netdev, "LRO is incompatible with XDP\n");
3901                         features &= ~NETIF_F_LRO;
3902                 }
3903                 if (features & NETIF_F_GRO_HW) {
3904                         netdev_warn(netdev, "HW GRO is incompatible with XDP\n");
3905                         features &= ~NETIF_F_GRO_HW;
3906                 }
3907         }
3908
3909         if (priv->xsk.refcnt) {
3910                 if (features & NETIF_F_GRO_HW) {
3911                         netdev_warn(netdev, "HW GRO is incompatible with AF_XDP (%u XSKs are active)\n",
3912                                     priv->xsk.refcnt);
3913                         features &= ~NETIF_F_GRO_HW;
3914                 }
3915         }
3916
3917         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3918                 features &= ~NETIF_F_RXHASH;
3919                 if (netdev->features & NETIF_F_RXHASH)
3920                         netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3921
3922                 if (features & NETIF_F_GRO_HW) {
3923                         netdev_warn(netdev, "Disabling HW-GRO, not supported when CQE compress is active\n");
3924                         features &= ~NETIF_F_GRO_HW;
3925                 }
3926         }
3927
3928         if (mlx5e_is_uplink_rep(priv))
3929                 features = mlx5e_fix_uplink_rep_features(netdev, features);
3930
3931         mutex_unlock(&priv->state_lock);
3932
3933         return features;
3934 }
3935
3936 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3937                                    struct mlx5e_channels *chs,
3938                                    struct mlx5e_params *new_params,
3939                                    struct mlx5_core_dev *mdev)
3940 {
3941         u16 ix;
3942
3943         for (ix = 0; ix < chs->params.num_channels; ix++) {
3944                 struct xsk_buff_pool *xsk_pool =
3945                         mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, ix);
3946                 struct mlx5e_xsk_param xsk;
3947
3948                 if (!xsk_pool)
3949                         continue;
3950
3951                 mlx5e_build_xsk_param(xsk_pool, &xsk);
3952
3953                 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3954                         u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3955                         int max_mtu_frame, max_mtu_page, max_mtu;
3956
3957                         /* Two criteria must be met:
3958                          * 1. HW MTU + all headrooms <= XSK frame size.
3959                          * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
3960                          */
3961                         max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
3962                         max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
3963                         max_mtu = min(max_mtu_frame, max_mtu_page);
3964
3965                         netdev_err(netdev, "MTU %d is too big for an XSK running on channel %u. Try MTU <= %d\n",
3966                                    new_params->sw_mtu, ix, max_mtu);
3967                         return false;
3968                 }
3969         }
3970
3971         return true;
3972 }
3973
3974 static bool mlx5e_params_validate_xdp(struct net_device *netdev, struct mlx5e_params *params)
3975 {
3976         bool is_linear;
3977
3978         /* No XSK params: AF_XDP can't be enabled yet at the point of setting
3979          * the XDP program.
3980          */
3981         is_linear = mlx5e_rx_is_linear_skb(params, NULL);
3982
3983         if (!is_linear && params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3984                 netdev_warn(netdev, "XDP is not allowed with striding RQ and MTU(%d) > %d\n",
3985                             params->sw_mtu,
3986                             mlx5e_xdp_max_mtu(params, NULL));
3987                 return false;
3988         }
3989         if (!is_linear && !params->xdp_prog->aux->xdp_has_frags) {
3990                 netdev_warn(netdev, "MTU(%d) > %d, too big for an XDP program not aware of multi buffer\n",
3991                             params->sw_mtu,
3992                             mlx5e_xdp_max_mtu(params, NULL));
3993                 return false;
3994         }
3995
3996         return true;
3997 }
3998
3999 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
4000                      mlx5e_fp_preactivate preactivate)
4001 {
4002         struct mlx5e_priv *priv = netdev_priv(netdev);
4003         struct mlx5e_params new_params;
4004         struct mlx5e_params *params;
4005         bool reset = true;
4006         int err = 0;
4007
4008         mutex_lock(&priv->state_lock);
4009
4010         params = &priv->channels.params;
4011
4012         new_params = *params;
4013         new_params.sw_mtu = new_mtu;
4014         err = mlx5e_validate_params(priv->mdev, &new_params);
4015         if (err)
4016                 goto out;
4017
4018         if (new_params.xdp_prog && !mlx5e_params_validate_xdp(netdev, &new_params)) {
4019                 err = -EINVAL;
4020                 goto out;
4021         }
4022
4023         if (priv->xsk.refcnt &&
4024             !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
4025                                     &new_params, priv->mdev)) {
4026                 err = -EINVAL;
4027                 goto out;
4028         }
4029
4030         if (params->packet_merge.type == MLX5E_PACKET_MERGE_LRO)
4031                 reset = false;
4032
4033         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4034                 bool is_linear_old = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, params, NULL);
4035                 bool is_linear_new = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
4036                                                                   &new_params, NULL);
4037                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
4038                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_params, NULL);
4039
4040                 /* Always reset in linear mode - hw_mtu is used in data path.
4041                  * Check that the mode was non-linear and didn't change.
4042                  * If XSK is active, XSK RQs are linear.
4043                  */
4044                 if (!is_linear_old && !is_linear_new && !priv->xsk.refcnt &&
4045                     ppw_old == ppw_new)
4046                         reset = false;
4047         }
4048
4049         err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, reset);
4050
4051 out:
4052         netdev->mtu = params->sw_mtu;
4053         mutex_unlock(&priv->state_lock);
4054         return err;
4055 }
4056
4057 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
4058 {
4059         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx);
4060 }
4061
4062 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx)
4063 {
4064         bool set  = *(bool *)ctx;
4065
4066         return mlx5e_ptp_rx_manage_fs(priv, set);
4067 }
4068
4069 static int mlx5e_hwstamp_config_no_ptp_rx(struct mlx5e_priv *priv, bool rx_filter)
4070 {
4071         bool rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
4072         int err;
4073
4074         if (!rx_filter)
4075                 /* Reset CQE compression to Admin default */
4076                 return mlx5e_modify_rx_cqe_compression_locked(priv, rx_cqe_compress_def, false);
4077
4078         if (!MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4079                 return 0;
4080
4081         /* Disable CQE compression */
4082         netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
4083         err = mlx5e_modify_rx_cqe_compression_locked(priv, false, true);
4084         if (err)
4085                 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
4086
4087         return err;
4088 }
4089
4090 static int mlx5e_hwstamp_config_ptp_rx(struct mlx5e_priv *priv, bool ptp_rx)
4091 {
4092         struct mlx5e_params new_params;
4093
4094         if (ptp_rx == priv->channels.params.ptp_rx)
4095                 return 0;
4096
4097         new_params = priv->channels.params;
4098         new_params.ptp_rx = ptp_rx;
4099         return mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx,
4100                                         &new_params.ptp_rx, true);
4101 }
4102
4103 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
4104 {
4105         struct hwtstamp_config config;
4106         bool rx_cqe_compress_def;
4107         bool ptp_rx;
4108         int err;
4109
4110         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
4111             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
4112                 return -EOPNOTSUPP;
4113
4114         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4115                 return -EFAULT;
4116
4117         /* TX HW timestamp */
4118         switch (config.tx_type) {
4119         case HWTSTAMP_TX_OFF:
4120         case HWTSTAMP_TX_ON:
4121                 break;
4122         default:
4123                 return -ERANGE;
4124         }
4125
4126         mutex_lock(&priv->state_lock);
4127         rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
4128
4129         /* RX HW timestamp */
4130         switch (config.rx_filter) {
4131         case HWTSTAMP_FILTER_NONE:
4132                 ptp_rx = false;
4133                 break;
4134         case HWTSTAMP_FILTER_ALL:
4135         case HWTSTAMP_FILTER_SOME:
4136         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4137         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4138         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4139         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4140         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4141         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4142         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4143         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4144         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4145         case HWTSTAMP_FILTER_PTP_V2_EVENT:
4146         case HWTSTAMP_FILTER_PTP_V2_SYNC:
4147         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4148         case HWTSTAMP_FILTER_NTP_ALL:
4149                 config.rx_filter = HWTSTAMP_FILTER_ALL;
4150                 /* ptp_rx is set if both HW TS is set and CQE
4151                  * compression is set
4152                  */
4153                 ptp_rx = rx_cqe_compress_def;
4154                 break;
4155         default:
4156                 err = -ERANGE;
4157                 goto err_unlock;
4158         }
4159
4160         if (!mlx5e_profile_feature_cap(priv->profile, PTP_RX))
4161                 err = mlx5e_hwstamp_config_no_ptp_rx(priv,
4162                                                      config.rx_filter != HWTSTAMP_FILTER_NONE);
4163         else
4164                 err = mlx5e_hwstamp_config_ptp_rx(priv, ptp_rx);
4165         if (err)
4166                 goto err_unlock;
4167
4168         memcpy(&priv->tstamp, &config, sizeof(config));
4169         mutex_unlock(&priv->state_lock);
4170
4171         /* might need to fix some features */
4172         netdev_update_features(priv->netdev);
4173
4174         return copy_to_user(ifr->ifr_data, &config,
4175                             sizeof(config)) ? -EFAULT : 0;
4176 err_unlock:
4177         mutex_unlock(&priv->state_lock);
4178         return err;
4179 }
4180
4181 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
4182 {
4183         struct hwtstamp_config *cfg = &priv->tstamp;
4184
4185         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4186                 return -EOPNOTSUPP;
4187
4188         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
4189 }
4190
4191 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4192 {
4193         struct mlx5e_priv *priv = netdev_priv(dev);
4194
4195         switch (cmd) {
4196         case SIOCSHWTSTAMP:
4197                 return mlx5e_hwstamp_set(priv, ifr);
4198         case SIOCGHWTSTAMP:
4199                 return mlx5e_hwstamp_get(priv, ifr);
4200         default:
4201                 return -EOPNOTSUPP;
4202         }
4203 }
4204
4205 #ifdef CONFIG_MLX5_ESWITCH
4206 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4207 {
4208         struct mlx5e_priv *priv = netdev_priv(dev);
4209         struct mlx5_core_dev *mdev = priv->mdev;
4210
4211         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4212 }
4213
4214 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4215                              __be16 vlan_proto)
4216 {
4217         struct mlx5e_priv *priv = netdev_priv(dev);
4218         struct mlx5_core_dev *mdev = priv->mdev;
4219
4220         if (vlan_proto != htons(ETH_P_8021Q))
4221                 return -EPROTONOSUPPORT;
4222
4223         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4224                                            vlan, qos);
4225 }
4226
4227 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4228 {
4229         struct mlx5e_priv *priv = netdev_priv(dev);
4230         struct mlx5_core_dev *mdev = priv->mdev;
4231
4232         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4233 }
4234
4235 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4236 {
4237         struct mlx5e_priv *priv = netdev_priv(dev);
4238         struct mlx5_core_dev *mdev = priv->mdev;
4239
4240         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4241 }
4242
4243 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4244                       int max_tx_rate)
4245 {
4246         struct mlx5e_priv *priv = netdev_priv(dev);
4247         struct mlx5_core_dev *mdev = priv->mdev;
4248
4249         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4250                                            max_tx_rate, min_tx_rate);
4251 }
4252
4253 static int mlx5_vport_link2ifla(u8 esw_link)
4254 {
4255         switch (esw_link) {
4256         case MLX5_VPORT_ADMIN_STATE_DOWN:
4257                 return IFLA_VF_LINK_STATE_DISABLE;
4258         case MLX5_VPORT_ADMIN_STATE_UP:
4259                 return IFLA_VF_LINK_STATE_ENABLE;
4260         }
4261         return IFLA_VF_LINK_STATE_AUTO;
4262 }
4263
4264 static int mlx5_ifla_link2vport(u8 ifla_link)
4265 {
4266         switch (ifla_link) {
4267         case IFLA_VF_LINK_STATE_DISABLE:
4268                 return MLX5_VPORT_ADMIN_STATE_DOWN;
4269         case IFLA_VF_LINK_STATE_ENABLE:
4270                 return MLX5_VPORT_ADMIN_STATE_UP;
4271         }
4272         return MLX5_VPORT_ADMIN_STATE_AUTO;
4273 }
4274
4275 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4276                                    int link_state)
4277 {
4278         struct mlx5e_priv *priv = netdev_priv(dev);
4279         struct mlx5_core_dev *mdev = priv->mdev;
4280
4281         if (mlx5e_is_uplink_rep(priv))
4282                 return -EOPNOTSUPP;
4283
4284         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4285                                             mlx5_ifla_link2vport(link_state));
4286 }
4287
4288 int mlx5e_get_vf_config(struct net_device *dev,
4289                         int vf, struct ifla_vf_info *ivi)
4290 {
4291         struct mlx5e_priv *priv = netdev_priv(dev);
4292         struct mlx5_core_dev *mdev = priv->mdev;
4293         int err;
4294
4295         if (!netif_device_present(dev))
4296                 return -EOPNOTSUPP;
4297
4298         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4299         if (err)
4300                 return err;
4301         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4302         return 0;
4303 }
4304
4305 int mlx5e_get_vf_stats(struct net_device *dev,
4306                        int vf, struct ifla_vf_stats *vf_stats)
4307 {
4308         struct mlx5e_priv *priv = netdev_priv(dev);
4309         struct mlx5_core_dev *mdev = priv->mdev;
4310
4311         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4312                                             vf_stats);
4313 }
4314
4315 static bool
4316 mlx5e_has_offload_stats(const struct net_device *dev, int attr_id)
4317 {
4318         struct mlx5e_priv *priv = netdev_priv(dev);
4319
4320         if (!netif_device_present(dev))
4321                 return false;
4322
4323         if (!mlx5e_is_uplink_rep(priv))
4324                 return false;
4325
4326         return mlx5e_rep_has_offload_stats(dev, attr_id);
4327 }
4328
4329 static int
4330 mlx5e_get_offload_stats(int attr_id, const struct net_device *dev,
4331                         void *sp)
4332 {
4333         struct mlx5e_priv *priv = netdev_priv(dev);
4334
4335         if (!mlx5e_is_uplink_rep(priv))
4336                 return -EOPNOTSUPP;
4337
4338         return mlx5e_rep_get_offload_stats(attr_id, dev, sp);
4339 }
4340 #endif
4341
4342 static bool mlx5e_tunnel_proto_supported_tx(struct mlx5_core_dev *mdev, u8 proto_type)
4343 {
4344         switch (proto_type) {
4345         case IPPROTO_GRE:
4346                 return MLX5_CAP_ETH(mdev, tunnel_stateless_gre);
4347         case IPPROTO_IPIP:
4348         case IPPROTO_IPV6:
4349                 return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) ||
4350                         MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_tx));
4351         default:
4352                 return false;
4353         }
4354 }
4355
4356 static bool mlx5e_gre_tunnel_inner_proto_offload_supported(struct mlx5_core_dev *mdev,
4357                                                            struct sk_buff *skb)
4358 {
4359         switch (skb->inner_protocol) {
4360         case htons(ETH_P_IP):
4361         case htons(ETH_P_IPV6):
4362         case htons(ETH_P_TEB):
4363                 return true;
4364         case htons(ETH_P_MPLS_UC):
4365         case htons(ETH_P_MPLS_MC):
4366                 return MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre);
4367         }
4368         return false;
4369 }
4370
4371 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4372                                                      struct sk_buff *skb,
4373                                                      netdev_features_t features)
4374 {
4375         unsigned int offset = 0;
4376         struct udphdr *udph;
4377         u8 proto;
4378         u16 port;
4379
4380         switch (vlan_get_protocol(skb)) {
4381         case htons(ETH_P_IP):
4382                 proto = ip_hdr(skb)->protocol;
4383                 break;
4384         case htons(ETH_P_IPV6):
4385                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4386                 break;
4387         default:
4388                 goto out;
4389         }
4390
4391         switch (proto) {
4392         case IPPROTO_GRE:
4393                 if (mlx5e_gre_tunnel_inner_proto_offload_supported(priv->mdev, skb))
4394                         return features;
4395                 break;
4396         case IPPROTO_IPIP:
4397         case IPPROTO_IPV6:
4398                 if (mlx5e_tunnel_proto_supported_tx(priv->mdev, IPPROTO_IPIP))
4399                         return features;
4400                 break;
4401         case IPPROTO_UDP:
4402                 udph = udp_hdr(skb);
4403                 port = be16_to_cpu(udph->dest);
4404
4405                 /* Verify if UDP port is being offloaded by HW */
4406                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4407                         return features;
4408
4409 #if IS_ENABLED(CONFIG_GENEVE)
4410                 /* Support Geneve offload for default UDP port */
4411                 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4412                         return features;
4413 #endif
4414                 break;
4415 #ifdef CONFIG_MLX5_EN_IPSEC
4416         case IPPROTO_ESP:
4417                 return mlx5e_ipsec_feature_check(skb, features);
4418 #endif
4419         }
4420
4421 out:
4422         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4423         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4424 }
4425
4426 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4427                                        struct net_device *netdev,
4428                                        netdev_features_t features)
4429 {
4430         struct mlx5e_priv *priv = netdev_priv(netdev);
4431
4432         features = vlan_features_check(skb, features);
4433         features = vxlan_features_check(skb, features);
4434
4435         /* Validate if the tunneled packet is being offloaded by HW */
4436         if (skb->encapsulation &&
4437             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4438                 return mlx5e_tunnel_features_check(priv, skb, features);
4439
4440         return features;
4441 }
4442
4443 static void mlx5e_tx_timeout_work(struct work_struct *work)
4444 {
4445         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4446                                                tx_timeout_work);
4447         struct net_device *netdev = priv->netdev;
4448         int i;
4449
4450         rtnl_lock();
4451         mutex_lock(&priv->state_lock);
4452
4453         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4454                 goto unlock;
4455
4456         for (i = 0; i < netdev->real_num_tx_queues; i++) {
4457                 struct netdev_queue *dev_queue =
4458                         netdev_get_tx_queue(netdev, i);
4459                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4460
4461                 if (!netif_xmit_stopped(dev_queue))
4462                         continue;
4463
4464                 if (mlx5e_reporter_tx_timeout(sq))
4465                 /* break if tried to reopened channels */
4466                         break;
4467         }
4468
4469 unlock:
4470         mutex_unlock(&priv->state_lock);
4471         rtnl_unlock();
4472 }
4473
4474 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue)
4475 {
4476         struct mlx5e_priv *priv = netdev_priv(dev);
4477
4478         netdev_err(dev, "TX timeout detected\n");
4479         queue_work(priv->wq, &priv->tx_timeout_work);
4480 }
4481
4482 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4483 {
4484         struct net_device *netdev = priv->netdev;
4485         struct mlx5e_params new_params;
4486
4487         if (priv->channels.params.packet_merge.type != MLX5E_PACKET_MERGE_NONE) {
4488                 netdev_warn(netdev, "can't set XDP while HW-GRO/LRO is on, disable them first\n");
4489                 return -EINVAL;
4490         }
4491
4492         new_params = priv->channels.params;
4493         new_params.xdp_prog = prog;
4494
4495         if (!mlx5e_params_validate_xdp(netdev, &new_params))
4496                 return -EINVAL;
4497
4498         return 0;
4499 }
4500
4501 static void mlx5e_rq_replace_xdp_prog(struct mlx5e_rq *rq, struct bpf_prog *prog)
4502 {
4503         struct bpf_prog *old_prog;
4504
4505         old_prog = rcu_replace_pointer(rq->xdp_prog, prog,
4506                                        lockdep_is_held(&rq->priv->state_lock));
4507         if (old_prog)
4508                 bpf_prog_put(old_prog);
4509 }
4510
4511 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4512 {
4513         struct mlx5e_priv *priv = netdev_priv(netdev);
4514         struct mlx5e_params new_params;
4515         struct bpf_prog *old_prog;
4516         int err = 0;
4517         bool reset;
4518         int i;
4519
4520         mutex_lock(&priv->state_lock);
4521
4522         if (prog) {
4523                 err = mlx5e_xdp_allowed(priv, prog);
4524                 if (err)
4525                         goto unlock;
4526         }
4527
4528         /* no need for full reset when exchanging programs */
4529         reset = (!priv->channels.params.xdp_prog || !prog);
4530
4531         new_params = priv->channels.params;
4532         new_params.xdp_prog = prog;
4533         if (reset)
4534                 mlx5e_set_rq_type(priv->mdev, &new_params);
4535         old_prog = priv->channels.params.xdp_prog;
4536
4537         err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
4538         if (err)
4539                 goto unlock;
4540
4541         if (old_prog)
4542                 bpf_prog_put(old_prog);
4543
4544         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4545                 goto unlock;
4546
4547         /* exchanging programs w/o reset, we update ref counts on behalf
4548          * of the channels RQs here.
4549          */
4550         bpf_prog_add(prog, priv->channels.num);
4551         for (i = 0; i < priv->channels.num; i++) {
4552                 struct mlx5e_channel *c = priv->channels.c[i];
4553
4554                 mlx5e_rq_replace_xdp_prog(&c->rq, prog);
4555                 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) {
4556                         bpf_prog_inc(prog);
4557                         mlx5e_rq_replace_xdp_prog(&c->xskrq, prog);
4558                 }
4559         }
4560
4561 unlock:
4562         mutex_unlock(&priv->state_lock);
4563         return err;
4564 }
4565
4566 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4567 {
4568         switch (xdp->command) {
4569         case XDP_SETUP_PROG:
4570                 return mlx5e_xdp_set(dev, xdp->prog);
4571         case XDP_SETUP_XSK_POOL:
4572                 return mlx5e_xsk_setup_pool(dev, xdp->xsk.pool,
4573                                             xdp->xsk.queue_id);
4574         default:
4575                 return -EINVAL;
4576         }
4577 }
4578
4579 #ifdef CONFIG_MLX5_ESWITCH
4580 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4581                                 struct net_device *dev, u32 filter_mask,
4582                                 int nlflags)
4583 {
4584         struct mlx5e_priv *priv = netdev_priv(dev);
4585         struct mlx5_core_dev *mdev = priv->mdev;
4586         u8 mode, setting;
4587         int err;
4588
4589         err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4590         if (err)
4591                 return err;
4592         mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4593         return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4594                                        mode,
4595                                        0, 0, nlflags, filter_mask, NULL);
4596 }
4597
4598 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4599                                 u16 flags, struct netlink_ext_ack *extack)
4600 {
4601         struct mlx5e_priv *priv = netdev_priv(dev);
4602         struct mlx5_core_dev *mdev = priv->mdev;
4603         struct nlattr *attr, *br_spec;
4604         u16 mode = BRIDGE_MODE_UNDEF;
4605         u8 setting;
4606         int rem;
4607
4608         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4609         if (!br_spec)
4610                 return -EINVAL;
4611
4612         nla_for_each_nested(attr, br_spec, rem) {
4613                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4614                         continue;
4615
4616                 if (nla_len(attr) < sizeof(mode))
4617                         return -EINVAL;
4618
4619                 mode = nla_get_u16(attr);
4620                 if (mode > BRIDGE_MODE_VEPA)
4621                         return -EINVAL;
4622
4623                 break;
4624         }
4625
4626         if (mode == BRIDGE_MODE_UNDEF)
4627                 return -EINVAL;
4628
4629         setting = (mode == BRIDGE_MODE_VEPA) ?  1 : 0;
4630         return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4631 }
4632 #endif
4633
4634 const struct net_device_ops mlx5e_netdev_ops = {
4635         .ndo_open                = mlx5e_open,
4636         .ndo_stop                = mlx5e_close,
4637         .ndo_start_xmit          = mlx5e_xmit,
4638         .ndo_setup_tc            = mlx5e_setup_tc,
4639         .ndo_select_queue        = mlx5e_select_queue,
4640         .ndo_get_stats64         = mlx5e_get_stats,
4641         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4642         .ndo_set_mac_address     = mlx5e_set_mac,
4643         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4644         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4645         .ndo_set_features        = mlx5e_set_features,
4646         .ndo_fix_features        = mlx5e_fix_features,
4647         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4648         .ndo_eth_ioctl            = mlx5e_ioctl,
4649         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4650         .ndo_features_check      = mlx5e_features_check,
4651         .ndo_tx_timeout          = mlx5e_tx_timeout,
4652         .ndo_bpf                 = mlx5e_xdp,
4653         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4654         .ndo_xsk_wakeup          = mlx5e_xsk_wakeup,
4655 #ifdef CONFIG_MLX5_EN_ARFS
4656         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4657 #endif
4658 #ifdef CONFIG_MLX5_ESWITCH
4659         .ndo_bridge_setlink      = mlx5e_bridge_setlink,
4660         .ndo_bridge_getlink      = mlx5e_bridge_getlink,
4661
4662         /* SRIOV E-Switch NDOs */
4663         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4664         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4665         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4666         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4667         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4668         .ndo_get_vf_config       = mlx5e_get_vf_config,
4669         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4670         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4671         .ndo_has_offload_stats   = mlx5e_has_offload_stats,
4672         .ndo_get_offload_stats   = mlx5e_get_offload_stats,
4673 #endif
4674         .ndo_get_devlink_port    = mlx5e_get_devlink_port,
4675 };
4676
4677 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4678 {
4679         int i;
4680
4681         /* The supported periods are organized in ascending order */
4682         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4683                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4684                         break;
4685
4686         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4687 }
4688
4689 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu)
4690 {
4691         struct mlx5e_params *params = &priv->channels.params;
4692         struct mlx5_core_dev *mdev = priv->mdev;
4693         u8 rx_cq_period_mode;
4694
4695         params->sw_mtu = mtu;
4696         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4697         params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2,
4698                                      priv->max_nch);
4699         mlx5e_params_mqprio_reset(params);
4700
4701         /* SQ */
4702         params->log_sq_size = is_kdump_kernel() ?
4703                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4704                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4705         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
4706
4707         /* XDP SQ */
4708         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
4709
4710         /* set CQE compression */
4711         params->rx_cqe_compress_def = false;
4712         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4713             MLX5_CAP_GEN(mdev, vport_group_manager))
4714                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4715
4716         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4717         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4718
4719         /* RQ */
4720         mlx5e_build_rq_params(mdev, params);
4721
4722         /* HW LRO */
4723         if (MLX5_CAP_ETH(mdev, lro_cap) &&
4724             params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4725                 /* No XSK params: checking the availability of striding RQ in general. */
4726                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4727                         params->packet_merge.type = slow_pci_heuristic(mdev) ?
4728                                 MLX5E_PACKET_MERGE_NONE : MLX5E_PACKET_MERGE_LRO;
4729         }
4730         params->packet_merge.timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4731
4732         /* CQ moderation params */
4733         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4734                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4735                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4736         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4737         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4738         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4739         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4740
4741         /* TX inline */
4742         mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
4743
4744         params->tunneled_offload_en = mlx5_tunnel_inner_ft_supported(mdev);
4745
4746         /* AF_XDP */
4747         params->xsk = xsk;
4748
4749         /* Do not update netdev->features directly in here
4750          * on mlx5e_attach_netdev() we will call mlx5e_update_features()
4751          * To update netdev->features please modify mlx5e_fix_features()
4752          */
4753 }
4754
4755 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4756 {
4757         struct mlx5e_priv *priv = netdev_priv(netdev);
4758         u8 addr[ETH_ALEN];
4759
4760         mlx5_query_mac_address(priv->mdev, addr);
4761         if (is_zero_ether_addr(addr) &&
4762             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4763                 eth_hw_addr_random(netdev);
4764                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4765                 return;
4766         }
4767
4768         eth_hw_addr_set(netdev, addr);
4769 }
4770
4771 static int mlx5e_vxlan_set_port(struct net_device *netdev, unsigned int table,
4772                                 unsigned int entry, struct udp_tunnel_info *ti)
4773 {
4774         struct mlx5e_priv *priv = netdev_priv(netdev);
4775
4776         return mlx5_vxlan_add_port(priv->mdev->vxlan, ntohs(ti->port));
4777 }
4778
4779 static int mlx5e_vxlan_unset_port(struct net_device *netdev, unsigned int table,
4780                                   unsigned int entry, struct udp_tunnel_info *ti)
4781 {
4782         struct mlx5e_priv *priv = netdev_priv(netdev);
4783
4784         return mlx5_vxlan_del_port(priv->mdev->vxlan, ntohs(ti->port));
4785 }
4786
4787 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv)
4788 {
4789         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4790                 return;
4791
4792         priv->nic_info.set_port = mlx5e_vxlan_set_port;
4793         priv->nic_info.unset_port = mlx5e_vxlan_unset_port;
4794         priv->nic_info.flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
4795                                 UDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN;
4796         priv->nic_info.tables[0].tunnel_types = UDP_TUNNEL_TYPE_VXLAN;
4797         /* Don't count the space hard-coded to the IANA port */
4798         priv->nic_info.tables[0].n_entries =
4799                 mlx5_vxlan_max_udp_ports(priv->mdev) - 1;
4800
4801         priv->netdev->udp_tunnel_nic_info = &priv->nic_info;
4802 }
4803
4804 static bool mlx5e_tunnel_any_tx_proto_supported(struct mlx5_core_dev *mdev)
4805 {
4806         int tt;
4807
4808         for (tt = 0; tt < MLX5_NUM_TUNNEL_TT; tt++) {
4809                 if (mlx5e_tunnel_proto_supported_tx(mdev, mlx5_get_proto_by_tunnel_type(tt)))
4810                         return true;
4811         }
4812         return (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev));
4813 }
4814
4815 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4816 {
4817         struct mlx5e_priv *priv = netdev_priv(netdev);
4818         struct mlx5_core_dev *mdev = priv->mdev;
4819         bool fcs_supported;
4820         bool fcs_enabled;
4821
4822         SET_NETDEV_DEV(netdev, mdev->device);
4823
4824         netdev->netdev_ops = &mlx5e_netdev_ops;
4825
4826         mlx5e_dcbnl_build_netdev(netdev);
4827
4828         netdev->watchdog_timeo    = 15 * HZ;
4829
4830         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4831
4832         netdev->vlan_features    |= NETIF_F_SG;
4833         netdev->vlan_features    |= NETIF_F_HW_CSUM;
4834         netdev->vlan_features    |= NETIF_F_GRO;
4835         netdev->vlan_features    |= NETIF_F_TSO;
4836         netdev->vlan_features    |= NETIF_F_TSO6;
4837         netdev->vlan_features    |= NETIF_F_RXCSUM;
4838         netdev->vlan_features    |= NETIF_F_RXHASH;
4839
4840         netdev->mpls_features    |= NETIF_F_SG;
4841         netdev->mpls_features    |= NETIF_F_HW_CSUM;
4842         netdev->mpls_features    |= NETIF_F_TSO;
4843         netdev->mpls_features    |= NETIF_F_TSO6;
4844
4845         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4846         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4847
4848         /* Tunneled LRO is not supported in the driver, and the same RQs are
4849          * shared between inner and outer TIRs, so the driver can't disable LRO
4850          * for inner TIRs while having it enabled for outer TIRs. Due to this,
4851          * block LRO altogether if the firmware declares tunneled LRO support.
4852          */
4853         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4854             !MLX5_CAP_ETH(mdev, tunnel_lro_vxlan) &&
4855             !MLX5_CAP_ETH(mdev, tunnel_lro_gre) &&
4856             mlx5e_check_fragmented_striding_rq_cap(mdev))
4857                 netdev->vlan_features    |= NETIF_F_LRO;
4858
4859         netdev->hw_features       = netdev->vlan_features;
4860         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4861         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4862         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4863         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4864
4865         if (mlx5e_tunnel_any_tx_proto_supported(mdev)) {
4866                 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4867                 netdev->hw_enc_features |= NETIF_F_TSO;
4868                 netdev->hw_enc_features |= NETIF_F_TSO6;
4869                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4870         }
4871
4872         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4873                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4874                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4875                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4876                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4877                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4878                 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL |
4879                                          NETIF_F_GSO_UDP_TUNNEL_CSUM;
4880         }
4881
4882         if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_GRE)) {
4883                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4884                                            NETIF_F_GSO_GRE_CSUM;
4885                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4886                                            NETIF_F_GSO_GRE_CSUM;
4887                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4888                                                 NETIF_F_GSO_GRE_CSUM;
4889         }
4890
4891         if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_IPIP)) {
4892                 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
4893                                        NETIF_F_GSO_IPXIP6;
4894                 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
4895                                            NETIF_F_GSO_IPXIP6;
4896                 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
4897                                                 NETIF_F_GSO_IPXIP6;
4898         }
4899
4900         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4901         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4902         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4903         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4904
4905         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4906
4907         if (fcs_supported)
4908                 netdev->hw_features |= NETIF_F_RXALL;
4909
4910         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4911                 netdev->hw_features |= NETIF_F_RXFCS;
4912
4913         if (mlx5_qos_is_supported(mdev))
4914                 netdev->hw_features |= NETIF_F_HW_TC;
4915
4916         netdev->features          = netdev->hw_features;
4917
4918         /* Defaults */
4919         if (fcs_enabled)
4920                 netdev->features  &= ~NETIF_F_RXALL;
4921         netdev->features  &= ~NETIF_F_LRO;
4922         netdev->features  &= ~NETIF_F_GRO_HW;
4923         netdev->features  &= ~NETIF_F_RXFCS;
4924
4925 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4926         if (FT_CAP(flow_modify_en) &&
4927             FT_CAP(modify_root) &&
4928             FT_CAP(identified_miss_table_mode) &&
4929             FT_CAP(flow_table_modify)) {
4930 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
4931                 netdev->hw_features      |= NETIF_F_HW_TC;
4932 #endif
4933 #ifdef CONFIG_MLX5_EN_ARFS
4934                 netdev->hw_features      |= NETIF_F_NTUPLE;
4935 #endif
4936         }
4937
4938         netdev->features         |= NETIF_F_HIGHDMA;
4939         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4940
4941         netdev->priv_flags       |= IFF_UNICAST_FLT;
4942
4943         mlx5e_set_netdev_dev_addr(netdev);
4944         mlx5e_ipsec_build_netdev(priv);
4945         mlx5e_ktls_build_netdev(priv);
4946 }
4947
4948 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4949 {
4950         u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {};
4951         u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {};
4952         struct mlx5_core_dev *mdev = priv->mdev;
4953         int err;
4954
4955         MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
4956         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4957         if (!err)
4958                 priv->q_counter =
4959                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4960
4961         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4962         if (!err)
4963                 priv->drop_rq_q_counter =
4964                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4965 }
4966
4967 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4968 {
4969         u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {};
4970
4971         MLX5_SET(dealloc_q_counter_in, in, opcode,
4972                  MLX5_CMD_OP_DEALLOC_Q_COUNTER);
4973         if (priv->q_counter) {
4974                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4975                          priv->q_counter);
4976                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4977         }
4978
4979         if (priv->drop_rq_q_counter) {
4980                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4981                          priv->drop_rq_q_counter);
4982                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4983         }
4984 }
4985
4986 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4987                           struct net_device *netdev)
4988 {
4989         struct mlx5e_priv *priv = netdev_priv(netdev);
4990         int err;
4991
4992         mlx5e_build_nic_params(priv, &priv->xsk, netdev->mtu);
4993         mlx5e_vxlan_set_netdev_info(priv);
4994
4995         mlx5e_timestamp_init(priv);
4996
4997         err = mlx5e_fs_init(priv);
4998         if (err) {
4999                 mlx5_core_err(mdev, "FS initialization failed, %d\n", err);
5000                 return err;
5001         }
5002
5003         err = mlx5e_ipsec_init(priv);
5004         if (err)
5005                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
5006
5007         err = mlx5e_ktls_init(priv);
5008         if (err)
5009                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
5010
5011         mlx5e_health_create_reporters(priv);
5012         return 0;
5013 }
5014
5015 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
5016 {
5017         mlx5e_health_destroy_reporters(priv);
5018         mlx5e_ktls_cleanup(priv);
5019         mlx5e_ipsec_cleanup(priv);
5020         mlx5e_fs_cleanup(priv);
5021 }
5022
5023 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
5024 {
5025         struct mlx5_core_dev *mdev = priv->mdev;
5026         enum mlx5e_rx_res_features features;
5027         int err;
5028
5029         priv->rx_res = mlx5e_rx_res_alloc();
5030         if (!priv->rx_res)
5031                 return -ENOMEM;
5032
5033         mlx5e_create_q_counters(priv);
5034
5035         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
5036         if (err) {
5037                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
5038                 goto err_destroy_q_counters;
5039         }
5040
5041         features = MLX5E_RX_RES_FEATURE_XSK | MLX5E_RX_RES_FEATURE_PTP;
5042         if (priv->channels.params.tunneled_offload_en)
5043                 features |= MLX5E_RX_RES_FEATURE_INNER_FT;
5044         err = mlx5e_rx_res_init(priv->rx_res, priv->mdev, features,
5045                                 priv->max_nch, priv->drop_rq.rqn,
5046                                 &priv->channels.params.packet_merge,
5047                                 priv->channels.params.num_channels);
5048         if (err)
5049                 goto err_close_drop_rq;
5050
5051         err = mlx5e_create_flow_steering(priv);
5052         if (err) {
5053                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
5054                 goto err_destroy_rx_res;
5055         }
5056
5057         err = mlx5e_tc_nic_init(priv);
5058         if (err)
5059                 goto err_destroy_flow_steering;
5060
5061         err = mlx5e_accel_init_rx(priv);
5062         if (err)
5063                 goto err_tc_nic_cleanup;
5064
5065 #ifdef CONFIG_MLX5_EN_ARFS
5066         priv->netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(priv->mdev);
5067 #endif
5068
5069         return 0;
5070
5071 err_tc_nic_cleanup:
5072         mlx5e_tc_nic_cleanup(priv);
5073 err_destroy_flow_steering:
5074         mlx5e_destroy_flow_steering(priv);
5075 err_destroy_rx_res:
5076         mlx5e_rx_res_destroy(priv->rx_res);
5077 err_close_drop_rq:
5078         mlx5e_close_drop_rq(&priv->drop_rq);
5079 err_destroy_q_counters:
5080         mlx5e_destroy_q_counters(priv);
5081         mlx5e_rx_res_free(priv->rx_res);
5082         priv->rx_res = NULL;
5083         return err;
5084 }
5085
5086 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5087 {
5088         mlx5e_accel_cleanup_rx(priv);
5089         mlx5e_tc_nic_cleanup(priv);
5090         mlx5e_destroy_flow_steering(priv);
5091         mlx5e_rx_res_destroy(priv->rx_res);
5092         mlx5e_close_drop_rq(&priv->drop_rq);
5093         mlx5e_destroy_q_counters(priv);
5094         mlx5e_rx_res_free(priv->rx_res);
5095         priv->rx_res = NULL;
5096 }
5097
5098 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5099 {
5100         int err;
5101
5102         err = mlx5e_create_tises(priv);
5103         if (err) {
5104                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5105                 return err;
5106         }
5107
5108         mlx5e_dcbnl_initialize(priv);
5109         return 0;
5110 }
5111
5112 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5113 {
5114         struct net_device *netdev = priv->netdev;
5115         struct mlx5_core_dev *mdev = priv->mdev;
5116
5117         mlx5e_init_l2_addr(priv);
5118
5119         /* Marking the link as currently not needed by the Driver */
5120         if (!netif_running(netdev))
5121                 mlx5e_modify_admin_state(mdev, MLX5_PORT_DOWN);
5122
5123         mlx5e_set_netdev_mtu_boundaries(priv);
5124         mlx5e_set_dev_port_mtu(priv);
5125
5126         mlx5_lag_add_netdev(mdev, netdev);
5127
5128         mlx5e_enable_async_events(priv);
5129         mlx5e_enable_blocking_events(priv);
5130         if (mlx5e_monitor_counter_supported(priv))
5131                 mlx5e_monitor_counter_init(priv);
5132
5133         mlx5e_hv_vhca_stats_create(priv);
5134         if (netdev->reg_state != NETREG_REGISTERED)
5135                 return;
5136         mlx5e_dcbnl_init_app(priv);
5137
5138         mlx5e_nic_set_rx_mode(priv);
5139
5140         rtnl_lock();
5141         if (netif_running(netdev))
5142                 mlx5e_open(netdev);
5143         udp_tunnel_nic_reset_ntf(priv->netdev);
5144         netif_device_attach(netdev);
5145         rtnl_unlock();
5146 }
5147
5148 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5149 {
5150         struct mlx5_core_dev *mdev = priv->mdev;
5151
5152         if (priv->netdev->reg_state == NETREG_REGISTERED)
5153                 mlx5e_dcbnl_delete_app(priv);
5154
5155         rtnl_lock();
5156         if (netif_running(priv->netdev))
5157                 mlx5e_close(priv->netdev);
5158         netif_device_detach(priv->netdev);
5159         rtnl_unlock();
5160
5161         mlx5e_nic_set_rx_mode(priv);
5162
5163         mlx5e_hv_vhca_stats_destroy(priv);
5164         if (mlx5e_monitor_counter_supported(priv))
5165                 mlx5e_monitor_counter_cleanup(priv);
5166
5167         mlx5e_disable_blocking_events(priv);
5168         if (priv->en_trap) {
5169                 mlx5e_deactivate_trap(priv);
5170                 mlx5e_close_trap(priv->en_trap);
5171                 priv->en_trap = NULL;
5172         }
5173         mlx5e_disable_async_events(priv);
5174         mlx5_lag_remove_netdev(mdev, priv->netdev);
5175         mlx5_vxlan_reset_to_default(mdev->vxlan);
5176 }
5177
5178 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5179 {
5180         return mlx5e_refresh_tirs(priv, false, false);
5181 }
5182
5183 static const struct mlx5e_profile mlx5e_nic_profile = {
5184         .init              = mlx5e_nic_init,
5185         .cleanup           = mlx5e_nic_cleanup,
5186         .init_rx           = mlx5e_init_nic_rx,
5187         .cleanup_rx        = mlx5e_cleanup_nic_rx,
5188         .init_tx           = mlx5e_init_nic_tx,
5189         .cleanup_tx        = mlx5e_cleanup_nic_tx,
5190         .enable            = mlx5e_nic_enable,
5191         .disable           = mlx5e_nic_disable,
5192         .update_rx         = mlx5e_update_nic_rx,
5193         .update_stats      = mlx5e_stats_update_ndo_stats,
5194         .update_carrier    = mlx5e_update_carrier,
5195         .rx_handlers       = &mlx5e_rx_handlers_nic,
5196         .max_tc            = MLX5E_MAX_NUM_TC,
5197         .rq_groups         = MLX5E_NUM_RQ_GROUPS(XSK),
5198         .stats_grps        = mlx5e_nic_stats_grps,
5199         .stats_grps_num    = mlx5e_nic_stats_grps_num,
5200         .features          = BIT(MLX5E_PROFILE_FEATURE_PTP_RX) |
5201                 BIT(MLX5E_PROFILE_FEATURE_PTP_TX) |
5202                 BIT(MLX5E_PROFILE_FEATURE_QOS_HTB),
5203 };
5204
5205 static int mlx5e_profile_max_num_channels(struct mlx5_core_dev *mdev,
5206                                           const struct mlx5e_profile *profile)
5207 {
5208         int nch;
5209
5210         nch = mlx5e_get_max_num_channels(mdev);
5211
5212         if (profile->max_nch_limit)
5213                 nch = min_t(int, nch, profile->max_nch_limit(mdev));
5214         return nch;
5215 }
5216
5217 static unsigned int
5218 mlx5e_calc_max_nch(struct mlx5_core_dev *mdev, struct net_device *netdev,
5219                    const struct mlx5e_profile *profile)
5220
5221 {
5222         unsigned int max_nch, tmp;
5223
5224         /* core resources */
5225         max_nch = mlx5e_profile_max_num_channels(mdev, profile);
5226
5227         /* netdev rx queues */
5228         tmp = netdev->num_rx_queues / max_t(u8, profile->rq_groups, 1);
5229         max_nch = min_t(unsigned int, max_nch, tmp);
5230
5231         /* netdev tx queues */
5232         tmp = netdev->num_tx_queues;
5233         if (mlx5_qos_is_supported(mdev))
5234                 tmp -= mlx5e_qos_max_leaf_nodes(mdev);
5235         if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn))
5236                 tmp -= profile->max_tc;
5237         tmp = tmp / profile->max_tc;
5238         max_nch = min_t(unsigned int, max_nch, tmp);
5239
5240         return max_nch;
5241 }
5242
5243 /* mlx5e generic netdev management API (move to en_common.c) */
5244 int mlx5e_priv_init(struct mlx5e_priv *priv,
5245                     const struct mlx5e_profile *profile,
5246                     struct net_device *netdev,
5247                     struct mlx5_core_dev *mdev)
5248 {
5249         int nch, num_txqs, node;
5250         int err;
5251
5252         num_txqs = netdev->num_tx_queues;
5253         nch = mlx5e_calc_max_nch(mdev, netdev, profile);
5254         node = dev_to_node(mlx5_core_dma_dev(mdev));
5255
5256         /* priv init */
5257         priv->mdev        = mdev;
5258         priv->netdev      = netdev;
5259         priv->msglevel    = MLX5E_MSG_LEVEL;
5260         priv->max_nch     = nch;
5261         priv->max_opened_tc = 1;
5262
5263         if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL))
5264                 return -ENOMEM;
5265
5266         mutex_init(&priv->state_lock);
5267
5268         err = mlx5e_selq_init(&priv->selq, &priv->state_lock);
5269         if (err)
5270                 goto err_free_cpumask;
5271
5272         hash_init(priv->htb.qos_tc2node);
5273         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5274         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5275         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5276         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5277
5278         priv->wq = create_singlethread_workqueue("mlx5e");
5279         if (!priv->wq)
5280                 goto err_free_selq;
5281
5282         priv->txq2sq = kcalloc_node(num_txqs, sizeof(*priv->txq2sq), GFP_KERNEL, node);
5283         if (!priv->txq2sq)
5284                 goto err_destroy_workqueue;
5285
5286         priv->tx_rates = kcalloc_node(num_txqs, sizeof(*priv->tx_rates), GFP_KERNEL, node);
5287         if (!priv->tx_rates)
5288                 goto err_free_txq2sq;
5289
5290         priv->channel_stats =
5291                 kcalloc_node(nch, sizeof(*priv->channel_stats), GFP_KERNEL, node);
5292         if (!priv->channel_stats)
5293                 goto err_free_tx_rates;
5294
5295         return 0;
5296
5297 err_free_tx_rates:
5298         kfree(priv->tx_rates);
5299 err_free_txq2sq:
5300         kfree(priv->txq2sq);
5301 err_destroy_workqueue:
5302         destroy_workqueue(priv->wq);
5303 err_free_selq:
5304         mlx5e_selq_cleanup(&priv->selq);
5305 err_free_cpumask:
5306         free_cpumask_var(priv->scratchpad.cpumask);
5307         return -ENOMEM;
5308 }
5309
5310 void mlx5e_priv_cleanup(struct mlx5e_priv *priv)
5311 {
5312         int i;
5313
5314         /* bail if change profile failed and also rollback failed */
5315         if (!priv->mdev)
5316                 return;
5317
5318         for (i = 0; i < priv->stats_nch; i++)
5319                 kvfree(priv->channel_stats[i]);
5320         kfree(priv->channel_stats);
5321         kfree(priv->tx_rates);
5322         kfree(priv->txq2sq);
5323         destroy_workqueue(priv->wq);
5324         mutex_lock(&priv->state_lock);
5325         mlx5e_selq_cleanup(&priv->selq);
5326         mutex_unlock(&priv->state_lock);
5327         free_cpumask_var(priv->scratchpad.cpumask);
5328
5329         for (i = 0; i < priv->htb.max_qos_sqs; i++)
5330                 kfree(priv->htb.qos_sq_stats[i]);
5331         kvfree(priv->htb.qos_sq_stats);
5332
5333         if (priv->mqprio_rl) {
5334                 mlx5e_mqprio_rl_cleanup(priv->mqprio_rl);
5335                 mlx5e_mqprio_rl_free(priv->mqprio_rl);
5336         }
5337
5338         memset(priv, 0, sizeof(*priv));
5339 }
5340
5341 static unsigned int mlx5e_get_max_num_txqs(struct mlx5_core_dev *mdev,
5342                                            const struct mlx5e_profile *profile)
5343 {
5344         unsigned int nch, ptp_txqs, qos_txqs;
5345
5346         nch = mlx5e_profile_max_num_channels(mdev, profile);
5347
5348         ptp_txqs = MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn) &&
5349                 mlx5e_profile_feature_cap(profile, PTP_TX) ?
5350                 profile->max_tc : 0;
5351
5352         qos_txqs = mlx5_qos_is_supported(mdev) &&
5353                 mlx5e_profile_feature_cap(profile, QOS_HTB) ?
5354                 mlx5e_qos_max_leaf_nodes(mdev) : 0;
5355
5356         return nch * profile->max_tc + ptp_txqs + qos_txqs;
5357 }
5358
5359 static unsigned int mlx5e_get_max_num_rxqs(struct mlx5_core_dev *mdev,
5360                                            const struct mlx5e_profile *profile)
5361 {
5362         unsigned int nch;
5363
5364         nch = mlx5e_profile_max_num_channels(mdev, profile);
5365
5366         return nch * profile->rq_groups;
5367 }
5368
5369 struct net_device *
5370 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile)
5371 {
5372         struct net_device *netdev;
5373         unsigned int txqs, rxqs;
5374         int err;
5375
5376         txqs = mlx5e_get_max_num_txqs(mdev, profile);
5377         rxqs = mlx5e_get_max_num_rxqs(mdev, profile);
5378
5379         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), txqs, rxqs);
5380         if (!netdev) {
5381                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5382                 return NULL;
5383         }
5384
5385         err = mlx5e_priv_init(netdev_priv(netdev), profile, netdev, mdev);
5386         if (err) {
5387                 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5388                 goto err_free_netdev;
5389         }
5390
5391         netif_carrier_off(netdev);
5392         netif_tx_disable(netdev);
5393         dev_net_set(netdev, mlx5_core_net(mdev));
5394
5395         return netdev;
5396
5397 err_free_netdev:
5398         free_netdev(netdev);
5399
5400         return NULL;
5401 }
5402
5403 static void mlx5e_update_features(struct net_device *netdev)
5404 {
5405         if (netdev->reg_state != NETREG_REGISTERED)
5406                 return; /* features will be updated on netdev registration */
5407
5408         rtnl_lock();
5409         netdev_update_features(netdev);
5410         rtnl_unlock();
5411 }
5412
5413 static void mlx5e_reset_channels(struct net_device *netdev)
5414 {
5415         netdev_reset_tc(netdev);
5416 }
5417
5418 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5419 {
5420         const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED;
5421         const struct mlx5e_profile *profile = priv->profile;
5422         int max_nch;
5423         int err;
5424
5425         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5426
5427         /* max number of channels may have changed */
5428         max_nch = mlx5e_calc_max_nch(priv->mdev, priv->netdev, profile);
5429         if (priv->channels.params.num_channels > max_nch) {
5430                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5431                 /* Reducing the number of channels - RXFH has to be reset, and
5432                  * mlx5e_num_channels_changed below will build the RQT.
5433                  */
5434                 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED;
5435                 priv->channels.params.num_channels = max_nch;
5436                 if (priv->channels.params.mqprio.mode == TC_MQPRIO_MODE_CHANNEL) {
5437                         mlx5_core_warn(priv->mdev, "MLX5E: Disabling MQPRIO channel mode\n");
5438                         mlx5e_params_mqprio_reset(&priv->channels.params);
5439                 }
5440         }
5441         if (max_nch != priv->max_nch) {
5442                 mlx5_core_warn(priv->mdev,
5443                                "MLX5E: Updating max number of channels from %u to %u\n",
5444                                priv->max_nch, max_nch);
5445                 priv->max_nch = max_nch;
5446         }
5447
5448         /* 1. Set the real number of queues in the kernel the first time.
5449          * 2. Set our default XPS cpumask.
5450          * 3. Build the RQT.
5451          *
5452          * rtnl_lock is required by netif_set_real_num_*_queues in case the
5453          * netdev has been registered by this point (if this function was called
5454          * in the reload or resume flow).
5455          */
5456         if (take_rtnl)
5457                 rtnl_lock();
5458         err = mlx5e_num_channels_changed(priv);
5459         if (take_rtnl)
5460                 rtnl_unlock();
5461         if (err)
5462                 goto out;
5463
5464         err = profile->init_tx(priv);
5465         if (err)
5466                 goto out;
5467
5468         err = profile->init_rx(priv);
5469         if (err)
5470                 goto err_cleanup_tx;
5471
5472         if (profile->enable)
5473                 profile->enable(priv);
5474
5475         mlx5e_update_features(priv->netdev);
5476
5477         return 0;
5478
5479 err_cleanup_tx:
5480         profile->cleanup_tx(priv);
5481
5482 out:
5483         mlx5e_reset_channels(priv->netdev);
5484         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5485         cancel_work_sync(&priv->update_stats_work);
5486         return err;
5487 }
5488
5489 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5490 {
5491         const struct mlx5e_profile *profile = priv->profile;
5492
5493         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5494
5495         if (profile->disable)
5496                 profile->disable(priv);
5497         flush_workqueue(priv->wq);
5498
5499         profile->cleanup_rx(priv);
5500         profile->cleanup_tx(priv);
5501         mlx5e_reset_channels(priv->netdev);
5502         cancel_work_sync(&priv->update_stats_work);
5503 }
5504
5505 static int
5506 mlx5e_netdev_attach_profile(struct net_device *netdev, struct mlx5_core_dev *mdev,
5507                             const struct mlx5e_profile *new_profile, void *new_ppriv)
5508 {
5509         struct mlx5e_priv *priv = netdev_priv(netdev);
5510         int err;
5511
5512         err = mlx5e_priv_init(priv, new_profile, netdev, mdev);
5513         if (err) {
5514                 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5515                 return err;
5516         }
5517         netif_carrier_off(netdev);
5518         priv->profile = new_profile;
5519         priv->ppriv = new_ppriv;
5520         err = new_profile->init(priv->mdev, priv->netdev);
5521         if (err)
5522                 goto priv_cleanup;
5523         err = mlx5e_attach_netdev(priv);
5524         if (err)
5525                 goto profile_cleanup;
5526         return err;
5527
5528 profile_cleanup:
5529         new_profile->cleanup(priv);
5530 priv_cleanup:
5531         mlx5e_priv_cleanup(priv);
5532         return err;
5533 }
5534
5535 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
5536                                 const struct mlx5e_profile *new_profile, void *new_ppriv)
5537 {
5538         const struct mlx5e_profile *orig_profile = priv->profile;
5539         struct net_device *netdev = priv->netdev;
5540         struct mlx5_core_dev *mdev = priv->mdev;
5541         void *orig_ppriv = priv->ppriv;
5542         int err, rollback_err;
5543
5544         /* cleanup old profile */
5545         mlx5e_detach_netdev(priv);
5546         priv->profile->cleanup(priv);
5547         mlx5e_priv_cleanup(priv);
5548
5549         err = mlx5e_netdev_attach_profile(netdev, mdev, new_profile, new_ppriv);
5550         if (err) { /* roll back to original profile */
5551                 netdev_warn(netdev, "%s: new profile init failed, %d\n", __func__, err);
5552                 goto rollback;
5553         }
5554
5555         return 0;
5556
5557 rollback:
5558         rollback_err = mlx5e_netdev_attach_profile(netdev, mdev, orig_profile, orig_ppriv);
5559         if (rollback_err)
5560                 netdev_err(netdev, "%s: failed to rollback to orig profile, %d\n",
5561                            __func__, rollback_err);
5562         return err;
5563 }
5564
5565 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv)
5566 {
5567         mlx5e_netdev_change_profile(priv, &mlx5e_nic_profile, NULL);
5568 }
5569
5570 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5571 {
5572         struct net_device *netdev = priv->netdev;
5573
5574         mlx5e_priv_cleanup(priv);
5575         free_netdev(netdev);
5576 }
5577
5578 static int mlx5e_resume(struct auxiliary_device *adev)
5579 {
5580         struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5581         struct mlx5e_priv *priv = auxiliary_get_drvdata(adev);
5582         struct net_device *netdev = priv->netdev;
5583         struct mlx5_core_dev *mdev = edev->mdev;
5584         int err;
5585
5586         if (netif_device_present(netdev))
5587                 return 0;
5588
5589         err = mlx5e_create_mdev_resources(mdev);
5590         if (err)
5591                 return err;
5592
5593         err = mlx5e_attach_netdev(priv);
5594         if (err) {
5595                 mlx5e_destroy_mdev_resources(mdev);
5596                 return err;
5597         }
5598
5599         return 0;
5600 }
5601
5602 static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state)
5603 {
5604         struct mlx5e_priv *priv = auxiliary_get_drvdata(adev);
5605         struct net_device *netdev = priv->netdev;
5606         struct mlx5_core_dev *mdev = priv->mdev;
5607
5608         if (!netif_device_present(netdev))
5609                 return -ENODEV;
5610
5611         mlx5e_detach_netdev(priv);
5612         mlx5e_destroy_mdev_resources(mdev);
5613         return 0;
5614 }
5615
5616 static int mlx5e_probe(struct auxiliary_device *adev,
5617                        const struct auxiliary_device_id *id)
5618 {
5619         struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5620         const struct mlx5e_profile *profile = &mlx5e_nic_profile;
5621         struct mlx5_core_dev *mdev = edev->mdev;
5622         struct net_device *netdev;
5623         pm_message_t state = {};
5624         struct mlx5e_priv *priv;
5625         int err;
5626
5627         netdev = mlx5e_create_netdev(mdev, profile);
5628         if (!netdev) {
5629                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5630                 return -ENOMEM;
5631         }
5632
5633         mlx5e_build_nic_netdev(netdev);
5634
5635         priv = netdev_priv(netdev);
5636         auxiliary_set_drvdata(adev, priv);
5637
5638         priv->profile = profile;
5639         priv->ppriv = NULL;
5640
5641         err = mlx5e_devlink_port_register(priv);
5642         if (err) {
5643                 mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err);
5644                 goto err_destroy_netdev;
5645         }
5646
5647         err = profile->init(mdev, netdev);
5648         if (err) {
5649                 mlx5_core_err(mdev, "mlx5e_nic_profile init failed, %d\n", err);
5650                 goto err_devlink_cleanup;
5651         }
5652
5653         err = mlx5e_resume(adev);
5654         if (err) {
5655                 mlx5_core_err(mdev, "mlx5e_resume failed, %d\n", err);
5656                 goto err_profile_cleanup;
5657         }
5658
5659         err = register_netdev(netdev);
5660         if (err) {
5661                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5662                 goto err_resume;
5663         }
5664
5665         mlx5e_devlink_port_type_eth_set(priv);
5666
5667         mlx5e_dcbnl_init_app(priv);
5668         mlx5_uplink_netdev_set(mdev, netdev);
5669         return 0;
5670
5671 err_resume:
5672         mlx5e_suspend(adev, state);
5673 err_profile_cleanup:
5674         profile->cleanup(priv);
5675 err_devlink_cleanup:
5676         mlx5e_devlink_port_unregister(priv);
5677 err_destroy_netdev:
5678         mlx5e_destroy_netdev(priv);
5679         return err;
5680 }
5681
5682 static void mlx5e_remove(struct auxiliary_device *adev)
5683 {
5684         struct mlx5e_priv *priv = auxiliary_get_drvdata(adev);
5685         pm_message_t state = {};
5686
5687         mlx5e_dcbnl_delete_app(priv);
5688         unregister_netdev(priv->netdev);
5689         mlx5e_suspend(adev, state);
5690         priv->profile->cleanup(priv);
5691         mlx5e_devlink_port_unregister(priv);
5692         mlx5e_destroy_netdev(priv);
5693 }
5694
5695 static const struct auxiliary_device_id mlx5e_id_table[] = {
5696         { .name = MLX5_ADEV_NAME ".eth", },
5697         {},
5698 };
5699
5700 MODULE_DEVICE_TABLE(auxiliary, mlx5e_id_table);
5701
5702 static struct auxiliary_driver mlx5e_driver = {
5703         .name = "eth",
5704         .probe = mlx5e_probe,
5705         .remove = mlx5e_remove,
5706         .suspend = mlx5e_suspend,
5707         .resume = mlx5e_resume,
5708         .id_table = mlx5e_id_table,
5709 };
5710
5711 int mlx5e_init(void)
5712 {
5713         int ret;
5714
5715         mlx5e_build_ptys2ethtool_map();
5716         ret = auxiliary_driver_register(&mlx5e_driver);
5717         if (ret)
5718                 return ret;
5719
5720         ret = mlx5e_rep_init();
5721         if (ret)
5722                 auxiliary_driver_unregister(&mlx5e_driver);
5723         return ret;
5724 }
5725
5726 void mlx5e_cleanup(void)
5727 {
5728         mlx5e_rep_cleanup();
5729         auxiliary_driver_unregister(&mlx5e_driver);
5730 }