2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/crash_dump.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/mlx5/fs.h>
47 #include <linux/rhashtable.h>
48 #include <net/udp_tunnel.h>
49 #include <net/switchdev.h>
51 #include <linux/dim.h>
52 #include <linux/bits.h>
54 #include "mlx5_core.h"
58 #include "lib/hv_vhca.h"
60 extern const struct net_device_ops mlx5e_netdev_ops;
63 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4)
64 #define MLX5E_METADATA_ETHER_LEN 8
66 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
68 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
70 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))
71 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))
73 #define MLX5E_MAX_NUM_TC 8
75 #define MLX5_RX_HEADROOM NET_SKB_PAD
76 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \
77 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
79 #define MLX5E_RX_MAX_HEAD (256)
81 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
82 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
83 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
84 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
85 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \
86 MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD))
88 #define MLX5_MPWRQ_LOG_WQE_SZ 18
89 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
90 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
91 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
93 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
94 #define MLX5E_REQUIRED_WQE_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8))
95 #define MLX5E_LOG_ALIGNED_MPWQE_PPW (ilog2(MLX5E_REQUIRED_WQE_MTTS))
96 #define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS)
97 #define MLX5E_MAX_RQ_NUM_MTTS \
98 ((1 << 16) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */
99 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))
100 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW \
101 (ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS))
102 #define MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW \
103 (MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW + \
104 (MLX5_MPWRQ_LOG_WQE_SZ - MLX5E_ORDER2_MAX_PACKET_MTU))
106 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM))
107 #define MLX5E_LOG_MAX_RX_WQE_BULK \
108 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ)))
110 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
111 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
112 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
114 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK)
115 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
116 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE min_t(u8, 0xd, \
117 MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW)
119 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2
121 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
122 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
123 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
125 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
126 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
127 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
128 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
129 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
130 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
131 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
132 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
134 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
135 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
136 #define MLX5E_MIN_NUM_CHANNELS 0x1
137 #define MLX5E_MAX_NUM_CHANNELS MLX5E_INDIR_RQT_SIZE
138 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
139 #define MLX5E_TX_CQ_POLL_BUDGET 128
140 #define MLX5E_TX_XSK_POLL_BUDGET 64
141 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */
143 #define MLX5E_UMR_WQE_INLINE_SZ \
144 (sizeof(struct mlx5e_umr_wqe) + \
145 ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(struct mlx5_mtt), \
146 MLX5_UMR_MTT_ALIGNMENT))
147 #define MLX5E_UMR_WQEBBS \
148 (DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_BB))
150 #define MLX5E_MSG_LEVEL NETIF_MSG_LINK
152 #define mlx5e_dbg(mlevel, priv, format, ...) \
154 if (NETIF_MSG_##mlevel & (priv)->msglevel) \
155 netdev_warn(priv->netdev, format, \
159 enum mlx5e_rq_group {
160 MLX5E_RQ_GROUP_REGULAR,
162 #define MLX5E_NUM_RQ_GROUPS(g) (1 + MLX5E_RQ_GROUP_##g)
165 static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev)
167 if (mlx5_lag_is_lacp_owner(mdev))
170 return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS);
173 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
176 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
177 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
180 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
185 /* Use this function to get max num channels (rxqs/txqs) only to create netdev */
186 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
188 return is_kdump_kernel() ?
189 MLX5E_MIN_NUM_CHANNELS :
190 min_t(int, mlx5_comp_vectors_count(mdev), MLX5E_MAX_NUM_CHANNELS);
193 struct mlx5e_tx_wqe {
194 struct mlx5_wqe_ctrl_seg ctrl;
195 struct mlx5_wqe_eth_seg eth;
196 struct mlx5_wqe_data_seg data[0];
199 struct mlx5e_rx_wqe_ll {
200 struct mlx5_wqe_srq_next_seg next;
201 struct mlx5_wqe_data_seg data[];
204 struct mlx5e_rx_wqe_cyc {
205 struct mlx5_wqe_data_seg data[0];
208 struct mlx5e_umr_wqe {
209 struct mlx5_wqe_ctrl_seg ctrl;
210 struct mlx5_wqe_umr_ctrl_seg uctrl;
211 struct mlx5_mkey_seg mkc;
212 struct mlx5_mtt inline_mtts[0];
215 extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
217 enum mlx5e_priv_flag {
218 MLX5E_PFLAG_RX_CQE_BASED_MODER,
219 MLX5E_PFLAG_TX_CQE_BASED_MODER,
220 MLX5E_PFLAG_RX_CQE_COMPRESS,
221 MLX5E_PFLAG_RX_STRIDING_RQ,
222 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE,
223 MLX5E_PFLAG_XDP_TX_MPWQE,
224 MLX5E_NUM_PFLAGS, /* Keep last */
227 #define MLX5E_SET_PFLAG(params, pflag, enable) \
230 (params)->pflags |= BIT(pflag); \
232 (params)->pflags &= ~(BIT(pflag)); \
235 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag))))
237 struct mlx5e_params {
240 u8 log_rq_mtu_frames;
243 bool rx_cqe_compress_def;
244 bool tunneled_offload_en;
245 struct dim_cq_moder rx_cq_moderation;
246 struct dim_cq_moder tx_cq_moderation;
248 u8 tx_min_inline_mode;
249 bool vlan_strip_disable;
255 struct bpf_prog *xdp_prog;
256 struct mlx5e_xsk *xsk;
262 MLX5E_RQ_STATE_ENABLED,
263 MLX5E_RQ_STATE_RECOVERING,
265 MLX5E_RQ_STATE_NO_CSUM_COMPLETE,
266 MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */
267 MLX5E_RQ_STATE_FPGA_TLS, /* FPGA TLS enabled */
271 /* data path - accessed per cqe */
274 /* data path - accessed per napi poll */
276 struct napi_struct *napi;
277 struct mlx5_core_cq mcq;
278 struct mlx5e_channel *channel;
281 struct mlx5_core_dev *mdev;
282 struct mlx5_wq_ctrl wq_ctrl;
283 } ____cacheline_aligned_in_smp;
285 struct mlx5e_cq_decomp {
286 /* cqe decompression */
287 struct mlx5_cqe64 title;
288 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
292 } ____cacheline_aligned_in_smp;
294 enum mlx5e_dma_map_type {
295 MLX5E_DMA_MAP_SINGLE,
299 struct mlx5e_sq_dma {
302 enum mlx5e_dma_map_type type;
306 MLX5E_SQ_STATE_ENABLED,
307 MLX5E_SQ_STATE_RECOVERING,
308 MLX5E_SQ_STATE_IPSEC,
311 MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE,
312 MLX5E_SQ_STATE_PENDING_XSK_TX,
318 /* dirtied @completion */
321 struct dim dim; /* Adaptive Moderation */
324 u16 pc ____cacheline_aligned_in_smp;
330 struct mlx5_wq_cyc wq;
332 struct mlx5e_sq_stats *stats;
334 struct mlx5e_sq_dma *dma_fifo;
335 struct mlx5e_tx_wqe_info *wqe_info;
337 void __iomem *uar_map;
338 struct netdev_queue *txq;
346 struct hwtstamp_config *tstamp;
347 struct mlx5_clock *clock;
350 struct mlx5_wq_ctrl wq_ctrl;
351 struct mlx5e_channel *channel;
355 struct work_struct recover_work;
356 } ____cacheline_aligned_in_smp;
358 struct mlx5e_dma_info {
362 struct xdp_buff *xsk;
366 /* XDP packets can be transmitted in different ways. On completion, we need to
367 * distinguish between them to clean up things in a proper way.
369 enum mlx5e_xdp_xmit_mode {
370 /* An xdp_frame was transmitted due to either XDP_REDIRECT from another
371 * device or XDP_TX from an XSK RQ. The frame has to be unmapped and
374 MLX5E_XDP_XMIT_MODE_FRAME,
376 /* The xdp_frame was created in place as a result of XDP_TX from a
377 * regular RQ. No DMA remapping happened, and the page belongs to us.
379 MLX5E_XDP_XMIT_MODE_PAGE,
381 /* No xdp_frame was created at all, the transmit happened from a UMEM
382 * page. The UMEM Completion Ring producer pointer has to be increased.
384 MLX5E_XDP_XMIT_MODE_XSK,
387 struct mlx5e_xdp_info {
388 enum mlx5e_xdp_xmit_mode mode;
391 struct xdp_frame *xdpf;
396 struct mlx5e_dma_info di;
401 struct mlx5e_xdp_xmit_data {
407 struct mlx5e_xdp_info_fifo {
408 struct mlx5e_xdp_info *xi;
414 struct mlx5e_xdp_mpwqe {
415 /* Current MPWQE session */
416 struct mlx5e_tx_wqe *wqe;
423 typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *);
424 typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *,
425 struct mlx5e_xdp_xmit_data *,
426 struct mlx5e_xdp_info *,
432 /* dirtied @completion */
437 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp;
439 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
440 struct mlx5e_xdp_mpwqe mpwqe;
445 struct xdp_umem *umem;
446 struct mlx5_wq_cyc wq;
447 struct mlx5e_xdpsq_stats *stats;
448 mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check;
449 mlx5e_fp_xmit_xdp_frame xmit_xdp_frame;
451 struct mlx5e_xdp_wqe_info *wqe_info;
452 struct mlx5e_xdp_info_fifo xdpi_fifo;
454 void __iomem *uar_map;
463 struct mlx5_wq_ctrl wq_ctrl;
464 struct mlx5e_channel *channel;
465 } ____cacheline_aligned_in_smp;
472 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
475 /* write@xmit, read@completion */
477 struct mlx5e_icosq_wqe_info *wqe_info;
481 struct mlx5_wq_cyc wq;
482 void __iomem *uar_map;
487 struct mlx5_wq_ctrl wq_ctrl;
488 struct mlx5e_channel *channel;
490 struct work_struct recover_work;
491 } ____cacheline_aligned_in_smp;
493 struct mlx5e_wqe_frag_info {
494 struct mlx5e_dma_info *di;
499 struct mlx5e_umr_dma_info {
500 struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
503 struct mlx5e_mpw_info {
504 struct mlx5e_umr_dma_info umr;
505 u16 consumed_strides;
506 DECLARE_BITMAP(xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
509 #define MLX5E_MAX_RX_FRAGS 4
511 /* a single cache unit is capable to serve one napi call (for non-striding rq)
512 * or a MPWQE (for striding rq).
514 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
515 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
516 #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
517 struct mlx5e_page_cache {
520 struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
524 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
525 typedef struct sk_buff *
526 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
527 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
528 typedef struct sk_buff *
529 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
530 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
531 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);
532 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
534 int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk);
537 MLX5E_RQ_FLAG_XDP_XMIT,
538 MLX5E_RQ_FLAG_XDP_REDIRECT,
541 struct mlx5e_rq_frag_info {
546 struct mlx5e_rq_frags_info {
547 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS];
557 struct mlx5_wq_cyc wq;
558 struct mlx5e_wqe_frag_info *frags;
559 struct mlx5e_dma_info *di;
560 struct mlx5e_rq_frags_info info;
561 mlx5e_fp_skb_from_cqe skb_from_cqe;
564 struct mlx5_wq_ll wq;
565 struct mlx5e_umr_wqe umr_wqe;
566 struct mlx5e_mpw_info *info;
567 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq;
579 u8 map_dir; /* dma map direction */
582 struct mlx5e_channel *channel;
584 struct net_device *netdev;
585 struct mlx5e_rq_stats *stats;
587 struct mlx5e_cq_decomp cqd;
588 struct mlx5e_page_cache page_cache;
589 struct hwtstamp_config *tstamp;
590 struct mlx5_clock *clock;
592 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
593 mlx5e_fp_post_rx_wqes post_wqes;
594 mlx5e_fp_dealloc_wqe dealloc_wqe;
600 struct dim dim; /* Dynamic Interrupt Moderation */
603 struct bpf_prog __rcu *xdp_prog;
604 struct mlx5e_xdpsq *xdpsq;
605 DECLARE_BITMAP(flags, 8);
606 struct page_pool *page_pool;
608 /* AF_XDP zero-copy */
609 struct xdp_umem *umem;
611 struct work_struct recover_work;
614 struct mlx5_wq_ctrl wq_ctrl;
618 struct mlx5_core_dev *mdev;
619 struct mlx5_core_mkey umr_mkey;
621 /* XDP read-mostly */
622 struct xdp_rxq_info xdp_rxq;
623 } ____cacheline_aligned_in_smp;
625 enum mlx5e_channel_state {
626 MLX5E_CHANNEL_STATE_XSK,
627 MLX5E_CHANNEL_NUM_STATES
630 struct mlx5e_channel {
633 struct mlx5e_xdpsq rq_xdpsq;
634 struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC];
635 struct mlx5e_icosq icosq; /* internal control operations */
637 struct napi_struct napi;
639 struct net_device *netdev;
645 struct mlx5e_xdpsq xdpsq;
647 /* AF_XDP zero-copy */
648 struct mlx5e_rq xskrq;
649 struct mlx5e_xdpsq xsksq;
652 struct mlx5e_icosq async_icosq;
653 /* async_icosq can be accessed from any CPU - the spinlock protects it. */
654 spinlock_t async_icosq_lock;
656 /* data path - accessed per napi poll */
657 struct irq_desc *irq_desc;
658 struct mlx5e_ch_stats *stats;
661 struct mlx5e_priv *priv;
662 struct mlx5_core_dev *mdev;
663 struct hwtstamp_config *tstamp;
664 DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES);
669 struct mlx5e_channels {
670 struct mlx5e_channel **c;
672 struct mlx5e_params params;
675 struct mlx5e_channel_stats {
676 struct mlx5e_ch_stats ch;
677 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
678 struct mlx5e_rq_stats rq;
679 struct mlx5e_rq_stats xskrq;
680 struct mlx5e_xdpsq_stats rq_xdpsq;
681 struct mlx5e_xdpsq_stats xdpsq;
682 struct mlx5e_xdpsq_stats xsksq;
683 } ____cacheline_aligned_in_smp;
687 MLX5E_STATE_DESTROYING,
688 MLX5E_STATE_XDP_TX_ENABLED,
689 MLX5E_STATE_XDP_ACTIVE,
699 struct mlx5e_rqt rqt;
700 struct list_head list;
708 struct mlx5e_rss_params {
709 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
710 u32 rx_hash_fields[MLX5E_NUM_INDIR_TIRS];
711 u8 toeplitz_hash_key[40];
715 struct mlx5e_modify_sq_param {
722 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
723 struct mlx5e_hv_vhca_stats_agent {
724 struct mlx5_hv_vhca_agent *agent;
725 struct delayed_work work;
732 /* UMEMs are stored separately from channels, because we don't want to
733 * lose them when channels are recreated. The kernel also stores UMEMs,
734 * but it doesn't distinguish between zero-copy and non-zero-copy UMEMs,
735 * so rely on our mechanism.
737 struct xdp_umem **umems;
742 /* Temporary storage for variables that are allocated when struct mlx5e_priv is
743 * initialized, and used where we can't allocate them because that functions
744 * must not fail. Use with care and make sure the same variable is not used
745 * simultaneously by multiple users.
747 struct mlx5e_scratchpad {
748 cpumask_var_t cpumask;
752 /* priv data path fields - start */
753 struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC];
754 int channel_tc2realtxq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
755 #ifdef CONFIG_MLX5_CORE_EN_DCB
756 struct mlx5e_dcbx_dp dcbx_dp;
758 /* priv data path fields - end */
762 struct mutex state_lock; /* Protects Interface state */
763 struct mlx5e_rq drop_rq;
765 struct mlx5e_channels channels;
766 u32 tisn[MLX5_MAX_PORTS][MLX5E_MAX_NUM_TC];
767 struct mlx5e_rqt indir_rqt;
768 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
769 struct mlx5e_tir inner_indir_tir[MLX5E_NUM_INDIR_TIRS];
770 struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
771 struct mlx5e_tir xsk_tir[MLX5E_MAX_NUM_CHANNELS];
772 struct mlx5e_rss_params rss_params;
773 u32 tx_rates[MLX5E_MAX_NUM_SQS];
775 struct mlx5e_flow_steering fs;
777 struct workqueue_struct *wq;
778 struct work_struct update_carrier_work;
779 struct work_struct set_rx_mode_work;
780 struct work_struct tx_timeout_work;
781 struct work_struct update_stats_work;
782 struct work_struct monitor_counters_work;
783 struct mlx5_nb monitor_counters_nb;
785 struct mlx5_core_dev *mdev;
786 struct net_device *netdev;
787 struct mlx5e_stats stats;
788 struct mlx5e_channel_stats channel_stats[MLX5E_MAX_NUM_CHANNELS];
791 struct hwtstamp_config tstamp;
793 u16 drop_rq_q_counter;
794 struct notifier_block events_nb;
796 struct udp_tunnel_nic_info nic_info;
797 #ifdef CONFIG_MLX5_CORE_EN_DCB
798 struct mlx5e_dcbx dcbx;
801 const struct mlx5e_profile *profile;
803 #ifdef CONFIG_MLX5_EN_IPSEC
804 struct mlx5e_ipsec *ipsec;
806 #ifdef CONFIG_MLX5_EN_TLS
807 struct mlx5e_tls *tls;
809 struct devlink_health_reporter *tx_reporter;
810 struct devlink_health_reporter *rx_reporter;
811 struct devlink_port dl_port;
812 struct mlx5e_xsk xsk;
813 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
814 struct mlx5e_hv_vhca_stats_agent stats_agent;
816 struct mlx5e_scratchpad scratchpad;
819 struct mlx5e_rx_handlers {
820 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
821 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
824 extern const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic;
826 struct mlx5e_profile {
827 int (*init)(struct mlx5_core_dev *mdev,
828 struct net_device *netdev,
829 const struct mlx5e_profile *profile, void *ppriv);
830 void (*cleanup)(struct mlx5e_priv *priv);
831 int (*init_rx)(struct mlx5e_priv *priv);
832 void (*cleanup_rx)(struct mlx5e_priv *priv);
833 int (*init_tx)(struct mlx5e_priv *priv);
834 void (*cleanup_tx)(struct mlx5e_priv *priv);
835 void (*enable)(struct mlx5e_priv *priv);
836 void (*disable)(struct mlx5e_priv *priv);
837 int (*update_rx)(struct mlx5e_priv *priv);
838 void (*update_stats)(struct mlx5e_priv *priv);
839 void (*update_carrier)(struct mlx5e_priv *priv);
840 unsigned int (*stats_grps_num)(struct mlx5e_priv *priv);
841 mlx5e_stats_grp_t *stats_grps;
842 const struct mlx5e_rx_handlers *rx_handlers;
847 void mlx5e_build_ptys2ethtool_map(void);
849 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev);
850 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
851 struct mlx5e_params *params);
853 void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);
854 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s);
856 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
857 int mlx5e_self_test_num(struct mlx5e_priv *priv);
858 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
860 void mlx5e_set_rx_mode_work(struct work_struct *work);
862 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
863 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
864 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val);
866 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
868 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
870 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
872 struct mlx5e_redirect_rqt_param {
875 u32 rqn; /* Direct RQN (Non-RSS) */
878 struct mlx5e_channels *channels;
879 } rss; /* RSS data */
883 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
884 struct mlx5e_redirect_rqt_param rrp);
885 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
886 const struct mlx5e_tirc_config *ttconfig,
887 void *tirc, bool inner);
888 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in);
889 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt);
891 struct mlx5e_xsk_param;
893 struct mlx5e_rq_param;
894 int mlx5e_open_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
895 struct mlx5e_rq_param *param, struct mlx5e_xsk_param *xsk,
896 struct xdp_umem *umem, struct mlx5e_rq *rq);
897 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time);
898 void mlx5e_deactivate_rq(struct mlx5e_rq *rq);
899 void mlx5e_close_rq(struct mlx5e_rq *rq);
901 struct mlx5e_sq_param;
902 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
903 struct mlx5e_sq_param *param, struct mlx5e_icosq *sq);
904 void mlx5e_close_icosq(struct mlx5e_icosq *sq);
905 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
906 struct mlx5e_sq_param *param, struct xdp_umem *umem,
907 struct mlx5e_xdpsq *sq, bool is_redirect);
908 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq);
910 struct mlx5e_cq_param;
911 int mlx5e_open_cq(struct mlx5e_channel *c, struct dim_cq_moder moder,
912 struct mlx5e_cq_param *param, struct mlx5e_cq *cq);
913 void mlx5e_close_cq(struct mlx5e_cq *cq);
915 int mlx5e_open_locked(struct net_device *netdev);
916 int mlx5e_close_locked(struct net_device *netdev);
918 int mlx5e_open_channels(struct mlx5e_priv *priv,
919 struct mlx5e_channels *chs);
920 void mlx5e_close_channels(struct mlx5e_channels *chs);
922 /* Function pointer to be used to modify HW or kernel settings while
925 typedef int (*mlx5e_fp_preactivate)(struct mlx5e_priv *priv, void *context);
926 #define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \
927 int fn##_ctx(struct mlx5e_priv *priv, void *context) \
931 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv);
932 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
933 struct mlx5e_channels *new_chs,
934 mlx5e_fp_preactivate preactivate,
936 int mlx5e_num_channels_changed(struct mlx5e_priv *priv);
937 int mlx5e_num_channels_changed_ctx(struct mlx5e_priv *priv, void *context);
938 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
939 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
941 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
944 void mlx5e_reset_tx_moderation(struct mlx5e_params *params, u8 cq_period_mode);
945 void mlx5e_reset_rx_moderation(struct mlx5e_params *params, u8 cq_period_mode);
946 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode);
947 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode);
949 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params);
950 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
951 struct mlx5e_params *params);
952 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state);
953 void mlx5e_activate_rq(struct mlx5e_rq *rq);
954 void mlx5e_deactivate_rq(struct mlx5e_rq *rq);
955 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq);
956 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq);
958 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
959 struct mlx5e_modify_sq_param *p);
960 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq);
961 void mlx5e_tx_disable_queue(struct netdev_queue *txq);
963 static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev)
965 return MLX5_CAP_ETH(mdev, swp) &&
966 MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso);
969 extern const struct ethtool_ops mlx5e_ethtool_ops;
971 int mlx5e_create_tir(struct mlx5_core_dev *mdev, struct mlx5e_tir *tir,
973 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
974 struct mlx5e_tir *tir);
975 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
976 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
977 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb,
979 void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc);
981 /* common netdev helpers */
982 void mlx5e_create_q_counters(struct mlx5e_priv *priv);
983 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv);
984 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
985 struct mlx5e_rq *drop_rq);
986 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq);
988 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv);
990 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc);
991 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv);
993 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
994 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
995 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
996 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
997 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt);
999 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn);
1000 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
1002 int mlx5e_create_tises(struct mlx5e_priv *priv);
1003 void mlx5e_destroy_tises(struct mlx5e_priv *priv);
1004 int mlx5e_update_nic_rx(struct mlx5e_priv *priv);
1005 void mlx5e_update_carrier(struct mlx5e_priv *priv);
1006 int mlx5e_close(struct net_device *netdev);
1007 int mlx5e_open(struct net_device *netdev);
1009 void mlx5e_queue_update_stats(struct mlx5e_priv *priv);
1010 int mlx5e_bits_invert(unsigned long a, int size);
1012 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv);
1013 int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv *priv, void *context);
1014 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
1015 mlx5e_fp_preactivate preactivate);
1016 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv);
1018 /* ethtool helpers */
1019 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
1020 struct ethtool_drvinfo *drvinfo);
1021 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
1022 uint32_t stringset, uint8_t *data);
1023 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
1024 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
1025 struct ethtool_stats *stats, u64 *data);
1026 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
1027 struct ethtool_ringparam *param);
1028 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
1029 struct ethtool_ringparam *param);
1030 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
1031 struct ethtool_channels *ch);
1032 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
1033 struct ethtool_channels *ch);
1034 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
1035 struct ethtool_coalesce *coal);
1036 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
1037 struct ethtool_coalesce *coal);
1038 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
1039 struct ethtool_link_ksettings *link_ksettings);
1040 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1041 const struct ethtool_link_ksettings *link_ksettings);
1042 int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, u8 *hfunc);
1043 int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key,
1045 int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
1047 int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd);
1048 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv);
1049 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv);
1050 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1051 struct ethtool_ts_info *info);
1052 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1053 struct ethtool_flash *flash);
1054 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1055 struct ethtool_pauseparam *pauseparam);
1056 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1057 struct ethtool_pauseparam *pauseparam);
1059 /* mlx5e generic netdev management API */
1060 int mlx5e_netdev_init(struct net_device *netdev,
1061 struct mlx5e_priv *priv,
1062 struct mlx5_core_dev *mdev,
1063 const struct mlx5e_profile *profile,
1065 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv);
1067 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile,
1068 int nch, void *ppriv);
1069 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
1070 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
1071 void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
1072 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv);
1073 void mlx5e_build_nic_params(struct mlx5e_priv *priv,
1074 struct mlx5e_xsk *xsk,
1075 struct mlx5e_rss_params *rss_params,
1076 struct mlx5e_params *params,
1078 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
1079 struct mlx5e_params *params);
1080 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
1082 void mlx5e_rx_dim_work(struct work_struct *work);
1083 void mlx5e_tx_dim_work(struct work_struct *work);
1085 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
1086 struct net_device *netdev,
1087 netdev_features_t features);
1088 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features);
1089 #ifdef CONFIG_MLX5_ESWITCH
1090 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac);
1091 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate);
1092 int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi);
1093 int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats);
1095 #endif /* __MLX5_EN_H__ */