1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 // Copyright (c) 2020 Mellanox Technologies
7 #include "en/fs_tt_redirect.h"
10 struct mlx5_flow_handle *l2_rule;
11 struct mlx5_flow_handle *udp_v4_rule;
12 struct mlx5_flow_handle *udp_v6_rule;
16 struct mlx5e_ptp_params {
17 struct mlx5e_params params;
18 struct mlx5e_sq_param txq_sq_param;
19 struct mlx5e_rq_param rq_param;
22 struct mlx5e_skb_cb_hwtstamp {
24 ktime_t port_hwtstamp;
27 void mlx5e_skb_cb_hwtstamp_init(struct sk_buff *skb)
29 memset(skb->cb, 0, sizeof(struct mlx5e_skb_cb_hwtstamp));
32 static struct mlx5e_skb_cb_hwtstamp *mlx5e_skb_cb_get_hwts(struct sk_buff *skb)
34 BUILD_BUG_ON(sizeof(struct mlx5e_skb_cb_hwtstamp) > sizeof(skb->cb));
35 return (struct mlx5e_skb_cb_hwtstamp *)skb->cb;
38 static void mlx5e_skb_cb_hwtstamp_tx(struct sk_buff *skb,
39 struct mlx5e_ptp_cq_stats *cq_stats)
41 struct skb_shared_hwtstamps hwts = {};
44 diff = abs(mlx5e_skb_cb_get_hwts(skb)->port_hwtstamp -
45 mlx5e_skb_cb_get_hwts(skb)->cqe_hwtstamp);
47 /* Maximal allowed diff is 1 / 128 second */
48 if (diff > (NSEC_PER_SEC >> 7)) {
50 cq_stats->abort_abs_diff_ns += diff;
54 hwts.hwtstamp = mlx5e_skb_cb_get_hwts(skb)->port_hwtstamp;
55 skb_tstamp_tx(skb, &hwts);
58 void mlx5e_skb_cb_hwtstamp_handler(struct sk_buff *skb, int hwtstamp_type,
60 struct mlx5e_ptp_cq_stats *cq_stats)
62 switch (hwtstamp_type) {
63 case (MLX5E_SKB_CB_CQE_HWTSTAMP):
64 mlx5e_skb_cb_get_hwts(skb)->cqe_hwtstamp = hwtstamp;
66 case (MLX5E_SKB_CB_PORT_HWTSTAMP):
67 mlx5e_skb_cb_get_hwts(skb)->port_hwtstamp = hwtstamp;
71 /* If both CQEs arrive, check and report the port tstamp, and clear skb cb as
72 * skb soon to be released.
74 if (!mlx5e_skb_cb_get_hwts(skb)->cqe_hwtstamp ||
75 !mlx5e_skb_cb_get_hwts(skb)->port_hwtstamp)
78 mlx5e_skb_cb_hwtstamp_tx(skb, cq_stats);
79 memset(skb->cb, 0, sizeof(struct mlx5e_skb_cb_hwtstamp));
82 static void mlx5e_ptp_handle_ts_cqe(struct mlx5e_ptpsq *ptpsq,
83 struct mlx5_cqe64 *cqe,
86 struct sk_buff *skb = mlx5e_skb_fifo_pop(&ptpsq->skb_fifo);
87 struct mlx5e_txqsq *sq = &ptpsq->txqsq;
90 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
91 ptpsq->cq_stats->err_cqe++;
95 hwtstamp = mlx5e_cqe_ts_to_ns(sq->ptp_cyc2time, sq->clock, get_cqe_ts(cqe));
96 mlx5e_skb_cb_hwtstamp_handler(skb, MLX5E_SKB_CB_PORT_HWTSTAMP,
97 hwtstamp, ptpsq->cq_stats);
98 ptpsq->cq_stats->cqe++;
101 napi_consume_skb(skb, budget);
104 static bool mlx5e_ptp_poll_ts_cq(struct mlx5e_cq *cq, int budget)
106 struct mlx5e_ptpsq *ptpsq = container_of(cq, struct mlx5e_ptpsq, ts_cq);
107 struct mlx5_cqwq *cqwq = &cq->wq;
108 struct mlx5_cqe64 *cqe;
111 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &ptpsq->txqsq.state)))
114 cqe = mlx5_cqwq_get_cqe(cqwq);
121 mlx5e_ptp_handle_ts_cqe(ptpsq, cqe, budget);
122 } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(cqwq)));
124 mlx5_cqwq_update_db_record(cqwq);
126 /* ensure cq space is freed before enabling more cqes */
129 return work_done == budget;
132 static int mlx5e_ptp_napi_poll(struct napi_struct *napi, int budget)
134 struct mlx5e_ptp *c = container_of(napi, struct mlx5e_ptp, napi);
135 struct mlx5e_ch_stats *ch_stats = c->stats;
136 struct mlx5e_rq *rq = &c->rq;
145 if (test_bit(MLX5E_PTP_STATE_TX, c->state)) {
146 for (i = 0; i < c->num_tc; i++) {
147 busy |= mlx5e_poll_tx_cq(&c->ptpsq[i].txqsq.cq, budget);
148 busy |= mlx5e_ptp_poll_ts_cq(&c->ptpsq[i].ts_cq, budget);
151 if (test_bit(MLX5E_PTP_STATE_RX, c->state) && likely(budget)) {
152 work_done = mlx5e_poll_rx_cq(&rq->cq, budget);
153 busy |= work_done == budget;
154 busy |= INDIRECT_CALL_2(rq->post_wqes,
155 mlx5e_post_rx_mpwqes,
165 if (unlikely(!napi_complete_done(napi, work_done)))
170 if (test_bit(MLX5E_PTP_STATE_TX, c->state)) {
171 for (i = 0; i < c->num_tc; i++) {
172 mlx5e_cq_arm(&c->ptpsq[i].txqsq.cq);
173 mlx5e_cq_arm(&c->ptpsq[i].ts_cq);
176 if (test_bit(MLX5E_PTP_STATE_RX, c->state))
177 mlx5e_cq_arm(&rq->cq);
185 static int mlx5e_ptp_alloc_txqsq(struct mlx5e_ptp *c, int txq_ix,
186 struct mlx5e_params *params,
187 struct mlx5e_sq_param *param,
188 struct mlx5e_txqsq *sq, int tc,
189 struct mlx5e_ptpsq *ptpsq)
191 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
192 struct mlx5_core_dev *mdev = c->mdev;
193 struct mlx5_wq_cyc *wq = &sq->wq;
198 sq->tstamp = c->tstamp;
199 sq->clock = &mdev->clock;
200 sq->mkey_be = c->mkey_be;
201 sq->netdev = c->netdev;
204 sq->ch_ix = MLX5E_PTP_CHANNEL_IX;
206 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map;
207 sq->min_inline_mode = params->tx_min_inline_mode;
208 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
209 sq->stats = &c->priv->ptp_stats.sq[tc];
211 INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
212 if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
213 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
214 sq->stop_room = param->stop_room;
215 sq->ptp_cyc2time = mlx5_sq_ts_translator(mdev);
217 node = dev_to_node(mlx5_core_dma_dev(mdev));
219 param->wq.db_numa_node = node;
220 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
223 wq->db = &wq->db[MLX5_SND_DBR];
225 err = mlx5e_alloc_txqsq_db(sq, node);
227 goto err_sq_wq_destroy;
232 mlx5_wq_destroy(&sq->wq_ctrl);
237 static void mlx5e_ptp_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
239 mlx5_core_destroy_sq(mdev, sqn);
242 static int mlx5e_ptp_alloc_traffic_db(struct mlx5e_ptpsq *ptpsq, int numa)
244 int wq_sz = mlx5_wq_cyc_get_size(&ptpsq->txqsq.wq);
246 ptpsq->skb_fifo.fifo = kvzalloc_node(array_size(wq_sz, sizeof(*ptpsq->skb_fifo.fifo)),
248 if (!ptpsq->skb_fifo.fifo)
251 ptpsq->skb_fifo.pc = &ptpsq->skb_fifo_pc;
252 ptpsq->skb_fifo.cc = &ptpsq->skb_fifo_cc;
253 ptpsq->skb_fifo.mask = wq_sz - 1;
258 static void mlx5e_ptp_drain_skb_fifo(struct mlx5e_skb_fifo *skb_fifo)
260 while (*skb_fifo->pc != *skb_fifo->cc) {
261 struct sk_buff *skb = mlx5e_skb_fifo_pop(skb_fifo);
263 dev_kfree_skb_any(skb);
267 static void mlx5e_ptp_free_traffic_db(struct mlx5e_skb_fifo *skb_fifo)
269 mlx5e_ptp_drain_skb_fifo(skb_fifo);
270 kvfree(skb_fifo->fifo);
273 static int mlx5e_ptp_open_txqsq(struct mlx5e_ptp *c, u32 tisn,
274 int txq_ix, struct mlx5e_ptp_params *cparams,
275 int tc, struct mlx5e_ptpsq *ptpsq)
277 struct mlx5e_sq_param *sqp = &cparams->txq_sq_param;
278 struct mlx5e_txqsq *txqsq = &ptpsq->txqsq;
279 struct mlx5e_create_sq_param csp = {};
282 err = mlx5e_ptp_alloc_txqsq(c, txq_ix, &cparams->params, sqp,
289 csp.cqn = txqsq->cq.mcq.cqn;
290 csp.wq_ctrl = &txqsq->wq_ctrl;
291 csp.min_inline_mode = txqsq->min_inline_mode;
292 csp.ts_cqe_to_dest_cqn = ptpsq->ts_cq.mcq.cqn;
294 err = mlx5e_create_sq_rdy(c->mdev, sqp, &csp, 0, &txqsq->sqn);
298 err = mlx5e_ptp_alloc_traffic_db(ptpsq,
299 dev_to_node(mlx5_core_dma_dev(c->mdev)));
306 mlx5e_free_txqsq(txqsq);
311 static void mlx5e_ptp_close_txqsq(struct mlx5e_ptpsq *ptpsq)
313 struct mlx5e_txqsq *sq = &ptpsq->txqsq;
314 struct mlx5_core_dev *mdev = sq->mdev;
316 mlx5e_ptp_free_traffic_db(&ptpsq->skb_fifo);
317 cancel_work_sync(&sq->recover_work);
318 mlx5e_ptp_destroy_sq(mdev, sq->sqn);
319 mlx5e_free_txqsq_descs(sq);
320 mlx5e_free_txqsq(sq);
323 static int mlx5e_ptp_open_txqsqs(struct mlx5e_ptp *c,
324 struct mlx5e_ptp_params *cparams)
326 struct mlx5e_params *params = &cparams->params;
327 u8 num_tc = mlx5e_get_dcb_num_tc(params);
332 ix_base = num_tc * params->num_channels;
334 for (tc = 0; tc < num_tc; tc++) {
335 int txq_ix = ix_base + tc;
337 err = mlx5e_ptp_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
338 cparams, tc, &c->ptpsq[tc]);
346 for (--tc; tc >= 0; tc--)
347 mlx5e_ptp_close_txqsq(&c->ptpsq[tc]);
352 static void mlx5e_ptp_close_txqsqs(struct mlx5e_ptp *c)
356 for (tc = 0; tc < c->num_tc; tc++)
357 mlx5e_ptp_close_txqsq(&c->ptpsq[tc]);
360 static int mlx5e_ptp_open_tx_cqs(struct mlx5e_ptp *c,
361 struct mlx5e_ptp_params *cparams)
363 struct mlx5e_params *params = &cparams->params;
364 struct mlx5e_create_cq_param ccp = {};
365 struct dim_cq_moder ptp_moder = {};
366 struct mlx5e_cq_param *cq_param;
371 num_tc = mlx5e_get_dcb_num_tc(params);
373 ccp.node = dev_to_node(mlx5_core_dma_dev(c->mdev));
374 ccp.ch_stats = c->stats;
376 ccp.ix = MLX5E_PTP_CHANNEL_IX;
378 cq_param = &cparams->txq_sq_param.cqp;
380 for (tc = 0; tc < num_tc; tc++) {
381 struct mlx5e_cq *cq = &c->ptpsq[tc].txqsq.cq;
383 err = mlx5e_open_cq(c->priv, ptp_moder, cq_param, &ccp, cq);
385 goto out_err_txqsq_cq;
388 for (tc = 0; tc < num_tc; tc++) {
389 struct mlx5e_cq *cq = &c->ptpsq[tc].ts_cq;
390 struct mlx5e_ptpsq *ptpsq = &c->ptpsq[tc];
392 err = mlx5e_open_cq(c->priv, ptp_moder, cq_param, &ccp, cq);
396 ptpsq->cq_stats = &c->priv->ptp_stats.cq[tc];
402 for (--tc; tc >= 0; tc--)
403 mlx5e_close_cq(&c->ptpsq[tc].ts_cq);
406 for (--tc; tc >= 0; tc--)
407 mlx5e_close_cq(&c->ptpsq[tc].txqsq.cq);
412 static int mlx5e_ptp_open_rx_cq(struct mlx5e_ptp *c,
413 struct mlx5e_ptp_params *cparams)
415 struct mlx5e_create_cq_param ccp = {};
416 struct dim_cq_moder ptp_moder = {};
417 struct mlx5e_cq_param *cq_param;
418 struct mlx5e_cq *cq = &c->rq.cq;
420 ccp.node = dev_to_node(mlx5_core_dma_dev(c->mdev));
421 ccp.ch_stats = c->stats;
423 ccp.ix = MLX5E_PTP_CHANNEL_IX;
425 cq_param = &cparams->rq_param.cqp;
427 return mlx5e_open_cq(c->priv, ptp_moder, cq_param, &ccp, cq);
430 static void mlx5e_ptp_close_tx_cqs(struct mlx5e_ptp *c)
434 for (tc = 0; tc < c->num_tc; tc++)
435 mlx5e_close_cq(&c->ptpsq[tc].ts_cq);
437 for (tc = 0; tc < c->num_tc; tc++)
438 mlx5e_close_cq(&c->ptpsq[tc].txqsq.cq);
441 static void mlx5e_ptp_build_sq_param(struct mlx5_core_dev *mdev,
442 struct mlx5e_params *params,
443 struct mlx5e_sq_param *param)
445 void *sqc = param->sqc;
448 mlx5e_build_sq_param_common(mdev, param);
450 wq = MLX5_ADDR_OF(sqc, sqc, wq);
451 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
452 param->stop_room = mlx5e_stop_room_for_wqe(MLX5_SEND_WQE_MAX_WQEBBS);
453 mlx5e_build_tx_cq_param(mdev, params, ¶m->cqp);
456 static void mlx5e_ptp_build_rq_param(struct mlx5_core_dev *mdev,
457 struct net_device *netdev,
459 struct mlx5e_ptp_params *ptp_params)
461 struct mlx5e_rq_param *rq_params = &ptp_params->rq_param;
462 struct mlx5e_params *params = &ptp_params->params;
464 params->rq_wq_type = MLX5_WQ_TYPE_CYCLIC;
465 mlx5e_init_rq_type_params(mdev, params);
466 params->sw_mtu = netdev->max_mtu;
467 mlx5e_build_rq_param(mdev, params, NULL, q_counter, rq_params);
470 static void mlx5e_ptp_build_params(struct mlx5e_ptp *c,
471 struct mlx5e_ptp_params *cparams,
472 struct mlx5e_params *orig)
474 struct mlx5e_params *params = &cparams->params;
476 params->tx_min_inline_mode = orig->tx_min_inline_mode;
477 params->num_channels = orig->num_channels;
478 params->hard_mtu = orig->hard_mtu;
479 params->sw_mtu = orig->sw_mtu;
480 params->mqprio = orig->mqprio;
483 if (test_bit(MLX5E_PTP_STATE_TX, c->state)) {
484 params->log_sq_size = orig->log_sq_size;
485 mlx5e_ptp_build_sq_param(c->mdev, params, &cparams->txq_sq_param);
488 if (test_bit(MLX5E_PTP_STATE_RX, c->state)) {
489 params->vlan_strip_disable = orig->vlan_strip_disable;
490 mlx5e_ptp_build_rq_param(c->mdev, c->netdev, c->priv->q_counter, cparams);
494 static int mlx5e_init_ptp_rq(struct mlx5e_ptp *c, struct mlx5e_params *params,
497 struct mlx5_core_dev *mdev = c->mdev;
498 struct mlx5e_priv *priv = c->priv;
501 rq->wq_type = params->rq_wq_type;
503 rq->netdev = priv->netdev;
505 rq->clock = &mdev->clock;
506 rq->tstamp = &priv->tstamp;
508 rq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
509 rq->stats = &c->priv->ptp_stats.rq;
510 rq->ix = MLX5E_PTP_CHANNEL_IX;
511 rq->ptp_cyc2time = mlx5_rq_ts_translator(mdev);
512 err = mlx5e_rq_set_handlers(rq, params, false);
516 return xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix, 0);
519 static int mlx5e_ptp_open_rq(struct mlx5e_ptp *c, struct mlx5e_params *params,
520 struct mlx5e_rq_param *rq_param)
522 int node = dev_to_node(c->mdev->device);
525 err = mlx5e_init_ptp_rq(c, params, &c->rq);
529 return mlx5e_open_rq(params, rq_param, NULL, node, &c->rq);
532 static int mlx5e_ptp_open_queues(struct mlx5e_ptp *c,
533 struct mlx5e_ptp_params *cparams)
537 if (test_bit(MLX5E_PTP_STATE_TX, c->state)) {
538 err = mlx5e_ptp_open_tx_cqs(c, cparams);
542 err = mlx5e_ptp_open_txqsqs(c, cparams);
546 if (test_bit(MLX5E_PTP_STATE_RX, c->state)) {
547 err = mlx5e_ptp_open_rx_cq(c, cparams);
551 err = mlx5e_ptp_open_rq(c, &cparams->params, &cparams->rq_param);
558 if (test_bit(MLX5E_PTP_STATE_RX, c->state))
559 mlx5e_close_cq(&c->rq.cq);
561 if (test_bit(MLX5E_PTP_STATE_TX, c->state))
562 mlx5e_ptp_close_txqsqs(c);
564 if (test_bit(MLX5E_PTP_STATE_TX, c->state))
565 mlx5e_ptp_close_tx_cqs(c);
570 static void mlx5e_ptp_close_queues(struct mlx5e_ptp *c)
572 if (test_bit(MLX5E_PTP_STATE_RX, c->state)) {
573 mlx5e_close_rq(&c->rq);
574 mlx5e_close_cq(&c->rq.cq);
576 if (test_bit(MLX5E_PTP_STATE_TX, c->state)) {
577 mlx5e_ptp_close_txqsqs(c);
578 mlx5e_ptp_close_tx_cqs(c);
582 static int mlx5e_ptp_set_state(struct mlx5e_ptp *c, struct mlx5e_params *params)
584 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_TX_PORT_TS))
585 __set_bit(MLX5E_PTP_STATE_TX, c->state);
588 __set_bit(MLX5E_PTP_STATE_RX, c->state);
590 return bitmap_empty(c->state, MLX5E_PTP_STATE_NUM_STATES) ? -EINVAL : 0;
593 static void mlx5e_ptp_rx_unset_fs(struct mlx5e_priv *priv)
595 struct mlx5e_ptp_fs *ptp_fs = priv->fs.ptp_fs;
600 mlx5e_fs_tt_redirect_del_rule(ptp_fs->l2_rule);
601 mlx5e_fs_tt_redirect_any_destroy(priv);
603 mlx5e_fs_tt_redirect_del_rule(ptp_fs->udp_v6_rule);
604 mlx5e_fs_tt_redirect_del_rule(ptp_fs->udp_v4_rule);
605 mlx5e_fs_tt_redirect_udp_destroy(priv);
606 ptp_fs->valid = false;
609 static int mlx5e_ptp_rx_set_fs(struct mlx5e_priv *priv)
611 u32 tirn = mlx5e_rx_res_get_tirn_ptp(priv->rx_res);
612 struct mlx5e_ptp_fs *ptp_fs = priv->fs.ptp_fs;
613 struct mlx5_flow_handle *rule;
619 err = mlx5e_fs_tt_redirect_udp_create(priv);
623 rule = mlx5e_fs_tt_redirect_udp_add_rule(priv, MLX5_TT_IPV4_UDP,
627 goto out_destroy_fs_udp;
629 ptp_fs->udp_v4_rule = rule;
631 rule = mlx5e_fs_tt_redirect_udp_add_rule(priv, MLX5_TT_IPV6_UDP,
635 goto out_destroy_udp_v4_rule;
637 ptp_fs->udp_v6_rule = rule;
639 err = mlx5e_fs_tt_redirect_any_create(priv);
641 goto out_destroy_udp_v6_rule;
643 rule = mlx5e_fs_tt_redirect_any_add_rule(priv, tirn, ETH_P_1588);
646 goto out_destroy_fs_any;
648 ptp_fs->l2_rule = rule;
649 ptp_fs->valid = true;
654 mlx5e_fs_tt_redirect_any_destroy(priv);
655 out_destroy_udp_v6_rule:
656 mlx5e_fs_tt_redirect_del_rule(ptp_fs->udp_v6_rule);
657 out_destroy_udp_v4_rule:
658 mlx5e_fs_tt_redirect_del_rule(ptp_fs->udp_v4_rule);
660 mlx5e_fs_tt_redirect_udp_destroy(priv);
665 int mlx5e_ptp_open(struct mlx5e_priv *priv, struct mlx5e_params *params,
666 u8 lag_port, struct mlx5e_ptp **cp)
668 struct net_device *netdev = priv->netdev;
669 struct mlx5_core_dev *mdev = priv->mdev;
670 struct mlx5e_ptp_params *cparams;
675 c = kvzalloc_node(sizeof(*c), GFP_KERNEL, dev_to_node(mlx5_core_dma_dev(mdev)));
676 cparams = kvzalloc(sizeof(*cparams), GFP_KERNEL);
681 c->mdev = priv->mdev;
682 c->tstamp = &priv->tstamp;
683 c->pdev = mlx5_core_dma_dev(priv->mdev);
684 c->netdev = priv->netdev;
685 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.hw_objs.mkey.key);
686 c->num_tc = mlx5e_get_dcb_num_tc(params);
687 c->stats = &priv->ptp_stats.ch;
688 c->lag_port = lag_port;
690 err = mlx5e_ptp_set_state(c, params);
694 netif_napi_add(netdev, &c->napi, mlx5e_ptp_napi_poll, 64);
696 mlx5e_ptp_build_params(c, cparams, params);
698 err = mlx5e_ptp_open_queues(c, cparams);
702 if (test_bit(MLX5E_PTP_STATE_RX, c->state))
703 priv->rx_ptp_opened = true;
712 netif_napi_del(&c->napi);
719 void mlx5e_ptp_close(struct mlx5e_ptp *c)
721 mlx5e_ptp_close_queues(c);
722 netif_napi_del(&c->napi);
727 void mlx5e_ptp_activate_channel(struct mlx5e_ptp *c)
731 napi_enable(&c->napi);
733 if (test_bit(MLX5E_PTP_STATE_TX, c->state)) {
734 for (tc = 0; tc < c->num_tc; tc++)
735 mlx5e_activate_txqsq(&c->ptpsq[tc].txqsq);
737 if (test_bit(MLX5E_PTP_STATE_RX, c->state)) {
738 mlx5e_ptp_rx_set_fs(c->priv);
739 mlx5e_activate_rq(&c->rq);
743 void mlx5e_ptp_deactivate_channel(struct mlx5e_ptp *c)
747 if (test_bit(MLX5E_PTP_STATE_RX, c->state))
748 mlx5e_deactivate_rq(&c->rq);
750 if (test_bit(MLX5E_PTP_STATE_TX, c->state)) {
751 for (tc = 0; tc < c->num_tc; tc++)
752 mlx5e_deactivate_txqsq(&c->ptpsq[tc].txqsq);
755 napi_disable(&c->napi);
758 int mlx5e_ptp_get_rqn(struct mlx5e_ptp *c, u32 *rqn)
760 if (!c || !test_bit(MLX5E_PTP_STATE_RX, c->state))
767 int mlx5e_ptp_alloc_rx_fs(struct mlx5e_priv *priv)
769 struct mlx5e_ptp_fs *ptp_fs;
771 if (!priv->profile->rx_ptp_support)
774 ptp_fs = kzalloc(sizeof(*ptp_fs), GFP_KERNEL);
778 priv->fs.ptp_fs = ptp_fs;
782 void mlx5e_ptp_free_rx_fs(struct mlx5e_priv *priv)
784 struct mlx5e_ptp_fs *ptp_fs = priv->fs.ptp_fs;
786 if (!priv->profile->rx_ptp_support)
789 mlx5e_ptp_rx_unset_fs(priv);
793 int mlx5e_ptp_rx_manage_fs(struct mlx5e_priv *priv, bool set)
795 struct mlx5e_ptp *c = priv->channels.ptp;
797 if (!priv->profile->rx_ptp_support)
800 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
804 if (!c || !test_bit(MLX5E_PTP_STATE_RX, c->state)) {
805 netdev_WARN_ONCE(priv->netdev, "Don't try to add PTP RX-FS rules");
808 return mlx5e_ptp_rx_set_fs(priv);
811 if (c && test_bit(MLX5E_PTP_STATE_RX, c->state)) {
812 netdev_WARN_ONCE(priv->netdev, "Don't try to remove PTP RX-FS rules");
815 mlx5e_ptp_rx_unset_fs(priv);