2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 #include <linux/bitops.h>
38 #include <linux/compiler.h>
39 #include <linux/list.h>
40 #include <linux/mutex.h>
41 #include <linux/netdevice.h>
42 #include <linux/if_vlan.h>
43 #ifdef CONFIG_MLX4_EN_DCB
44 #include <linux/dcbnl.h>
47 #include <linux/mlx4/device.h>
48 #include <linux/mlx4/qp.h>
49 #include <linux/mlx4/cq.h>
50 #include <linux/mlx4/srq.h>
51 #include <linux/mlx4/doorbell.h>
52 #include <linux/mlx4/cmd.h>
56 #define DRV_NAME "mlx4_en"
57 #define DRV_VERSION "2.0"
58 #define DRV_RELDATE "Dec 2011"
60 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
67 #define MLX4_EN_PAGE_SHIFT 12
68 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
69 #define MAX_RX_RINGS 16
70 #define MIN_RX_RINGS 4
72 #define HEADROOM (2048 / TXBB_SIZE + 1)
73 #define STAMP_STRIDE 64
74 #define STAMP_DWORDS (STAMP_STRIDE / 4)
75 #define STAMP_SHIFT 31
76 #define STAMP_VAL 0x7fffffff
77 #define STATS_DELAY (HZ / 4)
78 #define MAX_NUM_OF_FS_RULES 256
80 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
81 #define MAX_DESC_SIZE 512
82 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
85 * OS related constants and tunables
88 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
90 /* Use the maximum between 16384 and a single page */
91 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384)
92 #define MLX4_EN_ALLOC_ORDER get_order(MLX4_EN_ALLOC_SIZE)
94 #define MLX4_EN_MAX_LRO_DESCRIPTORS 32
96 /* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
97 * and 4K allocations) */
99 FRAG_SZ0 = 512 - NET_IP_ALIGN,
102 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
104 #define MLX4_EN_MAX_RX_FRAGS 4
106 /* Maximum ring sizes */
107 #define MLX4_EN_MAX_TX_SIZE 8192
108 #define MLX4_EN_MAX_RX_SIZE 8192
110 /* Minimum ring size for our page-allocation sceme to work */
111 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
112 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
114 #define MLX4_EN_SMALL_PKT_SIZE 64
115 #define MLX4_EN_MAX_TX_RING_P_UP 32
116 #define MLX4_EN_NUM_UP 8
117 #define MLX4_EN_DEF_TX_RING_SIZE 512
118 #define MLX4_EN_DEF_RX_RING_SIZE 1024
120 /* Target number of packets to coalesce with interrupt moderation */
121 #define MLX4_EN_RX_COAL_TARGET 44
122 #define MLX4_EN_RX_COAL_TIME 0x10
124 #define MLX4_EN_TX_COAL_PKTS 16
125 #define MLX4_EN_TX_COAL_TIME 0x80
127 #define MLX4_EN_RX_RATE_LOW 400000
128 #define MLX4_EN_RX_COAL_TIME_LOW 0
129 #define MLX4_EN_RX_RATE_HIGH 450000
130 #define MLX4_EN_RX_COAL_TIME_HIGH 128
131 #define MLX4_EN_RX_SIZE_THRESH 1024
132 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
133 #define MLX4_EN_SAMPLE_INTERVAL 0
134 #define MLX4_EN_AVG_PKT_SMALL 256
136 #define MLX4_EN_AUTO_CONF 0xffff
138 #define MLX4_EN_DEF_RX_PAUSE 1
139 #define MLX4_EN_DEF_TX_PAUSE 1
141 /* Interval between successive polls in the Tx routine when polling is used
142 instead of interrupts (in per-core Tx rings) - should be power of 2 */
143 #define MLX4_EN_TX_POLL_MODER 16
144 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
146 #define ETH_LLC_SNAP_SIZE 8
148 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
149 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
150 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
152 #define MLX4_EN_MIN_MTU 46
153 #define ETH_BCAST 0xffffffffffffULL
155 #define MLX4_EN_LOOPBACK_RETRIES 5
156 #define MLX4_EN_LOOPBACK_TIMEOUT 100
158 #ifdef MLX4_EN_PERF_STAT
159 /* Number of samples to 'average' */
161 #define AVG_FACTOR 1024
162 #define NUM_PERF_STATS NUM_PERF_COUNTERS
164 #define INC_PERF_COUNTER(cnt) (++(cnt))
165 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
166 #define AVG_PERF_COUNTER(cnt, sample) \
167 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
168 #define GET_PERF_COUNTER(cnt) (cnt)
169 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
173 #define NUM_PERF_STATS 0
174 #define INC_PERF_COUNTER(cnt) do {} while (0)
175 #define ADD_PERF_COUNTER(cnt, add) do {} while (0)
176 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
177 #define GET_PERF_COUNTER(cnt) (0)
178 #define GET_AVG_PERF_COUNTER(cnt) (0)
179 #endif /* MLX4_EN_PERF_STAT */
194 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
195 #define XNOR(x, y) (!(x) == !(y))
196 #define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL || addr == 0x0)
199 struct mlx4_en_tx_info {
209 #define MLX4_EN_BIT_DESC_OWN 0x80000000
210 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
211 #define MLX4_EN_MEMTYPE_PAD 0x100
212 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
215 struct mlx4_en_tx_desc {
216 struct mlx4_wqe_ctrl_seg ctrl;
218 struct mlx4_wqe_data_seg data; /* at least one data segment */
219 struct mlx4_wqe_lso_seg lso;
220 struct mlx4_wqe_inline_seg inl;
224 #define MLX4_EN_USE_SRQ 0x01000000
226 #define MLX4_EN_CX3_LOW_ID 0x1000
227 #define MLX4_EN_CX3_HIGH_ID 0x1005
229 struct mlx4_en_rx_alloc {
234 struct mlx4_en_tx_ring {
235 struct mlx4_hwq_resources wqres;
236 u32 size ; /* number of TXBBs */
239 u16 cqn; /* index of port CQ associated with this ring */
247 struct mlx4_en_tx_info *tx_info;
251 struct mlx4_qp_context context;
253 enum mlx4_qp_state qp_state;
254 struct mlx4_srq dummy;
256 unsigned long packets;
257 unsigned long tx_csum;
260 struct netdev_queue *tx_queue;
263 struct mlx4_en_rx_desc {
264 /* actual number of entries depends on rx ring stride */
265 struct mlx4_wqe_data_seg data[0];
268 struct mlx4_en_rx_ring {
269 struct mlx4_hwq_resources wqres;
270 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
271 u32 size ; /* number of Rx descs*/
276 u16 cqn; /* index of port CQ associated with this ring */
284 unsigned long packets;
285 unsigned long csum_ok;
286 unsigned long csum_none;
290 static inline int mlx4_en_can_lro(__be16 status)
292 return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
293 MLX4_CQE_STATUS_IPV4F |
294 MLX4_CQE_STATUS_IPV6 |
295 MLX4_CQE_STATUS_IPV4OPT |
296 MLX4_CQE_STATUS_TCP |
297 MLX4_CQE_STATUS_UDP |
298 MLX4_CQE_STATUS_IPOK)) ==
299 cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
300 MLX4_CQE_STATUS_IPOK |
301 MLX4_CQE_STATUS_TCP);
306 struct mlx4_hwq_resources wqres;
309 struct net_device *dev;
310 struct napi_struct napi;
317 struct mlx4_cqe *buf;
318 #define MLX4_EN_OPCODE_ERROR 0x1e
321 struct mlx4_en_port_profile {
334 struct mlx4_en_profile {
341 u8 num_tx_rings_p_up;
342 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
346 struct mlx4_dev *dev;
347 struct pci_dev *pdev;
348 struct mutex state_lock;
349 struct net_device *pndev[MLX4_MAX_PORTS + 1];
352 struct mlx4_en_profile profile;
354 struct workqueue_struct *workqueue;
355 struct device *dma_device;
356 void __iomem *uar_map;
357 struct mlx4_uar priv_uar;
361 u8 mac_removed[MLX4_MAX_PORTS + 1];
365 struct mlx4_en_rss_map {
367 struct mlx4_qp qps[MAX_RX_RINGS];
368 enum mlx4_qp_state state[MAX_RX_RINGS];
369 struct mlx4_qp indir_qp;
370 enum mlx4_qp_state indir_state;
373 struct mlx4_en_port_state {
379 struct mlx4_en_pkt_stats {
380 unsigned long broadcast;
381 unsigned long rx_prio[8];
382 unsigned long tx_prio[8];
383 #define NUM_PKT_STATS 17
386 struct mlx4_en_port_stats {
387 unsigned long tso_packets;
388 unsigned long queue_stopped;
389 unsigned long wake_queue;
390 unsigned long tx_timeout;
391 unsigned long rx_alloc_failed;
392 unsigned long rx_chksum_good;
393 unsigned long rx_chksum_none;
394 unsigned long tx_chksum_offload;
395 #define NUM_PORT_STATS 8
398 struct mlx4_en_perf_stats {
405 #define NUM_PERF_COUNTERS 6
408 enum mlx4_en_mclist_act {
414 struct mlx4_en_mc_list {
415 struct list_head list;
416 enum mlx4_en_mclist_act action;
421 struct mlx4_en_frag_info {
423 u16 frag_prefix_size;
430 #ifdef CONFIG_MLX4_EN_DCB
431 /* Minimal TC BW - setting to 0 will block traffic */
432 #define MLX4_EN_BW_MIN 1
433 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
435 #define MLX4_EN_TC_ETS 7
439 struct ethtool_flow_id {
440 struct ethtool_rx_flow_spec flow_spec;
444 struct mlx4_en_priv {
445 struct mlx4_en_dev *mdev;
446 struct mlx4_en_port_profile *prof;
447 struct net_device *dev;
448 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
449 struct net_device_stats stats;
450 struct net_device_stats ret_stats;
451 struct mlx4_en_port_state port_state;
452 spinlock_t stats_lock;
453 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
455 unsigned long last_moder_packets[MAX_RX_RINGS];
456 unsigned long last_moder_tx_packets;
457 unsigned long last_moder_bytes[MAX_RX_RINGS];
458 unsigned long last_moder_jiffies;
459 int last_moder_time[MAX_RX_RINGS];
469 u16 adaptive_rx_coal;
472 u32 validate_loopback;
474 struct mlx4_hwq_resources res;
487 struct mlx4_en_rss_map rss_map;
490 #define MLX4_EN_FLAG_PROMISC 0x1
491 #define MLX4_EN_FLAG_MC_PROMISC 0x2
495 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
499 struct mlx4_en_tx_ring *tx_ring;
500 struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
501 struct mlx4_en_cq *tx_cq;
502 struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
503 struct work_struct mcast_task;
504 struct work_struct mac_task;
505 struct work_struct watchdog_task;
506 struct work_struct linkstate_task;
507 struct delayed_work stats_task;
508 struct mlx4_en_perf_stats pstats;
509 struct mlx4_en_pkt_stats pkstats;
510 struct mlx4_en_port_stats port_stats;
512 struct list_head mc_list;
513 struct list_head curr_list;
515 struct mlx4_en_stat_out_mbox hw_stats;
521 #ifdef CONFIG_MLX4_EN_DCB
523 u16 maxrate[IEEE_8021QAZ_MAX_TCS];
528 MLX4_EN_WOL_MAGIC = (1ULL << 61),
529 MLX4_EN_WOL_ENABLED = (1ULL << 62),
532 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
534 void mlx4_en_destroy_netdev(struct net_device *dev);
535 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
536 struct mlx4_en_port_profile *prof);
538 int mlx4_en_start_port(struct net_device *dev);
539 void mlx4_en_stop_port(struct net_device *dev);
541 void mlx4_en_free_resources(struct mlx4_en_priv *priv);
542 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
544 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
545 int entries, int ring, enum cq_type mode);
546 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
547 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
549 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
550 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
551 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
553 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
554 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb);
555 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
557 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring,
558 int qpn, u32 size, u16 stride);
559 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring);
560 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
561 struct mlx4_en_tx_ring *ring,
562 int cq, int user_prio);
563 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
564 struct mlx4_en_tx_ring *ring);
566 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
567 struct mlx4_en_rx_ring *ring,
568 u32 size, u16 stride);
569 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
570 struct mlx4_en_rx_ring *ring,
571 u32 size, u16 stride);
572 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
573 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
574 struct mlx4_en_rx_ring *ring);
575 int mlx4_en_process_rx_cq(struct net_device *dev,
576 struct mlx4_en_cq *cq,
578 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
579 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
580 int is_tx, int rss, int qpn, int cqn, int user_prio,
581 struct mlx4_qp_context *context);
582 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
583 int mlx4_en_map_buffer(struct mlx4_buf *buf);
584 void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
586 void mlx4_en_calc_rx_buf(struct net_device *dev);
587 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
588 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
589 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
590 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
592 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
593 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
595 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
596 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
598 #ifdef CONFIG_MLX4_EN_DCB
599 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
602 #define MLX4_EN_NUM_SELF_TEST 5
603 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
604 u64 mlx4_en_mac_to_u64(u8 *addr);
609 extern const struct ethtool_ops mlx4_en_ethtool_ops;
614 * printk / logging functions
618 int en_print(const char *level, const struct mlx4_en_priv *priv,
619 const char *format, ...);
621 #define en_dbg(mlevel, priv, format, arg...) \
623 if (NETIF_MSG_##mlevel & priv->msg_enable) \
624 en_print(KERN_DEBUG, priv, format, ##arg); \
626 #define en_warn(priv, format, arg...) \
627 en_print(KERN_WARNING, priv, format, ##arg)
628 #define en_err(priv, format, arg...) \
629 en_print(KERN_ERR, priv, format, ##arg)
630 #define en_info(priv, format, arg...) \
631 en_print(KERN_INFO, priv, format, ## arg)
633 #define mlx4_err(mdev, format, arg...) \
634 pr_err("%s %s: " format, DRV_NAME, \
635 dev_name(&mdev->pdev->dev), ##arg)
636 #define mlx4_info(mdev, format, arg...) \
637 pr_info("%s %s: " format, DRV_NAME, \
638 dev_name(&mdev->pdev->dev), ##arg)
639 #define mlx4_warn(mdev, format, arg...) \
640 pr_warning("%s %s: " format, DRV_NAME, \
641 dev_name(&mdev->pdev->dev), ##arg)