2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 #include <linux/bitops.h>
38 #include <linux/compiler.h>
39 #include <linux/list.h>
40 #include <linux/mutex.h>
41 #include <linux/netdevice.h>
42 #include <linux/if_vlan.h>
43 #ifdef CONFIG_MLX4_EN_DCB
44 #include <linux/dcbnl.h>
46 #include <linux/cpu_rmap.h>
48 #include <linux/mlx4/device.h>
49 #include <linux/mlx4/qp.h>
50 #include <linux/mlx4/cq.h>
51 #include <linux/mlx4/srq.h>
52 #include <linux/mlx4/doorbell.h>
53 #include <linux/mlx4/cmd.h>
57 #define DRV_NAME "mlx4_en"
58 #define DRV_VERSION "2.0"
59 #define DRV_RELDATE "Dec 2011"
61 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
68 #define MLX4_EN_PAGE_SHIFT 12
69 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
70 #define MAX_RX_RINGS 16
71 #define MIN_RX_RINGS 4
73 #define HEADROOM (2048 / TXBB_SIZE + 1)
74 #define STAMP_STRIDE 64
75 #define STAMP_DWORDS (STAMP_STRIDE / 4)
76 #define STAMP_SHIFT 31
77 #define STAMP_VAL 0x7fffffff
78 #define STATS_DELAY (HZ / 4)
79 #define MAX_NUM_OF_FS_RULES 256
81 #define MLX4_EN_FILTER_HASH_SHIFT 4
82 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60
84 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
85 #define MAX_DESC_SIZE 512
86 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
89 * OS related constants and tunables
92 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
94 /* Use the maximum between 16384 and a single page */
95 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384)
96 #define MLX4_EN_ALLOC_ORDER get_order(MLX4_EN_ALLOC_SIZE)
98 #define MLX4_EN_MAX_LRO_DESCRIPTORS 32
100 /* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
101 * and 4K allocations) */
103 FRAG_SZ0 = 512 - NET_IP_ALIGN,
106 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
108 #define MLX4_EN_MAX_RX_FRAGS 4
110 /* Maximum ring sizes */
111 #define MLX4_EN_MAX_TX_SIZE 8192
112 #define MLX4_EN_MAX_RX_SIZE 8192
114 /* Minimum ring size for our page-allocation scheme to work */
115 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
116 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
118 #define MLX4_EN_SMALL_PKT_SIZE 64
119 #define MLX4_EN_MAX_TX_RING_P_UP 32
120 #define MLX4_EN_NUM_UP 8
121 #define MLX4_EN_DEF_TX_RING_SIZE 512
122 #define MLX4_EN_DEF_RX_RING_SIZE 1024
124 /* Target number of packets to coalesce with interrupt moderation */
125 #define MLX4_EN_RX_COAL_TARGET 44
126 #define MLX4_EN_RX_COAL_TIME 0x10
128 #define MLX4_EN_TX_COAL_PKTS 16
129 #define MLX4_EN_TX_COAL_TIME 0x80
131 #define MLX4_EN_RX_RATE_LOW 400000
132 #define MLX4_EN_RX_COAL_TIME_LOW 0
133 #define MLX4_EN_RX_RATE_HIGH 450000
134 #define MLX4_EN_RX_COAL_TIME_HIGH 128
135 #define MLX4_EN_RX_SIZE_THRESH 1024
136 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
137 #define MLX4_EN_SAMPLE_INTERVAL 0
138 #define MLX4_EN_AVG_PKT_SMALL 256
140 #define MLX4_EN_AUTO_CONF 0xffff
142 #define MLX4_EN_DEF_RX_PAUSE 1
143 #define MLX4_EN_DEF_TX_PAUSE 1
145 /* Interval between successive polls in the Tx routine when polling is used
146 instead of interrupts (in per-core Tx rings) - should be power of 2 */
147 #define MLX4_EN_TX_POLL_MODER 16
148 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
150 #define ETH_LLC_SNAP_SIZE 8
152 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
153 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
154 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
156 #define MLX4_EN_MIN_MTU 46
157 #define ETH_BCAST 0xffffffffffffULL
159 #define MLX4_EN_LOOPBACK_RETRIES 5
160 #define MLX4_EN_LOOPBACK_TIMEOUT 100
162 #ifdef MLX4_EN_PERF_STAT
163 /* Number of samples to 'average' */
165 #define AVG_FACTOR 1024
166 #define NUM_PERF_STATS NUM_PERF_COUNTERS
168 #define INC_PERF_COUNTER(cnt) (++(cnt))
169 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
170 #define AVG_PERF_COUNTER(cnt, sample) \
171 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
172 #define GET_PERF_COUNTER(cnt) (cnt)
173 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
177 #define NUM_PERF_STATS 0
178 #define INC_PERF_COUNTER(cnt) do {} while (0)
179 #define ADD_PERF_COUNTER(cnt, add) do {} while (0)
180 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
181 #define GET_PERF_COUNTER(cnt) (0)
182 #define GET_AVG_PERF_COUNTER(cnt) (0)
183 #endif /* MLX4_EN_PERF_STAT */
198 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
199 #define XNOR(x, y) (!(x) == !(y))
200 #define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL || addr == 0x0)
203 struct mlx4_en_tx_info {
213 #define MLX4_EN_BIT_DESC_OWN 0x80000000
214 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
215 #define MLX4_EN_MEMTYPE_PAD 0x100
216 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
219 struct mlx4_en_tx_desc {
220 struct mlx4_wqe_ctrl_seg ctrl;
222 struct mlx4_wqe_data_seg data; /* at least one data segment */
223 struct mlx4_wqe_lso_seg lso;
224 struct mlx4_wqe_inline_seg inl;
228 #define MLX4_EN_USE_SRQ 0x01000000
230 #define MLX4_EN_CX3_LOW_ID 0x1000
231 #define MLX4_EN_CX3_HIGH_ID 0x1005
233 struct mlx4_en_rx_alloc {
239 struct mlx4_en_tx_ring {
240 struct mlx4_hwq_resources wqres;
241 u32 size ; /* number of TXBBs */
244 u16 cqn; /* index of port CQ associated with this ring */
252 struct mlx4_en_tx_info *tx_info;
256 struct mlx4_qp_context context;
258 enum mlx4_qp_state qp_state;
259 struct mlx4_srq dummy;
261 unsigned long packets;
262 unsigned long tx_csum;
265 struct netdev_queue *tx_queue;
268 struct mlx4_en_rx_desc {
269 /* actual number of entries depends on rx ring stride */
270 struct mlx4_wqe_data_seg data[0];
273 struct mlx4_en_rx_ring {
274 struct mlx4_hwq_resources wqres;
275 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
276 u32 size ; /* number of Rx descs*/
281 u16 cqn; /* index of port CQ associated with this ring */
289 unsigned long packets;
290 unsigned long csum_ok;
291 unsigned long csum_none;
295 static inline int mlx4_en_can_lro(__be16 status)
297 return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
298 MLX4_CQE_STATUS_IPV4F |
299 MLX4_CQE_STATUS_IPV6 |
300 MLX4_CQE_STATUS_IPV4OPT |
301 MLX4_CQE_STATUS_TCP |
302 MLX4_CQE_STATUS_UDP |
303 MLX4_CQE_STATUS_IPOK)) ==
304 cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
305 MLX4_CQE_STATUS_IPOK |
306 MLX4_CQE_STATUS_TCP);
311 struct mlx4_hwq_resources wqres;
314 struct net_device *dev;
315 struct napi_struct napi;
322 struct mlx4_cqe *buf;
323 #define MLX4_EN_OPCODE_ERROR 0x1e
326 struct mlx4_en_port_profile {
339 struct mlx4_en_profile {
346 u8 num_tx_rings_p_up;
347 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
351 struct mlx4_dev *dev;
352 struct pci_dev *pdev;
353 struct mutex state_lock;
354 struct net_device *pndev[MLX4_MAX_PORTS + 1];
357 struct mlx4_en_profile profile;
359 struct workqueue_struct *workqueue;
360 struct device *dma_device;
361 void __iomem *uar_map;
362 struct mlx4_uar priv_uar;
366 u8 mac_removed[MLX4_MAX_PORTS + 1];
370 struct mlx4_en_rss_map {
372 struct mlx4_qp qps[MAX_RX_RINGS];
373 enum mlx4_qp_state state[MAX_RX_RINGS];
374 struct mlx4_qp indir_qp;
375 enum mlx4_qp_state indir_state;
378 struct mlx4_en_port_state {
384 struct mlx4_en_pkt_stats {
385 unsigned long broadcast;
386 unsigned long rx_prio[8];
387 unsigned long tx_prio[8];
388 #define NUM_PKT_STATS 17
391 struct mlx4_en_port_stats {
392 unsigned long tso_packets;
393 unsigned long queue_stopped;
394 unsigned long wake_queue;
395 unsigned long tx_timeout;
396 unsigned long rx_alloc_failed;
397 unsigned long rx_chksum_good;
398 unsigned long rx_chksum_none;
399 unsigned long tx_chksum_offload;
400 #define NUM_PORT_STATS 8
403 struct mlx4_en_perf_stats {
410 #define NUM_PERF_COUNTERS 6
413 enum mlx4_en_mclist_act {
419 struct mlx4_en_mc_list {
420 struct list_head list;
421 enum mlx4_en_mclist_act action;
426 struct mlx4_en_frag_info {
428 u16 frag_prefix_size;
435 #ifdef CONFIG_MLX4_EN_DCB
436 /* Minimal TC BW - setting to 0 will block traffic */
437 #define MLX4_EN_BW_MIN 1
438 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
440 #define MLX4_EN_TC_ETS 7
444 struct ethtool_flow_id {
445 struct ethtool_rx_flow_spec flow_spec;
449 struct mlx4_en_priv {
450 struct mlx4_en_dev *mdev;
451 struct mlx4_en_port_profile *prof;
452 struct net_device *dev;
453 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
454 struct net_device_stats stats;
455 struct net_device_stats ret_stats;
456 struct mlx4_en_port_state port_state;
457 spinlock_t stats_lock;
458 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
460 unsigned long last_moder_packets[MAX_RX_RINGS];
461 unsigned long last_moder_tx_packets;
462 unsigned long last_moder_bytes[MAX_RX_RINGS];
463 unsigned long last_moder_jiffies;
464 int last_moder_time[MAX_RX_RINGS];
474 u16 adaptive_rx_coal;
477 u32 validate_loopback;
479 struct mlx4_hwq_resources res;
492 struct mlx4_en_rss_map rss_map;
495 #define MLX4_EN_FLAG_PROMISC 0x1
496 #define MLX4_EN_FLAG_MC_PROMISC 0x2
500 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
504 struct mlx4_en_tx_ring *tx_ring;
505 struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
506 struct mlx4_en_cq *tx_cq;
507 struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
508 struct mlx4_qp drop_qp;
509 struct work_struct mcast_task;
510 struct work_struct mac_task;
511 struct work_struct watchdog_task;
512 struct work_struct linkstate_task;
513 struct delayed_work stats_task;
514 struct mlx4_en_perf_stats pstats;
515 struct mlx4_en_pkt_stats pkstats;
516 struct mlx4_en_port_stats port_stats;
518 struct list_head mc_list;
519 struct list_head curr_list;
521 struct mlx4_en_stat_out_mbox hw_stats;
527 #ifdef CONFIG_MLX4_EN_DCB
529 u16 maxrate[IEEE_8021QAZ_MAX_TCS];
531 #ifdef CONFIG_RFS_ACCEL
532 spinlock_t filters_lock;
534 struct list_head filters;
535 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
541 MLX4_EN_WOL_MAGIC = (1ULL << 61),
542 MLX4_EN_WOL_ENABLED = (1ULL << 62),
545 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
547 void mlx4_en_destroy_netdev(struct net_device *dev);
548 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
549 struct mlx4_en_port_profile *prof);
551 int mlx4_en_start_port(struct net_device *dev);
552 void mlx4_en_stop_port(struct net_device *dev);
554 void mlx4_en_free_resources(struct mlx4_en_priv *priv);
555 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
557 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
558 int entries, int ring, enum cq_type mode);
559 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
560 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
562 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
563 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
564 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
566 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
567 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb);
568 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
570 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring,
571 int qpn, u32 size, u16 stride);
572 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring);
573 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
574 struct mlx4_en_tx_ring *ring,
575 int cq, int user_prio);
576 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
577 struct mlx4_en_tx_ring *ring);
579 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
580 struct mlx4_en_rx_ring *ring,
581 u32 size, u16 stride);
582 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
583 struct mlx4_en_rx_ring *ring,
584 u32 size, u16 stride);
585 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
586 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
587 struct mlx4_en_rx_ring *ring);
588 int mlx4_en_process_rx_cq(struct net_device *dev,
589 struct mlx4_en_cq *cq,
591 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
592 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
593 int is_tx, int rss, int qpn, int cqn, int user_prio,
594 struct mlx4_qp_context *context);
595 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
596 int mlx4_en_map_buffer(struct mlx4_buf *buf);
597 void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
599 void mlx4_en_calc_rx_buf(struct net_device *dev);
600 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
601 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
602 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
603 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
604 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
605 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
607 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
608 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
610 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
611 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
613 #ifdef CONFIG_MLX4_EN_DCB
614 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
617 #ifdef CONFIG_RFS_ACCEL
618 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv,
619 struct mlx4_en_rx_ring *rx_ring);
622 #define MLX4_EN_NUM_SELF_TEST 5
623 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
624 u64 mlx4_en_mac_to_u64(u8 *addr);
629 extern const struct ethtool_ops mlx4_en_ethtool_ops;
634 * printk / logging functions
638 int en_print(const char *level, const struct mlx4_en_priv *priv,
639 const char *format, ...);
641 #define en_dbg(mlevel, priv, format, arg...) \
643 if (NETIF_MSG_##mlevel & priv->msg_enable) \
644 en_print(KERN_DEBUG, priv, format, ##arg); \
646 #define en_warn(priv, format, arg...) \
647 en_print(KERN_WARNING, priv, format, ##arg)
648 #define en_err(priv, format, arg...) \
649 en_print(KERN_ERR, priv, format, ##arg)
650 #define en_info(priv, format, arg...) \
651 en_print(KERN_INFO, priv, format, ## arg)
653 #define mlx4_err(mdev, format, arg...) \
654 pr_err("%s %s: " format, DRV_NAME, \
655 dev_name(&mdev->pdev->dev), ##arg)
656 #define mlx4_info(mdev, format, arg...) \
657 pr_info("%s %s: " format, DRV_NAME, \
658 dev_name(&mdev->pdev->dev), ##arg)
659 #define mlx4_warn(mdev, format, arg...) \
660 pr_warning("%s %s: " format, DRV_NAME, \
661 dev_name(&mdev->pdev->dev), ##arg)