2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/mutex.h>
41 #include <linux/radix-tree.h>
42 #include <linux/rbtree.h>
43 #include <linux/timer.h>
44 #include <linux/semaphore.h>
45 #include <linux/workqueue.h>
47 #include <linux/mlx4/device.h>
48 #include <linux/mlx4/driver.h>
49 #include <linux/mlx4/doorbell.h>
50 #include <linux/mlx4/cmd.h>
52 #define DRV_NAME "mlx4_core"
53 #define PFX DRV_NAME ": "
54 #define DRV_VERSION "1.1"
55 #define DRV_RELDATE "Dec, 2011"
57 #define MLX4_FS_UDP_UC_EN (1 << 1)
58 #define MLX4_FS_TCP_UC_EN (1 << 2)
59 #define MLX4_FS_NUM_OF_L2_ADDR 8
60 #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7
61 #define MLX4_FS_NUM_MCG (1 << 17)
65 MLX4_FS_L2_L3_L4_HASH,
70 #define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */
71 #define MLX4_RATELIMIT_DEFAULT 0xffff
73 struct mlx4_set_port_prio2tc_context {
77 struct mlx4_port_scheduler_tc_cfg_be {
80 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
84 struct mlx4_set_port_scheduler_context {
85 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
89 MLX4_HCR_BASE = 0x80680,
90 MLX4_HCR_SIZE = 0x0001c,
91 MLX4_CLR_INT_SIZE = 0x00008,
92 MLX4_SLAVE_COMM_BASE = 0x0,
93 MLX4_COMM_PAGESIZE = 0x1000
97 MLX4_MAX_MGM_ENTRY_SIZE = 0x1000,
98 MLX4_MAX_QP_PER_MGM = 4 * (MLX4_MAX_MGM_ENTRY_SIZE / 16 - 2),
99 MLX4_MTT_ENTRY_PER_SEG = 8,
103 MLX4_NUM_PDS = 1 << 15
107 MLX4_CMPT_TYPE_QP = 0,
108 MLX4_CMPT_TYPE_SRQ = 1,
109 MLX4_CMPT_TYPE_CQ = 2,
110 MLX4_CMPT_TYPE_EQ = 3,
115 MLX4_CMPT_SHIFT = 24,
116 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
120 MLX4_MR_DISABLED = 0,
125 #define MLX4_COMM_TIME 10000
131 MLX4_COMM_CMD_VHCR_EN,
132 MLX4_COMM_CMD_VHCR_POST,
133 MLX4_COMM_CMD_FLR = 254
136 /*The flag indicates that the slave should delay the RESET cmd*/
137 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
138 /*indicates how many retries will be done if we are in the middle of FLR*/
139 #define NUM_OF_RESET_RETRIES 10
140 #define SLEEP_TIME_IN_RESET (2 * 1000)
153 MLX4_NUM_OF_RESOURCE_TYPE
156 enum mlx4_alloc_mode {
158 RES_OP_RESERVE_AND_MAP,
162 enum mlx4_res_tracker_free_type {
164 RES_TR_FREE_SLAVES_ONLY,
165 RES_TR_FREE_STRUCTS_ONLY,
169 *Virtual HCR structures.
170 * mlx4_vhcr is the sw representation, in machine endianess
172 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
173 * to FW to go through communication channel.
174 * It is big endian, and has the same structure as the physical HCR
175 * used by command interface
188 struct mlx4_vhcr_cmd {
199 struct mlx4_cmd_info {
204 bool encode_slave_id;
205 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
206 struct mlx4_cmd_mailbox *inbox);
207 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
208 struct mlx4_cmd_mailbox *inbox,
209 struct mlx4_cmd_mailbox *outbox,
210 struct mlx4_cmd_info *cmd);
213 #ifdef CONFIG_MLX4_DEBUG
214 extern int mlx4_debug_level;
215 #else /* CONFIG_MLX4_DEBUG */
216 #define mlx4_debug_level (0)
217 #endif /* CONFIG_MLX4_DEBUG */
219 #define mlx4_dbg(mdev, format, arg...) \
221 if (mlx4_debug_level) \
222 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
225 #define mlx4_err(mdev, format, arg...) \
226 dev_err(&mdev->pdev->dev, format, ##arg)
227 #define mlx4_info(mdev, format, arg...) \
228 dev_info(&mdev->pdev->dev, format, ##arg)
229 #define mlx4_warn(mdev, format, arg...) \
230 dev_warn(&mdev->pdev->dev, format, ##arg)
232 extern int mlx4_log_num_mgm_entry_size;
233 extern int log_mtts_per_seg;
235 #define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
236 #define ALL_SLAVES 0xff
246 unsigned long *table;
250 unsigned long **bits;
251 unsigned int *num_free;
258 struct mlx4_icm_table {
266 struct mlx4_icm **icm;
270 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
272 struct mlx4_mpt_entry {
286 __be32 first_byte_offset;
290 * Must be packed because start is 64 bits but only aligned to 32 bits.
292 struct mlx4_eq_context {
306 __be32 mtt_base_addr_l;
308 __be32 consumer_index;
309 __be32 producer_index;
313 struct mlx4_cq_context {
317 __be32 logsize_usrpage;
325 __be32 mtt_base_addr_l;
326 __be32 last_notified_index;
327 __be32 solicit_producer_index;
328 __be32 consumer_index;
329 __be32 producer_index;
334 struct mlx4_srq_context {
335 __be32 state_logsize_srqn;
339 __be32 pg_offset_cqn;
344 __be32 mtt_base_addr_l;
346 __be16 limit_watermark;
355 struct mlx4_dev *dev;
356 void __iomem *doorbell;
362 struct mlx4_buf_list *page_list;
366 struct mlx4_slave_eqe {
372 struct mlx4_slave_event_eq_info {
377 struct mlx4_profile {
391 struct mlx4_icm *fw_icm;
392 struct mlx4_icm *aux_icm;
406 MLX4_MCAST_CONFIG = 0,
407 MLX4_MCAST_DISABLE = 1,
408 MLX4_MCAST_ENABLE = 2,
411 #define VLAN_FLTR_SIZE 128
413 struct mlx4_vlan_fltr {
414 __be32 entry[VLAN_FLTR_SIZE];
417 struct mlx4_mcast_entry {
418 struct list_head list;
422 struct mlx4_promisc_qp {
423 struct list_head list;
427 struct mlx4_steer_index {
428 struct list_head list;
430 struct list_head duplicates;
433 #define MLX4_EVENT_TYPES_NUM 64
435 struct mlx4_slave_state {
442 u16 mtu[MLX4_MAX_PORTS + 1];
443 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
444 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
445 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
446 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
447 /* event type to eq number lookup */
448 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
452 /*initialized via the kzalloc*/
453 u8 is_slave_going_down;
459 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
462 struct mlx4_resource_tracker {
464 /* tree for each resources */
465 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
466 /* num_of_slave's lists, one per slave */
467 struct slave_list *slave_list;
470 #define SLAVE_EVENT_EQ_SIZE 128
471 struct mlx4_slave_event_eq {
475 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
478 struct mlx4_master_qp0_state {
479 int proxy_qp0_active;
484 struct mlx4_mfunc_master_ctx {
485 struct mlx4_slave_state *slave_state;
486 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
487 int init_port_ref[MLX4_MAX_PORTS + 1];
488 u16 max_mtu[MLX4_MAX_PORTS + 1];
489 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
490 struct mlx4_resource_tracker res_tracker;
491 struct workqueue_struct *comm_wq;
492 struct work_struct comm_work;
493 struct work_struct slave_event_work;
494 struct work_struct slave_flr_event_work;
495 spinlock_t slave_state_lock;
496 __be32 comm_arm_bit_vector[4];
497 struct mlx4_eqe cmd_eqe;
498 struct mlx4_slave_event_eq slave_eq;
499 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
503 struct mlx4_comm __iomem *comm;
504 struct mlx4_vhcr_cmd *vhcr;
507 struct mlx4_mfunc_master_ctx master;
511 struct pci_pool *pool;
513 struct mutex hcr_mutex;
514 struct semaphore poll_sem;
515 struct semaphore event_sem;
516 struct semaphore slave_sem;
518 spinlock_t context_lock;
520 struct mlx4_cmd_context *context;
527 struct mlx4_uar_table {
528 struct mlx4_bitmap bitmap;
531 struct mlx4_mr_table {
532 struct mlx4_bitmap mpt_bitmap;
533 struct mlx4_buddy mtt_buddy;
536 struct mlx4_icm_table mtt_table;
537 struct mlx4_icm_table dmpt_table;
540 struct mlx4_cq_table {
541 struct mlx4_bitmap bitmap;
543 struct radix_tree_root tree;
544 struct mlx4_icm_table table;
545 struct mlx4_icm_table cmpt_table;
548 struct mlx4_eq_table {
549 struct mlx4_bitmap bitmap;
551 void __iomem *clr_int;
552 void __iomem **uar_map;
555 struct mlx4_icm_table table;
556 struct mlx4_icm_table cmpt_table;
561 struct mlx4_srq_table {
562 struct mlx4_bitmap bitmap;
564 struct radix_tree_root tree;
565 struct mlx4_icm_table table;
566 struct mlx4_icm_table cmpt_table;
569 struct mlx4_qp_table {
570 struct mlx4_bitmap bitmap;
574 struct mlx4_icm_table qp_table;
575 struct mlx4_icm_table auxc_table;
576 struct mlx4_icm_table altc_table;
577 struct mlx4_icm_table rdmarc_table;
578 struct mlx4_icm_table cmpt_table;
581 struct mlx4_mcg_table {
583 struct mlx4_bitmap bitmap;
584 struct mlx4_icm_table table;
587 struct mlx4_catas_err {
589 struct timer_list timer;
590 struct list_head list;
593 #define MLX4_MAX_MAC_NUM 128
594 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
596 struct mlx4_mac_table {
597 __be64 entries[MLX4_MAX_MAC_NUM];
598 int refs[MLX4_MAX_MAC_NUM];
604 #define MLX4_MAX_VLAN_NUM 128
605 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
607 struct mlx4_vlan_table {
608 __be32 entries[MLX4_MAX_VLAN_NUM];
609 int refs[MLX4_MAX_VLAN_NUM];
615 #define SET_PORT_GEN_ALL_VALID 0x7
616 #define SET_PORT_PROMISC_SHIFT 31
617 #define SET_PORT_MC_PROMISC_SHIFT 30
620 MCAST_DIRECT_ONLY = 0,
626 struct mlx4_set_port_general_context {
639 struct mlx4_set_port_rqp_calc_context {
657 struct mlx4_mac_entry {
662 struct mlx4_port_info {
663 struct mlx4_dev *dev;
666 struct device_attribute port_attr;
667 enum mlx4_port_type tmp_type;
668 char dev_mtu_name[16];
669 struct device_attribute port_mtu_attr;
670 struct mlx4_mac_table mac_table;
671 struct radix_tree_root mac_tree;
672 struct mlx4_vlan_table vlan_table;
677 struct mlx4_dev *dev;
678 u8 do_sense_port[MLX4_MAX_PORTS + 1];
679 u8 sense_allowed[MLX4_MAX_PORTS + 1];
680 struct delayed_work sense_poll;
683 struct mlx4_msix_ctl {
685 struct mutex pool_lock;
689 struct list_head promisc_qps[MLX4_NUM_STEERS];
690 struct list_head steer_entries[MLX4_NUM_STEERS];
696 struct list_head dev_list;
697 struct list_head ctx_list;
700 struct list_head pgdir_list;
701 struct mutex pgdir_mutex;
705 struct mlx4_mfunc mfunc;
707 struct mlx4_bitmap pd_bitmap;
708 struct mlx4_bitmap xrcd_bitmap;
709 struct mlx4_uar_table uar_table;
710 struct mlx4_mr_table mr_table;
711 struct mlx4_cq_table cq_table;
712 struct mlx4_eq_table eq_table;
713 struct mlx4_srq_table srq_table;
714 struct mlx4_qp_table qp_table;
715 struct mlx4_mcg_table mcg_table;
716 struct mlx4_bitmap counters_bitmap;
718 struct mlx4_catas_err catas_err;
720 void __iomem *clr_base;
722 struct mlx4_uar driver_uar;
724 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
725 struct mlx4_sense sense;
726 struct mutex port_mutex;
727 struct mlx4_msix_ctl msix_ctl;
728 struct mlx4_steer *steer;
729 struct list_head bf_list;
730 struct mutex bf_mutex;
731 struct io_mapping *bf_mapping;
736 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
738 return container_of(dev, struct mlx4_priv, dev);
741 #define MLX4_SENSE_RANGE (HZ * 3)
743 extern struct workqueue_struct *mlx4_wq;
745 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
746 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
747 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
748 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
749 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
750 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
751 u32 reserved_bot, u32 resetrved_top);
752 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
754 int mlx4_reset(struct mlx4_dev *dev);
756 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
757 void mlx4_free_eq_table(struct mlx4_dev *dev);
759 int mlx4_init_pd_table(struct mlx4_dev *dev);
760 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
761 int mlx4_init_uar_table(struct mlx4_dev *dev);
762 int mlx4_init_mr_table(struct mlx4_dev *dev);
763 int mlx4_init_eq_table(struct mlx4_dev *dev);
764 int mlx4_init_cq_table(struct mlx4_dev *dev);
765 int mlx4_init_qp_table(struct mlx4_dev *dev);
766 int mlx4_init_srq_table(struct mlx4_dev *dev);
767 int mlx4_init_mcg_table(struct mlx4_dev *dev);
769 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
770 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
771 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
772 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
773 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
774 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
775 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
776 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
777 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
778 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
779 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
780 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
781 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
782 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
783 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
784 int __mlx4_mr_reserve(struct mlx4_dev *dev);
785 void __mlx4_mr_release(struct mlx4_dev *dev, u32 index);
786 int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index);
787 void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index);
788 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
789 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
791 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
792 struct mlx4_vhcr *vhcr,
793 struct mlx4_cmd_mailbox *inbox,
794 struct mlx4_cmd_mailbox *outbox,
795 struct mlx4_cmd_info *cmd);
796 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
797 struct mlx4_vhcr *vhcr,
798 struct mlx4_cmd_mailbox *inbox,
799 struct mlx4_cmd_mailbox *outbox,
800 struct mlx4_cmd_info *cmd);
801 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
802 struct mlx4_vhcr *vhcr,
803 struct mlx4_cmd_mailbox *inbox,
804 struct mlx4_cmd_mailbox *outbox,
805 struct mlx4_cmd_info *cmd);
806 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
807 struct mlx4_vhcr *vhcr,
808 struct mlx4_cmd_mailbox *inbox,
809 struct mlx4_cmd_mailbox *outbox,
810 struct mlx4_cmd_info *cmd);
811 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
812 struct mlx4_vhcr *vhcr,
813 struct mlx4_cmd_mailbox *inbox,
814 struct mlx4_cmd_mailbox *outbox,
815 struct mlx4_cmd_info *cmd);
816 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
817 struct mlx4_vhcr *vhcr,
818 struct mlx4_cmd_mailbox *inbox,
819 struct mlx4_cmd_mailbox *outbox,
820 struct mlx4_cmd_info *cmd);
821 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
822 struct mlx4_vhcr *vhcr,
823 struct mlx4_cmd_mailbox *inbox,
824 struct mlx4_cmd_mailbox *outbox,
825 struct mlx4_cmd_info *cmd);
826 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
828 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
829 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
830 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
831 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
832 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
833 int start_index, int npages, u64 *page_list);
834 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
835 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
836 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
837 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
839 void mlx4_start_catas_poll(struct mlx4_dev *dev);
840 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
841 void mlx4_catas_init(void);
842 int mlx4_restart_one(struct pci_dev *pdev);
843 int mlx4_register_device(struct mlx4_dev *dev);
844 void mlx4_unregister_device(struct mlx4_dev *dev);
845 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
846 unsigned long param);
849 struct mlx4_init_hca_param;
851 u64 mlx4_make_profile(struct mlx4_dev *dev,
852 struct mlx4_profile *request,
853 struct mlx4_dev_cap *dev_cap,
854 struct mlx4_init_hca_param *init_hca);
855 void mlx4_master_comm_channel(struct work_struct *work);
856 void mlx4_gen_slave_eqe(struct work_struct *work);
857 void mlx4_master_handle_slave_flr(struct work_struct *work);
859 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
860 struct mlx4_vhcr *vhcr,
861 struct mlx4_cmd_mailbox *inbox,
862 struct mlx4_cmd_mailbox *outbox,
863 struct mlx4_cmd_info *cmd);
864 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
865 struct mlx4_vhcr *vhcr,
866 struct mlx4_cmd_mailbox *inbox,
867 struct mlx4_cmd_mailbox *outbox,
868 struct mlx4_cmd_info *cmd);
869 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
870 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
871 struct mlx4_cmd_mailbox *outbox,
872 struct mlx4_cmd_info *cmd);
873 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
874 struct mlx4_vhcr *vhcr,
875 struct mlx4_cmd_mailbox *inbox,
876 struct mlx4_cmd_mailbox *outbox,
877 struct mlx4_cmd_info *cmd);
878 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
879 struct mlx4_vhcr *vhcr,
880 struct mlx4_cmd_mailbox *inbox,
881 struct mlx4_cmd_mailbox *outbox,
882 struct mlx4_cmd_info *cmd);
883 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
884 struct mlx4_vhcr *vhcr,
885 struct mlx4_cmd_mailbox *inbox,
886 struct mlx4_cmd_mailbox *outbox,
887 struct mlx4_cmd_info *cmd);
888 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
889 struct mlx4_vhcr *vhcr,
890 struct mlx4_cmd_mailbox *inbox,
891 struct mlx4_cmd_mailbox *outbox,
892 struct mlx4_cmd_info *cmd);
893 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
894 struct mlx4_vhcr *vhcr,
895 struct mlx4_cmd_mailbox *inbox,
896 struct mlx4_cmd_mailbox *outbox,
897 struct mlx4_cmd_info *cmd);
898 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
899 struct mlx4_vhcr *vhcr,
900 struct mlx4_cmd_mailbox *inbox,
901 struct mlx4_cmd_mailbox *outbox,
902 struct mlx4_cmd_info *cmd);
903 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
904 struct mlx4_vhcr *vhcr,
905 struct mlx4_cmd_mailbox *inbox,
906 struct mlx4_cmd_mailbox *outbox,
907 struct mlx4_cmd_info *cmd);
908 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
909 struct mlx4_vhcr *vhcr,
910 struct mlx4_cmd_mailbox *inbox,
911 struct mlx4_cmd_mailbox *outbox,
912 struct mlx4_cmd_info *cmd);
913 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
914 struct mlx4_vhcr *vhcr,
915 struct mlx4_cmd_mailbox *inbox,
916 struct mlx4_cmd_mailbox *outbox,
917 struct mlx4_cmd_info *cmd);
918 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
919 struct mlx4_vhcr *vhcr,
920 struct mlx4_cmd_mailbox *inbox,
921 struct mlx4_cmd_mailbox *outbox,
922 struct mlx4_cmd_info *cmd);
923 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
924 struct mlx4_vhcr *vhcr,
925 struct mlx4_cmd_mailbox *inbox,
926 struct mlx4_cmd_mailbox *outbox,
927 struct mlx4_cmd_info *cmd);
928 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
929 struct mlx4_vhcr *vhcr,
930 struct mlx4_cmd_mailbox *inbox,
931 struct mlx4_cmd_mailbox *outbox,
932 struct mlx4_cmd_info *cmd);
933 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
934 struct mlx4_vhcr *vhcr,
935 struct mlx4_cmd_mailbox *inbox,
936 struct mlx4_cmd_mailbox *outbox,
937 struct mlx4_cmd_info *cmd);
938 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
939 struct mlx4_vhcr *vhcr,
940 struct mlx4_cmd_mailbox *inbox,
941 struct mlx4_cmd_mailbox *outbox,
942 struct mlx4_cmd_info *cmd);
943 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
944 struct mlx4_vhcr *vhcr,
945 struct mlx4_cmd_mailbox *inbox,
946 struct mlx4_cmd_mailbox *outbox,
947 struct mlx4_cmd_info *cmd);
949 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
951 int mlx4_cmd_init(struct mlx4_dev *dev);
952 void mlx4_cmd_cleanup(struct mlx4_dev *dev);
953 int mlx4_multi_func_init(struct mlx4_dev *dev);
954 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
955 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
956 int mlx4_cmd_use_events(struct mlx4_dev *dev);
957 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
959 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
960 unsigned long timeout);
962 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
963 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
965 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
967 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
969 void mlx4_handle_catas_err(struct mlx4_dev *dev);
971 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
972 enum mlx4_port_type *type);
973 void mlx4_do_sense_ports(struct mlx4_dev *dev,
974 enum mlx4_port_type *stype,
975 enum mlx4_port_type *defaults);
976 void mlx4_start_sense(struct mlx4_dev *dev);
977 void mlx4_stop_sense(struct mlx4_dev *dev);
978 void mlx4_sense_init(struct mlx4_dev *dev);
979 int mlx4_check_port_params(struct mlx4_dev *dev,
980 enum mlx4_port_type *port_type);
981 int mlx4_change_port_types(struct mlx4_dev *dev,
982 enum mlx4_port_type *port_types);
984 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
985 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
987 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
988 /* resource tracker functions*/
989 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
990 enum mlx4_resource resource_type,
991 u64 resource_id, int *slave);
992 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
993 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
995 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
996 enum mlx4_res_tracker_free_type type);
998 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
999 struct mlx4_vhcr *vhcr,
1000 struct mlx4_cmd_mailbox *inbox,
1001 struct mlx4_cmd_mailbox *outbox,
1002 struct mlx4_cmd_info *cmd);
1003 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1004 struct mlx4_vhcr *vhcr,
1005 struct mlx4_cmd_mailbox *inbox,
1006 struct mlx4_cmd_mailbox *outbox,
1007 struct mlx4_cmd_info *cmd);
1008 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1009 struct mlx4_vhcr *vhcr,
1010 struct mlx4_cmd_mailbox *inbox,
1011 struct mlx4_cmd_mailbox *outbox,
1012 struct mlx4_cmd_info *cmd);
1013 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1014 struct mlx4_vhcr *vhcr,
1015 struct mlx4_cmd_mailbox *inbox,
1016 struct mlx4_cmd_mailbox *outbox,
1017 struct mlx4_cmd_info *cmd);
1018 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1019 struct mlx4_vhcr *vhcr,
1020 struct mlx4_cmd_mailbox *inbox,
1021 struct mlx4_cmd_mailbox *outbox,
1022 struct mlx4_cmd_info *cmd);
1023 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1024 struct mlx4_vhcr *vhcr,
1025 struct mlx4_cmd_mailbox *inbox,
1026 struct mlx4_cmd_mailbox *outbox,
1027 struct mlx4_cmd_info *cmd);
1028 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1030 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1031 int *gid_tbl_len, int *pkey_tbl_len);
1033 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1034 struct mlx4_vhcr *vhcr,
1035 struct mlx4_cmd_mailbox *inbox,
1036 struct mlx4_cmd_mailbox *outbox,
1037 struct mlx4_cmd_info *cmd);
1039 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1040 struct mlx4_vhcr *vhcr,
1041 struct mlx4_cmd_mailbox *inbox,
1042 struct mlx4_cmd_mailbox *outbox,
1043 struct mlx4_cmd_info *cmd);
1044 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1045 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1046 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1047 int block_mcast_loopback, enum mlx4_protocol prot,
1048 enum mlx4_steer_type steer);
1049 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1050 struct mlx4_vhcr *vhcr,
1051 struct mlx4_cmd_mailbox *inbox,
1052 struct mlx4_cmd_mailbox *outbox,
1053 struct mlx4_cmd_info *cmd);
1054 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1055 struct mlx4_vhcr *vhcr,
1056 struct mlx4_cmd_mailbox *inbox,
1057 struct mlx4_cmd_mailbox *outbox,
1058 struct mlx4_cmd_info *cmd);
1059 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1060 int port, void *buf);
1061 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1062 struct mlx4_cmd_mailbox *outbox);
1063 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1064 struct mlx4_vhcr *vhcr,
1065 struct mlx4_cmd_mailbox *inbox,
1066 struct mlx4_cmd_mailbox *outbox,
1067 struct mlx4_cmd_info *cmd);
1068 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1069 struct mlx4_vhcr *vhcr,
1070 struct mlx4_cmd_mailbox *inbox,
1071 struct mlx4_cmd_mailbox *outbox,
1072 struct mlx4_cmd_info *cmd);
1073 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1074 struct mlx4_vhcr *vhcr,
1075 struct mlx4_cmd_mailbox *inbox,
1076 struct mlx4_cmd_mailbox *outbox,
1077 struct mlx4_cmd_info *cmd);
1078 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1079 struct mlx4_vhcr *vhcr,
1080 struct mlx4_cmd_mailbox *inbox,
1081 struct mlx4_cmd_mailbox *outbox,
1082 struct mlx4_cmd_info *cmd);
1083 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1084 struct mlx4_vhcr *vhcr,
1085 struct mlx4_cmd_mailbox *inbox,
1086 struct mlx4_cmd_mailbox *outbox,
1087 struct mlx4_cmd_info *cmd);
1089 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1090 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1092 static inline void set_param_l(u64 *arg, u32 val)
1094 *((u32 *)arg) = val;
1097 static inline void set_param_h(u64 *arg, u32 val)
1099 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1102 static inline u32 get_param_l(u64 *arg)
1104 return (u32) (*arg & 0xffffffff);
1107 static inline u32 get_param_h(u64 *arg)
1109 return (u32)(*arg >> 32);
1112 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1114 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1117 #define NOT_MASKED_PD_BITS 17