2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/mutex.h>
41 #include <linux/radix-tree.h>
42 #include <linux/rbtree.h>
43 #include <linux/timer.h>
44 #include <linux/semaphore.h>
45 #include <linux/workqueue.h>
47 #include <linux/mlx4/device.h>
48 #include <linux/mlx4/driver.h>
49 #include <linux/mlx4/doorbell.h>
50 #include <linux/mlx4/cmd.h>
52 #define DRV_NAME "mlx4_core"
53 #define PFX DRV_NAME ": "
54 #define DRV_VERSION "1.1"
55 #define DRV_RELDATE "Dec, 2011"
57 #define MLX4_FS_UDP_UC_EN (1 << 1)
58 #define MLX4_FS_TCP_UC_EN (1 << 2)
59 #define MLX4_FS_NUM_OF_L2_ADDR 8
60 #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7
61 #define MLX4_FS_NUM_MCG (1 << 17)
65 MLX4_FS_L2_L3_L4_HASH,
70 #define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */
71 #define MLX4_RATELIMIT_DEFAULT 0xffff
73 struct mlx4_set_port_prio2tc_context {
77 struct mlx4_port_scheduler_tc_cfg_be {
80 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
84 struct mlx4_set_port_scheduler_context {
85 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
89 MLX4_HCR_BASE = 0x80680,
90 MLX4_HCR_SIZE = 0x0001c,
91 MLX4_CLR_INT_SIZE = 0x00008,
92 MLX4_SLAVE_COMM_BASE = 0x0,
93 MLX4_COMM_PAGESIZE = 0x1000
97 MLX4_MAX_MGM_ENTRY_SIZE = 0x1000,
98 MLX4_MAX_QP_PER_MGM = 4 * (MLX4_MAX_MGM_ENTRY_SIZE / 16 - 2),
99 MLX4_MTT_ENTRY_PER_SEG = 8,
103 MLX4_NUM_PDS = 1 << 15
107 MLX4_CMPT_TYPE_QP = 0,
108 MLX4_CMPT_TYPE_SRQ = 1,
109 MLX4_CMPT_TYPE_CQ = 2,
110 MLX4_CMPT_TYPE_EQ = 3,
115 MLX4_CMPT_SHIFT = 24,
116 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
120 MLX4_MR_DISABLED = 0,
125 #define MLX4_COMM_TIME 10000
131 MLX4_COMM_CMD_VHCR_EN,
132 MLX4_COMM_CMD_VHCR_POST,
133 MLX4_COMM_CMD_FLR = 254
136 /*The flag indicates that the slave should delay the RESET cmd*/
137 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
138 /*indicates how many retries will be done if we are in the middle of FLR*/
139 #define NUM_OF_RESET_RETRIES 10
140 #define SLEEP_TIME_IN_RESET (2 * 1000)
152 MLX4_NUM_OF_RESOURCE_TYPE
155 enum mlx4_alloc_mode {
157 RES_OP_RESERVE_AND_MAP,
161 enum mlx4_res_tracker_free_type {
163 RES_TR_FREE_SLAVES_ONLY,
164 RES_TR_FREE_STRUCTS_ONLY,
168 *Virtual HCR structures.
169 * mlx4_vhcr is the sw representation, in machine endianess
171 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
172 * to FW to go through communication channel.
173 * It is big endian, and has the same structure as the physical HCR
174 * used by command interface
187 struct mlx4_vhcr_cmd {
198 struct mlx4_cmd_info {
203 bool encode_slave_id;
204 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
205 struct mlx4_cmd_mailbox *inbox);
206 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
207 struct mlx4_cmd_mailbox *inbox,
208 struct mlx4_cmd_mailbox *outbox,
209 struct mlx4_cmd_info *cmd);
212 #ifdef CONFIG_MLX4_DEBUG
213 extern int mlx4_debug_level;
214 #else /* CONFIG_MLX4_DEBUG */
215 #define mlx4_debug_level (0)
216 #endif /* CONFIG_MLX4_DEBUG */
218 #define mlx4_dbg(mdev, format, arg...) \
220 if (mlx4_debug_level) \
221 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
224 #define mlx4_err(mdev, format, arg...) \
225 dev_err(&mdev->pdev->dev, format, ##arg)
226 #define mlx4_info(mdev, format, arg...) \
227 dev_info(&mdev->pdev->dev, format, ##arg)
228 #define mlx4_warn(mdev, format, arg...) \
229 dev_warn(&mdev->pdev->dev, format, ##arg)
231 extern int mlx4_log_num_mgm_entry_size;
232 extern int log_mtts_per_seg;
234 #define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
235 #define ALL_SLAVES 0xff
245 unsigned long *table;
249 unsigned long **bits;
250 unsigned int *num_free;
257 struct mlx4_icm_table {
265 struct mlx4_icm **icm;
269 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
271 struct mlx4_mpt_entry {
285 __be32 first_byte_offset;
289 * Must be packed because start is 64 bits but only aligned to 32 bits.
291 struct mlx4_eq_context {
305 __be32 mtt_base_addr_l;
307 __be32 consumer_index;
308 __be32 producer_index;
312 struct mlx4_cq_context {
316 __be32 logsize_usrpage;
324 __be32 mtt_base_addr_l;
325 __be32 last_notified_index;
326 __be32 solicit_producer_index;
327 __be32 consumer_index;
328 __be32 producer_index;
333 struct mlx4_srq_context {
334 __be32 state_logsize_srqn;
338 __be32 pg_offset_cqn;
343 __be32 mtt_base_addr_l;
345 __be16 limit_watermark;
386 } __packed port_change;
388 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
390 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
391 } __packed comm_channel_arm;
396 } __packed mac_update;
402 } __packed flr_event;
404 __be16 current_temperature;
405 __be16 warning_threshold;
414 struct mlx4_dev *dev;
415 void __iomem *doorbell;
421 struct mlx4_buf_list *page_list;
425 struct mlx4_slave_eqe {
431 struct mlx4_slave_event_eq_info {
436 struct mlx4_profile {
450 struct mlx4_icm *fw_icm;
451 struct mlx4_icm *aux_icm;
465 MLX4_MCAST_CONFIG = 0,
466 MLX4_MCAST_DISABLE = 1,
467 MLX4_MCAST_ENABLE = 2,
470 #define VLAN_FLTR_SIZE 128
472 struct mlx4_vlan_fltr {
473 __be32 entry[VLAN_FLTR_SIZE];
476 struct mlx4_mcast_entry {
477 struct list_head list;
481 struct mlx4_promisc_qp {
482 struct list_head list;
486 struct mlx4_steer_index {
487 struct list_head list;
489 struct list_head duplicates;
492 #define MLX4_EVENT_TYPES_NUM 64
494 struct mlx4_slave_state {
501 u16 mtu[MLX4_MAX_PORTS + 1];
502 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
503 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
504 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
505 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
506 /* event type to eq number lookup */
507 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
511 /*initialized via the kzalloc*/
512 u8 is_slave_going_down;
518 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
521 struct mlx4_resource_tracker {
523 /* tree for each resources */
524 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
525 /* num_of_slave's lists, one per slave */
526 struct slave_list *slave_list;
529 #define SLAVE_EVENT_EQ_SIZE 128
530 struct mlx4_slave_event_eq {
534 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
537 struct mlx4_master_qp0_state {
538 int proxy_qp0_active;
543 struct mlx4_mfunc_master_ctx {
544 struct mlx4_slave_state *slave_state;
545 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
546 int init_port_ref[MLX4_MAX_PORTS + 1];
547 u16 max_mtu[MLX4_MAX_PORTS + 1];
548 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
549 struct mlx4_resource_tracker res_tracker;
550 struct workqueue_struct *comm_wq;
551 struct work_struct comm_work;
552 struct work_struct slave_event_work;
553 struct work_struct slave_flr_event_work;
554 spinlock_t slave_state_lock;
555 __be32 comm_arm_bit_vector[4];
556 struct mlx4_eqe cmd_eqe;
557 struct mlx4_slave_event_eq slave_eq;
558 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
562 struct mlx4_comm __iomem *comm;
563 struct mlx4_vhcr_cmd *vhcr;
566 struct mlx4_mfunc_master_ctx master;
570 struct pci_pool *pool;
572 struct mutex hcr_mutex;
573 struct semaphore poll_sem;
574 struct semaphore event_sem;
575 struct semaphore slave_sem;
577 spinlock_t context_lock;
579 struct mlx4_cmd_context *context;
586 struct mlx4_uar_table {
587 struct mlx4_bitmap bitmap;
590 struct mlx4_mr_table {
591 struct mlx4_bitmap mpt_bitmap;
592 struct mlx4_buddy mtt_buddy;
595 struct mlx4_icm_table mtt_table;
596 struct mlx4_icm_table dmpt_table;
599 struct mlx4_cq_table {
600 struct mlx4_bitmap bitmap;
602 struct radix_tree_root tree;
603 struct mlx4_icm_table table;
604 struct mlx4_icm_table cmpt_table;
607 struct mlx4_eq_table {
608 struct mlx4_bitmap bitmap;
610 void __iomem *clr_int;
611 void __iomem **uar_map;
614 struct mlx4_icm_table table;
615 struct mlx4_icm_table cmpt_table;
620 struct mlx4_srq_table {
621 struct mlx4_bitmap bitmap;
623 struct radix_tree_root tree;
624 struct mlx4_icm_table table;
625 struct mlx4_icm_table cmpt_table;
628 struct mlx4_qp_table {
629 struct mlx4_bitmap bitmap;
633 struct mlx4_icm_table qp_table;
634 struct mlx4_icm_table auxc_table;
635 struct mlx4_icm_table altc_table;
636 struct mlx4_icm_table rdmarc_table;
637 struct mlx4_icm_table cmpt_table;
640 struct mlx4_mcg_table {
642 struct mlx4_bitmap bitmap;
643 struct mlx4_icm_table table;
646 struct mlx4_catas_err {
648 struct timer_list timer;
649 struct list_head list;
652 #define MLX4_MAX_MAC_NUM 128
653 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
655 struct mlx4_mac_table {
656 __be64 entries[MLX4_MAX_MAC_NUM];
657 int refs[MLX4_MAX_MAC_NUM];
663 #define MLX4_MAX_VLAN_NUM 128
664 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
666 struct mlx4_vlan_table {
667 __be32 entries[MLX4_MAX_VLAN_NUM];
668 int refs[MLX4_MAX_VLAN_NUM];
674 #define SET_PORT_GEN_ALL_VALID 0x7
675 #define SET_PORT_PROMISC_SHIFT 31
676 #define SET_PORT_MC_PROMISC_SHIFT 30
679 MCAST_DIRECT_ONLY = 0,
685 struct mlx4_set_port_general_context {
698 struct mlx4_set_port_rqp_calc_context {
716 struct mlx4_mac_entry {
721 struct mlx4_port_info {
722 struct mlx4_dev *dev;
725 struct device_attribute port_attr;
726 enum mlx4_port_type tmp_type;
727 char dev_mtu_name[16];
728 struct device_attribute port_mtu_attr;
729 struct mlx4_mac_table mac_table;
730 struct radix_tree_root mac_tree;
731 struct mlx4_vlan_table vlan_table;
736 struct mlx4_dev *dev;
737 u8 do_sense_port[MLX4_MAX_PORTS + 1];
738 u8 sense_allowed[MLX4_MAX_PORTS + 1];
739 struct delayed_work sense_poll;
742 struct mlx4_msix_ctl {
744 struct mutex pool_lock;
748 struct list_head promisc_qps[MLX4_NUM_STEERS];
749 struct list_head steer_entries[MLX4_NUM_STEERS];
755 struct list_head dev_list;
756 struct list_head ctx_list;
759 struct list_head pgdir_list;
760 struct mutex pgdir_mutex;
764 struct mlx4_mfunc mfunc;
766 struct mlx4_bitmap pd_bitmap;
767 struct mlx4_bitmap xrcd_bitmap;
768 struct mlx4_uar_table uar_table;
769 struct mlx4_mr_table mr_table;
770 struct mlx4_cq_table cq_table;
771 struct mlx4_eq_table eq_table;
772 struct mlx4_srq_table srq_table;
773 struct mlx4_qp_table qp_table;
774 struct mlx4_mcg_table mcg_table;
775 struct mlx4_bitmap counters_bitmap;
777 struct mlx4_catas_err catas_err;
779 void __iomem *clr_base;
781 struct mlx4_uar driver_uar;
783 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
784 struct mlx4_sense sense;
785 struct mutex port_mutex;
786 struct mlx4_msix_ctl msix_ctl;
787 struct mlx4_steer *steer;
788 struct list_head bf_list;
789 struct mutex bf_mutex;
790 struct io_mapping *bf_mapping;
795 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
797 return container_of(dev, struct mlx4_priv, dev);
800 #define MLX4_SENSE_RANGE (HZ * 3)
802 extern struct workqueue_struct *mlx4_wq;
804 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
805 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
806 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
807 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
808 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
809 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
810 u32 reserved_bot, u32 resetrved_top);
811 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
813 int mlx4_reset(struct mlx4_dev *dev);
815 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
816 void mlx4_free_eq_table(struct mlx4_dev *dev);
818 int mlx4_init_pd_table(struct mlx4_dev *dev);
819 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
820 int mlx4_init_uar_table(struct mlx4_dev *dev);
821 int mlx4_init_mr_table(struct mlx4_dev *dev);
822 int mlx4_init_eq_table(struct mlx4_dev *dev);
823 int mlx4_init_cq_table(struct mlx4_dev *dev);
824 int mlx4_init_qp_table(struct mlx4_dev *dev);
825 int mlx4_init_srq_table(struct mlx4_dev *dev);
826 int mlx4_init_mcg_table(struct mlx4_dev *dev);
828 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
829 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
830 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
831 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
832 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
833 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
834 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
835 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
836 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
837 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
838 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
839 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
840 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
841 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
842 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
843 int __mlx4_mr_reserve(struct mlx4_dev *dev);
844 void __mlx4_mr_release(struct mlx4_dev *dev, u32 index);
845 int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index);
846 void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index);
847 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
848 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
850 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
851 struct mlx4_vhcr *vhcr,
852 struct mlx4_cmd_mailbox *inbox,
853 struct mlx4_cmd_mailbox *outbox,
854 struct mlx4_cmd_info *cmd);
855 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
856 struct mlx4_vhcr *vhcr,
857 struct mlx4_cmd_mailbox *inbox,
858 struct mlx4_cmd_mailbox *outbox,
859 struct mlx4_cmd_info *cmd);
860 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
861 struct mlx4_vhcr *vhcr,
862 struct mlx4_cmd_mailbox *inbox,
863 struct mlx4_cmd_mailbox *outbox,
864 struct mlx4_cmd_info *cmd);
865 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
866 struct mlx4_vhcr *vhcr,
867 struct mlx4_cmd_mailbox *inbox,
868 struct mlx4_cmd_mailbox *outbox,
869 struct mlx4_cmd_info *cmd);
870 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
871 struct mlx4_vhcr *vhcr,
872 struct mlx4_cmd_mailbox *inbox,
873 struct mlx4_cmd_mailbox *outbox,
874 struct mlx4_cmd_info *cmd);
875 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
876 struct mlx4_vhcr *vhcr,
877 struct mlx4_cmd_mailbox *inbox,
878 struct mlx4_cmd_mailbox *outbox,
879 struct mlx4_cmd_info *cmd);
880 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
881 struct mlx4_vhcr *vhcr,
882 struct mlx4_cmd_mailbox *inbox,
883 struct mlx4_cmd_mailbox *outbox,
884 struct mlx4_cmd_info *cmd);
885 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
887 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
888 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
889 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
890 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
891 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
892 int start_index, int npages, u64 *page_list);
893 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
894 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
895 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
896 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
898 void mlx4_start_catas_poll(struct mlx4_dev *dev);
899 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
900 void mlx4_catas_init(void);
901 int mlx4_restart_one(struct pci_dev *pdev);
902 int mlx4_register_device(struct mlx4_dev *dev);
903 void mlx4_unregister_device(struct mlx4_dev *dev);
904 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, int port);
907 struct mlx4_init_hca_param;
909 u64 mlx4_make_profile(struct mlx4_dev *dev,
910 struct mlx4_profile *request,
911 struct mlx4_dev_cap *dev_cap,
912 struct mlx4_init_hca_param *init_hca);
913 void mlx4_master_comm_channel(struct work_struct *work);
914 void mlx4_gen_slave_eqe(struct work_struct *work);
915 void mlx4_master_handle_slave_flr(struct work_struct *work);
917 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
918 struct mlx4_vhcr *vhcr,
919 struct mlx4_cmd_mailbox *inbox,
920 struct mlx4_cmd_mailbox *outbox,
921 struct mlx4_cmd_info *cmd);
922 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
923 struct mlx4_vhcr *vhcr,
924 struct mlx4_cmd_mailbox *inbox,
925 struct mlx4_cmd_mailbox *outbox,
926 struct mlx4_cmd_info *cmd);
927 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
928 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
929 struct mlx4_cmd_mailbox *outbox,
930 struct mlx4_cmd_info *cmd);
931 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
932 struct mlx4_vhcr *vhcr,
933 struct mlx4_cmd_mailbox *inbox,
934 struct mlx4_cmd_mailbox *outbox,
935 struct mlx4_cmd_info *cmd);
936 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
937 struct mlx4_vhcr *vhcr,
938 struct mlx4_cmd_mailbox *inbox,
939 struct mlx4_cmd_mailbox *outbox,
940 struct mlx4_cmd_info *cmd);
941 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
942 struct mlx4_vhcr *vhcr,
943 struct mlx4_cmd_mailbox *inbox,
944 struct mlx4_cmd_mailbox *outbox,
945 struct mlx4_cmd_info *cmd);
946 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
947 struct mlx4_vhcr *vhcr,
948 struct mlx4_cmd_mailbox *inbox,
949 struct mlx4_cmd_mailbox *outbox,
950 struct mlx4_cmd_info *cmd);
951 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
952 struct mlx4_vhcr *vhcr,
953 struct mlx4_cmd_mailbox *inbox,
954 struct mlx4_cmd_mailbox *outbox,
955 struct mlx4_cmd_info *cmd);
956 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
957 struct mlx4_vhcr *vhcr,
958 struct mlx4_cmd_mailbox *inbox,
959 struct mlx4_cmd_mailbox *outbox,
960 struct mlx4_cmd_info *cmd);
961 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
962 struct mlx4_vhcr *vhcr,
963 struct mlx4_cmd_mailbox *inbox,
964 struct mlx4_cmd_mailbox *outbox,
965 struct mlx4_cmd_info *cmd);
966 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
967 struct mlx4_vhcr *vhcr,
968 struct mlx4_cmd_mailbox *inbox,
969 struct mlx4_cmd_mailbox *outbox,
970 struct mlx4_cmd_info *cmd);
971 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
972 struct mlx4_vhcr *vhcr,
973 struct mlx4_cmd_mailbox *inbox,
974 struct mlx4_cmd_mailbox *outbox,
975 struct mlx4_cmd_info *cmd);
976 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
977 struct mlx4_vhcr *vhcr,
978 struct mlx4_cmd_mailbox *inbox,
979 struct mlx4_cmd_mailbox *outbox,
980 struct mlx4_cmd_info *cmd);
981 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
982 struct mlx4_vhcr *vhcr,
983 struct mlx4_cmd_mailbox *inbox,
984 struct mlx4_cmd_mailbox *outbox,
985 struct mlx4_cmd_info *cmd);
986 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
987 struct mlx4_vhcr *vhcr,
988 struct mlx4_cmd_mailbox *inbox,
989 struct mlx4_cmd_mailbox *outbox,
990 struct mlx4_cmd_info *cmd);
991 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
992 struct mlx4_vhcr *vhcr,
993 struct mlx4_cmd_mailbox *inbox,
994 struct mlx4_cmd_mailbox *outbox,
995 struct mlx4_cmd_info *cmd);
996 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
997 struct mlx4_vhcr *vhcr,
998 struct mlx4_cmd_mailbox *inbox,
999 struct mlx4_cmd_mailbox *outbox,
1000 struct mlx4_cmd_info *cmd);
1001 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1002 struct mlx4_vhcr *vhcr,
1003 struct mlx4_cmd_mailbox *inbox,
1004 struct mlx4_cmd_mailbox *outbox,
1005 struct mlx4_cmd_info *cmd);
1007 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
1009 int mlx4_cmd_init(struct mlx4_dev *dev);
1010 void mlx4_cmd_cleanup(struct mlx4_dev *dev);
1011 int mlx4_multi_func_init(struct mlx4_dev *dev);
1012 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
1013 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1014 int mlx4_cmd_use_events(struct mlx4_dev *dev);
1015 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1017 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1018 unsigned long timeout);
1020 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1021 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1023 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1025 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1027 void mlx4_handle_catas_err(struct mlx4_dev *dev);
1029 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1030 enum mlx4_port_type *type);
1031 void mlx4_do_sense_ports(struct mlx4_dev *dev,
1032 enum mlx4_port_type *stype,
1033 enum mlx4_port_type *defaults);
1034 void mlx4_start_sense(struct mlx4_dev *dev);
1035 void mlx4_stop_sense(struct mlx4_dev *dev);
1036 void mlx4_sense_init(struct mlx4_dev *dev);
1037 int mlx4_check_port_params(struct mlx4_dev *dev,
1038 enum mlx4_port_type *port_type);
1039 int mlx4_change_port_types(struct mlx4_dev *dev,
1040 enum mlx4_port_type *port_types);
1042 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1043 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1045 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port);
1046 /* resource tracker functions*/
1047 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1048 enum mlx4_resource resource_type,
1049 u64 resource_id, int *slave);
1050 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1051 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1053 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1054 enum mlx4_res_tracker_free_type type);
1056 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1057 struct mlx4_vhcr *vhcr,
1058 struct mlx4_cmd_mailbox *inbox,
1059 struct mlx4_cmd_mailbox *outbox,
1060 struct mlx4_cmd_info *cmd);
1061 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1062 struct mlx4_vhcr *vhcr,
1063 struct mlx4_cmd_mailbox *inbox,
1064 struct mlx4_cmd_mailbox *outbox,
1065 struct mlx4_cmd_info *cmd);
1066 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1067 struct mlx4_vhcr *vhcr,
1068 struct mlx4_cmd_mailbox *inbox,
1069 struct mlx4_cmd_mailbox *outbox,
1070 struct mlx4_cmd_info *cmd);
1071 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1072 struct mlx4_vhcr *vhcr,
1073 struct mlx4_cmd_mailbox *inbox,
1074 struct mlx4_cmd_mailbox *outbox,
1075 struct mlx4_cmd_info *cmd);
1076 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1077 struct mlx4_vhcr *vhcr,
1078 struct mlx4_cmd_mailbox *inbox,
1079 struct mlx4_cmd_mailbox *outbox,
1080 struct mlx4_cmd_info *cmd);
1081 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1082 struct mlx4_vhcr *vhcr,
1083 struct mlx4_cmd_mailbox *inbox,
1084 struct mlx4_cmd_mailbox *outbox,
1085 struct mlx4_cmd_info *cmd);
1086 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1089 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1090 struct mlx4_vhcr *vhcr,
1091 struct mlx4_cmd_mailbox *inbox,
1092 struct mlx4_cmd_mailbox *outbox,
1093 struct mlx4_cmd_info *cmd);
1095 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1096 struct mlx4_vhcr *vhcr,
1097 struct mlx4_cmd_mailbox *inbox,
1098 struct mlx4_cmd_mailbox *outbox,
1099 struct mlx4_cmd_info *cmd);
1100 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1101 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1102 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1103 int block_mcast_loopback, enum mlx4_protocol prot,
1104 enum mlx4_steer_type steer);
1105 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1106 struct mlx4_vhcr *vhcr,
1107 struct mlx4_cmd_mailbox *inbox,
1108 struct mlx4_cmd_mailbox *outbox,
1109 struct mlx4_cmd_info *cmd);
1110 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1111 struct mlx4_vhcr *vhcr,
1112 struct mlx4_cmd_mailbox *inbox,
1113 struct mlx4_cmd_mailbox *outbox,
1114 struct mlx4_cmd_info *cmd);
1115 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1116 int port, void *buf);
1117 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1118 struct mlx4_cmd_mailbox *outbox);
1119 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1120 struct mlx4_vhcr *vhcr,
1121 struct mlx4_cmd_mailbox *inbox,
1122 struct mlx4_cmd_mailbox *outbox,
1123 struct mlx4_cmd_info *cmd);
1124 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1125 struct mlx4_vhcr *vhcr,
1126 struct mlx4_cmd_mailbox *inbox,
1127 struct mlx4_cmd_mailbox *outbox,
1128 struct mlx4_cmd_info *cmd);
1129 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1130 struct mlx4_vhcr *vhcr,
1131 struct mlx4_cmd_mailbox *inbox,
1132 struct mlx4_cmd_mailbox *outbox,
1133 struct mlx4_cmd_info *cmd);
1134 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1135 struct mlx4_vhcr *vhcr,
1136 struct mlx4_cmd_mailbox *inbox,
1137 struct mlx4_cmd_mailbox *outbox,
1138 struct mlx4_cmd_info *cmd);
1139 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1140 struct mlx4_vhcr *vhcr,
1141 struct mlx4_cmd_mailbox *inbox,
1142 struct mlx4_cmd_mailbox *outbox,
1143 struct mlx4_cmd_info *cmd);
1145 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1146 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1148 static inline void set_param_l(u64 *arg, u32 val)
1150 *((u32 *)arg) = val;
1153 static inline void set_param_h(u64 *arg, u32 val)
1155 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1158 static inline u32 get_param_l(u64 *arg)
1160 return (u32) (*arg & 0xffffffff);
1163 static inline u32 get_param_h(u64 *arg)
1165 return (u32)(*arg >> 32);
1168 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1170 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1173 #define NOT_MASKED_PD_BITS 17