2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <net/busy_poll.h>
35 #include <linux/mlx4/cq.h>
36 #include <linux/slab.h>
37 #include <linux/mlx4/qp.h>
38 #include <linux/skbuff.h>
39 #include <linux/rculist.h>
40 #include <linux/if_ether.h>
41 #include <linux/if_vlan.h>
42 #include <linux/vmalloc.h>
43 #include <linux/irq.h>
45 #if IS_ENABLED(CONFIG_IPV6)
46 #include <net/ip6_checksum.h>
51 static int mlx4_alloc_pages(struct mlx4_en_priv *priv,
52 struct mlx4_en_rx_alloc *page_alloc,
53 const struct mlx4_en_frag_info *frag_info,
60 for (order = MLX4_EN_ALLOC_PREFER_ORDER; ;) {
64 gfp |= __GFP_COMP | __GFP_NOWARN | __GFP_NOMEMALLOC;
65 page = alloc_pages(gfp, order);
69 ((PAGE_SIZE << order) < frag_info->frag_size))
72 dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE << order,
74 if (dma_mapping_error(priv->ddev, dma)) {
78 page_alloc->page_size = PAGE_SIZE << order;
79 page_alloc->page = page;
80 page_alloc->dma = dma;
81 page_alloc->page_offset = 0;
82 /* Not doing get_page() for each frag is a big win
83 * on asymetric workloads. Note we can not use atomic_set().
85 page_ref_add(page, page_alloc->page_size / frag_info->frag_stride - 1);
89 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv,
90 struct mlx4_en_rx_desc *rx_desc,
91 struct mlx4_en_rx_alloc *frags,
92 struct mlx4_en_rx_alloc *ring_alloc,
95 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
96 const struct mlx4_en_frag_info *frag_info;
101 for (i = 0; i < priv->num_frags; i++) {
102 frag_info = &priv->frag_info[i];
103 page_alloc[i] = ring_alloc[i];
104 page_alloc[i].page_offset += frag_info->frag_stride;
106 if (page_alloc[i].page_offset + frag_info->frag_stride <=
107 ring_alloc[i].page_size)
110 if (mlx4_alloc_pages(priv, &page_alloc[i], frag_info, gfp))
114 for (i = 0; i < priv->num_frags; i++) {
115 frags[i] = ring_alloc[i];
116 dma = ring_alloc[i].dma + ring_alloc[i].page_offset;
117 ring_alloc[i] = page_alloc[i];
118 rx_desc->data[i].addr = cpu_to_be64(dma);
125 if (page_alloc[i].page != ring_alloc[i].page) {
126 dma_unmap_page(priv->ddev, page_alloc[i].dma,
127 page_alloc[i].page_size, PCI_DMA_FROMDEVICE);
128 page = page_alloc[i].page;
129 set_page_count(page, 1);
136 static void mlx4_en_free_frag(struct mlx4_en_priv *priv,
137 struct mlx4_en_rx_alloc *frags,
140 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
141 u32 next_frag_end = frags[i].page_offset + 2 * frag_info->frag_stride;
144 if (next_frag_end > frags[i].page_size)
145 dma_unmap_page(priv->ddev, frags[i].dma, frags[i].page_size,
149 put_page(frags[i].page);
152 static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
153 struct mlx4_en_rx_ring *ring)
156 struct mlx4_en_rx_alloc *page_alloc;
158 for (i = 0; i < priv->num_frags; i++) {
159 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
161 if (mlx4_alloc_pages(priv, &ring->page_alloc[i],
162 frag_info, GFP_KERNEL | __GFP_COLD))
165 en_dbg(DRV, priv, " frag %d allocator: - size:%d frags:%d\n",
166 i, ring->page_alloc[i].page_size,
167 page_ref_count(ring->page_alloc[i].page));
175 page_alloc = &ring->page_alloc[i];
176 dma_unmap_page(priv->ddev, page_alloc->dma,
177 page_alloc->page_size, PCI_DMA_FROMDEVICE);
178 page = page_alloc->page;
179 set_page_count(page, 1);
181 page_alloc->page = NULL;
186 static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
187 struct mlx4_en_rx_ring *ring)
189 struct mlx4_en_rx_alloc *page_alloc;
192 for (i = 0; i < priv->num_frags; i++) {
193 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
195 page_alloc = &ring->page_alloc[i];
196 en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
197 i, page_count(page_alloc->page));
199 dma_unmap_page(priv->ddev, page_alloc->dma,
200 page_alloc->page_size, PCI_DMA_FROMDEVICE);
201 while (page_alloc->page_offset + frag_info->frag_stride <
202 page_alloc->page_size) {
203 put_page(page_alloc->page);
204 page_alloc->page_offset += frag_info->frag_stride;
206 page_alloc->page = NULL;
210 static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
211 struct mlx4_en_rx_ring *ring, int index)
213 struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
217 /* Set size and memtype fields */
218 for (i = 0; i < priv->num_frags; i++) {
219 rx_desc->data[i].byte_count =
220 cpu_to_be32(priv->frag_info[i].frag_size);
221 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
224 /* If the number of used fragments does not fill up the ring stride,
225 * remaining (unused) fragments must be padded with null address/size
226 * and a special memory key */
227 possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
228 for (i = priv->num_frags; i < possible_frags; i++) {
229 rx_desc->data[i].byte_count = 0;
230 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
231 rx_desc->data[i].addr = 0;
235 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
236 struct mlx4_en_rx_ring *ring, int index,
239 struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
240 struct mlx4_en_rx_alloc *frags = ring->rx_info +
241 (index << priv->log_rx_info);
243 return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc, gfp);
246 static inline bool mlx4_en_is_ring_empty(struct mlx4_en_rx_ring *ring)
248 return ring->prod == ring->cons;
251 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
253 *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
256 static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
257 struct mlx4_en_rx_ring *ring,
260 struct mlx4_en_rx_alloc *frags;
263 frags = ring->rx_info + (index << priv->log_rx_info);
264 for (nr = 0; nr < priv->num_frags; nr++) {
265 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
266 mlx4_en_free_frag(priv, frags, nr);
270 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
272 struct mlx4_en_rx_ring *ring;
277 for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
278 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
279 ring = priv->rx_ring[ring_ind];
281 if (mlx4_en_prepare_rx_desc(priv, ring,
283 GFP_KERNEL | __GFP_COLD)) {
284 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
285 en_err(priv, "Failed to allocate enough rx buffers\n");
288 new_size = rounddown_pow_of_two(ring->actual_size);
289 en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n",
290 ring->actual_size, new_size);
301 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
302 ring = priv->rx_ring[ring_ind];
303 while (ring->actual_size > new_size) {
306 mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
313 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
314 struct mlx4_en_rx_ring *ring)
318 en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
319 ring->cons, ring->prod);
321 /* Unmap and free Rx buffers */
322 while (!mlx4_en_is_ring_empty(ring)) {
323 index = ring->cons & ring->size_mask;
324 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
325 mlx4_en_free_rx_desc(priv, ring, index);
330 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev)
335 struct mlx4_dev *dev = mdev->dev;
337 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
338 num_of_eqs = max_t(int, MIN_RX_RINGS,
340 mlx4_get_eqs_per_port(mdev->dev, i),
343 num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS :
344 min_t(int, num_of_eqs,
345 netif_get_num_default_rss_queues());
346 mdev->profile.prof[i].rx_ring_num =
347 rounddown_pow_of_two(num_rx_rings);
351 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
352 struct mlx4_en_rx_ring **pring,
353 u32 size, u16 stride, int node)
355 struct mlx4_en_dev *mdev = priv->mdev;
356 struct mlx4_en_rx_ring *ring;
360 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
362 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
364 en_err(priv, "Failed to allocate RX ring structure\n");
372 ring->size_mask = size - 1;
373 ring->stride = stride;
374 ring->log_stride = ffs(ring->stride) - 1;
375 ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
377 tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
378 sizeof(struct mlx4_en_rx_alloc));
379 ring->rx_info = vmalloc_node(tmp, node);
380 if (!ring->rx_info) {
381 ring->rx_info = vmalloc(tmp);
382 if (!ring->rx_info) {
388 en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
391 /* Allocate HW buffers on provided NUMA node */
392 set_dev_node(&mdev->dev->persist->pdev->dev, node);
393 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres,
394 ring->buf_size, 2 * PAGE_SIZE);
395 set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
399 err = mlx4_en_map_buffer(&ring->wqres.buf);
401 en_err(priv, "Failed to map RX buffer\n");
404 ring->buf = ring->wqres.buf.direct.buf;
406 ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter;
412 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
414 vfree(ring->rx_info);
415 ring->rx_info = NULL;
423 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
425 struct mlx4_en_rx_ring *ring;
429 int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
430 DS_SIZE * priv->num_frags);
432 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
433 ring = priv->rx_ring[ring_ind];
437 ring->actual_size = 0;
438 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn;
440 ring->stride = stride;
441 if (ring->stride <= TXBB_SIZE)
442 ring->buf += TXBB_SIZE;
444 ring->log_stride = ffs(ring->stride) - 1;
445 ring->buf_size = ring->size * ring->stride;
447 memset(ring->buf, 0, ring->buf_size);
448 mlx4_en_update_rx_prod_db(ring);
450 /* Initialize all descriptors */
451 for (i = 0; i < ring->size; i++)
452 mlx4_en_init_rx_desc(priv, ring, i);
454 /* Initialize page allocators */
455 err = mlx4_en_init_allocator(priv, ring);
457 en_err(priv, "Failed initializing ring allocator\n");
458 if (ring->stride <= TXBB_SIZE)
459 ring->buf -= TXBB_SIZE;
464 err = mlx4_en_fill_rx_buffers(priv);
468 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
469 ring = priv->rx_ring[ring_ind];
471 ring->size_mask = ring->actual_size - 1;
472 mlx4_en_update_rx_prod_db(ring);
478 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
479 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]);
481 ring_ind = priv->rx_ring_num - 1;
483 while (ring_ind >= 0) {
484 if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE)
485 priv->rx_ring[ring_ind]->buf -= TXBB_SIZE;
486 mlx4_en_destroy_allocator(priv, priv->rx_ring[ring_ind]);
492 /* We recover from out of memory by scheduling our napi poll
493 * function (mlx4_en_process_cq), which tries to allocate
494 * all missing RX buffers (call to mlx4_en_refill_rx_buffers).
496 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv)
503 for (ring = 0; ring < priv->rx_ring_num; ring++) {
504 if (mlx4_en_is_ring_empty(priv->rx_ring[ring]))
505 napi_reschedule(&priv->rx_cq[ring]->napi);
509 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
510 struct mlx4_en_rx_ring **pring,
511 u32 size, u16 stride)
513 struct mlx4_en_dev *mdev = priv->mdev;
514 struct mlx4_en_rx_ring *ring = *pring;
516 mlx4_en_unmap_buffer(&ring->wqres.buf);
517 mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE);
518 vfree(ring->rx_info);
519 ring->rx_info = NULL;
522 #ifdef CONFIG_RFS_ACCEL
523 mlx4_en_cleanup_filters(priv);
527 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
528 struct mlx4_en_rx_ring *ring)
530 mlx4_en_free_rx_buf(priv, ring);
531 if (ring->stride <= TXBB_SIZE)
532 ring->buf -= TXBB_SIZE;
533 mlx4_en_destroy_allocator(priv, ring);
537 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
538 struct mlx4_en_rx_desc *rx_desc,
539 struct mlx4_en_rx_alloc *frags,
543 struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags;
544 struct mlx4_en_frag_info *frag_info;
548 /* Collect used fragments while replacing them in the HW descriptors */
549 for (nr = 0; nr < priv->num_frags; nr++) {
550 frag_info = &priv->frag_info[nr];
551 if (length <= frag_info->frag_prefix_size)
556 dma = be64_to_cpu(rx_desc->data[nr].addr);
557 dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size,
560 /* Save page reference in skb */
561 __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page);
562 skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size);
563 skb_frags_rx[nr].page_offset = frags[nr].page_offset;
564 skb->truesize += frag_info->frag_stride;
565 frags[nr].page = NULL;
567 /* Adjust size of last fragment to match actual length */
569 skb_frag_size_set(&skb_frags_rx[nr - 1],
570 length - priv->frag_info[nr - 1].frag_prefix_size);
576 __skb_frag_unref(&skb_frags_rx[nr]);
582 static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
583 struct mlx4_en_rx_desc *rx_desc,
584 struct mlx4_en_rx_alloc *frags,
592 skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN);
594 en_dbg(RX_ERR, priv, "Failed allocating skb\n");
597 skb_reserve(skb, NET_IP_ALIGN);
600 /* Get pointer to first fragment so we could copy the headers into the
601 * (linear part of the) skb */
602 va = page_address(frags[0].page) + frags[0].page_offset;
604 if (length <= SMALL_PACKET_SIZE) {
605 /* We are copying all relevant data to the skb - temporarily
606 * sync buffers for the copy */
607 dma = be64_to_cpu(rx_desc->data[0].addr);
608 dma_sync_single_for_cpu(priv->ddev, dma, length,
610 skb_copy_to_linear_data(skb, va, length);
613 unsigned int pull_len;
615 /* Move relevant fragments to skb */
616 used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags,
618 if (unlikely(!used_frags)) {
622 skb_shinfo(skb)->nr_frags = used_frags;
624 pull_len = eth_get_headlen(va, SMALL_PACKET_SIZE);
625 /* Copy headers into the skb linear buffer */
626 memcpy(skb->data, va, pull_len);
627 skb->tail += pull_len;
629 /* Skip headers in first fragment */
630 skb_shinfo(skb)->frags[0].page_offset += pull_len;
632 /* Adjust size of first fragment */
633 skb_frag_size_sub(&skb_shinfo(skb)->frags[0], pull_len);
634 skb->data_len = length - pull_len;
639 static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb)
642 int offset = ETH_HLEN;
644 for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) {
645 if (*(skb->data + offset) != (unsigned char) (i & 0xff))
649 priv->loopback_ok = 1;
652 dev_kfree_skb_any(skb);
655 static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv,
656 struct mlx4_en_rx_ring *ring)
658 int index = ring->prod & ring->size_mask;
660 while ((u32) (ring->prod - ring->cons) < ring->actual_size) {
661 if (mlx4_en_prepare_rx_desc(priv, ring, index,
662 GFP_ATOMIC | __GFP_COLD))
665 index = ring->prod & ring->size_mask;
669 /* When hardware doesn't strip the vlan, we need to calculate the checksum
670 * over it and add it to the hardware's checksum calculation
672 static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum,
673 struct vlan_hdr *vlanh)
675 return csum_add(hw_checksum, *(__wsum *)vlanh);
678 /* Although the stack expects checksum which doesn't include the pseudo
679 * header, the HW adds it. To address that, we are subtracting the pseudo
680 * header checksum from the checksum value provided by the HW.
682 static void get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb,
685 __u16 length_for_csum = 0;
686 __wsum csum_pseudo_header = 0;
688 length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2));
689 csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr,
690 length_for_csum, iph->protocol, 0);
691 skb->csum = csum_sub(hw_checksum, csum_pseudo_header);
694 #if IS_ENABLED(CONFIG_IPV6)
695 /* In IPv6 packets, besides subtracting the pseudo header checksum,
696 * we also compute/add the IP header checksum which
697 * is not added by the HW.
699 static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb,
700 struct ipv6hdr *ipv6h)
702 __wsum csum_pseudo_hdr = 0;
704 if (ipv6h->nexthdr == IPPROTO_FRAGMENT || ipv6h->nexthdr == IPPROTO_HOPOPTS)
706 hw_checksum = csum_add(hw_checksum, (__force __wsum)(ipv6h->nexthdr << 8));
708 csum_pseudo_hdr = csum_partial(&ipv6h->saddr,
709 sizeof(ipv6h->saddr) + sizeof(ipv6h->daddr), 0);
710 csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ipv6h->payload_len);
711 csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ntohs(ipv6h->nexthdr));
713 skb->csum = csum_sub(hw_checksum, csum_pseudo_hdr);
714 skb->csum = csum_add(skb->csum, csum_partial(ipv6h, sizeof(struct ipv6hdr), 0));
718 static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va,
719 netdev_features_t dev_features)
721 __wsum hw_checksum = 0;
723 void *hdr = (u8 *)va + sizeof(struct ethhdr);
725 hw_checksum = csum_unfold((__force __sum16)cqe->checksum);
727 if (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK) &&
728 !(dev_features & NETIF_F_HW_VLAN_CTAG_RX)) {
729 hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr);
730 hdr += sizeof(struct vlan_hdr);
733 if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4))
734 get_fixed_ipv4_csum(hw_checksum, skb, hdr);
735 #if IS_ENABLED(CONFIG_IPV6)
736 else if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6))
737 if (get_fixed_ipv6_csum(hw_checksum, skb, hdr))
743 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
745 struct mlx4_en_priv *priv = netdev_priv(dev);
746 struct mlx4_en_dev *mdev = priv->mdev;
747 struct mlx4_cqe *cqe;
748 struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring];
749 struct mlx4_en_rx_alloc *frags;
750 struct mlx4_en_rx_desc *rx_desc;
757 int factor = priv->cqe_factor;
767 /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
768 * descriptor offset can be deduced from the CQE index instead of
769 * reading 'cqe->index' */
770 index = cq->mcq.cons_index & ring->size_mask;
771 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
773 /* Process all completed CQEs */
774 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
775 cq->mcq.cons_index & cq->size)) {
777 frags = ring->rx_info + (index << priv->log_rx_info);
778 rx_desc = ring->buf + (index << ring->log_stride);
781 * make sure we read the CQE after we read the ownership bit
785 /* Drop packet on bad receive or bad checksum */
786 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
787 MLX4_CQE_OPCODE_ERROR)) {
788 en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n",
789 ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome,
790 ((struct mlx4_err_cqe *)cqe)->syndrome);
793 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
794 en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
798 /* Check if we need to drop the packet if SRIOV is not enabled
799 * and not performing the selftest or flb disabled
801 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) {
804 /* Get pointer to first fragment since we haven't
805 * skb yet and cast it to ethhdr struct
807 dma = be64_to_cpu(rx_desc->data[0].addr);
808 dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh),
810 ethh = (struct ethhdr *)(page_address(frags[0].page) +
811 frags[0].page_offset);
813 if (is_multicast_ether_addr(ethh->h_dest)) {
814 struct mlx4_mac_entry *entry;
815 struct hlist_head *bucket;
816 unsigned int mac_hash;
818 /* Drop the packet, since HW loopback-ed it */
819 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX];
820 bucket = &priv->mac_hash[mac_hash];
822 hlist_for_each_entry_rcu(entry, bucket, hlist) {
823 if (ether_addr_equal_64bits(entry->mac,
834 * Packet is OK - process it.
836 length = be32_to_cpu(cqe->byte_cnt);
837 length -= ring->fcs_del;
838 ring->bytes += length;
840 l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) &&
841 (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL));
843 if (likely(dev->features & NETIF_F_RXCSUM)) {
844 if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP |
845 MLX4_CQE_STATUS_UDP)) {
846 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
847 cqe->checksum == cpu_to_be16(0xffff)) {
848 ip_summed = CHECKSUM_UNNECESSARY;
851 ip_summed = CHECKSUM_NONE;
855 if (priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP &&
856 (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
857 MLX4_CQE_STATUS_IPV6))) {
858 ip_summed = CHECKSUM_COMPLETE;
859 ring->csum_complete++;
861 ip_summed = CHECKSUM_NONE;
866 ip_summed = CHECKSUM_NONE;
870 /* This packet is eligible for GRO if it is:
871 * - DIX Ethernet (type interpretation)
873 * - without IP options
874 * - not an IP fragment
876 if (dev->features & NETIF_F_GRO) {
877 struct sk_buff *gro_skb = napi_get_frags(&cq->napi);
881 nr = mlx4_en_complete_rx_desc(priv,
882 rx_desc, frags, gro_skb,
887 if (ip_summed == CHECKSUM_COMPLETE) {
888 void *va = skb_frag_address(skb_shinfo(gro_skb)->frags);
889 if (check_csum(cqe, gro_skb, va,
891 ip_summed = CHECKSUM_NONE;
893 ring->csum_complete--;
897 skb_shinfo(gro_skb)->nr_frags = nr;
898 gro_skb->len = length;
899 gro_skb->data_len = length;
900 gro_skb->ip_summed = ip_summed;
902 if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
903 gro_skb->csum_level = 1;
905 if ((cqe->vlan_my_qpn &
906 cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK)) &&
907 (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
908 u16 vid = be16_to_cpu(cqe->sl_vid);
910 __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid);
911 } else if ((be32_to_cpu(cqe->vlan_my_qpn) &
912 MLX4_CQE_SVLAN_PRESENT_MASK) &&
913 (dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
914 __vlan_hwaccel_put_tag(gro_skb,
916 be16_to_cpu(cqe->sl_vid));
919 if (dev->features & NETIF_F_RXHASH)
920 skb_set_hash(gro_skb,
921 be32_to_cpu(cqe->immed_rss_invalid),
922 (ip_summed == CHECKSUM_UNNECESSARY) ?
926 skb_record_rx_queue(gro_skb, cq->ring);
928 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
929 timestamp = mlx4_en_get_cqe_ts(cqe);
930 mlx4_en_fill_hwtstamps(mdev,
931 skb_hwtstamps(gro_skb),
935 napi_gro_frags(&cq->napi);
939 /* GRO not possible, complete processing here */
940 skb = mlx4_en_rx_skb(priv, rx_desc, frags, length);
942 priv->stats.rx_dropped++;
946 if (unlikely(priv->validate_loopback)) {
947 validate_loopback(priv, skb);
951 if (ip_summed == CHECKSUM_COMPLETE) {
952 if (check_csum(cqe, skb, skb->data, dev->features)) {
953 ip_summed = CHECKSUM_NONE;
954 ring->csum_complete--;
959 skb->ip_summed = ip_summed;
960 skb->protocol = eth_type_trans(skb, dev);
961 skb_record_rx_queue(skb, cq->ring);
963 if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
966 if (dev->features & NETIF_F_RXHASH)
968 be32_to_cpu(cqe->immed_rss_invalid),
969 (ip_summed == CHECKSUM_UNNECESSARY) ?
973 if ((be32_to_cpu(cqe->vlan_my_qpn) &
974 MLX4_CQE_CVLAN_PRESENT_MASK) &&
975 (dev->features & NETIF_F_HW_VLAN_CTAG_RX))
976 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid));
977 else if ((be32_to_cpu(cqe->vlan_my_qpn) &
978 MLX4_CQE_SVLAN_PRESENT_MASK) &&
979 (dev->features & NETIF_F_HW_VLAN_STAG_RX))
980 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD),
981 be16_to_cpu(cqe->sl_vid));
983 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
984 timestamp = mlx4_en_get_cqe_ts(cqe);
985 mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb),
989 napi_gro_receive(&cq->napi, skb);
991 for (nr = 0; nr < priv->num_frags; nr++)
992 mlx4_en_free_frag(priv, frags, nr);
994 ++cq->mcq.cons_index;
995 index = (cq->mcq.cons_index) & ring->size_mask;
996 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
997 if (++polled == budget)
1002 AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
1003 mlx4_cq_set_ci(&cq->mcq);
1004 wmb(); /* ensure HW sees CQ consumer before we post new buffers */
1005 ring->cons = cq->mcq.cons_index;
1006 mlx4_en_refill_rx_buffers(priv, ring);
1007 mlx4_en_update_rx_prod_db(ring);
1012 void mlx4_en_rx_irq(struct mlx4_cq *mcq)
1014 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
1015 struct mlx4_en_priv *priv = netdev_priv(cq->dev);
1017 if (likely(priv->port_up))
1018 napi_schedule_irqoff(&cq->napi);
1020 mlx4_en_arm_cq(priv, cq);
1023 /* Rx CQ polling - called by NAPI */
1024 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
1026 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
1027 struct net_device *dev = cq->dev;
1028 struct mlx4_en_priv *priv = netdev_priv(dev);
1031 done = mlx4_en_process_rx_cq(dev, cq, budget);
1033 /* If we used up all the quota - we're probably not done yet... */
1034 if (done == budget) {
1035 const struct cpumask *aff;
1036 struct irq_data *idata;
1039 INC_PERF_COUNTER(priv->pstats.napi_quota);
1041 cpu_curr = smp_processor_id();
1042 idata = irq_desc_get_irq_data(cq->irq_desc);
1043 aff = irq_data_get_affinity_mask(idata);
1045 if (likely(cpumask_test_cpu(cpu_curr, aff)))
1048 /* Current cpu is not according to smp_irq_affinity -
1049 * probably affinity changed. need to stop this NAPI
1050 * poll, and restart it on the right CPU
1055 napi_complete_done(napi, done);
1056 mlx4_en_arm_cq(priv, cq);
1060 static const int frag_sizes[] = {
1067 void mlx4_en_calc_rx_buf(struct net_device *dev)
1069 struct mlx4_en_priv *priv = netdev_priv(dev);
1070 /* VLAN_HLEN is added twice,to support skb vlan tagged with multiple
1071 * headers. (For example: ETH_P_8021Q and ETH_P_8021AD).
1073 int eff_mtu = dev->mtu + ETH_HLEN + (2 * VLAN_HLEN);
1077 while (buf_size < eff_mtu) {
1078 priv->frag_info[i].frag_size =
1079 (eff_mtu > buf_size + frag_sizes[i]) ?
1080 frag_sizes[i] : eff_mtu - buf_size;
1081 priv->frag_info[i].frag_prefix_size = buf_size;
1082 priv->frag_info[i].frag_stride =
1083 ALIGN(priv->frag_info[i].frag_size,
1085 buf_size += priv->frag_info[i].frag_size;
1089 priv->num_frags = i;
1090 priv->rx_skb_size = eff_mtu;
1091 priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc));
1093 en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n",
1094 eff_mtu, priv->num_frags);
1095 for (i = 0; i < priv->num_frags; i++) {
1097 " frag:%d - size:%d prefix:%d stride:%d\n",
1099 priv->frag_info[i].frag_size,
1100 priv->frag_info[i].frag_prefix_size,
1101 priv->frag_info[i].frag_stride);
1105 /* RSS related functions */
1107 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
1108 struct mlx4_en_rx_ring *ring,
1109 enum mlx4_qp_state *state,
1112 struct mlx4_en_dev *mdev = priv->mdev;
1113 struct mlx4_qp_context *context;
1116 context = kmalloc(sizeof(*context), GFP_KERNEL);
1120 err = mlx4_qp_alloc(mdev->dev, qpn, qp, GFP_KERNEL);
1122 en_err(priv, "Failed to allocate qp #%x\n", qpn);
1125 qp->event = mlx4_en_sqp_event;
1127 memset(context, 0, sizeof *context);
1128 mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
1129 qpn, ring->cqn, -1, context);
1130 context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
1132 /* Cancel FCS removal if FW allows */
1133 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
1134 context->param3 |= cpu_to_be32(1 << 29);
1135 if (priv->dev->features & NETIF_F_RXFCS)
1138 ring->fcs_del = ETH_FCS_LEN;
1142 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
1144 mlx4_qp_remove(mdev->dev, qp);
1145 mlx4_qp_free(mdev->dev, qp);
1147 mlx4_en_update_rx_prod_db(ring);
1153 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv)
1158 err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn,
1159 MLX4_RESERVE_A0_QP);
1161 en_err(priv, "Failed reserving drop qpn\n");
1164 err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp, GFP_KERNEL);
1166 en_err(priv, "Failed allocating drop qp\n");
1167 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1174 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv)
1178 qpn = priv->drop_qp.qpn;
1179 mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp);
1180 mlx4_qp_free(priv->mdev->dev, &priv->drop_qp);
1181 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1184 /* Allocate rx qp's and configure them according to rss map */
1185 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
1187 struct mlx4_en_dev *mdev = priv->mdev;
1188 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1189 struct mlx4_qp_context context;
1190 struct mlx4_rss_context *rss_context;
1193 u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
1199 en_dbg(DRV, priv, "Configuring rss steering\n");
1200 err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
1202 &rss_map->base_qpn, 0);
1204 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
1208 for (i = 0; i < priv->rx_ring_num; i++) {
1209 qpn = rss_map->base_qpn + i;
1210 err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i],
1219 /* Configure RSS indirection qp */
1220 err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp, GFP_KERNEL);
1222 en_err(priv, "Failed to allocate RSS indirection QP\n");
1225 rss_map->indir_qp.event = mlx4_en_sqp_event;
1226 mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
1227 priv->rx_ring[0]->cqn, -1, &context);
1229 if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)
1230 rss_rings = priv->rx_ring_num;
1232 rss_rings = priv->prof->rss_rings;
1234 ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)
1235 + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
1237 rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 |
1238 (rss_map->base_qpn));
1239 rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
1240 if (priv->mdev->profile.udp_rss) {
1241 rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
1242 rss_context->base_qpn_udp = rss_context->default_qpn;
1245 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1246 en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n");
1247 rss_mask |= MLX4_RSS_BY_INNER_HEADERS;
1250 rss_context->flags = rss_mask;
1251 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1252 if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) {
1253 rss_context->hash_fn = MLX4_RSS_HASH_XOR;
1254 } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) {
1255 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1256 memcpy(rss_context->rss_key, priv->rss_key,
1257 MLX4_EN_RSS_KEY_SIZE);
1259 en_err(priv, "Unknown RSS hash function requested\n");
1263 err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
1264 &rss_map->indir_qp, &rss_map->indir_state);
1271 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1272 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1273 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1274 mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1276 for (i = 0; i < good_qps; i++) {
1277 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1278 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1279 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1280 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1282 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1286 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
1288 struct mlx4_en_dev *mdev = priv->mdev;
1289 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1292 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1293 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1294 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1295 mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1297 for (i = 0; i < priv->rx_ring_num; i++) {
1298 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1299 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1300 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1301 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1303 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);