1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
9 #include <linux/of_device.h>
10 #include <linux/of_mdio.h>
11 #include <linux/of_net.h>
12 #include <linux/of_address.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/regmap.h>
15 #include <linux/clk.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/if_vlan.h>
18 #include <linux/reset.h>
19 #include <linux/tcp.h>
20 #include <linux/interrupt.h>
21 #include <linux/pinctrl/devinfo.h>
22 #include <linux/phylink.h>
23 #include <linux/pcs/pcs-mtk-lynxi.h>
24 #include <linux/jhash.h>
25 #include <linux/bitfield.h>
27 #include <net/dst_metadata.h>
29 #include "mtk_eth_soc.h"
32 static int mtk_msg_level = -1;
33 module_param_named(msg_level, mtk_msg_level, int, 0);
34 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
36 #define MTK_ETHTOOL_STAT(x) { #x, \
37 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
39 #define MTK_ETHTOOL_XDP_STAT(x) { #x, \
40 offsetof(struct mtk_hw_stats, xdp_stats.x) / \
43 static const struct mtk_reg_map mtk_reg_map = {
44 .tx_irq_mask = 0x1a1c,
45 .tx_irq_status = 0x1a18,
55 .adma_rx_dbg0 = 0x0a38,
68 .tx_sch_rate = 0x1a14,
81 .gdma_to_ppe = 0x4444,
91 static const struct mtk_reg_map mt7628_reg_map = {
92 .tx_irq_mask = 0x0a28,
93 .tx_irq_status = 0x0a20,
101 .irq_status = 0x0a20,
107 static const struct mtk_reg_map mt7986_reg_map = {
108 .tx_irq_mask = 0x461c,
109 .tx_irq_status = 0x4618,
112 .rx_cnt_cfg = 0x6104,
117 .irq_status = 0x6220,
119 .adma_rx_dbg0 = 0x6238,
126 .rx_cnt_cfg = 0x4504,
142 .tx_sch_rate = 0x4798,
145 .gdma_to_ppe = 0x3333,
151 .pse_iq_sta = 0x0180,
152 .pse_oq_sta = 0x01a0,
155 /* strings used by ethtool */
156 static const struct mtk_ethtool_stats {
157 char str[ETH_GSTRING_LEN];
159 } mtk_ethtool_stats[] = {
160 MTK_ETHTOOL_STAT(tx_bytes),
161 MTK_ETHTOOL_STAT(tx_packets),
162 MTK_ETHTOOL_STAT(tx_skip),
163 MTK_ETHTOOL_STAT(tx_collisions),
164 MTK_ETHTOOL_STAT(rx_bytes),
165 MTK_ETHTOOL_STAT(rx_packets),
166 MTK_ETHTOOL_STAT(rx_overflow),
167 MTK_ETHTOOL_STAT(rx_fcs_errors),
168 MTK_ETHTOOL_STAT(rx_short_errors),
169 MTK_ETHTOOL_STAT(rx_long_errors),
170 MTK_ETHTOOL_STAT(rx_checksum_errors),
171 MTK_ETHTOOL_STAT(rx_flow_control_packets),
172 MTK_ETHTOOL_XDP_STAT(rx_xdp_redirect),
173 MTK_ETHTOOL_XDP_STAT(rx_xdp_pass),
174 MTK_ETHTOOL_XDP_STAT(rx_xdp_drop),
175 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx),
176 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx_errors),
177 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit),
178 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit_errors),
181 static const char * const mtk_clks_source_name[] = {
182 "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll",
183 "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb",
184 "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb",
185 "sgmii_ck", "eth2pll", "wocpu0", "wocpu1", "netsys0", "netsys1"
188 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
190 __raw_writel(val, eth->base + reg);
193 u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
195 return __raw_readl(eth->base + reg);
198 static u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg)
202 val = mtk_r32(eth, reg);
205 mtk_w32(eth, val, reg);
209 static int mtk_mdio_busy_wait(struct mtk_eth *eth)
211 unsigned long t_start = jiffies;
214 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
216 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
221 dev_err(eth->dev, "mdio: MDIO timeout\n");
225 static int _mtk_mdio_write_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg,
230 ret = mtk_mdio_busy_wait(eth);
234 mtk_w32(eth, PHY_IAC_ACCESS |
237 PHY_IAC_REG(phy_reg) |
238 PHY_IAC_ADDR(phy_addr) |
239 PHY_IAC_DATA(write_data),
242 ret = mtk_mdio_busy_wait(eth);
249 static int _mtk_mdio_write_c45(struct mtk_eth *eth, u32 phy_addr,
250 u32 devad, u32 phy_reg, u32 write_data)
254 ret = mtk_mdio_busy_wait(eth);
258 mtk_w32(eth, PHY_IAC_ACCESS |
260 PHY_IAC_CMD_C45_ADDR |
262 PHY_IAC_ADDR(phy_addr) |
263 PHY_IAC_DATA(phy_reg),
266 ret = mtk_mdio_busy_wait(eth);
270 mtk_w32(eth, PHY_IAC_ACCESS |
274 PHY_IAC_ADDR(phy_addr) |
275 PHY_IAC_DATA(write_data),
278 ret = mtk_mdio_busy_wait(eth);
285 static int _mtk_mdio_read_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg)
289 ret = mtk_mdio_busy_wait(eth);
293 mtk_w32(eth, PHY_IAC_ACCESS |
295 PHY_IAC_CMD_C22_READ |
296 PHY_IAC_REG(phy_reg) |
297 PHY_IAC_ADDR(phy_addr),
300 ret = mtk_mdio_busy_wait(eth);
304 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK;
307 static int _mtk_mdio_read_c45(struct mtk_eth *eth, u32 phy_addr,
308 u32 devad, u32 phy_reg)
312 ret = mtk_mdio_busy_wait(eth);
316 mtk_w32(eth, PHY_IAC_ACCESS |
318 PHY_IAC_CMD_C45_ADDR |
320 PHY_IAC_ADDR(phy_addr) |
321 PHY_IAC_DATA(phy_reg),
324 ret = mtk_mdio_busy_wait(eth);
328 mtk_w32(eth, PHY_IAC_ACCESS |
330 PHY_IAC_CMD_C45_READ |
332 PHY_IAC_ADDR(phy_addr),
335 ret = mtk_mdio_busy_wait(eth);
339 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK;
342 static int mtk_mdio_write_c22(struct mii_bus *bus, int phy_addr,
343 int phy_reg, u16 val)
345 struct mtk_eth *eth = bus->priv;
347 return _mtk_mdio_write_c22(eth, phy_addr, phy_reg, val);
350 static int mtk_mdio_write_c45(struct mii_bus *bus, int phy_addr,
351 int devad, int phy_reg, u16 val)
353 struct mtk_eth *eth = bus->priv;
355 return _mtk_mdio_write_c45(eth, phy_addr, devad, phy_reg, val);
358 static int mtk_mdio_read_c22(struct mii_bus *bus, int phy_addr, int phy_reg)
360 struct mtk_eth *eth = bus->priv;
362 return _mtk_mdio_read_c22(eth, phy_addr, phy_reg);
365 static int mtk_mdio_read_c45(struct mii_bus *bus, int phy_addr, int devad,
368 struct mtk_eth *eth = bus->priv;
370 return _mtk_mdio_read_c45(eth, phy_addr, devad, phy_reg);
373 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth,
374 phy_interface_t interface)
378 val = (interface == PHY_INTERFACE_MODE_TRGMII) ?
379 ETHSYS_TRGMII_MT7621_DDR_PLL : 0;
381 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
382 ETHSYS_TRGMII_MT7621_MASK, val);
387 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth,
388 phy_interface_t interface, int speed)
394 if (interface == PHY_INTERFACE_MODE_TRGMII) {
395 mtk_w32(eth, TRGMII_MODE, INTF_MODE);
396 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], 500000000);
398 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
402 if (speed == SPEED_1000) {
403 intf = INTF_MODE_RGMII_1000;
405 rck = RCK_CTRL_RGMII_1000;
406 tck = TCK_CTRL_RGMII_1000;
408 intf = INTF_MODE_RGMII_10_100;
410 rck = RCK_CTRL_RGMII_10_100;
411 tck = TCK_CTRL_RGMII_10_100;
414 mtk_w32(eth, intf, INTF_MODE);
416 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
417 ETHSYS_TRGMII_CLK_SEL362_5,
418 ETHSYS_TRGMII_CLK_SEL362_5);
420 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], rate);
422 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
424 mtk_w32(eth, rck, TRGMII_RCK_CTRL);
425 mtk_w32(eth, tck, TRGMII_TCK_CTRL);
428 static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
429 phy_interface_t interface)
431 struct mtk_mac *mac = container_of(config, struct mtk_mac,
433 struct mtk_eth *eth = mac->hw;
436 if (interface == PHY_INTERFACE_MODE_SGMII ||
437 phy_interface_mode_is_8023z(interface)) {
438 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
441 return eth->sgmii_pcs[sid];
447 static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
448 const struct phylink_link_state *state)
450 struct mtk_mac *mac = container_of(config, struct mtk_mac,
452 struct mtk_eth *eth = mac->hw;
453 int val, ge_mode, err = 0;
456 /* MT76x8 has no hardware settings between for the MAC */
457 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
458 mac->interface != state->interface) {
459 /* Setup soc pin functions */
460 switch (state->interface) {
461 case PHY_INTERFACE_MODE_TRGMII:
462 case PHY_INTERFACE_MODE_RGMII_TXID:
463 case PHY_INTERFACE_MODE_RGMII_RXID:
464 case PHY_INTERFACE_MODE_RGMII_ID:
465 case PHY_INTERFACE_MODE_RGMII:
466 case PHY_INTERFACE_MODE_MII:
467 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) {
468 err = mtk_gmac_rgmii_path_setup(eth, mac->id);
473 case PHY_INTERFACE_MODE_1000BASEX:
474 case PHY_INTERFACE_MODE_2500BASEX:
475 case PHY_INTERFACE_MODE_SGMII:
476 err = mtk_gmac_sgmii_path_setup(eth, mac->id);
480 case PHY_INTERFACE_MODE_GMII:
481 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) {
482 err = mtk_gmac_gephy_path_setup(eth, mac->id);
491 /* Setup clock for 1st gmac */
492 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII &&
493 !phy_interface_mode_is_8023z(state->interface) &&
494 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) {
495 if (MTK_HAS_CAPS(mac->hw->soc->caps,
496 MTK_TRGMII_MT7621_CLK)) {
497 if (mt7621_gmac0_rgmii_adjust(mac->hw,
501 /* FIXME: this is incorrect. Not only does it
502 * use state->speed (which is not guaranteed
503 * to be correct) but it also makes use of it
504 * in a code path that will only be reachable
505 * when the PHY interface mode changes, not
506 * when the speed changes. Consequently, RGMII
507 * is probably broken.
509 mtk_gmac0_rgmii_adjust(mac->hw,
513 /* mt7623_pad_clk_setup */
514 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
516 TD_DM_DRVP(8) | TD_DM_DRVN(8),
519 /* Assert/release MT7623 RXC reset */
520 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL,
522 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL);
526 switch (state->interface) {
527 case PHY_INTERFACE_MODE_MII:
528 case PHY_INTERFACE_MODE_GMII:
536 /* put the gmac into the right mode */
537 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
538 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
539 val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
540 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
542 mac->interface = state->interface;
546 if (state->interface == PHY_INTERFACE_MODE_SGMII ||
547 phy_interface_mode_is_8023z(state->interface)) {
548 /* The path GMAC to SGMII will be enabled once the SGMIISYS is
551 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
553 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
555 ~(u32)SYSCFG0_SGMII_MASK);
557 /* Save the syscfg0 value for mac_finish */
559 } else if (phylink_autoneg_inband(mode)) {
561 "In-band mode not supported in non SGMII mode!\n");
568 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__,
569 mac->id, phy_modes(state->interface));
573 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__,
574 mac->id, phy_modes(state->interface), err);
577 static int mtk_mac_finish(struct phylink_config *config, unsigned int mode,
578 phy_interface_t interface)
580 struct mtk_mac *mac = container_of(config, struct mtk_mac,
582 struct mtk_eth *eth = mac->hw;
583 u32 mcr_cur, mcr_new;
586 if (interface == PHY_INTERFACE_MODE_SGMII ||
587 phy_interface_mode_is_8023z(interface))
588 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
589 SYSCFG0_SGMII_MASK, mac->syscfg0);
592 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
594 mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE |
595 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK |
596 MAC_MCR_RX_FIFO_CLR_DIS;
598 /* Only update control register when needed! */
599 if (mcr_new != mcr_cur)
600 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
605 static void mtk_mac_pcs_get_state(struct phylink_config *config,
606 struct phylink_link_state *state)
608 struct mtk_mac *mac = container_of(config, struct mtk_mac,
610 u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id));
612 state->link = (pmsr & MAC_MSR_LINK);
613 state->duplex = (pmsr & MAC_MSR_DPX) >> 1;
615 switch (pmsr & (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)) {
617 state->speed = SPEED_10;
619 case MAC_MSR_SPEED_100:
620 state->speed = SPEED_100;
622 case MAC_MSR_SPEED_1000:
623 state->speed = SPEED_1000;
626 state->speed = SPEED_UNKNOWN;
630 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
631 if (pmsr & MAC_MSR_RX_FC)
632 state->pause |= MLO_PAUSE_RX;
633 if (pmsr & MAC_MSR_TX_FC)
634 state->pause |= MLO_PAUSE_TX;
637 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
638 phy_interface_t interface)
640 struct mtk_mac *mac = container_of(config, struct mtk_mac,
642 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
644 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN);
645 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
648 static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx,
651 const struct mtk_soc_data *soc = eth->soc;
654 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA))
657 val = MTK_QTX_SCH_MIN_RATE_EN |
658 /* minimum: 10 Mbps */
659 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
660 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
661 MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
662 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
663 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
665 if (IS_ENABLED(CONFIG_SOC_MT7621)) {
668 val |= MTK_QTX_SCH_MAX_RATE_EN |
669 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) |
670 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 2) |
671 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1);
674 val |= MTK_QTX_SCH_MAX_RATE_EN |
675 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) |
676 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 3);
677 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1);
680 val |= MTK_QTX_SCH_MAX_RATE_EN |
681 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 105) |
682 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) |
683 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10);
691 val |= MTK_QTX_SCH_MAX_RATE_EN |
692 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) |
693 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) |
694 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1);
697 val |= MTK_QTX_SCH_MAX_RATE_EN |
698 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) |
699 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5);
700 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1);
703 val |= MTK_QTX_SCH_MAX_RATE_EN |
704 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 10) |
705 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5) |
706 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10);
713 ofs = MTK_QTX_OFFSET * idx;
714 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
717 static void mtk_mac_link_up(struct phylink_config *config,
718 struct phy_device *phy,
719 unsigned int mode, phy_interface_t interface,
720 int speed, int duplex, bool tx_pause, bool rx_pause)
722 struct mtk_mac *mac = container_of(config, struct mtk_mac,
726 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
727 mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 |
728 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC |
729 MAC_MCR_FORCE_RX_FC);
731 /* Configure speed */
736 mcr |= MAC_MCR_SPEED_1000;
739 mcr |= MAC_MCR_SPEED_100;
743 /* Configure duplex */
744 if (duplex == DUPLEX_FULL)
745 mcr |= MAC_MCR_FORCE_DPX;
747 /* Configure pause modes - phylink will avoid these for half duplex */
749 mcr |= MAC_MCR_FORCE_TX_FC;
751 mcr |= MAC_MCR_FORCE_RX_FC;
753 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN;
754 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
757 static const struct phylink_mac_ops mtk_phylink_ops = {
758 .mac_select_pcs = mtk_mac_select_pcs,
759 .mac_pcs_get_state = mtk_mac_pcs_get_state,
760 .mac_config = mtk_mac_config,
761 .mac_finish = mtk_mac_finish,
762 .mac_link_down = mtk_mac_link_down,
763 .mac_link_up = mtk_mac_link_up,
766 static int mtk_mdio_init(struct mtk_eth *eth)
768 unsigned int max_clk = 2500000, divider;
769 struct device_node *mii_np;
773 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
775 dev_err(eth->dev, "no %s child node found", "mdio-bus");
779 if (!of_device_is_available(mii_np)) {
784 eth->mii_bus = devm_mdiobus_alloc(eth->dev);
790 eth->mii_bus->name = "mdio";
791 eth->mii_bus->read = mtk_mdio_read_c22;
792 eth->mii_bus->write = mtk_mdio_write_c22;
793 eth->mii_bus->read_c45 = mtk_mdio_read_c45;
794 eth->mii_bus->write_c45 = mtk_mdio_write_c45;
795 eth->mii_bus->priv = eth;
796 eth->mii_bus->parent = eth->dev;
798 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
800 if (!of_property_read_u32(mii_np, "clock-frequency", &val)) {
801 if (val > MDC_MAX_FREQ || val < MDC_MAX_FREQ / MDC_MAX_DIVIDER) {
802 dev_err(eth->dev, "MDIO clock frequency out of range");
808 divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63);
810 /* Configure MDC Divider */
811 val = mtk_r32(eth, MTK_PPSC);
812 val &= ~PPSC_MDC_CFG;
813 val |= FIELD_PREP(PPSC_MDC_CFG, divider) | PPSC_MDC_TURBO;
814 mtk_w32(eth, val, MTK_PPSC);
816 dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider);
818 ret = of_mdiobus_register(eth->mii_bus, mii_np);
825 static void mtk_mdio_cleanup(struct mtk_eth *eth)
830 mdiobus_unregister(eth->mii_bus);
833 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask)
838 spin_lock_irqsave(ð->tx_irq_lock, flags);
839 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask);
840 mtk_w32(eth, val & ~mask, eth->soc->reg_map->tx_irq_mask);
841 spin_unlock_irqrestore(ð->tx_irq_lock, flags);
844 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask)
849 spin_lock_irqsave(ð->tx_irq_lock, flags);
850 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask);
851 mtk_w32(eth, val | mask, eth->soc->reg_map->tx_irq_mask);
852 spin_unlock_irqrestore(ð->tx_irq_lock, flags);
855 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask)
860 spin_lock_irqsave(ð->rx_irq_lock, flags);
861 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask);
862 mtk_w32(eth, val & ~mask, eth->soc->reg_map->pdma.irq_mask);
863 spin_unlock_irqrestore(ð->rx_irq_lock, flags);
866 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask)
871 spin_lock_irqsave(ð->rx_irq_lock, flags);
872 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask);
873 mtk_w32(eth, val | mask, eth->soc->reg_map->pdma.irq_mask);
874 spin_unlock_irqrestore(ð->rx_irq_lock, flags);
877 static int mtk_set_mac_address(struct net_device *dev, void *p)
879 int ret = eth_mac_addr(dev, p);
880 struct mtk_mac *mac = netdev_priv(dev);
881 struct mtk_eth *eth = mac->hw;
882 const char *macaddr = dev->dev_addr;
887 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
890 spin_lock_bh(&mac->hw->page_lock);
891 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
892 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
893 MT7628_SDM_MAC_ADRH);
894 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
895 (macaddr[4] << 8) | macaddr[5],
896 MT7628_SDM_MAC_ADRL);
898 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
899 MTK_GDMA_MAC_ADRH(mac->id));
900 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
901 (macaddr[4] << 8) | macaddr[5],
902 MTK_GDMA_MAC_ADRL(mac->id));
904 spin_unlock_bh(&mac->hw->page_lock);
909 void mtk_stats_update_mac(struct mtk_mac *mac)
911 struct mtk_hw_stats *hw_stats = mac->hw_stats;
912 struct mtk_eth *eth = mac->hw;
914 u64_stats_update_begin(&hw_stats->syncp);
916 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
917 hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT);
918 hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT);
919 hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT);
920 hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT);
921 hw_stats->rx_checksum_errors +=
922 mtk_r32(mac->hw, MT7628_SDM_CS_ERR);
924 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
925 unsigned int offs = hw_stats->reg_offset;
928 hw_stats->rx_bytes += mtk_r32(mac->hw, reg_map->gdm1_cnt + offs);
929 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x4 + offs);
931 hw_stats->rx_bytes += (stats << 32);
932 hw_stats->rx_packets +=
933 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x8 + offs);
934 hw_stats->rx_overflow +=
935 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x10 + offs);
936 hw_stats->rx_fcs_errors +=
937 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x14 + offs);
938 hw_stats->rx_short_errors +=
939 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x18 + offs);
940 hw_stats->rx_long_errors +=
941 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x1c + offs);
942 hw_stats->rx_checksum_errors +=
943 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs);
944 hw_stats->rx_flow_control_packets +=
945 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs);
947 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs);
948 hw_stats->tx_collisions +=
949 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs);
950 hw_stats->tx_bytes +=
951 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs);
952 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs);
954 hw_stats->tx_bytes += (stats << 32);
955 hw_stats->tx_packets +=
956 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs);
959 u64_stats_update_end(&hw_stats->syncp);
962 static void mtk_stats_update(struct mtk_eth *eth)
966 for (i = 0; i < MTK_MAC_COUNT; i++) {
967 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
969 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) {
970 mtk_stats_update_mac(eth->mac[i]);
971 spin_unlock(ð->mac[i]->hw_stats->stats_lock);
976 static void mtk_get_stats64(struct net_device *dev,
977 struct rtnl_link_stats64 *storage)
979 struct mtk_mac *mac = netdev_priv(dev);
980 struct mtk_hw_stats *hw_stats = mac->hw_stats;
983 if (netif_running(dev) && netif_device_present(dev)) {
984 if (spin_trylock_bh(&hw_stats->stats_lock)) {
985 mtk_stats_update_mac(mac);
986 spin_unlock_bh(&hw_stats->stats_lock);
991 start = u64_stats_fetch_begin(&hw_stats->syncp);
992 storage->rx_packets = hw_stats->rx_packets;
993 storage->tx_packets = hw_stats->tx_packets;
994 storage->rx_bytes = hw_stats->rx_bytes;
995 storage->tx_bytes = hw_stats->tx_bytes;
996 storage->collisions = hw_stats->tx_collisions;
997 storage->rx_length_errors = hw_stats->rx_short_errors +
998 hw_stats->rx_long_errors;
999 storage->rx_over_errors = hw_stats->rx_overflow;
1000 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
1001 storage->rx_errors = hw_stats->rx_checksum_errors;
1002 storage->tx_aborted_errors = hw_stats->tx_skip;
1003 } while (u64_stats_fetch_retry(&hw_stats->syncp, start));
1005 storage->tx_errors = dev->stats.tx_errors;
1006 storage->rx_dropped = dev->stats.rx_dropped;
1007 storage->tx_dropped = dev->stats.tx_dropped;
1010 static inline int mtk_max_frag_size(int mtu)
1012 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
1013 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH_2K)
1014 mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN;
1016 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
1017 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
1020 static inline int mtk_max_buf_size(int frag_size)
1022 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
1023 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
1025 WARN_ON(buf_size < MTK_MAX_RX_LENGTH_2K);
1030 static bool mtk_rx_get_desc(struct mtk_eth *eth, struct mtk_rx_dma_v2 *rxd,
1031 struct mtk_rx_dma_v2 *dma_rxd)
1033 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
1034 if (!(rxd->rxd2 & RX_DMA_DONE))
1037 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
1038 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
1039 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
1040 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
1041 rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
1042 rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
1048 static void *mtk_max_lro_buf_alloc(gfp_t gfp_mask)
1050 unsigned int size = mtk_max_frag_size(MTK_MAX_LRO_RX_LENGTH);
1053 data = __get_free_pages(gfp_mask | __GFP_COMP | __GFP_NOWARN,
1056 return (void *)data;
1059 /* the qdma core needs scratch memory to be setup */
1060 static int mtk_init_fq_dma(struct mtk_eth *eth)
1062 const struct mtk_soc_data *soc = eth->soc;
1063 dma_addr_t phy_ring_tail;
1064 int cnt = MTK_QDMA_RING_SIZE;
1065 dma_addr_t dma_addr;
1068 eth->scratch_ring = dma_alloc_coherent(eth->dma_dev,
1069 cnt * soc->txrx.txd_size,
1070 ð->phy_scratch_ring,
1072 if (unlikely(!eth->scratch_ring))
1075 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, GFP_KERNEL);
1076 if (unlikely(!eth->scratch_head))
1079 dma_addr = dma_map_single(eth->dma_dev,
1080 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
1082 if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr)))
1085 phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1);
1087 for (i = 0; i < cnt; i++) {
1088 struct mtk_tx_dma_v2 *txd;
1090 txd = eth->scratch_ring + i * soc->txrx.txd_size;
1091 txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE;
1093 txd->txd2 = eth->phy_scratch_ring +
1094 (i + 1) * soc->txrx.txd_size;
1096 txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
1098 if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) {
1106 mtk_w32(eth, eth->phy_scratch_ring, soc->reg_map->qdma.fq_head);
1107 mtk_w32(eth, phy_ring_tail, soc->reg_map->qdma.fq_tail);
1108 mtk_w32(eth, (cnt << 16) | cnt, soc->reg_map->qdma.fq_count);
1109 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, soc->reg_map->qdma.fq_blen);
1114 static void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
1116 return ring->dma + (desc - ring->phys);
1119 static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
1120 void *txd, u32 txd_size)
1122 int idx = (txd - ring->dma) / txd_size;
1124 return &ring->buf[idx];
1127 static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring,
1128 struct mtk_tx_dma *dma)
1130 return ring->dma_pdma - (struct mtk_tx_dma *)ring->dma + dma;
1133 static int txd_to_idx(struct mtk_tx_ring *ring, void *dma, u32 txd_size)
1135 return (dma - ring->dma) / txd_size;
1138 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf,
1139 struct xdp_frame_bulk *bq, bool napi)
1141 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1142 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
1143 dma_unmap_single(eth->dma_dev,
1144 dma_unmap_addr(tx_buf, dma_addr0),
1145 dma_unmap_len(tx_buf, dma_len0),
1147 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
1148 dma_unmap_page(eth->dma_dev,
1149 dma_unmap_addr(tx_buf, dma_addr0),
1150 dma_unmap_len(tx_buf, dma_len0),
1154 if (dma_unmap_len(tx_buf, dma_len0)) {
1155 dma_unmap_page(eth->dma_dev,
1156 dma_unmap_addr(tx_buf, dma_addr0),
1157 dma_unmap_len(tx_buf, dma_len0),
1161 if (dma_unmap_len(tx_buf, dma_len1)) {
1162 dma_unmap_page(eth->dma_dev,
1163 dma_unmap_addr(tx_buf, dma_addr1),
1164 dma_unmap_len(tx_buf, dma_len1),
1169 if (tx_buf->data && tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) {
1170 if (tx_buf->type == MTK_TYPE_SKB) {
1171 struct sk_buff *skb = tx_buf->data;
1174 napi_consume_skb(skb, napi);
1176 dev_kfree_skb_any(skb);
1178 struct xdp_frame *xdpf = tx_buf->data;
1180 if (napi && tx_buf->type == MTK_TYPE_XDP_TX)
1181 xdp_return_frame_rx_napi(xdpf);
1183 xdp_return_frame_bulk(xdpf, bq);
1185 xdp_return_frame(xdpf);
1189 tx_buf->data = NULL;
1192 static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf,
1193 struct mtk_tx_dma *txd, dma_addr_t mapped_addr,
1194 size_t size, int idx)
1196 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1197 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
1198 dma_unmap_len_set(tx_buf, dma_len0, size);
1201 txd->txd3 = mapped_addr;
1202 txd->txd2 |= TX_DMA_PLEN1(size);
1203 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr);
1204 dma_unmap_len_set(tx_buf, dma_len1, size);
1206 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
1207 txd->txd1 = mapped_addr;
1208 txd->txd2 = TX_DMA_PLEN0(size);
1209 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
1210 dma_unmap_len_set(tx_buf, dma_len0, size);
1215 static void mtk_tx_set_dma_desc_v1(struct net_device *dev, void *txd,
1216 struct mtk_tx_dma_desc_info *info)
1218 struct mtk_mac *mac = netdev_priv(dev);
1219 struct mtk_eth *eth = mac->hw;
1220 struct mtk_tx_dma *desc = txd;
1223 WRITE_ONCE(desc->txd1, info->addr);
1225 data = TX_DMA_SWC | TX_DMA_PLEN0(info->size) |
1226 FIELD_PREP(TX_DMA_PQID, info->qid);
1229 WRITE_ONCE(desc->txd3, data);
1231 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT; /* forward port */
1235 /* tx checksum offload */
1237 data |= TX_DMA_CHKSUM;
1238 /* vlan header offload */
1240 data |= TX_DMA_INS_VLAN | info->vlan_tci;
1242 WRITE_ONCE(desc->txd4, data);
1245 static void mtk_tx_set_dma_desc_v2(struct net_device *dev, void *txd,
1246 struct mtk_tx_dma_desc_info *info)
1248 struct mtk_mac *mac = netdev_priv(dev);
1249 struct mtk_tx_dma_v2 *desc = txd;
1250 struct mtk_eth *eth = mac->hw;
1253 WRITE_ONCE(desc->txd1, info->addr);
1255 data = TX_DMA_PLEN0(info->size);
1258 WRITE_ONCE(desc->txd3, data);
1260 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */
1261 data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid);
1262 WRITE_ONCE(desc->txd4, data);
1267 data |= TX_DMA_TSO_V2;
1268 /* tx checksum offload */
1270 data |= TX_DMA_CHKSUM_V2;
1272 WRITE_ONCE(desc->txd5, data);
1275 if (info->first && info->vlan)
1276 data |= TX_DMA_INS_VLAN_V2 | info->vlan_tci;
1277 WRITE_ONCE(desc->txd6, data);
1279 WRITE_ONCE(desc->txd7, 0);
1280 WRITE_ONCE(desc->txd8, 0);
1283 static void mtk_tx_set_dma_desc(struct net_device *dev, void *txd,
1284 struct mtk_tx_dma_desc_info *info)
1286 struct mtk_mac *mac = netdev_priv(dev);
1287 struct mtk_eth *eth = mac->hw;
1289 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
1290 mtk_tx_set_dma_desc_v2(dev, txd, info);
1292 mtk_tx_set_dma_desc_v1(dev, txd, info);
1295 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
1296 int tx_num, struct mtk_tx_ring *ring, bool gso)
1298 struct mtk_tx_dma_desc_info txd_info = {
1299 .size = skb_headlen(skb),
1301 .csum = skb->ip_summed == CHECKSUM_PARTIAL,
1302 .vlan = skb_vlan_tag_present(skb),
1303 .qid = skb_get_queue_mapping(skb),
1304 .vlan_tci = skb_vlan_tag_get(skb),
1306 .last = !skb_is_nonlinear(skb),
1308 struct netdev_queue *txq;
1309 struct mtk_mac *mac = netdev_priv(dev);
1310 struct mtk_eth *eth = mac->hw;
1311 const struct mtk_soc_data *soc = eth->soc;
1312 struct mtk_tx_dma *itxd, *txd;
1313 struct mtk_tx_dma *itxd_pdma, *txd_pdma;
1314 struct mtk_tx_buf *itx_buf, *tx_buf;
1316 int queue = skb_get_queue_mapping(skb);
1319 txq = netdev_get_tx_queue(dev, queue);
1320 itxd = ring->next_free;
1321 itxd_pdma = qdma_to_pdma(ring, itxd);
1322 if (itxd == ring->last_free)
1325 itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size);
1326 memset(itx_buf, 0, sizeof(*itx_buf));
1328 txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size,
1330 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr)))
1333 mtk_tx_set_dma_desc(dev, itxd, &txd_info);
1335 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
1336 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
1337 MTK_TX_FLAGS_FPORT1;
1338 setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size,
1343 txd_pdma = qdma_to_pdma(ring, txd);
1345 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1346 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1347 unsigned int offset = 0;
1348 int frag_size = skb_frag_size(frag);
1351 bool new_desc = true;
1353 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) ||
1355 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
1356 txd_pdma = qdma_to_pdma(ring, txd);
1357 if (txd == ring->last_free)
1365 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
1366 txd_info.size = min_t(unsigned int, frag_size,
1367 soc->txrx.dma_max_len);
1368 txd_info.qid = queue;
1369 txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 &&
1370 !(frag_size - txd_info.size);
1371 txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag,
1372 offset, txd_info.size,
1374 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr)))
1377 mtk_tx_set_dma_desc(dev, txd, &txd_info);
1379 tx_buf = mtk_desc_to_tx_buf(ring, txd,
1380 soc->txrx.txd_size);
1382 memset(tx_buf, 0, sizeof(*tx_buf));
1383 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
1384 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
1385 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
1386 MTK_TX_FLAGS_FPORT1;
1388 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr,
1389 txd_info.size, k++);
1391 frag_size -= txd_info.size;
1392 offset += txd_info.size;
1396 /* store skb to cleanup */
1397 itx_buf->type = MTK_TYPE_SKB;
1398 itx_buf->data = skb;
1400 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1402 txd_pdma->txd2 |= TX_DMA_LS0;
1404 txd_pdma->txd2 |= TX_DMA_LS1;
1407 netdev_tx_sent_queue(txq, skb->len);
1408 skb_tx_timestamp(skb);
1410 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
1411 atomic_sub(n_desc, &ring->free_count);
1413 /* make sure that all changes to the dma ring are flushed before we
1418 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1419 if (netif_xmit_stopped(txq) || !netdev_xmit_more())
1420 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr);
1424 next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size),
1426 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0);
1433 tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size);
1436 mtk_tx_unmap(eth, tx_buf, NULL, false);
1438 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1439 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA))
1440 itxd_pdma->txd2 = TX_DMA_DESP2_DEF;
1442 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
1443 itxd_pdma = qdma_to_pdma(ring, itxd);
1444 } while (itxd != txd);
1449 static int mtk_cal_txd_req(struct mtk_eth *eth, struct sk_buff *skb)
1454 if (skb_is_gso(skb)) {
1455 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1456 frag = &skb_shinfo(skb)->frags[i];
1457 nfrags += DIV_ROUND_UP(skb_frag_size(frag),
1458 eth->soc->txrx.dma_max_len);
1461 nfrags += skb_shinfo(skb)->nr_frags;
1467 static int mtk_queue_stopped(struct mtk_eth *eth)
1471 for (i = 0; i < MTK_MAC_COUNT; i++) {
1472 if (!eth->netdev[i])
1474 if (netif_queue_stopped(eth->netdev[i]))
1481 static void mtk_wake_queue(struct mtk_eth *eth)
1485 for (i = 0; i < MTK_MAC_COUNT; i++) {
1486 if (!eth->netdev[i])
1488 netif_tx_wake_all_queues(eth->netdev[i]);
1492 static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
1494 struct mtk_mac *mac = netdev_priv(dev);
1495 struct mtk_eth *eth = mac->hw;
1496 struct mtk_tx_ring *ring = ð->tx_ring;
1497 struct net_device_stats *stats = &dev->stats;
1501 /* normally we can rely on the stack not calling this more than once,
1502 * however we have 2 queues running on the same ring so we need to lock
1505 spin_lock(ð->page_lock);
1507 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
1510 tx_num = mtk_cal_txd_req(eth, skb);
1511 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
1512 netif_tx_stop_all_queues(dev);
1513 netif_err(eth, tx_queued, dev,
1514 "Tx Ring full when queue awake!\n");
1515 spin_unlock(ð->page_lock);
1516 return NETDEV_TX_BUSY;
1519 /* TSO: fill MSS info in tcp checksum field */
1520 if (skb_is_gso(skb)) {
1521 if (skb_cow_head(skb, 0)) {
1522 netif_warn(eth, tx_err, dev,
1523 "GSO expand head fail.\n");
1527 if (skb_shinfo(skb)->gso_type &
1528 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1530 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
1534 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
1537 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
1538 netif_tx_stop_all_queues(dev);
1540 spin_unlock(ð->page_lock);
1542 return NETDEV_TX_OK;
1545 spin_unlock(ð->page_lock);
1546 stats->tx_dropped++;
1547 dev_kfree_skb_any(skb);
1548 return NETDEV_TX_OK;
1551 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth)
1554 struct mtk_rx_ring *ring;
1558 return ð->rx_ring[0];
1560 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
1561 struct mtk_rx_dma *rxd;
1563 ring = ð->rx_ring[i];
1564 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
1565 rxd = ring->dma + idx * eth->soc->txrx.rxd_size;
1566 if (rxd->rxd2 & RX_DMA_DONE) {
1567 ring->calc_idx_update = true;
1575 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth)
1577 struct mtk_rx_ring *ring;
1581 ring = ð->rx_ring[0];
1582 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
1584 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
1585 ring = ð->rx_ring[i];
1586 if (ring->calc_idx_update) {
1587 ring->calc_idx_update = false;
1588 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
1594 static bool mtk_page_pool_enabled(struct mtk_eth *eth)
1596 return MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2);
1599 static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth,
1600 struct xdp_rxq_info *xdp_q,
1603 struct page_pool_params pp_params = {
1605 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
1607 .nid = NUMA_NO_NODE,
1608 .dev = eth->dma_dev,
1609 .offset = MTK_PP_HEADROOM,
1610 .max_len = MTK_PP_MAX_BUF_SIZE,
1612 struct page_pool *pp;
1615 pp_params.dma_dir = rcu_access_pointer(eth->prog) ? DMA_BIDIRECTIONAL
1617 pp = page_pool_create(&pp_params);
1621 err = __xdp_rxq_info_reg(xdp_q, ð->dummy_dev, id,
1622 eth->rx_napi.napi_id, PAGE_SIZE);
1626 err = xdp_rxq_info_reg_mem_model(xdp_q, MEM_TYPE_PAGE_POOL, pp);
1628 goto err_unregister_rxq;
1633 xdp_rxq_info_unreg(xdp_q);
1635 page_pool_destroy(pp);
1637 return ERR_PTR(err);
1640 static void *mtk_page_pool_get_buff(struct page_pool *pp, dma_addr_t *dma_addr,
1645 page = page_pool_alloc_pages(pp, gfp_mask | __GFP_NOWARN);
1649 *dma_addr = page_pool_get_dma_addr(page) + MTK_PP_HEADROOM;
1650 return page_address(page);
1653 static void mtk_rx_put_buff(struct mtk_rx_ring *ring, void *data, bool napi)
1655 if (ring->page_pool)
1656 page_pool_put_full_page(ring->page_pool,
1657 virt_to_head_page(data), napi);
1659 skb_free_frag(data);
1662 static int mtk_xdp_frame_map(struct mtk_eth *eth, struct net_device *dev,
1663 struct mtk_tx_dma_desc_info *txd_info,
1664 struct mtk_tx_dma *txd, struct mtk_tx_buf *tx_buf,
1665 void *data, u16 headroom, int index, bool dma_map)
1667 struct mtk_tx_ring *ring = ð->tx_ring;
1668 struct mtk_mac *mac = netdev_priv(dev);
1669 struct mtk_tx_dma *txd_pdma;
1671 if (dma_map) { /* ndo_xdp_xmit */
1672 txd_info->addr = dma_map_single(eth->dma_dev, data,
1673 txd_info->size, DMA_TO_DEVICE);
1674 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info->addr)))
1677 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
1679 struct page *page = virt_to_head_page(data);
1681 txd_info->addr = page_pool_get_dma_addr(page) +
1682 sizeof(struct xdp_frame) + headroom;
1683 dma_sync_single_for_device(eth->dma_dev, txd_info->addr,
1684 txd_info->size, DMA_BIDIRECTIONAL);
1686 mtk_tx_set_dma_desc(dev, txd, txd_info);
1688 tx_buf->flags |= !mac->id ? MTK_TX_FLAGS_FPORT0 : MTK_TX_FLAGS_FPORT1;
1689 tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX;
1690 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
1692 txd_pdma = qdma_to_pdma(ring, txd);
1693 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info->addr, txd_info->size,
1699 static int mtk_xdp_submit_frame(struct mtk_eth *eth, struct xdp_frame *xdpf,
1700 struct net_device *dev, bool dma_map)
1702 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf);
1703 const struct mtk_soc_data *soc = eth->soc;
1704 struct mtk_tx_ring *ring = ð->tx_ring;
1705 struct mtk_mac *mac = netdev_priv(dev);
1706 struct mtk_tx_dma_desc_info txd_info = {
1709 .last = !xdp_frame_has_frags(xdpf),
1712 int err, index = 0, n_desc = 1, nr_frags;
1713 struct mtk_tx_buf *htx_buf, *tx_buf;
1714 struct mtk_tx_dma *htxd, *txd;
1715 void *data = xdpf->data;
1717 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
1720 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0;
1721 if (unlikely(atomic_read(&ring->free_count) <= 1 + nr_frags))
1724 spin_lock(ð->page_lock);
1726 txd = ring->next_free;
1727 if (txd == ring->last_free) {
1728 spin_unlock(ð->page_lock);
1733 tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->txrx.txd_size);
1734 memset(tx_buf, 0, sizeof(*tx_buf));
1738 err = mtk_xdp_frame_map(eth, dev, &txd_info, txd, tx_buf,
1739 data, xdpf->headroom, index, dma_map);
1746 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || (index & 0x1)) {
1747 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
1748 if (txd == ring->last_free)
1751 tx_buf = mtk_desc_to_tx_buf(ring, txd,
1752 soc->txrx.txd_size);
1753 memset(tx_buf, 0, sizeof(*tx_buf));
1757 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
1758 txd_info.size = skb_frag_size(&sinfo->frags[index]);
1759 txd_info.last = index + 1 == nr_frags;
1760 txd_info.qid = mac->id;
1761 data = skb_frag_address(&sinfo->frags[index]);
1765 /* store xdpf for cleanup */
1766 htx_buf->data = xdpf;
1768 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1769 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, txd);
1772 txd_pdma->txd2 |= TX_DMA_LS0;
1774 txd_pdma->txd2 |= TX_DMA_LS1;
1777 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
1778 atomic_sub(n_desc, &ring->free_count);
1780 /* make sure that all changes to the dma ring are flushed before we
1785 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1786 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr);
1790 idx = txd_to_idx(ring, txd, soc->txrx.txd_size);
1791 mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size),
1792 MT7628_TX_CTX_IDX0);
1795 spin_unlock(ð->page_lock);
1800 while (htxd != txd) {
1801 tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->txrx.txd_size);
1802 mtk_tx_unmap(eth, tx_buf, NULL, false);
1804 htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1805 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1806 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, htxd);
1808 txd_pdma->txd2 = TX_DMA_DESP2_DEF;
1811 htxd = mtk_qdma_phys_to_virt(ring, htxd->txd2);
1814 spin_unlock(ð->page_lock);
1819 static int mtk_xdp_xmit(struct net_device *dev, int num_frame,
1820 struct xdp_frame **frames, u32 flags)
1822 struct mtk_mac *mac = netdev_priv(dev);
1823 struct mtk_hw_stats *hw_stats = mac->hw_stats;
1824 struct mtk_eth *eth = mac->hw;
1827 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
1830 for (i = 0; i < num_frame; i++) {
1831 if (mtk_xdp_submit_frame(eth, frames[i], dev, true))
1836 u64_stats_update_begin(&hw_stats->syncp);
1837 hw_stats->xdp_stats.tx_xdp_xmit += nxmit;
1838 hw_stats->xdp_stats.tx_xdp_xmit_errors += num_frame - nxmit;
1839 u64_stats_update_end(&hw_stats->syncp);
1844 static u32 mtk_xdp_run(struct mtk_eth *eth, struct mtk_rx_ring *ring,
1845 struct xdp_buff *xdp, struct net_device *dev)
1847 struct mtk_mac *mac = netdev_priv(dev);
1848 struct mtk_hw_stats *hw_stats = mac->hw_stats;
1849 u64 *count = &hw_stats->xdp_stats.rx_xdp_drop;
1850 struct bpf_prog *prog;
1855 prog = rcu_dereference(eth->prog);
1859 act = bpf_prog_run_xdp(prog, xdp);
1862 count = &hw_stats->xdp_stats.rx_xdp_pass;
1865 if (unlikely(xdp_do_redirect(dev, xdp, prog))) {
1870 count = &hw_stats->xdp_stats.rx_xdp_redirect;
1873 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
1875 if (!xdpf || mtk_xdp_submit_frame(eth, xdpf, dev, false)) {
1876 count = &hw_stats->xdp_stats.rx_xdp_tx_errors;
1881 count = &hw_stats->xdp_stats.rx_xdp_tx;
1885 bpf_warn_invalid_xdp_action(dev, prog, act);
1888 trace_xdp_exception(dev, prog, act);
1894 page_pool_put_full_page(ring->page_pool,
1895 virt_to_head_page(xdp->data), true);
1898 u64_stats_update_begin(&hw_stats->syncp);
1899 *count = *count + 1;
1900 u64_stats_update_end(&hw_stats->syncp);
1907 static int mtk_poll_rx(struct napi_struct *napi, int budget,
1908 struct mtk_eth *eth)
1910 struct dim_sample dim_sample = {};
1911 struct mtk_rx_ring *ring;
1912 bool xdp_flush = false;
1914 struct sk_buff *skb;
1915 u8 *data, *new_data;
1916 struct mtk_rx_dma_v2 *rxd, trxd;
1917 int done = 0, bytes = 0;
1919 while (done < budget) {
1920 unsigned int pktlen, *rxdcsum;
1921 struct net_device *netdev;
1922 dma_addr_t dma_addr;
1926 ring = mtk_get_rx_ring(eth);
1927 if (unlikely(!ring))
1930 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
1931 rxd = ring->dma + idx * eth->soc->txrx.rxd_size;
1932 data = ring->data[idx];
1934 if (!mtk_rx_get_desc(eth, &trxd, rxd))
1937 /* find out which mac the packet come from. values start at 1 */
1938 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
1939 mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1;
1940 else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
1941 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG))
1942 mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1;
1944 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT ||
1948 netdev = eth->netdev[mac];
1950 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
1953 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
1955 /* alloc new buffer */
1956 if (ring->page_pool) {
1957 struct page *page = virt_to_head_page(data);
1958 struct xdp_buff xdp;
1961 new_data = mtk_page_pool_get_buff(ring->page_pool,
1964 if (unlikely(!new_data)) {
1965 netdev->stats.rx_dropped++;
1969 dma_sync_single_for_cpu(eth->dma_dev,
1970 page_pool_get_dma_addr(page) + MTK_PP_HEADROOM,
1971 pktlen, page_pool_get_dma_dir(ring->page_pool));
1973 xdp_init_buff(&xdp, PAGE_SIZE, &ring->xdp_q);
1974 xdp_prepare_buff(&xdp, data, MTK_PP_HEADROOM, pktlen,
1976 xdp_buff_clear_frags_flag(&xdp);
1978 ret = mtk_xdp_run(eth, ring, &xdp, netdev);
1979 if (ret == XDP_REDIRECT)
1982 if (ret != XDP_PASS)
1985 skb = build_skb(data, PAGE_SIZE);
1986 if (unlikely(!skb)) {
1987 page_pool_put_full_page(ring->page_pool,
1989 netdev->stats.rx_dropped++;
1993 skb_reserve(skb, xdp.data - xdp.data_hard_start);
1994 skb_put(skb, xdp.data_end - xdp.data);
1995 skb_mark_for_recycle(skb);
1997 if (ring->frag_size <= PAGE_SIZE)
1998 new_data = napi_alloc_frag(ring->frag_size);
2000 new_data = mtk_max_lro_buf_alloc(GFP_ATOMIC);
2002 if (unlikely(!new_data)) {
2003 netdev->stats.rx_dropped++;
2007 dma_addr = dma_map_single(eth->dma_dev,
2008 new_data + NET_SKB_PAD + eth->ip_align,
2009 ring->buf_size, DMA_FROM_DEVICE);
2010 if (unlikely(dma_mapping_error(eth->dma_dev,
2012 skb_free_frag(new_data);
2013 netdev->stats.rx_dropped++;
2017 dma_unmap_single(eth->dma_dev, trxd.rxd1,
2018 ring->buf_size, DMA_FROM_DEVICE);
2020 skb = build_skb(data, ring->frag_size);
2021 if (unlikely(!skb)) {
2022 netdev->stats.rx_dropped++;
2023 skb_free_frag(data);
2027 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
2028 skb_put(skb, pktlen);
2034 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
2035 reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
2036 hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
2037 if (hash != MTK_RXD5_FOE_ENTRY)
2038 skb_set_hash(skb, jhash_1word(hash, 0),
2040 rxdcsum = &trxd.rxd3;
2042 reason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4);
2043 hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY;
2044 if (hash != MTK_RXD4_FOE_ENTRY)
2045 skb_set_hash(skb, jhash_1word(hash, 0),
2047 rxdcsum = &trxd.rxd4;
2050 if (*rxdcsum & eth->soc->txrx.rx_dma_l4_valid)
2051 skb->ip_summed = CHECKSUM_UNNECESSARY;
2053 skb_checksum_none_assert(skb);
2054 skb->protocol = eth_type_trans(skb, netdev);
2056 /* When using VLAN untagging in combination with DSA, the
2057 * hardware treats the MTK special tag as a VLAN and untags it.
2059 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) &&
2060 (trxd.rxd2 & RX_DMA_VTAG) && netdev_uses_dsa(netdev)) {
2061 unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0);
2063 if (port < ARRAY_SIZE(eth->dsa_meta) &&
2064 eth->dsa_meta[port])
2065 skb_dst_set_noref(skb, ð->dsa_meta[port]->dst);
2068 if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED)
2069 mtk_ppe_check_skb(eth->ppe[0], skb, hash);
2071 skb_record_rx_queue(skb, 0);
2072 napi_gro_receive(napi, skb);
2075 ring->data[idx] = new_data;
2076 rxd->rxd1 = (unsigned int)dma_addr;
2078 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
2079 rxd->rxd2 = RX_DMA_LSO;
2081 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size);
2083 ring->calc_idx = idx;
2089 /* make sure that all changes to the dma ring are flushed before
2093 mtk_update_rx_cpu_idx(eth);
2096 eth->rx_packets += done;
2097 eth->rx_bytes += bytes;
2098 dim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes,
2100 net_dim(ð->rx_dim, dim_sample);
2108 struct mtk_poll_state {
2109 struct netdev_queue *txq;
2116 mtk_poll_tx_done(struct mtk_eth *eth, struct mtk_poll_state *state, u8 mac,
2117 struct sk_buff *skb)
2119 struct netdev_queue *txq;
2120 struct net_device *dev;
2121 unsigned int bytes = skb->len;
2125 eth->tx_bytes += bytes;
2127 dev = eth->netdev[mac];
2131 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
2132 if (state->txq == txq) {
2134 state->bytes += bytes;
2139 netdev_tx_completed_queue(state->txq, state->done, state->bytes);
2143 state->bytes = bytes;
2146 static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget,
2147 struct mtk_poll_state *state)
2149 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
2150 struct mtk_tx_ring *ring = ð->tx_ring;
2151 struct mtk_tx_buf *tx_buf;
2152 struct xdp_frame_bulk bq;
2153 struct mtk_tx_dma *desc;
2156 cpu = ring->last_free_ptr;
2157 dma = mtk_r32(eth, reg_map->qdma.drx_ptr);
2159 desc = mtk_qdma_phys_to_virt(ring, cpu);
2160 xdp_frame_bulk_init(&bq);
2162 while ((cpu != dma) && budget) {
2163 u32 next_cpu = desc->txd2;
2166 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
2167 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
2170 tx_buf = mtk_desc_to_tx_buf(ring, desc,
2171 eth->soc->txrx.txd_size);
2172 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1)
2178 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) {
2179 if (tx_buf->type == MTK_TYPE_SKB)
2180 mtk_poll_tx_done(eth, state, mac, tx_buf->data);
2184 mtk_tx_unmap(eth, tx_buf, &bq, true);
2186 ring->last_free = desc;
2187 atomic_inc(&ring->free_count);
2191 xdp_flush_frame_bulk(&bq);
2193 ring->last_free_ptr = cpu;
2194 mtk_w32(eth, cpu, reg_map->qdma.crx_ptr);
2199 static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget,
2200 struct mtk_poll_state *state)
2202 struct mtk_tx_ring *ring = ð->tx_ring;
2203 struct mtk_tx_buf *tx_buf;
2204 struct xdp_frame_bulk bq;
2205 struct mtk_tx_dma *desc;
2208 cpu = ring->cpu_idx;
2209 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0);
2210 xdp_frame_bulk_init(&bq);
2212 while ((cpu != dma) && budget) {
2213 tx_buf = &ring->buf[cpu];
2217 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) {
2218 if (tx_buf->type == MTK_TYPE_SKB)
2219 mtk_poll_tx_done(eth, state, 0, tx_buf->data);
2222 mtk_tx_unmap(eth, tx_buf, &bq, true);
2224 desc = ring->dma + cpu * eth->soc->txrx.txd_size;
2225 ring->last_free = desc;
2226 atomic_inc(&ring->free_count);
2228 cpu = NEXT_DESP_IDX(cpu, ring->dma_size);
2230 xdp_flush_frame_bulk(&bq);
2232 ring->cpu_idx = cpu;
2237 static int mtk_poll_tx(struct mtk_eth *eth, int budget)
2239 struct mtk_tx_ring *ring = ð->tx_ring;
2240 struct dim_sample dim_sample = {};
2241 struct mtk_poll_state state = {};
2243 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
2244 budget = mtk_poll_tx_qdma(eth, budget, &state);
2246 budget = mtk_poll_tx_pdma(eth, budget, &state);
2249 netdev_tx_completed_queue(state.txq, state.done, state.bytes);
2251 dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes,
2253 net_dim(ð->tx_dim, dim_sample);
2255 if (mtk_queue_stopped(eth) &&
2256 (atomic_read(&ring->free_count) > ring->thresh))
2257 mtk_wake_queue(eth);
2262 static void mtk_handle_status_irq(struct mtk_eth *eth)
2264 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
2266 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
2267 mtk_stats_update(eth);
2268 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
2273 static int mtk_napi_tx(struct napi_struct *napi, int budget)
2275 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
2276 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
2279 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
2280 mtk_handle_status_irq(eth);
2281 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->tx_irq_status);
2282 tx_done = mtk_poll_tx(eth, budget);
2284 if (unlikely(netif_msg_intr(eth))) {
2286 "done tx %d, intr 0x%08x/0x%x\n", tx_done,
2287 mtk_r32(eth, reg_map->tx_irq_status),
2288 mtk_r32(eth, reg_map->tx_irq_mask));
2291 if (tx_done == budget)
2294 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT)
2297 if (napi_complete_done(napi, tx_done))
2298 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
2303 static int mtk_napi_rx(struct napi_struct *napi, int budget)
2305 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
2306 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
2307 int rx_done_total = 0;
2309 mtk_handle_status_irq(eth);
2314 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask,
2315 reg_map->pdma.irq_status);
2316 rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth);
2317 rx_done_total += rx_done;
2319 if (unlikely(netif_msg_intr(eth))) {
2321 "done rx %d, intr 0x%08x/0x%x\n", rx_done,
2322 mtk_r32(eth, reg_map->pdma.irq_status),
2323 mtk_r32(eth, reg_map->pdma.irq_mask));
2326 if (rx_done_total == budget)
2329 } while (mtk_r32(eth, reg_map->pdma.irq_status) &
2330 eth->soc->txrx.rx_irq_done_mask);
2332 if (napi_complete_done(napi, rx_done_total))
2333 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask);
2335 return rx_done_total;
2338 static int mtk_tx_alloc(struct mtk_eth *eth)
2340 const struct mtk_soc_data *soc = eth->soc;
2341 struct mtk_tx_ring *ring = ð->tx_ring;
2342 int i, sz = soc->txrx.txd_size;
2343 struct mtk_tx_dma_v2 *txd;
2347 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA))
2348 ring_size = MTK_QDMA_RING_SIZE;
2350 ring_size = MTK_DMA_SIZE;
2352 ring->buf = kcalloc(ring_size, sizeof(*ring->buf),
2357 ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz,
2358 &ring->phys, GFP_KERNEL);
2362 for (i = 0; i < ring_size; i++) {
2363 int next = (i + 1) % ring_size;
2364 u32 next_ptr = ring->phys + next * sz;
2366 txd = ring->dma + i * sz;
2367 txd->txd2 = next_ptr;
2368 txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
2370 if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) {
2378 /* On MT7688 (PDMA only) this driver uses the ring->dma structs
2379 * only as the framework. The real HW descriptors are the PDMA
2380 * descriptors in ring->dma_pdma.
2382 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
2383 ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, ring_size * sz,
2384 &ring->phys_pdma, GFP_KERNEL);
2385 if (!ring->dma_pdma)
2388 for (i = 0; i < ring_size; i++) {
2389 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF;
2390 ring->dma_pdma[i].txd4 = 0;
2394 ring->dma_size = ring_size;
2395 atomic_set(&ring->free_count, ring_size - 2);
2396 ring->next_free = ring->dma;
2397 ring->last_free = (void *)txd;
2398 ring->last_free_ptr = (u32)(ring->phys + ((ring_size - 1) * sz));
2399 ring->thresh = MAX_SKB_FRAGS;
2401 /* make sure that all changes to the dma ring are flushed before we
2406 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
2407 mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr);
2408 mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr);
2410 ring->phys + ((ring_size - 1) * sz),
2411 soc->reg_map->qdma.crx_ptr);
2412 mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr);
2414 for (i = 0, ofs = 0; i < MTK_QDMA_NUM_QUEUES; i++) {
2415 val = (QDMA_RES_THRES << 8) | QDMA_RES_THRES;
2416 mtk_w32(eth, val, soc->reg_map->qdma.qtx_cfg + ofs);
2418 val = MTK_QTX_SCH_MIN_RATE_EN |
2419 /* minimum: 10 Mbps */
2420 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
2421 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
2422 MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
2423 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
2424 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
2425 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
2426 ofs += MTK_QTX_OFFSET;
2428 val = MTK_QDMA_TX_SCH_MAX_WFQ | (MTK_QDMA_TX_SCH_MAX_WFQ << 16);
2429 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate);
2430 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
2431 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4);
2433 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0);
2434 mtk_w32(eth, ring_size, MT7628_TX_MAX_CNT0);
2435 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0);
2436 mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx);
2445 static void mtk_tx_clean(struct mtk_eth *eth)
2447 const struct mtk_soc_data *soc = eth->soc;
2448 struct mtk_tx_ring *ring = ð->tx_ring;
2452 for (i = 0; i < ring->dma_size; i++)
2453 mtk_tx_unmap(eth, &ring->buf[i], NULL, false);
2459 dma_free_coherent(eth->dma_dev,
2460 ring->dma_size * soc->txrx.txd_size,
2461 ring->dma, ring->phys);
2465 if (ring->dma_pdma) {
2466 dma_free_coherent(eth->dma_dev,
2467 ring->dma_size * soc->txrx.txd_size,
2468 ring->dma_pdma, ring->phys_pdma);
2469 ring->dma_pdma = NULL;
2473 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
2475 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
2476 struct mtk_rx_ring *ring;
2477 int rx_data_len, rx_dma_size;
2480 if (rx_flag == MTK_RX_FLAGS_QDMA) {
2483 ring = ð->rx_ring_qdma;
2485 ring = ð->rx_ring[ring_no];
2488 if (rx_flag == MTK_RX_FLAGS_HWLRO) {
2489 rx_data_len = MTK_MAX_LRO_RX_LENGTH;
2490 rx_dma_size = MTK_HW_LRO_DMA_SIZE;
2492 rx_data_len = ETH_DATA_LEN;
2493 rx_dma_size = MTK_DMA_SIZE;
2496 ring->frag_size = mtk_max_frag_size(rx_data_len);
2497 ring->buf_size = mtk_max_buf_size(ring->frag_size);
2498 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data),
2503 if (mtk_page_pool_enabled(eth)) {
2504 struct page_pool *pp;
2506 pp = mtk_create_page_pool(eth, &ring->xdp_q, ring_no,
2511 ring->page_pool = pp;
2514 ring->dma = dma_alloc_coherent(eth->dma_dev,
2515 rx_dma_size * eth->soc->txrx.rxd_size,
2516 &ring->phys, GFP_KERNEL);
2520 for (i = 0; i < rx_dma_size; i++) {
2521 struct mtk_rx_dma_v2 *rxd;
2522 dma_addr_t dma_addr;
2525 rxd = ring->dma + i * eth->soc->txrx.rxd_size;
2526 if (ring->page_pool) {
2527 data = mtk_page_pool_get_buff(ring->page_pool,
2528 &dma_addr, GFP_KERNEL);
2532 if (ring->frag_size <= PAGE_SIZE)
2533 data = netdev_alloc_frag(ring->frag_size);
2535 data = mtk_max_lro_buf_alloc(GFP_KERNEL);
2540 dma_addr = dma_map_single(eth->dma_dev,
2541 data + NET_SKB_PAD + eth->ip_align,
2542 ring->buf_size, DMA_FROM_DEVICE);
2543 if (unlikely(dma_mapping_error(eth->dma_dev,
2545 skb_free_frag(data);
2549 rxd->rxd1 = (unsigned int)dma_addr;
2550 ring->data[i] = data;
2552 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
2553 rxd->rxd2 = RX_DMA_LSO;
2555 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size);
2559 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
2567 ring->dma_size = rx_dma_size;
2568 ring->calc_idx_update = false;
2569 ring->calc_idx = rx_dma_size - 1;
2570 if (rx_flag == MTK_RX_FLAGS_QDMA)
2571 ring->crx_idx_reg = reg_map->qdma.qcrx_ptr +
2572 ring_no * MTK_QRX_OFFSET;
2574 ring->crx_idx_reg = reg_map->pdma.pcrx_ptr +
2575 ring_no * MTK_QRX_OFFSET;
2576 /* make sure that all changes to the dma ring are flushed before we
2581 if (rx_flag == MTK_RX_FLAGS_QDMA) {
2582 mtk_w32(eth, ring->phys,
2583 reg_map->qdma.rx_ptr + ring_no * MTK_QRX_OFFSET);
2584 mtk_w32(eth, rx_dma_size,
2585 reg_map->qdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET);
2586 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no),
2587 reg_map->qdma.rst_idx);
2589 mtk_w32(eth, ring->phys,
2590 reg_map->pdma.rx_ptr + ring_no * MTK_QRX_OFFSET);
2591 mtk_w32(eth, rx_dma_size,
2592 reg_map->pdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET);
2593 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no),
2594 reg_map->pdma.rst_idx);
2596 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
2601 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring)
2605 if (ring->data && ring->dma) {
2606 for (i = 0; i < ring->dma_size; i++) {
2607 struct mtk_rx_dma *rxd;
2612 rxd = ring->dma + i * eth->soc->txrx.rxd_size;
2616 dma_unmap_single(eth->dma_dev, rxd->rxd1,
2617 ring->buf_size, DMA_FROM_DEVICE);
2618 mtk_rx_put_buff(ring, ring->data[i], false);
2625 dma_free_coherent(eth->dma_dev,
2626 ring->dma_size * eth->soc->txrx.rxd_size,
2627 ring->dma, ring->phys);
2631 if (ring->page_pool) {
2632 if (xdp_rxq_info_is_reg(&ring->xdp_q))
2633 xdp_rxq_info_unreg(&ring->xdp_q);
2634 page_pool_destroy(ring->page_pool);
2635 ring->page_pool = NULL;
2639 static int mtk_hwlro_rx_init(struct mtk_eth *eth)
2642 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0;
2643 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0;
2645 /* set LRO rings to auto-learn modes */
2646 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE;
2648 /* validate LRO ring */
2649 ring_ctrl_dw2 |= MTK_RING_VLD;
2651 /* set AGE timer (unit: 20us) */
2652 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H;
2653 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L;
2655 /* set max AGG timer (unit: 20us) */
2656 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME;
2658 /* set max LRO AGG count */
2659 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L;
2660 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H;
2662 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
2663 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i));
2664 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i));
2665 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i));
2668 /* IPv4 checksum update enable */
2669 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN;
2671 /* switch priority comparison to packet count mode */
2672 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE;
2674 /* bandwidth threshold setting */
2675 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2);
2677 /* auto-learn score delta setting */
2678 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA);
2680 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */
2681 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME,
2682 MTK_PDMA_LRO_ALT_REFRESH_TIMER);
2684 /* set HW LRO mode & the max aggregation count for rx packets */
2685 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff);
2687 /* the minimal remaining room of SDL0 in RXD for lro aggregation */
2688 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL;
2691 lro_ctrl_dw0 |= MTK_LRO_EN;
2693 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3);
2694 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0);
2699 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth)
2704 /* relinquish lro rings, flush aggregated packets */
2705 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0);
2707 /* wait for relinquishments done */
2708 for (i = 0; i < 10; i++) {
2709 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0);
2710 if (val & MTK_LRO_RING_RELINQUISH_DONE) {
2717 /* invalidate lro rings */
2718 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
2719 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i));
2721 /* disable HW LRO */
2722 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0);
2725 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip)
2729 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
2731 /* invalidate the IP setting */
2732 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
2734 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx));
2736 /* validate the IP setting */
2737 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
2740 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx)
2744 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
2746 /* invalidate the IP setting */
2747 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
2749 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx));
2752 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac)
2757 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
2758 if (mac->hwlro_ip[i])
2765 static int mtk_hwlro_add_ipaddr(struct net_device *dev,
2766 struct ethtool_rxnfc *cmd)
2768 struct ethtool_rx_flow_spec *fsp =
2769 (struct ethtool_rx_flow_spec *)&cmd->fs;
2770 struct mtk_mac *mac = netdev_priv(dev);
2771 struct mtk_eth *eth = mac->hw;
2774 if ((fsp->flow_type != TCP_V4_FLOW) ||
2775 (!fsp->h_u.tcp_ip4_spec.ip4dst) ||
2776 (fsp->location > 1))
2779 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst);
2780 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
2782 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
2784 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]);
2789 static int mtk_hwlro_del_ipaddr(struct net_device *dev,
2790 struct ethtool_rxnfc *cmd)
2792 struct ethtool_rx_flow_spec *fsp =
2793 (struct ethtool_rx_flow_spec *)&cmd->fs;
2794 struct mtk_mac *mac = netdev_priv(dev);
2795 struct mtk_eth *eth = mac->hw;
2798 if (fsp->location > 1)
2801 mac->hwlro_ip[fsp->location] = 0;
2802 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
2804 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
2806 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
2811 static void mtk_hwlro_netdev_disable(struct net_device *dev)
2813 struct mtk_mac *mac = netdev_priv(dev);
2814 struct mtk_eth *eth = mac->hw;
2817 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
2818 mac->hwlro_ip[i] = 0;
2819 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i;
2821 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
2824 mac->hwlro_ip_cnt = 0;
2827 static int mtk_hwlro_get_fdir_entry(struct net_device *dev,
2828 struct ethtool_rxnfc *cmd)
2830 struct mtk_mac *mac = netdev_priv(dev);
2831 struct ethtool_rx_flow_spec *fsp =
2832 (struct ethtool_rx_flow_spec *)&cmd->fs;
2834 if (fsp->location >= ARRAY_SIZE(mac->hwlro_ip))
2837 /* only tcp dst ipv4 is meaningful, others are meaningless */
2838 fsp->flow_type = TCP_V4_FLOW;
2839 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]);
2840 fsp->m_u.tcp_ip4_spec.ip4dst = 0;
2842 fsp->h_u.tcp_ip4_spec.ip4src = 0;
2843 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff;
2844 fsp->h_u.tcp_ip4_spec.psrc = 0;
2845 fsp->m_u.tcp_ip4_spec.psrc = 0xffff;
2846 fsp->h_u.tcp_ip4_spec.pdst = 0;
2847 fsp->m_u.tcp_ip4_spec.pdst = 0xffff;
2848 fsp->h_u.tcp_ip4_spec.tos = 0;
2849 fsp->m_u.tcp_ip4_spec.tos = 0xff;
2854 static int mtk_hwlro_get_fdir_all(struct net_device *dev,
2855 struct ethtool_rxnfc *cmd,
2858 struct mtk_mac *mac = netdev_priv(dev);
2862 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
2863 if (mac->hwlro_ip[i]) {
2869 cmd->rule_cnt = cnt;
2874 static netdev_features_t mtk_fix_features(struct net_device *dev,
2875 netdev_features_t features)
2877 if (!(features & NETIF_F_LRO)) {
2878 struct mtk_mac *mac = netdev_priv(dev);
2879 int ip_cnt = mtk_hwlro_get_ip_cnt(mac);
2882 netdev_info(dev, "RX flow is programmed, LRO should keep on\n");
2884 features |= NETIF_F_LRO;
2891 static int mtk_set_features(struct net_device *dev, netdev_features_t features)
2893 netdev_features_t diff = dev->features ^ features;
2895 if ((diff & NETIF_F_LRO) && !(features & NETIF_F_LRO))
2896 mtk_hwlro_netdev_disable(dev);
2901 /* wait for DMA to finish whatever it is doing before we start using it again */
2902 static int mtk_dma_busy_wait(struct mtk_eth *eth)
2908 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
2909 reg = eth->soc->reg_map->qdma.glo_cfg;
2911 reg = eth->soc->reg_map->pdma.glo_cfg;
2913 ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val,
2914 !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)),
2915 5, MTK_DMA_BUSY_TIMEOUT_US);
2917 dev_err(eth->dev, "DMA init timeout\n");
2922 static int mtk_dma_init(struct mtk_eth *eth)
2927 if (mtk_dma_busy_wait(eth))
2930 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2931 /* QDMA needs scratch memory for internal reordering of the
2934 err = mtk_init_fq_dma(eth);
2939 err = mtk_tx_alloc(eth);
2943 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2944 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA);
2949 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL);
2954 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
2955 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO);
2959 err = mtk_hwlro_rx_init(eth);
2964 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2965 /* Enable random early drop and set drop threshold
2968 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN |
2969 FC_THRES_MIN, eth->soc->reg_map->qdma.fc_th);
2970 mtk_w32(eth, 0x0, eth->soc->reg_map->qdma.hred);
2976 static void mtk_dma_free(struct mtk_eth *eth)
2978 const struct mtk_soc_data *soc = eth->soc;
2981 for (i = 0; i < MTK_MAC_COUNT; i++)
2983 netdev_reset_queue(eth->netdev[i]);
2984 if (eth->scratch_ring) {
2985 dma_free_coherent(eth->dma_dev,
2986 MTK_QDMA_RING_SIZE * soc->txrx.txd_size,
2987 eth->scratch_ring, eth->phy_scratch_ring);
2988 eth->scratch_ring = NULL;
2989 eth->phy_scratch_ring = 0;
2992 mtk_rx_clean(eth, ð->rx_ring[0]);
2993 mtk_rx_clean(eth, ð->rx_ring_qdma);
2996 mtk_hwlro_rx_uninit(eth);
2997 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
2998 mtk_rx_clean(eth, ð->rx_ring[i]);
3001 kfree(eth->scratch_head);
3004 static bool mtk_hw_reset_check(struct mtk_eth *eth)
3006 u32 val = mtk_r32(eth, MTK_INT_STATUS2);
3008 return (val & MTK_FE_INT_FQ_EMPTY) || (val & MTK_FE_INT_RFIFO_UF) ||
3009 (val & MTK_FE_INT_RFIFO_OV) || (val & MTK_FE_INT_TSO_FAIL) ||
3010 (val & MTK_FE_INT_TSO_ALIGN) || (val & MTK_FE_INT_TSO_ILLEGAL);
3013 static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue)
3015 struct mtk_mac *mac = netdev_priv(dev);
3016 struct mtk_eth *eth = mac->hw;
3018 if (test_bit(MTK_RESETTING, ð->state))
3021 if (!mtk_hw_reset_check(eth))
3024 eth->netdev[mac->id]->stats.tx_errors++;
3025 netif_err(eth, tx_err, dev, "transmit timed out\n");
3027 schedule_work(ð->pending_work);
3030 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
3032 struct mtk_eth *eth = _eth;
3035 if (likely(napi_schedule_prep(ð->rx_napi))) {
3036 __napi_schedule(ð->rx_napi);
3037 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
3043 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
3045 struct mtk_eth *eth = _eth;
3048 if (likely(napi_schedule_prep(ð->tx_napi))) {
3049 __napi_schedule(ð->tx_napi);
3050 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
3056 static irqreturn_t mtk_handle_irq(int irq, void *_eth)
3058 struct mtk_eth *eth = _eth;
3059 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
3061 if (mtk_r32(eth, reg_map->pdma.irq_mask) &
3062 eth->soc->txrx.rx_irq_done_mask) {
3063 if (mtk_r32(eth, reg_map->pdma.irq_status) &
3064 eth->soc->txrx.rx_irq_done_mask)
3065 mtk_handle_irq_rx(irq, _eth);
3067 if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) {
3068 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT)
3069 mtk_handle_irq_tx(irq, _eth);
3075 #ifdef CONFIG_NET_POLL_CONTROLLER
3076 static void mtk_poll_controller(struct net_device *dev)
3078 struct mtk_mac *mac = netdev_priv(dev);
3079 struct mtk_eth *eth = mac->hw;
3081 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
3082 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
3083 mtk_handle_irq_rx(eth->irq[2], dev);
3084 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
3085 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask);
3089 static int mtk_start_dma(struct mtk_eth *eth)
3091 u32 val, rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0;
3092 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
3095 err = mtk_dma_init(eth);
3101 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
3102 val = mtk_r32(eth, reg_map->qdma.glo_cfg);
3103 val |= MTK_TX_DMA_EN | MTK_RX_DMA_EN |
3104 MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO |
3105 MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE;
3107 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
3108 val |= MTK_MUTLI_CNT | MTK_RESV_BUF |
3109 MTK_WCOMP_EN | MTK_DMAD_WR_WDONE |
3110 MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN;
3112 val |= MTK_RX_BT_32DWORDS;
3113 mtk_w32(eth, val, reg_map->qdma.glo_cfg);
3116 MTK_RX_DMA_EN | rx_2b_offset |
3117 MTK_RX_BT_32DWORDS | MTK_MULTI_EN,
3118 reg_map->pdma.glo_cfg);
3120 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN |
3121 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS,
3122 reg_map->pdma.glo_cfg);
3128 static void mtk_gdm_config(struct mtk_eth *eth, u32 config)
3132 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
3135 for (i = 0; i < MTK_MAC_COUNT; i++) {
3136 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
3138 /* default setup the forward port to send frame to PDMA */
3141 /* Enable RX checksum */
3142 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
3146 if (eth->netdev[i] && netdev_uses_dsa(eth->netdev[i]))
3147 val |= MTK_GDMA_SPECIAL_TAG;
3149 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
3151 /* Reset and enable PSE */
3152 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
3153 mtk_w32(eth, 0, MTK_RST_GL);
3157 static bool mtk_uses_dsa(struct net_device *dev)
3159 #if IS_ENABLED(CONFIG_NET_DSA)
3160 return netdev_uses_dsa(dev) &&
3161 dev->dsa_ptr->tag_ops->proto == DSA_TAG_PROTO_MTK;
3167 static int mtk_device_event(struct notifier_block *n, unsigned long event, void *ptr)
3169 struct mtk_mac *mac = container_of(n, struct mtk_mac, device_notifier);
3170 struct mtk_eth *eth = mac->hw;
3171 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
3172 struct ethtool_link_ksettings s;
3173 struct net_device *ldev;
3174 struct list_head *iter;
3175 struct dsa_port *dp;
3177 if (event != NETDEV_CHANGE)
3180 netdev_for_each_lower_dev(dev, ldev, iter) {
3181 if (netdev_priv(ldev) == mac)
3188 if (!dsa_slave_dev_check(dev))
3191 if (__ethtool_get_link_ksettings(dev, &s))
3194 if (s.base.speed == 0 || s.base.speed == ((__u32)-1))
3197 dp = dsa_port_from_netdev(dev);
3198 if (dp->index >= MTK_QDMA_NUM_QUEUES)
3201 if (mac->speed > 0 && mac->speed <= s.base.speed)
3204 mtk_set_queue_speed(eth, dp->index + 3, s.base.speed);
3209 static int mtk_open(struct net_device *dev)
3211 struct mtk_mac *mac = netdev_priv(dev);
3212 struct mtk_eth *eth = mac->hw;
3215 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
3217 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
3222 /* we run 2 netdevs on the same dma ring so we only bring it up once */
3223 if (!refcount_read(ð->dma_refcnt)) {
3224 const struct mtk_soc_data *soc = eth->soc;
3228 err = mtk_start_dma(eth);
3230 phylink_disconnect_phy(mac->phylink);
3234 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
3235 mtk_ppe_start(eth->ppe[i]);
3237 gdm_config = soc->offload_version ? soc->reg_map->gdma_to_ppe
3239 mtk_gdm_config(eth, gdm_config);
3241 napi_enable(ð->tx_napi);
3242 napi_enable(ð->rx_napi);
3243 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
3244 mtk_rx_irq_enable(eth, soc->txrx.rx_irq_done_mask);
3245 refcount_set(ð->dma_refcnt, 1);
3248 refcount_inc(ð->dma_refcnt);
3250 phylink_start(mac->phylink);
3251 netif_tx_start_all_queues(dev);
3253 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
3256 if (mtk_uses_dsa(dev) && !eth->prog) {
3257 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) {
3258 struct metadata_dst *md_dst = eth->dsa_meta[i];
3263 md_dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX,
3268 md_dst->u.port_info.port_id = i;
3269 eth->dsa_meta[i] = md_dst;
3272 /* Hardware special tag parsing needs to be disabled if at least
3273 * one MAC does not use DSA.
3275 u32 val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
3277 val &= ~MTK_CDMP_STAG_EN;
3278 mtk_w32(eth, val, MTK_CDMP_IG_CTRL);
3280 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
3281 val &= ~MTK_CDMQ_STAG_EN;
3282 mtk_w32(eth, val, MTK_CDMQ_IG_CTRL);
3284 mtk_w32(eth, 0, MTK_CDMP_EG_CTRL);
3290 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
3295 /* stop the dma engine */
3296 spin_lock_bh(ð->page_lock);
3297 val = mtk_r32(eth, glo_cfg);
3298 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
3300 spin_unlock_bh(ð->page_lock);
3302 /* wait for dma stop */
3303 for (i = 0; i < 10; i++) {
3304 val = mtk_r32(eth, glo_cfg);
3305 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
3313 static int mtk_stop(struct net_device *dev)
3315 struct mtk_mac *mac = netdev_priv(dev);
3316 struct mtk_eth *eth = mac->hw;
3319 phylink_stop(mac->phylink);
3321 netif_tx_disable(dev);
3323 phylink_disconnect_phy(mac->phylink);
3325 /* only shutdown DMA if this is the last user */
3326 if (!refcount_dec_and_test(ð->dma_refcnt))
3329 mtk_gdm_config(eth, MTK_GDMA_DROP_ALL);
3331 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
3332 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
3333 napi_disable(ð->tx_napi);
3334 napi_disable(ð->rx_napi);
3336 cancel_work_sync(ð->rx_dim.work);
3337 cancel_work_sync(ð->tx_dim.work);
3339 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
3340 mtk_stop_dma(eth, eth->soc->reg_map->qdma.glo_cfg);
3341 mtk_stop_dma(eth, eth->soc->reg_map->pdma.glo_cfg);
3345 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
3346 mtk_ppe_stop(eth->ppe[i]);
3351 static int mtk_xdp_setup(struct net_device *dev, struct bpf_prog *prog,
3352 struct netlink_ext_ack *extack)
3354 struct mtk_mac *mac = netdev_priv(dev);
3355 struct mtk_eth *eth = mac->hw;
3356 struct bpf_prog *old_prog;
3360 NL_SET_ERR_MSG_MOD(extack, "XDP not supported with HWLRO");
3364 if (dev->mtu > MTK_PP_MAX_BUF_SIZE) {
3365 NL_SET_ERR_MSG_MOD(extack, "MTU too large for XDP");
3369 need_update = !!eth->prog != !!prog;
3370 if (netif_running(dev) && need_update)
3373 old_prog = rcu_replace_pointer(eth->prog, prog, lockdep_rtnl_is_held());
3375 bpf_prog_put(old_prog);
3377 if (netif_running(dev) && need_update)
3378 return mtk_open(dev);
3383 static int mtk_xdp(struct net_device *dev, struct netdev_bpf *xdp)
3385 switch (xdp->command) {
3386 case XDP_SETUP_PROG:
3387 return mtk_xdp_setup(dev, xdp->prog, xdp->extack);
3393 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits)
3395 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
3399 usleep_range(1000, 1100);
3400 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
3406 static void mtk_clk_disable(struct mtk_eth *eth)
3410 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--)
3411 clk_disable_unprepare(eth->clks[clk]);
3414 static int mtk_clk_enable(struct mtk_eth *eth)
3418 for (clk = 0; clk < MTK_CLK_MAX ; clk++) {
3419 ret = clk_prepare_enable(eth->clks[clk]);
3421 goto err_disable_clks;
3428 clk_disable_unprepare(eth->clks[clk]);
3433 static void mtk_dim_rx(struct work_struct *work)
3435 struct dim *dim = container_of(work, struct dim, work);
3436 struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim);
3437 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
3438 struct dim_cq_moder cur_profile;
3441 cur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode,
3443 spin_lock_bh(ð->dim_lock);
3445 val = mtk_r32(eth, reg_map->pdma.delay_irq);
3446 val &= MTK_PDMA_DELAY_TX_MASK;
3447 val |= MTK_PDMA_DELAY_RX_EN;
3449 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK);
3450 val |= cur << MTK_PDMA_DELAY_RX_PTIME_SHIFT;
3452 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK);
3453 val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT;
3455 mtk_w32(eth, val, reg_map->pdma.delay_irq);
3456 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
3457 mtk_w32(eth, val, reg_map->qdma.delay_irq);
3459 spin_unlock_bh(ð->dim_lock);
3461 dim->state = DIM_START_MEASURE;
3464 static void mtk_dim_tx(struct work_struct *work)
3466 struct dim *dim = container_of(work, struct dim, work);
3467 struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim);
3468 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
3469 struct dim_cq_moder cur_profile;
3472 cur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode,
3474 spin_lock_bh(ð->dim_lock);
3476 val = mtk_r32(eth, reg_map->pdma.delay_irq);
3477 val &= MTK_PDMA_DELAY_RX_MASK;
3478 val |= MTK_PDMA_DELAY_TX_EN;
3480 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK);
3481 val |= cur << MTK_PDMA_DELAY_TX_PTIME_SHIFT;
3483 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK);
3484 val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT;
3486 mtk_w32(eth, val, reg_map->pdma.delay_irq);
3487 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
3488 mtk_w32(eth, val, reg_map->qdma.delay_irq);
3490 spin_unlock_bh(ð->dim_lock);
3492 dim->state = DIM_START_MEASURE;
3495 static void mtk_set_mcr_max_rx(struct mtk_mac *mac, u32 val)
3497 struct mtk_eth *eth = mac->hw;
3498 u32 mcr_cur, mcr_new;
3500 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
3503 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
3504 mcr_new = mcr_cur & ~MAC_MCR_MAX_RX_MASK;
3507 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1518);
3508 else if (val <= 1536)
3509 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1536);
3510 else if (val <= 1552)
3511 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1552);
3513 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_2048);
3515 if (mcr_new != mcr_cur)
3516 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
3519 static void mtk_hw_reset(struct mtk_eth *eth)
3523 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
3524 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
3525 val = RSTCTRL_PPE0_V2;
3530 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
3531 val |= RSTCTRL_PPE1;
3533 ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
3535 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
3536 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
3540 static u32 mtk_hw_reset_read(struct mtk_eth *eth)
3544 regmap_read(eth->ethsys, ETHSYS_RSTCTRL, &val);
3548 static void mtk_hw_warm_reset(struct mtk_eth *eth)
3552 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, RSTCTRL_FE,
3554 if (readx_poll_timeout_atomic(mtk_hw_reset_read, eth, val,
3555 val & RSTCTRL_FE, 1, 1000)) {
3556 dev_err(eth->dev, "warm reset failed\n");
3561 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
3562 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2;
3564 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0;
3566 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
3567 rst_mask |= RSTCTRL_PPE1;
3569 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask);
3572 val = mtk_hw_reset_read(eth);
3573 if (!(val & rst_mask))
3574 dev_err(eth->dev, "warm reset stage0 failed %08x (%08x)\n",
3577 rst_mask |= RSTCTRL_FE;
3578 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, ~rst_mask);
3581 val = mtk_hw_reset_read(eth);
3583 dev_err(eth->dev, "warm reset stage1 failed %08x (%08x)\n",
3587 static bool mtk_hw_check_dma_hang(struct mtk_eth *eth)
3589 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
3590 bool gmac1_tx, gmac2_tx, gdm1_tx, gdm2_tx;
3591 bool oq_hang, cdm1_busy, adma_busy;
3592 bool wtx_busy, cdm_full, oq_free;
3593 u32 wdidx, val, gdm1_fc, gdm2_fc;
3594 bool qfsm_hang, qfwd_hang;
3597 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
3600 /* WDMA sanity checks */
3601 wdidx = mtk_r32(eth, reg_map->wdma_base[0] + 0xc);
3603 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x204);
3604 wtx_busy = FIELD_GET(MTK_TX_DMA_BUSY, val);
3606 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x230);
3607 cdm_full = !FIELD_GET(MTK_CDM_TXFIFO_RDY, val);
3609 oq_free = (!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(24, 16)) &&
3610 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x4) & GENMASK(8, 0)) &&
3611 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x10) & GENMASK(24, 16)));
3613 if (wdidx == eth->reset.wdidx && wtx_busy && cdm_full && oq_free) {
3614 if (++eth->reset.wdma_hang_count > 2) {
3615 eth->reset.wdma_hang_count = 0;
3621 /* QDMA sanity checks */
3622 qfsm_hang = !!mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x234);
3623 qfwd_hang = !mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x308);
3625 gdm1_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM1_FSM)) > 0;
3626 gdm2_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM2_FSM)) > 0;
3627 gmac1_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(0))) != 1;
3628 gmac2_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(1))) != 1;
3629 gdm1_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x24);
3630 gdm2_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x64);
3632 if (qfsm_hang && qfwd_hang &&
3633 ((gdm1_tx && gmac1_tx && gdm1_fc < 1) ||
3634 (gdm2_tx && gmac2_tx && gdm2_fc < 1))) {
3635 if (++eth->reset.qdma_hang_count > 2) {
3636 eth->reset.qdma_hang_count = 0;
3642 /* ADMA sanity checks */
3643 oq_hang = !!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(8, 0));
3644 cdm1_busy = !!(mtk_r32(eth, MTK_FE_CDM1_FSM) & GENMASK(31, 16));
3645 adma_busy = !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & GENMASK(4, 0)) &&
3646 !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & BIT(6));
3648 if (oq_hang && cdm1_busy && adma_busy) {
3649 if (++eth->reset.adma_hang_count > 2) {
3650 eth->reset.adma_hang_count = 0;
3656 eth->reset.wdma_hang_count = 0;
3657 eth->reset.qdma_hang_count = 0;
3658 eth->reset.adma_hang_count = 0;
3660 eth->reset.wdidx = wdidx;
3665 static void mtk_hw_reset_monitor_work(struct work_struct *work)
3667 struct delayed_work *del_work = to_delayed_work(work);
3668 struct mtk_eth *eth = container_of(del_work, struct mtk_eth,
3669 reset.monitor_work);
3671 if (test_bit(MTK_RESETTING, ð->state))
3674 /* DMA stuck checks */
3675 if (mtk_hw_check_dma_hang(eth))
3676 schedule_work(ð->pending_work);
3679 schedule_delayed_work(ð->reset.monitor_work,
3680 MTK_DMA_MONITOR_TIMEOUT);
3683 static int mtk_hw_init(struct mtk_eth *eth, bool reset)
3685 u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |
3686 ETHSYS_DMA_AG_MAP_PPE;
3687 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
3690 if (!reset && test_and_set_bit(MTK_HW_INIT, ð->state))
3694 pm_runtime_enable(eth->dev);
3695 pm_runtime_get_sync(eth->dev);
3697 ret = mtk_clk_enable(eth);
3699 goto err_disable_pm;
3703 regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask,
3704 of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask);
3706 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
3707 ret = device_reset(eth->dev);
3709 dev_err(eth->dev, "MAC reset failed!\n");
3710 goto err_disable_pm;
3713 /* set interrupt delays based on current Net DIM sample */
3714 mtk_dim_rx(ð->rx_dim.work);
3715 mtk_dim_tx(ð->tx_dim.work);
3717 /* disable delay and normal interrupt */
3718 mtk_tx_irq_disable(eth, ~0);
3719 mtk_rx_irq_disable(eth, ~0);
3727 mtk_hw_warm_reset(eth);
3731 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
3732 /* Set FE to PDMAv2 if necessary */
3733 val = mtk_r32(eth, MTK_FE_GLO_MISC);
3734 mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC);
3738 /* Set GE2 driving and slew rate */
3739 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
3742 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
3745 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
3748 /* Set linkdown as the default for each GMAC. Its own MCR would be set
3749 * up with the more appropriate value when mtk_mac_config call is being
3752 for (i = 0; i < MTK_MAC_COUNT; i++) {
3753 struct net_device *dev = eth->netdev[i];
3755 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i));
3757 struct mtk_mac *mac = netdev_priv(dev);
3759 mtk_set_mcr_max_rx(mac, dev->mtu + MTK_RX_ETH_HLEN);
3763 /* Indicates CDM to parse the MTK special tag from CPU
3764 * which also is working out for untag packets.
3766 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
3767 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
3768 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
3769 val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
3770 mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL);
3772 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
3775 /* set interrupt delays based on current Net DIM sample */
3776 mtk_dim_rx(ð->rx_dim.work);
3777 mtk_dim_tx(ð->tx_dim.work);
3779 /* disable delay and normal interrupt */
3780 mtk_tx_irq_disable(eth, ~0);
3781 mtk_rx_irq_disable(eth, ~0);
3783 /* FE int grouping */
3784 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp);
3785 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4);
3786 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp);
3787 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);
3788 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
3790 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
3791 /* PSE should not drop port8 and port9 packets from WDMA Tx */
3792 mtk_w32(eth, 0x00000300, PSE_DROP_CFG);
3794 /* PSE should drop packets to port 8/9 on WDMA Rx ring full */
3795 mtk_w32(eth, 0x00000300, PSE_PPE0_DROP);
3797 /* PSE Free Queue Flow Control */
3798 mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2);
3800 /* PSE config input queue threshold */
3801 mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1));
3802 mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2));
3803 mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3));
3804 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4));
3805 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5));
3806 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6));
3807 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7));
3808 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(8));
3810 /* PSE config output queue threshold */
3811 mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1));
3812 mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2));
3813 mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3));
3814 mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4));
3815 mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5));
3816 mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6));
3817 mtk_w32(eth, 0x00060006, PSE_OQ_TH(7));
3818 mtk_w32(eth, 0x00060006, PSE_OQ_TH(8));
3820 /* GDM and CDM Threshold */
3821 mtk_w32(eth, 0x00000004, MTK_GDM2_THRES);
3822 mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES);
3823 mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES);
3824 mtk_w32(eth, 0x00000004, MTK_CDME0_THRES);
3825 mtk_w32(eth, 0x00000004, MTK_CDME1_THRES);
3826 mtk_w32(eth, 0x00000004, MTK_CDMM_THRES);
3833 pm_runtime_put_sync(eth->dev);
3834 pm_runtime_disable(eth->dev);
3840 static int mtk_hw_deinit(struct mtk_eth *eth)
3842 if (!test_and_clear_bit(MTK_HW_INIT, ð->state))
3845 mtk_clk_disable(eth);
3847 pm_runtime_put_sync(eth->dev);
3848 pm_runtime_disable(eth->dev);
3853 static int __init mtk_init(struct net_device *dev)
3855 struct mtk_mac *mac = netdev_priv(dev);
3856 struct mtk_eth *eth = mac->hw;
3859 ret = of_get_ethdev_address(mac->of_node, dev);
3861 /* If the mac address is invalid, use random mac address */
3862 eth_hw_addr_random(dev);
3863 dev_err(eth->dev, "generated random MAC address %pM\n",
3870 static void mtk_uninit(struct net_device *dev)
3872 struct mtk_mac *mac = netdev_priv(dev);
3873 struct mtk_eth *eth = mac->hw;
3875 phylink_disconnect_phy(mac->phylink);
3876 mtk_tx_irq_disable(eth, ~0);
3877 mtk_rx_irq_disable(eth, ~0);
3880 static int mtk_change_mtu(struct net_device *dev, int new_mtu)
3882 int length = new_mtu + MTK_RX_ETH_HLEN;
3883 struct mtk_mac *mac = netdev_priv(dev);
3884 struct mtk_eth *eth = mac->hw;
3886 if (rcu_access_pointer(eth->prog) &&
3887 length > MTK_PP_MAX_BUF_SIZE) {
3888 netdev_err(dev, "Invalid MTU for XDP mode\n");
3892 mtk_set_mcr_max_rx(mac, length);
3898 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3900 struct mtk_mac *mac = netdev_priv(dev);
3906 return phylink_mii_ioctl(mac->phylink, ifr, cmd);
3914 static void mtk_prepare_for_reset(struct mtk_eth *eth)
3919 /* disabe FE P3 and P4 */
3920 val = mtk_r32(eth, MTK_FE_GLO_CFG) | MTK_FE_LINK_DOWN_P3;
3921 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
3922 val |= MTK_FE_LINK_DOWN_P4;
3923 mtk_w32(eth, val, MTK_FE_GLO_CFG);
3925 /* adjust PPE configurations to prepare for reset */
3926 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
3927 mtk_ppe_prepare_reset(eth->ppe[i]);
3929 /* disable NETSYS interrupts */
3930 mtk_w32(eth, 0, MTK_FE_INT_ENABLE);
3932 /* force link down GMAC */
3933 for (i = 0; i < 2; i++) {
3934 val = mtk_r32(eth, MTK_MAC_MCR(i)) & ~MAC_MCR_FORCE_LINK;
3935 mtk_w32(eth, val, MTK_MAC_MCR(i));
3939 static void mtk_pending_work(struct work_struct *work)
3941 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
3942 unsigned long restart = 0;
3947 set_bit(MTK_RESETTING, ð->state);
3949 mtk_prepare_for_reset(eth);
3951 /* Run again reset preliminary configuration in order to avoid any
3952 * possible race during FE reset since it can run releasing RTNL lock.
3954 mtk_prepare_for_reset(eth);
3956 /* stop all devices to make sure that dma is properly shut down */
3957 for (i = 0; i < MTK_MAC_COUNT; i++) {
3958 if (!eth->netdev[i] || !netif_running(eth->netdev[i]))
3961 mtk_stop(eth->netdev[i]);
3962 __set_bit(i, &restart);
3965 usleep_range(15000, 16000);
3968 pinctrl_select_state(eth->dev->pins->p,
3969 eth->dev->pins->default_state);
3970 mtk_hw_init(eth, true);
3972 /* restart DMA and enable IRQs */
3973 for (i = 0; i < MTK_MAC_COUNT; i++) {
3974 if (!test_bit(i, &restart))
3977 if (mtk_open(eth->netdev[i])) {
3978 netif_alert(eth, ifup, eth->netdev[i],
3979 "Driver up/down cycle failed\n");
3980 dev_close(eth->netdev[i]);
3984 /* enabe FE P3 and P4 */
3985 val = mtk_r32(eth, MTK_FE_GLO_CFG) & ~MTK_FE_LINK_DOWN_P3;
3986 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
3987 val &= ~MTK_FE_LINK_DOWN_P4;
3988 mtk_w32(eth, val, MTK_FE_GLO_CFG);
3990 clear_bit(MTK_RESETTING, ð->state);
3992 mtk_wed_fe_reset_complete();
3997 static int mtk_free_dev(struct mtk_eth *eth)
4001 for (i = 0; i < MTK_MAC_COUNT; i++) {
4002 if (!eth->netdev[i])
4004 free_netdev(eth->netdev[i]);
4007 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) {
4008 if (!eth->dsa_meta[i])
4010 metadata_dst_free(eth->dsa_meta[i]);
4016 static int mtk_unreg_dev(struct mtk_eth *eth)
4020 for (i = 0; i < MTK_MAC_COUNT; i++) {
4021 struct mtk_mac *mac;
4022 if (!eth->netdev[i])
4024 mac = netdev_priv(eth->netdev[i]);
4025 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
4026 unregister_netdevice_notifier(&mac->device_notifier);
4027 unregister_netdev(eth->netdev[i]);
4033 static void mtk_sgmii_destroy(struct mtk_eth *eth)
4037 for (i = 0; i < MTK_MAX_DEVS; i++)
4038 mtk_pcs_lynxi_destroy(eth->sgmii_pcs[i]);
4041 static int mtk_cleanup(struct mtk_eth *eth)
4043 mtk_sgmii_destroy(eth);
4046 cancel_work_sync(ð->pending_work);
4047 cancel_delayed_work_sync(ð->reset.monitor_work);
4052 static int mtk_get_link_ksettings(struct net_device *ndev,
4053 struct ethtool_link_ksettings *cmd)
4055 struct mtk_mac *mac = netdev_priv(ndev);
4057 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
4060 return phylink_ethtool_ksettings_get(mac->phylink, cmd);
4063 static int mtk_set_link_ksettings(struct net_device *ndev,
4064 const struct ethtool_link_ksettings *cmd)
4066 struct mtk_mac *mac = netdev_priv(ndev);
4068 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
4071 return phylink_ethtool_ksettings_set(mac->phylink, cmd);
4074 static void mtk_get_drvinfo(struct net_device *dev,
4075 struct ethtool_drvinfo *info)
4077 struct mtk_mac *mac = netdev_priv(dev);
4079 strscpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
4080 strscpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
4081 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
4084 static u32 mtk_get_msglevel(struct net_device *dev)
4086 struct mtk_mac *mac = netdev_priv(dev);
4088 return mac->hw->msg_enable;
4091 static void mtk_set_msglevel(struct net_device *dev, u32 value)
4093 struct mtk_mac *mac = netdev_priv(dev);
4095 mac->hw->msg_enable = value;
4098 static int mtk_nway_reset(struct net_device *dev)
4100 struct mtk_mac *mac = netdev_priv(dev);
4102 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
4108 return phylink_ethtool_nway_reset(mac->phylink);
4111 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4115 switch (stringset) {
4116 case ETH_SS_STATS: {
4117 struct mtk_mac *mac = netdev_priv(dev);
4119 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
4120 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
4121 data += ETH_GSTRING_LEN;
4123 if (mtk_page_pool_enabled(mac->hw))
4124 page_pool_ethtool_stats_get_strings(data);
4132 static int mtk_get_sset_count(struct net_device *dev, int sset)
4135 case ETH_SS_STATS: {
4136 int count = ARRAY_SIZE(mtk_ethtool_stats);
4137 struct mtk_mac *mac = netdev_priv(dev);
4139 if (mtk_page_pool_enabled(mac->hw))
4140 count += page_pool_ethtool_stats_get_count();
4148 static void mtk_ethtool_pp_stats(struct mtk_eth *eth, u64 *data)
4150 struct page_pool_stats stats = {};
4153 for (i = 0; i < ARRAY_SIZE(eth->rx_ring); i++) {
4154 struct mtk_rx_ring *ring = ð->rx_ring[i];
4156 if (!ring->page_pool)
4159 page_pool_get_stats(ring->page_pool, &stats);
4161 page_pool_ethtool_stats_get(data, &stats);
4164 static void mtk_get_ethtool_stats(struct net_device *dev,
4165 struct ethtool_stats *stats, u64 *data)
4167 struct mtk_mac *mac = netdev_priv(dev);
4168 struct mtk_hw_stats *hwstats = mac->hw_stats;
4169 u64 *data_src, *data_dst;
4173 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
4176 if (netif_running(dev) && netif_device_present(dev)) {
4177 if (spin_trylock_bh(&hwstats->stats_lock)) {
4178 mtk_stats_update_mac(mac);
4179 spin_unlock_bh(&hwstats->stats_lock);
4183 data_src = (u64 *)hwstats;
4187 start = u64_stats_fetch_begin(&hwstats->syncp);
4189 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
4190 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
4191 if (mtk_page_pool_enabled(mac->hw))
4192 mtk_ethtool_pp_stats(mac->hw, data_dst);
4193 } while (u64_stats_fetch_retry(&hwstats->syncp, start));
4196 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
4199 int ret = -EOPNOTSUPP;
4202 case ETHTOOL_GRXRINGS:
4203 if (dev->hw_features & NETIF_F_LRO) {
4204 cmd->data = MTK_MAX_RX_RING_NUM;
4208 case ETHTOOL_GRXCLSRLCNT:
4209 if (dev->hw_features & NETIF_F_LRO) {
4210 struct mtk_mac *mac = netdev_priv(dev);
4212 cmd->rule_cnt = mac->hwlro_ip_cnt;
4216 case ETHTOOL_GRXCLSRULE:
4217 if (dev->hw_features & NETIF_F_LRO)
4218 ret = mtk_hwlro_get_fdir_entry(dev, cmd);
4220 case ETHTOOL_GRXCLSRLALL:
4221 if (dev->hw_features & NETIF_F_LRO)
4222 ret = mtk_hwlro_get_fdir_all(dev, cmd,
4232 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
4234 int ret = -EOPNOTSUPP;
4237 case ETHTOOL_SRXCLSRLINS:
4238 if (dev->hw_features & NETIF_F_LRO)
4239 ret = mtk_hwlro_add_ipaddr(dev, cmd);
4241 case ETHTOOL_SRXCLSRLDEL:
4242 if (dev->hw_features & NETIF_F_LRO)
4243 ret = mtk_hwlro_del_ipaddr(dev, cmd);
4252 static u16 mtk_select_queue(struct net_device *dev, struct sk_buff *skb,
4253 struct net_device *sb_dev)
4255 struct mtk_mac *mac = netdev_priv(dev);
4256 unsigned int queue = 0;
4258 if (netdev_uses_dsa(dev))
4259 queue = skb_get_queue_mapping(skb) + 3;
4263 if (queue >= dev->num_tx_queues)
4269 static const struct ethtool_ops mtk_ethtool_ops = {
4270 .get_link_ksettings = mtk_get_link_ksettings,
4271 .set_link_ksettings = mtk_set_link_ksettings,
4272 .get_drvinfo = mtk_get_drvinfo,
4273 .get_msglevel = mtk_get_msglevel,
4274 .set_msglevel = mtk_set_msglevel,
4275 .nway_reset = mtk_nway_reset,
4276 .get_link = ethtool_op_get_link,
4277 .get_strings = mtk_get_strings,
4278 .get_sset_count = mtk_get_sset_count,
4279 .get_ethtool_stats = mtk_get_ethtool_stats,
4280 .get_rxnfc = mtk_get_rxnfc,
4281 .set_rxnfc = mtk_set_rxnfc,
4284 static const struct net_device_ops mtk_netdev_ops = {
4285 .ndo_init = mtk_init,
4286 .ndo_uninit = mtk_uninit,
4287 .ndo_open = mtk_open,
4288 .ndo_stop = mtk_stop,
4289 .ndo_start_xmit = mtk_start_xmit,
4290 .ndo_set_mac_address = mtk_set_mac_address,
4291 .ndo_validate_addr = eth_validate_addr,
4292 .ndo_eth_ioctl = mtk_do_ioctl,
4293 .ndo_change_mtu = mtk_change_mtu,
4294 .ndo_tx_timeout = mtk_tx_timeout,
4295 .ndo_get_stats64 = mtk_get_stats64,
4296 .ndo_fix_features = mtk_fix_features,
4297 .ndo_set_features = mtk_set_features,
4298 #ifdef CONFIG_NET_POLL_CONTROLLER
4299 .ndo_poll_controller = mtk_poll_controller,
4301 .ndo_setup_tc = mtk_eth_setup_tc,
4303 .ndo_xdp_xmit = mtk_xdp_xmit,
4304 .ndo_select_queue = mtk_select_queue,
4307 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
4309 const __be32 *_id = of_get_property(np, "reg", NULL);
4310 phy_interface_t phy_mode;
4311 struct phylink *phylink;
4312 struct mtk_mac *mac;
4318 dev_err(eth->dev, "missing mac id\n");
4322 id = be32_to_cpup(_id);
4323 if (id >= MTK_MAC_COUNT) {
4324 dev_err(eth->dev, "%d is not a valid mac id\n", id);
4328 if (eth->netdev[id]) {
4329 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
4333 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
4334 txqs = MTK_QDMA_NUM_QUEUES;
4336 eth->netdev[id] = alloc_etherdev_mqs(sizeof(*mac), txqs, 1);
4337 if (!eth->netdev[id]) {
4338 dev_err(eth->dev, "alloc_etherdev failed\n");
4341 mac = netdev_priv(eth->netdev[id]);
4347 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
4348 mac->hwlro_ip_cnt = 0;
4350 mac->hw_stats = devm_kzalloc(eth->dev,
4351 sizeof(*mac->hw_stats),
4353 if (!mac->hw_stats) {
4354 dev_err(eth->dev, "failed to allocate counter memory\n");
4358 spin_lock_init(&mac->hw_stats->stats_lock);
4359 u64_stats_init(&mac->hw_stats->syncp);
4360 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
4362 /* phylink create */
4363 err = of_get_phy_mode(np, &phy_mode);
4365 dev_err(eth->dev, "incorrect phy-mode\n");
4369 /* mac config is not set */
4370 mac->interface = PHY_INTERFACE_MODE_NA;
4371 mac->speed = SPEED_UNKNOWN;
4373 mac->phylink_config.dev = ð->netdev[id]->dev;
4374 mac->phylink_config.type = PHYLINK_NETDEV;
4375 /* This driver makes use of state->speed in mac_config */
4376 mac->phylink_config.legacy_pre_march2020 = true;
4377 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
4378 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD;
4380 __set_bit(PHY_INTERFACE_MODE_MII,
4381 mac->phylink_config.supported_interfaces);
4382 __set_bit(PHY_INTERFACE_MODE_GMII,
4383 mac->phylink_config.supported_interfaces);
4385 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII))
4386 phy_interface_set_rgmii(mac->phylink_config.supported_interfaces);
4388 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id)
4389 __set_bit(PHY_INTERFACE_MODE_TRGMII,
4390 mac->phylink_config.supported_interfaces);
4392 /* TRGMII is not permitted on MT7621 if using DDR2 */
4393 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) &&
4394 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII_MT7621_CLK)) {
4395 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val);
4396 if (val & SYSCFG_DRAM_TYPE_DDR2)
4397 __clear_bit(PHY_INTERFACE_MODE_TRGMII,
4398 mac->phylink_config.supported_interfaces);
4401 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) {
4402 __set_bit(PHY_INTERFACE_MODE_SGMII,
4403 mac->phylink_config.supported_interfaces);
4404 __set_bit(PHY_INTERFACE_MODE_1000BASEX,
4405 mac->phylink_config.supported_interfaces);
4406 __set_bit(PHY_INTERFACE_MODE_2500BASEX,
4407 mac->phylink_config.supported_interfaces);
4410 phylink = phylink_create(&mac->phylink_config,
4411 of_fwnode_handle(mac->of_node),
4412 phy_mode, &mtk_phylink_ops);
4413 if (IS_ERR(phylink)) {
4414 err = PTR_ERR(phylink);
4418 mac->phylink = phylink;
4420 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
4421 eth->netdev[id]->watchdog_timeo = 5 * HZ;
4422 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
4423 eth->netdev[id]->base_addr = (unsigned long)eth->base;
4425 eth->netdev[id]->hw_features = eth->soc->hw_features;
4427 eth->netdev[id]->hw_features |= NETIF_F_LRO;
4429 eth->netdev[id]->vlan_features = eth->soc->hw_features &
4430 ~NETIF_F_HW_VLAN_CTAG_TX;
4431 eth->netdev[id]->features |= eth->soc->hw_features;
4432 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
4434 eth->netdev[id]->irq = eth->irq[0];
4435 eth->netdev[id]->dev.of_node = np;
4437 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
4438 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
4440 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN;
4442 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
4443 mac->device_notifier.notifier_call = mtk_device_event;
4444 register_netdevice_notifier(&mac->device_notifier);
4447 if (mtk_page_pool_enabled(eth))
4448 eth->netdev[id]->xdp_features = NETDEV_XDP_ACT_BASIC |
4449 NETDEV_XDP_ACT_REDIRECT |
4450 NETDEV_XDP_ACT_NDO_XMIT |
4451 NETDEV_XDP_ACT_NDO_XMIT_SG;
4456 free_netdev(eth->netdev[id]);
4460 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev)
4462 struct net_device *dev, *tmp;
4463 LIST_HEAD(dev_list);
4468 for (i = 0; i < MTK_MAC_COUNT; i++) {
4469 dev = eth->netdev[i];
4471 if (!dev || !(dev->flags & IFF_UP))
4474 list_add_tail(&dev->close_list, &dev_list);
4477 dev_close_many(&dev_list, false);
4479 eth->dma_dev = dma_dev;
4481 list_for_each_entry_safe(dev, tmp, &dev_list, close_list) {
4482 list_del_init(&dev->close_list);
4483 dev_open(dev, NULL);
4489 static int mtk_sgmii_init(struct mtk_eth *eth)
4491 struct device_node *np;
4492 struct regmap *regmap;
4496 for (i = 0; i < MTK_MAX_DEVS; i++) {
4497 np = of_parse_phandle(eth->dev->of_node, "mediatek,sgmiisys", i);
4501 regmap = syscon_node_to_regmap(np);
4503 if (of_property_read_bool(np, "mediatek,pnswap"))
4504 flags |= MTK_SGMII_FLAG_PN_SWAP;
4509 return PTR_ERR(regmap);
4511 eth->sgmii_pcs[i] = mtk_pcs_lynxi_create(eth->dev, regmap,
4519 static int mtk_probe(struct platform_device *pdev)
4521 struct resource *res = NULL;
4522 struct device_node *mac_np;
4523 struct mtk_eth *eth;
4526 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
4530 eth->soc = of_device_get_match_data(&pdev->dev);
4532 eth->dev = &pdev->dev;
4533 eth->dma_dev = &pdev->dev;
4534 eth->base = devm_platform_ioremap_resource(pdev, 0);
4535 if (IS_ERR(eth->base))
4536 return PTR_ERR(eth->base);
4538 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
4539 eth->ip_align = NET_IP_ALIGN;
4541 spin_lock_init(ð->page_lock);
4542 spin_lock_init(ð->tx_irq_lock);
4543 spin_lock_init(ð->rx_irq_lock);
4544 spin_lock_init(ð->dim_lock);
4546 eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4547 INIT_WORK(ð->rx_dim.work, mtk_dim_rx);
4548 INIT_DELAYED_WORK(ð->reset.monitor_work, mtk_hw_reset_monitor_work);
4550 eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4551 INIT_WORK(ð->tx_dim.work, mtk_dim_tx);
4553 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
4554 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
4556 if (IS_ERR(eth->ethsys)) {
4557 dev_err(&pdev->dev, "no ethsys regmap found\n");
4558 return PTR_ERR(eth->ethsys);
4562 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) {
4563 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
4564 "mediatek,infracfg");
4565 if (IS_ERR(eth->infra)) {
4566 dev_err(&pdev->dev, "no infracfg regmap found\n");
4567 return PTR_ERR(eth->infra);
4571 if (of_dma_is_coherent(pdev->dev.of_node)) {
4574 cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
4575 "cci-control-port");
4576 /* enable CPU/bus coherency */
4578 regmap_write(cci, 0, 3);
4581 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
4582 err = mtk_sgmii_init(eth);
4588 if (eth->soc->required_pctl) {
4589 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
4591 if (IS_ERR(eth->pctl)) {
4592 dev_err(&pdev->dev, "no pctl regmap found\n");
4593 err = PTR_ERR(eth->pctl);
4594 goto err_destroy_sgmii;
4598 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
4599 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4602 goto err_destroy_sgmii;
4606 if (eth->soc->offload_version) {
4608 struct device_node *np;
4609 phys_addr_t wdma_phy;
4612 if (i >= ARRAY_SIZE(eth->soc->reg_map->wdma_base))
4615 np = of_parse_phandle(pdev->dev.of_node,
4620 wdma_base = eth->soc->reg_map->wdma_base[i];
4621 wdma_phy = res ? res->start + wdma_base : 0;
4622 mtk_wed_add_hw(np, eth, eth->base + wdma_base,
4627 for (i = 0; i < 3; i++) {
4628 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0)
4629 eth->irq[i] = eth->irq[0];
4631 eth->irq[i] = platform_get_irq(pdev, i);
4632 if (eth->irq[i] < 0) {
4633 dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
4638 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) {
4639 eth->clks[i] = devm_clk_get(eth->dev,
4640 mtk_clks_source_name[i]);
4641 if (IS_ERR(eth->clks[i])) {
4642 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) {
4643 err = -EPROBE_DEFER;
4646 if (eth->soc->required_clks & BIT(i)) {
4647 dev_err(&pdev->dev, "clock %s not found\n",
4648 mtk_clks_source_name[i]);
4652 eth->clks[i] = NULL;
4656 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
4657 INIT_WORK(ð->pending_work, mtk_pending_work);
4659 err = mtk_hw_init(eth, false);
4663 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO);
4665 for_each_child_of_node(pdev->dev.of_node, mac_np) {
4666 if (!of_device_is_compatible(mac_np,
4667 "mediatek,eth-mac"))
4670 if (!of_device_is_available(mac_np))
4673 err = mtk_add_mac(eth, mac_np);
4675 of_node_put(mac_np);
4680 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) {
4681 err = devm_request_irq(eth->dev, eth->irq[0],
4683 dev_name(eth->dev), eth);
4685 err = devm_request_irq(eth->dev, eth->irq[1],
4686 mtk_handle_irq_tx, 0,
4687 dev_name(eth->dev), eth);
4691 err = devm_request_irq(eth->dev, eth->irq[2],
4692 mtk_handle_irq_rx, 0,
4693 dev_name(eth->dev), eth);
4698 /* No MT7628/88 support yet */
4699 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
4700 err = mtk_mdio_init(eth);
4705 if (eth->soc->offload_version) {
4708 num_ppe = MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ? 2 : 1;
4709 num_ppe = min_t(u32, ARRAY_SIZE(eth->ppe), num_ppe);
4710 for (i = 0; i < num_ppe; i++) {
4711 u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400;
4713 eth->ppe[i] = mtk_ppe_init(eth, eth->base + ppe_addr, i);
4717 goto err_deinit_ppe;
4721 err = mtk_eth_offload_init(eth);
4723 goto err_deinit_ppe;
4726 for (i = 0; i < MTK_MAX_DEVS; i++) {
4727 if (!eth->netdev[i])
4730 err = register_netdev(eth->netdev[i]);
4732 dev_err(eth->dev, "error bringing up device\n");
4733 goto err_deinit_ppe;
4735 netif_info(eth, probe, eth->netdev[i],
4736 "mediatek frame engine at 0x%08lx, irq %d\n",
4737 eth->netdev[i]->base_addr, eth->irq[0]);
4740 /* we run 2 devices on the same DMA ring so we need a dummy device
4743 init_dummy_netdev(ð->dummy_dev);
4744 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx);
4745 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx);
4747 platform_set_drvdata(pdev, eth);
4748 schedule_delayed_work(ð->reset.monitor_work,
4749 MTK_DMA_MONITOR_TIMEOUT);
4754 mtk_ppe_deinit(eth);
4755 mtk_mdio_cleanup(eth);
4763 mtk_sgmii_destroy(eth);
4768 static int mtk_remove(struct platform_device *pdev)
4770 struct mtk_eth *eth = platform_get_drvdata(pdev);
4771 struct mtk_mac *mac;
4774 /* stop all devices to make sure that dma is properly shut down */
4775 for (i = 0; i < MTK_MAC_COUNT; i++) {
4776 if (!eth->netdev[i])
4778 mtk_stop(eth->netdev[i]);
4779 mac = netdev_priv(eth->netdev[i]);
4780 phylink_disconnect_phy(mac->phylink);
4786 netif_napi_del(ð->tx_napi);
4787 netif_napi_del(ð->rx_napi);
4789 mtk_mdio_cleanup(eth);
4794 static const struct mtk_soc_data mt2701_data = {
4795 .reg_map = &mtk_reg_map,
4796 .caps = MT7623_CAPS | MTK_HWLRO,
4797 .hw_features = MTK_HW_FEATURES,
4798 .required_clks = MT7623_CLKS_BITMAP,
4799 .required_pctl = true,
4801 .txd_size = sizeof(struct mtk_tx_dma),
4802 .rxd_size = sizeof(struct mtk_rx_dma),
4803 .rx_irq_done_mask = MTK_RX_DONE_INT,
4804 .rx_dma_l4_valid = RX_DMA_L4_VALID,
4805 .dma_max_len = MTK_TX_DMA_BUF_LEN,
4806 .dma_len_offset = 16,
4810 static const struct mtk_soc_data mt7621_data = {
4811 .reg_map = &mtk_reg_map,
4812 .caps = MT7621_CAPS,
4813 .hw_features = MTK_HW_FEATURES,
4814 .required_clks = MT7621_CLKS_BITMAP,
4815 .required_pctl = false,
4816 .offload_version = 1,
4818 .foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
4820 .txd_size = sizeof(struct mtk_tx_dma),
4821 .rxd_size = sizeof(struct mtk_rx_dma),
4822 .rx_irq_done_mask = MTK_RX_DONE_INT,
4823 .rx_dma_l4_valid = RX_DMA_L4_VALID,
4824 .dma_max_len = MTK_TX_DMA_BUF_LEN,
4825 .dma_len_offset = 16,
4829 static const struct mtk_soc_data mt7622_data = {
4830 .reg_map = &mtk_reg_map,
4832 .caps = MT7622_CAPS | MTK_HWLRO,
4833 .hw_features = MTK_HW_FEATURES,
4834 .required_clks = MT7622_CLKS_BITMAP,
4835 .required_pctl = false,
4836 .offload_version = 2,
4838 .has_accounting = true,
4839 .foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
4841 .txd_size = sizeof(struct mtk_tx_dma),
4842 .rxd_size = sizeof(struct mtk_rx_dma),
4843 .rx_irq_done_mask = MTK_RX_DONE_INT,
4844 .rx_dma_l4_valid = RX_DMA_L4_VALID,
4845 .dma_max_len = MTK_TX_DMA_BUF_LEN,
4846 .dma_len_offset = 16,
4850 static const struct mtk_soc_data mt7623_data = {
4851 .reg_map = &mtk_reg_map,
4852 .caps = MT7623_CAPS | MTK_HWLRO,
4853 .hw_features = MTK_HW_FEATURES,
4854 .required_clks = MT7623_CLKS_BITMAP,
4855 .required_pctl = true,
4856 .offload_version = 1,
4858 .foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
4860 .txd_size = sizeof(struct mtk_tx_dma),
4861 .rxd_size = sizeof(struct mtk_rx_dma),
4862 .rx_irq_done_mask = MTK_RX_DONE_INT,
4863 .rx_dma_l4_valid = RX_DMA_L4_VALID,
4864 .dma_max_len = MTK_TX_DMA_BUF_LEN,
4865 .dma_len_offset = 16,
4869 static const struct mtk_soc_data mt7629_data = {
4870 .reg_map = &mtk_reg_map,
4872 .caps = MT7629_CAPS | MTK_HWLRO,
4873 .hw_features = MTK_HW_FEATURES,
4874 .required_clks = MT7629_CLKS_BITMAP,
4875 .required_pctl = false,
4876 .has_accounting = true,
4878 .txd_size = sizeof(struct mtk_tx_dma),
4879 .rxd_size = sizeof(struct mtk_rx_dma),
4880 .rx_irq_done_mask = MTK_RX_DONE_INT,
4881 .rx_dma_l4_valid = RX_DMA_L4_VALID,
4882 .dma_max_len = MTK_TX_DMA_BUF_LEN,
4883 .dma_len_offset = 16,
4887 static const struct mtk_soc_data mt7981_data = {
4888 .reg_map = &mt7986_reg_map,
4890 .caps = MT7981_CAPS,
4891 .hw_features = MTK_HW_FEATURES,
4892 .required_clks = MT7981_CLKS_BITMAP,
4893 .required_pctl = false,
4894 .offload_version = 2,
4896 .foe_entry_size = sizeof(struct mtk_foe_entry),
4897 .has_accounting = true,
4899 .txd_size = sizeof(struct mtk_tx_dma_v2),
4900 .rxd_size = sizeof(struct mtk_rx_dma_v2),
4901 .rx_irq_done_mask = MTK_RX_DONE_INT_V2,
4902 .rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
4903 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
4904 .dma_len_offset = 8,
4908 static const struct mtk_soc_data mt7986_data = {
4909 .reg_map = &mt7986_reg_map,
4911 .caps = MT7986_CAPS,
4912 .hw_features = MTK_HW_FEATURES,
4913 .required_clks = MT7986_CLKS_BITMAP,
4914 .required_pctl = false,
4915 .offload_version = 2,
4917 .foe_entry_size = sizeof(struct mtk_foe_entry),
4918 .has_accounting = true,
4920 .txd_size = sizeof(struct mtk_tx_dma_v2),
4921 .rxd_size = sizeof(struct mtk_rx_dma_v2),
4922 .rx_irq_done_mask = MTK_RX_DONE_INT_V2,
4923 .rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
4924 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
4925 .dma_len_offset = 8,
4929 static const struct mtk_soc_data rt5350_data = {
4930 .reg_map = &mt7628_reg_map,
4931 .caps = MT7628_CAPS,
4932 .hw_features = MTK_HW_FEATURES_MT7628,
4933 .required_clks = MT7628_CLKS_BITMAP,
4934 .required_pctl = false,
4936 .txd_size = sizeof(struct mtk_tx_dma),
4937 .rxd_size = sizeof(struct mtk_rx_dma),
4938 .rx_irq_done_mask = MTK_RX_DONE_INT,
4939 .rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA,
4940 .dma_max_len = MTK_TX_DMA_BUF_LEN,
4941 .dma_len_offset = 16,
4945 const struct of_device_id of_mtk_match[] = {
4946 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data},
4947 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data},
4948 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
4949 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
4950 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data},
4951 { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data},
4952 { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data},
4953 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data},
4956 MODULE_DEVICE_TABLE(of, of_mtk_match);
4958 static struct platform_driver mtk_driver = {
4960 .remove = mtk_remove,
4962 .name = "mtk_soc_eth",
4963 .of_match_table = of_mtk_match,
4967 module_platform_driver(mtk_driver);
4969 MODULE_LICENSE("GPL");
4970 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
4971 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");