1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell RVU Virtual Function ethernet driver
4 * Copyright (C) 2020 Marvell.
8 #include <linux/etherdevice.h>
9 #include <linux/module.h>
10 #include <linux/pci.h>
11 #include <linux/net_tstamp.h>
13 #include "otx2_common.h"
18 #define DRV_NAME "rvu_nicvf"
19 #define DRV_STRING "Marvell RVU NIC Virtual Function Driver"
21 static const struct pci_device_id otx2_vf_id_table[] = {
22 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AFVF) },
23 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF) },
27 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>");
28 MODULE_DESCRIPTION(DRV_STRING);
29 MODULE_LICENSE("GPL v2");
30 MODULE_DEVICE_TABLE(pci, otx2_vf_id_table);
32 /* RVU VF Interrupt Vector Enumeration */
34 RVU_VF_INT_VEC_MBOX = 0x0,
37 static void otx2vf_process_vfaf_mbox_msg(struct otx2_nic *vf,
38 struct mbox_msghdr *msg)
40 if (msg->id >= MBOX_MSG_MAX) {
42 "Mbox msg with unknown ID %d\n", msg->id);
46 if (msg->sig != OTX2_MBOX_RSP_SIG) {
48 "Mbox msg with wrong signature %x, ID %d\n",
53 if (msg->rc == MBOX_MSG_INVALID) {
55 "PF/AF says the sent msg(s) %d were invalid\n",
62 vf->pcifunc = msg->pcifunc;
64 case MBOX_MSG_MSIX_OFFSET:
65 mbox_handler_msix_offset(vf, (struct msix_offset_rsp *)msg);
67 case MBOX_MSG_NPA_LF_ALLOC:
68 mbox_handler_npa_lf_alloc(vf, (struct npa_lf_alloc_rsp *)msg);
70 case MBOX_MSG_NIX_LF_ALLOC:
71 mbox_handler_nix_lf_alloc(vf, (struct nix_lf_alloc_rsp *)msg);
73 case MBOX_MSG_NIX_BP_ENABLE:
74 mbox_handler_nix_bp_enable(vf, (struct nix_bp_cfg_rsp *)msg);
79 "Mbox msg response has err %d, ID %d\n",
84 static void otx2vf_vfaf_mbox_handler(struct work_struct *work)
86 struct otx2_mbox_dev *mdev;
87 struct mbox_hdr *rsp_hdr;
88 struct mbox_msghdr *msg;
89 struct otx2_mbox *mbox;
93 af_mbox = container_of(work, struct mbox, mbox_wrk);
94 mbox = &af_mbox->mbox;
96 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
97 if (af_mbox->num_msgs == 0)
99 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
101 for (id = 0; id < af_mbox->num_msgs; id++) {
102 msg = (struct mbox_msghdr *)(mdev->mbase + offset);
103 otx2vf_process_vfaf_mbox_msg(af_mbox->pfvf, msg);
104 offset = mbox->rx_start + msg->next_msgoff;
105 if (mdev->msgs_acked == (af_mbox->num_msgs - 1))
106 __otx2_mbox_reset(mbox, 0);
111 static int otx2vf_process_mbox_msg_up(struct otx2_nic *vf,
112 struct mbox_msghdr *req)
117 /* Check if valid, if not reply with a invalid msg */
118 if (req->sig != OTX2_MBOX_REQ_SIG) {
119 otx2_reply_invalid_msg(&vf->mbox.mbox_up, 0, 0, req->id);
124 case MBOX_MSG_CGX_LINK_EVENT:
125 rsp = (struct msg_rsp *)otx2_mbox_alloc_msg(
126 &vf->mbox.mbox_up, 0,
127 sizeof(struct msg_rsp));
131 rsp->hdr.id = MBOX_MSG_CGX_LINK_EVENT;
132 rsp->hdr.sig = OTX2_MBOX_RSP_SIG;
133 rsp->hdr.pcifunc = 0;
135 err = otx2_mbox_up_handler_cgx_link_event(
136 vf, (struct cgx_link_info_msg *)req, rsp);
139 otx2_reply_invalid_msg(&vf->mbox.mbox_up, 0, 0, req->id);
145 static void otx2vf_vfaf_mbox_up_handler(struct work_struct *work)
147 struct otx2_mbox_dev *mdev;
148 struct mbox_hdr *rsp_hdr;
149 struct mbox_msghdr *msg;
150 struct otx2_mbox *mbox;
151 struct mbox *vf_mbox;
155 vf_mbox = container_of(work, struct mbox, mbox_up_wrk);
157 mbox = &vf_mbox->mbox_up;
158 mdev = &mbox->dev[0];
160 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
161 if (vf_mbox->up_num_msgs == 0)
164 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
166 for (id = 0; id < vf_mbox->up_num_msgs; id++) {
167 msg = (struct mbox_msghdr *)(mdev->mbase + offset);
168 otx2vf_process_mbox_msg_up(vf, msg);
169 offset = mbox->rx_start + msg->next_msgoff;
172 otx2_mbox_msg_send(mbox, 0);
175 static irqreturn_t otx2vf_vfaf_mbox_intr_handler(int irq, void *vf_irq)
177 struct otx2_nic *vf = (struct otx2_nic *)vf_irq;
178 struct otx2_mbox_dev *mdev;
179 struct otx2_mbox *mbox;
180 struct mbox_hdr *hdr;
183 otx2_write64(vf, RVU_VF_INT, BIT_ULL(0));
185 /* Read latest mbox data */
188 /* Check for PF => VF response messages */
189 mbox = &vf->mbox.mbox;
190 mdev = &mbox->dev[0];
191 otx2_sync_mbox_bbuf(mbox, 0);
193 trace_otx2_msg_interrupt(mbox->pdev, "PF to VF", BIT_ULL(0));
195 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
197 vf->mbox.num_msgs = hdr->num_msgs;
199 memset(mbox->hwbase + mbox->rx_start, 0,
200 ALIGN(sizeof(struct mbox_hdr), sizeof(u64)));
201 queue_work(vf->mbox_wq, &vf->mbox.mbox_wrk);
203 /* Check for PF => VF notification messages */
204 mbox = &vf->mbox.mbox_up;
205 mdev = &mbox->dev[0];
206 otx2_sync_mbox_bbuf(mbox, 0);
208 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
210 vf->mbox.up_num_msgs = hdr->num_msgs;
212 memset(mbox->hwbase + mbox->rx_start, 0,
213 ALIGN(sizeof(struct mbox_hdr), sizeof(u64)));
214 queue_work(vf->mbox_wq, &vf->mbox.mbox_up_wrk);
220 static void otx2vf_disable_mbox_intr(struct otx2_nic *vf)
222 int vector = pci_irq_vector(vf->pdev, RVU_VF_INT_VEC_MBOX);
224 /* Disable VF => PF mailbox IRQ */
225 otx2_write64(vf, RVU_VF_INT_ENA_W1C, BIT_ULL(0));
226 free_irq(vector, vf);
229 static int otx2vf_register_mbox_intr(struct otx2_nic *vf, bool probe_pf)
231 struct otx2_hw *hw = &vf->hw;
236 /* Register mailbox interrupt handler */
237 irq_name = &hw->irq_name[RVU_VF_INT_VEC_MBOX * NAME_SIZE];
238 snprintf(irq_name, NAME_SIZE, "RVUVFAF Mbox");
239 err = request_irq(pci_irq_vector(vf->pdev, RVU_VF_INT_VEC_MBOX),
240 otx2vf_vfaf_mbox_intr_handler, 0, irq_name, vf);
243 "RVUPF: IRQ registration failed for VFAF mbox irq\n");
247 /* Enable mailbox interrupt for msgs coming from PF.
248 * First clear to avoid spurious interrupts, if any.
250 otx2_write64(vf, RVU_VF_INT, BIT_ULL(0));
251 otx2_write64(vf, RVU_VF_INT_ENA_W1S, BIT_ULL(0));
256 /* Check mailbox communication with PF */
257 req = otx2_mbox_alloc_msg_ready(&vf->mbox);
259 otx2vf_disable_mbox_intr(vf);
263 err = otx2_sync_mbox_msg(&vf->mbox);
266 "AF not responding to mailbox, deferring probe\n");
267 otx2vf_disable_mbox_intr(vf);
268 return -EPROBE_DEFER;
273 static void otx2vf_vfaf_mbox_destroy(struct otx2_nic *vf)
275 struct mbox *mbox = &vf->mbox;
278 destroy_workqueue(vf->mbox_wq);
282 if (mbox->mbox.hwbase && !test_bit(CN10K_MBOX, &vf->hw.cap_flag))
283 iounmap((void __iomem *)mbox->mbox.hwbase);
285 otx2_mbox_destroy(&mbox->mbox);
286 otx2_mbox_destroy(&mbox->mbox_up);
289 static int otx2vf_vfaf_mbox_init(struct otx2_nic *vf)
291 struct mbox *mbox = &vf->mbox;
292 void __iomem *hwbase;
296 vf->mbox_wq = alloc_ordered_workqueue("otx2_vfaf_mailbox",
297 WQ_HIGHPRI | WQ_MEM_RECLAIM);
301 if (test_bit(CN10K_MBOX, &vf->hw.cap_flag)) {
302 /* For cn10k platform, VF mailbox region is in its BAR2
305 hwbase = vf->reg_base + RVU_VF_MBOX_REGION;
307 /* Mailbox is a reserved memory (in RAM) region shared between
308 * admin function (i.e PF0) and this VF, shouldn't be mapped as
309 * device memory to allow unaligned accesses.
311 hwbase = ioremap_wc(pci_resource_start(vf->pdev,
313 pci_resource_len(vf->pdev,
316 dev_err(vf->dev, "Unable to map VFAF mailbox region\n");
322 err = otx2_mbox_init(&mbox->mbox, hwbase, vf->pdev, vf->reg_base,
327 err = otx2_mbox_init(&mbox->mbox_up, hwbase, vf->pdev, vf->reg_base,
328 MBOX_DIR_VFPF_UP, 1);
332 err = otx2_mbox_bbuf_init(mbox, vf->pdev);
336 INIT_WORK(&mbox->mbox_wrk, otx2vf_vfaf_mbox_handler);
337 INIT_WORK(&mbox->mbox_up_wrk, otx2vf_vfaf_mbox_up_handler);
338 mutex_init(&mbox->lock);
342 if (hwbase && !test_bit(CN10K_MBOX, &vf->hw.cap_flag))
344 destroy_workqueue(vf->mbox_wq);
348 static int otx2vf_open(struct net_device *netdev)
353 err = otx2_open(netdev);
357 /* LBKs do not receive link events so tell everyone we are up here */
358 vf = netdev_priv(netdev);
359 if (is_otx2_lbkvf(vf->pdev)) {
360 pr_info("%s NIC Link is UP\n", netdev->name);
361 netif_carrier_on(netdev);
362 netif_tx_start_all_queues(netdev);
368 static int otx2vf_stop(struct net_device *netdev)
370 return otx2_stop(netdev);
373 static netdev_tx_t otx2vf_xmit(struct sk_buff *skb, struct net_device *netdev)
375 struct otx2_nic *vf = netdev_priv(netdev);
376 int qidx = skb_get_queue_mapping(skb);
377 struct otx2_snd_queue *sq;
378 struct netdev_queue *txq;
380 sq = &vf->qset.sq[qidx];
381 txq = netdev_get_tx_queue(netdev, qidx);
383 if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) {
384 netif_tx_stop_queue(txq);
386 /* Check again, incase SQBs got freed up */
388 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb)
390 netif_tx_wake_queue(txq);
392 return NETDEV_TX_BUSY;
398 static void otx2vf_set_rx_mode(struct net_device *netdev)
400 struct otx2_nic *vf = netdev_priv(netdev);
402 queue_work(vf->otx2_wq, &vf->rx_mode_work);
405 static void otx2vf_do_set_rx_mode(struct work_struct *work)
407 struct otx2_nic *vf = container_of(work, struct otx2_nic, rx_mode_work);
408 struct net_device *netdev = vf->netdev;
409 unsigned int flags = netdev->flags;
410 struct nix_rx_mode *req;
412 mutex_lock(&vf->mbox.lock);
414 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&vf->mbox);
416 mutex_unlock(&vf->mbox.lock);
420 req->mode = NIX_RX_MODE_UCAST;
422 if (flags & IFF_PROMISC)
423 req->mode |= NIX_RX_MODE_PROMISC;
424 if (flags & (IFF_ALLMULTI | IFF_MULTICAST))
425 req->mode |= NIX_RX_MODE_ALLMULTI;
427 req->mode |= NIX_RX_MODE_USE_MCE;
429 otx2_sync_mbox_msg(&vf->mbox);
431 mutex_unlock(&vf->mbox.lock);
434 static int otx2vf_change_mtu(struct net_device *netdev, int new_mtu)
436 bool if_up = netif_running(netdev);
442 netdev_info(netdev, "Changing MTU from %d to %d\n",
443 netdev->mtu, new_mtu);
444 netdev->mtu = new_mtu;
447 err = otx2vf_open(netdev);
452 static void otx2vf_reset_task(struct work_struct *work)
454 struct otx2_nic *vf = container_of(work, struct otx2_nic, reset_task);
458 if (netif_running(vf->netdev)) {
459 otx2vf_stop(vf->netdev);
461 otx2vf_open(vf->netdev);
467 static int otx2vf_set_features(struct net_device *netdev,
468 netdev_features_t features)
470 return otx2_handle_ntuple_tc_features(netdev, features);
473 static const struct net_device_ops otx2vf_netdev_ops = {
474 .ndo_open = otx2vf_open,
475 .ndo_stop = otx2vf_stop,
476 .ndo_start_xmit = otx2vf_xmit,
477 .ndo_select_queue = otx2_select_queue,
478 .ndo_set_rx_mode = otx2vf_set_rx_mode,
479 .ndo_set_mac_address = otx2_set_mac_address,
480 .ndo_change_mtu = otx2vf_change_mtu,
481 .ndo_set_features = otx2vf_set_features,
482 .ndo_get_stats64 = otx2_get_stats64,
483 .ndo_tx_timeout = otx2_tx_timeout,
484 .ndo_eth_ioctl = otx2_ioctl,
485 .ndo_setup_tc = otx2_setup_tc,
488 static int otx2_wq_init(struct otx2_nic *vf)
490 vf->otx2_wq = create_singlethread_workqueue("otx2vf_wq");
494 INIT_WORK(&vf->rx_mode_work, otx2vf_do_set_rx_mode);
495 INIT_WORK(&vf->reset_task, otx2vf_reset_task);
499 static int otx2vf_realloc_msix_vectors(struct otx2_nic *vf)
501 struct otx2_hw *hw = &vf->hw;
504 num_vec = hw->nix_msixoff;
505 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues;
507 otx2vf_disable_mbox_intr(vf);
508 pci_free_irq_vectors(hw->pdev);
509 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX);
511 dev_err(vf->dev, "%s: Failed to realloc %d IRQ vectors\n",
516 return otx2vf_register_mbox_intr(vf, false);
519 static int otx2vf_probe(struct pci_dev *pdev, const struct pci_device_id *id)
521 int num_vec = pci_msix_vec_count(pdev);
522 struct device *dev = &pdev->dev;
523 int err, qcount, qos_txqs;
524 struct net_device *netdev;
528 err = pcim_enable_device(pdev);
530 dev_err(dev, "Failed to enable PCI device\n");
534 err = pci_request_regions(pdev, DRV_NAME);
536 dev_err(dev, "PCI request regions failed 0x%x\n", err);
540 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48));
542 dev_err(dev, "DMA mask config failed, abort\n");
543 goto err_release_regions;
546 pci_set_master(pdev);
548 qcount = num_online_cpus();
549 qos_txqs = min_t(int, qcount, OTX2_QOS_MAX_LEAF_NODES);
550 netdev = alloc_etherdev_mqs(sizeof(*vf), qcount + qos_txqs, qcount);
553 goto err_release_regions;
556 pci_set_drvdata(pdev, netdev);
557 SET_NETDEV_DEV(netdev, &pdev->dev);
558 vf = netdev_priv(netdev);
562 vf->iommu_domain = iommu_get_domain_for_dev(dev);
564 vf->flags |= OTX2_FLAG_INTF_DOWN;
567 hw->rx_queues = qcount;
568 hw->tx_queues = qcount;
569 hw->max_queues = qcount;
570 hw->non_qos_queues = qcount;
571 hw->rbuf_len = OTX2_DEFAULT_RBUF_LEN;
572 /* Use CQE of 128 byte descriptor size by default */
575 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE,
579 goto err_free_netdev;
582 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec,
583 sizeof(cpumask_var_t), GFP_KERNEL);
584 if (!hw->affinity_mask) {
586 goto err_free_netdev;
589 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX);
591 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n",
593 goto err_free_netdev;
596 vf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
598 dev_err(dev, "Unable to map physical function CSRs, aborting\n");
600 goto err_free_irq_vectors;
603 otx2_setup_dev_hw_settings(vf);
604 /* Init VF <=> PF mailbox stuff */
605 err = otx2vf_vfaf_mbox_init(vf);
607 goto err_free_irq_vectors;
609 /* Register mailbox interrupt */
610 err = otx2vf_register_mbox_intr(vf, true);
612 goto err_mbox_destroy;
614 /* Request AF to attach NPA and LIX LFs to this AF */
615 err = otx2_attach_npa_nix(vf);
617 goto err_disable_mbox_intr;
619 err = otx2vf_realloc_msix_vectors(vf);
621 goto err_detach_rsrc;
623 err = otx2_set_real_num_queues(netdev, qcount, qcount);
625 goto err_detach_rsrc;
627 err = cn10k_lmtst_init(vf);
629 goto err_detach_rsrc;
631 /* Don't check for error. Proceed without ptp */
634 /* Assign default mac address */
635 otx2_get_mac_from_af(netdev);
637 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM |
638 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH |
639 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
641 netdev->features = netdev->hw_features;
642 /* Support TSO on tag interface */
643 netdev->vlan_features |= netdev->features;
644 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
645 NETIF_F_HW_VLAN_STAG_TX;
646 netdev->features |= netdev->hw_features;
648 netdev->hw_features |= NETIF_F_NTUPLE;
649 netdev->hw_features |= NETIF_F_RXALL;
650 netdev->hw_features |= NETIF_F_HW_TC;
652 netif_set_tso_max_segs(netdev, OTX2_MAX_GSO_SEGS);
653 netdev->watchdog_timeo = OTX2_TX_TIMEOUT;
655 netdev->netdev_ops = &otx2vf_netdev_ops;
657 netdev->min_mtu = OTX2_MIN_MTU;
658 netdev->max_mtu = otx2_get_max_mtu(vf);
660 /* To distinguish, for LBK VFs set netdev name explicitly */
661 if (is_otx2_lbkvf(vf->pdev)) {
664 n = (vf->pcifunc >> RVU_PFVF_FUNC_SHIFT) & RVU_PFVF_FUNC_MASK;
665 /* Need to subtract 1 to get proper VF number */
667 snprintf(netdev->name, sizeof(netdev->name), "lbk%d", n);
670 err = register_netdev(netdev);
672 dev_err(dev, "Failed to register netdevice\n");
673 goto err_ptp_destroy;
676 err = otx2_wq_init(vf);
678 goto err_unreg_netdev;
680 otx2vf_set_ethtool_ops(netdev);
682 err = otx2vf_mcam_flow_init(vf);
684 goto err_unreg_netdev;
686 err = otx2_init_tc(vf);
688 goto err_unreg_netdev;
690 err = otx2_register_dl(vf);
692 goto err_shutdown_tc;
695 err = otx2_dcbnl_set_ops(netdev);
697 goto err_shutdown_tc;
699 otx2_qos_init(vf, qos_txqs);
704 otx2_shutdown_tc(vf);
706 unregister_netdev(netdev);
708 otx2_ptp_destroy(vf);
710 free_percpu(vf->hw.lmt_info);
711 if (test_bit(CN10K_LMTST, &vf->hw.cap_flag))
712 qmem_free(vf->dev, vf->dync_lmt);
713 otx2_detach_resources(&vf->mbox);
714 err_disable_mbox_intr:
715 otx2vf_disable_mbox_intr(vf);
717 otx2vf_vfaf_mbox_destroy(vf);
718 err_free_irq_vectors:
719 pci_free_irq_vectors(hw->pdev);
721 pci_set_drvdata(pdev, NULL);
724 pci_release_regions(pdev);
728 static void otx2vf_remove(struct pci_dev *pdev)
730 struct net_device *netdev = pci_get_drvdata(pdev);
736 vf = netdev_priv(netdev);
738 /* Disable 802.3x pause frames */
739 if (vf->flags & OTX2_FLAG_RX_PAUSE_ENABLED ||
740 (vf->flags & OTX2_FLAG_TX_PAUSE_ENABLED)) {
741 vf->flags &= ~OTX2_FLAG_RX_PAUSE_ENABLED;
742 vf->flags &= ~OTX2_FLAG_TX_PAUSE_ENABLED;
743 otx2_config_pause_frm(vf);
747 /* Disable PFC config */
750 otx2_config_priority_flow_ctrl(vf);
754 cancel_work_sync(&vf->reset_task);
755 otx2_unregister_dl(vf);
756 unregister_netdev(netdev);
758 destroy_workqueue(vf->otx2_wq);
759 otx2_ptp_destroy(vf);
760 otx2_mcam_flow_del(vf);
761 otx2_shutdown_tc(vf);
762 otx2_shutdown_qos(vf);
763 otx2vf_disable_mbox_intr(vf);
764 otx2_detach_resources(&vf->mbox);
765 free_percpu(vf->hw.lmt_info);
766 if (test_bit(CN10K_LMTST, &vf->hw.cap_flag))
767 qmem_free(vf->dev, vf->dync_lmt);
768 otx2vf_vfaf_mbox_destroy(vf);
769 pci_free_irq_vectors(vf->pdev);
770 pci_set_drvdata(pdev, NULL);
773 pci_release_regions(pdev);
776 static struct pci_driver otx2vf_driver = {
778 .id_table = otx2_vf_id_table,
779 .probe = otx2vf_probe,
780 .remove = otx2vf_remove,
781 .shutdown = otx2vf_remove,
784 static int __init otx2vf_init_module(void)
786 pr_info("%s: %s\n", DRV_NAME, DRV_STRING);
788 return pci_register_driver(&otx2vf_driver);
791 static void __exit otx2vf_cleanup_module(void)
793 pci_unregister_driver(&otx2vf_driver);
796 module_init(otx2vf_init_module);
797 module_exit(otx2vf_cleanup_module);