1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell RPM CN10K driver
4 * Copyright (C) 2020 Marvell.
7 #include <linux/bitfield.h>
14 #define LMT_TBL_OP_READ 0
15 #define LMT_TBL_OP_WRITE 1
16 #define LMT_MAP_TABLE_SIZE (128 * 1024)
17 #define LMT_MAPTBL_ENTRY_SIZE 16
19 /* Function to perform operations (read/write) on lmtst map table */
20 static int lmtst_map_table_ops(struct rvu *rvu, u32 index, u64 *val,
23 void __iomem *lmt_map_base;
26 tbl_base = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_MAP_BASE);
28 lmt_map_base = ioremap_wc(tbl_base, LMT_MAP_TABLE_SIZE);
30 dev_err(rvu->dev, "Failed to setup lmt map table mapping!!\n");
34 if (lmt_tbl_op == LMT_TBL_OP_READ) {
35 *val = readq(lmt_map_base + index);
37 writeq((*val), (lmt_map_base + index));
38 /* Flushing the AP interceptor cache to make APR_LMT_MAP_ENTRY_S
39 * changes effective. Write 1 for flush and read is being used as a
40 * barrier and sets up a data dependency. Write to 0 after a write
41 * to 1 to complete the flush.
43 rvu_write64(rvu, BLKADDR_APR, APR_AF_LMT_CTL, BIT_ULL(0));
44 rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_CTL);
45 rvu_write64(rvu, BLKADDR_APR, APR_AF_LMT_CTL, 0x00);
48 iounmap(lmt_map_base);
52 static u32 rvu_get_lmtst_tbl_index(struct rvu *rvu, u16 pcifunc)
54 return ((rvu_get_pf(pcifunc) * rvu->hw->total_vfs) +
55 (pcifunc & RVU_PFVF_FUNC_MASK)) * LMT_MAPTBL_ENTRY_SIZE;
58 int rvu_mbox_handler_lmtst_tbl_setup(struct rvu *rvu,
59 struct lmtst_tbl_setup_req *req,
62 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc);
63 u32 pri_tbl_idx, sec_tbl_idx;
67 /* Reconfiguring lmtst map table in lmt region shared mode i.e. make
68 * multiple PF_FUNCs to share an LMTLINE region, so primary/base
69 * pcifunc (which is passed as an argument to mailbox) is the one
70 * whose lmt base address will be shared among other secondary
71 * pcifunc (will be the one who is calling this mailbox).
73 if (req->base_pcifunc) {
74 /* Calculating the LMT table index equivalent to primary
77 pri_tbl_idx = rvu_get_lmtst_tbl_index(rvu, req->base_pcifunc);
79 /* Truncating secondary pcifunc to calculate the LMT table index
80 * equivalent to secondary pcifunc.
82 sec_tbl_idx = rvu_get_lmtst_tbl_index(rvu, req->hdr.pcifunc);
83 /* Read the base lmt addr of the secondary pcifunc */
84 err = lmtst_map_table_ops(rvu, sec_tbl_idx, &val,
88 "Failed to read LMT map table: index 0x%x err %d\n",
93 /* Storing the seondary's lmt base address as this needs to be
94 * reverted in FLR. Also making sure this default value doesn't
95 * get overwritten on multiple calls to this mailbox.
97 if (!pfvf->lmt_base_addr)
98 pfvf->lmt_base_addr = val;
100 /* Read the base lmt addr of the primary pcifunc */
101 err = lmtst_map_table_ops(rvu, pri_tbl_idx, &val,
105 "Failed to read LMT map table: index 0x%x err %d\n",
110 /* Update the base lmt addr of secondary with primary's base
113 err = lmtst_map_table_ops(rvu, sec_tbl_idx, &val,
117 "Failed to update LMT map table: index 0x%x err %d\n",
127 /* Resetting the lmtst map table to original base addresses */
128 void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc)
130 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
134 if (is_rvu_otx2(rvu))
137 if (pfvf->lmt_base_addr) {
138 /* This corresponds to lmt map table index */
139 tbl_idx = rvu_get_lmtst_tbl_index(rvu, pcifunc);
140 /* Reverting back original lmt base addr for respective
143 err = lmtst_map_table_ops(rvu, tbl_idx, &pfvf->lmt_base_addr,
147 "Failed to update LMT map table: index 0x%x err %d\n",
149 pfvf->lmt_base_addr = 0;
153 int rvu_set_channels_base(struct rvu *rvu)
155 struct rvu_hwinfo *hw = rvu->hw;
160 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, 0);
164 nix_const = rvu_read64(rvu, blkaddr, NIX_AF_CONST);
166 hw->cgx = (nix_const >> 12) & 0xFULL;
167 hw->lmac_per_cgx = (nix_const >> 8) & 0xFULL;
168 hw->cgx_links = hw->cgx * hw->lmac_per_cgx;
169 hw->lbk_links = (nix_const >> 24) & 0xFULL;
170 hw->cpt_links = (nix_const >> 44) & 0xFULL;
173 hw->cgx_chan_base = NIX_CHAN_CGX_LMAC_CHX(0, 0, 0);
174 hw->lbk_chan_base = NIX_CHAN_LBK_CHX(0, 0);
175 hw->sdp_chan_base = NIX_CHAN_SDP_CH_START;
177 /* No Programmable channels */
178 if (!(nix_const & BIT_ULL(60)))
181 hw->cap.programmable_chans = true;
183 /* If programmable channels are present then configure
184 * channels such that all channel numbers are contiguous
185 * leaving no holes. This way the new CPT channels can be
186 * accomodated. The order of channel numbers assigned is
187 * LBK, SDP, CGX and CPT.
189 hw->sdp_chan_base = hw->lbk_chan_base + hw->lbk_links *
190 ((nix_const >> 16) & 0xFFULL);
191 hw->cgx_chan_base = hw->sdp_chan_base + hw->sdp_links * SDP_CHANNELS;
193 cpt_chan_base = hw->cgx_chan_base + hw->cgx_links *
194 (nix_const & 0xFFULL);
196 /* Out of 4096 channels start CPT from 2048 so
197 * that MSB for CPT channels is always set
199 if (cpt_chan_base <= 0x800) {
200 hw->cpt_chan_base = 0x800;
203 "CPT channels could not fit in the range 2048-4095\n");
210 #define LBK_CONNECT_NIXX(a) (0x0 + (a))
212 static void __rvu_lbk_set_chans(struct rvu *rvu, void __iomem *base,
213 u64 offset, int lbkid, u16 chans)
215 struct rvu_hwinfo *hw = rvu->hw;
218 cfg = readq(base + offset);
219 cfg &= ~(LBK_LINK_CFG_RANGE_MASK |
220 LBK_LINK_CFG_ID_MASK | LBK_LINK_CFG_BASE_MASK);
221 cfg |= FIELD_PREP(LBK_LINK_CFG_RANGE_MASK, ilog2(chans));
222 cfg |= FIELD_PREP(LBK_LINK_CFG_ID_MASK, lbkid);
223 cfg |= FIELD_PREP(LBK_LINK_CFG_BASE_MASK, hw->lbk_chan_base);
225 writeq(cfg, base + offset);
228 static void rvu_lbk_set_channels(struct rvu *rvu)
230 struct pci_dev *pdev = NULL;
236 /* To loopback packets between multiple NIX blocks
237 * mutliple LBK blocks are needed. With two NIX blocks,
238 * four LBK blocks are needed and each LBK block
239 * source and destination are as follows:
240 * LBK0 - source NIX0 and destination NIX1
241 * LBK1 - source NIX0 and destination NIX1
242 * LBK2 - source NIX1 and destination NIX0
243 * LBK3 - source NIX1 and destination NIX1
244 * As per the HRM channel numbers should be programmed as:
245 * P2X and X2P of LBK0 as same
246 * P2X and X2P of LBK3 as same
247 * P2X of LBK1 and X2P of LBK2 as same
248 * P2X of LBK2 and X2P of LBK1 as same
251 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM,
252 PCI_DEVID_OCTEONTX2_LBK, pdev);
256 base = pci_ioremap_bar(pdev, 0);
260 lbk_const = readq(base + LBK_CONST);
261 chans = FIELD_GET(LBK_CONST_CHANS, lbk_const);
262 dst = FIELD_GET(LBK_CONST_DST, lbk_const);
263 src = FIELD_GET(LBK_CONST_SRC, lbk_const);
266 if (src == LBK_CONNECT_NIXX(0)) { /* LBK0 */
267 __rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_X2P,
269 __rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_P2X,
271 } else if (src == LBK_CONNECT_NIXX(1)) { /* LBK3 */
272 __rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_X2P,
274 __rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_P2X,
278 if (src == LBK_CONNECT_NIXX(0)) { /* LBK1 */
279 __rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_X2P,
281 __rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_P2X,
283 } else if (src == LBK_CONNECT_NIXX(1)) { /* LBK2 */
284 __rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_X2P,
286 __rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_P2X,
296 static void __rvu_nix_set_channels(struct rvu *rvu, int blkaddr)
298 u64 nix_const = rvu_read64(rvu, blkaddr, NIX_AF_CONST);
299 u16 cgx_chans, lbk_chans, sdp_chans, cpt_chans;
300 struct rvu_hwinfo *hw = rvu->hw;
301 int link, nix_link = 0;
305 cgx_chans = nix_const & 0xFFULL;
306 lbk_chans = (nix_const >> 16) & 0xFFULL;
307 sdp_chans = SDP_CHANNELS;
308 cpt_chans = (nix_const >> 32) & 0xFFFULL;
310 start = hw->cgx_chan_base;
311 for (link = 0; link < hw->cgx_links; link++, nix_link++) {
312 cfg = rvu_read64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link));
313 cfg &= ~(NIX_AF_LINKX_BASE_MASK | NIX_AF_LINKX_RANGE_MASK);
314 cfg |= FIELD_PREP(NIX_AF_LINKX_RANGE_MASK, ilog2(cgx_chans));
315 cfg |= FIELD_PREP(NIX_AF_LINKX_BASE_MASK, start);
316 rvu_write64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link), cfg);
320 start = hw->lbk_chan_base;
321 for (link = 0; link < hw->lbk_links; link++, nix_link++) {
322 cfg = rvu_read64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link));
323 cfg &= ~(NIX_AF_LINKX_BASE_MASK | NIX_AF_LINKX_RANGE_MASK);
324 cfg |= FIELD_PREP(NIX_AF_LINKX_RANGE_MASK, ilog2(lbk_chans));
325 cfg |= FIELD_PREP(NIX_AF_LINKX_BASE_MASK, start);
326 rvu_write64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link), cfg);
330 start = hw->sdp_chan_base;
331 for (link = 0; link < hw->sdp_links; link++, nix_link++) {
332 cfg = rvu_read64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link));
333 cfg &= ~(NIX_AF_LINKX_BASE_MASK | NIX_AF_LINKX_RANGE_MASK);
334 cfg |= FIELD_PREP(NIX_AF_LINKX_RANGE_MASK, ilog2(sdp_chans));
335 cfg |= FIELD_PREP(NIX_AF_LINKX_BASE_MASK, start);
336 rvu_write64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link), cfg);
340 start = hw->cpt_chan_base;
341 for (link = 0; link < hw->cpt_links; link++, nix_link++) {
342 cfg = rvu_read64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link));
343 cfg &= ~(NIX_AF_LINKX_BASE_MASK | NIX_AF_LINKX_RANGE_MASK);
344 cfg |= FIELD_PREP(NIX_AF_LINKX_RANGE_MASK, ilog2(cpt_chans));
345 cfg |= FIELD_PREP(NIX_AF_LINKX_BASE_MASK, start);
346 rvu_write64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link), cfg);
351 static void rvu_nix_set_channels(struct rvu *rvu)
355 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr);
357 __rvu_nix_set_channels(rvu, blkaddr);
358 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr);
362 static void __rvu_rpm_set_channels(int cgxid, int lmacid, u16 base)
366 cfg = cgx_lmac_read(cgxid, lmacid, RPMX_CMRX_LINK_CFG);
367 cfg &= ~(RPMX_CMRX_LINK_BASE_MASK | RPMX_CMRX_LINK_RANGE_MASK);
369 /* There is no read-only constant register to read
370 * the number of channels for LMAC and it is always 16.
372 cfg |= FIELD_PREP(RPMX_CMRX_LINK_RANGE_MASK, ilog2(16));
373 cfg |= FIELD_PREP(RPMX_CMRX_LINK_BASE_MASK, base);
374 cgx_lmac_write(cgxid, lmacid, RPMX_CMRX_LINK_CFG, cfg);
377 static void rvu_rpm_set_channels(struct rvu *rvu)
379 struct rvu_hwinfo *hw = rvu->hw;
380 u16 base = hw->cgx_chan_base;
383 for (cgx = 0; cgx < rvu->cgx_cnt_max; cgx++) {
384 for (lmac = 0; lmac < hw->lmac_per_cgx; lmac++) {
385 __rvu_rpm_set_channels(cgx, lmac, base);
391 void rvu_program_channels(struct rvu *rvu)
393 struct rvu_hwinfo *hw = rvu->hw;
395 if (!hw->cap.programmable_chans)
398 rvu_nix_set_channels(rvu);
399 rvu_lbk_set_channels(rvu);
400 rvu_rpm_set_channels(rvu);