drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for Marvell PPv2 network controller for Armada 375 SoC.
   4  *
   5  * Copyright (C) 2014 Marvell
   6  *
   7  * Marcin Wojtas <mw@semihalf.com>
   8  */
   9
  10 #include <linux/acpi.h>
  11 #include <linux/kernel.h>
  12 #include <linux/netdevice.h>
  13 #include <linux/etherdevice.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/skbuff.h>
  16 #include <linux/inetdevice.h>
  17 #include <linux/mbus.h>
  18 #include <linux/module.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/cpumask.h>
  22 #include <linux/of.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/of_mdio.h>
  25 #include <linux/of_net.h>
  26 #include <linux/of_address.h>
  27 #include <linux/of_device.h>
  28 #include <linux/phy.h>
  29 #include <linux/phylink.h>
  30 #include <linux/phy/phy.h>
  31 #include <linux/clk.h>
  32 #include <linux/hrtimer.h>
  33 #include <linux/ktime.h>
  34 #include <linux/regmap.h>
  35 #include <uapi/linux/ppp_defs.h>
  36 #include <net/ip.h>
  37 #include <net/ipv6.h>
  38 #include <net/tso.h>
  39
  40 #include "mvpp2.h"
  41 #include "mvpp2_prs.h"
  42 #include "mvpp2_cls.h"
  43
  44 enum mvpp2_bm_pool_log_num {
  45         MVPP2_BM_SHORT,
  46         MVPP2_BM_LONG,
  47         MVPP2_BM_JUMBO,
  48         MVPP2_BM_POOLS_NUM
  49 };
  50
  51 static struct {
  52         int pkt_size;
  53         int buf_num;
  54 } mvpp2_pools[MVPP2_BM_POOLS_NUM];
  55
  56 /* The prototype is added here to be used in start_dev when using ACPI. This
  57  * will be removed once phylink is used for all modes (dt+ACPI).
  58  */
  59 static void mvpp2_mac_config(struct net_device *dev, unsigned int mode,
  60                              const struct phylink_link_state *state);
  61 static void mvpp2_mac_link_up(struct net_device *dev, unsigned int mode,
  62                               phy_interface_t interface, struct phy_device *phy);
  63
  64 /* Queue modes */
  65 #define MVPP2_QDIST_SINGLE_MODE 0
  66 #define MVPP2_QDIST_MULTI_MODE  1
  67
  68 static int queue_mode = MVPP2_QDIST_MULTI_MODE;
  69
  70 module_param(queue_mode, int, 0444);
  71 MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)");
  72
  73 /* Utility/helper methods */
  74
  75 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
  76 {
  77         writel(data, priv->swth_base[0] + offset);
  78 }
  79
  80 u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
  81 {
  82         return readl(priv->swth_base[0] + offset);
  83 }
  84
  85 static u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset)
  86 {
  87         return readl_relaxed(priv->swth_base[0] + offset);
  88 }
  89
  90 static inline u32 mvpp2_cpu_to_thread(struct mvpp2 *priv, int cpu)
  91 {
  92         return cpu % priv->nthreads;
  93 }
  94
  95 /* These accessors should be used to access:
  96  *
  97  * - per-thread registers, where each thread has its own copy of the
  98  *   register.
  99  *
 100  *   MVPP2_BM_VIRT_ALLOC_REG
 101  *   MVPP2_BM_ADDR_HIGH_ALLOC
 102  *   MVPP22_BM_ADDR_HIGH_RLS_REG
 103  *   MVPP2_BM_VIRT_RLS_REG
 104  *   MVPP2_ISR_RX_TX_CAUSE_REG
 105  *   MVPP2_ISR_RX_TX_MASK_REG
 106  *   MVPP2_TXQ_NUM_REG
 107  *   MVPP2_AGGR_TXQ_UPDATE_REG
 108  *   MVPP2_TXQ_RSVD_REQ_REG
 109  *   MVPP2_TXQ_RSVD_RSLT_REG
 110  *   MVPP2_TXQ_SENT_REG
 111  *   MVPP2_RXQ_NUM_REG
 112  *
 113  * - global registers that must be accessed through a specific thread
 114  *   window, because they are related to an access to a per-thread
 115  *   register
 116  *
 117  *   MVPP2_BM_PHY_ALLOC_REG    (related to MVPP2_BM_VIRT_ALLOC_REG)
 118  *   MVPP2_BM_PHY_RLS_REG      (related to MVPP2_BM_VIRT_RLS_REG)
 119  *   MVPP2_RXQ_THRESH_REG      (related to MVPP2_RXQ_NUM_REG)
 120  *   MVPP2_RXQ_DESC_ADDR_REG   (related to MVPP2_RXQ_NUM_REG)
 121  *   MVPP2_RXQ_DESC_SIZE_REG   (related to MVPP2_RXQ_NUM_REG)
 122  *   MVPP2_RXQ_INDEX_REG       (related to MVPP2_RXQ_NUM_REG)
 123  *   MVPP2_TXQ_PENDING_REG     (related to MVPP2_TXQ_NUM_REG)
 124  *   MVPP2_TXQ_DESC_ADDR_REG   (related to MVPP2_TXQ_NUM_REG)
 125  *   MVPP2_TXQ_DESC_SIZE_REG   (related to MVPP2_TXQ_NUM_REG)
 126  *   MVPP2_TXQ_INDEX_REG       (related to MVPP2_TXQ_NUM_REG)
 127  *   MVPP2_TXQ_PENDING_REG     (related to MVPP2_TXQ_NUM_REG)
 128  *   MVPP2_TXQ_PREF_BUF_REG    (related to MVPP2_TXQ_NUM_REG)
 129  *   MVPP2_TXQ_PREF_BUF_REG    (related to MVPP2_TXQ_NUM_REG)
 130  */
 131 static void mvpp2_thread_write(struct mvpp2 *priv, unsigned int thread,
 132                                u32 offset, u32 data)
 133 {
 134         writel(data, priv->swth_base[thread] + offset);
 135 }
 136
 137 static u32 mvpp2_thread_read(struct mvpp2 *priv, unsigned int thread,
 138                              u32 offset)
 139 {
 140         return readl(priv->swth_base[thread] + offset);
 141 }
 142
 143 static void mvpp2_thread_write_relaxed(struct mvpp2 *priv, unsigned int thread,
 144                                        u32 offset, u32 data)
 145 {
 146         writel_relaxed(data, priv->swth_base[thread] + offset);
 147 }
 148
 149 static u32 mvpp2_thread_read_relaxed(struct mvpp2 *priv, unsigned int thread,
 150                                      u32 offset)
 151 {
 152         return readl_relaxed(priv->swth_base[thread] + offset);
 153 }
 154
 155 static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port,
 156                                             struct mvpp2_tx_desc *tx_desc)
 157 {
 158         if (port->priv->hw_version == MVPP21)
 159                 return le32_to_cpu(tx_desc->pp21.buf_dma_addr);
 160         else
 161                 return le64_to_cpu(tx_desc->pp22.buf_dma_addr_ptp) &
 162                        MVPP2_DESC_DMA_MASK;
 163 }
 164
 165 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
 166                                       struct mvpp2_tx_desc *tx_desc,
 167                                       dma_addr_t dma_addr)
 168 {
 169         dma_addr_t addr, offset;
 170
 171         addr = dma_addr & ~MVPP2_TX_DESC_ALIGN;
 172         offset = dma_addr & MVPP2_TX_DESC_ALIGN;
 173
 174         if (port->priv->hw_version == MVPP21) {
 175                 tx_desc->pp21.buf_dma_addr = cpu_to_le32(addr);
 176                 tx_desc->pp21.packet_offset = offset;
 177         } else {
 178                 __le64 val = cpu_to_le64(addr);
 179
 180                 tx_desc->pp22.buf_dma_addr_ptp &= ~cpu_to_le64(MVPP2_DESC_DMA_MASK);
 181                 tx_desc->pp22.buf_dma_addr_ptp |= val;
 182                 tx_desc->pp22.packet_offset = offset;
 183         }
 184 }
 185
 186 static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port,
 187                                     struct mvpp2_tx_desc *tx_desc)
 188 {
 189         if (port->priv->hw_version == MVPP21)
 190                 return le16_to_cpu(tx_desc->pp21.data_size);
 191         else
 192                 return le16_to_cpu(tx_desc->pp22.data_size);
 193 }
 194
 195 static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
 196                                   struct mvpp2_tx_desc *tx_desc,
 197                                   size_t size)
 198 {
 199         if (port->priv->hw_version == MVPP21)
 200                 tx_desc->pp21.data_size = cpu_to_le16(size);
 201         else
 202                 tx_desc->pp22.data_size = cpu_to_le16(size);
 203 }
 204
 205 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
 206                                  struct mvpp2_tx_desc *tx_desc,
 207                                  unsigned int txq)
 208 {
 209         if (port->priv->hw_version == MVPP21)
 210                 tx_desc->pp21.phys_txq = txq;
 211         else
 212                 tx_desc->pp22.phys_txq = txq;
 213 }
 214
 215 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
 216                                  struct mvpp2_tx_desc *tx_desc,
 217                                  unsigned int command)
 218 {
 219         if (port->priv->hw_version == MVPP21)
 220                 tx_desc->pp21.command = cpu_to_le32(command);
 221         else
 222                 tx_desc->pp22.command = cpu_to_le32(command);
 223 }
 224
 225 static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port,
 226                                             struct mvpp2_tx_desc *tx_desc)
 227 {
 228         if (port->priv->hw_version == MVPP21)
 229                 return tx_desc->pp21.packet_offset;
 230         else
 231                 return tx_desc->pp22.packet_offset;
 232 }
 233
 234 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
 235                                             struct mvpp2_rx_desc *rx_desc)
 236 {
 237         if (port->priv->hw_version == MVPP21)
 238                 return le32_to_cpu(rx_desc->pp21.buf_dma_addr);
 239         else
 240                 return le64_to_cpu(rx_desc->pp22.buf_dma_addr_key_hash) &
 241                        MVPP2_DESC_DMA_MASK;
 242 }
 243
 244 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
 245                                              struct mvpp2_rx_desc *rx_desc)
 246 {
 247         if (port->priv->hw_version == MVPP21)
 248                 return le32_to_cpu(rx_desc->pp21.buf_cookie);
 249         else
 250                 return le64_to_cpu(rx_desc->pp22.buf_cookie_misc) &
 251                        MVPP2_DESC_DMA_MASK;
 252 }
 253
 254 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
 255                                     struct mvpp2_rx_desc *rx_desc)
 256 {
 257         if (port->priv->hw_version == MVPP21)
 258                 return le16_to_cpu(rx_desc->pp21.data_size);
 259         else
 260                 return le16_to_cpu(rx_desc->pp22.data_size);
 261 }
 262
 263 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
 264                                    struct mvpp2_rx_desc *rx_desc)
 265 {
 266         if (port->priv->hw_version == MVPP21)
 267                 return le32_to_cpu(rx_desc->pp21.status);
 268         else
 269                 return le32_to_cpu(rx_desc->pp22.status);
 270 }
 271
 272 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
 273 {
 274         txq_pcpu->txq_get_index++;
 275         if (txq_pcpu->txq_get_index == txq_pcpu->size)
 276                 txq_pcpu->txq_get_index = 0;
 277 }
 278
 279 static void mvpp2_txq_inc_put(struct mvpp2_port *port,
 280                               struct mvpp2_txq_pcpu *txq_pcpu,
 281                               struct sk_buff *skb,
 282                               struct mvpp2_tx_desc *tx_desc)
 283 {
 284         struct mvpp2_txq_pcpu_buf *tx_buf =
 285                 txq_pcpu->buffs + txq_pcpu->txq_put_index;
 286         tx_buf->skb = skb;
 287         tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc);
 288         tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) +
 289                 mvpp2_txdesc_offset_get(port, tx_desc);
 290         txq_pcpu->txq_put_index++;
 291         if (txq_pcpu->txq_put_index == txq_pcpu->size)
 292                 txq_pcpu->txq_put_index = 0;
 293 }
 294
 295 /* Get number of physical egress port */
 296 static inline int mvpp2_egress_port(struct mvpp2_port *port)
 297 {
 298         return MVPP2_MAX_TCONT + port->id;
 299 }
 300
 301 /* Get number of physical TXQ */
 302 static inline int mvpp2_txq_phys(int port, int txq)
 303 {
 304         return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
 305 }
 306
 307 static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool)
 308 {
 309         if (likely(pool->frag_size <= PAGE_SIZE))
 310                 return netdev_alloc_frag(pool->frag_size);
 311         else
 312                 return kmalloc(pool->frag_size, GFP_ATOMIC);
 313 }
 314
 315 static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool, void *data)
 316 {
 317         if (likely(pool->frag_size <= PAGE_SIZE))
 318                 skb_free_frag(data);
 319         else
 320                 kfree(data);
 321 }
 322
 323 /* Buffer Manager configuration routines */
 324
 325 /* Create pool */
 326 static int mvpp2_bm_pool_create(struct platform_device *pdev,
 327                                 struct mvpp2 *priv,
 328                                 struct mvpp2_bm_pool *bm_pool, int size)
 329 {
 330         u32 val;
 331
 332         /* Number of buffer pointers must be a multiple of 16, as per
 333          * hardware constraints
 334          */
 335         if (!IS_ALIGNED(size, 16))
 336                 return -EINVAL;
 337
 338         /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 needs 16
 339          * bytes per buffer pointer
 340          */
 341         if (priv->hw_version == MVPP21)
 342                 bm_pool->size_bytes = 2 * sizeof(u32) * size;
 343         else
 344                 bm_pool->size_bytes = 2 * sizeof(u64) * size;
 345
 346         bm_pool->virt_addr = dma_alloc_coherent(&pdev->dev, bm_pool->size_bytes,
 347                                                 &bm_pool->dma_addr,
 348                                                 GFP_KERNEL);
 349         if (!bm_pool->virt_addr)
 350                 return -ENOMEM;
 351
 352         if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
 353                         MVPP2_BM_POOL_PTR_ALIGN)) {
 354                 dma_free_coherent(&pdev->dev, bm_pool->size_bytes,
 355                                   bm_pool->virt_addr, bm_pool->dma_addr);
 356                 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
 357                         bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
 358                 return -ENOMEM;
 359         }
 360
 361         mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
 362                     lower_32_bits(bm_pool->dma_addr));
 363         mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
 364
 365         val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
 366         val |= MVPP2_BM_START_MASK;
 367         mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
 368
 369         bm_pool->size = size;
 370         bm_pool->pkt_size = 0;
 371         bm_pool->buf_num = 0;
 372
 373         return 0;
 374 }
 375
 376 /* Set pool buffer size */
 377 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
 378                                       struct mvpp2_bm_pool *bm_pool,
 379                                       int buf_size)
 380 {
 381         u32 val;
 382
 383         bm_pool->buf_size = buf_size;
 384
 385         val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
 386         mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
 387 }
 388
 389 static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv,
 390                                     struct mvpp2_bm_pool *bm_pool,
 391                                     dma_addr_t *dma_addr,
 392                                     phys_addr_t *phys_addr)
 393 {
 394         unsigned int thread = mvpp2_cpu_to_thread(priv, get_cpu());
 395
 396         *dma_addr = mvpp2_thread_read(priv, thread,
 397                                       MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
 398         *phys_addr = mvpp2_thread_read(priv, thread, MVPP2_BM_VIRT_ALLOC_REG);
 399
 400         if (priv->hw_version == MVPP22) {
 401                 u32 val;
 402                 u32 dma_addr_highbits, phys_addr_highbits;
 403
 404                 val = mvpp2_thread_read(priv, thread, MVPP22_BM_ADDR_HIGH_ALLOC);
 405                 dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK);
 406                 phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >>
 407                         MVPP22_BM_ADDR_HIGH_VIRT_SHIFT;
 408
 409                 if (sizeof(dma_addr_t) == 8)
 410                         *dma_addr |= (u64)dma_addr_highbits << 32;
 411
 412                 if (sizeof(phys_addr_t) == 8)
 413                         *phys_addr |= (u64)phys_addr_highbits << 32;
 414         }
 415
 416         put_cpu();
 417 }
 418
 419 /* Free all buffers from the pool */
 420 static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv,
 421                                struct mvpp2_bm_pool *bm_pool, int buf_num)
 422 {
 423         int i;
 424
 425         if (buf_num > bm_pool->buf_num) {
 426                 WARN(1, "Pool does not have so many bufs pool(%d) bufs(%d)\n",
 427                      bm_pool->id, buf_num);
 428                 buf_num = bm_pool->buf_num;
 429         }
 430
 431         for (i = 0; i < buf_num; i++) {
 432                 dma_addr_t buf_dma_addr;
 433                 phys_addr_t buf_phys_addr;
 434                 void *data;
 435
 436                 mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool,
 437                                         &buf_dma_addr, &buf_phys_addr);
 438
 439                 dma_unmap_single(dev, buf_dma_addr,
 440                                  bm_pool->buf_size, DMA_FROM_DEVICE);
 441
 442                 data = (void *)phys_to_virt(buf_phys_addr);
 443                 if (!data)
 444                         break;
 445
 446                 mvpp2_frag_free(bm_pool, data);
 447         }
 448
 449         /* Update BM driver with number of buffers removed from pool */
 450         bm_pool->buf_num -= i;
 451 }
 452
 453 /* Check number of buffers in BM pool */
 454 static int mvpp2_check_hw_buf_num(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool)
 455 {
 456         int buf_num = 0;
 457
 458         buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) &
 459                                     MVPP22_BM_POOL_PTRS_NUM_MASK;
 460         buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) &
 461                                     MVPP2_BM_BPPI_PTR_NUM_MASK;
 462
 463         /* HW has one buffer ready which is not reflected in the counters */
 464         if (buf_num)
 465                 buf_num += 1;
 466
 467         return buf_num;
 468 }
 469
 470 /* Cleanup pool */
 471 static int mvpp2_bm_pool_destroy(struct platform_device *pdev,
 472                                  struct mvpp2 *priv,
 473                                  struct mvpp2_bm_pool *bm_pool)
 474 {
 475         int buf_num;
 476         u32 val;
 477
 478         buf_num = mvpp2_check_hw_buf_num(priv, bm_pool);
 479         mvpp2_bm_bufs_free(&pdev->dev, priv, bm_pool, buf_num);
 480
 481         /* Check buffer counters after free */
 482         buf_num = mvpp2_check_hw_buf_num(priv, bm_pool);
 483         if (buf_num) {
 484                 WARN(1, "cannot free all buffers in pool %d, buf_num left %d\n",
 485                      bm_pool->id, bm_pool->buf_num);
 486                 return 0;
 487         }
 488
 489         val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
 490         val |= MVPP2_BM_STOP_MASK;
 491         mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
 492
 493         dma_free_coherent(&pdev->dev, bm_pool->size_bytes,
 494                           bm_pool->virt_addr,
 495                           bm_pool->dma_addr);
 496         return 0;
 497 }
 498
 499 static int mvpp2_bm_pools_init(struct platform_device *pdev,
 500                                struct mvpp2 *priv)
 501 {
 502         int i, err, size;
 503         struct mvpp2_bm_pool *bm_pool;
 504
 505         /* Create all pools with maximum size */
 506         size = MVPP2_BM_POOL_SIZE_MAX;
 507         for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
 508                 bm_pool = &priv->bm_pools[i];
 509                 bm_pool->id = i;
 510                 err = mvpp2_bm_pool_create(pdev, priv, bm_pool, size);
 511                 if (err)
 512                         goto err_unroll_pools;
 513                 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
 514         }
 515         return 0;
 516
 517 err_unroll_pools:
 518         dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);
 519         for (i = i - 1; i >= 0; i--)
 520                 mvpp2_bm_pool_destroy(pdev, priv, &priv->bm_pools[i]);
 521         return err;
 522 }
 523
 524 static int mvpp2_bm_init(struct platform_device *pdev, struct mvpp2 *priv)
 525 {
 526         int i, err;
 527
 528         for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
 529                 /* Mask BM all interrupts */
 530                 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
 531                 /* Clear BM cause register */
 532                 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
 533         }
 534
 535         /* Allocate and initialize BM pools */
 536         priv->bm_pools = devm_kcalloc(&pdev->dev, MVPP2_BM_POOLS_NUM,
 537                                       sizeof(*priv->bm_pools), GFP_KERNEL);
 538         if (!priv->bm_pools)
 539                 return -ENOMEM;
 540
 541         err = mvpp2_bm_pools_init(pdev, priv);
 542         if (err < 0)
 543                 return err;
 544         return 0;
 545 }
 546
 547 static void mvpp2_setup_bm_pool(void)
 548 {
 549         /* Short pool */
 550         mvpp2_pools[MVPP2_BM_SHORT].buf_num  = MVPP2_BM_SHORT_BUF_NUM;
 551         mvpp2_pools[MVPP2_BM_SHORT].pkt_size = MVPP2_BM_SHORT_PKT_SIZE;
 552
 553         /* Long pool */
 554         mvpp2_pools[MVPP2_BM_LONG].buf_num  = MVPP2_BM_LONG_BUF_NUM;
 555         mvpp2_pools[MVPP2_BM_LONG].pkt_size = MVPP2_BM_LONG_PKT_SIZE;
 556
 557         /* Jumbo pool */
 558         mvpp2_pools[MVPP2_BM_JUMBO].buf_num  = MVPP2_BM_JUMBO_BUF_NUM;
 559         mvpp2_pools[MVPP2_BM_JUMBO].pkt_size = MVPP2_BM_JUMBO_PKT_SIZE;
 560 }
 561
 562 /* Attach long pool to rxq */
 563 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
 564                                     int lrxq, int long_pool)
 565 {
 566         u32 val, mask;
 567         int prxq;
 568
 569         /* Get queue physical ID */
 570         prxq = port->rxqs[lrxq]->id;
 571
 572         if (port->priv->hw_version == MVPP21)
 573                 mask = MVPP21_RXQ_POOL_LONG_MASK;
 574         else
 575                 mask = MVPP22_RXQ_POOL_LONG_MASK;
 576
 577         val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
 578         val &= ~mask;
 579         val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
 580         mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
 581 }
 582
 583 /* Attach short pool to rxq */
 584 static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port,
 585                                      int lrxq, int short_pool)
 586 {
 587         u32 val, mask;
 588         int prxq;
 589
 590         /* Get queue physical ID */
 591         prxq = port->rxqs[lrxq]->id;
 592
 593         if (port->priv->hw_version == MVPP21)
 594                 mask = MVPP21_RXQ_POOL_SHORT_MASK;
 595         else
 596                 mask = MVPP22_RXQ_POOL_SHORT_MASK;
 597
 598         val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
 599         val &= ~mask;
 600         val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask;
 601         mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
 602 }
 603
 604 static void *mvpp2_buf_alloc(struct mvpp2_port *port,
 605                              struct mvpp2_bm_pool *bm_pool,
 606                              dma_addr_t *buf_dma_addr,
 607                              phys_addr_t *buf_phys_addr,
 608                              gfp_t gfp_mask)
 609 {
 610         dma_addr_t dma_addr;
 611         void *data;
 612
 613         data = mvpp2_frag_alloc(bm_pool);
 614         if (!data)
 615                 return NULL;
 616
 617         dma_addr = dma_map_single(port->dev->dev.parent, data,
 618                                   MVPP2_RX_BUF_SIZE(bm_pool->pkt_size),
 619                                   DMA_FROM_DEVICE);
 620         if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) {
 621                 mvpp2_frag_free(bm_pool, data);
 622                 return NULL;
 623         }
 624         *buf_dma_addr = dma_addr;
 625         *buf_phys_addr = virt_to_phys(data);
 626
 627         return data;
 628 }
 629
 630 /* Release buffer to BM */
 631 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
 632                                      dma_addr_t buf_dma_addr,
 633                                      phys_addr_t buf_phys_addr)
 634 {
 635         unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
 636         unsigned long flags = 0;
 637
 638         if (test_bit(thread, &port->priv->lock_map))
 639                 spin_lock_irqsave(&port->bm_lock[thread], flags);
 640
 641         if (port->priv->hw_version == MVPP22) {
 642                 u32 val = 0;
 643
 644                 if (sizeof(dma_addr_t) == 8)
 645                         val |= upper_32_bits(buf_dma_addr) &
 646                                 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
 647
 648                 if (sizeof(phys_addr_t) == 8)
 649                         val |= (upper_32_bits(buf_phys_addr)
 650                                 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
 651                                 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
 652
 653                 mvpp2_thread_write_relaxed(port->priv, thread,
 654                                            MVPP22_BM_ADDR_HIGH_RLS_REG, val);
 655         }
 656
 657         /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
 658          * returned in the "cookie" field of the RX
 659          * descriptor. Instead of storing the virtual address, we
 660          * store the physical address
 661          */
 662         mvpp2_thread_write_relaxed(port->priv, thread,
 663                                    MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
 664         mvpp2_thread_write_relaxed(port->priv, thread,
 665                                    MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
 666
 667         if (test_bit(thread, &port->priv->lock_map))
 668                 spin_unlock_irqrestore(&port->bm_lock[thread], flags);
 669
 670         put_cpu();
 671 }
 672
 673 /* Allocate buffers for the pool */
 674 static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
 675                              struct mvpp2_bm_pool *bm_pool, int buf_num)
 676 {
 677         int i, buf_size, total_size;
 678         dma_addr_t dma_addr;
 679         phys_addr_t phys_addr;
 680         void *buf;
 681
 682         buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size);
 683         total_size = MVPP2_RX_TOTAL_SIZE(buf_size);
 684
 685         if (buf_num < 0 ||
 686             (buf_num + bm_pool->buf_num > bm_pool->size)) {
 687                 netdev_err(port->dev,
 688                            "cannot allocate %d buffers for pool %d\n",
 689                            buf_num, bm_pool->id);
 690                 return 0;
 691         }
 692
 693         for (i = 0; i < buf_num; i++) {
 694                 buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr,
 695                                       &phys_addr, GFP_KERNEL);
 696                 if (!buf)
 697                         break;
 698
 699                 mvpp2_bm_pool_put(port, bm_pool->id, dma_addr,
 700                                   phys_addr);
 701         }
 702
 703         /* Update BM driver with number of buffers added to pool */
 704         bm_pool->buf_num += i;
 705
 706         netdev_dbg(port->dev,
 707                    "pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n",
 708                    bm_pool->id, bm_pool->pkt_size, buf_size, total_size);
 709
 710         netdev_dbg(port->dev,
 711                    "pool %d: %d of %d buffers added\n",
 712                    bm_pool->id, i, buf_num);
 713         return i;
 714 }
 715
 716 /* Notify the driver that BM pool is being used as specific type and return the
 717  * pool pointer on success
 718  */
 719 static struct mvpp2_bm_pool *
 720 mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size)
 721 {
 722         struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
 723         int num;
 724
 725         if (pool >= MVPP2_BM_POOLS_NUM) {
 726                 netdev_err(port->dev, "Invalid pool %d\n", pool);
 727                 return NULL;
 728         }
 729
 730         /* Allocate buffers in case BM pool is used as long pool, but packet
 731          * size doesn't match MTU or BM pool hasn't being used yet
 732          */
 733         if (new_pool->pkt_size == 0) {
 734                 int pkts_num;
 735
 736                 /* Set default buffer number or free all the buffers in case
 737                  * the pool is not empty
 738                  */
 739                 pkts_num = new_pool->buf_num;
 740                 if (pkts_num == 0)
 741                         pkts_num = mvpp2_pools[pool].buf_num;
 742                 else
 743                         mvpp2_bm_bufs_free(port->dev->dev.parent,
 744                                            port->priv, new_pool, pkts_num);
 745
 746                 new_pool->pkt_size = pkt_size;
 747                 new_pool->frag_size =
 748                         SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) +
 749                         MVPP2_SKB_SHINFO_SIZE;
 750
 751                 /* Allocate buffers for this pool */
 752                 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
 753                 if (num != pkts_num) {
 754                         WARN(1, "pool %d: %d of %d allocated\n",
 755                              new_pool->id, num, pkts_num);
 756                         return NULL;
 757                 }
 758         }
 759
 760         mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
 761                                   MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
 762
 763         return new_pool;
 764 }
 765
 766 /* Initialize pools for swf */
 767 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
 768 {
 769         int rxq;
 770         enum mvpp2_bm_pool_log_num long_log_pool, short_log_pool;
 771
 772         /* If port pkt_size is higher than 1518B:
 773          * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool
 774          * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool
 775          */
 776         if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) {
 777                 long_log_pool = MVPP2_BM_JUMBO;
 778                 short_log_pool = MVPP2_BM_LONG;
 779         } else {
 780                 long_log_pool = MVPP2_BM_LONG;
 781                 short_log_pool = MVPP2_BM_SHORT;
 782         }
 783
 784         if (!port->pool_long) {
 785                 port->pool_long =
 786                         mvpp2_bm_pool_use(port, long_log_pool,
 787                                           mvpp2_pools[long_log_pool].pkt_size);
 788                 if (!port->pool_long)
 789                         return -ENOMEM;
 790
 791                 port->pool_long->port_map |= BIT(port->id);
 792
 793                 for (rxq = 0; rxq < port->nrxqs; rxq++)
 794                         mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
 795         }
 796
 797         if (!port->pool_short) {
 798                 port->pool_short =
 799                         mvpp2_bm_pool_use(port, short_log_pool,
 800                                           mvpp2_pools[short_log_pool].pkt_size);
 801                 if (!port->pool_short)
 802                         return -ENOMEM;
 803
 804                 port->pool_short->port_map |= BIT(port->id);
 805
 806                 for (rxq = 0; rxq < port->nrxqs; rxq++)
 807                         mvpp2_rxq_short_pool_set(port, rxq,
 808                                                  port->pool_short->id);
 809         }
 810
 811         return 0;
 812 }
 813
 814 static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu)
 815 {
 816         struct mvpp2_port *port = netdev_priv(dev);
 817         enum mvpp2_bm_pool_log_num new_long_pool;
 818         int pkt_size = MVPP2_RX_PKT_SIZE(mtu);
 819
 820         /* If port MTU is higher than 1518B:
 821          * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool
 822          * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool
 823          */
 824         if (pkt_size > MVPP2_BM_LONG_PKT_SIZE)
 825                 new_long_pool = MVPP2_BM_JUMBO;
 826         else
 827                 new_long_pool = MVPP2_BM_LONG;
 828
 829         if (new_long_pool != port->pool_long->id) {
 830                 /* Remove port from old short & long pool */
 831                 port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id,
 832                                                     port->pool_long->pkt_size);
 833                 port->pool_long->port_map &= ~BIT(port->id);
 834                 port->pool_long = NULL;
 835
 836                 port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id,
 837                                                      port->pool_short->pkt_size);
 838                 port->pool_short->port_map &= ~BIT(port->id);
 839                 port->pool_short = NULL;
 840
 841                 port->pkt_size =  pkt_size;
 842
 843                 /* Add port to new short & long pool */
 844                 mvpp2_swf_bm_pool_init(port);
 845
 846                 /* Update L4 checksum when jumbo enable/disable on port */
 847                 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) {
 848                         dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
 849                         dev->hw_features &= ~(NETIF_F_IP_CSUM |
 850                                               NETIF_F_IPV6_CSUM);
 851                 } else {
 852                         dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
 853                         dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
 854                 }
 855         }
 856
 857         dev->mtu = mtu;
 858         dev->wanted_features = dev->features;
 859
 860         netdev_update_features(dev);
 861         return 0;
 862 }
 863
 864 static inline void mvpp2_interrupts_enable(struct mvpp2_port *port)
 865 {
 866         int i, sw_thread_mask = 0;
 867
 868         for (i = 0; i < port->nqvecs; i++)
 869                 sw_thread_mask |= port->qvecs[i].sw_thread_mask;
 870
 871         mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
 872                     MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask));
 873 }
 874
 875 static inline void mvpp2_interrupts_disable(struct mvpp2_port *port)
 876 {
 877         int i, sw_thread_mask = 0;
 878
 879         for (i = 0; i < port->nqvecs; i++)
 880                 sw_thread_mask |= port->qvecs[i].sw_thread_mask;
 881
 882         mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
 883                     MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask));
 884 }
 885
 886 static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector *qvec)
 887 {
 888         struct mvpp2_port *port = qvec->port;
 889
 890         mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
 891                     MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask));
 892 }
 893
 894 static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec)
 895 {
 896         struct mvpp2_port *port = qvec->port;
 897
 898         mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
 899                     MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask));
 900 }
 901
 902 /* Mask the current thread's Rx/Tx interrupts
 903  * Called by on_each_cpu(), guaranteed to run with migration disabled,
 904  * using smp_processor_id() is OK.
 905  */
 906 static void mvpp2_interrupts_mask(void *arg)
 907 {
 908         struct mvpp2_port *port = arg;
 909
 910         /* If the thread isn't used, don't do anything */
 911         if (smp_processor_id() > port->priv->nthreads)
 912                 return;
 913
 914         mvpp2_thread_write(port->priv,
 915                            mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
 916                            MVPP2_ISR_RX_TX_MASK_REG(port->id), 0);
 917 }
 918
 919 /* Unmask the current thread's Rx/Tx interrupts.
 920  * Called by on_each_cpu(), guaranteed to run with migration disabled,
 921  * using smp_processor_id() is OK.
 922  */
 923 static void mvpp2_interrupts_unmask(void *arg)
 924 {
 925         struct mvpp2_port *port = arg;
 926         u32 val;
 927
 928         /* If the thread isn't used, don't do anything */
 929         if (smp_processor_id() > port->priv->nthreads)
 930                 return;
 931
 932         val = MVPP2_CAUSE_MISC_SUM_MASK |
 933                 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
 934         if (port->has_tx_irqs)
 935                 val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
 936
 937         mvpp2_thread_write(port->priv,
 938                            mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
 939                            MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
 940 }
 941
 942 static void
 943 mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask)
 944 {
 945         u32 val;
 946         int i;
 947
 948         if (port->priv->hw_version != MVPP22)
 949                 return;
 950
 951         if (mask)
 952                 val = 0;
 953         else
 954                 val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(MVPP22);
 955
 956         for (i = 0; i < port->nqvecs; i++) {
 957                 struct mvpp2_queue_vector *v = port->qvecs + i;
 958
 959                 if (v->type != MVPP2_QUEUE_VECTOR_SHARED)
 960                         continue;
 961
 962                 mvpp2_thread_write(port->priv, v->sw_thread_id,
 963                                    MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
 964         }
 965 }
 966
 967 /* Port configuration routines */
 968
 969 static void mvpp22_gop_init_rgmii(struct mvpp2_port *port)
 970 {
 971         struct mvpp2 *priv = port->priv;
 972         u32 val;
 973
 974         regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
 975         val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT;
 976         regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
 977
 978         regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
 979         if (port->gop_id == 2)
 980                 val |= GENCONF_CTRL0_PORT0_RGMII | GENCONF_CTRL0_PORT1_RGMII;
 981         else if (port->gop_id == 3)
 982                 val |= GENCONF_CTRL0_PORT1_RGMII_MII;
 983         regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
 984 }
 985
 986 static void mvpp22_gop_init_sgmii(struct mvpp2_port *port)
 987 {
 988         struct mvpp2 *priv = port->priv;
 989         u32 val;
 990
 991         regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
 992         val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT |
 993                GENCONF_PORT_CTRL0_RX_DATA_SAMPLE;
 994         regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
 995
 996         if (port->gop_id > 1) {
 997                 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
 998                 if (port->gop_id == 2)
 999                         val &= ~GENCONF_CTRL0_PORT0_RGMII;
1000                 else if (port->gop_id == 3)
1001                         val &= ~GENCONF_CTRL0_PORT1_RGMII_MII;
1002                 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
1003         }
1004 }
1005
1006 static void mvpp22_gop_init_10gkr(struct mvpp2_port *port)
1007 {
1008         struct mvpp2 *priv = port->priv;
1009         void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
1010         void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
1011         u32 val;
1012
1013         /* XPCS */
1014         val = readl(xpcs + MVPP22_XPCS_CFG0);
1015         val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) |
1016                  MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3));
1017         val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2);
1018         writel(val, xpcs + MVPP22_XPCS_CFG0);
1019
1020         /* MPCS */
1021         val = readl(mpcs + MVPP22_MPCS_CTRL);
1022         val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN;
1023         writel(val, mpcs + MVPP22_MPCS_CTRL);
1024
1025         val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
1026         val &= ~(MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7) | MAC_CLK_RESET_MAC |
1027                  MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX);
1028         val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1);
1029         writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
1030
1031         val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET;
1032         val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX;
1033         writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
1034 }
1035
1036 static int mvpp22_gop_init(struct mvpp2_port *port)
1037 {
1038         struct mvpp2 *priv = port->priv;
1039         u32 val;
1040
1041         if (!priv->sysctrl_base)
1042                 return 0;
1043
1044         switch (port->phy_interface) {
1045         case PHY_INTERFACE_MODE_RGMII:
1046         case PHY_INTERFACE_MODE_RGMII_ID:
1047         case PHY_INTERFACE_MODE_RGMII_RXID:
1048         case PHY_INTERFACE_MODE_RGMII_TXID:
1049                 if (port->gop_id == 0)
1050                         goto invalid_conf;
1051                 mvpp22_gop_init_rgmii(port);
1052                 break;
1053         case PHY_INTERFACE_MODE_SGMII:
1054         case PHY_INTERFACE_MODE_1000BASEX:
1055         case PHY_INTERFACE_MODE_2500BASEX:
1056                 mvpp22_gop_init_sgmii(port);
1057                 break;
1058         case PHY_INTERFACE_MODE_10GKR:
1059                 if (port->gop_id != 0)
1060                         goto invalid_conf;
1061                 mvpp22_gop_init_10gkr(port);
1062                 break;
1063         default:
1064                 goto unsupported_conf;
1065         }
1066
1067         regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val);
1068         val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) |
1069                GENCONF_PORT_CTRL1_EN(port->gop_id);
1070         regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val);
1071
1072         regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1073         val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR;
1074         regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1075
1076         regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val);
1077         val |= GENCONF_SOFT_RESET1_GOP;
1078         regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val);
1079
1080 unsupported_conf:
1081         return 0;
1082
1083 invalid_conf:
1084         netdev_err(port->dev, "Invalid port configuration\n");
1085         return -EINVAL;
1086 }
1087
1088 static void mvpp22_gop_unmask_irq(struct mvpp2_port *port)
1089 {
1090         u32 val;
1091
1092         if (phy_interface_mode_is_rgmii(port->phy_interface) ||
1093             port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
1094             port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
1095             port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
1096                 /* Enable the GMAC link status irq for this port */
1097                 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
1098                 val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
1099                 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
1100         }
1101
1102         if (port->gop_id == 0) {
1103                 /* Enable the XLG/GIG irqs for this port */
1104                 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
1105                 if (port->phy_interface == PHY_INTERFACE_MODE_10GKR)
1106                         val |= MVPP22_XLG_EXT_INT_MASK_XLG;
1107                 else
1108                         val |= MVPP22_XLG_EXT_INT_MASK_GIG;
1109                 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
1110         }
1111 }
1112
1113 static void mvpp22_gop_mask_irq(struct mvpp2_port *port)
1114 {
1115         u32 val;
1116
1117         if (port->gop_id == 0) {
1118                 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
1119                 val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG |
1120                          MVPP22_XLG_EXT_INT_MASK_GIG);
1121                 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
1122         }
1123
1124         if (phy_interface_mode_is_rgmii(port->phy_interface) ||
1125             port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
1126             port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
1127             port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
1128                 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
1129                 val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
1130                 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
1131         }
1132 }
1133
1134 static void mvpp22_gop_setup_irq(struct mvpp2_port *port)
1135 {
1136         u32 val;
1137
1138         if (phy_interface_mode_is_rgmii(port->phy_interface) ||
1139             port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
1140             port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
1141             port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
1142                 val = readl(port->base + MVPP22_GMAC_INT_MASK);
1143                 val |= MVPP22_GMAC_INT_MASK_LINK_STAT;
1144                 writel(val, port->base + MVPP22_GMAC_INT_MASK);
1145         }
1146
1147         if (port->gop_id == 0) {
1148                 val = readl(port->base + MVPP22_XLG_INT_MASK);
1149                 val |= MVPP22_XLG_INT_MASK_LINK;
1150                 writel(val, port->base + MVPP22_XLG_INT_MASK);
1151         }
1152
1153         mvpp22_gop_unmask_irq(port);
1154 }
1155
1156 /* Sets the PHY mode of the COMPHY (which configures the serdes lanes).
1157  *
1158  * The PHY mode used by the PPv2 driver comes from the network subsystem, while
1159  * the one given to the COMPHY comes from the generic PHY subsystem. Hence they
1160  * differ.
1161  *
1162  * The COMPHY configures the serdes lanes regardless of the actual use of the
1163  * lanes by the physical layer. This is why configurations like
1164  * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid.
1165  */
1166 static int mvpp22_comphy_init(struct mvpp2_port *port)
1167 {
1168         enum phy_mode mode;
1169         int ret;
1170
1171         if (!port->comphy)
1172                 return 0;
1173
1174         switch (port->phy_interface) {
1175         case PHY_INTERFACE_MODE_SGMII:
1176         case PHY_INTERFACE_MODE_1000BASEX:
1177                 mode = PHY_MODE_SGMII;
1178                 break;
1179         case PHY_INTERFACE_MODE_2500BASEX:
1180                 mode = PHY_MODE_2500SGMII;
1181                 break;
1182         case PHY_INTERFACE_MODE_10GKR:
1183                 mode = PHY_MODE_10GKR;
1184                 break;
1185         default:
1186                 return -EINVAL;
1187         }
1188
1189         ret = phy_set_mode(port->comphy, mode);
1190         if (ret)
1191                 return ret;
1192
1193         return phy_power_on(port->comphy);
1194 }
1195
1196 static void mvpp2_port_enable(struct mvpp2_port *port)
1197 {
1198         u32 val;
1199
1200         /* Only GOP port 0 has an XLG MAC */
1201         if (port->gop_id == 0 &&
1202             (port->phy_interface == PHY_INTERFACE_MODE_XAUI ||
1203              port->phy_interface == PHY_INTERFACE_MODE_10GKR)) {
1204                 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
1205                 val |= MVPP22_XLG_CTRL0_PORT_EN |
1206                        MVPP22_XLG_CTRL0_MAC_RESET_DIS;
1207                 val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS;
1208                 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1209         } else {
1210                 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1211                 val |= MVPP2_GMAC_PORT_EN_MASK;
1212                 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
1213                 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1214         }
1215 }
1216
1217 static void mvpp2_port_disable(struct mvpp2_port *port)
1218 {
1219         u32 val;
1220
1221         /* Only GOP port 0 has an XLG MAC */
1222         if (port->gop_id == 0 &&
1223             (port->phy_interface == PHY_INTERFACE_MODE_XAUI ||
1224              port->phy_interface == PHY_INTERFACE_MODE_10GKR)) {
1225                 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
1226                 val &= ~MVPP22_XLG_CTRL0_PORT_EN;
1227                 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1228
1229                 /* Disable & reset should be done separately */
1230                 val &= ~MVPP22_XLG_CTRL0_MAC_RESET_DIS;
1231                 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1232         } else {
1233                 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1234                 val &= ~(MVPP2_GMAC_PORT_EN_MASK);
1235                 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1236         }
1237 }
1238
1239 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
1240 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
1241 {
1242         u32 val;
1243
1244         val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
1245                     ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
1246         writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
1247 }
1248
1249 /* Configure loopback port */
1250 static void mvpp2_port_loopback_set(struct mvpp2_port *port,
1251                                     const struct phylink_link_state *state)
1252 {
1253         u32 val;
1254
1255         val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
1256
1257         if (state->speed == 1000)
1258                 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
1259         else
1260                 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
1261
1262         if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
1263             port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
1264             port->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
1265                 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
1266         else
1267                 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
1268
1269         writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
1270 }
1271
1272 struct mvpp2_ethtool_counter {
1273         unsigned int offset;
1274         const char string[ETH_GSTRING_LEN];
1275         bool reg_is_64b;
1276 };
1277
1278 static u64 mvpp2_read_count(struct mvpp2_port *port,
1279                             const struct mvpp2_ethtool_counter *counter)
1280 {
1281         u64 val;
1282
1283         val = readl(port->stats_base + counter->offset);
1284         if (counter->reg_is_64b)
1285                 val += (u64)readl(port->stats_base + counter->offset + 4) << 32;
1286
1287         return val;
1288 }
1289
1290 /* Due to the fact that software statistics and hardware statistics are, by
1291  * design, incremented at different moments in the chain of packet processing,
1292  * it is very likely that incoming packets could have been dropped after being
1293  * counted by hardware but before reaching software statistics (most probably
1294  * multicast packets), and in the oppposite way, during transmission, FCS bytes
1295  * are added in between as well as TSO skb will be split and header bytes added.
1296  * Hence, statistics gathered from userspace with ifconfig (software) and
1297  * ethtool (hardware) cannot be compared.
1298  */
1299 static const struct mvpp2_ethtool_counter mvpp2_ethtool_regs[] = {
1300         { MVPP2_MIB_GOOD_OCTETS_RCVD, "good_octets_received", true },
1301         { MVPP2_MIB_BAD_OCTETS_RCVD, "bad_octets_received" },
1302         { MVPP2_MIB_CRC_ERRORS_SENT, "crc_errors_sent" },
1303         { MVPP2_MIB_UNICAST_FRAMES_RCVD, "unicast_frames_received" },
1304         { MVPP2_MIB_BROADCAST_FRAMES_RCVD, "broadcast_frames_received" },
1305         { MVPP2_MIB_MULTICAST_FRAMES_RCVD, "multicast_frames_received" },
1306         { MVPP2_MIB_FRAMES_64_OCTETS, "frames_64_octets" },
1307         { MVPP2_MIB_FRAMES_65_TO_127_OCTETS, "frames_65_to_127_octet" },
1308         { MVPP2_MIB_FRAMES_128_TO_255_OCTETS, "frames_128_to_255_octet" },
1309         { MVPP2_MIB_FRAMES_256_TO_511_OCTETS, "frames_256_to_511_octet" },
1310         { MVPP2_MIB_FRAMES_512_TO_1023_OCTETS, "frames_512_to_1023_octet" },
1311         { MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS, "frames_1024_to_max_octet" },
1312         { MVPP2_MIB_GOOD_OCTETS_SENT, "good_octets_sent", true },
1313         { MVPP2_MIB_UNICAST_FRAMES_SENT, "unicast_frames_sent" },
1314         { MVPP2_MIB_MULTICAST_FRAMES_SENT, "multicast_frames_sent" },
1315         { MVPP2_MIB_BROADCAST_FRAMES_SENT, "broadcast_frames_sent" },
1316         { MVPP2_MIB_FC_SENT, "fc_sent" },
1317         { MVPP2_MIB_FC_RCVD, "fc_received" },
1318         { MVPP2_MIB_RX_FIFO_OVERRUN, "rx_fifo_overrun" },
1319         { MVPP2_MIB_UNDERSIZE_RCVD, "undersize_received" },
1320         { MVPP2_MIB_FRAGMENTS_RCVD, "fragments_received" },
1321         { MVPP2_MIB_OVERSIZE_RCVD, "oversize_received" },
1322         { MVPP2_MIB_JABBER_RCVD, "jabber_received" },
1323         { MVPP2_MIB_MAC_RCV_ERROR, "mac_receive_error" },
1324         { MVPP2_MIB_BAD_CRC_EVENT, "bad_crc_event" },
1325         { MVPP2_MIB_COLLISION, "collision" },
1326         { MVPP2_MIB_LATE_COLLISION, "late_collision" },
1327 };
1328
1329 static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset,
1330                                       u8 *data)
1331 {
1332         if (sset == ETH_SS_STATS) {
1333                 int i;
1334
1335                 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++)
1336                         memcpy(data + i * ETH_GSTRING_LEN,
1337                                &mvpp2_ethtool_regs[i].string, ETH_GSTRING_LEN);
1338         }
1339 }
1340
1341 static void mvpp2_gather_hw_statistics(struct work_struct *work)
1342 {
1343         struct delayed_work *del_work = to_delayed_work(work);
1344         struct mvpp2_port *port = container_of(del_work, struct mvpp2_port,
1345                                                stats_work);
1346         u64 *pstats;
1347         int i;
1348
1349         mutex_lock(&port->gather_stats_lock);
1350
1351         pstats = port->ethtool_stats;
1352         for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++)
1353                 *pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_regs[i]);
1354
1355         /* No need to read again the counters right after this function if it
1356          * was called asynchronously by the user (ie. use of ethtool).
1357          */
1358         cancel_delayed_work(&port->stats_work);
1359         queue_delayed_work(port->priv->stats_queue, &port->stats_work,
1360                            MVPP2_MIB_COUNTERS_STATS_DELAY);
1361
1362         mutex_unlock(&port->gather_stats_lock);
1363 }
1364
1365 static void mvpp2_ethtool_get_stats(struct net_device *dev,
1366                                     struct ethtool_stats *stats, u64 *data)
1367 {
1368         struct mvpp2_port *port = netdev_priv(dev);
1369
1370         /* Update statistics for the given port, then take the lock to avoid
1371          * concurrent accesses on the ethtool_stats structure during its copy.
1372          */
1373         mvpp2_gather_hw_statistics(&port->stats_work.work);
1374
1375         mutex_lock(&port->gather_stats_lock);
1376         memcpy(data, port->ethtool_stats,
1377                sizeof(u64) * ARRAY_SIZE(mvpp2_ethtool_regs));
1378         mutex_unlock(&port->gather_stats_lock);
1379 }
1380
1381 static int mvpp2_ethtool_get_sset_count(struct net_device *dev, int sset)
1382 {
1383         if (sset == ETH_SS_STATS)
1384                 return ARRAY_SIZE(mvpp2_ethtool_regs);
1385
1386         return -EOPNOTSUPP;
1387 }
1388
1389 static void mvpp2_port_reset(struct mvpp2_port *port)
1390 {
1391         u32 val;
1392         unsigned int i;
1393
1394         /* Read the GOP statistics to reset the hardware counters */
1395         for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++)
1396                 mvpp2_read_count(port, &mvpp2_ethtool_regs[i]);
1397
1398         val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
1399                     ~MVPP2_GMAC_PORT_RESET_MASK;
1400         writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
1401
1402         while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
1403                MVPP2_GMAC_PORT_RESET_MASK)
1404                 continue;
1405 }
1406
1407 /* Change maximum receive size of the port */
1408 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
1409 {
1410         u32 val;
1411
1412         val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1413         val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
1414         val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
1415                     MVPP2_GMAC_MAX_RX_SIZE_OFFS);
1416         writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1417 }
1418
1419 /* Change maximum receive size of the port */
1420 static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port)
1421 {
1422         u32 val;
1423
1424         val =  readl(port->base + MVPP22_XLG_CTRL1_REG);
1425         val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK;
1426         val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
1427                MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS;
1428         writel(val, port->base + MVPP22_XLG_CTRL1_REG);
1429 }
1430
1431 /* Set defaults to the MVPP2 port */
1432 static void mvpp2_defaults_set(struct mvpp2_port *port)
1433 {
1434         int tx_port_num, val, queue, ptxq, lrxq;
1435
1436         if (port->priv->hw_version == MVPP21) {
1437                 /* Update TX FIFO MIN Threshold */
1438                 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
1439                 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
1440                 /* Min. TX threshold must be less than minimal packet length */
1441                 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
1442                 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
1443         }
1444
1445         /* Disable Legacy WRR, Disable EJP, Release from reset */
1446         tx_port_num = mvpp2_egress_port(port);
1447         mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
1448                     tx_port_num);
1449         mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
1450
1451         /* Close bandwidth for all queues */
1452         for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) {
1453                 ptxq = mvpp2_txq_phys(port->id, queue);
1454                 mvpp2_write(port->priv,
1455                             MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0);
1456         }
1457
1458         /* Set refill period to 1 usec, refill tokens
1459          * and bucket size to maximum
1460          */
1461         mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG,
1462                     port->priv->tclk / USEC_PER_SEC);
1463         val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
1464         val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
1465         val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
1466         val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
1467         mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
1468         val = MVPP2_TXP_TOKEN_SIZE_MAX;
1469         mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
1470
1471         /* Set MaximumLowLatencyPacketSize value to 256 */
1472         mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
1473                     MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
1474                     MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
1475
1476         /* Enable Rx cache snoop */
1477         for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
1478                 queue = port->rxqs[lrxq]->id;
1479                 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
1480                 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
1481                            MVPP2_SNOOP_BUF_HDR_MASK;
1482                 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
1483         }
1484
1485         /* At default, mask all interrupts to all present cpus */
1486         mvpp2_interrupts_disable(port);
1487 }
1488
1489 /* Enable/disable receiving packets */
1490 static void mvpp2_ingress_enable(struct mvpp2_port *port)
1491 {
1492         u32 val;
1493         int lrxq, queue;
1494
1495         for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
1496                 queue = port->rxqs[lrxq]->id;
1497                 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
1498                 val &= ~MVPP2_RXQ_DISABLE_MASK;
1499                 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
1500         }
1501 }
1502
1503 static void mvpp2_ingress_disable(struct mvpp2_port *port)
1504 {
1505         u32 val;
1506         int lrxq, queue;
1507
1508         for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
1509                 queue = port->rxqs[lrxq]->id;
1510                 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
1511                 val |= MVPP2_RXQ_DISABLE_MASK;
1512                 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
1513         }
1514 }
1515
1516 /* Enable transmit via physical egress queue
1517  * - HW starts take descriptors from DRAM
1518  */
1519 static void mvpp2_egress_enable(struct mvpp2_port *port)
1520 {
1521         u32 qmap;
1522         int queue;
1523         int tx_port_num = mvpp2_egress_port(port);
1524
1525         /* Enable all initialized TXs. */
1526         qmap = 0;
1527         for (queue = 0; queue < port->ntxqs; queue++) {
1528                 struct mvpp2_tx_queue *txq = port->txqs[queue];
1529
1530                 if (txq->descs)
1531                         qmap |= (1 << queue);
1532         }
1533
1534         mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
1535         mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
1536 }
1537
1538 /* Disable transmit via physical egress queue
1539  * - HW doesn't take descriptors from DRAM
1540  */
1541 static void mvpp2_egress_disable(struct mvpp2_port *port)
1542 {
1543         u32 reg_data;
1544         int delay;
1545         int tx_port_num = mvpp2_egress_port(port);
1546
1547         /* Issue stop command for active channels only */
1548         mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
1549         reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
1550                     MVPP2_TXP_SCHED_ENQ_MASK;
1551         if (reg_data != 0)
1552                 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
1553                             (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
1554
1555         /* Wait for all Tx activity to terminate. */
1556         delay = 0;
1557         do {
1558                 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
1559                         netdev_warn(port->dev,
1560                                     "Tx stop timed out, status=0x%08x\n",
1561                                     reg_data);
1562                         break;
1563                 }
1564                 mdelay(1);
1565                 delay++;
1566
1567                 /* Check port TX Command register that all
1568                  * Tx queues are stopped
1569                  */
1570                 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
1571         } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
1572 }
1573
1574 /* Rx descriptors helper methods */
1575
1576 /* Get number of Rx descriptors occupied by received packets */
1577 static inline int
1578 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
1579 {
1580         u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
1581
1582         return val & MVPP2_RXQ_OCCUPIED_MASK;
1583 }
1584
1585 /* Update Rx queue status with the number of occupied and available
1586  * Rx descriptor slots.
1587  */
1588 static inline void
1589 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
1590                         int used_count, int free_count)
1591 {
1592         /* Decrement the number of used descriptors and increment count
1593          * increment the number of free descriptors.
1594          */
1595         u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
1596
1597         mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
1598 }
1599
1600 /* Get pointer to next RX descriptor to be processed by SW */
1601 static inline struct mvpp2_rx_desc *
1602 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
1603 {
1604         int rx_desc = rxq->next_desc_to_proc;
1605
1606         rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
1607         prefetch(rxq->descs + rxq->next_desc_to_proc);
1608         return rxq->descs + rx_desc;
1609 }
1610
1611 /* Set rx queue offset */
1612 static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
1613                                  int prxq, int offset)
1614 {
1615         u32 val;
1616
1617         /* Convert offset from bytes to units of 32 bytes */
1618         offset = offset >> 5;
1619
1620         val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
1621         val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
1622
1623         /* Offset is in */
1624         val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
1625                     MVPP2_RXQ_PACKET_OFFSET_MASK);
1626
1627         mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
1628 }
1629
1630 /* Tx descriptors helper methods */
1631
1632 /* Get pointer to next Tx descriptor to be processed (send) by HW */
1633 static struct mvpp2_tx_desc *
1634 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
1635 {
1636         int tx_desc = txq->next_desc_to_proc;
1637
1638         txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
1639         return txq->descs + tx_desc;
1640 }
1641
1642 /* Update HW with number of aggregated Tx descriptors to be sent
1643  *
1644  * Called only from mvpp2_tx(), so migration is disabled, using
1645  * smp_processor_id() is OK.
1646  */
1647 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
1648 {
1649         /* aggregated access - relevant TXQ number is written in TX desc */
1650         mvpp2_thread_write(port->priv,
1651                            mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
1652                            MVPP2_AGGR_TXQ_UPDATE_REG, pending);
1653 }
1654
1655 /* Check if there are enough free descriptors in aggregated txq.
1656  * If not, update the number of occupied descriptors and repeat the check.
1657  *
1658  * Called only from mvpp2_tx(), so migration is disabled, using
1659  * smp_processor_id() is OK.
1660  */
1661 static int mvpp2_aggr_desc_num_check(struct mvpp2_port *port,
1662                                      struct mvpp2_tx_queue *aggr_txq, int num)
1663 {
1664         if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) {
1665                 /* Update number of occupied aggregated Tx descriptors */
1666                 unsigned int thread =
1667                         mvpp2_cpu_to_thread(port->priv, smp_processor_id());
1668                 u32 val = mvpp2_read_relaxed(port->priv,
1669                                              MVPP2_AGGR_TXQ_STATUS_REG(thread));
1670
1671                 aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK;
1672
1673                 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE)
1674                         return -ENOMEM;
1675         }
1676         return 0;
1677 }
1678
1679 /* Reserved Tx descriptors allocation request
1680  *
1681  * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called
1682  * only by mvpp2_tx(), so migration is disabled, using
1683  * smp_processor_id() is OK.
1684  */
1685 static int mvpp2_txq_alloc_reserved_desc(struct mvpp2_port *port,
1686                                          struct mvpp2_tx_queue *txq, int num)
1687 {
1688         unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
1689         struct mvpp2 *priv = port->priv;
1690         u32 val;
1691
1692         val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num;
1693         mvpp2_thread_write_relaxed(priv, thread, MVPP2_TXQ_RSVD_REQ_REG, val);
1694
1695         val = mvpp2_thread_read_relaxed(priv, thread, MVPP2_TXQ_RSVD_RSLT_REG);
1696
1697         return val & MVPP2_TXQ_RSVD_RSLT_MASK;
1698 }
1699
1700 /* Check if there are enough reserved descriptors for transmission.
1701  * If not, request chunk of reserved descriptors and check again.
1702  */
1703 static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2_port *port,
1704                                             struct mvpp2_tx_queue *txq,
1705                                             struct mvpp2_txq_pcpu *txq_pcpu,
1706                                             int num)
1707 {
1708         int req, desc_count;
1709         unsigned int thread;
1710
1711         if (txq_pcpu->reserved_num >= num)
1712                 return 0;
1713
1714         /* Not enough descriptors reserved! Update the reserved descriptor
1715          * count and check again.
1716          */
1717
1718         desc_count = 0;
1719         /* Compute total of used descriptors */
1720         for (thread = 0; thread < port->priv->nthreads; thread++) {
1721                 struct mvpp2_txq_pcpu *txq_pcpu_aux;
1722
1723                 txq_pcpu_aux = per_cpu_ptr(txq->pcpu, thread);
1724                 desc_count += txq_pcpu_aux->count;
1725                 desc_count += txq_pcpu_aux->reserved_num;
1726         }
1727
1728         req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num);
1729         desc_count += req;
1730
1731         if (desc_count >
1732            (txq->size - (MVPP2_MAX_THREADS * MVPP2_CPU_DESC_CHUNK)))
1733                 return -ENOMEM;
1734
1735         txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(port, txq, req);
1736
1737         /* OK, the descriptor could have been updated: check again. */
1738         if (txq_pcpu->reserved_num < num)
1739                 return -ENOMEM;
1740         return 0;
1741 }
1742
1743 /* Release the last allocated Tx descriptor. Useful to handle DMA
1744  * mapping failures in the Tx path.
1745  */
1746 static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq)
1747 {
1748         if (txq->next_desc_to_proc == 0)
1749                 txq->next_desc_to_proc = txq->last_desc - 1;
1750         else
1751                 txq->next_desc_to_proc--;
1752 }
1753
1754 /* Set Tx descriptors fields relevant for CSUM calculation */
1755 static u32 mvpp2_txq_desc_csum(int l3_offs, int l3_proto,
1756                                int ip_hdr_len, int l4_proto)
1757 {
1758         u32 command;
1759
1760         /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1761          * G_L4_chk, L4_type required only for checksum calculation
1762          */
1763         command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT);
1764         command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT);
1765         command |= MVPP2_TXD_IP_CSUM_DISABLE;
1766
1767         if (l3_proto == htons(ETH_P_IP)) {
1768                 command &= ~MVPP2_TXD_IP_CSUM_DISABLE;  /* enable IPv4 csum */
1769                 command &= ~MVPP2_TXD_L3_IP6;           /* enable IPv4 */
1770         } else {
1771                 command |= MVPP2_TXD_L3_IP6;            /* enable IPv6 */
1772         }
1773
1774         if (l4_proto == IPPROTO_TCP) {
1775                 command &= ~MVPP2_TXD_L4_UDP;           /* enable TCP */
1776                 command &= ~MVPP2_TXD_L4_CSUM_FRAG;     /* generate L4 csum */
1777         } else if (l4_proto == IPPROTO_UDP) {
1778                 command |= MVPP2_TXD_L4_UDP;            /* enable UDP */
1779                 command &= ~MVPP2_TXD_L4_CSUM_FRAG;     /* generate L4 csum */
1780         } else {
1781                 command |= MVPP2_TXD_L4_CSUM_NOT;
1782         }
1783
1784         return command;
1785 }
1786
1787 /* Get number of sent descriptors and decrement counter.
1788  * The number of sent descriptors is returned.
1789  * Per-thread access
1790  *
1791  * Called only from mvpp2_txq_done(), called from mvpp2_tx()
1792  * (migration disabled) and from the TX completion tasklet (migration
1793  * disabled) so using smp_processor_id() is OK.
1794  */
1795 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
1796                                            struct mvpp2_tx_queue *txq)
1797 {
1798         u32 val;
1799
1800         /* Reading status reg resets transmitted descriptor counter */
1801         val = mvpp2_thread_read_relaxed(port->priv,
1802                                         mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
1803                                         MVPP2_TXQ_SENT_REG(txq->id));
1804
1805         return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
1806                 MVPP2_TRANSMITTED_COUNT_OFFSET;
1807 }
1808
1809 /* Called through on_each_cpu(), so runs on all CPUs, with migration
1810  * disabled, therefore using smp_processor_id() is OK.
1811  */
1812 static void mvpp2_txq_sent_counter_clear(void *arg)
1813 {
1814         struct mvpp2_port *port = arg;
1815         int queue;
1816
1817         /* If the thread isn't used, don't do anything */
1818         if (smp_processor_id() > port->priv->nthreads)
1819                 return;
1820
1821         for (queue = 0; queue < port->ntxqs; queue++) {
1822                 int id = port->txqs[queue]->id;
1823
1824                 mvpp2_thread_read(port->priv,
1825                                   mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
1826                                   MVPP2_TXQ_SENT_REG(id));
1827         }
1828 }
1829
1830 /* Set max sizes for Tx queues */
1831 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
1832 {
1833         u32     val, size, mtu;
1834         int     txq, tx_port_num;
1835
1836         mtu = port->pkt_size * 8;
1837         if (mtu > MVPP2_TXP_MTU_MAX)
1838                 mtu = MVPP2_TXP_MTU_MAX;
1839
1840         /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
1841         mtu = 3 * mtu;
1842
1843         /* Indirect access to registers */
1844         tx_port_num = mvpp2_egress_port(port);
1845         mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
1846
1847         /* Set MTU */
1848         val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
1849         val &= ~MVPP2_TXP_MTU_MAX;
1850         val |= mtu;
1851         mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
1852
1853         /* TXP token size and all TXQs token size must be larger that MTU */
1854         val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
1855         size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
1856         if (size < mtu) {
1857                 size = mtu;
1858                 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
1859                 val |= size;
1860                 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
1861         }
1862
1863         for (txq = 0; txq < port->ntxqs; txq++) {
1864                 val = mvpp2_read(port->priv,
1865                                  MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
1866                 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
1867
1868                 if (size < mtu) {
1869                         size = mtu;
1870                         val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
1871                         val |= size;
1872                         mvpp2_write(port->priv,
1873                                     MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
1874                                     val);
1875                 }
1876         }
1877 }
1878
1879 /* Set the number of packets that will be received before Rx interrupt
1880  * will be generated by HW.
1881  */
1882 static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port,
1883                                    struct mvpp2_rx_queue *rxq)
1884 {
1885         unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
1886
1887         if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK)
1888                 rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK;
1889
1890         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
1891         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_THRESH_REG,
1892                            rxq->pkts_coal);
1893
1894         put_cpu();
1895 }
1896
1897 /* For some reason in the LSP this is done on each CPU. Why ? */
1898 static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port,
1899                                    struct mvpp2_tx_queue *txq)
1900 {
1901         unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
1902         u32 val;
1903
1904         if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK)
1905                 txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK;
1906
1907         val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET);
1908         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
1909         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_THRESH_REG, val);
1910
1911         put_cpu();
1912 }
1913
1914 static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz)
1915 {
1916         u64 tmp = (u64)clk_hz * usec;
1917
1918         do_div(tmp, USEC_PER_SEC);
1919
1920         return tmp > U32_MAX ? U32_MAX : tmp;
1921 }
1922
1923 static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz)
1924 {
1925         u64 tmp = (u64)cycles * USEC_PER_SEC;
1926
1927         do_div(tmp, clk_hz);
1928
1929         return tmp > U32_MAX ? U32_MAX : tmp;
1930 }
1931
1932 /* Set the time delay in usec before Rx interrupt */
1933 static void mvpp2_rx_time_coal_set(struct mvpp2_port *port,
1934                                    struct mvpp2_rx_queue *rxq)
1935 {
1936         unsigned long freq = port->priv->tclk;
1937         u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
1938
1939         if (val > MVPP2_MAX_ISR_RX_THRESHOLD) {
1940                 rxq->time_coal =
1941                         mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq);
1942
1943                 /* re-evaluate to get actual register value */
1944                 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
1945         }
1946
1947         mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val);
1948 }
1949
1950 static void mvpp2_tx_time_coal_set(struct mvpp2_port *port)
1951 {
1952         unsigned long freq = port->priv->tclk;
1953         u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq);
1954
1955         if (val > MVPP2_MAX_ISR_TX_THRESHOLD) {
1956                 port->tx_time_coal =
1957                         mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD, freq);
1958
1959                 /* re-evaluate to get actual register value */
1960                 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq);
1961         }
1962
1963         mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val);
1964 }
1965
1966 /* Free Tx queue skbuffs */
1967 static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
1968                                 struct mvpp2_tx_queue *txq,
1969                                 struct mvpp2_txq_pcpu *txq_pcpu, int num)
1970 {
1971         int i;
1972
1973         for (i = 0; i < num; i++) {
1974                 struct mvpp2_txq_pcpu_buf *tx_buf =
1975                         txq_pcpu->buffs + txq_pcpu->txq_get_index;
1976
1977                 if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma))
1978                         dma_unmap_single(port->dev->dev.parent, tx_buf->dma,
1979                                          tx_buf->size, DMA_TO_DEVICE);
1980                 if (tx_buf->skb)
1981                         dev_kfree_skb_any(tx_buf->skb);
1982
1983                 mvpp2_txq_inc_get(txq_pcpu);
1984         }
1985 }
1986
1987 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
1988                                                         u32 cause)
1989 {
1990         int queue = fls(cause) - 1;
1991
1992         return port->rxqs[queue];
1993 }
1994
1995 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
1996                                                         u32 cause)
1997 {
1998         int queue = fls(cause) - 1;
1999
2000         return port->txqs[queue];
2001 }
2002
2003 /* Handle end of transmission */
2004 static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
2005                            struct mvpp2_txq_pcpu *txq_pcpu)
2006 {
2007         struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id);
2008         int tx_done;
2009
2010         if (txq_pcpu->thread != mvpp2_cpu_to_thread(port->priv, smp_processor_id()))
2011                 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n");
2012
2013         tx_done = mvpp2_txq_sent_desc_proc(port, txq);
2014         if (!tx_done)
2015                 return;
2016         mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done);
2017
2018         txq_pcpu->count -= tx_done;
2019
2020         if (netif_tx_queue_stopped(nq))
2021                 if (txq_pcpu->count <= txq_pcpu->wake_threshold)
2022                         netif_tx_wake_queue(nq);
2023 }
2024
2025 static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause,
2026                                   unsigned int thread)
2027 {
2028         struct mvpp2_tx_queue *txq;
2029         struct mvpp2_txq_pcpu *txq_pcpu;
2030         unsigned int tx_todo = 0;
2031
2032         while (cause) {
2033                 txq = mvpp2_get_tx_queue(port, cause);
2034                 if (!txq)
2035                         break;
2036
2037                 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2038
2039                 if (txq_pcpu->count) {
2040                         mvpp2_txq_done(port, txq, txq_pcpu);
2041                         tx_todo += txq_pcpu->count;
2042                 }
2043
2044                 cause &= ~(1 << txq->log_id);
2045         }
2046         return tx_todo;
2047 }
2048
2049 /* Rx/Tx queue initialization/cleanup methods */
2050
2051 /* Allocate and initialize descriptors for aggr TXQ */
2052 static int mvpp2_aggr_txq_init(struct platform_device *pdev,
2053                                struct mvpp2_tx_queue *aggr_txq,
2054                                unsigned int thread, struct mvpp2 *priv)
2055 {
2056         u32 txq_dma;
2057
2058         /* Allocate memory for TX descriptors */
2059         aggr_txq->descs = dma_zalloc_coherent(&pdev->dev,
2060                                 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
2061                                 &aggr_txq->descs_dma, GFP_KERNEL);
2062         if (!aggr_txq->descs)
2063                 return -ENOMEM;
2064
2065         aggr_txq->last_desc = MVPP2_AGGR_TXQ_SIZE - 1;
2066
2067         /* Aggr TXQ no reset WA */
2068         aggr_txq->next_desc_to_proc = mvpp2_read(priv,
2069                                                  MVPP2_AGGR_TXQ_INDEX_REG(thread));
2070
2071         /* Set Tx descriptors queue starting address indirect
2072          * access
2073          */
2074         if (priv->hw_version == MVPP21)
2075                 txq_dma = aggr_txq->descs_dma;
2076         else
2077                 txq_dma = aggr_txq->descs_dma >>
2078                         MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
2079
2080         mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(thread), txq_dma);
2081         mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(thread),
2082                     MVPP2_AGGR_TXQ_SIZE);
2083
2084         return 0;
2085 }
2086
2087 /* Create a specified Rx queue */
2088 static int mvpp2_rxq_init(struct mvpp2_port *port,
2089                           struct mvpp2_rx_queue *rxq)
2090
2091 {
2092         unsigned int thread;
2093         u32 rxq_dma;
2094
2095         rxq->size = port->rx_ring_size;
2096
2097         /* Allocate memory for RX descriptors */
2098         rxq->descs = dma_alloc_coherent(port->dev->dev.parent,
2099                                         rxq->size * MVPP2_DESC_ALIGNED_SIZE,
2100                                         &rxq->descs_dma, GFP_KERNEL);
2101         if (!rxq->descs)
2102                 return -ENOMEM;
2103
2104         rxq->last_desc = rxq->size - 1;
2105
2106         /* Zero occupied and non-occupied counters - direct access */
2107         mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
2108
2109         /* Set Rx descriptors queue starting address - indirect access */
2110         thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2111         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
2112         if (port->priv->hw_version == MVPP21)
2113                 rxq_dma = rxq->descs_dma;
2114         else
2115                 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
2116         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
2117         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
2118         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_INDEX_REG, 0);
2119         put_cpu();
2120
2121         /* Set Offset */
2122         mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
2123
2124         /* Set coalescing pkts and time */
2125         mvpp2_rx_pkts_coal_set(port, rxq);
2126         mvpp2_rx_time_coal_set(port, rxq);
2127
2128         /* Add number of descriptors ready for receiving packets */
2129         mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
2130
2131         return 0;
2132 }
2133
2134 /* Push packets received by the RXQ to BM pool */
2135 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
2136                                 struct mvpp2_rx_queue *rxq)
2137 {
2138         int rx_received, i;
2139
2140         rx_received = mvpp2_rxq_received(port, rxq->id);
2141         if (!rx_received)
2142                 return;
2143
2144         for (i = 0; i < rx_received; i++) {
2145                 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
2146                 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
2147                 int pool;
2148
2149                 pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >>
2150                         MVPP2_RXD_BM_POOL_ID_OFFS;
2151
2152                 mvpp2_bm_pool_put(port, pool,
2153                                   mvpp2_rxdesc_dma_addr_get(port, rx_desc),
2154                                   mvpp2_rxdesc_cookie_get(port, rx_desc));
2155         }
2156         mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
2157 }
2158
2159 /* Cleanup Rx queue */
2160 static void mvpp2_rxq_deinit(struct mvpp2_port *port,
2161                              struct mvpp2_rx_queue *rxq)
2162 {
2163         unsigned int thread;
2164
2165         mvpp2_rxq_drop_pkts(port, rxq);
2166
2167         if (rxq->descs)
2168                 dma_free_coherent(port->dev->dev.parent,
2169                                   rxq->size * MVPP2_DESC_ALIGNED_SIZE,
2170                                   rxq->descs,
2171                                   rxq->descs_dma);
2172
2173         rxq->descs             = NULL;
2174         rxq->last_desc         = 0;
2175         rxq->next_desc_to_proc = 0;
2176         rxq->descs_dma         = 0;
2177
2178         /* Clear Rx descriptors queue starting address and size;
2179          * free descriptor number
2180          */
2181         mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
2182         thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2183         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
2184         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, 0);
2185         mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, 0);
2186         put_cpu();
2187 }
2188
2189 /* Create and initialize a Tx queue */
2190 static int mvpp2_txq_init(struct mvpp2_port *port,
2191                           struct mvpp2_tx_queue *txq)
2192 {
2193         u32 val;
2194         unsigned int thread;
2195         int desc, desc_per_txq, tx_port_num;
2196         struct mvpp2_txq_pcpu *txq_pcpu;
2197
2198         txq->size = port->tx_ring_size;
2199
2200         /* Allocate memory for Tx descriptors */
2201         txq->descs = dma_alloc_coherent(port->dev->dev.parent,
2202                                 txq->size * MVPP2_DESC_ALIGNED_SIZE,
2203                                 &txq->descs_dma, GFP_KERNEL);
2204         if (!txq->descs)
2205                 return -ENOMEM;
2206
2207         txq->last_desc = txq->size - 1;
2208
2209         /* Set Tx descriptors queue starting address - indirect access */
2210         thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2211         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
2212         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG,
2213                            txq->descs_dma);
2214         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG,
2215                            txq->size & MVPP2_TXQ_DESC_SIZE_MASK);
2216         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_INDEX_REG, 0);
2217         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_RSVD_CLR_REG,
2218                            txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
2219         val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PENDING_REG);
2220         val &= ~MVPP2_TXQ_PENDING_MASK;
2221         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PENDING_REG, val);
2222
2223         /* Calculate base address in prefetch buffer. We reserve 16 descriptors
2224          * for each existing TXQ.
2225          * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
2226          * GBE ports assumed to be continuous from 0 to MVPP2_MAX_PORTS
2227          */
2228         desc_per_txq = 16;
2229         desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
2230                (txq->log_id * desc_per_txq);
2231
2232         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG,
2233                            MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
2234                            MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
2235         put_cpu();
2236
2237         /* WRR / EJP configuration - indirect access */
2238         tx_port_num = mvpp2_egress_port(port);
2239         mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2240
2241         val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
2242         val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
2243         val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
2244         val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
2245         mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
2246
2247         val = MVPP2_TXQ_TOKEN_SIZE_MAX;
2248         mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
2249                     val);
2250
2251         for (thread = 0; thread < port->priv->nthreads; thread++) {
2252                 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2253                 txq_pcpu->size = txq->size;
2254                 txq_pcpu->buffs = kmalloc_array(txq_pcpu->size,
2255                                                 sizeof(*txq_pcpu->buffs),
2256                                                 GFP_KERNEL);
2257                 if (!txq_pcpu->buffs)
2258                         return -ENOMEM;
2259
2260                 txq_pcpu->count = 0;
2261                 txq_pcpu->reserved_num = 0;
2262                 txq_pcpu->txq_put_index = 0;
2263                 txq_pcpu->txq_get_index = 0;
2264                 txq_pcpu->tso_headers = NULL;
2265
2266                 txq_pcpu->stop_threshold = txq->size - MVPP2_MAX_SKB_DESCS;
2267                 txq_pcpu->wake_threshold = txq_pcpu->stop_threshold / 2;
2268
2269                 txq_pcpu->tso_headers =
2270                         dma_alloc_coherent(port->dev->dev.parent,
2271                                            txq_pcpu->size * TSO_HEADER_SIZE,
2272                                            &txq_pcpu->tso_headers_dma,
2273                                            GFP_KERNEL);
2274                 if (!txq_pcpu->tso_headers)
2275                         return -ENOMEM;
2276         }
2277
2278         return 0;
2279 }
2280
2281 /* Free allocated TXQ resources */
2282 static void mvpp2_txq_deinit(struct mvpp2_port *port,
2283                              struct mvpp2_tx_queue *txq)
2284 {
2285         struct mvpp2_txq_pcpu *txq_pcpu;
2286         unsigned int thread;
2287
2288         for (thread = 0; thread < port->priv->nthreads; thread++) {
2289                 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2290                 kfree(txq_pcpu->buffs);
2291
2292                 if (txq_pcpu->tso_headers)
2293                         dma_free_coherent(port->dev->dev.parent,
2294                                           txq_pcpu->size * TSO_HEADER_SIZE,
2295                                           txq_pcpu->tso_headers,
2296                                           txq_pcpu->tso_headers_dma);
2297
2298                 txq_pcpu->tso_headers = NULL;
2299         }
2300
2301         if (txq->descs)
2302                 dma_free_coherent(port->dev->dev.parent,
2303                                   txq->size * MVPP2_DESC_ALIGNED_SIZE,
2304                                   txq->descs, txq->descs_dma);
2305
2306         txq->descs             = NULL;
2307         txq->last_desc         = 0;
2308         txq->next_desc_to_proc = 0;
2309         txq->descs_dma         = 0;
2310
2311         /* Set minimum bandwidth for disabled TXQs */
2312         mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
2313
2314         /* Set Tx descriptors queue starting address and size */
2315         thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2316         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
2317         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 0);
2318         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 0);
2319         put_cpu();
2320 }
2321
2322 /* Cleanup Tx ports */
2323 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
2324 {
2325         struct mvpp2_txq_pcpu *txq_pcpu;
2326         int delay, pending;
2327         unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2328         u32 val;
2329
2330         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
2331         val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG);
2332         val |= MVPP2_TXQ_DRAIN_EN_MASK;
2333         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val);
2334
2335         /* The napi queue has been stopped so wait for all packets
2336          * to be transmitted.
2337          */
2338         delay = 0;
2339         do {
2340                 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
2341                         netdev_warn(port->dev,
2342                                     "port %d: cleaning queue %d timed out\n",
2343                                     port->id, txq->log_id);
2344                         break;
2345                 }
2346                 mdelay(1);
2347                 delay++;
2348
2349                 pending = mvpp2_thread_read(port->priv, thread,
2350                                             MVPP2_TXQ_PENDING_REG);
2351                 pending &= MVPP2_TXQ_PENDING_MASK;
2352         } while (pending);
2353
2354         val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
2355         mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val);
2356         put_cpu();
2357
2358         for (thread = 0; thread < port->priv->nthreads; thread++) {
2359                 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2360
2361                 /* Release all packets */
2362                 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
2363
2364                 /* Reset queue */
2365                 txq_pcpu->count = 0;
2366                 txq_pcpu->txq_put_index = 0;
2367                 txq_pcpu->txq_get_index = 0;
2368         }
2369 }
2370
2371 /* Cleanup all Tx queues */
2372 static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
2373 {
2374         struct mvpp2_tx_queue *txq;
2375         int queue;
2376         u32 val;
2377
2378         val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
2379
2380         /* Reset Tx ports and delete Tx queues */
2381         val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
2382         mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
2383
2384         for (queue = 0; queue < port->ntxqs; queue++) {
2385                 txq = port->txqs[queue];
2386                 mvpp2_txq_clean(port, txq);
2387                 mvpp2_txq_deinit(port, txq);
2388         }
2389
2390         on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
2391
2392         val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
2393         mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
2394 }
2395
2396 /* Cleanup all Rx queues */
2397 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
2398 {
2399         int queue;
2400
2401         for (queue = 0; queue < port->nrxqs; queue++)
2402                 mvpp2_rxq_deinit(port, port->rxqs[queue]);
2403 }
2404
2405 /* Init all Rx queues for port */
2406 static int mvpp2_setup_rxqs(struct mvpp2_port *port)
2407 {
2408         int queue, err;
2409
2410         for (queue = 0; queue < port->nrxqs; queue++) {
2411                 err = mvpp2_rxq_init(port, port->rxqs[queue]);
2412                 if (err)
2413                         goto err_cleanup;
2414         }
2415         return 0;
2416
2417 err_cleanup:
2418         mvpp2_cleanup_rxqs(port);
2419         return err;
2420 }
2421
2422 /* Init all tx queues for port */
2423 static int mvpp2_setup_txqs(struct mvpp2_port *port)
2424 {
2425         struct mvpp2_tx_queue *txq;
2426         int queue, err;
2427
2428         for (queue = 0; queue < port->ntxqs; queue++) {
2429                 txq = port->txqs[queue];
2430                 err = mvpp2_txq_init(port, txq);
2431                 if (err)
2432                         goto err_cleanup;
2433         }
2434
2435         if (port->has_tx_irqs) {
2436                 mvpp2_tx_time_coal_set(port);
2437                 for (queue = 0; queue < port->ntxqs; queue++) {
2438                         txq = port->txqs[queue];
2439                         mvpp2_tx_pkts_coal_set(port, txq);
2440                 }
2441         }
2442
2443         on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
2444         return 0;
2445
2446 err_cleanup:
2447         mvpp2_cleanup_txqs(port);
2448         return err;
2449 }
2450
2451 /* The callback for per-port interrupt */
2452 static irqreturn_t mvpp2_isr(int irq, void *dev_id)
2453 {
2454         struct mvpp2_queue_vector *qv = dev_id;
2455
2456         mvpp2_qvec_interrupt_disable(qv);
2457
2458         napi_schedule(&qv->napi);
2459
2460         return IRQ_HANDLED;
2461 }
2462
2463 /* Per-port interrupt for link status changes */
2464 static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id)
2465 {
2466         struct mvpp2_port *port = (struct mvpp2_port *)dev_id;
2467         struct net_device *dev = port->dev;
2468         bool event = false, link = false;
2469         u32 val;
2470
2471         mvpp22_gop_mask_irq(port);
2472
2473         if (port->gop_id == 0 &&
2474             port->phy_interface == PHY_INTERFACE_MODE_10GKR) {
2475                 val = readl(port->base + MVPP22_XLG_INT_STAT);
2476                 if (val & MVPP22_XLG_INT_STAT_LINK) {
2477                         event = true;
2478                         val = readl(port->base + MVPP22_XLG_STATUS);
2479                         if (val & MVPP22_XLG_STATUS_LINK_UP)
2480                                 link = true;
2481                 }
2482         } else if (phy_interface_mode_is_rgmii(port->phy_interface) ||
2483                    port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
2484                    port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
2485                    port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
2486                 val = readl(port->base + MVPP22_GMAC_INT_STAT);
2487                 if (val & MVPP22_GMAC_INT_STAT_LINK) {
2488                         event = true;
2489                         val = readl(port->base + MVPP2_GMAC_STATUS0);
2490                         if (val & MVPP2_GMAC_STATUS0_LINK_UP)
2491                                 link = true;
2492                 }
2493         }
2494
2495         if (port->phylink) {
2496                 phylink_mac_change(port->phylink, link);
2497                 goto handled;
2498         }
2499
2500         if (!netif_running(dev) || !event)
2501                 goto handled;
2502
2503         if (link) {
2504                 mvpp2_interrupts_enable(port);
2505
2506                 mvpp2_egress_enable(port);
2507                 mvpp2_ingress_enable(port);
2508                 netif_carrier_on(dev);
2509                 netif_tx_wake_all_queues(dev);
2510         } else {
2511                 netif_tx_stop_all_queues(dev);
2512                 netif_carrier_off(dev);
2513                 mvpp2_ingress_disable(port);
2514                 mvpp2_egress_disable(port);
2515
2516                 mvpp2_interrupts_disable(port);
2517         }
2518
2519 handled:
2520         mvpp22_gop_unmask_irq(port);
2521         return IRQ_HANDLED;
2522 }
2523
2524 static void mvpp2_timer_set(struct mvpp2_port_pcpu *port_pcpu)
2525 {
2526         ktime_t interval;
2527
2528         if (!port_pcpu->timer_scheduled) {
2529                 port_pcpu->timer_scheduled = true;
2530                 interval = MVPP2_TXDONE_HRTIMER_PERIOD_NS;
2531                 hrtimer_start(&port_pcpu->tx_done_timer, interval,
2532                               HRTIMER_MODE_REL_PINNED);
2533         }
2534 }
2535
2536 static void mvpp2_tx_proc_cb(unsigned long data)
2537 {
2538         struct net_device *dev = (struct net_device *)data;
2539         struct mvpp2_port *port = netdev_priv(dev);
2540         struct mvpp2_port_pcpu *port_pcpu;
2541         unsigned int tx_todo, cause;
2542
2543         port_pcpu = per_cpu_ptr(port->pcpu,
2544                                 mvpp2_cpu_to_thread(port->priv, smp_processor_id()));
2545
2546         if (!netif_running(dev))
2547                 return;
2548         port_pcpu->timer_scheduled = false;
2549
2550         /* Process all the Tx queues */
2551         cause = (1 << port->ntxqs) - 1;
2552         tx_todo = mvpp2_tx_done(port, cause,
2553                                 mvpp2_cpu_to_thread(port->priv, smp_processor_id()));
2554
2555         /* Set the timer in case not all the packets were processed */
2556         if (tx_todo)
2557                 mvpp2_timer_set(port_pcpu);
2558 }
2559
2560 static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer)
2561 {
2562         struct mvpp2_port_pcpu *port_pcpu = container_of(timer,
2563                                                          struct mvpp2_port_pcpu,
2564                                                          tx_done_timer);
2565
2566         tasklet_schedule(&port_pcpu->tx_done_tasklet);
2567
2568         return HRTIMER_NORESTART;
2569 }
2570
2571 /* Main RX/TX processing routines */
2572
2573 /* Display more error info */
2574 static void mvpp2_rx_error(struct mvpp2_port *port,
2575                            struct mvpp2_rx_desc *rx_desc)
2576 {
2577         u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
2578         size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
2579         char *err_str = NULL;
2580
2581         switch (status & MVPP2_RXD_ERR_CODE_MASK) {
2582         case MVPP2_RXD_ERR_CRC:
2583                 err_str = "crc";
2584                 break;
2585         case MVPP2_RXD_ERR_OVERRUN:
2586                 err_str = "overrun";
2587                 break;
2588         case MVPP2_RXD_ERR_RESOURCE:
2589                 err_str = "resource";
2590                 break;
2591         }
2592         if (err_str && net_ratelimit())
2593                 netdev_err(port->dev,
2594                            "bad rx status %08x (%s error), size=%zu\n",
2595                            status, err_str, sz);
2596 }
2597
2598 /* Handle RX checksum offload */
2599 static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status,
2600                           struct sk_buff *skb)
2601 {
2602         if (((status & MVPP2_RXD_L3_IP4) &&
2603              !(status & MVPP2_RXD_IP4_HEADER_ERR)) ||
2604             (status & MVPP2_RXD_L3_IP6))
2605                 if (((status & MVPP2_RXD_L4_UDP) ||
2606                      (status & MVPP2_RXD_L4_TCP)) &&
2607                      (status & MVPP2_RXD_L4_CSUM_OK)) {
2608                         skb->csum = 0;
2609                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2610                         return;
2611                 }
2612
2613         skb->ip_summed = CHECKSUM_NONE;
2614 }
2615
2616 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */
2617 static int mvpp2_rx_refill(struct mvpp2_port *port,
2618                            struct mvpp2_bm_pool *bm_pool, int pool)
2619 {
2620         dma_addr_t dma_addr;
2621         phys_addr_t phys_addr;
2622         void *buf;
2623
2624         /* No recycle or too many buffers are in use, so allocate a new skb */
2625         buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, &phys_addr,
2626                               GFP_ATOMIC);
2627         if (!buf)
2628                 return -ENOMEM;
2629
2630         mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
2631
2632         return 0;
2633 }
2634
2635 /* Handle tx checksum */
2636 static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb)
2637 {
2638         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2639                 int ip_hdr_len = 0;
2640                 u8 l4_proto;
2641
2642                 if (skb->protocol == htons(ETH_P_IP)) {
2643                         struct iphdr *ip4h = ip_hdr(skb);
2644
2645                         /* Calculate IPv4 checksum and L4 checksum */
2646                         ip_hdr_len = ip4h->ihl;
2647                         l4_proto = ip4h->protocol;
2648                 } else if (skb->protocol == htons(ETH_P_IPV6)) {
2649                         struct ipv6hdr *ip6h = ipv6_hdr(skb);
2650
2651                         /* Read l4_protocol from one of IPv6 extra headers */
2652                         if (skb_network_header_len(skb) > 0)
2653                                 ip_hdr_len = (skb_network_header_len(skb) >> 2);
2654                         l4_proto = ip6h->nexthdr;
2655                 } else {
2656                         return MVPP2_TXD_L4_CSUM_NOT;
2657                 }
2658
2659                 return mvpp2_txq_desc_csum(skb_network_offset(skb),
2660                                 skb->protocol, ip_hdr_len, l4_proto);
2661         }
2662
2663         return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE;
2664 }
2665
2666 /* Main rx processing */
2667 static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi,
2668                     int rx_todo, struct mvpp2_rx_queue *rxq)
2669 {
2670         struct net_device *dev = port->dev;
2671         int rx_received;
2672         int rx_done = 0;
2673         u32 rcvd_pkts = 0;
2674         u32 rcvd_bytes = 0;
2675
2676         /* Get number of received packets and clamp the to-do */
2677         rx_received = mvpp2_rxq_received(port, rxq->id);
2678         if (rx_todo > rx_received)
2679                 rx_todo = rx_received;
2680
2681         while (rx_done < rx_todo) {
2682                 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
2683                 struct mvpp2_bm_pool *bm_pool;
2684                 struct sk_buff *skb;
2685                 unsigned int frag_size;
2686                 dma_addr_t dma_addr;
2687                 phys_addr_t phys_addr;
2688                 u32 rx_status;
2689                 int pool, rx_bytes, err;
2690                 void *data;
2691
2692                 rx_done++;
2693                 rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
2694                 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
2695                 rx_bytes -= MVPP2_MH_SIZE;
2696                 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
2697                 phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc);
2698                 data = (void *)phys_to_virt(phys_addr);
2699
2700                 pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >>
2701                         MVPP2_RXD_BM_POOL_ID_OFFS;
2702                 bm_pool = &port->priv->bm_pools[pool];
2703
2704                 /* In case of an error, release the requested buffer pointer
2705                  * to the Buffer Manager. This request process is controlled
2706                  * by the hardware, and the information about the buffer is
2707                  * comprised by the RX descriptor.
2708                  */
2709                 if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
2710 err_drop_frame:
2711                         dev->stats.rx_errors++;
2712                         mvpp2_rx_error(port, rx_desc);
2713                         /* Return the buffer to the pool */
2714                         mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
2715                         continue;
2716                 }
2717
2718                 if (bm_pool->frag_size > PAGE_SIZE)
2719                         frag_size = 0;
2720                 else
2721                         frag_size = bm_pool->frag_size;
2722
2723                 skb = build_skb(data, frag_size);
2724                 if (!skb) {
2725                         netdev_warn(port->dev, "skb build failed\n");
2726                         goto err_drop_frame;
2727                 }
2728
2729                 err = mvpp2_rx_refill(port, bm_pool, pool);
2730                 if (err) {
2731                         netdev_err(port->dev, "failed to refill BM pools\n");
2732                         goto err_drop_frame;
2733                 }
2734
2735                 dma_unmap_single(dev->dev.parent, dma_addr,
2736                                  bm_pool->buf_size, DMA_FROM_DEVICE);
2737
2738                 rcvd_pkts++;
2739                 rcvd_bytes += rx_bytes;
2740
2741                 skb_reserve(skb, MVPP2_MH_SIZE + NET_SKB_PAD);
2742                 skb_put(skb, rx_bytes);
2743                 skb->protocol = eth_type_trans(skb, dev);
2744                 mvpp2_rx_csum(port, rx_status, skb);
2745
2746                 napi_gro_receive(napi, skb);
2747         }
2748
2749         if (rcvd_pkts) {
2750                 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
2751
2752                 u64_stats_update_begin(&stats->syncp);
2753                 stats->rx_packets += rcvd_pkts;
2754                 stats->rx_bytes   += rcvd_bytes;
2755                 u64_stats_update_end(&stats->syncp);
2756         }
2757
2758         /* Update Rx queue management counters */
2759         wmb();
2760         mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done);
2761
2762         return rx_todo;
2763 }
2764
2765 static inline void
2766 tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
2767                   struct mvpp2_tx_desc *desc)
2768 {
2769         unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
2770         struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2771
2772         dma_addr_t buf_dma_addr =
2773                 mvpp2_txdesc_dma_addr_get(port, desc);
2774         size_t buf_sz =
2775                 mvpp2_txdesc_size_get(port, desc);
2776         if (!IS_TSO_HEADER(txq_pcpu, buf_dma_addr))
2777                 dma_unmap_single(port->dev->dev.parent, buf_dma_addr,
2778                                  buf_sz, DMA_TO_DEVICE);
2779         mvpp2_txq_desc_put(txq);
2780 }
2781
2782 /* Handle tx fragmentation processing */
2783 static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb,
2784                                  struct mvpp2_tx_queue *aggr_txq,
2785                                  struct mvpp2_tx_queue *txq)
2786 {
2787         unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
2788         struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2789         struct mvpp2_tx_desc *tx_desc;
2790         int i;
2791         dma_addr_t buf_dma_addr;
2792
2793         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2794                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2795                 void *addr = page_address(frag->page.p) + frag->page_offset;
2796
2797                 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
2798                 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
2799                 mvpp2_txdesc_size_set(port, tx_desc, frag->size);
2800
2801                 buf_dma_addr = dma_map_single(port->dev->dev.parent, addr,
2802                                               frag->size, DMA_TO_DEVICE);
2803                 if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) {
2804                         mvpp2_txq_desc_put(txq);
2805                         goto cleanup;
2806                 }
2807
2808                 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
2809
2810                 if (i == (skb_shinfo(skb)->nr_frags - 1)) {
2811                         /* Last descriptor */
2812                         mvpp2_txdesc_cmd_set(port, tx_desc,
2813                                              MVPP2_TXD_L_DESC);
2814                         mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc);
2815                 } else {
2816                         /* Descriptor in the middle: Not First, Not Last */
2817                         mvpp2_txdesc_cmd_set(port, tx_desc, 0);
2818                         mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
2819                 }
2820         }
2821
2822         return 0;
2823 cleanup:
2824         /* Release all descriptors that were used to map fragments of
2825          * this packet, as well as the corresponding DMA mappings
2826          */
2827         for (i = i - 1; i >= 0; i--) {
2828                 tx_desc = txq->descs + i;
2829                 tx_desc_unmap_put(port, txq, tx_desc);
2830         }
2831
2832         return -ENOMEM;
2833 }
2834
2835 static inline void mvpp2_tso_put_hdr(struct sk_buff *skb,
2836                                      struct net_device *dev,
2837                                      struct mvpp2_tx_queue *txq,
2838                                      struct mvpp2_tx_queue *aggr_txq,
2839                                      struct mvpp2_txq_pcpu *txq_pcpu,
2840                                      int hdr_sz)
2841 {
2842         struct mvpp2_port *port = netdev_priv(dev);
2843         struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
2844         dma_addr_t addr;
2845
2846         mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
2847         mvpp2_txdesc_size_set(port, tx_desc, hdr_sz);
2848
2849         addr = txq_pcpu->tso_headers_dma +
2850                txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
2851         mvpp2_txdesc_dma_addr_set(port, tx_desc, addr);
2852
2853         mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) |
2854                                             MVPP2_TXD_F_DESC |
2855                                             MVPP2_TXD_PADDING_DISABLE);
2856         mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
2857 }
2858
2859 static inline int mvpp2_tso_put_data(struct sk_buff *skb,
2860                                      struct net_device *dev, struct tso_t *tso,
2861                                      struct mvpp2_tx_queue *txq,
2862                                      struct mvpp2_tx_queue *aggr_txq,
2863                                      struct mvpp2_txq_pcpu *txq_pcpu,
2864                                      int sz, bool left, bool last)
2865 {
2866         struct mvpp2_port *port = netdev_priv(dev);
2867         struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
2868         dma_addr_t buf_dma_addr;
2869
2870         mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
2871         mvpp2_txdesc_size_set(port, tx_desc, sz);
2872
2873         buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz,
2874                                       DMA_TO_DEVICE);
2875         if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
2876                 mvpp2_txq_desc_put(txq);
2877                 return -ENOMEM;
2878         }
2879
2880         mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
2881
2882         if (!left) {
2883                 mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC);
2884                 if (last) {
2885                         mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc);
2886                         return 0;
2887                 }
2888         } else {
2889                 mvpp2_txdesc_cmd_set(port, tx_desc, 0);
2890         }
2891
2892         mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
2893         return 0;
2894 }
2895
2896 static int mvpp2_tx_tso(struct sk_buff *skb, struct net_device *dev,
2897                         struct mvpp2_tx_queue *txq,
2898                         struct mvpp2_tx_queue *aggr_txq,
2899                         struct mvpp2_txq_pcpu *txq_pcpu)
2900 {
2901         struct mvpp2_port *port = netdev_priv(dev);
2902         struct tso_t tso;
2903         int hdr_sz = skb_transport_offset(skb) + tcp_hdrlen(skb);
2904         int i, len, descs = 0;
2905
2906         /* Check number of available descriptors */
2907         if (mvpp2_aggr_desc_num_check(port, aggr_txq, tso_count_descs(skb)) ||
2908             mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu,
2909                                              tso_count_descs(skb)))
2910                 return 0;
2911
2912         tso_start(skb, &tso);
2913         len = skb->len - hdr_sz;
2914         while (len > 0) {
2915                 int left = min_t(int, skb_shinfo(skb)->gso_size, len);
2916                 char *hdr = txq_pcpu->tso_headers +
2917                             txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
2918
2919                 len -= left;
2920                 descs++;
2921
2922                 tso_build_hdr(skb, hdr, &tso, left, len == 0);
2923                 mvpp2_tso_put_hdr(skb, dev, txq, aggr_txq, txq_pcpu, hdr_sz);
2924
2925                 while (left > 0) {
2926                         int sz = min_t(int, tso.size, left);
2927                         left -= sz;
2928                         descs++;
2929
2930                         if (mvpp2_tso_put_data(skb, dev, &tso, txq, aggr_txq,
2931                                                txq_pcpu, sz, left, len == 0))
2932                                 goto release;
2933                         tso_build_data(skb, &tso, sz);
2934                 }
2935         }
2936
2937         return descs;
2938
2939 release:
2940         for (i = descs - 1; i >= 0; i--) {
2941                 struct mvpp2_tx_desc *tx_desc = txq->descs + i;
2942                 tx_desc_unmap_put(port, txq, tx_desc);
2943         }
2944         return 0;
2945 }
2946
2947 /* Main tx processing */
2948 static int mvpp2_tx(struct sk_buff *skb, struct net_device *dev)
2949 {
2950         struct mvpp2_port *port = netdev_priv(dev);
2951         struct mvpp2_tx_queue *txq, *aggr_txq;
2952         struct mvpp2_txq_pcpu *txq_pcpu;
2953         struct mvpp2_tx_desc *tx_desc;
2954         dma_addr_t buf_dma_addr;
2955         unsigned long flags = 0;
2956         unsigned int thread;
2957         int frags = 0;
2958         u16 txq_id;
2959         u32 tx_cmd;
2960
2961         thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
2962
2963         txq_id = skb_get_queue_mapping(skb);
2964         txq = port->txqs[txq_id];
2965         txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2966         aggr_txq = &port->priv->aggr_txqs[thread];
2967
2968         if (test_bit(thread, &port->priv->lock_map))
2969                 spin_lock_irqsave(&port->tx_lock[thread], flags);
2970
2971         if (skb_is_gso(skb)) {
2972                 frags = mvpp2_tx_tso(skb, dev, txq, aggr_txq, txq_pcpu);
2973                 goto out;
2974         }
2975         frags = skb_shinfo(skb)->nr_frags + 1;
2976
2977         /* Check number of available descriptors */
2978         if (mvpp2_aggr_desc_num_check(port, aggr_txq, frags) ||
2979             mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, frags)) {
2980                 frags = 0;
2981                 goto out;
2982         }
2983
2984         /* Get a descriptor for the first part of the packet */
2985         tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
2986         mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
2987         mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb));
2988
2989         buf_dma_addr = dma_map_single(dev->dev.parent, skb->data,
2990                                       skb_headlen(skb), DMA_TO_DEVICE);
2991         if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
2992                 mvpp2_txq_desc_put(txq);
2993                 frags = 0;
2994                 goto out;
2995         }
2996
2997         mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
2998
2999         tx_cmd = mvpp2_skb_tx_csum(port, skb);
3000
3001         if (frags == 1) {
3002                 /* First and Last descriptor */
3003                 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
3004                 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
3005                 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc);
3006         } else {
3007                 /* First but not Last */
3008                 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE;
3009                 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
3010                 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
3011
3012                 /* Continue with other skb fragments */
3013                 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) {
3014                         tx_desc_unmap_put(port, txq, tx_desc);
3015                         frags = 0;
3016                 }
3017         }
3018
3019 out:
3020         if (frags > 0) {
3021                 struct mvpp2_pcpu_stats *stats = per_cpu_ptr(port->stats, thread);
3022                 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
3023
3024                 txq_pcpu->reserved_num -= frags;
3025                 txq_pcpu->count += frags;
3026                 aggr_txq->count += frags;
3027
3028                 /* Enable transmit */
3029                 wmb();
3030                 mvpp2_aggr_txq_pend_desc_add(port, frags);
3031
3032                 if (txq_pcpu->count >= txq_pcpu->stop_threshold)
3033                         netif_tx_stop_queue(nq);
3034
3035                 u64_stats_update_begin(&stats->syncp);
3036                 stats->tx_packets++;
3037                 stats->tx_bytes += skb->len;
3038                 u64_stats_update_end(&stats->syncp);
3039         } else {
3040                 dev->stats.tx_dropped++;
3041                 dev_kfree_skb_any(skb);
3042         }
3043
3044         /* Finalize TX processing */
3045         if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal)
3046                 mvpp2_txq_done(port, txq, txq_pcpu);
3047
3048         /* Set the timer in case not all frags were processed */
3049         if (!port->has_tx_irqs && txq_pcpu->count <= frags &&
3050             txq_pcpu->count > 0) {
3051                 struct mvpp2_port_pcpu *port_pcpu = per_cpu_ptr(port->pcpu, thread);
3052
3053                 mvpp2_timer_set(port_pcpu);
3054         }
3055
3056         if (test_bit(thread, &port->priv->lock_map))
3057                 spin_unlock_irqrestore(&port->tx_lock[thread], flags);
3058
3059         return NETDEV_TX_OK;
3060 }
3061
3062 static inline void mvpp2_cause_error(struct net_device *dev, int cause)
3063 {
3064         if (cause & MVPP2_CAUSE_FCS_ERR_MASK)
3065                 netdev_err(dev, "FCS error\n");
3066         if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK)
3067                 netdev_err(dev, "rx fifo overrun error\n");
3068         if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK)
3069                 netdev_err(dev, "tx fifo underrun error\n");
3070 }
3071
3072 static int mvpp2_poll(struct napi_struct *napi, int budget)
3073 {
3074         u32 cause_rx_tx, cause_rx, cause_tx, cause_misc;
3075         int rx_done = 0;
3076         struct mvpp2_port *port = netdev_priv(napi->dev);
3077         struct mvpp2_queue_vector *qv;
3078         unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
3079
3080         qv = container_of(napi, struct mvpp2_queue_vector, napi);
3081
3082         /* Rx/Tx cause register
3083          *
3084          * Bits 0-15: each bit indicates received packets on the Rx queue
3085          * (bit 0 is for Rx queue 0).
3086          *
3087          * Bits 16-23: each bit indicates transmitted packets on the Tx queue
3088          * (bit 16 is for Tx queue 0).
3089          *
3090          * Each CPU has its own Rx/Tx cause register
3091          */
3092         cause_rx_tx = mvpp2_thread_read_relaxed(port->priv, qv->sw_thread_id,
3093                                                 MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
3094
3095         cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
3096         if (cause_misc) {
3097                 mvpp2_cause_error(port->dev, cause_misc);
3098
3099                 /* Clear the cause register */
3100                 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0);
3101                 mvpp2_thread_write(port->priv, thread,
3102                                    MVPP2_ISR_RX_TX_CAUSE_REG(port->id),
3103                                    cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK);
3104         }
3105
3106         cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
3107         if (cause_tx) {
3108                 cause_tx >>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET;
3109                 mvpp2_tx_done(port, cause_tx, qv->sw_thread_id);
3110         }
3111
3112         /* Process RX packets */
3113         cause_rx = cause_rx_tx &
3114                    MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
3115         cause_rx <<= qv->first_rxq;
3116         cause_rx |= qv->pending_cause_rx;
3117         while (cause_rx && budget > 0) {
3118                 int count;
3119                 struct mvpp2_rx_queue *rxq;
3120
3121                 rxq = mvpp2_get_rx_queue(port, cause_rx);
3122                 if (!rxq)
3123                         break;
3124
3125                 count = mvpp2_rx(port, napi, budget, rxq);
3126                 rx_done += count;
3127                 budget -= count;
3128                 if (budget > 0) {
3129                         /* Clear the bit associated to this Rx queue
3130                          * so that next iteration will continue from
3131                          * the next Rx queue.
3132                          */
3133                         cause_rx &= ~(1 << rxq->logic_rxq);
3134                 }
3135         }
3136
3137         if (budget > 0) {
3138                 cause_rx = 0;
3139                 napi_complete_done(napi, rx_done);
3140
3141                 mvpp2_qvec_interrupt_enable(qv);
3142         }
3143         qv->pending_cause_rx = cause_rx;
3144         return rx_done;
3145 }
3146
3147 static void mvpp22_mode_reconfigure(struct mvpp2_port *port)
3148 {
3149         u32 ctrl3;
3150
3151         /* comphy reconfiguration */
3152         mvpp22_comphy_init(port);
3153
3154         /* gop reconfiguration */
3155         mvpp22_gop_init(port);
3156
3157         /* Only GOP port 0 has an XLG MAC */
3158         if (port->gop_id == 0) {
3159                 ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG);
3160                 ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
3161
3162                 if (port->phy_interface == PHY_INTERFACE_MODE_XAUI ||
3163                     port->phy_interface == PHY_INTERFACE_MODE_10GKR)
3164                         ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G;
3165                 else
3166                         ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
3167
3168                 writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG);
3169         }
3170
3171         if (port->gop_id == 0 &&
3172             (port->phy_interface == PHY_INTERFACE_MODE_XAUI ||
3173              port->phy_interface == PHY_INTERFACE_MODE_10GKR))
3174                 mvpp2_xlg_max_rx_size_set(port);
3175         else
3176                 mvpp2_gmac_max_rx_size_set(port);
3177 }
3178
3179 /* Set hw internals when starting port */
3180 static void mvpp2_start_dev(struct mvpp2_port *port)
3181 {
3182         int i;
3183
3184         mvpp2_txp_max_tx_size_set(port);
3185
3186         for (i = 0; i < port->nqvecs; i++)
3187                 napi_enable(&port->qvecs[i].napi);
3188
3189         /* Enable interrupts on all threads */
3190         mvpp2_interrupts_enable(port);
3191
3192         if (port->priv->hw_version == MVPP22)
3193                 mvpp22_mode_reconfigure(port);
3194
3195         if (port->phylink) {
3196                 netif_carrier_off(port->dev);
3197                 phylink_start(port->phylink);
3198         } else {
3199                 /* Phylink isn't used as of now for ACPI, so the MAC has to be
3200                  * configured manually when the interface is started. This will
3201                  * be removed as soon as the phylink ACPI support lands in.
3202                  */
3203                 struct phylink_link_state state = {
3204                         .interface = port->phy_interface,
3205                 };
3206                 mvpp2_mac_config(port->dev, MLO_AN_INBAND, &state);
3207                 mvpp2_mac_link_up(port->dev, MLO_AN_INBAND, port->phy_interface,
3208                                   NULL);
3209         }
3210
3211         netif_tx_start_all_queues(port->dev);
3212 }
3213
3214 /* Set hw internals when stopping port */
3215 static void mvpp2_stop_dev(struct mvpp2_port *port)
3216 {
3217         int i;
3218
3219         /* Disable interrupts on all threads */
3220         mvpp2_interrupts_disable(port);
3221
3222         for (i = 0; i < port->nqvecs; i++)
3223                 napi_disable(&port->qvecs[i].napi);
3224
3225         if (port->phylink)
3226                 phylink_stop(port->phylink);
3227         phy_power_off(port->comphy);
3228 }
3229
3230 static int mvpp2_check_ringparam_valid(struct net_device *dev,
3231                                        struct ethtool_ringparam *ring)
3232 {
3233         u16 new_rx_pending = ring->rx_pending;
3234         u16 new_tx_pending = ring->tx_pending;
3235
3236         if (ring->rx_pending == 0 || ring->tx_pending == 0)
3237                 return -EINVAL;
3238
3239         if (ring->rx_pending > MVPP2_MAX_RXD_MAX)
3240                 new_rx_pending = MVPP2_MAX_RXD_MAX;
3241         else if (!IS_ALIGNED(ring->rx_pending, 16))
3242                 new_rx_pending = ALIGN(ring->rx_pending, 16);
3243
3244         if (ring->tx_pending > MVPP2_MAX_TXD_MAX)
3245                 new_tx_pending = MVPP2_MAX_TXD_MAX;
3246         else if (!IS_ALIGNED(ring->tx_pending, 32))
3247                 new_tx_pending = ALIGN(ring->tx_pending, 32);
3248
3249         /* The Tx ring size cannot be smaller than the minimum number of
3250          * descriptors needed for TSO.
3251          */
3252         if (new_tx_pending < MVPP2_MAX_SKB_DESCS)
3253                 new_tx_pending = ALIGN(MVPP2_MAX_SKB_DESCS, 32);
3254
3255         if (ring->rx_pending != new_rx_pending) {
3256                 netdev_info(dev, "illegal Rx ring size value %d, round to %d\n",
3257                             ring->rx_pending, new_rx_pending);
3258                 ring->rx_pending = new_rx_pending;
3259         }
3260
3261         if (ring->tx_pending != new_tx_pending) {
3262                 netdev_info(dev, "illegal Tx ring size value %d, round to %d\n",
3263                             ring->tx_pending, new_tx_pending);
3264                 ring->tx_pending = new_tx_pending;
3265         }
3266
3267         return 0;
3268 }
3269
3270 static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr)
3271 {
3272         u32 mac_addr_l, mac_addr_m, mac_addr_h;
3273
3274         mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
3275         mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE);
3276         mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH);
3277         addr[0] = (mac_addr_h >> 24) & 0xFF;
3278         addr[1] = (mac_addr_h >> 16) & 0xFF;
3279         addr[2] = (mac_addr_h >> 8) & 0xFF;
3280         addr[3] = mac_addr_h & 0xFF;
3281         addr[4] = mac_addr_m & 0xFF;
3282         addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF;
3283 }
3284
3285 static int mvpp2_irqs_init(struct mvpp2_port *port)
3286 {
3287         int err, i;
3288
3289         for (i = 0; i < port->nqvecs; i++) {
3290                 struct mvpp2_queue_vector *qv = port->qvecs + i;
3291
3292                 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE)
3293                         irq_set_status_flags(qv->irq, IRQ_NO_BALANCING);
3294
3295                 err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv);
3296                 if (err)
3297                         goto err;
3298
3299                 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) {
3300                         unsigned long mask = 0;
3301                         unsigned int cpu;
3302
3303                         for_each_present_cpu(cpu) {
3304                                 if (mvpp2_cpu_to_thread(port->priv, cpu) ==
3305                                     qv->sw_thread_id)
3306                                         mask |= BIT(cpu);
3307                         }
3308
3309                         irq_set_affinity_hint(qv->irq, to_cpumask(&mask));
3310                 }
3311         }
3312
3313         return 0;
3314 err:
3315         for (i = 0; i < port->nqvecs; i++) {
3316                 struct mvpp2_queue_vector *qv = port->qvecs + i;
3317
3318                 irq_set_affinity_hint(qv->irq, NULL);
3319                 free_irq(qv->irq, qv);
3320         }
3321
3322         return err;
3323 }
3324
3325 static void mvpp2_irqs_deinit(struct mvpp2_port *port)
3326 {
3327         int i;
3328
3329         for (i = 0; i < port->nqvecs; i++) {
3330                 struct mvpp2_queue_vector *qv = port->qvecs + i;
3331
3332                 irq_set_affinity_hint(qv->irq, NULL);
3333                 irq_clear_status_flags(qv->irq, IRQ_NO_BALANCING);
3334                 free_irq(qv->irq, qv);
3335         }
3336 }
3337
3338 static bool mvpp22_rss_is_supported(void)
3339 {
3340         return queue_mode == MVPP2_QDIST_MULTI_MODE;
3341 }
3342
3343 static int mvpp2_open(struct net_device *dev)
3344 {
3345         struct mvpp2_port *port = netdev_priv(dev);
3346         struct mvpp2 *priv = port->priv;
3347         unsigned char mac_bcast[ETH_ALEN] = {
3348                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3349         bool valid = false;
3350         int err;
3351
3352         err = mvpp2_prs_mac_da_accept(port, mac_bcast, true);
3353         if (err) {
3354                 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
3355                 return err;
3356         }
3357         err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, true);
3358         if (err) {
3359                 netdev_err(dev, "mvpp2_prs_mac_da_accept own addr failed\n");
3360                 return err;
3361         }
3362         err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH);
3363         if (err) {
3364                 netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n");
3365                 return err;
3366         }
3367         err = mvpp2_prs_def_flow(port);
3368         if (err) {
3369                 netdev_err(dev, "mvpp2_prs_def_flow failed\n");
3370                 return err;
3371         }
3372
3373         /* Allocate the Rx/Tx queues */
3374         err = mvpp2_setup_rxqs(port);
3375         if (err) {
3376                 netdev_err(port->dev, "cannot allocate Rx queues\n");
3377                 return err;
3378         }
3379
3380         err = mvpp2_setup_txqs(port);
3381         if (err) {
3382                 netdev_err(port->dev, "cannot allocate Tx queues\n");
3383                 goto err_cleanup_rxqs;
3384         }
3385
3386         err = mvpp2_irqs_init(port);
3387         if (err) {
3388                 netdev_err(port->dev, "cannot init IRQs\n");
3389                 goto err_cleanup_txqs;
3390         }
3391
3392         /* Phylink isn't supported yet in ACPI mode */
3393         if (port->of_node) {
3394                 err = phylink_of_phy_connect(port->phylink, port->of_node, 0);
3395                 if (err) {
3396                         netdev_err(port->dev, "could not attach PHY (%d)\n",
3397                                    err);
3398                         goto err_free_irq;
3399                 }
3400
3401                 valid = true;
3402         }
3403
3404         if (priv->hw_version == MVPP22 && port->link_irq && !port->phylink) {
3405                 err = request_irq(port->link_irq, mvpp2_link_status_isr, 0,
3406                                   dev->name, port);
3407                 if (err) {
3408                         netdev_err(port->dev, "cannot request link IRQ %d\n",
3409                                    port->link_irq);
3410                         goto err_free_irq;
3411                 }
3412
3413                 mvpp22_gop_setup_irq(port);
3414
3415                 /* In default link is down */
3416                 netif_carrier_off(port->dev);
3417
3418                 valid = true;
3419         } else {
3420                 port->link_irq = 0;
3421         }
3422
3423         if (!valid) {
3424                 netdev_err(port->dev,
3425                            "invalid configuration: no dt or link IRQ");
3426                 goto err_free_irq;
3427         }
3428
3429         /* Unmask interrupts on all CPUs */
3430         on_each_cpu(mvpp2_interrupts_unmask, port, 1);
3431         mvpp2_shared_interrupt_mask_unmask(port, false);
3432
3433         mvpp2_start_dev(port);
3434
3435         /* Start hardware statistics gathering */
3436         queue_delayed_work(priv->stats_queue, &port->stats_work,
3437                            MVPP2_MIB_COUNTERS_STATS_DELAY);
3438
3439         return 0;
3440
3441 err_free_irq:
3442         mvpp2_irqs_deinit(port);
3443 err_cleanup_txqs:
3444         mvpp2_cleanup_txqs(port);
3445 err_cleanup_rxqs:
3446         mvpp2_cleanup_rxqs(port);
3447         return err;
3448 }
3449
3450 static int mvpp2_stop(struct net_device *dev)
3451 {
3452         struct mvpp2_port *port = netdev_priv(dev);
3453         struct mvpp2_port_pcpu *port_pcpu;
3454         unsigned int thread;
3455
3456         mvpp2_stop_dev(port);
3457
3458         /* Mask interrupts on all threads */
3459         on_each_cpu(mvpp2_interrupts_mask, port, 1);
3460         mvpp2_shared_interrupt_mask_unmask(port, true);
3461
3462         if (port->phylink)
3463                 phylink_disconnect_phy(port->phylink);
3464         if (port->link_irq)
3465                 free_irq(port->link_irq, port);
3466
3467         mvpp2_irqs_deinit(port);
3468         if (!port->has_tx_irqs) {
3469                 for (thread = 0; thread < port->priv->nthreads; thread++) {
3470                         port_pcpu = per_cpu_ptr(port->pcpu, thread);
3471
3472                         hrtimer_cancel(&port_pcpu->tx_done_timer);
3473                         port_pcpu->timer_scheduled = false;
3474                         tasklet_kill(&port_pcpu->tx_done_tasklet);
3475                 }
3476         }
3477         mvpp2_cleanup_rxqs(port);
3478         mvpp2_cleanup_txqs(port);
3479
3480         cancel_delayed_work_sync(&port->stats_work);
3481
3482         return 0;
3483 }
3484
3485 static int mvpp2_prs_mac_da_accept_list(struct mvpp2_port *port,
3486                                         struct netdev_hw_addr_list *list)
3487 {
3488         struct netdev_hw_addr *ha;
3489         int ret;
3490
3491         netdev_hw_addr_list_for_each(ha, list) {
3492                 ret = mvpp2_prs_mac_da_accept(port, ha->addr, true);
3493                 if (ret)
3494                         return ret;
3495         }
3496
3497         return 0;
3498 }
3499
3500 static void mvpp2_set_rx_promisc(struct mvpp2_port *port, bool enable)
3501 {
3502         if (!enable && (port->dev->features & NETIF_F_HW_VLAN_CTAG_FILTER))
3503                 mvpp2_prs_vid_enable_filtering(port);
3504         else
3505                 mvpp2_prs_vid_disable_filtering(port);
3506
3507         mvpp2_prs_mac_promisc_set(port->priv, port->id,
3508                                   MVPP2_PRS_L2_UNI_CAST, enable);
3509
3510         mvpp2_prs_mac_promisc_set(port->priv, port->id,
3511                                   MVPP2_PRS_L2_MULTI_CAST, enable);
3512 }
3513
3514 static void mvpp2_set_rx_mode(struct net_device *dev)
3515 {
3516         struct mvpp2_port *port = netdev_priv(dev);
3517
3518         /* Clear the whole UC and MC list */
3519         mvpp2_prs_mac_del_all(port);
3520
3521         if (dev->flags & IFF_PROMISC) {
3522                 mvpp2_set_rx_promisc(port, true);
3523                 return;
3524         }
3525
3526         mvpp2_set_rx_promisc(port, false);
3527
3528         if (netdev_uc_count(dev) > MVPP2_PRS_MAC_UC_FILT_MAX ||
3529             mvpp2_prs_mac_da_accept_list(port, &dev->uc))
3530                 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3531                                           MVPP2_PRS_L2_UNI_CAST, true);
3532
3533         if (dev->flags & IFF_ALLMULTI) {
3534                 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3535                                           MVPP2_PRS_L2_MULTI_CAST, true);
3536                 return;
3537         }
3538
3539         if (netdev_mc_count(dev) > MVPP2_PRS_MAC_MC_FILT_MAX ||
3540             mvpp2_prs_mac_da_accept_list(port, &dev->mc))
3541                 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3542                                           MVPP2_PRS_L2_MULTI_CAST, true);
3543 }
3544
3545 static int mvpp2_set_mac_address(struct net_device *dev, void *p)
3546 {
3547         const struct sockaddr *addr = p;
3548         int err;
3549
3550         if (!is_valid_ether_addr(addr->sa_data))
3551                 return -EADDRNOTAVAIL;
3552
3553         err = mvpp2_prs_update_mac_da(dev, addr->sa_data);
3554         if (err) {
3555                 /* Reconfigure parser accept the original MAC address */
3556                 mvpp2_prs_update_mac_da(dev, dev->dev_addr);
3557                 netdev_err(dev, "failed to change MAC address\n");
3558         }
3559         return err;
3560 }
3561
3562 static int mvpp2_change_mtu(struct net_device *dev, int mtu)
3563 {
3564         struct mvpp2_port *port = netdev_priv(dev);
3565         int err;
3566
3567         if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) {
3568                 netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu,
3569                             ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8));
3570                 mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8);
3571         }
3572
3573         if (!netif_running(dev)) {
3574                 err = mvpp2_bm_update_mtu(dev, mtu);
3575                 if (!err) {
3576                         port->pkt_size =  MVPP2_RX_PKT_SIZE(mtu);
3577                         return 0;
3578                 }
3579
3580                 /* Reconfigure BM to the original MTU */
3581                 err = mvpp2_bm_update_mtu(dev, dev->mtu);
3582                 if (err)
3583                         goto log_error;
3584         }
3585
3586         mvpp2_stop_dev(port);
3587
3588         err = mvpp2_bm_update_mtu(dev, mtu);
3589         if (!err) {
3590                 port->pkt_size =  MVPP2_RX_PKT_SIZE(mtu);
3591                 goto out_start;
3592         }
3593
3594         /* Reconfigure BM to the original MTU */
3595         err = mvpp2_bm_update_mtu(dev, dev->mtu);
3596         if (err)
3597                 goto log_error;
3598
3599 out_start:
3600         mvpp2_start_dev(port);
3601         mvpp2_egress_enable(port);
3602         mvpp2_ingress_enable(port);
3603
3604         return 0;
3605 log_error:
3606         netdev_err(dev, "failed to change MTU\n");
3607         return err;
3608 }
3609
3610 static void
3611 mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
3612 {
3613         struct mvpp2_port *port = netdev_priv(dev);
3614         unsigned int start;
3615         unsigned int cpu;
3616
3617         for_each_possible_cpu(cpu) {
3618                 struct mvpp2_pcpu_stats *cpu_stats;
3619                 u64 rx_packets;
3620                 u64 rx_bytes;
3621                 u64 tx_packets;
3622                 u64 tx_bytes;
3623
3624                 cpu_stats = per_cpu_ptr(port->stats, cpu);
3625                 do {
3626                         start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
3627                         rx_packets = cpu_stats->rx_packets;
3628                         rx_bytes   = cpu_stats->rx_bytes;
3629                         tx_packets = cpu_stats->tx_packets;
3630                         tx_bytes   = cpu_stats->tx_bytes;
3631                 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
3632
3633                 stats->rx_packets += rx_packets;
3634                 stats->rx_bytes   += rx_bytes;
3635                 stats->tx_packets += tx_packets;
3636                 stats->tx_bytes   += tx_bytes;
3637         }
3638
3639         stats->rx_errors        = dev->stats.rx_errors;
3640         stats->rx_dropped       = dev->stats.rx_dropped;
3641         stats->tx_dropped       = dev->stats.tx_dropped;
3642 }
3643
3644 static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3645 {
3646         struct mvpp2_port *port = netdev_priv(dev);
3647
3648         if (!port->phylink)
3649                 return -ENOTSUPP;
3650
3651         return phylink_mii_ioctl(port->phylink, ifr, cmd);
3652 }
3653
3654 static int mvpp2_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
3655 {
3656         struct mvpp2_port *port = netdev_priv(dev);
3657         int ret;
3658
3659         ret = mvpp2_prs_vid_entry_add(port, vid);
3660         if (ret)
3661                 netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n",
3662                            MVPP2_PRS_VLAN_FILT_MAX - 1);
3663         return ret;
3664 }
3665
3666 static int mvpp2_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
3667 {
3668         struct mvpp2_port *port = netdev_priv(dev);
3669
3670         mvpp2_prs_vid_entry_remove(port, vid);
3671         return 0;
3672 }
3673
3674 static int mvpp2_set_features(struct net_device *dev,
3675                               netdev_features_t features)
3676 {
3677         netdev_features_t changed = dev->features ^ features;
3678         struct mvpp2_port *port = netdev_priv(dev);
3679
3680         if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) {
3681                 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) {
3682                         mvpp2_prs_vid_enable_filtering(port);
3683                 } else {
3684                         /* Invalidate all registered VID filters for this
3685                          * port
3686                          */
3687                         mvpp2_prs_vid_remove_all(port);
3688
3689                         mvpp2_prs_vid_disable_filtering(port);
3690                 }
3691         }
3692
3693         if (changed & NETIF_F_RXHASH) {
3694                 if (features & NETIF_F_RXHASH)
3695                         mvpp22_rss_enable(port);
3696                 else
3697                         mvpp22_rss_disable(port);
3698         }
3699
3700         return 0;
3701 }
3702
3703 /* Ethtool methods */
3704
3705 static int mvpp2_ethtool_nway_reset(struct net_device *dev)
3706 {
3707         struct mvpp2_port *port = netdev_priv(dev);
3708
3709         if (!port->phylink)
3710                 return -ENOTSUPP;
3711
3712         return phylink_ethtool_nway_reset(port->phylink);
3713 }
3714
3715 /* Set interrupt coalescing for ethtools */
3716 static int mvpp2_ethtool_set_coalesce(struct net_device *dev,
3717                                       struct ethtool_coalesce *c)
3718 {
3719         struct mvpp2_port *port = netdev_priv(dev);
3720         int queue;
3721
3722         for (queue = 0; queue < port->nrxqs; queue++) {
3723                 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
3724
3725                 rxq->time_coal = c->rx_coalesce_usecs;
3726                 rxq->pkts_coal = c->rx_max_coalesced_frames;
3727                 mvpp2_rx_pkts_coal_set(port, rxq);
3728                 mvpp2_rx_time_coal_set(port, rxq);
3729         }
3730
3731         if (port->has_tx_irqs) {
3732                 port->tx_time_coal = c->tx_coalesce_usecs;
3733                 mvpp2_tx_time_coal_set(port);
3734         }
3735
3736         for (queue = 0; queue < port->ntxqs; queue++) {
3737                 struct mvpp2_tx_queue *txq = port->txqs[queue];
3738
3739                 txq->done_pkts_coal = c->tx_max_coalesced_frames;
3740
3741                 if (port->has_tx_irqs)
3742                         mvpp2_tx_pkts_coal_set(port, txq);
3743         }
3744
3745         return 0;
3746 }
3747
3748 /* get coalescing for ethtools */
3749 static int mvpp2_ethtool_get_coalesce(struct net_device *dev,
3750                                       struct ethtool_coalesce *c)
3751 {
3752         struct mvpp2_port *port = netdev_priv(dev);
3753
3754         c->rx_coalesce_usecs       = port->rxqs[0]->time_coal;
3755         c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal;
3756         c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal;
3757         c->tx_coalesce_usecs       = port->tx_time_coal;
3758         return 0;
3759 }
3760
3761 static void mvpp2_ethtool_get_drvinfo(struct net_device *dev,
3762                                       struct ethtool_drvinfo *drvinfo)
3763 {
3764         strlcpy(drvinfo->driver, MVPP2_DRIVER_NAME,
3765                 sizeof(drvinfo->driver));
3766         strlcpy(drvinfo->version, MVPP2_DRIVER_VERSION,
3767                 sizeof(drvinfo->version));
3768         strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
3769                 sizeof(drvinfo->bus_info));
3770 }
3771
3772 static void mvpp2_ethtool_get_ringparam(struct net_device *dev,
3773                                         struct ethtool_ringparam *ring)
3774 {
3775         struct mvpp2_port *port = netdev_priv(dev);
3776
3777         ring->rx_max_pending = MVPP2_MAX_RXD_MAX;
3778         ring->tx_max_pending = MVPP2_MAX_TXD_MAX;
3779         ring->rx_pending = port->rx_ring_size;
3780         ring->tx_pending = port->tx_ring_size;
3781 }
3782
3783 static int mvpp2_ethtool_set_ringparam(struct net_device *dev,
3784                                        struct ethtool_ringparam *ring)
3785 {
3786         struct mvpp2_port *port = netdev_priv(dev);
3787         u16 prev_rx_ring_size = port->rx_ring_size;
3788         u16 prev_tx_ring_size = port->tx_ring_size;
3789         int err;
3790
3791         err = mvpp2_check_ringparam_valid(dev, ring);
3792         if (err)
3793                 return err;
3794
3795         if (!netif_running(dev)) {
3796                 port->rx_ring_size = ring->rx_pending;
3797                 port->tx_ring_size = ring->tx_pending;
3798                 return 0;
3799         }
3800
3801         /* The interface is running, so we have to force a
3802          * reallocation of the queues
3803          */
3804         mvpp2_stop_dev(port);
3805         mvpp2_cleanup_rxqs(port);
3806         mvpp2_cleanup_txqs(port);
3807
3808         port->rx_ring_size = ring->rx_pending;
3809         port->tx_ring_size = ring->tx_pending;
3810
3811         err = mvpp2_setup_rxqs(port);
3812         if (err) {
3813                 /* Reallocate Rx queues with the original ring size */
3814                 port->rx_ring_size = prev_rx_ring_size;
3815                 ring->rx_pending = prev_rx_ring_size;
3816                 err = mvpp2_setup_rxqs(port);
3817                 if (err)
3818                         goto err_out;
3819         }
3820         err = mvpp2_setup_txqs(port);
3821         if (err) {
3822                 /* Reallocate Tx queues with the original ring size */
3823                 port->tx_ring_size = prev_tx_ring_size;
3824                 ring->tx_pending = prev_tx_ring_size;
3825                 err = mvpp2_setup_txqs(port);
3826                 if (err)
3827                         goto err_clean_rxqs;
3828         }
3829
3830         mvpp2_start_dev(port);
3831         mvpp2_egress_enable(port);
3832         mvpp2_ingress_enable(port);
3833
3834         return 0;
3835
3836 err_clean_rxqs:
3837         mvpp2_cleanup_rxqs(port);
3838 err_out:
3839         netdev_err(dev, "failed to change ring parameters");
3840         return err;
3841 }
3842
3843 static void mvpp2_ethtool_get_pause_param(struct net_device *dev,
3844                                           struct ethtool_pauseparam *pause)
3845 {
3846         struct mvpp2_port *port = netdev_priv(dev);
3847
3848         if (!port->phylink)
3849                 return;
3850
3851         phylink_ethtool_get_pauseparam(port->phylink, pause);
3852 }
3853
3854 static int mvpp2_ethtool_set_pause_param(struct net_device *dev,
3855                                          struct ethtool_pauseparam *pause)
3856 {
3857         struct mvpp2_port *port = netdev_priv(dev);
3858
3859         if (!port->phylink)
3860                 return -ENOTSUPP;
3861
3862         return phylink_ethtool_set_pauseparam(port->phylink, pause);
3863 }
3864
3865 static int mvpp2_ethtool_get_link_ksettings(struct net_device *dev,
3866                                             struct ethtool_link_ksettings *cmd)
3867 {
3868         struct mvpp2_port *port = netdev_priv(dev);
3869
3870         if (!port->phylink)
3871                 return -ENOTSUPP;
3872
3873         return phylink_ethtool_ksettings_get(port->phylink, cmd);
3874 }
3875
3876 static int mvpp2_ethtool_set_link_ksettings(struct net_device *dev,
3877                                             const struct ethtool_link_ksettings *cmd)
3878 {
3879         struct mvpp2_port *port = netdev_priv(dev);
3880
3881         if (!port->phylink)
3882                 return -ENOTSUPP;
3883
3884         return phylink_ethtool_ksettings_set(port->phylink, cmd);
3885 }
3886
3887 static int mvpp2_ethtool_get_rxnfc(struct net_device *dev,
3888                                    struct ethtool_rxnfc *info, u32 *rules)
3889 {
3890         struct mvpp2_port *port = netdev_priv(dev);
3891         int ret = 0;
3892
3893         if (!mvpp22_rss_is_supported())
3894                 return -EOPNOTSUPP;
3895
3896         switch (info->cmd) {
3897         case ETHTOOL_GRXFH:
3898                 ret = mvpp2_ethtool_rxfh_get(port, info);
3899                 break;
3900         case ETHTOOL_GRXRINGS:
3901                 info->data = port->nrxqs;
3902                 break;
3903         default:
3904                 return -ENOTSUPP;
3905         }
3906
3907         return ret;
3908 }
3909
3910 static int mvpp2_ethtool_set_rxnfc(struct net_device *dev,
3911                                    struct ethtool_rxnfc *info)
3912 {
3913         struct mvpp2_port *port = netdev_priv(dev);
3914         int ret = 0;
3915
3916         if (!mvpp22_rss_is_supported())
3917                 return -EOPNOTSUPP;
3918
3919         switch (info->cmd) {
3920         case ETHTOOL_SRXFH:
3921                 ret = mvpp2_ethtool_rxfh_set(port, info);
3922                 break;
3923         default:
3924                 return -EOPNOTSUPP;
3925         }
3926         return ret;
3927 }
3928
3929 static u32 mvpp2_ethtool_get_rxfh_indir_size(struct net_device *dev)
3930 {
3931         return mvpp22_rss_is_supported() ? MVPP22_RSS_TABLE_ENTRIES : 0;
3932 }
3933
3934 static int mvpp2_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
3935                                   u8 *hfunc)
3936 {
3937         struct mvpp2_port *port = netdev_priv(dev);
3938
3939         if (!mvpp22_rss_is_supported())
3940                 return -EOPNOTSUPP;
3941
3942         if (indir)
3943                 memcpy(indir, port->indir,
3944                        ARRAY_SIZE(port->indir) * sizeof(port->indir[0]));
3945
3946         if (hfunc)
3947                 *hfunc = ETH_RSS_HASH_CRC32;
3948
3949         return 0;
3950 }
3951
3952 static int mvpp2_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,
3953                                   const u8 *key, const u8 hfunc)
3954 {
3955         struct mvpp2_port *port = netdev_priv(dev);
3956
3957         if (!mvpp22_rss_is_supported())
3958                 return -EOPNOTSUPP;
3959
3960         if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32)
3961                 return -EOPNOTSUPP;
3962
3963         if (key)
3964                 return -EOPNOTSUPP;
3965
3966         if (indir) {
3967                 memcpy(port->indir, indir,
3968                        ARRAY_SIZE(port->indir) * sizeof(port->indir[0]));
3969                 mvpp22_rss_fill_table(port, port->id);
3970         }
3971
3972         return 0;
3973 }
3974
3975 /* Device ops */
3976
3977 static const struct net_device_ops mvpp2_netdev_ops = {
3978         .ndo_open               = mvpp2_open,
3979         .ndo_stop               = mvpp2_stop,
3980         .ndo_start_xmit         = mvpp2_tx,
3981         .ndo_set_rx_mode        = mvpp2_set_rx_mode,
3982         .ndo_set_mac_address    = mvpp2_set_mac_address,
3983         .ndo_change_mtu         = mvpp2_change_mtu,
3984         .ndo_get_stats64        = mvpp2_get_stats64,
3985         .ndo_do_ioctl           = mvpp2_ioctl,
3986         .ndo_vlan_rx_add_vid    = mvpp2_vlan_rx_add_vid,
3987         .ndo_vlan_rx_kill_vid   = mvpp2_vlan_rx_kill_vid,
3988         .ndo_set_features       = mvpp2_set_features,
3989 };
3990
3991 static const struct ethtool_ops mvpp2_eth_tool_ops = {
3992         .nway_reset             = mvpp2_ethtool_nway_reset,
3993         .get_link               = ethtool_op_get_link,
3994         .set_coalesce           = mvpp2_ethtool_set_coalesce,
3995         .get_coalesce           = mvpp2_ethtool_get_coalesce,
3996         .get_drvinfo            = mvpp2_ethtool_get_drvinfo,
3997         .get_ringparam          = mvpp2_ethtool_get_ringparam,
3998         .set_ringparam          = mvpp2_ethtool_set_ringparam,
3999         .get_strings            = mvpp2_ethtool_get_strings,
4000         .get_ethtool_stats      = mvpp2_ethtool_get_stats,
4001         .get_sset_count         = mvpp2_ethtool_get_sset_count,
4002         .get_pauseparam         = mvpp2_ethtool_get_pause_param,
4003         .set_pauseparam         = mvpp2_ethtool_set_pause_param,
4004         .get_link_ksettings     = mvpp2_ethtool_get_link_ksettings,
4005         .set_link_ksettings     = mvpp2_ethtool_set_link_ksettings,
4006         .get_rxnfc              = mvpp2_ethtool_get_rxnfc,
4007         .set_rxnfc              = mvpp2_ethtool_set_rxnfc,
4008         .get_rxfh_indir_size    = mvpp2_ethtool_get_rxfh_indir_size,
4009         .get_rxfh               = mvpp2_ethtool_get_rxfh,
4010         .set_rxfh               = mvpp2_ethtool_set_rxfh,
4011
4012 };
4013
4014 /* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that
4015  * had a single IRQ defined per-port.
4016  */
4017 static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port,
4018                                            struct device_node *port_node)
4019 {
4020         struct mvpp2_queue_vector *v = &port->qvecs[0];
4021
4022         v->first_rxq = 0;
4023         v->nrxqs = port->nrxqs;
4024         v->type = MVPP2_QUEUE_VECTOR_SHARED;
4025         v->sw_thread_id = 0;
4026         v->sw_thread_mask = *cpumask_bits(cpu_online_mask);
4027         v->port = port;
4028         v->irq = irq_of_parse_and_map(port_node, 0);
4029         if (v->irq <= 0)
4030                 return -EINVAL;
4031         netif_napi_add(port->dev, &v->napi, mvpp2_poll,
4032                        NAPI_POLL_WEIGHT);
4033
4034         port->nqvecs = 1;
4035
4036         return 0;
4037 }
4038
4039 static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port,
4040                                           struct device_node *port_node)
4041 {
4042         struct mvpp2 *priv = port->priv;
4043         struct mvpp2_queue_vector *v;
4044         int i, ret;
4045
4046         switch (queue_mode) {
4047         case MVPP2_QDIST_SINGLE_MODE:
4048                 port->nqvecs = priv->nthreads + 1;
4049                 break;
4050         case MVPP2_QDIST_MULTI_MODE:
4051                 port->nqvecs = priv->nthreads;
4052                 break;
4053         }
4054
4055         for (i = 0; i < port->nqvecs; i++) {
4056                 char irqname[16];
4057
4058                 v = port->qvecs + i;
4059
4060                 v->port = port;
4061                 v->type = MVPP2_QUEUE_VECTOR_PRIVATE;
4062                 v->sw_thread_id = i;
4063                 v->sw_thread_mask = BIT(i);
4064
4065                 if (port->flags & MVPP2_F_DT_COMPAT)
4066                         snprintf(irqname, sizeof(irqname), "tx-cpu%d", i);
4067                 else
4068                         snprintf(irqname, sizeof(irqname), "hif%d", i);
4069
4070                 if (queue_mode == MVPP2_QDIST_MULTI_MODE) {
4071                         v->first_rxq = i * MVPP2_DEFAULT_RXQ;
4072                         v->nrxqs = MVPP2_DEFAULT_RXQ;
4073                 } else if (queue_mode == MVPP2_QDIST_SINGLE_MODE &&
4074                            i == (port->nqvecs - 1)) {
4075                         v->first_rxq = 0;
4076                         v->nrxqs = port->nrxqs;
4077                         v->type = MVPP2_QUEUE_VECTOR_SHARED;
4078
4079                         if (port->flags & MVPP2_F_DT_COMPAT)
4080                                 strncpy(irqname, "rx-shared", sizeof(irqname));
4081                 }
4082
4083                 if (port_node)
4084                         v->irq = of_irq_get_byname(port_node, irqname);
4085                 else
4086                         v->irq = fwnode_irq_get(port->fwnode, i);
4087                 if (v->irq <= 0) {
4088                         ret = -EINVAL;
4089                         goto err;
4090                 }
4091
4092                 netif_napi_add(port->dev, &v->napi, mvpp2_poll,
4093                                NAPI_POLL_WEIGHT);
4094         }
4095
4096         return 0;
4097
4098 err:
4099         for (i = 0; i < port->nqvecs; i++)
4100                 irq_dispose_mapping(port->qvecs[i].irq);
4101         return ret;
4102 }
4103
4104 static int mvpp2_queue_vectors_init(struct mvpp2_port *port,
4105                                     struct device_node *port_node)
4106 {
4107         if (port->has_tx_irqs)
4108                 return mvpp2_multi_queue_vectors_init(port, port_node);
4109         else
4110                 return mvpp2_simple_queue_vectors_init(port, port_node);
4111 }
4112
4113 static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port)
4114 {
4115         int i;
4116
4117         for (i = 0; i < port->nqvecs; i++)
4118                 irq_dispose_mapping(port->qvecs[i].irq);
4119 }
4120
4121 /* Configure Rx queue group interrupt for this port */
4122 static void mvpp2_rx_irqs_setup(struct mvpp2_port *port)
4123 {
4124         struct mvpp2 *priv = port->priv;
4125         u32 val;
4126         int i;
4127
4128         if (priv->hw_version == MVPP21) {
4129                 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
4130                             port->nrxqs);
4131                 return;
4132         }
4133
4134         /* Handle the more complicated PPv2.2 case */
4135         for (i = 0; i < port->nqvecs; i++) {
4136                 struct mvpp2_queue_vector *qv = port->qvecs + i;
4137
4138                 if (!qv->nrxqs)
4139                         continue;
4140
4141                 val = qv->sw_thread_id;
4142                 val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET;
4143                 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
4144
4145                 val = qv->first_rxq;
4146                 val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET;
4147                 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
4148         }
4149 }
4150
4151 /* Initialize port HW */
4152 static int mvpp2_port_init(struct mvpp2_port *port)
4153 {
4154         struct device *dev = port->dev->dev.parent;
4155         struct mvpp2 *priv = port->priv;
4156         struct mvpp2_txq_pcpu *txq_pcpu;
4157         unsigned int thread;
4158         int queue, err;
4159
4160         /* Checks for hardware constraints */
4161         if (port->first_rxq + port->nrxqs >
4162             MVPP2_MAX_PORTS * priv->max_port_rxqs)
4163                 return -EINVAL;
4164
4165         if (port->nrxqs % MVPP2_DEFAULT_RXQ ||
4166             port->nrxqs > priv->max_port_rxqs || port->ntxqs > MVPP2_MAX_TXQ)
4167                 return -EINVAL;
4168
4169         /* Disable port */
4170         mvpp2_egress_disable(port);
4171         mvpp2_port_disable(port);
4172
4173         port->tx_time_coal = MVPP2_TXDONE_COAL_USEC;
4174
4175         port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs),
4176                                   GFP_KERNEL);
4177         if (!port->txqs)
4178                 return -ENOMEM;
4179
4180         /* Associate physical Tx queues to this port and initialize.
4181          * The mapping is predefined.
4182          */
4183         for (queue = 0; queue < port->ntxqs; queue++) {
4184                 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
4185                 struct mvpp2_tx_queue *txq;
4186
4187                 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
4188                 if (!txq) {
4189                         err = -ENOMEM;
4190                         goto err_free_percpu;
4191                 }
4192
4193                 txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu);
4194                 if (!txq->pcpu) {
4195                         err = -ENOMEM;
4196                         goto err_free_percpu;
4197                 }
4198
4199                 txq->id = queue_phy_id;
4200                 txq->log_id = queue;
4201                 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
4202                 for (thread = 0; thread < priv->nthreads; thread++) {
4203                         txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
4204                         txq_pcpu->thread = thread;
4205                 }
4206
4207                 port->txqs[queue] = txq;
4208         }
4209
4210         port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs),
4211                                   GFP_KERNEL);
4212         if (!port->rxqs) {
4213                 err = -ENOMEM;
4214                 goto err_free_percpu;
4215         }
4216
4217         /* Allocate and initialize Rx queue for this port */
4218         for (queue = 0; queue < port->nrxqs; queue++) {
4219                 struct mvpp2_rx_queue *rxq;
4220
4221                 /* Map physical Rx queue to port's logical Rx queue */
4222                 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
4223                 if (!rxq) {
4224                         err = -ENOMEM;
4225                         goto err_free_percpu;
4226                 }
4227                 /* Map this Rx queue to a physical queue */
4228                 rxq->id = port->first_rxq + queue;
4229                 rxq->port = port->id;
4230                 rxq->logic_rxq = queue;
4231
4232                 port->rxqs[queue] = rxq;
4233         }
4234
4235         mvpp2_rx_irqs_setup(port);
4236
4237         /* Create Rx descriptor rings */
4238         for (queue = 0; queue < port->nrxqs; queue++) {
4239                 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
4240
4241                 rxq->size = port->rx_ring_size;
4242                 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
4243                 rxq->time_coal = MVPP2_RX_COAL_USEC;
4244         }
4245
4246         mvpp2_ingress_disable(port);
4247
4248         /* Port default configuration */
4249         mvpp2_defaults_set(port);
4250
4251         /* Port's classifier configuration */
4252         mvpp2_cls_oversize_rxq_set(port);
4253         mvpp2_cls_port_config(port);
4254
4255         if (mvpp22_rss_is_supported())
4256                 mvpp22_rss_port_init(port);
4257
4258         /* Provide an initial Rx packet size */
4259         port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu);
4260
4261         /* Initialize pools for swf */
4262         err = mvpp2_swf_bm_pool_init(port);
4263         if (err)
4264                 goto err_free_percpu;
4265
4266         return 0;
4267
4268 err_free_percpu:
4269         for (queue = 0; queue < port->ntxqs; queue++) {
4270                 if (!port->txqs[queue])
4271                         continue;
4272                 free_percpu(port->txqs[queue]->pcpu);
4273         }
4274         return err;
4275 }
4276
4277 static bool mvpp22_port_has_legacy_tx_irqs(struct device_node *port_node,
4278                                            unsigned long *flags)
4279 {
4280         char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1", "tx-cpu2",
4281                           "tx-cpu3" };
4282         int i;
4283
4284         for (i = 0; i < 5; i++)
4285                 if (of_property_match_string(port_node, "interrupt-names",
4286                                              irqs[i]) < 0)
4287                         return false;
4288
4289         *flags |= MVPP2_F_DT_COMPAT;
4290         return true;
4291 }
4292
4293 /* Checks if the port dt description has the required Tx interrupts:
4294  * - PPv2.1: there are no such interrupts.
4295  * - PPv2.2:
4296  *   - The old DTs have: "rx-shared", "tx-cpuX" with X in [0...3]
4297  *   - The new ones have: "hifX" with X in [0..8]
4298  *
4299  * All those variants are supported to keep the backward compatibility.
4300  */
4301 static bool mvpp2_port_has_irqs(struct mvpp2 *priv,
4302                                 struct device_node *port_node,
4303                                 unsigned long *flags)
4304 {
4305         char name[5];
4306         int i;
4307
4308         /* ACPI */
4309         if (!port_node)
4310                 return true;
4311
4312         if (priv->hw_version == MVPP21)
4313                 return false;
4314
4315         if (mvpp22_port_has_legacy_tx_irqs(port_node, flags))
4316                 return true;
4317
4318         for (i = 0; i < MVPP2_MAX_THREADS; i++) {
4319                 snprintf(name, 5, "hif%d", i);
4320                 if (of_property_match_string(port_node, "interrupt-names",
4321                                              name) < 0)
4322                         return false;
4323         }
4324
4325         return true;
4326 }
4327
4328 static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv,
4329                                      struct fwnode_handle *fwnode,
4330                                      char **mac_from)
4331 {
4332         struct mvpp2_port *port = netdev_priv(dev);
4333         char hw_mac_addr[ETH_ALEN] = {0};
4334         char fw_mac_addr[ETH_ALEN];
4335
4336         if (fwnode_get_mac_address(fwnode, fw_mac_addr, ETH_ALEN)) {
4337                 *mac_from = "firmware node";
4338                 ether_addr_copy(dev->dev_addr, fw_mac_addr);
4339                 return;
4340         }
4341
4342         if (priv->hw_version == MVPP21) {
4343                 mvpp21_get_mac_address(port, hw_mac_addr);
4344                 if (is_valid_ether_addr(hw_mac_addr)) {
4345                         *mac_from = "hardware";
4346                         ether_addr_copy(dev->dev_addr, hw_mac_addr);
4347                         return;
4348                 }
4349         }
4350
4351         *mac_from = "random";
4352         eth_hw_addr_random(dev);
4353 }
4354
4355 static void mvpp2_phylink_validate(struct net_device *dev,
4356                                    unsigned long *supported,
4357                                    struct phylink_link_state *state)
4358 {
4359         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
4360
4361         phylink_set(mask, Autoneg);
4362         phylink_set_port_modes(mask);
4363         phylink_set(mask, Pause);
4364         phylink_set(mask, Asym_Pause);
4365
4366         switch (state->interface) {
4367         case PHY_INTERFACE_MODE_10GKR:
4368                 phylink_set(mask, 10000baseCR_Full);
4369                 phylink_set(mask, 10000baseSR_Full);
4370                 phylink_set(mask, 10000baseLR_Full);
4371                 phylink_set(mask, 10000baseLRM_Full);
4372                 phylink_set(mask, 10000baseER_Full);
4373                 phylink_set(mask, 10000baseKR_Full);
4374                 /* Fall-through */
4375         default:
4376                 phylink_set(mask, 10baseT_Half);
4377                 phylink_set(mask, 10baseT_Full);
4378                 phylink_set(mask, 100baseT_Half);
4379                 phylink_set(mask, 100baseT_Full);
4380                 phylink_set(mask, 10000baseT_Full);
4381                 /* Fall-through */
4382         case PHY_INTERFACE_MODE_1000BASEX:
4383         case PHY_INTERFACE_MODE_2500BASEX:
4384                 phylink_set(mask, 1000baseT_Full);
4385                 phylink_set(mask, 1000baseX_Full);
4386                 phylink_set(mask, 2500baseX_Full);
4387         }
4388
4389         bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
4390         bitmap_and(state->advertising, state->advertising, mask,
4391                    __ETHTOOL_LINK_MODE_MASK_NBITS);
4392 }
4393
4394 static void mvpp22_xlg_link_state(struct mvpp2_port *port,
4395                                   struct phylink_link_state *state)
4396 {
4397         u32 val;
4398
4399         state->speed = SPEED_10000;
4400         state->duplex = 1;
4401         state->an_complete = 1;
4402
4403         val = readl(port->base + MVPP22_XLG_STATUS);
4404         state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP);
4405
4406         state->pause = 0;
4407         val = readl(port->base + MVPP22_XLG_CTRL0_REG);
4408         if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN)
4409                 state->pause |= MLO_PAUSE_TX;
4410         if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN)
4411                 state->pause |= MLO_PAUSE_RX;
4412 }
4413
4414 static void mvpp2_gmac_link_state(struct mvpp2_port *port,
4415                                   struct phylink_link_state *state)
4416 {
4417         u32 val;
4418
4419         val = readl(port->base + MVPP2_GMAC_STATUS0);
4420
4421         state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE);
4422         state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP);
4423         state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX);
4424
4425         switch (port->phy_interface) {
4426         case PHY_INTERFACE_MODE_1000BASEX:
4427                 state->speed = SPEED_1000;
4428                 break;
4429         case PHY_INTERFACE_MODE_2500BASEX:
4430                 state->speed = SPEED_2500;
4431                 break;
4432         default:
4433                 if (val & MVPP2_GMAC_STATUS0_GMII_SPEED)
4434                         state->speed = SPEED_1000;
4435                 else if (val & MVPP2_GMAC_STATUS0_MII_SPEED)
4436                         state->speed = SPEED_100;
4437                 else
4438                         state->speed = SPEED_10;
4439         }
4440
4441         state->pause = 0;
4442         if (val & MVPP2_GMAC_STATUS0_RX_PAUSE)
4443                 state->pause |= MLO_PAUSE_RX;
4444         if (val & MVPP2_GMAC_STATUS0_TX_PAUSE)
4445                 state->pause |= MLO_PAUSE_TX;
4446 }
4447
4448 static int mvpp2_phylink_mac_link_state(struct net_device *dev,
4449                                         struct phylink_link_state *state)
4450 {
4451         struct mvpp2_port *port = netdev_priv(dev);
4452
4453         if (port->priv->hw_version == MVPP22 && port->gop_id == 0) {
4454                 u32 mode = readl(port->base + MVPP22_XLG_CTRL3_REG);
4455                 mode &= MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
4456
4457                 if (mode == MVPP22_XLG_CTRL3_MACMODESELECT_10G) {
4458                         mvpp22_xlg_link_state(port, state);
4459                         return 1;
4460                 }
4461         }
4462
4463         mvpp2_gmac_link_state(port, state);
4464         return 1;
4465 }
4466
4467 static void mvpp2_mac_an_restart(struct net_device *dev)
4468 {
4469         struct mvpp2_port *port = netdev_priv(dev);
4470         u32 val;
4471
4472         if (port->phy_interface != PHY_INTERFACE_MODE_SGMII)
4473                 return;
4474
4475         val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4476         /* The RESTART_AN bit is cleared by the h/w after restarting the AN
4477          * process.
4478          */
4479         val |= MVPP2_GMAC_IN_BAND_RESTART_AN | MVPP2_GMAC_IN_BAND_AUTONEG;
4480         writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4481 }
4482
4483 static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode,
4484                              const struct phylink_link_state *state)
4485 {
4486         u32 ctrl0, ctrl4;
4487
4488         ctrl0 = readl(port->base + MVPP22_XLG_CTRL0_REG);
4489         ctrl4 = readl(port->base + MVPP22_XLG_CTRL4_REG);
4490
4491         if (state->pause & MLO_PAUSE_TX)
4492                 ctrl0 |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN;
4493         if (state->pause & MLO_PAUSE_RX)
4494                 ctrl0 |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN;
4495
4496         ctrl4 &= ~MVPP22_XLG_CTRL4_MACMODSELECT_GMAC;
4497         ctrl4 |= MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC |
4498                  MVPP22_XLG_CTRL4_EN_IDLE_CHECK;
4499
4500         writel(ctrl0, port->base + MVPP22_XLG_CTRL0_REG);
4501         writel(ctrl4, port->base + MVPP22_XLG_CTRL4_REG);
4502 }
4503
4504 static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
4505                               const struct phylink_link_state *state)
4506 {
4507         u32 an, ctrl0, ctrl2, ctrl4;
4508
4509         an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4510         ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
4511         ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
4512         ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
4513
4514         /* Force link down */
4515         an &= ~MVPP2_GMAC_FORCE_LINK_PASS;
4516         an |= MVPP2_GMAC_FORCE_LINK_DOWN;
4517         writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4518
4519         /* Set the GMAC in a reset state */
4520         ctrl2 |= MVPP2_GMAC_PORT_RESET_MASK;
4521         writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG);
4522
4523         an &= ~(MVPP2_GMAC_CONFIG_MII_SPEED | MVPP2_GMAC_CONFIG_GMII_SPEED |
4524                 MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FC_ADV_EN |
4525                 MVPP2_GMAC_FC_ADV_ASM_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG |
4526                 MVPP2_GMAC_CONFIG_FULL_DUPLEX | MVPP2_GMAC_AN_DUPLEX_EN |
4527                 MVPP2_GMAC_FORCE_LINK_DOWN);
4528         ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK;
4529         ctrl2 &= ~(MVPP2_GMAC_PORT_RESET_MASK | MVPP2_GMAC_PCS_ENABLE_MASK);
4530
4531         if (state->interface == PHY_INTERFACE_MODE_1000BASEX ||
4532             state->interface == PHY_INTERFACE_MODE_2500BASEX) {
4533                 /* 1000BaseX and 2500BaseX ports cannot negotiate speed nor can
4534                  * they negotiate duplex: they are always operating with a fixed
4535                  * speed of 1000/2500Mbps in full duplex, so force 1000/2500
4536                  * speed and full duplex here.
4537                  */
4538                 ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK;
4539                 an |= MVPP2_GMAC_CONFIG_GMII_SPEED |
4540                       MVPP2_GMAC_CONFIG_FULL_DUPLEX;
4541         } else if (!phy_interface_mode_is_rgmii(state->interface)) {
4542                 an |= MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG;
4543         }
4544
4545         if (state->duplex)
4546                 an |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
4547         if (phylink_test(state->advertising, Pause))
4548                 an |= MVPP2_GMAC_FC_ADV_EN;
4549         if (phylink_test(state->advertising, Asym_Pause))
4550                 an |= MVPP2_GMAC_FC_ADV_ASM_EN;
4551
4552         if (state->interface == PHY_INTERFACE_MODE_SGMII ||
4553             state->interface == PHY_INTERFACE_MODE_1000BASEX ||
4554             state->interface == PHY_INTERFACE_MODE_2500BASEX) {
4555                 an |= MVPP2_GMAC_IN_BAND_AUTONEG;
4556                 ctrl2 |= MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK;
4557
4558                 ctrl4 &= ~(MVPP22_CTRL4_EXT_PIN_GMII_SEL |
4559                            MVPP22_CTRL4_RX_FC_EN | MVPP22_CTRL4_TX_FC_EN);
4560                 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS |
4561                          MVPP22_CTRL4_DP_CLK_SEL |
4562                          MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
4563
4564                 if (state->pause & MLO_PAUSE_TX)
4565                         ctrl4 |= MVPP22_CTRL4_TX_FC_EN;
4566                 if (state->pause & MLO_PAUSE_RX)
4567                         ctrl4 |= MVPP22_CTRL4_RX_FC_EN;
4568         } else if (phy_interface_mode_is_rgmii(state->interface)) {
4569                 an |= MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS;
4570
4571                 if (state->speed == SPEED_1000)
4572                         an |= MVPP2_GMAC_CONFIG_GMII_SPEED;
4573                 else if (state->speed == SPEED_100)
4574                         an |= MVPP2_GMAC_CONFIG_MII_SPEED;
4575
4576                 ctrl4 &= ~MVPP22_CTRL4_DP_CLK_SEL;
4577                 ctrl4 |= MVPP22_CTRL4_EXT_PIN_GMII_SEL |
4578                          MVPP22_CTRL4_SYNC_BYPASS_DIS |
4579                          MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
4580         }
4581
4582         writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG);
4583         writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG);
4584         writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG);
4585         writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4586 }
4587
4588 static void mvpp2_mac_config(struct net_device *dev, unsigned int mode,
4589                              const struct phylink_link_state *state)
4590 {
4591         struct mvpp2_port *port = netdev_priv(dev);
4592
4593         /* Check for invalid configuration */
4594         if (state->interface == PHY_INTERFACE_MODE_10GKR && port->gop_id != 0) {
4595                 netdev_err(dev, "Invalid mode on %s\n", dev->name);
4596                 return;
4597         }
4598
4599         /* Make sure the port is disabled when reconfiguring the mode */
4600         mvpp2_port_disable(port);
4601
4602         if (port->priv->hw_version == MVPP22 &&
4603             port->phy_interface != state->interface) {
4604                 port->phy_interface = state->interface;
4605
4606                 /* Reconfigure the serdes lanes */
4607                 phy_power_off(port->comphy);
4608                 mvpp22_mode_reconfigure(port);
4609         }
4610
4611         /* mac (re)configuration */
4612         if (state->interface == PHY_INTERFACE_MODE_10GKR)
4613                 mvpp2_xlg_config(port, mode, state);
4614         else if (phy_interface_mode_is_rgmii(state->interface) ||
4615                  state->interface == PHY_INTERFACE_MODE_SGMII ||
4616                  state->interface == PHY_INTERFACE_MODE_1000BASEX ||
4617                  state->interface == PHY_INTERFACE_MODE_2500BASEX)
4618                 mvpp2_gmac_config(port, mode, state);
4619
4620         if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK)
4621                 mvpp2_port_loopback_set(port, state);
4622
4623         mvpp2_port_enable(port);
4624 }
4625
4626 static void mvpp2_mac_link_up(struct net_device *dev, unsigned int mode,
4627                               phy_interface_t interface, struct phy_device *phy)
4628 {
4629         struct mvpp2_port *port = netdev_priv(dev);
4630         u32 val;
4631
4632         if (!phylink_autoneg_inband(mode) &&
4633             interface != PHY_INTERFACE_MODE_10GKR) {
4634                 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4635                 val &= ~MVPP2_GMAC_FORCE_LINK_DOWN;
4636                 if (phy_interface_mode_is_rgmii(interface))
4637                         val |= MVPP2_GMAC_FORCE_LINK_PASS;
4638                 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4639         }
4640
4641         mvpp2_port_enable(port);
4642
4643         mvpp2_egress_enable(port);
4644         mvpp2_ingress_enable(port);
4645         netif_tx_wake_all_queues(dev);
4646 }
4647
4648 static void mvpp2_mac_link_down(struct net_device *dev, unsigned int mode,
4649                                 phy_interface_t interface)
4650 {
4651         struct mvpp2_port *port = netdev_priv(dev);
4652         u32 val;
4653
4654         if (!phylink_autoneg_inband(mode) &&
4655             interface != PHY_INTERFACE_MODE_10GKR) {
4656                 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4657                 val &= ~MVPP2_GMAC_FORCE_LINK_PASS;
4658                 val |= MVPP2_GMAC_FORCE_LINK_DOWN;
4659                 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4660         }
4661
4662         netif_tx_stop_all_queues(dev);
4663         mvpp2_egress_disable(port);
4664         mvpp2_ingress_disable(port);
4665
4666         /* When using link interrupts to notify phylink of a MAC state change,
4667          * we do not want the port to be disabled (we want to receive further
4668          * interrupts, to be notified when the port will have a link later).
4669          */
4670         if (!port->has_phy)
4671                 return;
4672
4673         mvpp2_port_disable(port);
4674 }
4675
4676 static const struct phylink_mac_ops mvpp2_phylink_ops = {
4677         .validate = mvpp2_phylink_validate,
4678         .mac_link_state = mvpp2_phylink_mac_link_state,
4679         .mac_an_restart = mvpp2_mac_an_restart,
4680         .mac_config = mvpp2_mac_config,
4681         .mac_link_up = mvpp2_mac_link_up,
4682         .mac_link_down = mvpp2_mac_link_down,
4683 };
4684
4685 /* Ports initialization */
4686 static int mvpp2_port_probe(struct platform_device *pdev,
4687                             struct fwnode_handle *port_fwnode,
4688                             struct mvpp2 *priv)
4689 {
4690         struct phy *comphy = NULL;
4691         struct mvpp2_port *port;
4692         struct mvpp2_port_pcpu *port_pcpu;
4693         struct device_node *port_node = to_of_node(port_fwnode);
4694         struct net_device *dev;
4695         struct resource *res;
4696         struct phylink *phylink;
4697         char *mac_from = "";
4698         unsigned int ntxqs, nrxqs, thread;
4699         unsigned long flags = 0;
4700         bool has_tx_irqs;
4701         u32 id;
4702         int features;
4703         int phy_mode;
4704         int err, i;
4705
4706         has_tx_irqs = mvpp2_port_has_irqs(priv, port_node, &flags);
4707         if (!has_tx_irqs && queue_mode == MVPP2_QDIST_MULTI_MODE) {
4708                 dev_err(&pdev->dev,
4709                         "not enough IRQs to support multi queue mode\n");
4710                 return -EINVAL;
4711         }
4712
4713         ntxqs = MVPP2_MAX_TXQ;
4714         if (priv->hw_version == MVPP22 && queue_mode == MVPP2_QDIST_MULTI_MODE)
4715                 nrxqs = MVPP2_DEFAULT_RXQ * num_possible_cpus();
4716         else
4717                 nrxqs = MVPP2_DEFAULT_RXQ;
4718
4719         dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs);
4720         if (!dev)
4721                 return -ENOMEM;
4722
4723         phy_mode = fwnode_get_phy_mode(port_fwnode);
4724         if (phy_mode < 0) {
4725                 dev_err(&pdev->dev, "incorrect phy mode\n");
4726                 err = phy_mode;
4727                 goto err_free_netdev;
4728         }
4729
4730         if (port_node) {
4731                 comphy = devm_of_phy_get(&pdev->dev, port_node, NULL);
4732                 if (IS_ERR(comphy)) {
4733                         if (PTR_ERR(comphy) == -EPROBE_DEFER) {
4734                                 err = -EPROBE_DEFER;
4735                                 goto err_free_netdev;
4736                         }
4737                         comphy = NULL;
4738                 }
4739         }
4740
4741         if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) {
4742                 err = -EINVAL;
4743                 dev_err(&pdev->dev, "missing port-id value\n");
4744                 goto err_free_netdev;
4745         }
4746
4747         dev->tx_queue_len = MVPP2_MAX_TXD_MAX;
4748         dev->watchdog_timeo = 5 * HZ;
4749         dev->netdev_ops = &mvpp2_netdev_ops;
4750         dev->ethtool_ops = &mvpp2_eth_tool_ops;
4751
4752         port = netdev_priv(dev);
4753         port->dev = dev;
4754         port->fwnode = port_fwnode;
4755         port->has_phy = !!of_find_property(port_node, "phy", NULL);
4756         port->ntxqs = ntxqs;
4757         port->nrxqs = nrxqs;
4758         port->priv = priv;
4759         port->has_tx_irqs = has_tx_irqs;
4760         port->flags = flags;
4761
4762         err = mvpp2_queue_vectors_init(port, port_node);
4763         if (err)
4764                 goto err_free_netdev;
4765
4766         if (port_node)
4767                 port->link_irq = of_irq_get_byname(port_node, "link");
4768         else
4769                 port->link_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1);
4770         if (port->link_irq == -EPROBE_DEFER) {
4771                 err = -EPROBE_DEFER;
4772                 goto err_deinit_qvecs;
4773         }
4774         if (port->link_irq <= 0)
4775                 /* the link irq is optional */
4776                 port->link_irq = 0;
4777
4778         if (fwnode_property_read_bool(port_fwnode, "marvell,loopback"))
4779                 port->flags |= MVPP2_F_LOOPBACK;
4780
4781         port->id = id;
4782         if (priv->hw_version == MVPP21)
4783                 port->first_rxq = port->id * port->nrxqs;
4784         else
4785                 port->first_rxq = port->id * priv->max_port_rxqs;
4786
4787         port->of_node = port_node;
4788         port->phy_interface = phy_mode;
4789         port->comphy = comphy;
4790
4791         if (priv->hw_version == MVPP21) {
4792                 res = platform_get_resource(pdev, IORESOURCE_MEM, 2 + id);
4793                 port->base = devm_ioremap_resource(&pdev->dev, res);
4794                 if (IS_ERR(port->base)) {
4795                         err = PTR_ERR(port->base);
4796                         goto err_free_irq;
4797                 }
4798
4799                 port->stats_base = port->priv->lms_base +
4800                                    MVPP21_MIB_COUNTERS_OFFSET +
4801                                    port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ;
4802         } else {
4803                 if (fwnode_property_read_u32(port_fwnode, "gop-port-id",
4804                                              &port->gop_id)) {
4805                         err = -EINVAL;
4806                         dev_err(&pdev->dev, "missing gop-port-id value\n");
4807                         goto err_deinit_qvecs;
4808                 }
4809
4810                 port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id);
4811                 port->stats_base = port->priv->iface_base +
4812                                    MVPP22_MIB_COUNTERS_OFFSET +
4813                                    port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ;
4814         }
4815
4816         /* Alloc per-cpu and ethtool stats */
4817         port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats);
4818         if (!port->stats) {
4819                 err = -ENOMEM;
4820                 goto err_free_irq;
4821         }
4822
4823         port->ethtool_stats = devm_kcalloc(&pdev->dev,
4824                                            ARRAY_SIZE(mvpp2_ethtool_regs),
4825                                            sizeof(u64), GFP_KERNEL);
4826         if (!port->ethtool_stats) {
4827                 err = -ENOMEM;
4828                 goto err_free_stats;
4829         }
4830
4831         mutex_init(&port->gather_stats_lock);
4832         INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics);
4833
4834         mvpp2_port_copy_mac_addr(dev, priv, port_fwnode, &mac_from);
4835
4836         port->tx_ring_size = MVPP2_MAX_TXD_DFLT;
4837         port->rx_ring_size = MVPP2_MAX_RXD_DFLT;
4838         SET_NETDEV_DEV(dev, &pdev->dev);
4839
4840         err = mvpp2_port_init(port);
4841         if (err < 0) {
4842                 dev_err(&pdev->dev, "failed to init port %d\n", id);
4843                 goto err_free_stats;
4844         }
4845
4846         mvpp2_port_periodic_xon_disable(port);
4847
4848         mvpp2_port_reset(port);
4849
4850         port->pcpu = alloc_percpu(struct mvpp2_port_pcpu);
4851         if (!port->pcpu) {
4852                 err = -ENOMEM;
4853                 goto err_free_txq_pcpu;
4854         }
4855
4856         if (!port->has_tx_irqs) {
4857                 for (thread = 0; thread < priv->nthreads; thread++) {
4858                         port_pcpu = per_cpu_ptr(port->pcpu, thread);
4859
4860                         hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC,
4861                                      HRTIMER_MODE_REL_PINNED);
4862                         port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb;
4863                         port_pcpu->timer_scheduled = false;
4864
4865                         tasklet_init(&port_pcpu->tx_done_tasklet,
4866                                      mvpp2_tx_proc_cb,
4867                                      (unsigned long)dev);
4868                 }
4869         }
4870
4871         features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4872                    NETIF_F_TSO;
4873         dev->features = features | NETIF_F_RXCSUM;
4874         dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO |
4875                             NETIF_F_HW_VLAN_CTAG_FILTER;
4876
4877         if (mvpp22_rss_is_supported())
4878                 dev->hw_features |= NETIF_F_RXHASH;
4879
4880         if (port->pool_long->id == MVPP2_BM_JUMBO && port->id != 0) {
4881                 dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
4882                 dev->hw_features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
4883         }
4884
4885         dev->vlan_features |= features;
4886         dev->gso_max_segs = MVPP2_MAX_TSO_SEGS;
4887         dev->priv_flags |= IFF_UNICAST_FLT;
4888
4889         /* MTU range: 68 - 9704 */
4890         dev->min_mtu = ETH_MIN_MTU;
4891         /* 9704 == 9728 - 20 and rounding to 8 */
4892         dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE;
4893         dev->dev.of_node = port_node;
4894
4895         /* Phylink isn't used w/ ACPI as of now */
4896         if (port_node) {
4897                 phylink = phylink_create(dev, port_fwnode, phy_mode,
4898                                          &mvpp2_phylink_ops);
4899                 if (IS_ERR(phylink)) {
4900                         err = PTR_ERR(phylink);
4901                         goto err_free_port_pcpu;
4902                 }
4903                 port->phylink = phylink;
4904         } else {
4905                 port->phylink = NULL;
4906         }
4907
4908         err = register_netdev(dev);
4909         if (err < 0) {
4910                 dev_err(&pdev->dev, "failed to register netdev\n");
4911                 goto err_phylink;
4912         }
4913         netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr);
4914
4915         priv->port_list[priv->port_count++] = port;
4916
4917         return 0;
4918
4919 err_phylink:
4920         if (port->phylink)
4921                 phylink_destroy(port->phylink);
4922 err_free_port_pcpu:
4923         free_percpu(port->pcpu);
4924 err_free_txq_pcpu:
4925         for (i = 0; i < port->ntxqs; i++)
4926                 free_percpu(port->txqs[i]->pcpu);
4927 err_free_stats:
4928         free_percpu(port->stats);
4929 err_free_irq:
4930         if (port->link_irq)
4931                 irq_dispose_mapping(port->link_irq);
4932 err_deinit_qvecs:
4933         mvpp2_queue_vectors_deinit(port);
4934 err_free_netdev:
4935         free_netdev(dev);
4936         return err;
4937 }
4938
4939 /* Ports removal routine */
4940 static void mvpp2_port_remove(struct mvpp2_port *port)
4941 {
4942         int i;
4943
4944         unregister_netdev(port->dev);
4945         if (port->phylink)
4946                 phylink_destroy(port->phylink);
4947         free_percpu(port->pcpu);
4948         free_percpu(port->stats);
4949         for (i = 0; i < port->ntxqs; i++)
4950                 free_percpu(port->txqs[i]->pcpu);
4951         mvpp2_queue_vectors_deinit(port);
4952         if (port->link_irq)
4953                 irq_dispose_mapping(port->link_irq);
4954         free_netdev(port->dev);
4955 }
4956
4957 /* Initialize decoding windows */
4958 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
4959                                     struct mvpp2 *priv)
4960 {
4961         u32 win_enable;
4962         int i;
4963
4964         for (i = 0; i < 6; i++) {
4965                 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
4966                 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
4967
4968                 if (i < 4)
4969                         mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
4970         }
4971
4972         win_enable = 0;
4973
4974         for (i = 0; i < dram->num_cs; i++) {
4975                 const struct mbus_dram_window *cs = dram->cs + i;
4976
4977                 mvpp2_write(priv, MVPP2_WIN_BASE(i),
4978                             (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
4979                             dram->mbus_dram_target_id);
4980
4981                 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
4982                             (cs->size - 1) & 0xffff0000);
4983
4984                 win_enable |= (1 << i);
4985         }
4986
4987         mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
4988 }
4989
4990 /* Initialize Rx FIFO's */
4991 static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
4992 {
4993         int port;
4994
4995         for (port = 0; port < MVPP2_MAX_PORTS; port++) {
4996                 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4997                             MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
4998                 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4999                             MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB);
5000         }
5001
5002         mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
5003                     MVPP2_RX_FIFO_PORT_MIN_PKT);
5004         mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
5005 }
5006
5007 static void mvpp22_rx_fifo_init(struct mvpp2 *priv)
5008 {
5009         int port;
5010
5011         /* The FIFO size parameters are set depending on the maximum speed a
5012          * given port can handle:
5013          * - Port 0: 10Gbps
5014          * - Port 1: 2.5Gbps
5015          * - Ports 2 and 3: 1Gbps
5016          */
5017
5018         mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(0),
5019                     MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB);
5020         mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(0),
5021                     MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB);
5022
5023         mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(1),
5024                     MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB);
5025         mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(1),
5026                     MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB);
5027
5028         for (port = 2; port < MVPP2_MAX_PORTS; port++) {
5029                 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
5030                             MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
5031                 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
5032                             MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB);
5033         }
5034
5035         mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
5036                     MVPP2_RX_FIFO_PORT_MIN_PKT);
5037         mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
5038 }
5039
5040 /* Initialize Tx FIFO's: the total FIFO size is 19kB on PPv2.2 and 10G
5041  * interfaces must have a Tx FIFO size of 10kB. As only port 0 can do 10G,
5042  * configure its Tx FIFO size to 10kB and the others ports Tx FIFO size to 3kB.
5043  */
5044 static void mvpp22_tx_fifo_init(struct mvpp2 *priv)
5045 {
5046         int port, size, thrs;
5047
5048         for (port = 0; port < MVPP2_MAX_PORTS; port++) {
5049                 if (port == 0) {
5050                         size = MVPP22_TX_FIFO_DATA_SIZE_10KB;
5051                         thrs = MVPP2_TX_FIFO_THRESHOLD_10KB;
5052                 } else {
5053                         size = MVPP22_TX_FIFO_DATA_SIZE_3KB;
5054                         thrs = MVPP2_TX_FIFO_THRESHOLD_3KB;
5055                 }
5056                 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size);
5057                 mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), thrs);
5058         }
5059 }
5060
5061 static void mvpp2_axi_init(struct mvpp2 *priv)
5062 {
5063         u32 val, rdval, wrval;
5064
5065         mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
5066
5067         /* AXI Bridge Configuration */
5068
5069         rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
5070                 << MVPP22_AXI_ATTR_CACHE_OFFS;
5071         rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
5072                 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
5073
5074         wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
5075                 << MVPP22_AXI_ATTR_CACHE_OFFS;
5076         wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
5077                 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
5078
5079         /* BM */
5080         mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
5081         mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
5082
5083         /* Descriptors */
5084         mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
5085         mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
5086         mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
5087         mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
5088
5089         /* Buffer Data */
5090         mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
5091         mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
5092
5093         val = MVPP22_AXI_CODE_CACHE_NON_CACHE
5094                 << MVPP22_AXI_CODE_CACHE_OFFS;
5095         val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
5096                 << MVPP22_AXI_CODE_DOMAIN_OFFS;
5097         mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
5098         mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
5099
5100         val = MVPP22_AXI_CODE_CACHE_RD_CACHE
5101                 << MVPP22_AXI_CODE_CACHE_OFFS;
5102         val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
5103                 << MVPP22_AXI_CODE_DOMAIN_OFFS;
5104
5105         mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
5106
5107         val = MVPP22_AXI_CODE_CACHE_WR_CACHE
5108                 << MVPP22_AXI_CODE_CACHE_OFFS;
5109         val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
5110                 << MVPP22_AXI_CODE_DOMAIN_OFFS;
5111
5112         mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
5113 }
5114
5115 /* Initialize network controller common part HW */
5116 static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
5117 {
5118         const struct mbus_dram_target_info *dram_target_info;
5119         int err, i;
5120         u32 val;
5121
5122         /* MBUS windows configuration */
5123         dram_target_info = mv_mbus_dram_info();
5124         if (dram_target_info)
5125                 mvpp2_conf_mbus_windows(dram_target_info, priv);
5126
5127         if (priv->hw_version == MVPP22)
5128                 mvpp2_axi_init(priv);
5129
5130         /* Disable HW PHY polling */
5131         if (priv->hw_version == MVPP21) {
5132                 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
5133                 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
5134                 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
5135         } else {
5136                 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
5137                 val &= ~MVPP22_SMI_POLLING_EN;
5138                 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
5139         }
5140
5141         /* Allocate and initialize aggregated TXQs */
5142         priv->aggr_txqs = devm_kcalloc(&pdev->dev, MVPP2_MAX_THREADS,
5143                                        sizeof(*priv->aggr_txqs),
5144                                        GFP_KERNEL);
5145         if (!priv->aggr_txqs)
5146                 return -ENOMEM;
5147
5148         for (i = 0; i < MVPP2_MAX_THREADS; i++) {
5149                 priv->aggr_txqs[i].id = i;
5150                 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
5151                 err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv);
5152                 if (err < 0)
5153                         return err;
5154         }
5155
5156         /* Fifo Init */
5157         if (priv->hw_version == MVPP21) {
5158                 mvpp2_rx_fifo_init(priv);
5159         } else {
5160                 mvpp22_rx_fifo_init(priv);
5161                 mvpp22_tx_fifo_init(priv);
5162         }
5163
5164         if (priv->hw_version == MVPP21)
5165                 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
5166                        priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
5167
5168         /* Allow cache snoop when transmiting packets */
5169         mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
5170
5171         /* Buffer Manager initialization */
5172         err = mvpp2_bm_init(pdev, priv);
5173         if (err < 0)
5174                 return err;
5175
5176         /* Parser default initialization */
5177         err = mvpp2_prs_default_init(pdev, priv);
5178         if (err < 0)
5179                 return err;
5180
5181         /* Classifier default initialization */
5182         mvpp2_cls_init(priv);
5183
5184         return 0;
5185 }
5186
5187 static int mvpp2_probe(struct platform_device *pdev)
5188 {
5189         const struct acpi_device_id *acpi_id;
5190         struct fwnode_handle *fwnode = pdev->dev.fwnode;
5191         struct fwnode_handle *port_fwnode;
5192         struct mvpp2 *priv;
5193         struct resource *res;
5194         void __iomem *base;
5195         int i, shared;
5196         int err;
5197
5198         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
5199         if (!priv)
5200                 return -ENOMEM;
5201
5202         if (has_acpi_companion(&pdev->dev)) {
5203                 acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
5204                                             &pdev->dev);
5205                 priv->hw_version = (unsigned long)acpi_id->driver_data;
5206         } else {
5207                 priv->hw_version =
5208                         (unsigned long)of_device_get_match_data(&pdev->dev);
5209         }
5210
5211         /* multi queue mode isn't supported on PPV2.1, fallback to single
5212          * mode
5213          */
5214         if (priv->hw_version == MVPP21)
5215                 queue_mode = MVPP2_QDIST_SINGLE_MODE;
5216
5217         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5218         base = devm_ioremap_resource(&pdev->dev, res);
5219         if (IS_ERR(base))
5220                 return PTR_ERR(base);
5221
5222         if (priv->hw_version == MVPP21) {
5223                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
5224                 priv->lms_base = devm_ioremap_resource(&pdev->dev, res);
5225                 if (IS_ERR(priv->lms_base))
5226                         return PTR_ERR(priv->lms_base);
5227         } else {
5228                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
5229                 if (has_acpi_companion(&pdev->dev)) {
5230                         /* In case the MDIO memory region is declared in
5231                          * the ACPI, it can already appear as 'in-use'
5232                          * in the OS. Because it is overlapped by second
5233                          * region of the network controller, make
5234                          * sure it is released, before requesting it again.
5235                          * The care is taken by mvpp2 driver to avoid
5236                          * concurrent access to this memory region.
5237                          */
5238                         release_resource(res);
5239                 }
5240                 priv->iface_base = devm_ioremap_resource(&pdev->dev, res);
5241                 if (IS_ERR(priv->iface_base))
5242                         return PTR_ERR(priv->iface_base);
5243         }
5244
5245         if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) {
5246                 priv->sysctrl_base =
5247                         syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
5248                                                         "marvell,system-controller");
5249                 if (IS_ERR(priv->sysctrl_base))
5250                         /* The system controller regmap is optional for dt
5251                          * compatibility reasons. When not provided, the
5252                          * configuration of the GoP relies on the
5253                          * firmware/bootloader.
5254                          */
5255                         priv->sysctrl_base = NULL;
5256         }
5257
5258         mvpp2_setup_bm_pool();
5259
5260
5261         priv->nthreads = min_t(unsigned int, num_present_cpus(),
5262                                MVPP2_MAX_THREADS);
5263
5264         shared = num_present_cpus() - priv->nthreads;
5265         if (shared > 0)
5266                 bitmap_fill(&priv->lock_map,
5267                             min_t(int, shared, MVPP2_MAX_THREADS));
5268
5269         for (i = 0; i < MVPP2_MAX_THREADS; i++) {
5270                 u32 addr_space_sz;
5271
5272                 addr_space_sz = (priv->hw_version == MVPP21 ?
5273                                  MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ);
5274                 priv->swth_base[i] = base + i * addr_space_sz;
5275         }
5276
5277         if (priv->hw_version == MVPP21)
5278                 priv->max_port_rxqs = 8;
5279         else
5280                 priv->max_port_rxqs = 32;
5281
5282         if (dev_of_node(&pdev->dev)) {
5283                 priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk");
5284                 if (IS_ERR(priv->pp_clk))
5285                         return PTR_ERR(priv->pp_clk);
5286                 err = clk_prepare_enable(priv->pp_clk);
5287                 if (err < 0)
5288                         return err;
5289
5290                 priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk");
5291                 if (IS_ERR(priv->gop_clk)) {
5292                         err = PTR_ERR(priv->gop_clk);
5293                         goto err_pp_clk;
5294                 }
5295                 err = clk_prepare_enable(priv->gop_clk);
5296                 if (err < 0)
5297                         goto err_pp_clk;
5298
5299                 if (priv->hw_version == MVPP22) {
5300                         priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk");
5301                         if (IS_ERR(priv->mg_clk)) {
5302                                 err = PTR_ERR(priv->mg_clk);
5303                                 goto err_gop_clk;
5304                         }
5305
5306                         err = clk_prepare_enable(priv->mg_clk);
5307                         if (err < 0)
5308                                 goto err_gop_clk;
5309
5310                         priv->mg_core_clk = devm_clk_get(&pdev->dev, "mg_core_clk");
5311                         if (IS_ERR(priv->mg_core_clk)) {
5312                                 priv->mg_core_clk = NULL;
5313                         } else {
5314                                 err = clk_prepare_enable(priv->mg_core_clk);
5315                                 if (err < 0)
5316                                         goto err_mg_clk;
5317                         }
5318                 }
5319
5320                 priv->axi_clk = devm_clk_get(&pdev->dev, "axi_clk");
5321                 if (IS_ERR(priv->axi_clk)) {
5322                         err = PTR_ERR(priv->axi_clk);
5323                         if (err == -EPROBE_DEFER)
5324                                 goto err_mg_core_clk;
5325                         priv->axi_clk = NULL;
5326                 } else {
5327                         err = clk_prepare_enable(priv->axi_clk);
5328                         if (err < 0)
5329                                 goto err_mg_core_clk;
5330                 }
5331
5332                 /* Get system's tclk rate */
5333                 priv->tclk = clk_get_rate(priv->pp_clk);
5334         } else if (device_property_read_u32(&pdev->dev, "clock-frequency",
5335                                             &priv->tclk)) {
5336                 dev_err(&pdev->dev, "missing clock-frequency value\n");
5337                 return -EINVAL;
5338         }
5339
5340         if (priv->hw_version == MVPP22) {
5341                 err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK);
5342                 if (err)
5343                         goto err_axi_clk;
5344                 /* Sadly, the BM pools all share the same register to
5345                  * store the high 32 bits of their address. So they
5346                  * must all have the same high 32 bits, which forces
5347                  * us to restrict coherent memory to DMA_BIT_MASK(32).
5348                  */
5349                 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
5350                 if (err)
5351                         goto err_axi_clk;
5352         }
5353
5354         /* Initialize network controller */
5355         err = mvpp2_init(pdev, priv);
5356         if (err < 0) {
5357                 dev_err(&pdev->dev, "failed to initialize controller\n");
5358                 goto err_axi_clk;
5359         }
5360
5361         /* Initialize ports */
5362         fwnode_for_each_available_child_node(fwnode, port_fwnode) {
5363                 err = mvpp2_port_probe(pdev, port_fwnode, priv);
5364                 if (err < 0)
5365                         goto err_port_probe;
5366         }
5367
5368         if (priv->port_count == 0) {
5369                 dev_err(&pdev->dev, "no ports enabled\n");
5370                 err = -ENODEV;
5371                 goto err_axi_clk;
5372         }
5373
5374         /* Statistics must be gathered regularly because some of them (like
5375          * packets counters) are 32-bit registers and could overflow quite
5376          * quickly. For instance, a 10Gb link used at full bandwidth with the
5377          * smallest packets (64B) will overflow a 32-bit counter in less than
5378          * 30 seconds. Then, use a workqueue to fill 64-bit counters.
5379          */
5380         snprintf(priv->queue_name, sizeof(priv->queue_name),
5381                  "stats-wq-%s%s", netdev_name(priv->port_list[0]->dev),
5382                  priv->port_count > 1 ? "+" : "");
5383         priv->stats_queue = create_singlethread_workqueue(priv->queue_name);
5384         if (!priv->stats_queue) {
5385                 err = -ENOMEM;
5386                 goto err_port_probe;
5387         }
5388
5389         mvpp2_dbgfs_init(priv, pdev->name);
5390
5391         platform_set_drvdata(pdev, priv);
5392         return 0;
5393
5394 err_port_probe:
5395         i = 0;
5396         fwnode_for_each_available_child_node(fwnode, port_fwnode) {
5397                 if (priv->port_list[i])
5398                         mvpp2_port_remove(priv->port_list[i]);
5399                 i++;
5400         }
5401 err_axi_clk:
5402         clk_disable_unprepare(priv->axi_clk);
5403
5404 err_mg_core_clk:
5405         if (priv->hw_version == MVPP22)
5406                 clk_disable_unprepare(priv->mg_core_clk);
5407 err_mg_clk:
5408         if (priv->hw_version == MVPP22)
5409                 clk_disable_unprepare(priv->mg_clk);
5410 err_gop_clk:
5411         clk_disable_unprepare(priv->gop_clk);
5412 err_pp_clk:
5413         clk_disable_unprepare(priv->pp_clk);
5414         return err;
5415 }
5416
5417 static int mvpp2_remove(struct platform_device *pdev)
5418 {
5419         struct mvpp2 *priv = platform_get_drvdata(pdev);
5420         struct fwnode_handle *fwnode = pdev->dev.fwnode;
5421         struct fwnode_handle *port_fwnode;
5422         int i = 0;
5423
5424         mvpp2_dbgfs_cleanup(priv);
5425
5426         flush_workqueue(priv->stats_queue);
5427         destroy_workqueue(priv->stats_queue);
5428
5429         fwnode_for_each_available_child_node(fwnode, port_fwnode) {
5430                 if (priv->port_list[i]) {
5431                         mutex_destroy(&priv->port_list[i]->gather_stats_lock);
5432                         mvpp2_port_remove(priv->port_list[i]);
5433                 }
5434                 i++;
5435         }
5436
5437         for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
5438                 struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i];
5439
5440                 mvpp2_bm_pool_destroy(pdev, priv, bm_pool);
5441         }
5442
5443         for (i = 0; i < MVPP2_MAX_THREADS; i++) {
5444                 struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i];
5445
5446                 dma_free_coherent(&pdev->dev,
5447                                   MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
5448                                   aggr_txq->descs,
5449                                   aggr_txq->descs_dma);
5450         }
5451
5452         if (is_acpi_node(port_fwnode))
5453                 return 0;
5454
5455         clk_disable_unprepare(priv->axi_clk);
5456         clk_disable_unprepare(priv->mg_core_clk);
5457         clk_disable_unprepare(priv->mg_clk);
5458         clk_disable_unprepare(priv->pp_clk);
5459         clk_disable_unprepare(priv->gop_clk);
5460
5461         return 0;
5462 }
5463
5464 static const struct of_device_id mvpp2_match[] = {
5465         {
5466                 .compatible = "marvell,armada-375-pp2",
5467                 .data = (void *)MVPP21,
5468         },
5469         {
5470                 .compatible = "marvell,armada-7k-pp22",
5471                 .data = (void *)MVPP22,
5472         },
5473         { }
5474 };
5475 MODULE_DEVICE_TABLE(of, mvpp2_match);
5476
5477 static const struct acpi_device_id mvpp2_acpi_match[] = {
5478         { "MRVL0110", MVPP22 },
5479         { },
5480 };
5481 MODULE_DEVICE_TABLE(acpi, mvpp2_acpi_match);
5482
5483 static struct platform_driver mvpp2_driver = {
5484         .probe = mvpp2_probe,
5485         .remove = mvpp2_remove,
5486         .driver = {
5487                 .name = MVPP2_DRIVER_NAME,
5488                 .of_match_table = mvpp2_match,
5489                 .acpi_match_table = ACPI_PTR(mvpp2_acpi_match),
5490         },
5491 };
5492
5493 module_platform_driver(mvpp2_driver);
5494
5495 MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com");
5496 MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>");
5497 MODULE_LICENSE("GPL v2");