2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
4 * Copyright (C) 2012 Marvell
6 * Rami Rosen <rosenr@marvell.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/clk.h>
15 #include <linux/cpu.h>
16 #include <linux/etherdevice.h>
17 #include <linux/if_vlan.h>
18 #include <linux/inetdevice.h>
19 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/mbus.h>
23 #include <linux/module.h>
24 #include <linux/netdevice.h>
26 #include <linux/of_address.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_mdio.h>
29 #include <linux/of_net.h>
30 #include <linux/phy/phy.h>
31 #include <linux/phy.h>
32 #include <linux/phylink.h>
33 #include <linux/platform_device.h>
34 #include <linux/skbuff.h>
36 #include "mvneta_bm.h"
40 #include <net/page_pool.h>
41 #include <linux/bpf_trace.h>
44 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
45 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0)
46 #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4
47 #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30
48 #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6
49 #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0
50 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
51 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
52 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
53 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
54 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
55 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
56 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
57 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
58 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
59 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
60 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
61 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
62 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
63 #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2))
64 #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3
65 #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8
66 #define MVNETA_PORT_RX_RESET 0x1cc0
67 #define MVNETA_PORT_RX_DMA_RESET BIT(0)
68 #define MVNETA_PHY_ADDR 0x2000
69 #define MVNETA_PHY_ADDR_MASK 0x1f
70 #define MVNETA_MBUS_RETRY 0x2010
71 #define MVNETA_UNIT_INTR_CAUSE 0x2080
72 #define MVNETA_UNIT_CONTROL 0x20B0
73 #define MVNETA_PHY_POLLING_ENABLE BIT(1)
74 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
75 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
76 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
77 #define MVNETA_BASE_ADDR_ENABLE 0x2290
78 #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294
79 #define MVNETA_PORT_CONFIG 0x2400
80 #define MVNETA_UNI_PROMISC_MODE BIT(0)
81 #define MVNETA_DEF_RXQ(q) ((q) << 1)
82 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
83 #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
84 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
85 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
86 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
87 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
88 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
89 MVNETA_DEF_RXQ_ARP(q) | \
90 MVNETA_DEF_RXQ_TCP(q) | \
91 MVNETA_DEF_RXQ_UDP(q) | \
92 MVNETA_DEF_RXQ_BPDU(q) | \
93 MVNETA_TX_UNSET_ERR_SUM | \
94 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
95 #define MVNETA_PORT_CONFIG_EXTEND 0x2404
96 #define MVNETA_MAC_ADDR_LOW 0x2414
97 #define MVNETA_MAC_ADDR_HIGH 0x2418
98 #define MVNETA_SDMA_CONFIG 0x241c
99 #define MVNETA_SDMA_BRST_SIZE_16 4
100 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
101 #define MVNETA_RX_NO_DATA_SWAP BIT(4)
102 #define MVNETA_TX_NO_DATA_SWAP BIT(5)
103 #define MVNETA_DESC_SWAP BIT(6)
104 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
105 #define MVNETA_PORT_STATUS 0x2444
106 #define MVNETA_TX_IN_PRGRS BIT(1)
107 #define MVNETA_TX_FIFO_EMPTY BIT(8)
108 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
109 #define MVNETA_SERDES_CFG 0x24A0
110 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
111 #define MVNETA_QSGMII_SERDES_PROTO 0x0667
112 #define MVNETA_TYPE_PRIO 0x24bc
113 #define MVNETA_FORCE_UNI BIT(21)
114 #define MVNETA_TXQ_CMD_1 0x24e4
115 #define MVNETA_TXQ_CMD 0x2448
116 #define MVNETA_TXQ_DISABLE_SHIFT 8
117 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
118 #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484
119 #define MVNETA_OVERRUN_FRAME_COUNT 0x2488
120 #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4
121 #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31)
122 #define MVNETA_ACC_MODE 0x2500
123 #define MVNETA_BM_ADDRESS 0x2504
124 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
125 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
126 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
127 #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq)
128 #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8)
129 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
131 /* Exception Interrupt Port/Queue Cause register
133 * Their behavior depend of the mapping done using the PCPX2Q
134 * registers. For a given CPU if the bit associated to a queue is not
135 * set, then for the register a read from this CPU will always return
136 * 0 and a write won't do anything
139 #define MVNETA_INTR_NEW_CAUSE 0x25a0
140 #define MVNETA_INTR_NEW_MASK 0x25a4
142 /* bits 0..7 = TXQ SENT, one bit per queue.
143 * bits 8..15 = RXQ OCCUP, one bit per queue.
144 * bits 16..23 = RXQ FREE, one bit per queue.
145 * bit 29 = OLD_REG_SUM, see old reg ?
146 * bit 30 = TX_ERR_SUM, one bit for 4 ports
147 * bit 31 = MISC_SUM, one bit for 4 ports
149 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
150 #define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
151 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
152 #define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
153 #define MVNETA_MISCINTR_INTR_MASK BIT(31)
155 #define MVNETA_INTR_OLD_CAUSE 0x25a8
156 #define MVNETA_INTR_OLD_MASK 0x25ac
158 /* Data Path Port/Queue Cause Register */
159 #define MVNETA_INTR_MISC_CAUSE 0x25b0
160 #define MVNETA_INTR_MISC_MASK 0x25b4
162 #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0)
163 #define MVNETA_CAUSE_LINK_CHANGE BIT(1)
164 #define MVNETA_CAUSE_PTP BIT(4)
166 #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7)
167 #define MVNETA_CAUSE_RX_OVERRUN BIT(8)
168 #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9)
169 #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10)
170 #define MVNETA_CAUSE_TX_UNDERUN BIT(11)
171 #define MVNETA_CAUSE_PRBS_ERR BIT(12)
172 #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13)
173 #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14)
175 #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16
176 #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT)
177 #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool)))
179 #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24
180 #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT)
181 #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q)))
183 #define MVNETA_INTR_ENABLE 0x25b8
184 #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00
185 #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff
187 #define MVNETA_RXQ_CMD 0x2680
188 #define MVNETA_RXQ_DISABLE_SHIFT 8
189 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
190 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
191 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
192 #define MVNETA_GMAC_CTRL_0 0x2c00
193 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
194 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
195 #define MVNETA_GMAC0_PORT_1000BASE_X BIT(1)
196 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
197 #define MVNETA_GMAC_CTRL_2 0x2c08
198 #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0)
199 #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
200 #define MVNETA_GMAC2_PORT_RGMII BIT(4)
201 #define MVNETA_GMAC2_PORT_RESET BIT(6)
202 #define MVNETA_GMAC_STATUS 0x2c10
203 #define MVNETA_GMAC_LINK_UP BIT(0)
204 #define MVNETA_GMAC_SPEED_1000 BIT(1)
205 #define MVNETA_GMAC_SPEED_100 BIT(2)
206 #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
207 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
208 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
209 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
210 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
211 #define MVNETA_GMAC_AN_COMPLETE BIT(11)
212 #define MVNETA_GMAC_SYNC_OK BIT(14)
213 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
214 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
215 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
216 #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2)
217 #define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3)
218 #define MVNETA_GMAC_INBAND_RESTART_AN BIT(4)
219 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
220 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
221 #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
222 #define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8)
223 #define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9)
224 #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11)
225 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
226 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
227 #define MVNETA_GMAC_CTRL_4 0x2c90
228 #define MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE BIT(1)
229 #define MVNETA_MIB_COUNTERS_BASE 0x3000
230 #define MVNETA_MIB_LATE_COLLISION 0x7c
231 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
232 #define MVNETA_DA_FILT_OTH_MCAST 0x3500
233 #define MVNETA_DA_FILT_UCAST_BASE 0x3600
234 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
235 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
236 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
237 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
238 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
239 #define MVNETA_TXQ_DEC_SENT_SHIFT 16
240 #define MVNETA_TXQ_DEC_SENT_MASK 0xff
241 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
242 #define MVNETA_TXQ_SENT_DESC_SHIFT 16
243 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
244 #define MVNETA_PORT_TX_RESET 0x3cf0
245 #define MVNETA_PORT_TX_DMA_RESET BIT(0)
246 #define MVNETA_TX_MTU 0x3e0c
247 #define MVNETA_TX_TOKEN_SIZE 0x3e14
248 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
249 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
250 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
252 #define MVNETA_LPI_CTRL_0 0x2cc0
253 #define MVNETA_LPI_CTRL_1 0x2cc4
254 #define MVNETA_LPI_REQUEST_ENABLE BIT(0)
255 #define MVNETA_LPI_CTRL_2 0x2cc8
256 #define MVNETA_LPI_STATUS 0x2ccc
258 #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
260 /* Descriptor ring Macros */
261 #define MVNETA_QUEUE_NEXT_DESC(q, index) \
262 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
264 /* Various constants */
267 #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */
268 #define MVNETA_RX_COAL_PKTS 32
269 #define MVNETA_RX_COAL_USEC 100
271 /* The two bytes Marvell header. Either contains a special value used
272 * by Marvell switches when a specific hardware mode is enabled (not
273 * supported by this driver) or is filled automatically by zeroes on
274 * the RX side. Those two bytes being at the front of the Ethernet
275 * header, they allow to have the IP header aligned on a 4 bytes
276 * boundary automatically: the hardware skips those two bytes on its
279 #define MVNETA_MH_SIZE 2
281 #define MVNETA_VLAN_TAG_LEN 4
283 #define MVNETA_TX_CSUM_DEF_SIZE 1600
284 #define MVNETA_TX_CSUM_MAX_SIZE 9800
285 #define MVNETA_ACC_MODE_EXT1 1
286 #define MVNETA_ACC_MODE_EXT2 2
288 #define MVNETA_MAX_DECODE_WIN 6
290 /* Timeout constants */
291 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
292 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
293 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
295 #define MVNETA_TX_MTU_MAX 0x3ffff
297 /* The RSS lookup table actually has 256 entries but we do not use
300 #define MVNETA_RSS_LU_TABLE_SIZE 1
302 /* Max number of Rx descriptors */
303 #define MVNETA_MAX_RXD 512
305 /* Max number of Tx descriptors */
306 #define MVNETA_MAX_TXD 1024
308 /* Max number of allowed TCP segments for software TSO */
309 #define MVNETA_MAX_TSO_SEGS 100
311 #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
313 /* descriptor aligned size */
314 #define MVNETA_DESC_ALIGNED_SIZE 32
316 /* Number of bytes to be taken into account by HW when putting incoming data
317 * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet
318 * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers.
320 #define MVNETA_RX_PKT_OFFSET_CORRECTION 64
322 #define MVNETA_RX_PKT_SIZE(mtu) \
323 ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
324 ETH_HLEN + ETH_FCS_LEN, \
327 /* Driver assumes that the last 3 bits are 0 */
328 #define MVNETA_SKB_HEADROOM ALIGN(max(NET_SKB_PAD, XDP_PACKET_HEADROOM), 8)
329 #define MVNETA_SKB_PAD (SKB_DATA_ALIGN(sizeof(struct skb_shared_info) + \
330 MVNETA_SKB_HEADROOM))
331 #define MVNETA_SKB_SIZE(len) (SKB_DATA_ALIGN(len) + MVNETA_SKB_PAD)
332 #define MVNETA_MAX_RX_BUF_SIZE (PAGE_SIZE - MVNETA_SKB_PAD)
334 #define IS_TSO_HEADER(txq, addr) \
335 ((addr >= txq->tso_hdrs_phys) && \
336 (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE))
338 #define MVNETA_RX_GET_BM_POOL_ID(rxd) \
339 (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT)
342 ETHTOOL_STAT_EEE_WAKEUP,
343 ETHTOOL_STAT_SKB_ALLOC_ERR,
344 ETHTOOL_STAT_REFILL_ERR,
345 ETHTOOL_XDP_REDIRECT,
351 ETHTOOL_XDP_XMIT_ERR,
355 struct mvneta_statistic {
356 unsigned short offset;
358 const char name[ETH_GSTRING_LEN];
365 #define MVNETA_XDP_PASS 0
366 #define MVNETA_XDP_DROPPED BIT(0)
367 #define MVNETA_XDP_TX BIT(1)
368 #define MVNETA_XDP_REDIR BIT(2)
370 static const struct mvneta_statistic mvneta_statistics[] = {
371 { 0x3000, T_REG_64, "good_octets_received", },
372 { 0x3010, T_REG_32, "good_frames_received", },
373 { 0x3008, T_REG_32, "bad_octets_received", },
374 { 0x3014, T_REG_32, "bad_frames_received", },
375 { 0x3018, T_REG_32, "broadcast_frames_received", },
376 { 0x301c, T_REG_32, "multicast_frames_received", },
377 { 0x3050, T_REG_32, "unrec_mac_control_received", },
378 { 0x3058, T_REG_32, "good_fc_received", },
379 { 0x305c, T_REG_32, "bad_fc_received", },
380 { 0x3060, T_REG_32, "undersize_received", },
381 { 0x3064, T_REG_32, "fragments_received", },
382 { 0x3068, T_REG_32, "oversize_received", },
383 { 0x306c, T_REG_32, "jabber_received", },
384 { 0x3070, T_REG_32, "mac_receive_error", },
385 { 0x3074, T_REG_32, "bad_crc_event", },
386 { 0x3078, T_REG_32, "collision", },
387 { 0x307c, T_REG_32, "late_collision", },
388 { 0x2484, T_REG_32, "rx_discard", },
389 { 0x2488, T_REG_32, "rx_overrun", },
390 { 0x3020, T_REG_32, "frames_64_octets", },
391 { 0x3024, T_REG_32, "frames_65_to_127_octets", },
392 { 0x3028, T_REG_32, "frames_128_to_255_octets", },
393 { 0x302c, T_REG_32, "frames_256_to_511_octets", },
394 { 0x3030, T_REG_32, "frames_512_to_1023_octets", },
395 { 0x3034, T_REG_32, "frames_1024_to_max_octets", },
396 { 0x3038, T_REG_64, "good_octets_sent", },
397 { 0x3040, T_REG_32, "good_frames_sent", },
398 { 0x3044, T_REG_32, "excessive_collision", },
399 { 0x3048, T_REG_32, "multicast_frames_sent", },
400 { 0x304c, T_REG_32, "broadcast_frames_sent", },
401 { 0x3054, T_REG_32, "fc_sent", },
402 { 0x300c, T_REG_32, "internal_mac_transmit_err", },
403 { ETHTOOL_STAT_EEE_WAKEUP, T_SW, "eee_wakeup_errors", },
404 { ETHTOOL_STAT_SKB_ALLOC_ERR, T_SW, "skb_alloc_errors", },
405 { ETHTOOL_STAT_REFILL_ERR, T_SW, "refill_errors", },
406 { ETHTOOL_XDP_REDIRECT, T_SW, "rx_xdp_redirect", },
407 { ETHTOOL_XDP_PASS, T_SW, "rx_xdp_pass", },
408 { ETHTOOL_XDP_DROP, T_SW, "rx_xdp_drop", },
409 { ETHTOOL_XDP_TX, T_SW, "rx_xdp_tx", },
410 { ETHTOOL_XDP_TX_ERR, T_SW, "rx_xdp_tx_errors", },
411 { ETHTOOL_XDP_XMIT, T_SW, "tx_xdp_xmit", },
412 { ETHTOOL_XDP_XMIT_ERR, T_SW, "tx_xdp_xmit_errors", },
415 struct mvneta_stats {
430 struct mvneta_ethtool_stats {
431 struct mvneta_stats ps;
436 struct mvneta_pcpu_stats {
437 struct u64_stats_sync syncp;
439 struct mvneta_ethtool_stats es;
444 struct mvneta_pcpu_port {
445 /* Pointer to the shared port */
446 struct mvneta_port *pp;
448 /* Pointer to the CPU-local NAPI struct */
449 struct napi_struct napi;
451 /* Cause of the previous interrupt */
461 struct mvneta_pcpu_port __percpu *ports;
462 struct mvneta_pcpu_stats __percpu *stats;
468 struct mvneta_rx_queue *rxqs;
469 struct mvneta_tx_queue *txqs;
470 struct net_device *dev;
471 struct hlist_node node_online;
472 struct hlist_node node_dead;
474 /* Protect the access to the percpu interrupt registers,
475 * ensuring that the configuration remains coherent.
481 struct napi_struct napi;
483 struct bpf_prog *xdp_prog;
493 phy_interface_t phy_interface;
494 struct device_node *dn;
495 unsigned int tx_csum_limit;
496 struct phylink *phylink;
497 struct phylink_config phylink_config;
500 struct mvneta_bm *bm_priv;
501 struct mvneta_bm_pool *pool_long;
502 struct mvneta_bm_pool *pool_short;
509 u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
511 u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
513 /* Flags for special SoC configurations */
514 bool neta_armada3700;
515 u16 rx_offset_correction;
516 const struct mbus_dram_target_info *dram_target_info;
519 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
520 * layout of the transmit and reception DMA descriptors, and their
521 * layout is therefore defined by the hardware design
524 #define MVNETA_TX_L3_OFF_SHIFT 0
525 #define MVNETA_TX_IP_HLEN_SHIFT 8
526 #define MVNETA_TX_L4_UDP BIT(16)
527 #define MVNETA_TX_L3_IP6 BIT(17)
528 #define MVNETA_TXD_IP_CSUM BIT(18)
529 #define MVNETA_TXD_Z_PAD BIT(19)
530 #define MVNETA_TXD_L_DESC BIT(20)
531 #define MVNETA_TXD_F_DESC BIT(21)
532 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
533 MVNETA_TXD_L_DESC | \
535 #define MVNETA_TX_L4_CSUM_FULL BIT(30)
536 #define MVNETA_TX_L4_CSUM_NOT BIT(31)
538 #define MVNETA_RXD_ERR_CRC 0x0
539 #define MVNETA_RXD_BM_POOL_SHIFT 13
540 #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14))
541 #define MVNETA_RXD_ERR_SUMMARY BIT(16)
542 #define MVNETA_RXD_ERR_OVERRUN BIT(17)
543 #define MVNETA_RXD_ERR_LEN BIT(18)
544 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
545 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
546 #define MVNETA_RXD_L3_IP4 BIT(25)
547 #define MVNETA_RXD_LAST_DESC BIT(26)
548 #define MVNETA_RXD_FIRST_DESC BIT(27)
549 #define MVNETA_RXD_FIRST_LAST_DESC (MVNETA_RXD_FIRST_DESC | \
550 MVNETA_RXD_LAST_DESC)
551 #define MVNETA_RXD_L4_CSUM_OK BIT(30)
553 #if defined(__LITTLE_ENDIAN)
554 struct mvneta_tx_desc {
555 u32 command; /* Options used by HW for packet transmitting.*/
556 u16 reserved1; /* csum_l4 (for future use) */
557 u16 data_size; /* Data size of transmitted packet in bytes */
558 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
559 u32 reserved2; /* hw_cmd - (for future use, PMT) */
560 u32 reserved3[4]; /* Reserved - (for future use) */
563 struct mvneta_rx_desc {
564 u32 status; /* Info about received packet */
565 u16 reserved1; /* pnc_info - (for future use, PnC) */
566 u16 data_size; /* Size of received packet in bytes */
568 u32 buf_phys_addr; /* Physical address of the buffer */
569 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
571 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
572 u16 reserved3; /* prefetch_cmd, for future use */
573 u16 reserved4; /* csum_l4 - (for future use, PnC) */
575 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
576 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
579 struct mvneta_tx_desc {
580 u16 data_size; /* Data size of transmitted packet in bytes */
581 u16 reserved1; /* csum_l4 (for future use) */
582 u32 command; /* Options used by HW for packet transmitting.*/
583 u32 reserved2; /* hw_cmd - (for future use, PMT) */
584 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
585 u32 reserved3[4]; /* Reserved - (for future use) */
588 struct mvneta_rx_desc {
589 u16 data_size; /* Size of received packet in bytes */
590 u16 reserved1; /* pnc_info - (for future use, PnC) */
591 u32 status; /* Info about received packet */
593 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
594 u32 buf_phys_addr; /* Physical address of the buffer */
596 u16 reserved4; /* csum_l4 - (for future use, PnC) */
597 u16 reserved3; /* prefetch_cmd, for future use */
598 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
600 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
601 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
605 enum mvneta_tx_buf_type {
611 struct mvneta_tx_buf {
612 enum mvneta_tx_buf_type type;
614 struct xdp_frame *xdpf;
619 struct mvneta_tx_queue {
620 /* Number of this TX queue, in the range 0-7 */
623 /* Number of TX DMA descriptors in the descriptor ring */
626 /* Number of currently used TX DMA descriptor in the
631 int tx_stop_threshold;
632 int tx_wake_threshold;
634 /* Array of transmitted buffers */
635 struct mvneta_tx_buf *buf;
637 /* Index of last TX DMA descriptor that was inserted */
640 /* Index of the TX DMA descriptor to be cleaned up */
645 /* Virtual address of the TX DMA descriptors array */
646 struct mvneta_tx_desc *descs;
648 /* DMA address of the TX DMA descriptors array */
649 dma_addr_t descs_phys;
651 /* Index of the last TX DMA descriptor */
654 /* Index of the next TX DMA descriptor to process */
655 int next_desc_to_proc;
657 /* DMA buffers for TSO headers */
660 /* DMA address of TSO headers */
661 dma_addr_t tso_hdrs_phys;
663 /* Affinity mask for CPUs*/
664 cpumask_t affinity_mask;
667 struct mvneta_rx_queue {
668 /* rx queue number, in the range 0-7 */
671 /* num of rx descriptors in the rx descriptor ring */
678 struct page_pool *page_pool;
679 struct xdp_rxq_info xdp_rxq;
681 /* Virtual address of the RX buffer */
682 void **buf_virt_addr;
684 /* Virtual address of the RX DMA descriptors array */
685 struct mvneta_rx_desc *descs;
687 /* DMA address of the RX DMA descriptors array */
688 dma_addr_t descs_phys;
690 /* Index of the last RX DMA descriptor */
693 /* Index of the next RX DMA descriptor to process */
694 int next_desc_to_proc;
696 /* Index of first RX DMA descriptor to refill */
700 /* pointer to uncomplete skb buffer */
705 static enum cpuhp_state online_hpstate;
706 /* The hardware supports eight (8) rx queues, but we are only allowing
707 * the first one to be used. Therefore, let's just allocate one queue.
709 static int rxq_number = 8;
710 static int txq_number = 8;
714 static int rx_copybreak __read_mostly = 256;
716 /* HW BM need that each port be identify by a unique ID */
717 static int global_port_id;
719 #define MVNETA_DRIVER_NAME "mvneta"
720 #define MVNETA_DRIVER_VERSION "1.0"
722 /* Utility/helper methods */
724 /* Write helper method */
725 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
727 writel(data, pp->base + offset);
730 /* Read helper method */
731 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
733 return readl(pp->base + offset);
736 /* Increment txq get counter */
737 static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq)
739 txq->txq_get_index++;
740 if (txq->txq_get_index == txq->size)
741 txq->txq_get_index = 0;
744 /* Increment txq put counter */
745 static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq)
747 txq->txq_put_index++;
748 if (txq->txq_put_index == txq->size)
749 txq->txq_put_index = 0;
753 /* Clear all MIB counters */
754 static void mvneta_mib_counters_clear(struct mvneta_port *pp)
759 /* Perform dummy reads from MIB counters */
760 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
761 dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
762 dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT);
763 dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT);
766 /* Get System Network Statistics */
768 mvneta_get_stats64(struct net_device *dev,
769 struct rtnl_link_stats64 *stats)
771 struct mvneta_port *pp = netdev_priv(dev);
775 for_each_possible_cpu(cpu) {
776 struct mvneta_pcpu_stats *cpu_stats;
784 cpu_stats = per_cpu_ptr(pp->stats, cpu);
786 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
787 rx_packets = cpu_stats->es.ps.rx_packets;
788 rx_bytes = cpu_stats->es.ps.rx_bytes;
789 rx_dropped = cpu_stats->rx_dropped;
790 rx_errors = cpu_stats->rx_errors;
791 tx_packets = cpu_stats->es.ps.tx_packets;
792 tx_bytes = cpu_stats->es.ps.tx_bytes;
793 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
795 stats->rx_packets += rx_packets;
796 stats->rx_bytes += rx_bytes;
797 stats->rx_dropped += rx_dropped;
798 stats->rx_errors += rx_errors;
799 stats->tx_packets += tx_packets;
800 stats->tx_bytes += tx_bytes;
803 stats->tx_dropped = dev->stats.tx_dropped;
806 /* Rx descriptors helper methods */
808 /* Checks whether the RX descriptor having this status is both the first
809 * and the last descriptor for the RX packet. Each RX packet is currently
810 * received through a single RX descriptor, so not having each RX
811 * descriptor with its first and last bits set is an error
813 static int mvneta_rxq_desc_is_first_last(u32 status)
815 return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
816 MVNETA_RXD_FIRST_LAST_DESC;
819 /* Add number of descriptors ready to receive new packets */
820 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
821 struct mvneta_rx_queue *rxq,
824 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
827 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
828 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
829 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
830 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
831 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
834 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
835 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
838 /* Get number of RX descriptors occupied by received packets */
839 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
840 struct mvneta_rx_queue *rxq)
844 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
845 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
848 /* Update num of rx desc called upon return from rx path or
849 * from mvneta_rxq_drop_pkts().
851 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
852 struct mvneta_rx_queue *rxq,
853 int rx_done, int rx_filled)
857 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
859 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
860 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
864 /* Only 255 descriptors can be added at once */
865 while ((rx_done > 0) || (rx_filled > 0)) {
866 if (rx_done <= 0xff) {
873 if (rx_filled <= 0xff) {
874 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
877 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
880 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
884 /* Get pointer to next RX descriptor to be processed by SW */
885 static struct mvneta_rx_desc *
886 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
888 int rx_desc = rxq->next_desc_to_proc;
890 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
891 prefetch(rxq->descs + rxq->next_desc_to_proc);
892 return rxq->descs + rx_desc;
895 /* Change maximum receive size of the port. */
896 static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size)
900 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
901 val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK;
902 val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) <<
903 MVNETA_GMAC_MAX_RX_SIZE_SHIFT;
904 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
908 /* Set rx queue offset */
909 static void mvneta_rxq_offset_set(struct mvneta_port *pp,
910 struct mvneta_rx_queue *rxq,
915 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
916 val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK;
919 val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3);
920 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
924 /* Tx descriptors helper methods */
926 /* Update HW with number of TX descriptors to be sent */
927 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
928 struct mvneta_tx_queue *txq,
933 pend_desc += txq->pending;
935 /* Only 255 Tx descriptors can be added at once */
937 val = min(pend_desc, 255);
938 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
940 } while (pend_desc > 0);
944 /* Get pointer to next TX descriptor to be processed (send) by HW */
945 static struct mvneta_tx_desc *
946 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
948 int tx_desc = txq->next_desc_to_proc;
950 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
951 return txq->descs + tx_desc;
954 /* Release the last allocated TX descriptor. Useful to handle DMA
955 * mapping failures in the TX path.
957 static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq)
959 if (txq->next_desc_to_proc == 0)
960 txq->next_desc_to_proc = txq->last_desc - 1;
962 txq->next_desc_to_proc--;
965 /* Set rxq buf size */
966 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
967 struct mvneta_rx_queue *rxq,
972 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
974 val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
975 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
977 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
980 /* Disable buffer management (BM) */
981 static void mvneta_rxq_bm_disable(struct mvneta_port *pp,
982 struct mvneta_rx_queue *rxq)
986 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
987 val &= ~MVNETA_RXQ_HW_BUF_ALLOC;
988 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
991 /* Enable buffer management (BM) */
992 static void mvneta_rxq_bm_enable(struct mvneta_port *pp,
993 struct mvneta_rx_queue *rxq)
997 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
998 val |= MVNETA_RXQ_HW_BUF_ALLOC;
999 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
1002 /* Notify HW about port's assignment of pool for bigger packets */
1003 static void mvneta_rxq_long_pool_set(struct mvneta_port *pp,
1004 struct mvneta_rx_queue *rxq)
1008 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
1009 val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK;
1010 val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT);
1012 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
1015 /* Notify HW about port's assignment of pool for smaller packets */
1016 static void mvneta_rxq_short_pool_set(struct mvneta_port *pp,
1017 struct mvneta_rx_queue *rxq)
1021 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
1022 val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK;
1023 val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT);
1025 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
1028 /* Set port's receive buffer size for assigned BM pool */
1029 static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp,
1035 if (!IS_ALIGNED(buf_size, 8)) {
1036 dev_warn(pp->dev->dev.parent,
1037 "illegal buf_size value %d, round to %d\n",
1038 buf_size, ALIGN(buf_size, 8));
1039 buf_size = ALIGN(buf_size, 8);
1042 val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id));
1043 val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK;
1044 mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val);
1047 /* Configure MBUS window in order to enable access BM internal SRAM */
1048 static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize,
1051 u32 win_enable, win_protect;
1054 win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE);
1056 if (pp->bm_win_id < 0) {
1057 /* Find first not occupied window */
1058 for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) {
1059 if (win_enable & (1 << i)) {
1064 if (i == MVNETA_MAX_DECODE_WIN)
1070 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
1071 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
1074 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
1076 mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) |
1077 (attr << 8) | target);
1079 mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000);
1081 win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE);
1082 win_protect |= 3 << (2 * i);
1083 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
1085 win_enable &= ~(1 << i);
1086 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
1091 static int mvneta_bm_port_mbus_init(struct mvneta_port *pp)
1097 /* Get BM window information */
1098 err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize,
1105 /* Open NETA -> BM window */
1106 err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize,
1109 netdev_info(pp->dev, "fail to configure mbus window to BM\n");
1115 /* Assign and initialize pools for port. In case of fail
1116 * buffer manager will remain disabled for current port.
1118 static int mvneta_bm_port_init(struct platform_device *pdev,
1119 struct mvneta_port *pp)
1121 struct device_node *dn = pdev->dev.of_node;
1122 u32 long_pool_id, short_pool_id;
1124 if (!pp->neta_armada3700) {
1127 ret = mvneta_bm_port_mbus_init(pp);
1132 if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) {
1133 netdev_info(pp->dev, "missing long pool id\n");
1137 /* Create port's long pool depending on mtu */
1138 pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id,
1139 MVNETA_BM_LONG, pp->id,
1140 MVNETA_RX_PKT_SIZE(pp->dev->mtu));
1141 if (!pp->pool_long) {
1142 netdev_info(pp->dev, "fail to obtain long pool for port\n");
1146 pp->pool_long->port_map |= 1 << pp->id;
1148 mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size,
1151 /* If short pool id is not defined, assume using single pool */
1152 if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id))
1153 short_pool_id = long_pool_id;
1155 /* Create port's short pool */
1156 pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id,
1157 MVNETA_BM_SHORT, pp->id,
1158 MVNETA_BM_SHORT_PKT_SIZE);
1159 if (!pp->pool_short) {
1160 netdev_info(pp->dev, "fail to obtain short pool for port\n");
1161 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
1165 if (short_pool_id != long_pool_id) {
1166 pp->pool_short->port_map |= 1 << pp->id;
1167 mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size,
1168 pp->pool_short->id);
1174 /* Update settings of a pool for bigger packets */
1175 static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu)
1177 struct mvneta_bm_pool *bm_pool = pp->pool_long;
1178 struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool;
1181 /* Release all buffers from long pool */
1182 mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id);
1183 if (hwbm_pool->buf_num) {
1184 WARN(1, "cannot free all buffers in pool %d\n",
1189 bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu);
1190 bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size);
1191 hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
1192 SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size));
1194 /* Fill entire long pool */
1195 num = hwbm_pool_add(hwbm_pool, hwbm_pool->size);
1196 if (num != hwbm_pool->size) {
1197 WARN(1, "pool %d: %d of %d allocated\n",
1198 bm_pool->id, num, hwbm_pool->size);
1201 mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id);
1206 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
1207 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id);
1210 pp->rx_offset_correction = MVNETA_SKB_HEADROOM;
1211 mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1);
1212 netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n");
1215 /* Start the Ethernet port RX and TX activity */
1216 static void mvneta_port_up(struct mvneta_port *pp)
1221 /* Enable all initialized TXs. */
1223 for (queue = 0; queue < txq_number; queue++) {
1224 struct mvneta_tx_queue *txq = &pp->txqs[queue];
1226 q_map |= (1 << queue);
1228 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
1231 /* Enable all initialized RXQs. */
1232 for (queue = 0; queue < rxq_number; queue++) {
1233 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
1236 q_map |= (1 << queue);
1238 mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
1241 /* Stop the Ethernet port activity */
1242 static void mvneta_port_down(struct mvneta_port *pp)
1247 /* Stop Rx port activity. Check port Rx activity. */
1248 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
1250 /* Issue stop command for active channels only */
1252 mvreg_write(pp, MVNETA_RXQ_CMD,
1253 val << MVNETA_RXQ_DISABLE_SHIFT);
1255 /* Wait for all Rx activity to terminate. */
1258 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
1259 netdev_warn(pp->dev,
1260 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n",
1266 val = mvreg_read(pp, MVNETA_RXQ_CMD);
1267 } while (val & MVNETA_RXQ_ENABLE_MASK);
1269 /* Stop Tx port activity. Check port Tx activity. Issue stop
1270 * command for active channels only
1272 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
1275 mvreg_write(pp, MVNETA_TXQ_CMD,
1276 (val << MVNETA_TXQ_DISABLE_SHIFT));
1278 /* Wait for all Tx activity to terminate. */
1281 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
1282 netdev_warn(pp->dev,
1283 "TIMEOUT for TX stopped status=0x%08x\n",
1289 /* Check TX Command reg that all Txqs are stopped */
1290 val = mvreg_read(pp, MVNETA_TXQ_CMD);
1292 } while (val & MVNETA_TXQ_ENABLE_MASK);
1294 /* Double check to verify that TX FIFO is empty */
1297 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
1298 netdev_warn(pp->dev,
1299 "TX FIFO empty timeout status=0x%08x\n",
1305 val = mvreg_read(pp, MVNETA_PORT_STATUS);
1306 } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
1307 (val & MVNETA_TX_IN_PRGRS));
1312 /* Enable the port by setting the port enable bit of the MAC control register */
1313 static void mvneta_port_enable(struct mvneta_port *pp)
1318 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
1319 val |= MVNETA_GMAC0_PORT_ENABLE;
1320 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
1323 /* Disable the port and wait for about 200 usec before retuning */
1324 static void mvneta_port_disable(struct mvneta_port *pp)
1328 /* Reset the Enable bit in the Serial Control Register */
1329 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
1330 val &= ~MVNETA_GMAC0_PORT_ENABLE;
1331 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
1336 /* Multicast tables methods */
1338 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
1339 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
1347 val = 0x1 | (queue << 1);
1348 val |= (val << 24) | (val << 16) | (val << 8);
1351 for (offset = 0; offset <= 0xc; offset += 4)
1352 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
1355 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
1356 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
1364 val = 0x1 | (queue << 1);
1365 val |= (val << 24) | (val << 16) | (val << 8);
1368 for (offset = 0; offset <= 0xfc; offset += 4)
1369 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
1373 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
1374 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
1380 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
1383 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
1384 val = 0x1 | (queue << 1);
1385 val |= (val << 24) | (val << 16) | (val << 8);
1388 for (offset = 0; offset <= 0xfc; offset += 4)
1389 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
1392 static void mvneta_percpu_unmask_interrupt(void *arg)
1394 struct mvneta_port *pp = arg;
1396 /* All the queue are unmasked, but actually only the ones
1397 * mapped to this CPU will be unmasked
1399 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
1400 MVNETA_RX_INTR_MASK_ALL |
1401 MVNETA_TX_INTR_MASK_ALL |
1402 MVNETA_MISCINTR_INTR_MASK);
1405 static void mvneta_percpu_mask_interrupt(void *arg)
1407 struct mvneta_port *pp = arg;
1409 /* All the queue are masked, but actually only the ones
1410 * mapped to this CPU will be masked
1412 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
1413 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
1414 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
1417 static void mvneta_percpu_clear_intr_cause(void *arg)
1419 struct mvneta_port *pp = arg;
1421 /* All the queue are cleared, but actually only the ones
1422 * mapped to this CPU will be cleared
1424 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
1425 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
1426 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
1429 /* This method sets defaults to the NETA port:
1430 * Clears interrupt Cause and Mask registers.
1431 * Clears all MAC tables.
1432 * Sets defaults to all registers.
1433 * Resets RX and TX descriptor rings.
1435 * This method can be called after mvneta_port_down() to return the port
1436 * settings to defaults.
1438 static void mvneta_defaults_set(struct mvneta_port *pp)
1443 int max_cpu = num_present_cpus();
1445 /* Clear all Cause registers */
1446 on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
1448 /* Mask all interrupts */
1449 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
1450 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
1452 /* Enable MBUS Retry bit16 */
1453 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
1455 /* Set CPU queue access map. CPUs are assigned to the RX and
1456 * TX queues modulo their number. If there is only one TX
1457 * queue then it is assigned to the CPU associated to the
1460 for_each_present_cpu(cpu) {
1461 int rxq_map = 0, txq_map = 0;
1463 if (!pp->neta_armada3700) {
1464 for (rxq = 0; rxq < rxq_number; rxq++)
1465 if ((rxq % max_cpu) == cpu)
1466 rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
1468 for (txq = 0; txq < txq_number; txq++)
1469 if ((txq % max_cpu) == cpu)
1470 txq_map |= MVNETA_CPU_TXQ_ACCESS(txq);
1472 /* With only one TX queue we configure a special case
1473 * which will allow to get all the irq on a single
1476 if (txq_number == 1)
1477 txq_map = (cpu == pp->rxq_def) ?
1478 MVNETA_CPU_TXQ_ACCESS(1) : 0;
1481 txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
1482 rxq_map = MVNETA_CPU_RXQ_ACCESS_ALL_MASK;
1485 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
1488 /* Reset RX and TX DMAs */
1489 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
1490 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
1492 /* Disable Legacy WRR, Disable EJP, Release from reset */
1493 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
1494 for (queue = 0; queue < txq_number; queue++) {
1495 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
1496 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
1499 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
1500 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
1502 /* Set Port Acceleration Mode */
1504 /* HW buffer management + legacy parser */
1505 val = MVNETA_ACC_MODE_EXT2;
1507 /* SW buffer management + legacy parser */
1508 val = MVNETA_ACC_MODE_EXT1;
1509 mvreg_write(pp, MVNETA_ACC_MODE, val);
1512 mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr);
1514 /* Update val of portCfg register accordingly with all RxQueue types */
1515 val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def);
1516 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
1519 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
1520 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
1522 /* Build PORT_SDMA_CONFIG_REG */
1525 /* Default burst size */
1526 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
1527 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
1528 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
1530 #if defined(__BIG_ENDIAN)
1531 val |= MVNETA_DESC_SWAP;
1534 /* Assign port SDMA configuration */
1535 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
1537 /* Disable PHY polling in hardware, since we're using the
1538 * kernel phylib to do this.
1540 val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
1541 val &= ~MVNETA_PHY_POLLING_ENABLE;
1542 mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
1544 mvneta_set_ucast_table(pp, -1);
1545 mvneta_set_special_mcast_table(pp, -1);
1546 mvneta_set_other_mcast_table(pp, -1);
1548 /* Set port interrupt enable register - default enable all */
1549 mvreg_write(pp, MVNETA_INTR_ENABLE,
1550 (MVNETA_RXQ_INTR_ENABLE_ALL_MASK
1551 | MVNETA_TXQ_INTR_ENABLE_ALL_MASK));
1553 mvneta_mib_counters_clear(pp);
1556 /* Set max sizes for tx queues */
1557 static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size)
1563 mtu = max_tx_size * 8;
1564 if (mtu > MVNETA_TX_MTU_MAX)
1565 mtu = MVNETA_TX_MTU_MAX;
1568 val = mvreg_read(pp, MVNETA_TX_MTU);
1569 val &= ~MVNETA_TX_MTU_MAX;
1571 mvreg_write(pp, MVNETA_TX_MTU, val);
1573 /* TX token size and all TXQs token size must be larger that MTU */
1574 val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE);
1576 size = val & MVNETA_TX_TOKEN_SIZE_MAX;
1579 val &= ~MVNETA_TX_TOKEN_SIZE_MAX;
1581 mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val);
1583 for (queue = 0; queue < txq_number; queue++) {
1584 val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue));
1586 size = val & MVNETA_TXQ_TOKEN_SIZE_MAX;
1589 val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX;
1591 mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val);
1596 /* Set unicast address */
1597 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
1600 unsigned int unicast_reg;
1601 unsigned int tbl_offset;
1602 unsigned int reg_offset;
1604 /* Locate the Unicast table entry */
1605 last_nibble = (0xf & last_nibble);
1607 /* offset from unicast tbl base */
1608 tbl_offset = (last_nibble / 4) * 4;
1610 /* offset within the above reg */
1611 reg_offset = last_nibble % 4;
1613 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
1616 /* Clear accepts frame bit at specified unicast DA tbl entry */
1617 unicast_reg &= ~(0xff << (8 * reg_offset));
1619 unicast_reg &= ~(0xff << (8 * reg_offset));
1620 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1623 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
1626 /* Set mac address */
1627 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
1634 mac_l = (addr[4] << 8) | (addr[5]);
1635 mac_h = (addr[0] << 24) | (addr[1] << 16) |
1636 (addr[2] << 8) | (addr[3] << 0);
1638 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
1639 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
1642 /* Accept frames of this address */
1643 mvneta_set_ucast_addr(pp, addr[5], queue);
1646 /* Set the number of packets that will be received before RX interrupt
1647 * will be generated by HW.
1649 static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp,
1650 struct mvneta_rx_queue *rxq, u32 value)
1652 mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id),
1653 value | MVNETA_RXQ_NON_OCCUPIED(0));
1656 /* Set the time delay in usec before RX interrupt will be generated by
1659 static void mvneta_rx_time_coal_set(struct mvneta_port *pp,
1660 struct mvneta_rx_queue *rxq, u32 value)
1663 unsigned long clk_rate;
1665 clk_rate = clk_get_rate(pp->clk);
1666 val = (clk_rate / 1000000) * value;
1668 mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);
1671 /* Set threshold for TX_DONE pkts coalescing */
1672 static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp,
1673 struct mvneta_tx_queue *txq, u32 value)
1677 val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id));
1679 val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK;
1680 val |= MVNETA_TXQ_SENT_THRESH_MASK(value);
1682 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val);
1685 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
1686 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
1687 u32 phys_addr, void *virt_addr,
1688 struct mvneta_rx_queue *rxq)
1692 rx_desc->buf_phys_addr = phys_addr;
1693 i = rx_desc - rxq->descs;
1694 rxq->buf_virt_addr[i] = virt_addr;
1697 /* Decrement sent descriptors counter */
1698 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
1699 struct mvneta_tx_queue *txq,
1704 /* Only 255 TX descriptors can be updated at once */
1705 while (sent_desc > 0xff) {
1706 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
1707 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1708 sent_desc = sent_desc - 0xff;
1711 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
1712 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1715 /* Get number of TX descriptors already sent by HW */
1716 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
1717 struct mvneta_tx_queue *txq)
1722 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
1723 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
1724 MVNETA_TXQ_SENT_DESC_SHIFT;
1729 /* Get number of sent descriptors and decrement counter.
1730 * The number of sent descriptors is returned.
1732 static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp,
1733 struct mvneta_tx_queue *txq)
1737 /* Get number of sent descriptors */
1738 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1740 /* Decrement sent descriptors counter */
1742 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
1747 /* Set TXQ descriptors fields relevant for CSUM calculation */
1748 static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto,
1749 int ip_hdr_len, int l4_proto)
1753 /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1754 * G_L4_chk, L4_type; required only for checksum
1757 command = l3_offs << MVNETA_TX_L3_OFF_SHIFT;
1758 command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT;
1760 if (l3_proto == htons(ETH_P_IP))
1761 command |= MVNETA_TXD_IP_CSUM;
1763 command |= MVNETA_TX_L3_IP6;
1765 if (l4_proto == IPPROTO_TCP)
1766 command |= MVNETA_TX_L4_CSUM_FULL;
1767 else if (l4_proto == IPPROTO_UDP)
1768 command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL;
1770 command |= MVNETA_TX_L4_CSUM_NOT;
1776 /* Display more error info */
1777 static void mvneta_rx_error(struct mvneta_port *pp,
1778 struct mvneta_rx_desc *rx_desc)
1780 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
1781 u32 status = rx_desc->status;
1783 /* update per-cpu counter */
1784 u64_stats_update_begin(&stats->syncp);
1786 u64_stats_update_end(&stats->syncp);
1788 switch (status & MVNETA_RXD_ERR_CODE_MASK) {
1789 case MVNETA_RXD_ERR_CRC:
1790 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
1791 status, rx_desc->data_size);
1793 case MVNETA_RXD_ERR_OVERRUN:
1794 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
1795 status, rx_desc->data_size);
1797 case MVNETA_RXD_ERR_LEN:
1798 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
1799 status, rx_desc->data_size);
1801 case MVNETA_RXD_ERR_RESOURCE:
1802 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
1803 status, rx_desc->data_size);
1808 /* Handle RX checksum offload based on the descriptor's status */
1809 static void mvneta_rx_csum(struct mvneta_port *pp, u32 status,
1810 struct sk_buff *skb)
1812 if ((pp->dev->features & NETIF_F_RXCSUM) &&
1813 (status & MVNETA_RXD_L3_IP4) &&
1814 (status & MVNETA_RXD_L4_CSUM_OK)) {
1816 skb->ip_summed = CHECKSUM_UNNECESSARY;
1820 skb->ip_summed = CHECKSUM_NONE;
1823 /* Return tx queue pointer (find last set bit) according to <cause> returned
1824 * form tx_done reg. <cause> must not be null. The return value is always a
1825 * valid queue for matching the first one found in <cause>.
1827 static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp,
1830 int queue = fls(cause) - 1;
1832 return &pp->txqs[queue];
1835 /* Free tx queue skbuffs */
1836 static void mvneta_txq_bufs_free(struct mvneta_port *pp,
1837 struct mvneta_tx_queue *txq, int num,
1838 struct netdev_queue *nq)
1840 unsigned int bytes_compl = 0, pkts_compl = 0;
1843 for (i = 0; i < num; i++) {
1844 struct mvneta_tx_buf *buf = &txq->buf[txq->txq_get_index];
1845 struct mvneta_tx_desc *tx_desc = txq->descs +
1848 mvneta_txq_inc_get(txq);
1850 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr) &&
1851 buf->type != MVNETA_TYPE_XDP_TX)
1852 dma_unmap_single(pp->dev->dev.parent,
1853 tx_desc->buf_phys_addr,
1854 tx_desc->data_size, DMA_TO_DEVICE);
1855 if (buf->type == MVNETA_TYPE_SKB && buf->skb) {
1856 bytes_compl += buf->skb->len;
1858 dev_kfree_skb_any(buf->skb);
1859 } else if (buf->type == MVNETA_TYPE_XDP_TX ||
1860 buf->type == MVNETA_TYPE_XDP_NDO) {
1861 xdp_return_frame(buf->xdpf);
1865 netdev_tx_completed_queue(nq, pkts_compl, bytes_compl);
1868 /* Handle end of transmission */
1869 static void mvneta_txq_done(struct mvneta_port *pp,
1870 struct mvneta_tx_queue *txq)
1872 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
1875 tx_done = mvneta_txq_sent_desc_proc(pp, txq);
1879 mvneta_txq_bufs_free(pp, txq, tx_done, nq);
1881 txq->count -= tx_done;
1883 if (netif_tx_queue_stopped(nq)) {
1884 if (txq->count <= txq->tx_wake_threshold)
1885 netif_tx_wake_queue(nq);
1889 /* Refill processing for SW buffer management */
1890 /* Allocate page per descriptor */
1891 static int mvneta_rx_refill(struct mvneta_port *pp,
1892 struct mvneta_rx_desc *rx_desc,
1893 struct mvneta_rx_queue *rxq,
1896 dma_addr_t phys_addr;
1899 page = page_pool_alloc_pages(rxq->page_pool,
1900 gfp_mask | __GFP_NOWARN);
1904 phys_addr = page_pool_get_dma_addr(page) + pp->rx_offset_correction;
1905 mvneta_rx_desc_fill(rx_desc, phys_addr, page, rxq);
1910 /* Handle tx checksum */
1911 static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb)
1913 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1915 __be16 l3_proto = vlan_get_protocol(skb);
1918 if (l3_proto == htons(ETH_P_IP)) {
1919 struct iphdr *ip4h = ip_hdr(skb);
1921 /* Calculate IPv4 checksum and L4 checksum */
1922 ip_hdr_len = ip4h->ihl;
1923 l4_proto = ip4h->protocol;
1924 } else if (l3_proto == htons(ETH_P_IPV6)) {
1925 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1927 /* Read l4_protocol from one of IPv6 extra headers */
1928 if (skb_network_header_len(skb) > 0)
1929 ip_hdr_len = (skb_network_header_len(skb) >> 2);
1930 l4_proto = ip6h->nexthdr;
1932 return MVNETA_TX_L4_CSUM_NOT;
1934 return mvneta_txq_desc_csum(skb_network_offset(skb),
1935 l3_proto, ip_hdr_len, l4_proto);
1938 return MVNETA_TX_L4_CSUM_NOT;
1941 /* Drop packets received by the RXQ and free buffers */
1942 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
1943 struct mvneta_rx_queue *rxq)
1947 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1949 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1952 for (i = 0; i < rx_done; i++) {
1953 struct mvneta_rx_desc *rx_desc =
1954 mvneta_rxq_next_desc_get(rxq);
1955 u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
1956 struct mvneta_bm_pool *bm_pool;
1958 bm_pool = &pp->bm_priv->bm_pools[pool_id];
1959 /* Return dropped buffer to the pool */
1960 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
1961 rx_desc->buf_phys_addr);
1966 for (i = 0; i < rxq->size; i++) {
1967 struct mvneta_rx_desc *rx_desc = rxq->descs + i;
1968 void *data = rxq->buf_virt_addr[i];
1969 if (!data || !(rx_desc->buf_phys_addr))
1972 page_pool_put_full_page(rxq->page_pool, data, false);
1974 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq))
1975 xdp_rxq_info_unreg(&rxq->xdp_rxq);
1976 page_pool_destroy(rxq->page_pool);
1977 rxq->page_pool = NULL;
1981 mvneta_update_stats(struct mvneta_port *pp,
1982 struct mvneta_stats *ps)
1984 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
1986 u64_stats_update_begin(&stats->syncp);
1987 stats->es.ps.rx_packets += ps->rx_packets;
1988 stats->es.ps.rx_bytes += ps->rx_bytes;
1990 stats->es.ps.xdp_redirect += ps->xdp_redirect;
1991 stats->es.ps.xdp_pass += ps->xdp_pass;
1992 stats->es.ps.xdp_drop += ps->xdp_drop;
1993 u64_stats_update_end(&stats->syncp);
1997 int mvneta_rx_refill_queue(struct mvneta_port *pp, struct mvneta_rx_queue *rxq)
1999 struct mvneta_rx_desc *rx_desc;
2000 int curr_desc = rxq->first_to_refill;
2003 for (i = 0; (i < rxq->refill_num) && (i < 64); i++) {
2004 rx_desc = rxq->descs + curr_desc;
2005 if (!(rx_desc->buf_phys_addr)) {
2006 if (mvneta_rx_refill(pp, rx_desc, rxq, GFP_ATOMIC)) {
2007 struct mvneta_pcpu_stats *stats;
2009 pr_err("Can't refill queue %d. Done %d from %d\n",
2010 rxq->id, i, rxq->refill_num);
2012 stats = this_cpu_ptr(pp->stats);
2013 u64_stats_update_begin(&stats->syncp);
2014 stats->es.refill_error++;
2015 u64_stats_update_end(&stats->syncp);
2019 curr_desc = MVNETA_QUEUE_NEXT_DESC(rxq, curr_desc);
2021 rxq->refill_num -= i;
2022 rxq->first_to_refill = curr_desc;
2028 mvneta_xdp_submit_frame(struct mvneta_port *pp, struct mvneta_tx_queue *txq,
2029 struct xdp_frame *xdpf, bool dma_map)
2031 struct mvneta_tx_desc *tx_desc;
2032 struct mvneta_tx_buf *buf;
2033 dma_addr_t dma_addr;
2035 if (txq->count >= txq->tx_stop_threshold)
2036 return MVNETA_XDP_DROPPED;
2038 tx_desc = mvneta_txq_next_desc_get(txq);
2040 buf = &txq->buf[txq->txq_put_index];
2043 dma_addr = dma_map_single(pp->dev->dev.parent, xdpf->data,
2044 xdpf->len, DMA_TO_DEVICE);
2045 if (dma_mapping_error(pp->dev->dev.parent, dma_addr)) {
2046 mvneta_txq_desc_put(txq);
2047 return MVNETA_XDP_DROPPED;
2049 buf->type = MVNETA_TYPE_XDP_NDO;
2051 struct page *page = virt_to_page(xdpf->data);
2053 dma_addr = page_pool_get_dma_addr(page) +
2054 sizeof(*xdpf) + xdpf->headroom;
2055 dma_sync_single_for_device(pp->dev->dev.parent, dma_addr,
2056 xdpf->len, DMA_BIDIRECTIONAL);
2057 buf->type = MVNETA_TYPE_XDP_TX;
2061 tx_desc->command = MVNETA_TXD_FLZ_DESC;
2062 tx_desc->buf_phys_addr = dma_addr;
2063 tx_desc->data_size = xdpf->len;
2065 mvneta_txq_inc_put(txq);
2069 return MVNETA_XDP_TX;
2073 mvneta_xdp_xmit_back(struct mvneta_port *pp, struct xdp_buff *xdp)
2075 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2076 struct mvneta_tx_queue *txq;
2077 struct netdev_queue *nq;
2078 struct xdp_frame *xdpf;
2082 xdpf = xdp_convert_buff_to_frame(xdp);
2083 if (unlikely(!xdpf))
2084 return MVNETA_XDP_DROPPED;
2086 cpu = smp_processor_id();
2087 txq = &pp->txqs[cpu % txq_number];
2088 nq = netdev_get_tx_queue(pp->dev, txq->id);
2090 __netif_tx_lock(nq, cpu);
2091 ret = mvneta_xdp_submit_frame(pp, txq, xdpf, false);
2092 if (ret == MVNETA_XDP_TX) {
2093 u64_stats_update_begin(&stats->syncp);
2094 stats->es.ps.tx_bytes += xdpf->len;
2095 stats->es.ps.tx_packets++;
2096 stats->es.ps.xdp_tx++;
2097 u64_stats_update_end(&stats->syncp);
2099 mvneta_txq_pend_desc_add(pp, txq, 0);
2101 u64_stats_update_begin(&stats->syncp);
2102 stats->es.ps.xdp_tx_err++;
2103 u64_stats_update_end(&stats->syncp);
2105 __netif_tx_unlock(nq);
2111 mvneta_xdp_xmit(struct net_device *dev, int num_frame,
2112 struct xdp_frame **frames, u32 flags)
2114 struct mvneta_port *pp = netdev_priv(dev);
2115 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2116 int i, nxmit_byte = 0, nxmit = num_frame;
2117 int cpu = smp_processor_id();
2118 struct mvneta_tx_queue *txq;
2119 struct netdev_queue *nq;
2122 if (unlikely(test_bit(__MVNETA_DOWN, &pp->state)))
2125 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
2128 txq = &pp->txqs[cpu % txq_number];
2129 nq = netdev_get_tx_queue(pp->dev, txq->id);
2131 __netif_tx_lock(nq, cpu);
2132 for (i = 0; i < num_frame; i++) {
2133 ret = mvneta_xdp_submit_frame(pp, txq, frames[i], true);
2134 if (ret == MVNETA_XDP_TX) {
2135 nxmit_byte += frames[i]->len;
2137 xdp_return_frame_rx_napi(frames[i]);
2142 if (unlikely(flags & XDP_XMIT_FLUSH))
2143 mvneta_txq_pend_desc_add(pp, txq, 0);
2144 __netif_tx_unlock(nq);
2146 u64_stats_update_begin(&stats->syncp);
2147 stats->es.ps.tx_bytes += nxmit_byte;
2148 stats->es.ps.tx_packets += nxmit;
2149 stats->es.ps.xdp_xmit += nxmit;
2150 stats->es.ps.xdp_xmit_err += num_frame - nxmit;
2151 u64_stats_update_end(&stats->syncp);
2157 mvneta_run_xdp(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
2158 struct bpf_prog *prog, struct xdp_buff *xdp,
2159 struct mvneta_stats *stats)
2161 unsigned int len, sync;
2165 len = xdp->data_end - xdp->data_hard_start - pp->rx_offset_correction;
2166 act = bpf_prog_run_xdp(prog, xdp);
2168 /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */
2169 sync = xdp->data_end - xdp->data_hard_start - pp->rx_offset_correction;
2170 sync = max(sync, len);
2175 return MVNETA_XDP_PASS;
2176 case XDP_REDIRECT: {
2179 err = xdp_do_redirect(pp->dev, xdp, prog);
2180 if (unlikely(err)) {
2181 ret = MVNETA_XDP_DROPPED;
2182 page = virt_to_head_page(xdp->data);
2183 page_pool_put_page(rxq->page_pool, page, sync, true);
2185 ret = MVNETA_XDP_REDIR;
2186 stats->xdp_redirect++;
2191 ret = mvneta_xdp_xmit_back(pp, xdp);
2192 if (ret != MVNETA_XDP_TX) {
2193 page = virt_to_head_page(xdp->data);
2194 page_pool_put_page(rxq->page_pool, page, sync, true);
2198 bpf_warn_invalid_xdp_action(act);
2201 trace_xdp_exception(pp->dev, prog, act);
2204 page = virt_to_head_page(xdp->data);
2205 page_pool_put_page(rxq->page_pool, page, sync, true);
2206 ret = MVNETA_XDP_DROPPED;
2211 stats->rx_bytes += xdp->data_end - xdp->data;
2212 stats->rx_packets++;
2218 mvneta_swbm_rx_frame(struct mvneta_port *pp,
2219 struct mvneta_rx_desc *rx_desc,
2220 struct mvneta_rx_queue *rxq,
2221 struct xdp_buff *xdp,
2222 struct bpf_prog *xdp_prog,
2224 struct mvneta_stats *stats)
2226 unsigned char *data = page_address(page);
2227 int data_len = -MVNETA_MH_SIZE, len;
2228 struct net_device *dev = pp->dev;
2229 enum dma_data_direction dma_dir;
2232 if (MVNETA_SKB_SIZE(rx_desc->data_size) > PAGE_SIZE) {
2233 len = MVNETA_MAX_RX_BUF_SIZE;
2236 len = rx_desc->data_size;
2237 data_len += len - ETH_FCS_LEN;
2240 dma_dir = page_pool_get_dma_dir(rxq->page_pool);
2241 dma_sync_single_for_cpu(dev->dev.parent,
2242 rx_desc->buf_phys_addr,
2245 /* Prefetch header */
2248 xdp->data_hard_start = data;
2249 xdp->data = data + pp->rx_offset_correction + MVNETA_MH_SIZE;
2250 xdp->data_end = xdp->data + data_len;
2251 xdp_set_data_meta_invalid(xdp);
2254 ret = mvneta_run_xdp(pp, rxq, xdp_prog, xdp, stats);
2259 rxq->skb = build_skb(xdp->data_hard_start, PAGE_SIZE);
2260 if (unlikely(!rxq->skb)) {
2261 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2263 netdev_err(dev, "Can't allocate skb on queue %d\n", rxq->id);
2265 u64_stats_update_begin(&stats->syncp);
2266 stats->es.skb_alloc_error++;
2267 stats->rx_dropped++;
2268 u64_stats_update_end(&stats->syncp);
2272 page_pool_release_page(rxq->page_pool, page);
2274 skb_reserve(rxq->skb,
2275 xdp->data - xdp->data_hard_start);
2276 skb_put(rxq->skb, xdp->data_end - xdp->data);
2277 mvneta_rx_csum(pp, rx_desc->status, rxq->skb);
2279 rxq->left_size = rx_desc->data_size - len;
2282 rx_desc->buf_phys_addr = 0;
2288 mvneta_swbm_add_rx_fragment(struct mvneta_port *pp,
2289 struct mvneta_rx_desc *rx_desc,
2290 struct mvneta_rx_queue *rxq,
2293 struct net_device *dev = pp->dev;
2294 enum dma_data_direction dma_dir;
2297 if (rxq->left_size > MVNETA_MAX_RX_BUF_SIZE) {
2298 len = MVNETA_MAX_RX_BUF_SIZE;
2301 len = rxq->left_size;
2302 data_len = len - ETH_FCS_LEN;
2304 dma_dir = page_pool_get_dma_dir(rxq->page_pool);
2305 dma_sync_single_for_cpu(dev->dev.parent,
2306 rx_desc->buf_phys_addr,
2309 /* refill descriptor with new buffer later */
2310 skb_add_rx_frag(rxq->skb,
2311 skb_shinfo(rxq->skb)->nr_frags,
2312 page, pp->rx_offset_correction, data_len,
2315 page_pool_release_page(rxq->page_pool, page);
2316 rx_desc->buf_phys_addr = 0;
2317 rxq->left_size -= len;
2320 /* Main rx processing when using software buffer management */
2321 static int mvneta_rx_swbm(struct napi_struct *napi,
2322 struct mvneta_port *pp, int budget,
2323 struct mvneta_rx_queue *rxq)
2325 int rx_proc = 0, rx_todo, refill;
2326 struct net_device *dev = pp->dev;
2327 struct mvneta_stats ps = {};
2328 struct bpf_prog *xdp_prog;
2329 struct xdp_buff xdp_buf;
2331 /* Get number of received packets */
2332 rx_todo = mvneta_rxq_busy_desc_num_get(pp, rxq);
2335 xdp_prog = READ_ONCE(pp->xdp_prog);
2336 xdp_buf.rxq = &rxq->xdp_rxq;
2337 xdp_buf.frame_sz = PAGE_SIZE;
2339 /* Fairness NAPI loop */
2340 while (rx_proc < budget && rx_proc < rx_todo) {
2341 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
2342 u32 rx_status, index;
2345 index = rx_desc - rxq->descs;
2346 page = (struct page *)rxq->buf_virt_addr[index];
2348 rx_status = rx_desc->status;
2352 if (rx_status & MVNETA_RXD_FIRST_DESC) {
2355 /* Check errors only for FIRST descriptor */
2356 if (rx_status & MVNETA_RXD_ERR_SUMMARY) {
2357 mvneta_rx_error(pp, rx_desc);
2358 /* leave the descriptor untouched */
2362 err = mvneta_swbm_rx_frame(pp, rx_desc, rxq, &xdp_buf,
2363 xdp_prog, page, &ps);
2367 if (unlikely(!rxq->skb)) {
2368 pr_debug("no skb for rx_status 0x%x\n",
2372 mvneta_swbm_add_rx_fragment(pp, rx_desc, rxq, page);
2373 } /* Middle or Last descriptor */
2375 if (!(rx_status & MVNETA_RXD_LAST_DESC))
2376 /* no last descriptor this time */
2379 if (rxq->left_size) {
2380 pr_err("get last desc, but left_size (%d) != 0\n",
2382 dev_kfree_skb_any(rxq->skb);
2388 ps.rx_bytes += rxq->skb->len;
2391 /* Linux processing */
2392 rxq->skb->protocol = eth_type_trans(rxq->skb, dev);
2394 napi_gro_receive(napi, rxq->skb);
2396 /* clean uncomplete skb pointer in queue */
2401 if (ps.xdp_redirect)
2405 mvneta_update_stats(pp, &ps);
2407 /* return some buffers to hardware queue, one at a time is too slow */
2408 refill = mvneta_rx_refill_queue(pp, rxq);
2410 /* Update rxq management counters */
2411 mvneta_rxq_desc_num_update(pp, rxq, rx_proc, refill);
2413 return ps.rx_packets;
2416 /* Main rx processing when using hardware buffer management */
2417 static int mvneta_rx_hwbm(struct napi_struct *napi,
2418 struct mvneta_port *pp, int rx_todo,
2419 struct mvneta_rx_queue *rxq)
2421 struct net_device *dev = pp->dev;
2426 /* Get number of received packets */
2427 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
2429 if (rx_todo > rx_done)
2434 /* Fairness NAPI loop */
2435 while (rx_done < rx_todo) {
2436 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
2437 struct mvneta_bm_pool *bm_pool = NULL;
2438 struct sk_buff *skb;
2439 unsigned char *data;
2440 dma_addr_t phys_addr;
2441 u32 rx_status, frag_size;
2446 rx_status = rx_desc->status;
2447 rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
2448 data = (u8 *)(uintptr_t)rx_desc->buf_cookie;
2449 phys_addr = rx_desc->buf_phys_addr;
2450 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
2451 bm_pool = &pp->bm_priv->bm_pools[pool_id];
2453 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
2454 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
2455 err_drop_frame_ret_pool:
2456 /* Return the buffer to the pool */
2457 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
2458 rx_desc->buf_phys_addr);
2460 mvneta_rx_error(pp, rx_desc);
2461 /* leave the descriptor untouched */
2465 if (rx_bytes <= rx_copybreak) {
2466 /* better copy a small frame and not unmap the DMA region */
2467 skb = netdev_alloc_skb_ip_align(dev, rx_bytes);
2469 goto err_drop_frame_ret_pool;
2471 dma_sync_single_range_for_cpu(&pp->bm_priv->pdev->dev,
2472 rx_desc->buf_phys_addr,
2473 MVNETA_MH_SIZE + NET_SKB_PAD,
2476 skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD,
2479 skb->protocol = eth_type_trans(skb, dev);
2480 mvneta_rx_csum(pp, rx_status, skb);
2481 napi_gro_receive(napi, skb);
2484 rcvd_bytes += rx_bytes;
2486 /* Return the buffer to the pool */
2487 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
2488 rx_desc->buf_phys_addr);
2490 /* leave the descriptor and buffer untouched */
2494 /* Refill processing */
2495 err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC);
2497 struct mvneta_pcpu_stats *stats;
2499 netdev_err(dev, "Linux processing - Can't refill\n");
2501 stats = this_cpu_ptr(pp->stats);
2502 u64_stats_update_begin(&stats->syncp);
2503 stats->es.refill_error++;
2504 u64_stats_update_end(&stats->syncp);
2506 goto err_drop_frame_ret_pool;
2509 frag_size = bm_pool->hwbm_pool.frag_size;
2511 skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size);
2513 /* After refill old buffer has to be unmapped regardless
2514 * the skb is successfully built or not.
2516 dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr,
2517 bm_pool->buf_size, DMA_FROM_DEVICE);
2519 goto err_drop_frame;
2522 rcvd_bytes += rx_bytes;
2524 /* Linux processing */
2525 skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD);
2526 skb_put(skb, rx_bytes);
2528 skb->protocol = eth_type_trans(skb, dev);
2530 mvneta_rx_csum(pp, rx_status, skb);
2532 napi_gro_receive(napi, skb);
2536 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2538 u64_stats_update_begin(&stats->syncp);
2539 stats->es.ps.rx_packets += rcvd_pkts;
2540 stats->es.ps.rx_bytes += rcvd_bytes;
2541 u64_stats_update_end(&stats->syncp);
2544 /* Update rxq management counters */
2545 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
2551 mvneta_tso_put_hdr(struct sk_buff *skb,
2552 struct mvneta_port *pp, struct mvneta_tx_queue *txq)
2554 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2555 struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index];
2556 struct mvneta_tx_desc *tx_desc;
2558 tx_desc = mvneta_txq_next_desc_get(txq);
2559 tx_desc->data_size = hdr_len;
2560 tx_desc->command = mvneta_skb_tx_csum(pp, skb);
2561 tx_desc->command |= MVNETA_TXD_F_DESC;
2562 tx_desc->buf_phys_addr = txq->tso_hdrs_phys +
2563 txq->txq_put_index * TSO_HEADER_SIZE;
2564 buf->type = MVNETA_TYPE_SKB;
2567 mvneta_txq_inc_put(txq);
2571 mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq,
2572 struct sk_buff *skb, char *data, int size,
2573 bool last_tcp, bool is_last)
2575 struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index];
2576 struct mvneta_tx_desc *tx_desc;
2578 tx_desc = mvneta_txq_next_desc_get(txq);
2579 tx_desc->data_size = size;
2580 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data,
2581 size, DMA_TO_DEVICE);
2582 if (unlikely(dma_mapping_error(dev->dev.parent,
2583 tx_desc->buf_phys_addr))) {
2584 mvneta_txq_desc_put(txq);
2588 tx_desc->command = 0;
2589 buf->type = MVNETA_TYPE_SKB;
2593 /* last descriptor in the TCP packet */
2594 tx_desc->command = MVNETA_TXD_L_DESC;
2596 /* last descriptor in SKB */
2600 mvneta_txq_inc_put(txq);
2604 static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev,
2605 struct mvneta_tx_queue *txq)
2607 int total_len, data_left;
2609 struct mvneta_port *pp = netdev_priv(dev);
2611 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2614 /* Count needed descriptors */
2615 if ((txq->count + tso_count_descs(skb)) >= txq->size)
2618 if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) {
2619 pr_info("*** Is this even possible???!?!?\n");
2623 /* Initialize the TSO handler, and prepare the first payload */
2624 tso_start(skb, &tso);
2626 total_len = skb->len - hdr_len;
2627 while (total_len > 0) {
2630 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
2631 total_len -= data_left;
2634 /* prepare packet headers: MAC + IP + TCP */
2635 hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE;
2636 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
2638 mvneta_tso_put_hdr(skb, pp, txq);
2640 while (data_left > 0) {
2644 size = min_t(int, tso.size, data_left);
2646 if (mvneta_tso_put_data(dev, txq, skb,
2653 tso_build_data(skb, &tso, size);
2660 /* Release all used data descriptors; header descriptors must not
2663 for (i = desc_count - 1; i >= 0; i--) {
2664 struct mvneta_tx_desc *tx_desc = txq->descs + i;
2665 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr))
2666 dma_unmap_single(pp->dev->dev.parent,
2667 tx_desc->buf_phys_addr,
2670 mvneta_txq_desc_put(txq);
2675 /* Handle tx fragmentation processing */
2676 static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb,
2677 struct mvneta_tx_queue *txq)
2679 struct mvneta_tx_desc *tx_desc;
2680 int i, nr_frags = skb_shinfo(skb)->nr_frags;
2682 for (i = 0; i < nr_frags; i++) {
2683 struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index];
2684 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2685 void *addr = skb_frag_address(frag);
2687 tx_desc = mvneta_txq_next_desc_get(txq);
2688 tx_desc->data_size = skb_frag_size(frag);
2690 tx_desc->buf_phys_addr =
2691 dma_map_single(pp->dev->dev.parent, addr,
2692 tx_desc->data_size, DMA_TO_DEVICE);
2694 if (dma_mapping_error(pp->dev->dev.parent,
2695 tx_desc->buf_phys_addr)) {
2696 mvneta_txq_desc_put(txq);
2700 if (i == nr_frags - 1) {
2701 /* Last descriptor */
2702 tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD;
2705 /* Descriptor in the middle: Not First, Not Last */
2706 tx_desc->command = 0;
2709 buf->type = MVNETA_TYPE_SKB;
2710 mvneta_txq_inc_put(txq);
2716 /* Release all descriptors that were used to map fragments of
2717 * this packet, as well as the corresponding DMA mappings
2719 for (i = i - 1; i >= 0; i--) {
2720 tx_desc = txq->descs + i;
2721 dma_unmap_single(pp->dev->dev.parent,
2722 tx_desc->buf_phys_addr,
2725 mvneta_txq_desc_put(txq);
2731 /* Main tx processing */
2732 static netdev_tx_t mvneta_tx(struct sk_buff *skb, struct net_device *dev)
2734 struct mvneta_port *pp = netdev_priv(dev);
2735 u16 txq_id = skb_get_queue_mapping(skb);
2736 struct mvneta_tx_queue *txq = &pp->txqs[txq_id];
2737 struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index];
2738 struct mvneta_tx_desc *tx_desc;
2743 if (!netif_running(dev))
2746 if (skb_is_gso(skb)) {
2747 frags = mvneta_tx_tso(skb, dev, txq);
2751 frags = skb_shinfo(skb)->nr_frags + 1;
2753 /* Get a descriptor for the first part of the packet */
2754 tx_desc = mvneta_txq_next_desc_get(txq);
2756 tx_cmd = mvneta_skb_tx_csum(pp, skb);
2758 tx_desc->data_size = skb_headlen(skb);
2760 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data,
2763 if (unlikely(dma_mapping_error(dev->dev.parent,
2764 tx_desc->buf_phys_addr))) {
2765 mvneta_txq_desc_put(txq);
2770 buf->type = MVNETA_TYPE_SKB;
2772 /* First and Last descriptor */
2773 tx_cmd |= MVNETA_TXD_FLZ_DESC;
2774 tx_desc->command = tx_cmd;
2776 mvneta_txq_inc_put(txq);
2778 /* First but not Last */
2779 tx_cmd |= MVNETA_TXD_F_DESC;
2781 mvneta_txq_inc_put(txq);
2782 tx_desc->command = tx_cmd;
2783 /* Continue with other skb fragments */
2784 if (mvneta_tx_frag_process(pp, skb, txq)) {
2785 dma_unmap_single(dev->dev.parent,
2786 tx_desc->buf_phys_addr,
2789 mvneta_txq_desc_put(txq);
2797 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
2798 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2800 netdev_tx_sent_queue(nq, len);
2802 txq->count += frags;
2803 if (txq->count >= txq->tx_stop_threshold)
2804 netif_tx_stop_queue(nq);
2806 if (!netdev_xmit_more() || netif_xmit_stopped(nq) ||
2807 txq->pending + frags > MVNETA_TXQ_DEC_SENT_MASK)
2808 mvneta_txq_pend_desc_add(pp, txq, frags);
2810 txq->pending += frags;
2812 u64_stats_update_begin(&stats->syncp);
2813 stats->es.ps.tx_bytes += len;
2814 stats->es.ps.tx_packets++;
2815 u64_stats_update_end(&stats->syncp);
2817 dev->stats.tx_dropped++;
2818 dev_kfree_skb_any(skb);
2821 return NETDEV_TX_OK;
2825 /* Free tx resources, when resetting a port */
2826 static void mvneta_txq_done_force(struct mvneta_port *pp,
2827 struct mvneta_tx_queue *txq)
2830 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
2831 int tx_done = txq->count;
2833 mvneta_txq_bufs_free(pp, txq, tx_done, nq);
2837 txq->txq_put_index = 0;
2838 txq->txq_get_index = 0;
2841 /* Handle tx done - called in softirq context. The <cause_tx_done> argument
2842 * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL.
2844 static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done)
2846 struct mvneta_tx_queue *txq;
2847 struct netdev_queue *nq;
2848 int cpu = smp_processor_id();
2850 while (cause_tx_done) {
2851 txq = mvneta_tx_done_policy(pp, cause_tx_done);
2853 nq = netdev_get_tx_queue(pp->dev, txq->id);
2854 __netif_tx_lock(nq, cpu);
2857 mvneta_txq_done(pp, txq);
2859 __netif_tx_unlock(nq);
2860 cause_tx_done &= ~((1 << txq->id));
2864 /* Compute crc8 of the specified address, using a unique algorithm ,
2865 * according to hw spec, different than generic crc8 algorithm
2867 static int mvneta_addr_crc(unsigned char *addr)
2872 for (i = 0; i < ETH_ALEN; i++) {
2875 crc = (crc ^ addr[i]) << 8;
2876 for (j = 7; j >= 0; j--) {
2877 if (crc & (0x100 << j))
2885 /* This method controls the net device special MAC multicast support.
2886 * The Special Multicast Table for MAC addresses supports MAC of the form
2887 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
2888 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2889 * Table entries in the DA-Filter table. This method set the Special
2890 * Multicast Table appropriate entry.
2892 static void mvneta_set_special_mcast_addr(struct mvneta_port *pp,
2893 unsigned char last_byte,
2896 unsigned int smc_table_reg;
2897 unsigned int tbl_offset;
2898 unsigned int reg_offset;
2900 /* Register offset from SMC table base */
2901 tbl_offset = (last_byte / 4);
2902 /* Entry offset within the above reg */
2903 reg_offset = last_byte % 4;
2905 smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST
2909 smc_table_reg &= ~(0xff << (8 * reg_offset));
2911 smc_table_reg &= ~(0xff << (8 * reg_offset));
2912 smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
2915 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4,
2919 /* This method controls the network device Other MAC multicast support.
2920 * The Other Multicast Table is used for multicast of another type.
2921 * A CRC-8 is used as an index to the Other Multicast Table entries
2922 * in the DA-Filter table.
2923 * The method gets the CRC-8 value from the calling routine and
2924 * sets the Other Multicast Table appropriate entry according to the
2927 static void mvneta_set_other_mcast_addr(struct mvneta_port *pp,
2931 unsigned int omc_table_reg;
2932 unsigned int tbl_offset;
2933 unsigned int reg_offset;
2935 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
2936 reg_offset = crc8 % 4; /* Entry offset within the above reg */
2938 omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset);
2941 /* Clear accepts frame bit at specified Other DA table entry */
2942 omc_table_reg &= ~(0xff << (8 * reg_offset));
2944 omc_table_reg &= ~(0xff << (8 * reg_offset));
2945 omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
2948 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg);
2951 /* The network device supports multicast using two tables:
2952 * 1) Special Multicast Table for MAC addresses of the form
2953 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
2954 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2955 * Table entries in the DA-Filter table.
2956 * 2) Other Multicast Table for multicast of another type. A CRC-8 value
2957 * is used as an index to the Other Multicast Table entries in the
2960 static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr,
2963 unsigned char crc_result = 0;
2965 if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) {
2966 mvneta_set_special_mcast_addr(pp, p_addr[5], queue);
2970 crc_result = mvneta_addr_crc(p_addr);
2972 if (pp->mcast_count[crc_result] == 0) {
2973 netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n",
2978 pp->mcast_count[crc_result]--;
2979 if (pp->mcast_count[crc_result] != 0) {
2980 netdev_info(pp->dev,
2981 "After delete there are %d valid Mcast for crc8=0x%02x\n",
2982 pp->mcast_count[crc_result], crc_result);
2986 pp->mcast_count[crc_result]++;
2988 mvneta_set_other_mcast_addr(pp, crc_result, queue);
2993 /* Configure Fitering mode of Ethernet port */
2994 static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp,
2997 u32 port_cfg_reg, val;
2999 port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG);
3001 val = mvreg_read(pp, MVNETA_TYPE_PRIO);
3003 /* Set / Clear UPM bit in port configuration register */
3005 /* Accept all Unicast addresses */
3006 port_cfg_reg |= MVNETA_UNI_PROMISC_MODE;
3007 val |= MVNETA_FORCE_UNI;
3008 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff);
3009 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff);
3011 /* Reject all Unicast addresses */
3012 port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE;
3013 val &= ~MVNETA_FORCE_UNI;
3016 mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg);
3017 mvreg_write(pp, MVNETA_TYPE_PRIO, val);
3020 /* register unicast and multicast addresses */
3021 static void mvneta_set_rx_mode(struct net_device *dev)
3023 struct mvneta_port *pp = netdev_priv(dev);
3024 struct netdev_hw_addr *ha;
3026 if (dev->flags & IFF_PROMISC) {
3027 /* Accept all: Multicast + Unicast */
3028 mvneta_rx_unicast_promisc_set(pp, 1);
3029 mvneta_set_ucast_table(pp, pp->rxq_def);
3030 mvneta_set_special_mcast_table(pp, pp->rxq_def);
3031 mvneta_set_other_mcast_table(pp, pp->rxq_def);
3033 /* Accept single Unicast */
3034 mvneta_rx_unicast_promisc_set(pp, 0);
3035 mvneta_set_ucast_table(pp, -1);
3036 mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def);
3038 if (dev->flags & IFF_ALLMULTI) {
3039 /* Accept all multicast */
3040 mvneta_set_special_mcast_table(pp, pp->rxq_def);
3041 mvneta_set_other_mcast_table(pp, pp->rxq_def);
3043 /* Accept only initialized multicast */
3044 mvneta_set_special_mcast_table(pp, -1);
3045 mvneta_set_other_mcast_table(pp, -1);
3047 if (!netdev_mc_empty(dev)) {
3048 netdev_for_each_mc_addr(ha, dev) {
3049 mvneta_mcast_addr_set(pp, ha->addr,
3057 /* Interrupt handling - the callback for request_irq() */
3058 static irqreturn_t mvneta_isr(int irq, void *dev_id)
3060 struct mvneta_port *pp = (struct mvneta_port *)dev_id;
3062 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
3063 napi_schedule(&pp->napi);
3068 /* Interrupt handling - the callback for request_percpu_irq() */
3069 static irqreturn_t mvneta_percpu_isr(int irq, void *dev_id)
3071 struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id;
3073 disable_percpu_irq(port->pp->dev->irq);
3074 napi_schedule(&port->napi);
3079 static void mvneta_link_change(struct mvneta_port *pp)
3081 u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
3083 phylink_mac_change(pp->phylink, !!(gmac_stat & MVNETA_GMAC_LINK_UP));
3087 * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
3088 * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
3089 * Bits 8 -15 of the cause Rx Tx register indicate that are received
3090 * packets on the corresponding RXQ (Bit 8 is for RX queue 0).
3091 * Each CPU has its own causeRxTx register
3093 static int mvneta_poll(struct napi_struct *napi, int budget)
3098 struct mvneta_port *pp = netdev_priv(napi->dev);
3099 struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
3101 if (!netif_running(pp->dev)) {
3102 napi_complete(napi);
3106 /* Read cause register */
3107 cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE);
3108 if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) {
3109 u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE);
3111 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
3113 if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE |
3114 MVNETA_CAUSE_LINK_CHANGE))
3115 mvneta_link_change(pp);
3118 /* Release Tx descriptors */
3119 if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) {
3120 mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL));
3121 cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL;
3124 /* For the case where the last mvneta_poll did not process all
3127 cause_rx_tx |= pp->neta_armada3700 ? pp->cause_rx_tx :
3130 rx_queue = fls(((cause_rx_tx >> 8) & 0xff));
3132 rx_queue = rx_queue - 1;
3134 rx_done = mvneta_rx_hwbm(napi, pp, budget,
3135 &pp->rxqs[rx_queue]);
3137 rx_done = mvneta_rx_swbm(napi, pp, budget,
3138 &pp->rxqs[rx_queue]);
3141 if (rx_done < budget) {
3143 napi_complete_done(napi, rx_done);
3145 if (pp->neta_armada3700) {
3146 unsigned long flags;
3148 local_irq_save(flags);
3149 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
3150 MVNETA_RX_INTR_MASK(rxq_number) |
3151 MVNETA_TX_INTR_MASK(txq_number) |
3152 MVNETA_MISCINTR_INTR_MASK);
3153 local_irq_restore(flags);
3155 enable_percpu_irq(pp->dev->irq, 0);
3159 if (pp->neta_armada3700)
3160 pp->cause_rx_tx = cause_rx_tx;
3162 port->cause_rx_tx = cause_rx_tx;
3167 static int mvneta_create_page_pool(struct mvneta_port *pp,
3168 struct mvneta_rx_queue *rxq, int size)
3170 struct bpf_prog *xdp_prog = READ_ONCE(pp->xdp_prog);
3171 struct page_pool_params pp_params = {
3173 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
3175 .nid = NUMA_NO_NODE,
3176 .dev = pp->dev->dev.parent,
3177 .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE,
3178 .offset = pp->rx_offset_correction,
3179 .max_len = MVNETA_MAX_RX_BUF_SIZE,
3183 rxq->page_pool = page_pool_create(&pp_params);
3184 if (IS_ERR(rxq->page_pool)) {
3185 err = PTR_ERR(rxq->page_pool);
3186 rxq->page_pool = NULL;
3190 err = xdp_rxq_info_reg(&rxq->xdp_rxq, pp->dev, rxq->id);
3194 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL,
3197 goto err_unregister_rxq;
3202 xdp_rxq_info_unreg(&rxq->xdp_rxq);
3204 page_pool_destroy(rxq->page_pool);
3205 rxq->page_pool = NULL;
3209 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
3210 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
3215 err = mvneta_create_page_pool(pp, rxq, num);
3219 for (i = 0; i < num; i++) {
3220 memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc));
3221 if (mvneta_rx_refill(pp, rxq->descs + i, rxq,
3224 "%s:rxq %d, %d of %d buffs filled\n",
3225 __func__, rxq->id, i, num);
3230 /* Add this number of RX descriptors as non occupied (ready to
3233 mvneta_rxq_non_occup_desc_add(pp, rxq, i);
3238 /* Free all packets pending transmit from all TXQs and reset TX port */
3239 static void mvneta_tx_reset(struct mvneta_port *pp)
3243 /* free the skb's in the tx ring */
3244 for (queue = 0; queue < txq_number; queue++)
3245 mvneta_txq_done_force(pp, &pp->txqs[queue]);
3247 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
3248 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
3251 static void mvneta_rx_reset(struct mvneta_port *pp)
3253 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
3254 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
3257 /* Rx/Tx queue initialization/cleanup methods */
3259 static int mvneta_rxq_sw_init(struct mvneta_port *pp,
3260 struct mvneta_rx_queue *rxq)
3262 rxq->size = pp->rx_ring_size;
3264 /* Allocate memory for RX descriptors */
3265 rxq->descs = dma_alloc_coherent(pp->dev->dev.parent,
3266 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
3267 &rxq->descs_phys, GFP_KERNEL);
3271 rxq->last_desc = rxq->size - 1;
3276 static void mvneta_rxq_hw_init(struct mvneta_port *pp,
3277 struct mvneta_rx_queue *rxq)
3279 /* Set Rx descriptors queue starting address */
3280 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
3281 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
3283 /* Set coalescing pkts and time */
3284 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
3285 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
3289 mvneta_rxq_offset_set(pp, rxq, 0);
3290 mvneta_rxq_buf_size_set(pp, rxq, PAGE_SIZE < SZ_64K ?
3291 MVNETA_MAX_RX_BUF_SIZE :
3292 MVNETA_RX_BUF_SIZE(pp->pkt_size));
3293 mvneta_rxq_bm_disable(pp, rxq);
3294 mvneta_rxq_fill(pp, rxq, rxq->size);
3297 mvneta_rxq_offset_set(pp, rxq,
3298 NET_SKB_PAD - pp->rx_offset_correction);
3300 mvneta_rxq_bm_enable(pp, rxq);
3301 /* Fill RXQ with buffers from RX pool */
3302 mvneta_rxq_long_pool_set(pp, rxq);
3303 mvneta_rxq_short_pool_set(pp, rxq);
3304 mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size);
3308 /* Create a specified RX queue */
3309 static int mvneta_rxq_init(struct mvneta_port *pp,
3310 struct mvneta_rx_queue *rxq)
3315 ret = mvneta_rxq_sw_init(pp, rxq);
3319 mvneta_rxq_hw_init(pp, rxq);
3324 /* Cleanup Rx queue */
3325 static void mvneta_rxq_deinit(struct mvneta_port *pp,
3326 struct mvneta_rx_queue *rxq)
3328 mvneta_rxq_drop_pkts(pp, rxq);
3331 dev_kfree_skb_any(rxq->skb);
3334 dma_free_coherent(pp->dev->dev.parent,
3335 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
3341 rxq->next_desc_to_proc = 0;
3342 rxq->descs_phys = 0;
3343 rxq->first_to_refill = 0;
3344 rxq->refill_num = 0;
3349 static int mvneta_txq_sw_init(struct mvneta_port *pp,
3350 struct mvneta_tx_queue *txq)
3354 txq->size = pp->tx_ring_size;
3356 /* A queue must always have room for at least one skb.
3357 * Therefore, stop the queue when the free entries reaches
3358 * the maximum number of descriptors per skb.
3360 txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS;
3361 txq->tx_wake_threshold = txq->tx_stop_threshold / 2;
3363 /* Allocate memory for TX descriptors */
3364 txq->descs = dma_alloc_coherent(pp->dev->dev.parent,
3365 txq->size * MVNETA_DESC_ALIGNED_SIZE,
3366 &txq->descs_phys, GFP_KERNEL);
3370 txq->last_desc = txq->size - 1;
3372 txq->buf = kmalloc_array(txq->size, sizeof(*txq->buf), GFP_KERNEL);
3374 dma_free_coherent(pp->dev->dev.parent,
3375 txq->size * MVNETA_DESC_ALIGNED_SIZE,
3376 txq->descs, txq->descs_phys);
3380 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
3381 txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent,
3382 txq->size * TSO_HEADER_SIZE,
3383 &txq->tso_hdrs_phys, GFP_KERNEL);
3384 if (!txq->tso_hdrs) {
3386 dma_free_coherent(pp->dev->dev.parent,
3387 txq->size * MVNETA_DESC_ALIGNED_SIZE,
3388 txq->descs, txq->descs_phys);
3392 /* Setup XPS mapping */
3394 cpu = txq->id % num_present_cpus();
3396 cpu = pp->rxq_def % num_present_cpus();
3397 cpumask_set_cpu(cpu, &txq->affinity_mask);
3398 netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id);
3403 static void mvneta_txq_hw_init(struct mvneta_port *pp,
3404 struct mvneta_tx_queue *txq)
3406 /* Set maximum bandwidth for enabled TXQs */
3407 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
3408 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
3410 /* Set Tx descriptors queue starting address */
3411 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
3412 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
3414 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
3417 /* Create and initialize a tx queue */
3418 static int mvneta_txq_init(struct mvneta_port *pp,
3419 struct mvneta_tx_queue *txq)
3423 ret = mvneta_txq_sw_init(pp, txq);
3427 mvneta_txq_hw_init(pp, txq);
3432 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
3433 static void mvneta_txq_sw_deinit(struct mvneta_port *pp,
3434 struct mvneta_tx_queue *txq)
3436 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
3441 dma_free_coherent(pp->dev->dev.parent,
3442 txq->size * TSO_HEADER_SIZE,
3443 txq->tso_hdrs, txq->tso_hdrs_phys);
3445 dma_free_coherent(pp->dev->dev.parent,
3446 txq->size * MVNETA_DESC_ALIGNED_SIZE,
3447 txq->descs, txq->descs_phys);
3449 netdev_tx_reset_queue(nq);
3453 txq->next_desc_to_proc = 0;
3454 txq->descs_phys = 0;
3457 static void mvneta_txq_hw_deinit(struct mvneta_port *pp,
3458 struct mvneta_tx_queue *txq)
3460 /* Set minimum bandwidth for disabled TXQs */
3461 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
3462 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
3464 /* Set Tx descriptors queue starting address and size */
3465 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
3466 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
3469 static void mvneta_txq_deinit(struct mvneta_port *pp,
3470 struct mvneta_tx_queue *txq)
3472 mvneta_txq_sw_deinit(pp, txq);
3473 mvneta_txq_hw_deinit(pp, txq);
3476 /* Cleanup all Tx queues */
3477 static void mvneta_cleanup_txqs(struct mvneta_port *pp)
3481 for (queue = 0; queue < txq_number; queue++)
3482 mvneta_txq_deinit(pp, &pp->txqs[queue]);
3485 /* Cleanup all Rx queues */
3486 static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
3490 for (queue = 0; queue < rxq_number; queue++)
3491 mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
3495 /* Init all Rx queues */
3496 static int mvneta_setup_rxqs(struct mvneta_port *pp)
3500 for (queue = 0; queue < rxq_number; queue++) {
3501 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
3504 netdev_err(pp->dev, "%s: can't create rxq=%d\n",
3506 mvneta_cleanup_rxqs(pp);
3514 /* Init all tx queues */
3515 static int mvneta_setup_txqs(struct mvneta_port *pp)
3519 for (queue = 0; queue < txq_number; queue++) {
3520 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
3522 netdev_err(pp->dev, "%s: can't create txq=%d\n",
3524 mvneta_cleanup_txqs(pp);
3532 static int mvneta_comphy_init(struct mvneta_port *pp)
3539 ret = phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET,
3544 return phy_power_on(pp->comphy);
3547 static void mvneta_start_dev(struct mvneta_port *pp)
3551 WARN_ON(mvneta_comphy_init(pp));
3553 mvneta_max_rx_size_set(pp, pp->pkt_size);
3554 mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
3556 /* start the Rx/Tx activity */
3557 mvneta_port_enable(pp);
3559 if (!pp->neta_armada3700) {
3560 /* Enable polling on the port */
3561 for_each_online_cpu(cpu) {
3562 struct mvneta_pcpu_port *port =
3563 per_cpu_ptr(pp->ports, cpu);
3565 napi_enable(&port->napi);
3568 napi_enable(&pp->napi);
3571 /* Unmask interrupts. It has to be done from each CPU */
3572 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
3574 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
3575 MVNETA_CAUSE_PHY_STATUS_CHANGE |
3576 MVNETA_CAUSE_LINK_CHANGE);
3578 phylink_start(pp->phylink);
3579 netif_tx_start_all_queues(pp->dev);
3581 clear_bit(__MVNETA_DOWN, &pp->state);
3584 static void mvneta_stop_dev(struct mvneta_port *pp)
3588 set_bit(__MVNETA_DOWN, &pp->state);
3590 phylink_stop(pp->phylink);
3592 if (!pp->neta_armada3700) {
3593 for_each_online_cpu(cpu) {
3594 struct mvneta_pcpu_port *port =
3595 per_cpu_ptr(pp->ports, cpu);
3597 napi_disable(&port->napi);
3600 napi_disable(&pp->napi);
3603 netif_carrier_off(pp->dev);
3605 mvneta_port_down(pp);
3606 netif_tx_stop_all_queues(pp->dev);
3608 /* Stop the port activity */
3609 mvneta_port_disable(pp);
3611 /* Clear all ethernet port interrupts */
3612 on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
3614 /* Mask all ethernet port interrupts */
3615 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
3617 mvneta_tx_reset(pp);
3618 mvneta_rx_reset(pp);
3620 WARN_ON(phy_power_off(pp->comphy));
3623 static void mvneta_percpu_enable(void *arg)
3625 struct mvneta_port *pp = arg;
3627 enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE);
3630 static void mvneta_percpu_disable(void *arg)
3632 struct mvneta_port *pp = arg;
3634 disable_percpu_irq(pp->dev->irq);
3637 /* Change the device mtu */
3638 static int mvneta_change_mtu(struct net_device *dev, int mtu)
3640 struct mvneta_port *pp = netdev_priv(dev);
3643 if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) {
3644 netdev_info(dev, "Illegal MTU value %d, rounding to %d\n",
3645 mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8));
3646 mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8);
3649 if (pp->xdp_prog && mtu > MVNETA_MAX_RX_BUF_SIZE) {
3650 netdev_info(dev, "Illegal MTU value %d for XDP mode\n", mtu);
3656 if (!netif_running(dev)) {
3658 mvneta_bm_update_mtu(pp, mtu);
3660 netdev_update_features(dev);
3664 /* The interface is running, so we have to force a
3665 * reallocation of the queues
3667 mvneta_stop_dev(pp);
3668 on_each_cpu(mvneta_percpu_disable, pp, true);
3670 mvneta_cleanup_txqs(pp);
3671 mvneta_cleanup_rxqs(pp);
3674 mvneta_bm_update_mtu(pp, mtu);
3676 pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu);
3678 ret = mvneta_setup_rxqs(pp);
3680 netdev_err(dev, "unable to setup rxqs after MTU change\n");
3684 ret = mvneta_setup_txqs(pp);
3686 netdev_err(dev, "unable to setup txqs after MTU change\n");
3690 on_each_cpu(mvneta_percpu_enable, pp, true);
3691 mvneta_start_dev(pp);
3693 netdev_update_features(dev);
3698 static netdev_features_t mvneta_fix_features(struct net_device *dev,
3699 netdev_features_t features)
3701 struct mvneta_port *pp = netdev_priv(dev);
3703 if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) {
3704 features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO);
3706 "Disable IP checksum for MTU greater than %dB\n",
3713 /* Get mac address */
3714 static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr)
3716 u32 mac_addr_l, mac_addr_h;
3718 mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW);
3719 mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH);
3720 addr[0] = (mac_addr_h >> 24) & 0xFF;
3721 addr[1] = (mac_addr_h >> 16) & 0xFF;
3722 addr[2] = (mac_addr_h >> 8) & 0xFF;
3723 addr[3] = mac_addr_h & 0xFF;
3724 addr[4] = (mac_addr_l >> 8) & 0xFF;
3725 addr[5] = mac_addr_l & 0xFF;
3728 /* Handle setting mac address */
3729 static int mvneta_set_mac_addr(struct net_device *dev, void *addr)
3731 struct mvneta_port *pp = netdev_priv(dev);
3732 struct sockaddr *sockaddr = addr;
3735 ret = eth_prepare_mac_addr_change(dev, addr);
3738 /* Remove previous address table entry */
3739 mvneta_mac_addr_set(pp, dev->dev_addr, -1);
3741 /* Set new addr in hw */
3742 mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def);
3744 eth_commit_mac_addr_change(dev, addr);
3748 static void mvneta_validate(struct phylink_config *config,
3749 unsigned long *supported,
3750 struct phylink_link_state *state)
3752 struct net_device *ndev = to_net_dev(config->dev);
3753 struct mvneta_port *pp = netdev_priv(ndev);
3754 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
3756 /* We only support QSGMII, SGMII, 802.3z and RGMII modes */
3757 if (state->interface != PHY_INTERFACE_MODE_NA &&
3758 state->interface != PHY_INTERFACE_MODE_QSGMII &&
3759 state->interface != PHY_INTERFACE_MODE_SGMII &&
3760 !phy_interface_mode_is_8023z(state->interface) &&
3761 !phy_interface_mode_is_rgmii(state->interface)) {
3762 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
3766 /* Allow all the expected bits */
3767 phylink_set(mask, Autoneg);
3768 phylink_set_port_modes(mask);
3770 /* Asymmetric pause is unsupported */
3771 phylink_set(mask, Pause);
3773 /* Half-duplex at speeds higher than 100Mbit is unsupported */
3774 if (pp->comphy || state->interface != PHY_INTERFACE_MODE_2500BASEX) {
3775 phylink_set(mask, 1000baseT_Full);
3776 phylink_set(mask, 1000baseX_Full);
3778 if (pp->comphy || state->interface == PHY_INTERFACE_MODE_2500BASEX) {
3779 phylink_set(mask, 2500baseT_Full);
3780 phylink_set(mask, 2500baseX_Full);
3783 if (!phy_interface_mode_is_8023z(state->interface)) {
3784 /* 10M and 100M are only supported in non-802.3z mode */
3785 phylink_set(mask, 10baseT_Half);
3786 phylink_set(mask, 10baseT_Full);
3787 phylink_set(mask, 100baseT_Half);
3788 phylink_set(mask, 100baseT_Full);
3791 bitmap_and(supported, supported, mask,
3792 __ETHTOOL_LINK_MODE_MASK_NBITS);
3793 bitmap_and(state->advertising, state->advertising, mask,
3794 __ETHTOOL_LINK_MODE_MASK_NBITS);
3796 /* We can only operate at 2500BaseX or 1000BaseX. If requested
3797 * to advertise both, only report advertising at 2500BaseX.
3799 phylink_helper_basex_speed(state);
3802 static void mvneta_mac_pcs_get_state(struct phylink_config *config,
3803 struct phylink_link_state *state)
3805 struct net_device *ndev = to_net_dev(config->dev);
3806 struct mvneta_port *pp = netdev_priv(ndev);
3809 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
3811 if (gmac_stat & MVNETA_GMAC_SPEED_1000)
3813 state->interface == PHY_INTERFACE_MODE_2500BASEX ?
3814 SPEED_2500 : SPEED_1000;
3815 else if (gmac_stat & MVNETA_GMAC_SPEED_100)
3816 state->speed = SPEED_100;
3818 state->speed = SPEED_10;
3820 state->an_complete = !!(gmac_stat & MVNETA_GMAC_AN_COMPLETE);
3821 state->link = !!(gmac_stat & MVNETA_GMAC_LINK_UP);
3822 state->duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX);
3825 if (gmac_stat & MVNETA_GMAC_RX_FLOW_CTRL_ENABLE)
3826 state->pause |= MLO_PAUSE_RX;
3827 if (gmac_stat & MVNETA_GMAC_TX_FLOW_CTRL_ENABLE)
3828 state->pause |= MLO_PAUSE_TX;
3831 static void mvneta_mac_an_restart(struct phylink_config *config)
3833 struct net_device *ndev = to_net_dev(config->dev);
3834 struct mvneta_port *pp = netdev_priv(ndev);
3835 u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3837 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
3838 gmac_an | MVNETA_GMAC_INBAND_RESTART_AN);
3839 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
3840 gmac_an & ~MVNETA_GMAC_INBAND_RESTART_AN);
3843 static void mvneta_mac_config(struct phylink_config *config, unsigned int mode,
3844 const struct phylink_link_state *state)
3846 struct net_device *ndev = to_net_dev(config->dev);
3847 struct mvneta_port *pp = netdev_priv(ndev);
3848 u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
3849 u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
3850 u32 new_ctrl4, gmac_ctrl4 = mvreg_read(pp, MVNETA_GMAC_CTRL_4);
3851 u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
3852 u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3854 new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X;
3855 new_ctrl2 = gmac_ctrl2 & ~(MVNETA_GMAC2_INBAND_AN_ENABLE |
3856 MVNETA_GMAC2_PORT_RESET);
3857 new_ctrl4 = gmac_ctrl4 & ~(MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE);
3858 new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE;
3859 new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE |
3860 MVNETA_GMAC_INBAND_RESTART_AN |
3861 MVNETA_GMAC_AN_SPEED_EN |
3862 MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL |
3863 MVNETA_GMAC_AN_FLOW_CTRL_EN |
3864 MVNETA_GMAC_AN_DUPLEX_EN);
3866 /* Even though it might look weird, when we're configured in
3867 * SGMII or QSGMII mode, the RGMII bit needs to be set.
3869 new_ctrl2 |= MVNETA_GMAC2_PORT_RGMII;
3871 if (state->interface == PHY_INTERFACE_MODE_QSGMII ||
3872 state->interface == PHY_INTERFACE_MODE_SGMII ||
3873 phy_interface_mode_is_8023z(state->interface))
3874 new_ctrl2 |= MVNETA_GMAC2_PCS_ENABLE;
3876 if (phylink_test(state->advertising, Pause))
3877 new_an |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL;
3879 if (!phylink_autoneg_inband(mode)) {
3880 /* Phy or fixed speed - nothing to do, leave the
3881 * configured speed, duplex and flow control as-is.
3883 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
3884 /* SGMII mode receives the state from the PHY */
3885 new_ctrl2 |= MVNETA_GMAC2_INBAND_AN_ENABLE;
3886 new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
3887 new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN |
3888 MVNETA_GMAC_FORCE_LINK_PASS |
3889 MVNETA_GMAC_CONFIG_MII_SPEED |
3890 MVNETA_GMAC_CONFIG_GMII_SPEED |
3891 MVNETA_GMAC_CONFIG_FULL_DUPLEX)) |
3892 MVNETA_GMAC_INBAND_AN_ENABLE |
3893 MVNETA_GMAC_AN_SPEED_EN |
3894 MVNETA_GMAC_AN_DUPLEX_EN;
3896 /* 802.3z negotiation - only 1000base-X */
3897 new_ctrl0 |= MVNETA_GMAC0_PORT_1000BASE_X;
3898 new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
3899 new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN |
3900 MVNETA_GMAC_FORCE_LINK_PASS |
3901 MVNETA_GMAC_CONFIG_MII_SPEED)) |
3902 MVNETA_GMAC_INBAND_AN_ENABLE |
3903 MVNETA_GMAC_CONFIG_GMII_SPEED |
3904 /* The MAC only supports FD mode */
3905 MVNETA_GMAC_CONFIG_FULL_DUPLEX;
3907 if (state->pause & MLO_PAUSE_AN && state->an_enabled)
3908 new_an |= MVNETA_GMAC_AN_FLOW_CTRL_EN;
3911 /* Armada 370 documentation says we can only change the port mode
3912 * and in-band enable when the link is down, so force it down
3913 * while making these changes. We also do this for GMAC_CTRL2 */
3914 if ((new_ctrl0 ^ gmac_ctrl0) & MVNETA_GMAC0_PORT_1000BASE_X ||
3915 (new_ctrl2 ^ gmac_ctrl2) & MVNETA_GMAC2_INBAND_AN_ENABLE ||
3916 (new_an ^ gmac_an) & MVNETA_GMAC_INBAND_AN_ENABLE) {
3917 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
3918 (gmac_an & ~MVNETA_GMAC_FORCE_LINK_PASS) |
3919 MVNETA_GMAC_FORCE_LINK_DOWN);
3923 /* When at 2.5G, the link partner can send frames with shortened
3926 if (state->speed == SPEED_2500)
3927 new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE;
3929 if (pp->comphy && pp->phy_interface != state->interface &&
3930 (state->interface == PHY_INTERFACE_MODE_SGMII ||
3931 state->interface == PHY_INTERFACE_MODE_1000BASEX ||
3932 state->interface == PHY_INTERFACE_MODE_2500BASEX)) {
3933 pp->phy_interface = state->interface;
3935 WARN_ON(phy_power_off(pp->comphy));
3936 WARN_ON(mvneta_comphy_init(pp));
3939 if (new_ctrl0 != gmac_ctrl0)
3940 mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0);
3941 if (new_ctrl2 != gmac_ctrl2)
3942 mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2);
3943 if (new_ctrl4 != gmac_ctrl4)
3944 mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4);
3945 if (new_clk != gmac_clk)
3946 mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk);
3947 if (new_an != gmac_an)
3948 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an);
3950 if (gmac_ctrl2 & MVNETA_GMAC2_PORT_RESET) {
3951 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
3952 MVNETA_GMAC2_PORT_RESET) != 0)
3957 static void mvneta_set_eee(struct mvneta_port *pp, bool enable)
3961 lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1);
3963 lpi_ctl1 |= MVNETA_LPI_REQUEST_ENABLE;
3965 lpi_ctl1 &= ~MVNETA_LPI_REQUEST_ENABLE;
3966 mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1);
3969 static void mvneta_mac_link_down(struct phylink_config *config,
3970 unsigned int mode, phy_interface_t interface)
3972 struct net_device *ndev = to_net_dev(config->dev);
3973 struct mvneta_port *pp = netdev_priv(ndev);
3976 mvneta_port_down(pp);
3978 if (!phylink_autoneg_inband(mode)) {
3979 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3980 val &= ~MVNETA_GMAC_FORCE_LINK_PASS;
3981 val |= MVNETA_GMAC_FORCE_LINK_DOWN;
3982 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
3985 pp->eee_active = false;
3986 mvneta_set_eee(pp, false);
3989 static void mvneta_mac_link_up(struct phylink_config *config,
3990 struct phy_device *phy,
3991 unsigned int mode, phy_interface_t interface,
3992 int speed, int duplex,
3993 bool tx_pause, bool rx_pause)
3995 struct net_device *ndev = to_net_dev(config->dev);
3996 struct mvneta_port *pp = netdev_priv(ndev);
3999 if (!phylink_autoneg_inband(mode)) {
4000 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
4001 val &= ~(MVNETA_GMAC_FORCE_LINK_DOWN |
4002 MVNETA_GMAC_CONFIG_MII_SPEED |
4003 MVNETA_GMAC_CONFIG_GMII_SPEED |
4004 MVNETA_GMAC_CONFIG_FLOW_CTRL |
4005 MVNETA_GMAC_CONFIG_FULL_DUPLEX);
4006 val |= MVNETA_GMAC_FORCE_LINK_PASS;
4008 if (speed == SPEED_1000 || speed == SPEED_2500)
4009 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
4010 else if (speed == SPEED_100)
4011 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
4013 if (duplex == DUPLEX_FULL)
4014 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
4016 if (tx_pause || rx_pause)
4017 val |= MVNETA_GMAC_CONFIG_FLOW_CTRL;
4019 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
4021 /* When inband doesn't cover flow control or flow control is
4022 * disabled, we need to manually configure it. This bit will
4023 * only have effect if MVNETA_GMAC_AN_FLOW_CTRL_EN is unset.
4025 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
4026 val &= ~MVNETA_GMAC_CONFIG_FLOW_CTRL;
4028 if (tx_pause || rx_pause)
4029 val |= MVNETA_GMAC_CONFIG_FLOW_CTRL;
4031 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
4036 if (phy && pp->eee_enabled) {
4037 pp->eee_active = phy_init_eee(phy, 0) >= 0;
4038 mvneta_set_eee(pp, pp->eee_active && pp->tx_lpi_enabled);
4042 static const struct phylink_mac_ops mvneta_phylink_ops = {
4043 .validate = mvneta_validate,
4044 .mac_pcs_get_state = mvneta_mac_pcs_get_state,
4045 .mac_an_restart = mvneta_mac_an_restart,
4046 .mac_config = mvneta_mac_config,
4047 .mac_link_down = mvneta_mac_link_down,
4048 .mac_link_up = mvneta_mac_link_up,
4051 static int mvneta_mdio_probe(struct mvneta_port *pp)
4053 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL };
4054 int err = phylink_of_phy_connect(pp->phylink, pp->dn, 0);
4057 netdev_err(pp->dev, "could not attach PHY: %d\n", err);
4059 phylink_ethtool_get_wol(pp->phylink, &wol);
4060 device_set_wakeup_capable(&pp->dev->dev, !!wol.supported);
4065 static void mvneta_mdio_remove(struct mvneta_port *pp)
4067 phylink_disconnect_phy(pp->phylink);
4070 /* Electing a CPU must be done in an atomic way: it should be done
4071 * after or before the removal/insertion of a CPU and this function is
4074 static void mvneta_percpu_elect(struct mvneta_port *pp)
4076 int elected_cpu = 0, max_cpu, cpu, i = 0;
4078 /* Use the cpu associated to the rxq when it is online, in all
4079 * the other cases, use the cpu 0 which can't be offline.
4081 if (cpu_online(pp->rxq_def))
4082 elected_cpu = pp->rxq_def;
4084 max_cpu = num_present_cpus();
4086 for_each_online_cpu(cpu) {
4087 int rxq_map = 0, txq_map = 0;
4090 for (rxq = 0; rxq < rxq_number; rxq++)
4091 if ((rxq % max_cpu) == cpu)
4092 rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
4094 if (cpu == elected_cpu)
4095 /* Map the default receive queue queue to the
4098 rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def);
4100 /* We update the TX queue map only if we have one
4101 * queue. In this case we associate the TX queue to
4102 * the CPU bound to the default RX queue
4104 if (txq_number == 1)
4105 txq_map = (cpu == elected_cpu) ?
4106 MVNETA_CPU_TXQ_ACCESS(1) : 0;
4108 txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) &
4109 MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
4111 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
4113 /* Update the interrupt mask on each CPU according the
4116 smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt,
4123 static int mvneta_cpu_online(unsigned int cpu, struct hlist_node *node)
4126 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
4128 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
4131 spin_lock(&pp->lock);
4133 * Configuring the driver for a new CPU while the driver is
4134 * stopping is racy, so just avoid it.
4136 if (pp->is_stopped) {
4137 spin_unlock(&pp->lock);
4140 netif_tx_stop_all_queues(pp->dev);
4143 * We have to synchronise on tha napi of each CPU except the one
4144 * just being woken up
4146 for_each_online_cpu(other_cpu) {
4147 if (other_cpu != cpu) {
4148 struct mvneta_pcpu_port *other_port =
4149 per_cpu_ptr(pp->ports, other_cpu);
4151 napi_synchronize(&other_port->napi);
4155 /* Mask all ethernet port interrupts */
4156 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
4157 napi_enable(&port->napi);
4160 * Enable per-CPU interrupts on the CPU that is
4163 mvneta_percpu_enable(pp);
4166 * Enable per-CPU interrupt on the one CPU we care
4169 mvneta_percpu_elect(pp);
4171 /* Unmask all ethernet port interrupts */
4172 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
4173 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
4174 MVNETA_CAUSE_PHY_STATUS_CHANGE |
4175 MVNETA_CAUSE_LINK_CHANGE);
4176 netif_tx_start_all_queues(pp->dev);
4177 spin_unlock(&pp->lock);
4181 static int mvneta_cpu_down_prepare(unsigned int cpu, struct hlist_node *node)
4183 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
4185 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
4188 * Thanks to this lock we are sure that any pending cpu election is
4191 spin_lock(&pp->lock);
4192 /* Mask all ethernet port interrupts */
4193 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
4194 spin_unlock(&pp->lock);
4196 napi_synchronize(&port->napi);
4197 napi_disable(&port->napi);
4198 /* Disable per-CPU interrupts on the CPU that is brought down. */
4199 mvneta_percpu_disable(pp);
4203 static int mvneta_cpu_dead(unsigned int cpu, struct hlist_node *node)
4205 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
4208 /* Check if a new CPU must be elected now this on is down */
4209 spin_lock(&pp->lock);
4210 mvneta_percpu_elect(pp);
4211 spin_unlock(&pp->lock);
4212 /* Unmask all ethernet port interrupts */
4213 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
4214 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
4215 MVNETA_CAUSE_PHY_STATUS_CHANGE |
4216 MVNETA_CAUSE_LINK_CHANGE);
4217 netif_tx_start_all_queues(pp->dev);
4221 static int mvneta_open(struct net_device *dev)
4223 struct mvneta_port *pp = netdev_priv(dev);
4226 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
4228 ret = mvneta_setup_rxqs(pp);
4232 ret = mvneta_setup_txqs(pp);
4234 goto err_cleanup_rxqs;
4236 /* Connect to port interrupt line */
4237 if (pp->neta_armada3700)
4238 ret = request_irq(pp->dev->irq, mvneta_isr, 0,
4241 ret = request_percpu_irq(pp->dev->irq, mvneta_percpu_isr,
4242 dev->name, pp->ports);
4244 netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq);
4245 goto err_cleanup_txqs;
4248 if (!pp->neta_armada3700) {
4249 /* Enable per-CPU interrupt on all the CPU to handle our RX
4252 on_each_cpu(mvneta_percpu_enable, pp, true);
4254 pp->is_stopped = false;
4255 /* Register a CPU notifier to handle the case where our CPU
4256 * might be taken offline.
4258 ret = cpuhp_state_add_instance_nocalls(online_hpstate,
4263 ret = cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
4266 goto err_free_online_hp;
4269 ret = mvneta_mdio_probe(pp);
4271 netdev_err(dev, "cannot probe MDIO bus\n");
4272 goto err_free_dead_hp;
4275 mvneta_start_dev(pp);
4280 if (!pp->neta_armada3700)
4281 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
4284 if (!pp->neta_armada3700)
4285 cpuhp_state_remove_instance_nocalls(online_hpstate,
4288 if (pp->neta_armada3700) {
4289 free_irq(pp->dev->irq, pp);
4291 on_each_cpu(mvneta_percpu_disable, pp, true);
4292 free_percpu_irq(pp->dev->irq, pp->ports);
4295 mvneta_cleanup_txqs(pp);
4297 mvneta_cleanup_rxqs(pp);
4301 /* Stop the port, free port interrupt line */
4302 static int mvneta_stop(struct net_device *dev)
4304 struct mvneta_port *pp = netdev_priv(dev);
4306 if (!pp->neta_armada3700) {
4307 /* Inform that we are stopping so we don't want to setup the
4308 * driver for new CPUs in the notifiers. The code of the
4309 * notifier for CPU online is protected by the same spinlock,
4310 * so when we get the lock, the notifer work is done.
4312 spin_lock(&pp->lock);
4313 pp->is_stopped = true;
4314 spin_unlock(&pp->lock);
4316 mvneta_stop_dev(pp);
4317 mvneta_mdio_remove(pp);
4319 cpuhp_state_remove_instance_nocalls(online_hpstate,
4321 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
4323 on_each_cpu(mvneta_percpu_disable, pp, true);
4324 free_percpu_irq(dev->irq, pp->ports);
4326 mvneta_stop_dev(pp);
4327 mvneta_mdio_remove(pp);
4328 free_irq(dev->irq, pp);
4331 mvneta_cleanup_rxqs(pp);
4332 mvneta_cleanup_txqs(pp);
4337 static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4339 struct mvneta_port *pp = netdev_priv(dev);
4341 return phylink_mii_ioctl(pp->phylink, ifr, cmd);
4344 static int mvneta_xdp_setup(struct net_device *dev, struct bpf_prog *prog,
4345 struct netlink_ext_ack *extack)
4347 bool need_update, running = netif_running(dev);
4348 struct mvneta_port *pp = netdev_priv(dev);
4349 struct bpf_prog *old_prog;
4351 if (prog && dev->mtu > MVNETA_MAX_RX_BUF_SIZE) {
4352 NL_SET_ERR_MSG_MOD(extack, "Jumbo frames not supported on XDP");
4357 NL_SET_ERR_MSG_MOD(extack,
4358 "Hardware Buffer Management not supported on XDP");
4362 need_update = !!pp->xdp_prog != !!prog;
4363 if (running && need_update)
4366 old_prog = xchg(&pp->xdp_prog, prog);
4368 bpf_prog_put(old_prog);
4370 if (running && need_update)
4371 return mvneta_open(dev);
4376 static int mvneta_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4378 struct mvneta_port *pp = netdev_priv(dev);
4380 switch (xdp->command) {
4381 case XDP_SETUP_PROG:
4382 return mvneta_xdp_setup(dev, xdp->prog, xdp->extack);
4383 case XDP_QUERY_PROG:
4384 xdp->prog_id = pp->xdp_prog ? pp->xdp_prog->aux->id : 0;
4391 /* Ethtool methods */
4393 /* Set link ksettings (phy address, speed) for ethtools */
4395 mvneta_ethtool_set_link_ksettings(struct net_device *ndev,
4396 const struct ethtool_link_ksettings *cmd)
4398 struct mvneta_port *pp = netdev_priv(ndev);
4400 return phylink_ethtool_ksettings_set(pp->phylink, cmd);
4403 /* Get link ksettings for ethtools */
4405 mvneta_ethtool_get_link_ksettings(struct net_device *ndev,
4406 struct ethtool_link_ksettings *cmd)
4408 struct mvneta_port *pp = netdev_priv(ndev);
4410 return phylink_ethtool_ksettings_get(pp->phylink, cmd);
4413 static int mvneta_ethtool_nway_reset(struct net_device *dev)
4415 struct mvneta_port *pp = netdev_priv(dev);
4417 return phylink_ethtool_nway_reset(pp->phylink);
4420 /* Set interrupt coalescing for ethtools */
4421 static int mvneta_ethtool_set_coalesce(struct net_device *dev,
4422 struct ethtool_coalesce *c)
4424 struct mvneta_port *pp = netdev_priv(dev);
4427 for (queue = 0; queue < rxq_number; queue++) {
4428 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
4429 rxq->time_coal = c->rx_coalesce_usecs;
4430 rxq->pkts_coal = c->rx_max_coalesced_frames;
4431 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
4432 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
4435 for (queue = 0; queue < txq_number; queue++) {
4436 struct mvneta_tx_queue *txq = &pp->txqs[queue];
4437 txq->done_pkts_coal = c->tx_max_coalesced_frames;
4438 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
4444 /* get coalescing for ethtools */
4445 static int mvneta_ethtool_get_coalesce(struct net_device *dev,
4446 struct ethtool_coalesce *c)
4448 struct mvneta_port *pp = netdev_priv(dev);
4450 c->rx_coalesce_usecs = pp->rxqs[0].time_coal;
4451 c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal;
4453 c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal;
4458 static void mvneta_ethtool_get_drvinfo(struct net_device *dev,
4459 struct ethtool_drvinfo *drvinfo)
4461 strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME,
4462 sizeof(drvinfo->driver));
4463 strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION,
4464 sizeof(drvinfo->version));
4465 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
4466 sizeof(drvinfo->bus_info));
4470 static void mvneta_ethtool_get_ringparam(struct net_device *netdev,
4471 struct ethtool_ringparam *ring)
4473 struct mvneta_port *pp = netdev_priv(netdev);
4475 ring->rx_max_pending = MVNETA_MAX_RXD;
4476 ring->tx_max_pending = MVNETA_MAX_TXD;
4477 ring->rx_pending = pp->rx_ring_size;
4478 ring->tx_pending = pp->tx_ring_size;
4481 static int mvneta_ethtool_set_ringparam(struct net_device *dev,
4482 struct ethtool_ringparam *ring)
4484 struct mvneta_port *pp = netdev_priv(dev);
4486 if ((ring->rx_pending == 0) || (ring->tx_pending == 0))
4488 pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ?
4489 ring->rx_pending : MVNETA_MAX_RXD;
4491 pp->tx_ring_size = clamp_t(u16, ring->tx_pending,
4492 MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD);
4493 if (pp->tx_ring_size != ring->tx_pending)
4494 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
4495 pp->tx_ring_size, ring->tx_pending);
4497 if (netif_running(dev)) {
4499 if (mvneta_open(dev)) {
4501 "error on opening device after ring param change\n");
4509 static void mvneta_ethtool_get_pauseparam(struct net_device *dev,
4510 struct ethtool_pauseparam *pause)
4512 struct mvneta_port *pp = netdev_priv(dev);
4514 phylink_ethtool_get_pauseparam(pp->phylink, pause);
4517 static int mvneta_ethtool_set_pauseparam(struct net_device *dev,
4518 struct ethtool_pauseparam *pause)
4520 struct mvneta_port *pp = netdev_priv(dev);
4522 return phylink_ethtool_set_pauseparam(pp->phylink, pause);
4525 static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset,
4528 if (sset == ETH_SS_STATS) {
4531 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
4532 memcpy(data + i * ETH_GSTRING_LEN,
4533 mvneta_statistics[i].name, ETH_GSTRING_LEN);
4538 mvneta_ethtool_update_pcpu_stats(struct mvneta_port *pp,
4539 struct mvneta_ethtool_stats *es)
4544 for_each_possible_cpu(cpu) {
4545 struct mvneta_pcpu_stats *stats;
4546 u64 skb_alloc_error;
4556 stats = per_cpu_ptr(pp->stats, cpu);
4558 start = u64_stats_fetch_begin_irq(&stats->syncp);
4559 skb_alloc_error = stats->es.skb_alloc_error;
4560 refill_error = stats->es.refill_error;
4561 xdp_redirect = stats->es.ps.xdp_redirect;
4562 xdp_pass = stats->es.ps.xdp_pass;
4563 xdp_drop = stats->es.ps.xdp_drop;
4564 xdp_xmit = stats->es.ps.xdp_xmit;
4565 xdp_xmit_err = stats->es.ps.xdp_xmit_err;
4566 xdp_tx = stats->es.ps.xdp_tx;
4567 xdp_tx_err = stats->es.ps.xdp_tx_err;
4568 } while (u64_stats_fetch_retry_irq(&stats->syncp, start));
4570 es->skb_alloc_error += skb_alloc_error;
4571 es->refill_error += refill_error;
4572 es->ps.xdp_redirect += xdp_redirect;
4573 es->ps.xdp_pass += xdp_pass;
4574 es->ps.xdp_drop += xdp_drop;
4575 es->ps.xdp_xmit += xdp_xmit;
4576 es->ps.xdp_xmit_err += xdp_xmit_err;
4577 es->ps.xdp_tx += xdp_tx;
4578 es->ps.xdp_tx_err += xdp_tx_err;
4582 static void mvneta_ethtool_update_stats(struct mvneta_port *pp)
4584 struct mvneta_ethtool_stats stats = {};
4585 const struct mvneta_statistic *s;
4586 void __iomem *base = pp->base;
4591 mvneta_ethtool_update_pcpu_stats(pp, &stats);
4592 for (i = 0, s = mvneta_statistics;
4593 s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics);
4597 val = readl_relaxed(base + s->offset);
4598 pp->ethtool_stats[i] += val;
4601 /* Docs say to read low 32-bit then high */
4602 low = readl_relaxed(base + s->offset);
4603 high = readl_relaxed(base + s->offset + 4);
4604 val = (u64)high << 32 | low;
4605 pp->ethtool_stats[i] += val;
4608 switch (s->offset) {
4609 case ETHTOOL_STAT_EEE_WAKEUP:
4610 val = phylink_get_eee_err(pp->phylink);
4611 pp->ethtool_stats[i] += val;
4613 case ETHTOOL_STAT_SKB_ALLOC_ERR:
4614 pp->ethtool_stats[i] = stats.skb_alloc_error;
4616 case ETHTOOL_STAT_REFILL_ERR:
4617 pp->ethtool_stats[i] = stats.refill_error;
4619 case ETHTOOL_XDP_REDIRECT:
4620 pp->ethtool_stats[i] = stats.ps.xdp_redirect;
4622 case ETHTOOL_XDP_PASS:
4623 pp->ethtool_stats[i] = stats.ps.xdp_pass;
4625 case ETHTOOL_XDP_DROP:
4626 pp->ethtool_stats[i] = stats.ps.xdp_drop;
4628 case ETHTOOL_XDP_TX:
4629 pp->ethtool_stats[i] = stats.ps.xdp_tx;
4631 case ETHTOOL_XDP_TX_ERR:
4632 pp->ethtool_stats[i] = stats.ps.xdp_tx_err;
4634 case ETHTOOL_XDP_XMIT:
4635 pp->ethtool_stats[i] = stats.ps.xdp_xmit;
4637 case ETHTOOL_XDP_XMIT_ERR:
4638 pp->ethtool_stats[i] = stats.ps.xdp_xmit_err;
4646 static void mvneta_ethtool_get_stats(struct net_device *dev,
4647 struct ethtool_stats *stats, u64 *data)
4649 struct mvneta_port *pp = netdev_priv(dev);
4652 mvneta_ethtool_update_stats(pp);
4654 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
4655 *data++ = pp->ethtool_stats[i];
4658 static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset)
4660 if (sset == ETH_SS_STATS)
4661 return ARRAY_SIZE(mvneta_statistics);
4665 static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev)
4667 return MVNETA_RSS_LU_TABLE_SIZE;
4670 static int mvneta_ethtool_get_rxnfc(struct net_device *dev,
4671 struct ethtool_rxnfc *info,
4672 u32 *rules __always_unused)
4674 switch (info->cmd) {
4675 case ETHTOOL_GRXRINGS:
4676 info->data = rxq_number;
4685 static int mvneta_config_rss(struct mvneta_port *pp)
4690 netif_tx_stop_all_queues(pp->dev);
4692 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
4694 if (!pp->neta_armada3700) {
4695 /* We have to synchronise on the napi of each CPU */
4696 for_each_online_cpu(cpu) {
4697 struct mvneta_pcpu_port *pcpu_port =
4698 per_cpu_ptr(pp->ports, cpu);
4700 napi_synchronize(&pcpu_port->napi);
4701 napi_disable(&pcpu_port->napi);
4704 napi_synchronize(&pp->napi);
4705 napi_disable(&pp->napi);
4708 pp->rxq_def = pp->indir[0];
4710 /* Update unicast mapping */
4711 mvneta_set_rx_mode(pp->dev);
4713 /* Update val of portCfg register accordingly with all RxQueue types */
4714 val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def);
4715 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
4717 /* Update the elected CPU matching the new rxq_def */
4718 spin_lock(&pp->lock);
4719 mvneta_percpu_elect(pp);
4720 spin_unlock(&pp->lock);
4722 if (!pp->neta_armada3700) {
4723 /* We have to synchronise on the napi of each CPU */
4724 for_each_online_cpu(cpu) {
4725 struct mvneta_pcpu_port *pcpu_port =
4726 per_cpu_ptr(pp->ports, cpu);
4728 napi_enable(&pcpu_port->napi);
4731 napi_enable(&pp->napi);
4734 netif_tx_start_all_queues(pp->dev);
4739 static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,
4740 const u8 *key, const u8 hfunc)
4742 struct mvneta_port *pp = netdev_priv(dev);
4744 /* Current code for Armada 3700 doesn't support RSS features yet */
4745 if (pp->neta_armada3700)
4748 /* We require at least one supported parameter to be changed
4749 * and no change in any of the unsupported parameters
4752 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
4758 memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE);
4760 return mvneta_config_rss(pp);
4763 static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
4766 struct mvneta_port *pp = netdev_priv(dev);
4768 /* Current code for Armada 3700 doesn't support RSS features yet */
4769 if (pp->neta_armada3700)
4773 *hfunc = ETH_RSS_HASH_TOP;
4778 memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE);
4783 static void mvneta_ethtool_get_wol(struct net_device *dev,
4784 struct ethtool_wolinfo *wol)
4786 struct mvneta_port *pp = netdev_priv(dev);
4788 phylink_ethtool_get_wol(pp->phylink, wol);
4791 static int mvneta_ethtool_set_wol(struct net_device *dev,
4792 struct ethtool_wolinfo *wol)
4794 struct mvneta_port *pp = netdev_priv(dev);
4797 ret = phylink_ethtool_set_wol(pp->phylink, wol);
4799 device_set_wakeup_enable(&dev->dev, !!wol->wolopts);
4804 static int mvneta_ethtool_get_eee(struct net_device *dev,
4805 struct ethtool_eee *eee)
4807 struct mvneta_port *pp = netdev_priv(dev);
4810 lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0);
4812 eee->eee_enabled = pp->eee_enabled;
4813 eee->eee_active = pp->eee_active;
4814 eee->tx_lpi_enabled = pp->tx_lpi_enabled;
4815 eee->tx_lpi_timer = (lpi_ctl0) >> 8; // * scale;
4817 return phylink_ethtool_get_eee(pp->phylink, eee);
4820 static int mvneta_ethtool_set_eee(struct net_device *dev,
4821 struct ethtool_eee *eee)
4823 struct mvneta_port *pp = netdev_priv(dev);
4826 /* The Armada 37x documents do not give limits for this other than
4827 * it being an 8-bit register. */
4828 if (eee->tx_lpi_enabled && eee->tx_lpi_timer > 255)
4831 lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0);
4832 lpi_ctl0 &= ~(0xff << 8);
4833 lpi_ctl0 |= eee->tx_lpi_timer << 8;
4834 mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0);
4836 pp->eee_enabled = eee->eee_enabled;
4837 pp->tx_lpi_enabled = eee->tx_lpi_enabled;
4839 mvneta_set_eee(pp, eee->tx_lpi_enabled && eee->eee_enabled);
4841 return phylink_ethtool_set_eee(pp->phylink, eee);
4844 static const struct net_device_ops mvneta_netdev_ops = {
4845 .ndo_open = mvneta_open,
4846 .ndo_stop = mvneta_stop,
4847 .ndo_start_xmit = mvneta_tx,
4848 .ndo_set_rx_mode = mvneta_set_rx_mode,
4849 .ndo_set_mac_address = mvneta_set_mac_addr,
4850 .ndo_change_mtu = mvneta_change_mtu,
4851 .ndo_fix_features = mvneta_fix_features,
4852 .ndo_get_stats64 = mvneta_get_stats64,
4853 .ndo_do_ioctl = mvneta_ioctl,
4854 .ndo_bpf = mvneta_xdp,
4855 .ndo_xdp_xmit = mvneta_xdp_xmit,
4858 static const struct ethtool_ops mvneta_eth_tool_ops = {
4859 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS |
4860 ETHTOOL_COALESCE_MAX_FRAMES,
4861 .nway_reset = mvneta_ethtool_nway_reset,
4862 .get_link = ethtool_op_get_link,
4863 .set_coalesce = mvneta_ethtool_set_coalesce,
4864 .get_coalesce = mvneta_ethtool_get_coalesce,
4865 .get_drvinfo = mvneta_ethtool_get_drvinfo,
4866 .get_ringparam = mvneta_ethtool_get_ringparam,
4867 .set_ringparam = mvneta_ethtool_set_ringparam,
4868 .get_pauseparam = mvneta_ethtool_get_pauseparam,
4869 .set_pauseparam = mvneta_ethtool_set_pauseparam,
4870 .get_strings = mvneta_ethtool_get_strings,
4871 .get_ethtool_stats = mvneta_ethtool_get_stats,
4872 .get_sset_count = mvneta_ethtool_get_sset_count,
4873 .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size,
4874 .get_rxnfc = mvneta_ethtool_get_rxnfc,
4875 .get_rxfh = mvneta_ethtool_get_rxfh,
4876 .set_rxfh = mvneta_ethtool_set_rxfh,
4877 .get_link_ksettings = mvneta_ethtool_get_link_ksettings,
4878 .set_link_ksettings = mvneta_ethtool_set_link_ksettings,
4879 .get_wol = mvneta_ethtool_get_wol,
4880 .set_wol = mvneta_ethtool_set_wol,
4881 .get_eee = mvneta_ethtool_get_eee,
4882 .set_eee = mvneta_ethtool_set_eee,
4886 static int mvneta_init(struct device *dev, struct mvneta_port *pp)
4891 mvneta_port_disable(pp);
4893 /* Set port default values */
4894 mvneta_defaults_set(pp);
4896 pp->txqs = devm_kcalloc(dev, txq_number, sizeof(*pp->txqs), GFP_KERNEL);
4900 /* Initialize TX descriptor rings */
4901 for (queue = 0; queue < txq_number; queue++) {
4902 struct mvneta_tx_queue *txq = &pp->txqs[queue];
4904 txq->size = pp->tx_ring_size;
4905 txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS;
4908 pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*pp->rxqs), GFP_KERNEL);
4912 /* Create Rx descriptor rings */
4913 for (queue = 0; queue < rxq_number; queue++) {
4914 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
4916 rxq->size = pp->rx_ring_size;
4917 rxq->pkts_coal = MVNETA_RX_COAL_PKTS;
4918 rxq->time_coal = MVNETA_RX_COAL_USEC;
4920 = devm_kmalloc_array(pp->dev->dev.parent,
4922 sizeof(*rxq->buf_virt_addr),
4924 if (!rxq->buf_virt_addr)
4931 /* platform glue : initialize decoding windows */
4932 static void mvneta_conf_mbus_windows(struct mvneta_port *pp,
4933 const struct mbus_dram_target_info *dram)
4939 for (i = 0; i < 6; i++) {
4940 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
4941 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
4944 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
4951 for (i = 0; i < dram->num_cs; i++) {
4952 const struct mbus_dram_window *cs = dram->cs + i;
4954 mvreg_write(pp, MVNETA_WIN_BASE(i),
4955 (cs->base & 0xffff0000) |
4956 (cs->mbus_attr << 8) |
4957 dram->mbus_dram_target_id);
4959 mvreg_write(pp, MVNETA_WIN_SIZE(i),
4960 (cs->size - 1) & 0xffff0000);
4962 win_enable &= ~(1 << i);
4963 win_protect |= 3 << (2 * i);
4966 /* For Armada3700 open default 4GB Mbus window, leaving
4967 * arbitration of target/attribute to a different layer
4970 mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000);
4971 win_enable &= ~BIT(0);
4975 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
4976 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
4979 /* Power up the port */
4980 static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
4982 /* MAC Cause register should be cleared */
4983 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
4985 if (phy_mode == PHY_INTERFACE_MODE_QSGMII)
4986 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
4987 else if (phy_mode == PHY_INTERFACE_MODE_SGMII ||
4988 phy_interface_mode_is_8023z(phy_mode))
4989 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
4990 else if (!phy_interface_mode_is_rgmii(phy_mode))
4996 /* Device initialization routine */
4997 static int mvneta_probe(struct platform_device *pdev)
4999 struct device_node *dn = pdev->dev.of_node;
5000 struct device_node *bm_node;
5001 struct mvneta_port *pp;
5002 struct net_device *dev;
5003 struct phylink *phylink;
5005 const char *dt_mac_addr;
5006 char hw_mac_addr[ETH_ALEN];
5007 phy_interface_t phy_mode;
5008 const char *mac_from;
5013 dev = devm_alloc_etherdev_mqs(&pdev->dev, sizeof(struct mvneta_port),
5014 txq_number, rxq_number);
5018 dev->irq = irq_of_parse_and_map(dn, 0);
5022 err = of_get_phy_mode(dn, &phy_mode);
5024 dev_err(&pdev->dev, "incorrect phy-mode\n");
5028 comphy = devm_of_phy_get(&pdev->dev, dn, NULL);
5029 if (comphy == ERR_PTR(-EPROBE_DEFER)) {
5030 err = -EPROBE_DEFER;
5032 } else if (IS_ERR(comphy)) {
5036 pp = netdev_priv(dev);
5037 spin_lock_init(&pp->lock);
5039 pp->phylink_config.dev = &dev->dev;
5040 pp->phylink_config.type = PHYLINK_NETDEV;
5042 phylink = phylink_create(&pp->phylink_config, pdev->dev.fwnode,
5043 phy_mode, &mvneta_phylink_ops);
5044 if (IS_ERR(phylink)) {
5045 err = PTR_ERR(phylink);
5049 dev->tx_queue_len = MVNETA_MAX_TXD;
5050 dev->watchdog_timeo = 5 * HZ;
5051 dev->netdev_ops = &mvneta_netdev_ops;
5053 dev->ethtool_ops = &mvneta_eth_tool_ops;
5055 pp->phylink = phylink;
5056 pp->comphy = comphy;
5057 pp->phy_interface = phy_mode;
5060 pp->rxq_def = rxq_def;
5061 pp->indir[0] = rxq_def;
5063 /* Get special SoC configurations */
5064 if (of_device_is_compatible(dn, "marvell,armada-3700-neta"))
5065 pp->neta_armada3700 = true;
5067 pp->clk = devm_clk_get(&pdev->dev, "core");
5068 if (IS_ERR(pp->clk))
5069 pp->clk = devm_clk_get(&pdev->dev, NULL);
5070 if (IS_ERR(pp->clk)) {
5071 err = PTR_ERR(pp->clk);
5072 goto err_free_phylink;
5075 clk_prepare_enable(pp->clk);
5077 pp->clk_bus = devm_clk_get(&pdev->dev, "bus");
5078 if (!IS_ERR(pp->clk_bus))
5079 clk_prepare_enable(pp->clk_bus);
5081 pp->base = devm_platform_ioremap_resource(pdev, 0);
5082 if (IS_ERR(pp->base)) {
5083 err = PTR_ERR(pp->base);
5087 /* Alloc per-cpu port structure */
5088 pp->ports = alloc_percpu(struct mvneta_pcpu_port);
5094 /* Alloc per-cpu stats */
5095 pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats);
5098 goto err_free_ports;
5101 dt_mac_addr = of_get_mac_address(dn);
5102 if (!IS_ERR(dt_mac_addr)) {
5103 mac_from = "device tree";
5104 ether_addr_copy(dev->dev_addr, dt_mac_addr);
5106 mvneta_get_mac_addr(pp, hw_mac_addr);
5107 if (is_valid_ether_addr(hw_mac_addr)) {
5108 mac_from = "hardware";
5109 memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN);
5111 mac_from = "random";
5112 eth_hw_addr_random(dev);
5116 if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) {
5117 if (tx_csum_limit < 0 ||
5118 tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) {
5119 tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE;
5120 dev_info(&pdev->dev,
5121 "Wrong TX csum limit in DT, set to %dB\n",
5122 MVNETA_TX_CSUM_DEF_SIZE);
5124 } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) {
5125 tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE;
5127 tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE;
5130 pp->tx_csum_limit = tx_csum_limit;
5132 pp->dram_target_info = mv_mbus_dram_info();
5133 /* Armada3700 requires setting default configuration of Mbus
5134 * windows, however without using filled mbus_dram_target_info
5137 if (pp->dram_target_info || pp->neta_armada3700)
5138 mvneta_conf_mbus_windows(pp, pp->dram_target_info);
5140 pp->tx_ring_size = MVNETA_MAX_TXD;
5141 pp->rx_ring_size = MVNETA_MAX_RXD;
5144 SET_NETDEV_DEV(dev, &pdev->dev);
5146 pp->id = global_port_id++;
5148 /* Obtain access to BM resources if enabled and already initialized */
5149 bm_node = of_parse_phandle(dn, "buffer-manager", 0);
5151 pp->bm_priv = mvneta_bm_get(bm_node);
5153 err = mvneta_bm_port_init(pdev, pp);
5155 dev_info(&pdev->dev,
5156 "use SW buffer management\n");
5157 mvneta_bm_put(pp->bm_priv);
5161 /* Set RX packet offset correction for platforms, whose
5162 * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit
5163 * platforms and 0B for 32-bit ones.
5165 pp->rx_offset_correction = max(0,
5167 MVNETA_RX_PKT_OFFSET_CORRECTION);
5169 of_node_put(bm_node);
5171 /* sw buffer management */
5173 pp->rx_offset_correction = MVNETA_SKB_HEADROOM;
5175 err = mvneta_init(&pdev->dev, pp);
5179 err = mvneta_port_power_up(pp, phy_mode);
5181 dev_err(&pdev->dev, "can't power up port\n");
5185 /* Armada3700 network controller does not support per-cpu
5186 * operation, so only single NAPI should be initialized.
5188 if (pp->neta_armada3700) {
5189 netif_napi_add(dev, &pp->napi, mvneta_poll, NAPI_POLL_WEIGHT);
5191 for_each_present_cpu(cpu) {
5192 struct mvneta_pcpu_port *port =
5193 per_cpu_ptr(pp->ports, cpu);
5195 netif_napi_add(dev, &port->napi, mvneta_poll,
5201 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
5202 NETIF_F_TSO | NETIF_F_RXCSUM;
5203 dev->hw_features |= dev->features;
5204 dev->vlan_features |= dev->features;
5205 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5206 dev->gso_max_segs = MVNETA_MAX_TSO_SEGS;
5208 /* MTU range: 68 - 9676 */
5209 dev->min_mtu = ETH_MIN_MTU;
5210 /* 9676 == 9700 - 20 and rounding to 8 */
5211 dev->max_mtu = 9676;
5213 err = register_netdev(dev);
5215 dev_err(&pdev->dev, "failed to register\n");
5219 netdev_info(dev, "Using %s mac address %pM\n", mac_from,
5222 platform_set_drvdata(pdev, pp->dev);
5228 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
5229 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short,
5231 mvneta_bm_put(pp->bm_priv);
5233 free_percpu(pp->stats);
5235 free_percpu(pp->ports);
5237 clk_disable_unprepare(pp->clk_bus);
5238 clk_disable_unprepare(pp->clk);
5241 phylink_destroy(pp->phylink);
5243 irq_dispose_mapping(dev->irq);
5247 /* Device removal routine */
5248 static int mvneta_remove(struct platform_device *pdev)
5250 struct net_device *dev = platform_get_drvdata(pdev);
5251 struct mvneta_port *pp = netdev_priv(dev);
5253 unregister_netdev(dev);
5254 clk_disable_unprepare(pp->clk_bus);
5255 clk_disable_unprepare(pp->clk);
5256 free_percpu(pp->ports);
5257 free_percpu(pp->stats);
5258 irq_dispose_mapping(dev->irq);
5259 phylink_destroy(pp->phylink);
5262 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
5263 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short,
5265 mvneta_bm_put(pp->bm_priv);
5271 #ifdef CONFIG_PM_SLEEP
5272 static int mvneta_suspend(struct device *device)
5275 struct net_device *dev = dev_get_drvdata(device);
5276 struct mvneta_port *pp = netdev_priv(dev);
5278 if (!netif_running(dev))
5281 if (!pp->neta_armada3700) {
5282 spin_lock(&pp->lock);
5283 pp->is_stopped = true;
5284 spin_unlock(&pp->lock);
5286 cpuhp_state_remove_instance_nocalls(online_hpstate,
5288 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
5293 mvneta_stop_dev(pp);
5296 for (queue = 0; queue < rxq_number; queue++) {
5297 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
5299 mvneta_rxq_drop_pkts(pp, rxq);
5302 for (queue = 0; queue < txq_number; queue++) {
5303 struct mvneta_tx_queue *txq = &pp->txqs[queue];
5305 mvneta_txq_hw_deinit(pp, txq);
5309 netif_device_detach(dev);
5310 clk_disable_unprepare(pp->clk_bus);
5311 clk_disable_unprepare(pp->clk);
5316 static int mvneta_resume(struct device *device)
5318 struct platform_device *pdev = to_platform_device(device);
5319 struct net_device *dev = dev_get_drvdata(device);
5320 struct mvneta_port *pp = netdev_priv(dev);
5323 clk_prepare_enable(pp->clk);
5324 if (!IS_ERR(pp->clk_bus))
5325 clk_prepare_enable(pp->clk_bus);
5326 if (pp->dram_target_info || pp->neta_armada3700)
5327 mvneta_conf_mbus_windows(pp, pp->dram_target_info);
5329 err = mvneta_bm_port_init(pdev, pp);
5331 dev_info(&pdev->dev, "use SW buffer management\n");
5332 pp->rx_offset_correction = MVNETA_SKB_HEADROOM;
5336 mvneta_defaults_set(pp);
5337 err = mvneta_port_power_up(pp, pp->phy_interface);
5339 dev_err(device, "can't power up port\n");
5343 netif_device_attach(dev);
5345 if (!netif_running(dev))
5348 for (queue = 0; queue < rxq_number; queue++) {
5349 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
5351 rxq->next_desc_to_proc = 0;
5352 mvneta_rxq_hw_init(pp, rxq);
5355 for (queue = 0; queue < txq_number; queue++) {
5356 struct mvneta_tx_queue *txq = &pp->txqs[queue];
5358 txq->next_desc_to_proc = 0;
5359 mvneta_txq_hw_init(pp, txq);
5362 if (!pp->neta_armada3700) {
5363 spin_lock(&pp->lock);
5364 pp->is_stopped = false;
5365 spin_unlock(&pp->lock);
5366 cpuhp_state_add_instance_nocalls(online_hpstate,
5368 cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
5373 mvneta_start_dev(pp);
5375 mvneta_set_rx_mode(dev);
5381 static SIMPLE_DEV_PM_OPS(mvneta_pm_ops, mvneta_suspend, mvneta_resume);
5383 static const struct of_device_id mvneta_match[] = {
5384 { .compatible = "marvell,armada-370-neta" },
5385 { .compatible = "marvell,armada-xp-neta" },
5386 { .compatible = "marvell,armada-3700-neta" },
5389 MODULE_DEVICE_TABLE(of, mvneta_match);
5391 static struct platform_driver mvneta_driver = {
5392 .probe = mvneta_probe,
5393 .remove = mvneta_remove,
5395 .name = MVNETA_DRIVER_NAME,
5396 .of_match_table = mvneta_match,
5397 .pm = &mvneta_pm_ops,
5401 static int __init mvneta_driver_init(void)
5405 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/mvneta:online",
5407 mvneta_cpu_down_prepare);
5410 online_hpstate = ret;
5411 ret = cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD, "net/mvneta:dead",
5412 NULL, mvneta_cpu_dead);
5416 ret = platform_driver_register(&mvneta_driver);
5422 cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD);
5424 cpuhp_remove_multi_state(online_hpstate);
5428 module_init(mvneta_driver_init);
5430 static void __exit mvneta_driver_exit(void)
5432 platform_driver_unregister(&mvneta_driver);
5433 cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD);
5434 cpuhp_remove_multi_state(online_hpstate);
5436 module_exit(mvneta_driver_exit);
5438 MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com");
5439 MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
5440 MODULE_LICENSE("GPL");
5442 module_param(rxq_number, int, 0444);
5443 module_param(txq_number, int, 0444);
5445 module_param(rxq_def, int, 0444);
5446 module_param(rx_copybreak, int, 0644);