2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
4 * Copyright (C) 2012 Marvell
6 * Rami Rosen <rosenr@marvell.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/clk.h>
15 #include <linux/cpu.h>
16 #include <linux/etherdevice.h>
17 #include <linux/if_vlan.h>
18 #include <linux/inetdevice.h>
19 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/mbus.h>
23 #include <linux/module.h>
24 #include <linux/netdevice.h>
26 #include <linux/of_address.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_mdio.h>
29 #include <linux/of_net.h>
30 #include <linux/phy/phy.h>
31 #include <linux/phy.h>
32 #include <linux/phylink.h>
33 #include <linux/platform_device.h>
34 #include <linux/skbuff.h>
36 #include "mvneta_bm.h"
40 #include <net/page_pool.h>
41 #include <linux/bpf_trace.h>
44 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
45 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0)
46 #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4
47 #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30
48 #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6
49 #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0
50 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
51 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
52 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
53 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
54 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
55 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
56 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
57 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
58 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
59 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
60 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
61 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
62 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
63 #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2))
64 #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3
65 #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8
66 #define MVNETA_PORT_RX_RESET 0x1cc0
67 #define MVNETA_PORT_RX_DMA_RESET BIT(0)
68 #define MVNETA_PHY_ADDR 0x2000
69 #define MVNETA_PHY_ADDR_MASK 0x1f
70 #define MVNETA_MBUS_RETRY 0x2010
71 #define MVNETA_UNIT_INTR_CAUSE 0x2080
72 #define MVNETA_UNIT_CONTROL 0x20B0
73 #define MVNETA_PHY_POLLING_ENABLE BIT(1)
74 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
75 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
76 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
77 #define MVNETA_BASE_ADDR_ENABLE 0x2290
78 #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294
79 #define MVNETA_PORT_CONFIG 0x2400
80 #define MVNETA_UNI_PROMISC_MODE BIT(0)
81 #define MVNETA_DEF_RXQ(q) ((q) << 1)
82 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
83 #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
84 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
85 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
86 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
87 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
88 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
89 MVNETA_DEF_RXQ_ARP(q) | \
90 MVNETA_DEF_RXQ_TCP(q) | \
91 MVNETA_DEF_RXQ_UDP(q) | \
92 MVNETA_DEF_RXQ_BPDU(q) | \
93 MVNETA_TX_UNSET_ERR_SUM | \
94 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
95 #define MVNETA_PORT_CONFIG_EXTEND 0x2404
96 #define MVNETA_MAC_ADDR_LOW 0x2414
97 #define MVNETA_MAC_ADDR_HIGH 0x2418
98 #define MVNETA_SDMA_CONFIG 0x241c
99 #define MVNETA_SDMA_BRST_SIZE_16 4
100 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
101 #define MVNETA_RX_NO_DATA_SWAP BIT(4)
102 #define MVNETA_TX_NO_DATA_SWAP BIT(5)
103 #define MVNETA_DESC_SWAP BIT(6)
104 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
105 #define MVNETA_PORT_STATUS 0x2444
106 #define MVNETA_TX_IN_PRGRS BIT(1)
107 #define MVNETA_TX_FIFO_EMPTY BIT(8)
108 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
109 #define MVNETA_SERDES_CFG 0x24A0
110 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
111 #define MVNETA_QSGMII_SERDES_PROTO 0x0667
112 #define MVNETA_TYPE_PRIO 0x24bc
113 #define MVNETA_FORCE_UNI BIT(21)
114 #define MVNETA_TXQ_CMD_1 0x24e4
115 #define MVNETA_TXQ_CMD 0x2448
116 #define MVNETA_TXQ_DISABLE_SHIFT 8
117 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
118 #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484
119 #define MVNETA_OVERRUN_FRAME_COUNT 0x2488
120 #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4
121 #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31)
122 #define MVNETA_ACC_MODE 0x2500
123 #define MVNETA_BM_ADDRESS 0x2504
124 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
125 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
126 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
127 #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq)
128 #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8)
129 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
131 /* Exception Interrupt Port/Queue Cause register
133 * Their behavior depend of the mapping done using the PCPX2Q
134 * registers. For a given CPU if the bit associated to a queue is not
135 * set, then for the register a read from this CPU will always return
136 * 0 and a write won't do anything
139 #define MVNETA_INTR_NEW_CAUSE 0x25a0
140 #define MVNETA_INTR_NEW_MASK 0x25a4
142 /* bits 0..7 = TXQ SENT, one bit per queue.
143 * bits 8..15 = RXQ OCCUP, one bit per queue.
144 * bits 16..23 = RXQ FREE, one bit per queue.
145 * bit 29 = OLD_REG_SUM, see old reg ?
146 * bit 30 = TX_ERR_SUM, one bit for 4 ports
147 * bit 31 = MISC_SUM, one bit for 4 ports
149 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
150 #define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
151 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
152 #define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
153 #define MVNETA_MISCINTR_INTR_MASK BIT(31)
155 #define MVNETA_INTR_OLD_CAUSE 0x25a8
156 #define MVNETA_INTR_OLD_MASK 0x25ac
158 /* Data Path Port/Queue Cause Register */
159 #define MVNETA_INTR_MISC_CAUSE 0x25b0
160 #define MVNETA_INTR_MISC_MASK 0x25b4
162 #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0)
163 #define MVNETA_CAUSE_LINK_CHANGE BIT(1)
164 #define MVNETA_CAUSE_PTP BIT(4)
166 #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7)
167 #define MVNETA_CAUSE_RX_OVERRUN BIT(8)
168 #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9)
169 #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10)
170 #define MVNETA_CAUSE_TX_UNDERUN BIT(11)
171 #define MVNETA_CAUSE_PRBS_ERR BIT(12)
172 #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13)
173 #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14)
175 #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16
176 #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT)
177 #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool)))
179 #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24
180 #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT)
181 #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q)))
183 #define MVNETA_INTR_ENABLE 0x25b8
184 #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00
185 #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff
187 #define MVNETA_RXQ_CMD 0x2680
188 #define MVNETA_RXQ_DISABLE_SHIFT 8
189 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
190 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
191 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
192 #define MVNETA_GMAC_CTRL_0 0x2c00
193 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
194 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
195 #define MVNETA_GMAC0_PORT_1000BASE_X BIT(1)
196 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
197 #define MVNETA_GMAC_CTRL_2 0x2c08
198 #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0)
199 #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
200 #define MVNETA_GMAC2_PORT_RGMII BIT(4)
201 #define MVNETA_GMAC2_PORT_RESET BIT(6)
202 #define MVNETA_GMAC_STATUS 0x2c10
203 #define MVNETA_GMAC_LINK_UP BIT(0)
204 #define MVNETA_GMAC_SPEED_1000 BIT(1)
205 #define MVNETA_GMAC_SPEED_100 BIT(2)
206 #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
207 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
208 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
209 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
210 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
211 #define MVNETA_GMAC_AN_COMPLETE BIT(11)
212 #define MVNETA_GMAC_SYNC_OK BIT(14)
213 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
214 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
215 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
216 #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2)
217 #define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3)
218 #define MVNETA_GMAC_INBAND_RESTART_AN BIT(4)
219 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
220 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
221 #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
222 #define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8)
223 #define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9)
224 #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11)
225 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
226 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
227 #define MVNETA_GMAC_CTRL_4 0x2c90
228 #define MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE BIT(1)
229 #define MVNETA_MIB_COUNTERS_BASE 0x3000
230 #define MVNETA_MIB_LATE_COLLISION 0x7c
231 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
232 #define MVNETA_DA_FILT_OTH_MCAST 0x3500
233 #define MVNETA_DA_FILT_UCAST_BASE 0x3600
234 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
235 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
236 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
237 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
238 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
239 #define MVNETA_TXQ_DEC_SENT_SHIFT 16
240 #define MVNETA_TXQ_DEC_SENT_MASK 0xff
241 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
242 #define MVNETA_TXQ_SENT_DESC_SHIFT 16
243 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
244 #define MVNETA_PORT_TX_RESET 0x3cf0
245 #define MVNETA_PORT_TX_DMA_RESET BIT(0)
246 #define MVNETA_TX_MTU 0x3e0c
247 #define MVNETA_TX_TOKEN_SIZE 0x3e14
248 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
249 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
250 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
252 #define MVNETA_LPI_CTRL_0 0x2cc0
253 #define MVNETA_LPI_CTRL_1 0x2cc4
254 #define MVNETA_LPI_REQUEST_ENABLE BIT(0)
255 #define MVNETA_LPI_CTRL_2 0x2cc8
256 #define MVNETA_LPI_STATUS 0x2ccc
258 #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
260 /* Descriptor ring Macros */
261 #define MVNETA_QUEUE_NEXT_DESC(q, index) \
262 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
264 /* Various constants */
267 #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */
268 #define MVNETA_RX_COAL_PKTS 32
269 #define MVNETA_RX_COAL_USEC 100
271 /* The two bytes Marvell header. Either contains a special value used
272 * by Marvell switches when a specific hardware mode is enabled (not
273 * supported by this driver) or is filled automatically by zeroes on
274 * the RX side. Those two bytes being at the front of the Ethernet
275 * header, they allow to have the IP header aligned on a 4 bytes
276 * boundary automatically: the hardware skips those two bytes on its
279 #define MVNETA_MH_SIZE 2
281 #define MVNETA_VLAN_TAG_LEN 4
283 #define MVNETA_TX_CSUM_DEF_SIZE 1600
284 #define MVNETA_TX_CSUM_MAX_SIZE 9800
285 #define MVNETA_ACC_MODE_EXT1 1
286 #define MVNETA_ACC_MODE_EXT2 2
288 #define MVNETA_MAX_DECODE_WIN 6
290 /* Timeout constants */
291 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
292 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
293 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
295 #define MVNETA_TX_MTU_MAX 0x3ffff
297 /* The RSS lookup table actually has 256 entries but we do not use
300 #define MVNETA_RSS_LU_TABLE_SIZE 1
302 /* Max number of Rx descriptors */
303 #define MVNETA_MAX_RXD 512
305 /* Max number of Tx descriptors */
306 #define MVNETA_MAX_TXD 1024
308 /* Max number of allowed TCP segments for software TSO */
309 #define MVNETA_MAX_TSO_SEGS 100
311 #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
313 /* descriptor aligned size */
314 #define MVNETA_DESC_ALIGNED_SIZE 32
316 /* Number of bytes to be taken into account by HW when putting incoming data
317 * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet
318 * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers.
320 #define MVNETA_RX_PKT_OFFSET_CORRECTION 64
322 #define MVNETA_RX_PKT_SIZE(mtu) \
323 ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
324 ETH_HLEN + ETH_FCS_LEN, \
327 /* Driver assumes that the last 3 bits are 0 */
328 #define MVNETA_SKB_HEADROOM ALIGN(max(NET_SKB_PAD, XDP_PACKET_HEADROOM), 8)
329 #define MVNETA_SKB_PAD (SKB_DATA_ALIGN(sizeof(struct skb_shared_info) + \
330 MVNETA_SKB_HEADROOM))
331 #define MVNETA_SKB_SIZE(len) (SKB_DATA_ALIGN(len) + MVNETA_SKB_PAD)
332 #define MVNETA_MAX_RX_BUF_SIZE (PAGE_SIZE - MVNETA_SKB_PAD)
334 #define IS_TSO_HEADER(txq, addr) \
335 ((addr >= txq->tso_hdrs_phys) && \
336 (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE))
338 #define MVNETA_RX_GET_BM_POOL_ID(rxd) \
339 (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT)
342 ETHTOOL_STAT_EEE_WAKEUP,
343 ETHTOOL_STAT_SKB_ALLOC_ERR,
344 ETHTOOL_STAT_REFILL_ERR,
345 ETHTOOL_XDP_REDIRECT,
351 ETHTOOL_XDP_XMIT_ERR,
355 struct mvneta_statistic {
356 unsigned short offset;
358 const char name[ETH_GSTRING_LEN];
365 #define MVNETA_XDP_PASS 0
366 #define MVNETA_XDP_DROPPED BIT(0)
367 #define MVNETA_XDP_TX BIT(1)
368 #define MVNETA_XDP_REDIR BIT(2)
370 static const struct mvneta_statistic mvneta_statistics[] = {
371 { 0x3000, T_REG_64, "good_octets_received", },
372 { 0x3010, T_REG_32, "good_frames_received", },
373 { 0x3008, T_REG_32, "bad_octets_received", },
374 { 0x3014, T_REG_32, "bad_frames_received", },
375 { 0x3018, T_REG_32, "broadcast_frames_received", },
376 { 0x301c, T_REG_32, "multicast_frames_received", },
377 { 0x3050, T_REG_32, "unrec_mac_control_received", },
378 { 0x3058, T_REG_32, "good_fc_received", },
379 { 0x305c, T_REG_32, "bad_fc_received", },
380 { 0x3060, T_REG_32, "undersize_received", },
381 { 0x3064, T_REG_32, "fragments_received", },
382 { 0x3068, T_REG_32, "oversize_received", },
383 { 0x306c, T_REG_32, "jabber_received", },
384 { 0x3070, T_REG_32, "mac_receive_error", },
385 { 0x3074, T_REG_32, "bad_crc_event", },
386 { 0x3078, T_REG_32, "collision", },
387 { 0x307c, T_REG_32, "late_collision", },
388 { 0x2484, T_REG_32, "rx_discard", },
389 { 0x2488, T_REG_32, "rx_overrun", },
390 { 0x3020, T_REG_32, "frames_64_octets", },
391 { 0x3024, T_REG_32, "frames_65_to_127_octets", },
392 { 0x3028, T_REG_32, "frames_128_to_255_octets", },
393 { 0x302c, T_REG_32, "frames_256_to_511_octets", },
394 { 0x3030, T_REG_32, "frames_512_to_1023_octets", },
395 { 0x3034, T_REG_32, "frames_1024_to_max_octets", },
396 { 0x3038, T_REG_64, "good_octets_sent", },
397 { 0x3040, T_REG_32, "good_frames_sent", },
398 { 0x3044, T_REG_32, "excessive_collision", },
399 { 0x3048, T_REG_32, "multicast_frames_sent", },
400 { 0x304c, T_REG_32, "broadcast_frames_sent", },
401 { 0x3054, T_REG_32, "fc_sent", },
402 { 0x300c, T_REG_32, "internal_mac_transmit_err", },
403 { ETHTOOL_STAT_EEE_WAKEUP, T_SW, "eee_wakeup_errors", },
404 { ETHTOOL_STAT_SKB_ALLOC_ERR, T_SW, "skb_alloc_errors", },
405 { ETHTOOL_STAT_REFILL_ERR, T_SW, "refill_errors", },
406 { ETHTOOL_XDP_REDIRECT, T_SW, "rx_xdp_redirect", },
407 { ETHTOOL_XDP_PASS, T_SW, "rx_xdp_pass", },
408 { ETHTOOL_XDP_DROP, T_SW, "rx_xdp_drop", },
409 { ETHTOOL_XDP_TX, T_SW, "rx_xdp_tx", },
410 { ETHTOOL_XDP_TX_ERR, T_SW, "rx_xdp_tx_errors", },
411 { ETHTOOL_XDP_XMIT, T_SW, "tx_xdp_xmit", },
412 { ETHTOOL_XDP_XMIT_ERR, T_SW, "tx_xdp_xmit_errors", },
415 struct mvneta_stats {
430 struct mvneta_ethtool_stats {
431 struct mvneta_stats ps;
436 struct mvneta_pcpu_stats {
437 struct u64_stats_sync syncp;
439 struct mvneta_ethtool_stats es;
444 struct mvneta_pcpu_port {
445 /* Pointer to the shared port */
446 struct mvneta_port *pp;
448 /* Pointer to the CPU-local NAPI struct */
449 struct napi_struct napi;
451 /* Cause of the previous interrupt */
457 struct mvneta_pcpu_port __percpu *ports;
458 struct mvneta_pcpu_stats __percpu *stats;
462 struct mvneta_rx_queue *rxqs;
463 struct mvneta_tx_queue *txqs;
464 struct net_device *dev;
465 struct hlist_node node_online;
466 struct hlist_node node_dead;
468 /* Protect the access to the percpu interrupt registers,
469 * ensuring that the configuration remains coherent.
475 struct napi_struct napi;
477 struct bpf_prog *xdp_prog;
487 phy_interface_t phy_interface;
488 struct device_node *dn;
489 unsigned int tx_csum_limit;
490 struct phylink *phylink;
491 struct phylink_config phylink_config;
494 struct mvneta_bm *bm_priv;
495 struct mvneta_bm_pool *pool_long;
496 struct mvneta_bm_pool *pool_short;
503 u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
505 u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
507 /* Flags for special SoC configurations */
508 bool neta_armada3700;
509 u16 rx_offset_correction;
510 const struct mbus_dram_target_info *dram_target_info;
513 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
514 * layout of the transmit and reception DMA descriptors, and their
515 * layout is therefore defined by the hardware design
518 #define MVNETA_TX_L3_OFF_SHIFT 0
519 #define MVNETA_TX_IP_HLEN_SHIFT 8
520 #define MVNETA_TX_L4_UDP BIT(16)
521 #define MVNETA_TX_L3_IP6 BIT(17)
522 #define MVNETA_TXD_IP_CSUM BIT(18)
523 #define MVNETA_TXD_Z_PAD BIT(19)
524 #define MVNETA_TXD_L_DESC BIT(20)
525 #define MVNETA_TXD_F_DESC BIT(21)
526 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
527 MVNETA_TXD_L_DESC | \
529 #define MVNETA_TX_L4_CSUM_FULL BIT(30)
530 #define MVNETA_TX_L4_CSUM_NOT BIT(31)
532 #define MVNETA_RXD_ERR_CRC 0x0
533 #define MVNETA_RXD_BM_POOL_SHIFT 13
534 #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14))
535 #define MVNETA_RXD_ERR_SUMMARY BIT(16)
536 #define MVNETA_RXD_ERR_OVERRUN BIT(17)
537 #define MVNETA_RXD_ERR_LEN BIT(18)
538 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
539 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
540 #define MVNETA_RXD_L3_IP4 BIT(25)
541 #define MVNETA_RXD_LAST_DESC BIT(26)
542 #define MVNETA_RXD_FIRST_DESC BIT(27)
543 #define MVNETA_RXD_FIRST_LAST_DESC (MVNETA_RXD_FIRST_DESC | \
544 MVNETA_RXD_LAST_DESC)
545 #define MVNETA_RXD_L4_CSUM_OK BIT(30)
547 #if defined(__LITTLE_ENDIAN)
548 struct mvneta_tx_desc {
549 u32 command; /* Options used by HW for packet transmitting.*/
550 u16 reserved1; /* csum_l4 (for future use) */
551 u16 data_size; /* Data size of transmitted packet in bytes */
552 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
553 u32 reserved2; /* hw_cmd - (for future use, PMT) */
554 u32 reserved3[4]; /* Reserved - (for future use) */
557 struct mvneta_rx_desc {
558 u32 status; /* Info about received packet */
559 u16 reserved1; /* pnc_info - (for future use, PnC) */
560 u16 data_size; /* Size of received packet in bytes */
562 u32 buf_phys_addr; /* Physical address of the buffer */
563 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
565 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
566 u16 reserved3; /* prefetch_cmd, for future use */
567 u16 reserved4; /* csum_l4 - (for future use, PnC) */
569 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
570 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
573 struct mvneta_tx_desc {
574 u16 data_size; /* Data size of transmitted packet in bytes */
575 u16 reserved1; /* csum_l4 (for future use) */
576 u32 command; /* Options used by HW for packet transmitting.*/
577 u32 reserved2; /* hw_cmd - (for future use, PMT) */
578 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
579 u32 reserved3[4]; /* Reserved - (for future use) */
582 struct mvneta_rx_desc {
583 u16 data_size; /* Size of received packet in bytes */
584 u16 reserved1; /* pnc_info - (for future use, PnC) */
585 u32 status; /* Info about received packet */
587 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
588 u32 buf_phys_addr; /* Physical address of the buffer */
590 u16 reserved4; /* csum_l4 - (for future use, PnC) */
591 u16 reserved3; /* prefetch_cmd, for future use */
592 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
594 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
595 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
599 enum mvneta_tx_buf_type {
605 struct mvneta_tx_buf {
606 enum mvneta_tx_buf_type type;
608 struct xdp_frame *xdpf;
613 struct mvneta_tx_queue {
614 /* Number of this TX queue, in the range 0-7 */
617 /* Number of TX DMA descriptors in the descriptor ring */
620 /* Number of currently used TX DMA descriptor in the
625 int tx_stop_threshold;
626 int tx_wake_threshold;
628 /* Array of transmitted buffers */
629 struct mvneta_tx_buf *buf;
631 /* Index of last TX DMA descriptor that was inserted */
634 /* Index of the TX DMA descriptor to be cleaned up */
639 /* Virtual address of the TX DMA descriptors array */
640 struct mvneta_tx_desc *descs;
642 /* DMA address of the TX DMA descriptors array */
643 dma_addr_t descs_phys;
645 /* Index of the last TX DMA descriptor */
648 /* Index of the next TX DMA descriptor to process */
649 int next_desc_to_proc;
651 /* DMA buffers for TSO headers */
654 /* DMA address of TSO headers */
655 dma_addr_t tso_hdrs_phys;
657 /* Affinity mask for CPUs*/
658 cpumask_t affinity_mask;
661 struct mvneta_rx_queue {
662 /* rx queue number, in the range 0-7 */
665 /* num of rx descriptors in the rx descriptor ring */
672 struct page_pool *page_pool;
673 struct xdp_rxq_info xdp_rxq;
675 /* Virtual address of the RX buffer */
676 void **buf_virt_addr;
678 /* Virtual address of the RX DMA descriptors array */
679 struct mvneta_rx_desc *descs;
681 /* DMA address of the RX DMA descriptors array */
682 dma_addr_t descs_phys;
684 /* Index of the last RX DMA descriptor */
687 /* Index of the next RX DMA descriptor to process */
688 int next_desc_to_proc;
690 /* Index of first RX DMA descriptor to refill */
694 /* pointer to uncomplete skb buffer */
699 static enum cpuhp_state online_hpstate;
700 /* The hardware supports eight (8) rx queues, but we are only allowing
701 * the first one to be used. Therefore, let's just allocate one queue.
703 static int rxq_number = 8;
704 static int txq_number = 8;
708 static int rx_copybreak __read_mostly = 256;
710 /* HW BM need that each port be identify by a unique ID */
711 static int global_port_id;
713 #define MVNETA_DRIVER_NAME "mvneta"
714 #define MVNETA_DRIVER_VERSION "1.0"
716 /* Utility/helper methods */
718 /* Write helper method */
719 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
721 writel(data, pp->base + offset);
724 /* Read helper method */
725 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
727 return readl(pp->base + offset);
730 /* Increment txq get counter */
731 static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq)
733 txq->txq_get_index++;
734 if (txq->txq_get_index == txq->size)
735 txq->txq_get_index = 0;
738 /* Increment txq put counter */
739 static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq)
741 txq->txq_put_index++;
742 if (txq->txq_put_index == txq->size)
743 txq->txq_put_index = 0;
747 /* Clear all MIB counters */
748 static void mvneta_mib_counters_clear(struct mvneta_port *pp)
753 /* Perform dummy reads from MIB counters */
754 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
755 dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
756 dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT);
757 dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT);
760 /* Get System Network Statistics */
762 mvneta_get_stats64(struct net_device *dev,
763 struct rtnl_link_stats64 *stats)
765 struct mvneta_port *pp = netdev_priv(dev);
769 for_each_possible_cpu(cpu) {
770 struct mvneta_pcpu_stats *cpu_stats;
778 cpu_stats = per_cpu_ptr(pp->stats, cpu);
780 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
781 rx_packets = cpu_stats->es.ps.rx_packets;
782 rx_bytes = cpu_stats->es.ps.rx_bytes;
783 rx_dropped = cpu_stats->rx_dropped;
784 rx_errors = cpu_stats->rx_errors;
785 tx_packets = cpu_stats->es.ps.tx_packets;
786 tx_bytes = cpu_stats->es.ps.tx_bytes;
787 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
789 stats->rx_packets += rx_packets;
790 stats->rx_bytes += rx_bytes;
791 stats->rx_dropped += rx_dropped;
792 stats->rx_errors += rx_errors;
793 stats->tx_packets += tx_packets;
794 stats->tx_bytes += tx_bytes;
797 stats->tx_dropped = dev->stats.tx_dropped;
800 /* Rx descriptors helper methods */
802 /* Checks whether the RX descriptor having this status is both the first
803 * and the last descriptor for the RX packet. Each RX packet is currently
804 * received through a single RX descriptor, so not having each RX
805 * descriptor with its first and last bits set is an error
807 static int mvneta_rxq_desc_is_first_last(u32 status)
809 return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
810 MVNETA_RXD_FIRST_LAST_DESC;
813 /* Add number of descriptors ready to receive new packets */
814 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
815 struct mvneta_rx_queue *rxq,
818 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
821 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
822 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
823 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
824 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
825 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
828 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
829 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
832 /* Get number of RX descriptors occupied by received packets */
833 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
834 struct mvneta_rx_queue *rxq)
838 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
839 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
842 /* Update num of rx desc called upon return from rx path or
843 * from mvneta_rxq_drop_pkts().
845 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
846 struct mvneta_rx_queue *rxq,
847 int rx_done, int rx_filled)
851 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
853 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
854 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
858 /* Only 255 descriptors can be added at once */
859 while ((rx_done > 0) || (rx_filled > 0)) {
860 if (rx_done <= 0xff) {
867 if (rx_filled <= 0xff) {
868 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
871 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
874 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
878 /* Get pointer to next RX descriptor to be processed by SW */
879 static struct mvneta_rx_desc *
880 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
882 int rx_desc = rxq->next_desc_to_proc;
884 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
885 prefetch(rxq->descs + rxq->next_desc_to_proc);
886 return rxq->descs + rx_desc;
889 /* Change maximum receive size of the port. */
890 static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size)
894 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
895 val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK;
896 val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) <<
897 MVNETA_GMAC_MAX_RX_SIZE_SHIFT;
898 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
902 /* Set rx queue offset */
903 static void mvneta_rxq_offset_set(struct mvneta_port *pp,
904 struct mvneta_rx_queue *rxq,
909 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
910 val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK;
913 val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3);
914 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
918 /* Tx descriptors helper methods */
920 /* Update HW with number of TX descriptors to be sent */
921 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
922 struct mvneta_tx_queue *txq,
927 pend_desc += txq->pending;
929 /* Only 255 Tx descriptors can be added at once */
931 val = min(pend_desc, 255);
932 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
934 } while (pend_desc > 0);
938 /* Get pointer to next TX descriptor to be processed (send) by HW */
939 static struct mvneta_tx_desc *
940 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
942 int tx_desc = txq->next_desc_to_proc;
944 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
945 return txq->descs + tx_desc;
948 /* Release the last allocated TX descriptor. Useful to handle DMA
949 * mapping failures in the TX path.
951 static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq)
953 if (txq->next_desc_to_proc == 0)
954 txq->next_desc_to_proc = txq->last_desc - 1;
956 txq->next_desc_to_proc--;
959 /* Set rxq buf size */
960 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
961 struct mvneta_rx_queue *rxq,
966 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
968 val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
969 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
971 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
974 /* Disable buffer management (BM) */
975 static void mvneta_rxq_bm_disable(struct mvneta_port *pp,
976 struct mvneta_rx_queue *rxq)
980 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
981 val &= ~MVNETA_RXQ_HW_BUF_ALLOC;
982 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
985 /* Enable buffer management (BM) */
986 static void mvneta_rxq_bm_enable(struct mvneta_port *pp,
987 struct mvneta_rx_queue *rxq)
991 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
992 val |= MVNETA_RXQ_HW_BUF_ALLOC;
993 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
996 /* Notify HW about port's assignment of pool for bigger packets */
997 static void mvneta_rxq_long_pool_set(struct mvneta_port *pp,
998 struct mvneta_rx_queue *rxq)
1002 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
1003 val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK;
1004 val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT);
1006 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
1009 /* Notify HW about port's assignment of pool for smaller packets */
1010 static void mvneta_rxq_short_pool_set(struct mvneta_port *pp,
1011 struct mvneta_rx_queue *rxq)
1015 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
1016 val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK;
1017 val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT);
1019 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
1022 /* Set port's receive buffer size for assigned BM pool */
1023 static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp,
1029 if (!IS_ALIGNED(buf_size, 8)) {
1030 dev_warn(pp->dev->dev.parent,
1031 "illegal buf_size value %d, round to %d\n",
1032 buf_size, ALIGN(buf_size, 8));
1033 buf_size = ALIGN(buf_size, 8);
1036 val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id));
1037 val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK;
1038 mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val);
1041 /* Configure MBUS window in order to enable access BM internal SRAM */
1042 static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize,
1045 u32 win_enable, win_protect;
1048 win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE);
1050 if (pp->bm_win_id < 0) {
1051 /* Find first not occupied window */
1052 for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) {
1053 if (win_enable & (1 << i)) {
1058 if (i == MVNETA_MAX_DECODE_WIN)
1064 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
1065 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
1068 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
1070 mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) |
1071 (attr << 8) | target);
1073 mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000);
1075 win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE);
1076 win_protect |= 3 << (2 * i);
1077 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
1079 win_enable &= ~(1 << i);
1080 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
1085 static int mvneta_bm_port_mbus_init(struct mvneta_port *pp)
1091 /* Get BM window information */
1092 err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize,
1099 /* Open NETA -> BM window */
1100 err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize,
1103 netdev_info(pp->dev, "fail to configure mbus window to BM\n");
1109 /* Assign and initialize pools for port. In case of fail
1110 * buffer manager will remain disabled for current port.
1112 static int mvneta_bm_port_init(struct platform_device *pdev,
1113 struct mvneta_port *pp)
1115 struct device_node *dn = pdev->dev.of_node;
1116 u32 long_pool_id, short_pool_id;
1118 if (!pp->neta_armada3700) {
1121 ret = mvneta_bm_port_mbus_init(pp);
1126 if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) {
1127 netdev_info(pp->dev, "missing long pool id\n");
1131 /* Create port's long pool depending on mtu */
1132 pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id,
1133 MVNETA_BM_LONG, pp->id,
1134 MVNETA_RX_PKT_SIZE(pp->dev->mtu));
1135 if (!pp->pool_long) {
1136 netdev_info(pp->dev, "fail to obtain long pool for port\n");
1140 pp->pool_long->port_map |= 1 << pp->id;
1142 mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size,
1145 /* If short pool id is not defined, assume using single pool */
1146 if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id))
1147 short_pool_id = long_pool_id;
1149 /* Create port's short pool */
1150 pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id,
1151 MVNETA_BM_SHORT, pp->id,
1152 MVNETA_BM_SHORT_PKT_SIZE);
1153 if (!pp->pool_short) {
1154 netdev_info(pp->dev, "fail to obtain short pool for port\n");
1155 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
1159 if (short_pool_id != long_pool_id) {
1160 pp->pool_short->port_map |= 1 << pp->id;
1161 mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size,
1162 pp->pool_short->id);
1168 /* Update settings of a pool for bigger packets */
1169 static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu)
1171 struct mvneta_bm_pool *bm_pool = pp->pool_long;
1172 struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool;
1175 /* Release all buffers from long pool */
1176 mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id);
1177 if (hwbm_pool->buf_num) {
1178 WARN(1, "cannot free all buffers in pool %d\n",
1183 bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu);
1184 bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size);
1185 hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
1186 SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size));
1188 /* Fill entire long pool */
1189 num = hwbm_pool_add(hwbm_pool, hwbm_pool->size);
1190 if (num != hwbm_pool->size) {
1191 WARN(1, "pool %d: %d of %d allocated\n",
1192 bm_pool->id, num, hwbm_pool->size);
1195 mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id);
1200 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
1201 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id);
1204 pp->rx_offset_correction = MVNETA_SKB_HEADROOM;
1205 mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1);
1206 netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n");
1209 /* Start the Ethernet port RX and TX activity */
1210 static void mvneta_port_up(struct mvneta_port *pp)
1215 /* Enable all initialized TXs. */
1217 for (queue = 0; queue < txq_number; queue++) {
1218 struct mvneta_tx_queue *txq = &pp->txqs[queue];
1220 q_map |= (1 << queue);
1222 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
1225 /* Enable all initialized RXQs. */
1226 for (queue = 0; queue < rxq_number; queue++) {
1227 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
1230 q_map |= (1 << queue);
1232 mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
1235 /* Stop the Ethernet port activity */
1236 static void mvneta_port_down(struct mvneta_port *pp)
1241 /* Stop Rx port activity. Check port Rx activity. */
1242 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
1244 /* Issue stop command for active channels only */
1246 mvreg_write(pp, MVNETA_RXQ_CMD,
1247 val << MVNETA_RXQ_DISABLE_SHIFT);
1249 /* Wait for all Rx activity to terminate. */
1252 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
1253 netdev_warn(pp->dev,
1254 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n",
1260 val = mvreg_read(pp, MVNETA_RXQ_CMD);
1261 } while (val & MVNETA_RXQ_ENABLE_MASK);
1263 /* Stop Tx port activity. Check port Tx activity. Issue stop
1264 * command for active channels only
1266 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
1269 mvreg_write(pp, MVNETA_TXQ_CMD,
1270 (val << MVNETA_TXQ_DISABLE_SHIFT));
1272 /* Wait for all Tx activity to terminate. */
1275 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
1276 netdev_warn(pp->dev,
1277 "TIMEOUT for TX stopped status=0x%08x\n",
1283 /* Check TX Command reg that all Txqs are stopped */
1284 val = mvreg_read(pp, MVNETA_TXQ_CMD);
1286 } while (val & MVNETA_TXQ_ENABLE_MASK);
1288 /* Double check to verify that TX FIFO is empty */
1291 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
1292 netdev_warn(pp->dev,
1293 "TX FIFO empty timeout status=0x%08x\n",
1299 val = mvreg_read(pp, MVNETA_PORT_STATUS);
1300 } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
1301 (val & MVNETA_TX_IN_PRGRS));
1306 /* Enable the port by setting the port enable bit of the MAC control register */
1307 static void mvneta_port_enable(struct mvneta_port *pp)
1312 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
1313 val |= MVNETA_GMAC0_PORT_ENABLE;
1314 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
1317 /* Disable the port and wait for about 200 usec before retuning */
1318 static void mvneta_port_disable(struct mvneta_port *pp)
1322 /* Reset the Enable bit in the Serial Control Register */
1323 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
1324 val &= ~MVNETA_GMAC0_PORT_ENABLE;
1325 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
1330 /* Multicast tables methods */
1332 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
1333 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
1341 val = 0x1 | (queue << 1);
1342 val |= (val << 24) | (val << 16) | (val << 8);
1345 for (offset = 0; offset <= 0xc; offset += 4)
1346 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
1349 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
1350 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
1358 val = 0x1 | (queue << 1);
1359 val |= (val << 24) | (val << 16) | (val << 8);
1362 for (offset = 0; offset <= 0xfc; offset += 4)
1363 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
1367 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
1368 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
1374 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
1377 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
1378 val = 0x1 | (queue << 1);
1379 val |= (val << 24) | (val << 16) | (val << 8);
1382 for (offset = 0; offset <= 0xfc; offset += 4)
1383 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
1386 static void mvneta_percpu_unmask_interrupt(void *arg)
1388 struct mvneta_port *pp = arg;
1390 /* All the queue are unmasked, but actually only the ones
1391 * mapped to this CPU will be unmasked
1393 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
1394 MVNETA_RX_INTR_MASK_ALL |
1395 MVNETA_TX_INTR_MASK_ALL |
1396 MVNETA_MISCINTR_INTR_MASK);
1399 static void mvneta_percpu_mask_interrupt(void *arg)
1401 struct mvneta_port *pp = arg;
1403 /* All the queue are masked, but actually only the ones
1404 * mapped to this CPU will be masked
1406 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
1407 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
1408 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
1411 static void mvneta_percpu_clear_intr_cause(void *arg)
1413 struct mvneta_port *pp = arg;
1415 /* All the queue are cleared, but actually only the ones
1416 * mapped to this CPU will be cleared
1418 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
1419 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
1420 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
1423 /* This method sets defaults to the NETA port:
1424 * Clears interrupt Cause and Mask registers.
1425 * Clears all MAC tables.
1426 * Sets defaults to all registers.
1427 * Resets RX and TX descriptor rings.
1429 * This method can be called after mvneta_port_down() to return the port
1430 * settings to defaults.
1432 static void mvneta_defaults_set(struct mvneta_port *pp)
1437 int max_cpu = num_present_cpus();
1439 /* Clear all Cause registers */
1440 on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
1442 /* Mask all interrupts */
1443 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
1444 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
1446 /* Enable MBUS Retry bit16 */
1447 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
1449 /* Set CPU queue access map. CPUs are assigned to the RX and
1450 * TX queues modulo their number. If there is only one TX
1451 * queue then it is assigned to the CPU associated to the
1454 for_each_present_cpu(cpu) {
1455 int rxq_map = 0, txq_map = 0;
1457 if (!pp->neta_armada3700) {
1458 for (rxq = 0; rxq < rxq_number; rxq++)
1459 if ((rxq % max_cpu) == cpu)
1460 rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
1462 for (txq = 0; txq < txq_number; txq++)
1463 if ((txq % max_cpu) == cpu)
1464 txq_map |= MVNETA_CPU_TXQ_ACCESS(txq);
1466 /* With only one TX queue we configure a special case
1467 * which will allow to get all the irq on a single
1470 if (txq_number == 1)
1471 txq_map = (cpu == pp->rxq_def) ?
1472 MVNETA_CPU_TXQ_ACCESS(1) : 0;
1475 txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
1476 rxq_map = MVNETA_CPU_RXQ_ACCESS_ALL_MASK;
1479 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
1482 /* Reset RX and TX DMAs */
1483 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
1484 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
1486 /* Disable Legacy WRR, Disable EJP, Release from reset */
1487 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
1488 for (queue = 0; queue < txq_number; queue++) {
1489 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
1490 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
1493 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
1494 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
1496 /* Set Port Acceleration Mode */
1498 /* HW buffer management + legacy parser */
1499 val = MVNETA_ACC_MODE_EXT2;
1501 /* SW buffer management + legacy parser */
1502 val = MVNETA_ACC_MODE_EXT1;
1503 mvreg_write(pp, MVNETA_ACC_MODE, val);
1506 mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr);
1508 /* Update val of portCfg register accordingly with all RxQueue types */
1509 val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def);
1510 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
1513 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
1514 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
1516 /* Build PORT_SDMA_CONFIG_REG */
1519 /* Default burst size */
1520 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
1521 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
1522 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
1524 #if defined(__BIG_ENDIAN)
1525 val |= MVNETA_DESC_SWAP;
1528 /* Assign port SDMA configuration */
1529 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
1531 /* Disable PHY polling in hardware, since we're using the
1532 * kernel phylib to do this.
1534 val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
1535 val &= ~MVNETA_PHY_POLLING_ENABLE;
1536 mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
1538 mvneta_set_ucast_table(pp, -1);
1539 mvneta_set_special_mcast_table(pp, -1);
1540 mvneta_set_other_mcast_table(pp, -1);
1542 /* Set port interrupt enable register - default enable all */
1543 mvreg_write(pp, MVNETA_INTR_ENABLE,
1544 (MVNETA_RXQ_INTR_ENABLE_ALL_MASK
1545 | MVNETA_TXQ_INTR_ENABLE_ALL_MASK));
1547 mvneta_mib_counters_clear(pp);
1550 /* Set max sizes for tx queues */
1551 static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size)
1557 mtu = max_tx_size * 8;
1558 if (mtu > MVNETA_TX_MTU_MAX)
1559 mtu = MVNETA_TX_MTU_MAX;
1562 val = mvreg_read(pp, MVNETA_TX_MTU);
1563 val &= ~MVNETA_TX_MTU_MAX;
1565 mvreg_write(pp, MVNETA_TX_MTU, val);
1567 /* TX token size and all TXQs token size must be larger that MTU */
1568 val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE);
1570 size = val & MVNETA_TX_TOKEN_SIZE_MAX;
1573 val &= ~MVNETA_TX_TOKEN_SIZE_MAX;
1575 mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val);
1577 for (queue = 0; queue < txq_number; queue++) {
1578 val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue));
1580 size = val & MVNETA_TXQ_TOKEN_SIZE_MAX;
1583 val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX;
1585 mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val);
1590 /* Set unicast address */
1591 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
1594 unsigned int unicast_reg;
1595 unsigned int tbl_offset;
1596 unsigned int reg_offset;
1598 /* Locate the Unicast table entry */
1599 last_nibble = (0xf & last_nibble);
1601 /* offset from unicast tbl base */
1602 tbl_offset = (last_nibble / 4) * 4;
1604 /* offset within the above reg */
1605 reg_offset = last_nibble % 4;
1607 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
1610 /* Clear accepts frame bit at specified unicast DA tbl entry */
1611 unicast_reg &= ~(0xff << (8 * reg_offset));
1613 unicast_reg &= ~(0xff << (8 * reg_offset));
1614 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1617 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
1620 /* Set mac address */
1621 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
1628 mac_l = (addr[4] << 8) | (addr[5]);
1629 mac_h = (addr[0] << 24) | (addr[1] << 16) |
1630 (addr[2] << 8) | (addr[3] << 0);
1632 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
1633 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
1636 /* Accept frames of this address */
1637 mvneta_set_ucast_addr(pp, addr[5], queue);
1640 /* Set the number of packets that will be received before RX interrupt
1641 * will be generated by HW.
1643 static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp,
1644 struct mvneta_rx_queue *rxq, u32 value)
1646 mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id),
1647 value | MVNETA_RXQ_NON_OCCUPIED(0));
1650 /* Set the time delay in usec before RX interrupt will be generated by
1653 static void mvneta_rx_time_coal_set(struct mvneta_port *pp,
1654 struct mvneta_rx_queue *rxq, u32 value)
1657 unsigned long clk_rate;
1659 clk_rate = clk_get_rate(pp->clk);
1660 val = (clk_rate / 1000000) * value;
1662 mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);
1665 /* Set threshold for TX_DONE pkts coalescing */
1666 static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp,
1667 struct mvneta_tx_queue *txq, u32 value)
1671 val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id));
1673 val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK;
1674 val |= MVNETA_TXQ_SENT_THRESH_MASK(value);
1676 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val);
1679 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
1680 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
1681 u32 phys_addr, void *virt_addr,
1682 struct mvneta_rx_queue *rxq)
1686 rx_desc->buf_phys_addr = phys_addr;
1687 i = rx_desc - rxq->descs;
1688 rxq->buf_virt_addr[i] = virt_addr;
1691 /* Decrement sent descriptors counter */
1692 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
1693 struct mvneta_tx_queue *txq,
1698 /* Only 255 TX descriptors can be updated at once */
1699 while (sent_desc > 0xff) {
1700 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
1701 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1702 sent_desc = sent_desc - 0xff;
1705 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
1706 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1709 /* Get number of TX descriptors already sent by HW */
1710 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
1711 struct mvneta_tx_queue *txq)
1716 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
1717 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
1718 MVNETA_TXQ_SENT_DESC_SHIFT;
1723 /* Get number of sent descriptors and decrement counter.
1724 * The number of sent descriptors is returned.
1726 static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp,
1727 struct mvneta_tx_queue *txq)
1731 /* Get number of sent descriptors */
1732 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1734 /* Decrement sent descriptors counter */
1736 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
1741 /* Set TXQ descriptors fields relevant for CSUM calculation */
1742 static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto,
1743 int ip_hdr_len, int l4_proto)
1747 /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1748 * G_L4_chk, L4_type; required only for checksum
1751 command = l3_offs << MVNETA_TX_L3_OFF_SHIFT;
1752 command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT;
1754 if (l3_proto == htons(ETH_P_IP))
1755 command |= MVNETA_TXD_IP_CSUM;
1757 command |= MVNETA_TX_L3_IP6;
1759 if (l4_proto == IPPROTO_TCP)
1760 command |= MVNETA_TX_L4_CSUM_FULL;
1761 else if (l4_proto == IPPROTO_UDP)
1762 command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL;
1764 command |= MVNETA_TX_L4_CSUM_NOT;
1770 /* Display more error info */
1771 static void mvneta_rx_error(struct mvneta_port *pp,
1772 struct mvneta_rx_desc *rx_desc)
1774 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
1775 u32 status = rx_desc->status;
1777 /* update per-cpu counter */
1778 u64_stats_update_begin(&stats->syncp);
1780 u64_stats_update_end(&stats->syncp);
1782 switch (status & MVNETA_RXD_ERR_CODE_MASK) {
1783 case MVNETA_RXD_ERR_CRC:
1784 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
1785 status, rx_desc->data_size);
1787 case MVNETA_RXD_ERR_OVERRUN:
1788 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
1789 status, rx_desc->data_size);
1791 case MVNETA_RXD_ERR_LEN:
1792 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
1793 status, rx_desc->data_size);
1795 case MVNETA_RXD_ERR_RESOURCE:
1796 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
1797 status, rx_desc->data_size);
1802 /* Handle RX checksum offload based on the descriptor's status */
1803 static void mvneta_rx_csum(struct mvneta_port *pp, u32 status,
1804 struct sk_buff *skb)
1806 if ((pp->dev->features & NETIF_F_RXCSUM) &&
1807 (status & MVNETA_RXD_L3_IP4) &&
1808 (status & MVNETA_RXD_L4_CSUM_OK)) {
1810 skb->ip_summed = CHECKSUM_UNNECESSARY;
1814 skb->ip_summed = CHECKSUM_NONE;
1817 /* Return tx queue pointer (find last set bit) according to <cause> returned
1818 * form tx_done reg. <cause> must not be null. The return value is always a
1819 * valid queue for matching the first one found in <cause>.
1821 static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp,
1824 int queue = fls(cause) - 1;
1826 return &pp->txqs[queue];
1829 /* Free tx queue skbuffs */
1830 static void mvneta_txq_bufs_free(struct mvneta_port *pp,
1831 struct mvneta_tx_queue *txq, int num,
1832 struct netdev_queue *nq)
1834 unsigned int bytes_compl = 0, pkts_compl = 0;
1837 for (i = 0; i < num; i++) {
1838 struct mvneta_tx_buf *buf = &txq->buf[txq->txq_get_index];
1839 struct mvneta_tx_desc *tx_desc = txq->descs +
1842 mvneta_txq_inc_get(txq);
1844 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr) &&
1845 buf->type != MVNETA_TYPE_XDP_TX)
1846 dma_unmap_single(pp->dev->dev.parent,
1847 tx_desc->buf_phys_addr,
1848 tx_desc->data_size, DMA_TO_DEVICE);
1849 if (buf->type == MVNETA_TYPE_SKB && buf->skb) {
1850 bytes_compl += buf->skb->len;
1852 dev_kfree_skb_any(buf->skb);
1853 } else if (buf->type == MVNETA_TYPE_XDP_TX ||
1854 buf->type == MVNETA_TYPE_XDP_NDO) {
1855 xdp_return_frame(buf->xdpf);
1859 netdev_tx_completed_queue(nq, pkts_compl, bytes_compl);
1862 /* Handle end of transmission */
1863 static void mvneta_txq_done(struct mvneta_port *pp,
1864 struct mvneta_tx_queue *txq)
1866 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
1869 tx_done = mvneta_txq_sent_desc_proc(pp, txq);
1873 mvneta_txq_bufs_free(pp, txq, tx_done, nq);
1875 txq->count -= tx_done;
1877 if (netif_tx_queue_stopped(nq)) {
1878 if (txq->count <= txq->tx_wake_threshold)
1879 netif_tx_wake_queue(nq);
1883 /* Refill processing for SW buffer management */
1884 /* Allocate page per descriptor */
1885 static int mvneta_rx_refill(struct mvneta_port *pp,
1886 struct mvneta_rx_desc *rx_desc,
1887 struct mvneta_rx_queue *rxq,
1890 dma_addr_t phys_addr;
1893 page = page_pool_alloc_pages(rxq->page_pool,
1894 gfp_mask | __GFP_NOWARN);
1898 phys_addr = page_pool_get_dma_addr(page) + pp->rx_offset_correction;
1899 mvneta_rx_desc_fill(rx_desc, phys_addr, page, rxq);
1904 /* Handle tx checksum */
1905 static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb)
1907 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1909 __be16 l3_proto = vlan_get_protocol(skb);
1912 if (l3_proto == htons(ETH_P_IP)) {
1913 struct iphdr *ip4h = ip_hdr(skb);
1915 /* Calculate IPv4 checksum and L4 checksum */
1916 ip_hdr_len = ip4h->ihl;
1917 l4_proto = ip4h->protocol;
1918 } else if (l3_proto == htons(ETH_P_IPV6)) {
1919 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1921 /* Read l4_protocol from one of IPv6 extra headers */
1922 if (skb_network_header_len(skb) > 0)
1923 ip_hdr_len = (skb_network_header_len(skb) >> 2);
1924 l4_proto = ip6h->nexthdr;
1926 return MVNETA_TX_L4_CSUM_NOT;
1928 return mvneta_txq_desc_csum(skb_network_offset(skb),
1929 l3_proto, ip_hdr_len, l4_proto);
1932 return MVNETA_TX_L4_CSUM_NOT;
1935 /* Drop packets received by the RXQ and free buffers */
1936 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
1937 struct mvneta_rx_queue *rxq)
1941 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1943 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1946 for (i = 0; i < rx_done; i++) {
1947 struct mvneta_rx_desc *rx_desc =
1948 mvneta_rxq_next_desc_get(rxq);
1949 u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
1950 struct mvneta_bm_pool *bm_pool;
1952 bm_pool = &pp->bm_priv->bm_pools[pool_id];
1953 /* Return dropped buffer to the pool */
1954 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
1955 rx_desc->buf_phys_addr);
1960 for (i = 0; i < rxq->size; i++) {
1961 struct mvneta_rx_desc *rx_desc = rxq->descs + i;
1962 void *data = rxq->buf_virt_addr[i];
1963 if (!data || !(rx_desc->buf_phys_addr))
1966 page_pool_put_full_page(rxq->page_pool, data, false);
1968 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq))
1969 xdp_rxq_info_unreg(&rxq->xdp_rxq);
1970 page_pool_destroy(rxq->page_pool);
1971 rxq->page_pool = NULL;
1975 mvneta_update_stats(struct mvneta_port *pp,
1976 struct mvneta_stats *ps)
1978 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
1980 u64_stats_update_begin(&stats->syncp);
1981 stats->es.ps.rx_packets += ps->rx_packets;
1982 stats->es.ps.rx_bytes += ps->rx_bytes;
1984 stats->es.ps.xdp_redirect += ps->xdp_redirect;
1985 stats->es.ps.xdp_pass += ps->xdp_pass;
1986 stats->es.ps.xdp_drop += ps->xdp_drop;
1987 u64_stats_update_end(&stats->syncp);
1991 int mvneta_rx_refill_queue(struct mvneta_port *pp, struct mvneta_rx_queue *rxq)
1993 struct mvneta_rx_desc *rx_desc;
1994 int curr_desc = rxq->first_to_refill;
1997 for (i = 0; (i < rxq->refill_num) && (i < 64); i++) {
1998 rx_desc = rxq->descs + curr_desc;
1999 if (!(rx_desc->buf_phys_addr)) {
2000 if (mvneta_rx_refill(pp, rx_desc, rxq, GFP_ATOMIC)) {
2001 struct mvneta_pcpu_stats *stats;
2003 pr_err("Can't refill queue %d. Done %d from %d\n",
2004 rxq->id, i, rxq->refill_num);
2006 stats = this_cpu_ptr(pp->stats);
2007 u64_stats_update_begin(&stats->syncp);
2008 stats->es.refill_error++;
2009 u64_stats_update_end(&stats->syncp);
2013 curr_desc = MVNETA_QUEUE_NEXT_DESC(rxq, curr_desc);
2015 rxq->refill_num -= i;
2016 rxq->first_to_refill = curr_desc;
2022 mvneta_xdp_submit_frame(struct mvneta_port *pp, struct mvneta_tx_queue *txq,
2023 struct xdp_frame *xdpf, bool dma_map)
2025 struct mvneta_tx_desc *tx_desc;
2026 struct mvneta_tx_buf *buf;
2027 dma_addr_t dma_addr;
2029 if (txq->count >= txq->tx_stop_threshold)
2030 return MVNETA_XDP_DROPPED;
2032 tx_desc = mvneta_txq_next_desc_get(txq);
2034 buf = &txq->buf[txq->txq_put_index];
2037 dma_addr = dma_map_single(pp->dev->dev.parent, xdpf->data,
2038 xdpf->len, DMA_TO_DEVICE);
2039 if (dma_mapping_error(pp->dev->dev.parent, dma_addr)) {
2040 mvneta_txq_desc_put(txq);
2041 return MVNETA_XDP_DROPPED;
2043 buf->type = MVNETA_TYPE_XDP_NDO;
2045 struct page *page = virt_to_page(xdpf->data);
2047 dma_addr = page_pool_get_dma_addr(page) +
2048 sizeof(*xdpf) + xdpf->headroom;
2049 dma_sync_single_for_device(pp->dev->dev.parent, dma_addr,
2050 xdpf->len, DMA_BIDIRECTIONAL);
2051 buf->type = MVNETA_TYPE_XDP_TX;
2055 tx_desc->command = MVNETA_TXD_FLZ_DESC;
2056 tx_desc->buf_phys_addr = dma_addr;
2057 tx_desc->data_size = xdpf->len;
2059 mvneta_txq_inc_put(txq);
2063 return MVNETA_XDP_TX;
2067 mvneta_xdp_xmit_back(struct mvneta_port *pp, struct xdp_buff *xdp)
2069 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2070 struct mvneta_tx_queue *txq;
2071 struct netdev_queue *nq;
2072 struct xdp_frame *xdpf;
2076 xdpf = xdp_convert_buff_to_frame(xdp);
2077 if (unlikely(!xdpf))
2078 return MVNETA_XDP_DROPPED;
2080 cpu = smp_processor_id();
2081 txq = &pp->txqs[cpu % txq_number];
2082 nq = netdev_get_tx_queue(pp->dev, txq->id);
2084 __netif_tx_lock(nq, cpu);
2085 ret = mvneta_xdp_submit_frame(pp, txq, xdpf, false);
2086 if (ret == MVNETA_XDP_TX) {
2087 u64_stats_update_begin(&stats->syncp);
2088 stats->es.ps.tx_bytes += xdpf->len;
2089 stats->es.ps.tx_packets++;
2090 stats->es.ps.xdp_tx++;
2091 u64_stats_update_end(&stats->syncp);
2093 mvneta_txq_pend_desc_add(pp, txq, 0);
2095 u64_stats_update_begin(&stats->syncp);
2096 stats->es.ps.xdp_tx_err++;
2097 u64_stats_update_end(&stats->syncp);
2099 __netif_tx_unlock(nq);
2105 mvneta_xdp_xmit(struct net_device *dev, int num_frame,
2106 struct xdp_frame **frames, u32 flags)
2108 struct mvneta_port *pp = netdev_priv(dev);
2109 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2110 int i, nxmit_byte = 0, nxmit = num_frame;
2111 int cpu = smp_processor_id();
2112 struct mvneta_tx_queue *txq;
2113 struct netdev_queue *nq;
2116 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
2119 txq = &pp->txqs[cpu % txq_number];
2120 nq = netdev_get_tx_queue(pp->dev, txq->id);
2122 __netif_tx_lock(nq, cpu);
2123 for (i = 0; i < num_frame; i++) {
2124 ret = mvneta_xdp_submit_frame(pp, txq, frames[i], true);
2125 if (ret == MVNETA_XDP_TX) {
2126 nxmit_byte += frames[i]->len;
2128 xdp_return_frame_rx_napi(frames[i]);
2133 if (unlikely(flags & XDP_XMIT_FLUSH))
2134 mvneta_txq_pend_desc_add(pp, txq, 0);
2135 __netif_tx_unlock(nq);
2137 u64_stats_update_begin(&stats->syncp);
2138 stats->es.ps.tx_bytes += nxmit_byte;
2139 stats->es.ps.tx_packets += nxmit;
2140 stats->es.ps.xdp_xmit += nxmit;
2141 stats->es.ps.xdp_xmit_err += num_frame - nxmit;
2142 u64_stats_update_end(&stats->syncp);
2148 mvneta_run_xdp(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
2149 struct bpf_prog *prog, struct xdp_buff *xdp,
2150 struct mvneta_stats *stats)
2152 unsigned int len, sync;
2156 len = xdp->data_end - xdp->data_hard_start - pp->rx_offset_correction;
2157 act = bpf_prog_run_xdp(prog, xdp);
2159 /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */
2160 sync = xdp->data_end - xdp->data_hard_start - pp->rx_offset_correction;
2161 sync = max(sync, len);
2166 return MVNETA_XDP_PASS;
2167 case XDP_REDIRECT: {
2170 err = xdp_do_redirect(pp->dev, xdp, prog);
2171 if (unlikely(err)) {
2172 ret = MVNETA_XDP_DROPPED;
2173 page = virt_to_head_page(xdp->data);
2174 page_pool_put_page(rxq->page_pool, page, sync, true);
2176 ret = MVNETA_XDP_REDIR;
2177 stats->xdp_redirect++;
2182 ret = mvneta_xdp_xmit_back(pp, xdp);
2183 if (ret != MVNETA_XDP_TX) {
2184 page = virt_to_head_page(xdp->data);
2185 page_pool_put_page(rxq->page_pool, page, sync, true);
2189 bpf_warn_invalid_xdp_action(act);
2192 trace_xdp_exception(pp->dev, prog, act);
2195 page = virt_to_head_page(xdp->data);
2196 page_pool_put_page(rxq->page_pool, page, sync, true);
2197 ret = MVNETA_XDP_DROPPED;
2202 stats->rx_bytes += xdp->data_end - xdp->data;
2203 stats->rx_packets++;
2209 mvneta_swbm_rx_frame(struct mvneta_port *pp,
2210 struct mvneta_rx_desc *rx_desc,
2211 struct mvneta_rx_queue *rxq,
2212 struct xdp_buff *xdp,
2213 struct bpf_prog *xdp_prog,
2215 struct mvneta_stats *stats)
2217 unsigned char *data = page_address(page);
2218 int data_len = -MVNETA_MH_SIZE, len;
2219 struct net_device *dev = pp->dev;
2220 enum dma_data_direction dma_dir;
2223 if (MVNETA_SKB_SIZE(rx_desc->data_size) > PAGE_SIZE) {
2224 len = MVNETA_MAX_RX_BUF_SIZE;
2227 len = rx_desc->data_size;
2228 data_len += len - ETH_FCS_LEN;
2231 dma_dir = page_pool_get_dma_dir(rxq->page_pool);
2232 dma_sync_single_for_cpu(dev->dev.parent,
2233 rx_desc->buf_phys_addr,
2236 /* Prefetch header */
2239 xdp->data_hard_start = data;
2240 xdp->data = data + pp->rx_offset_correction + MVNETA_MH_SIZE;
2241 xdp->data_end = xdp->data + data_len;
2242 xdp_set_data_meta_invalid(xdp);
2245 ret = mvneta_run_xdp(pp, rxq, xdp_prog, xdp, stats);
2250 rxq->skb = build_skb(xdp->data_hard_start, PAGE_SIZE);
2251 if (unlikely(!rxq->skb)) {
2252 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2254 netdev_err(dev, "Can't allocate skb on queue %d\n", rxq->id);
2256 u64_stats_update_begin(&stats->syncp);
2257 stats->es.skb_alloc_error++;
2258 stats->rx_dropped++;
2259 u64_stats_update_end(&stats->syncp);
2263 page_pool_release_page(rxq->page_pool, page);
2265 skb_reserve(rxq->skb,
2266 xdp->data - xdp->data_hard_start);
2267 skb_put(rxq->skb, xdp->data_end - xdp->data);
2268 mvneta_rx_csum(pp, rx_desc->status, rxq->skb);
2270 rxq->left_size = rx_desc->data_size - len;
2273 rx_desc->buf_phys_addr = 0;
2279 mvneta_swbm_add_rx_fragment(struct mvneta_port *pp,
2280 struct mvneta_rx_desc *rx_desc,
2281 struct mvneta_rx_queue *rxq,
2284 struct net_device *dev = pp->dev;
2285 enum dma_data_direction dma_dir;
2288 if (rxq->left_size > MVNETA_MAX_RX_BUF_SIZE) {
2289 len = MVNETA_MAX_RX_BUF_SIZE;
2292 len = rxq->left_size;
2293 data_len = len - ETH_FCS_LEN;
2295 dma_dir = page_pool_get_dma_dir(rxq->page_pool);
2296 dma_sync_single_for_cpu(dev->dev.parent,
2297 rx_desc->buf_phys_addr,
2300 /* refill descriptor with new buffer later */
2301 skb_add_rx_frag(rxq->skb,
2302 skb_shinfo(rxq->skb)->nr_frags,
2303 page, pp->rx_offset_correction, data_len,
2306 page_pool_release_page(rxq->page_pool, page);
2307 rx_desc->buf_phys_addr = 0;
2308 rxq->left_size -= len;
2311 /* Main rx processing when using software buffer management */
2312 static int mvneta_rx_swbm(struct napi_struct *napi,
2313 struct mvneta_port *pp, int budget,
2314 struct mvneta_rx_queue *rxq)
2316 int rx_proc = 0, rx_todo, refill;
2317 struct net_device *dev = pp->dev;
2318 struct mvneta_stats ps = {};
2319 struct bpf_prog *xdp_prog;
2320 struct xdp_buff xdp_buf;
2322 /* Get number of received packets */
2323 rx_todo = mvneta_rxq_busy_desc_num_get(pp, rxq);
2326 xdp_prog = READ_ONCE(pp->xdp_prog);
2327 xdp_buf.rxq = &rxq->xdp_rxq;
2328 xdp_buf.frame_sz = PAGE_SIZE;
2330 /* Fairness NAPI loop */
2331 while (rx_proc < budget && rx_proc < rx_todo) {
2332 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
2333 u32 rx_status, index;
2336 index = rx_desc - rxq->descs;
2337 page = (struct page *)rxq->buf_virt_addr[index];
2339 rx_status = rx_desc->status;
2343 if (rx_status & MVNETA_RXD_FIRST_DESC) {
2346 /* Check errors only for FIRST descriptor */
2347 if (rx_status & MVNETA_RXD_ERR_SUMMARY) {
2348 mvneta_rx_error(pp, rx_desc);
2349 /* leave the descriptor untouched */
2353 err = mvneta_swbm_rx_frame(pp, rx_desc, rxq, &xdp_buf,
2354 xdp_prog, page, &ps);
2358 if (unlikely(!rxq->skb)) {
2359 pr_debug("no skb for rx_status 0x%x\n",
2363 mvneta_swbm_add_rx_fragment(pp, rx_desc, rxq, page);
2364 } /* Middle or Last descriptor */
2366 if (!(rx_status & MVNETA_RXD_LAST_DESC))
2367 /* no last descriptor this time */
2370 if (rxq->left_size) {
2371 pr_err("get last desc, but left_size (%d) != 0\n",
2373 dev_kfree_skb_any(rxq->skb);
2379 ps.rx_bytes += rxq->skb->len;
2382 /* Linux processing */
2383 rxq->skb->protocol = eth_type_trans(rxq->skb, dev);
2385 napi_gro_receive(napi, rxq->skb);
2387 /* clean uncomplete skb pointer in queue */
2392 if (ps.xdp_redirect)
2396 mvneta_update_stats(pp, &ps);
2398 /* return some buffers to hardware queue, one at a time is too slow */
2399 refill = mvneta_rx_refill_queue(pp, rxq);
2401 /* Update rxq management counters */
2402 mvneta_rxq_desc_num_update(pp, rxq, rx_proc, refill);
2404 return ps.rx_packets;
2407 /* Main rx processing when using hardware buffer management */
2408 static int mvneta_rx_hwbm(struct napi_struct *napi,
2409 struct mvneta_port *pp, int rx_todo,
2410 struct mvneta_rx_queue *rxq)
2412 struct net_device *dev = pp->dev;
2417 /* Get number of received packets */
2418 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
2420 if (rx_todo > rx_done)
2425 /* Fairness NAPI loop */
2426 while (rx_done < rx_todo) {
2427 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
2428 struct mvneta_bm_pool *bm_pool = NULL;
2429 struct sk_buff *skb;
2430 unsigned char *data;
2431 dma_addr_t phys_addr;
2432 u32 rx_status, frag_size;
2437 rx_status = rx_desc->status;
2438 rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
2439 data = (u8 *)(uintptr_t)rx_desc->buf_cookie;
2440 phys_addr = rx_desc->buf_phys_addr;
2441 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
2442 bm_pool = &pp->bm_priv->bm_pools[pool_id];
2444 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
2445 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
2446 err_drop_frame_ret_pool:
2447 /* Return the buffer to the pool */
2448 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
2449 rx_desc->buf_phys_addr);
2451 mvneta_rx_error(pp, rx_desc);
2452 /* leave the descriptor untouched */
2456 if (rx_bytes <= rx_copybreak) {
2457 /* better copy a small frame and not unmap the DMA region */
2458 skb = netdev_alloc_skb_ip_align(dev, rx_bytes);
2460 goto err_drop_frame_ret_pool;
2462 dma_sync_single_range_for_cpu(&pp->bm_priv->pdev->dev,
2463 rx_desc->buf_phys_addr,
2464 MVNETA_MH_SIZE + NET_SKB_PAD,
2467 skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD,
2470 skb->protocol = eth_type_trans(skb, dev);
2471 mvneta_rx_csum(pp, rx_status, skb);
2472 napi_gro_receive(napi, skb);
2475 rcvd_bytes += rx_bytes;
2477 /* Return the buffer to the pool */
2478 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
2479 rx_desc->buf_phys_addr);
2481 /* leave the descriptor and buffer untouched */
2485 /* Refill processing */
2486 err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC);
2488 struct mvneta_pcpu_stats *stats;
2490 netdev_err(dev, "Linux processing - Can't refill\n");
2492 stats = this_cpu_ptr(pp->stats);
2493 u64_stats_update_begin(&stats->syncp);
2494 stats->es.refill_error++;
2495 u64_stats_update_end(&stats->syncp);
2497 goto err_drop_frame_ret_pool;
2500 frag_size = bm_pool->hwbm_pool.frag_size;
2502 skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size);
2504 /* After refill old buffer has to be unmapped regardless
2505 * the skb is successfully built or not.
2507 dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr,
2508 bm_pool->buf_size, DMA_FROM_DEVICE);
2510 goto err_drop_frame;
2513 rcvd_bytes += rx_bytes;
2515 /* Linux processing */
2516 skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD);
2517 skb_put(skb, rx_bytes);
2519 skb->protocol = eth_type_trans(skb, dev);
2521 mvneta_rx_csum(pp, rx_status, skb);
2523 napi_gro_receive(napi, skb);
2527 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2529 u64_stats_update_begin(&stats->syncp);
2530 stats->es.ps.rx_packets += rcvd_pkts;
2531 stats->es.ps.rx_bytes += rcvd_bytes;
2532 u64_stats_update_end(&stats->syncp);
2535 /* Update rxq management counters */
2536 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
2542 mvneta_tso_put_hdr(struct sk_buff *skb,
2543 struct mvneta_port *pp, struct mvneta_tx_queue *txq)
2545 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2546 struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index];
2547 struct mvneta_tx_desc *tx_desc;
2549 tx_desc = mvneta_txq_next_desc_get(txq);
2550 tx_desc->data_size = hdr_len;
2551 tx_desc->command = mvneta_skb_tx_csum(pp, skb);
2552 tx_desc->command |= MVNETA_TXD_F_DESC;
2553 tx_desc->buf_phys_addr = txq->tso_hdrs_phys +
2554 txq->txq_put_index * TSO_HEADER_SIZE;
2555 buf->type = MVNETA_TYPE_SKB;
2558 mvneta_txq_inc_put(txq);
2562 mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq,
2563 struct sk_buff *skb, char *data, int size,
2564 bool last_tcp, bool is_last)
2566 struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index];
2567 struct mvneta_tx_desc *tx_desc;
2569 tx_desc = mvneta_txq_next_desc_get(txq);
2570 tx_desc->data_size = size;
2571 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data,
2572 size, DMA_TO_DEVICE);
2573 if (unlikely(dma_mapping_error(dev->dev.parent,
2574 tx_desc->buf_phys_addr))) {
2575 mvneta_txq_desc_put(txq);
2579 tx_desc->command = 0;
2580 buf->type = MVNETA_TYPE_SKB;
2584 /* last descriptor in the TCP packet */
2585 tx_desc->command = MVNETA_TXD_L_DESC;
2587 /* last descriptor in SKB */
2591 mvneta_txq_inc_put(txq);
2595 static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev,
2596 struct mvneta_tx_queue *txq)
2598 int total_len, data_left;
2600 struct mvneta_port *pp = netdev_priv(dev);
2602 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2605 /* Count needed descriptors */
2606 if ((txq->count + tso_count_descs(skb)) >= txq->size)
2609 if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) {
2610 pr_info("*** Is this even possible???!?!?\n");
2614 /* Initialize the TSO handler, and prepare the first payload */
2615 tso_start(skb, &tso);
2617 total_len = skb->len - hdr_len;
2618 while (total_len > 0) {
2621 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
2622 total_len -= data_left;
2625 /* prepare packet headers: MAC + IP + TCP */
2626 hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE;
2627 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
2629 mvneta_tso_put_hdr(skb, pp, txq);
2631 while (data_left > 0) {
2635 size = min_t(int, tso.size, data_left);
2637 if (mvneta_tso_put_data(dev, txq, skb,
2644 tso_build_data(skb, &tso, size);
2651 /* Release all used data descriptors; header descriptors must not
2654 for (i = desc_count - 1; i >= 0; i--) {
2655 struct mvneta_tx_desc *tx_desc = txq->descs + i;
2656 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr))
2657 dma_unmap_single(pp->dev->dev.parent,
2658 tx_desc->buf_phys_addr,
2661 mvneta_txq_desc_put(txq);
2666 /* Handle tx fragmentation processing */
2667 static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb,
2668 struct mvneta_tx_queue *txq)
2670 struct mvneta_tx_desc *tx_desc;
2671 int i, nr_frags = skb_shinfo(skb)->nr_frags;
2673 for (i = 0; i < nr_frags; i++) {
2674 struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index];
2675 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2676 void *addr = skb_frag_address(frag);
2678 tx_desc = mvneta_txq_next_desc_get(txq);
2679 tx_desc->data_size = skb_frag_size(frag);
2681 tx_desc->buf_phys_addr =
2682 dma_map_single(pp->dev->dev.parent, addr,
2683 tx_desc->data_size, DMA_TO_DEVICE);
2685 if (dma_mapping_error(pp->dev->dev.parent,
2686 tx_desc->buf_phys_addr)) {
2687 mvneta_txq_desc_put(txq);
2691 if (i == nr_frags - 1) {
2692 /* Last descriptor */
2693 tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD;
2696 /* Descriptor in the middle: Not First, Not Last */
2697 tx_desc->command = 0;
2700 buf->type = MVNETA_TYPE_SKB;
2701 mvneta_txq_inc_put(txq);
2707 /* Release all descriptors that were used to map fragments of
2708 * this packet, as well as the corresponding DMA mappings
2710 for (i = i - 1; i >= 0; i--) {
2711 tx_desc = txq->descs + i;
2712 dma_unmap_single(pp->dev->dev.parent,
2713 tx_desc->buf_phys_addr,
2716 mvneta_txq_desc_put(txq);
2722 /* Main tx processing */
2723 static netdev_tx_t mvneta_tx(struct sk_buff *skb, struct net_device *dev)
2725 struct mvneta_port *pp = netdev_priv(dev);
2726 u16 txq_id = skb_get_queue_mapping(skb);
2727 struct mvneta_tx_queue *txq = &pp->txqs[txq_id];
2728 struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index];
2729 struct mvneta_tx_desc *tx_desc;
2734 if (!netif_running(dev))
2737 if (skb_is_gso(skb)) {
2738 frags = mvneta_tx_tso(skb, dev, txq);
2742 frags = skb_shinfo(skb)->nr_frags + 1;
2744 /* Get a descriptor for the first part of the packet */
2745 tx_desc = mvneta_txq_next_desc_get(txq);
2747 tx_cmd = mvneta_skb_tx_csum(pp, skb);
2749 tx_desc->data_size = skb_headlen(skb);
2751 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data,
2754 if (unlikely(dma_mapping_error(dev->dev.parent,
2755 tx_desc->buf_phys_addr))) {
2756 mvneta_txq_desc_put(txq);
2761 buf->type = MVNETA_TYPE_SKB;
2763 /* First and Last descriptor */
2764 tx_cmd |= MVNETA_TXD_FLZ_DESC;
2765 tx_desc->command = tx_cmd;
2767 mvneta_txq_inc_put(txq);
2769 /* First but not Last */
2770 tx_cmd |= MVNETA_TXD_F_DESC;
2772 mvneta_txq_inc_put(txq);
2773 tx_desc->command = tx_cmd;
2774 /* Continue with other skb fragments */
2775 if (mvneta_tx_frag_process(pp, skb, txq)) {
2776 dma_unmap_single(dev->dev.parent,
2777 tx_desc->buf_phys_addr,
2780 mvneta_txq_desc_put(txq);
2788 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
2789 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2791 netdev_tx_sent_queue(nq, len);
2793 txq->count += frags;
2794 if (txq->count >= txq->tx_stop_threshold)
2795 netif_tx_stop_queue(nq);
2797 if (!netdev_xmit_more() || netif_xmit_stopped(nq) ||
2798 txq->pending + frags > MVNETA_TXQ_DEC_SENT_MASK)
2799 mvneta_txq_pend_desc_add(pp, txq, frags);
2801 txq->pending += frags;
2803 u64_stats_update_begin(&stats->syncp);
2804 stats->es.ps.tx_bytes += len;
2805 stats->es.ps.tx_packets++;
2806 u64_stats_update_end(&stats->syncp);
2808 dev->stats.tx_dropped++;
2809 dev_kfree_skb_any(skb);
2812 return NETDEV_TX_OK;
2816 /* Free tx resources, when resetting a port */
2817 static void mvneta_txq_done_force(struct mvneta_port *pp,
2818 struct mvneta_tx_queue *txq)
2821 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
2822 int tx_done = txq->count;
2824 mvneta_txq_bufs_free(pp, txq, tx_done, nq);
2828 txq->txq_put_index = 0;
2829 txq->txq_get_index = 0;
2832 /* Handle tx done - called in softirq context. The <cause_tx_done> argument
2833 * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL.
2835 static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done)
2837 struct mvneta_tx_queue *txq;
2838 struct netdev_queue *nq;
2839 int cpu = smp_processor_id();
2841 while (cause_tx_done) {
2842 txq = mvneta_tx_done_policy(pp, cause_tx_done);
2844 nq = netdev_get_tx_queue(pp->dev, txq->id);
2845 __netif_tx_lock(nq, cpu);
2848 mvneta_txq_done(pp, txq);
2850 __netif_tx_unlock(nq);
2851 cause_tx_done &= ~((1 << txq->id));
2855 /* Compute crc8 of the specified address, using a unique algorithm ,
2856 * according to hw spec, different than generic crc8 algorithm
2858 static int mvneta_addr_crc(unsigned char *addr)
2863 for (i = 0; i < ETH_ALEN; i++) {
2866 crc = (crc ^ addr[i]) << 8;
2867 for (j = 7; j >= 0; j--) {
2868 if (crc & (0x100 << j))
2876 /* This method controls the net device special MAC multicast support.
2877 * The Special Multicast Table for MAC addresses supports MAC of the form
2878 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
2879 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2880 * Table entries in the DA-Filter table. This method set the Special
2881 * Multicast Table appropriate entry.
2883 static void mvneta_set_special_mcast_addr(struct mvneta_port *pp,
2884 unsigned char last_byte,
2887 unsigned int smc_table_reg;
2888 unsigned int tbl_offset;
2889 unsigned int reg_offset;
2891 /* Register offset from SMC table base */
2892 tbl_offset = (last_byte / 4);
2893 /* Entry offset within the above reg */
2894 reg_offset = last_byte % 4;
2896 smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST
2900 smc_table_reg &= ~(0xff << (8 * reg_offset));
2902 smc_table_reg &= ~(0xff << (8 * reg_offset));
2903 smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
2906 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4,
2910 /* This method controls the network device Other MAC multicast support.
2911 * The Other Multicast Table is used for multicast of another type.
2912 * A CRC-8 is used as an index to the Other Multicast Table entries
2913 * in the DA-Filter table.
2914 * The method gets the CRC-8 value from the calling routine and
2915 * sets the Other Multicast Table appropriate entry according to the
2918 static void mvneta_set_other_mcast_addr(struct mvneta_port *pp,
2922 unsigned int omc_table_reg;
2923 unsigned int tbl_offset;
2924 unsigned int reg_offset;
2926 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
2927 reg_offset = crc8 % 4; /* Entry offset within the above reg */
2929 omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset);
2932 /* Clear accepts frame bit at specified Other DA table entry */
2933 omc_table_reg &= ~(0xff << (8 * reg_offset));
2935 omc_table_reg &= ~(0xff << (8 * reg_offset));
2936 omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
2939 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg);
2942 /* The network device supports multicast using two tables:
2943 * 1) Special Multicast Table for MAC addresses of the form
2944 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
2945 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2946 * Table entries in the DA-Filter table.
2947 * 2) Other Multicast Table for multicast of another type. A CRC-8 value
2948 * is used as an index to the Other Multicast Table entries in the
2951 static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr,
2954 unsigned char crc_result = 0;
2956 if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) {
2957 mvneta_set_special_mcast_addr(pp, p_addr[5], queue);
2961 crc_result = mvneta_addr_crc(p_addr);
2963 if (pp->mcast_count[crc_result] == 0) {
2964 netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n",
2969 pp->mcast_count[crc_result]--;
2970 if (pp->mcast_count[crc_result] != 0) {
2971 netdev_info(pp->dev,
2972 "After delete there are %d valid Mcast for crc8=0x%02x\n",
2973 pp->mcast_count[crc_result], crc_result);
2977 pp->mcast_count[crc_result]++;
2979 mvneta_set_other_mcast_addr(pp, crc_result, queue);
2984 /* Configure Fitering mode of Ethernet port */
2985 static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp,
2988 u32 port_cfg_reg, val;
2990 port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG);
2992 val = mvreg_read(pp, MVNETA_TYPE_PRIO);
2994 /* Set / Clear UPM bit in port configuration register */
2996 /* Accept all Unicast addresses */
2997 port_cfg_reg |= MVNETA_UNI_PROMISC_MODE;
2998 val |= MVNETA_FORCE_UNI;
2999 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff);
3000 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff);
3002 /* Reject all Unicast addresses */
3003 port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE;
3004 val &= ~MVNETA_FORCE_UNI;
3007 mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg);
3008 mvreg_write(pp, MVNETA_TYPE_PRIO, val);
3011 /* register unicast and multicast addresses */
3012 static void mvneta_set_rx_mode(struct net_device *dev)
3014 struct mvneta_port *pp = netdev_priv(dev);
3015 struct netdev_hw_addr *ha;
3017 if (dev->flags & IFF_PROMISC) {
3018 /* Accept all: Multicast + Unicast */
3019 mvneta_rx_unicast_promisc_set(pp, 1);
3020 mvneta_set_ucast_table(pp, pp->rxq_def);
3021 mvneta_set_special_mcast_table(pp, pp->rxq_def);
3022 mvneta_set_other_mcast_table(pp, pp->rxq_def);
3024 /* Accept single Unicast */
3025 mvneta_rx_unicast_promisc_set(pp, 0);
3026 mvneta_set_ucast_table(pp, -1);
3027 mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def);
3029 if (dev->flags & IFF_ALLMULTI) {
3030 /* Accept all multicast */
3031 mvneta_set_special_mcast_table(pp, pp->rxq_def);
3032 mvneta_set_other_mcast_table(pp, pp->rxq_def);
3034 /* Accept only initialized multicast */
3035 mvneta_set_special_mcast_table(pp, -1);
3036 mvneta_set_other_mcast_table(pp, -1);
3038 if (!netdev_mc_empty(dev)) {
3039 netdev_for_each_mc_addr(ha, dev) {
3040 mvneta_mcast_addr_set(pp, ha->addr,
3048 /* Interrupt handling - the callback for request_irq() */
3049 static irqreturn_t mvneta_isr(int irq, void *dev_id)
3051 struct mvneta_port *pp = (struct mvneta_port *)dev_id;
3053 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
3054 napi_schedule(&pp->napi);
3059 /* Interrupt handling - the callback for request_percpu_irq() */
3060 static irqreturn_t mvneta_percpu_isr(int irq, void *dev_id)
3062 struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id;
3064 disable_percpu_irq(port->pp->dev->irq);
3065 napi_schedule(&port->napi);
3070 static void mvneta_link_change(struct mvneta_port *pp)
3072 u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
3074 phylink_mac_change(pp->phylink, !!(gmac_stat & MVNETA_GMAC_LINK_UP));
3078 * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
3079 * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
3080 * Bits 8 -15 of the cause Rx Tx register indicate that are received
3081 * packets on the corresponding RXQ (Bit 8 is for RX queue 0).
3082 * Each CPU has its own causeRxTx register
3084 static int mvneta_poll(struct napi_struct *napi, int budget)
3089 struct mvneta_port *pp = netdev_priv(napi->dev);
3090 struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
3092 if (!netif_running(pp->dev)) {
3093 napi_complete(napi);
3097 /* Read cause register */
3098 cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE);
3099 if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) {
3100 u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE);
3102 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
3104 if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE |
3105 MVNETA_CAUSE_LINK_CHANGE))
3106 mvneta_link_change(pp);
3109 /* Release Tx descriptors */
3110 if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) {
3111 mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL));
3112 cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL;
3115 /* For the case where the last mvneta_poll did not process all
3118 cause_rx_tx |= pp->neta_armada3700 ? pp->cause_rx_tx :
3121 rx_queue = fls(((cause_rx_tx >> 8) & 0xff));
3123 rx_queue = rx_queue - 1;
3125 rx_done = mvneta_rx_hwbm(napi, pp, budget,
3126 &pp->rxqs[rx_queue]);
3128 rx_done = mvneta_rx_swbm(napi, pp, budget,
3129 &pp->rxqs[rx_queue]);
3132 if (rx_done < budget) {
3134 napi_complete_done(napi, rx_done);
3136 if (pp->neta_armada3700) {
3137 unsigned long flags;
3139 local_irq_save(flags);
3140 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
3141 MVNETA_RX_INTR_MASK(rxq_number) |
3142 MVNETA_TX_INTR_MASK(txq_number) |
3143 MVNETA_MISCINTR_INTR_MASK);
3144 local_irq_restore(flags);
3146 enable_percpu_irq(pp->dev->irq, 0);
3150 if (pp->neta_armada3700)
3151 pp->cause_rx_tx = cause_rx_tx;
3153 port->cause_rx_tx = cause_rx_tx;
3158 static int mvneta_create_page_pool(struct mvneta_port *pp,
3159 struct mvneta_rx_queue *rxq, int size)
3161 struct bpf_prog *xdp_prog = READ_ONCE(pp->xdp_prog);
3162 struct page_pool_params pp_params = {
3164 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
3166 .nid = NUMA_NO_NODE,
3167 .dev = pp->dev->dev.parent,
3168 .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE,
3169 .offset = pp->rx_offset_correction,
3170 .max_len = MVNETA_MAX_RX_BUF_SIZE,
3174 rxq->page_pool = page_pool_create(&pp_params);
3175 if (IS_ERR(rxq->page_pool)) {
3176 err = PTR_ERR(rxq->page_pool);
3177 rxq->page_pool = NULL;
3181 err = xdp_rxq_info_reg(&rxq->xdp_rxq, pp->dev, rxq->id);
3185 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL,
3188 goto err_unregister_rxq;
3193 xdp_rxq_info_unreg(&rxq->xdp_rxq);
3195 page_pool_destroy(rxq->page_pool);
3196 rxq->page_pool = NULL;
3200 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
3201 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
3206 err = mvneta_create_page_pool(pp, rxq, num);
3210 for (i = 0; i < num; i++) {
3211 memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc));
3212 if (mvneta_rx_refill(pp, rxq->descs + i, rxq,
3215 "%s:rxq %d, %d of %d buffs filled\n",
3216 __func__, rxq->id, i, num);
3221 /* Add this number of RX descriptors as non occupied (ready to
3224 mvneta_rxq_non_occup_desc_add(pp, rxq, i);
3229 /* Free all packets pending transmit from all TXQs and reset TX port */
3230 static void mvneta_tx_reset(struct mvneta_port *pp)
3234 /* free the skb's in the tx ring */
3235 for (queue = 0; queue < txq_number; queue++)
3236 mvneta_txq_done_force(pp, &pp->txqs[queue]);
3238 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
3239 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
3242 static void mvneta_rx_reset(struct mvneta_port *pp)
3244 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
3245 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
3248 /* Rx/Tx queue initialization/cleanup methods */
3250 static int mvneta_rxq_sw_init(struct mvneta_port *pp,
3251 struct mvneta_rx_queue *rxq)
3253 rxq->size = pp->rx_ring_size;
3255 /* Allocate memory for RX descriptors */
3256 rxq->descs = dma_alloc_coherent(pp->dev->dev.parent,
3257 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
3258 &rxq->descs_phys, GFP_KERNEL);
3262 rxq->last_desc = rxq->size - 1;
3267 static void mvneta_rxq_hw_init(struct mvneta_port *pp,
3268 struct mvneta_rx_queue *rxq)
3270 /* Set Rx descriptors queue starting address */
3271 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
3272 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
3274 /* Set coalescing pkts and time */
3275 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
3276 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
3280 mvneta_rxq_offset_set(pp, rxq, 0);
3281 mvneta_rxq_buf_size_set(pp, rxq, PAGE_SIZE < SZ_64K ?
3282 MVNETA_MAX_RX_BUF_SIZE :
3283 MVNETA_RX_BUF_SIZE(pp->pkt_size));
3284 mvneta_rxq_bm_disable(pp, rxq);
3285 mvneta_rxq_fill(pp, rxq, rxq->size);
3288 mvneta_rxq_offset_set(pp, rxq,
3289 NET_SKB_PAD - pp->rx_offset_correction);
3291 mvneta_rxq_bm_enable(pp, rxq);
3292 /* Fill RXQ with buffers from RX pool */
3293 mvneta_rxq_long_pool_set(pp, rxq);
3294 mvneta_rxq_short_pool_set(pp, rxq);
3295 mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size);
3299 /* Create a specified RX queue */
3300 static int mvneta_rxq_init(struct mvneta_port *pp,
3301 struct mvneta_rx_queue *rxq)
3306 ret = mvneta_rxq_sw_init(pp, rxq);
3310 mvneta_rxq_hw_init(pp, rxq);
3315 /* Cleanup Rx queue */
3316 static void mvneta_rxq_deinit(struct mvneta_port *pp,
3317 struct mvneta_rx_queue *rxq)
3319 mvneta_rxq_drop_pkts(pp, rxq);
3322 dev_kfree_skb_any(rxq->skb);
3325 dma_free_coherent(pp->dev->dev.parent,
3326 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
3332 rxq->next_desc_to_proc = 0;
3333 rxq->descs_phys = 0;
3334 rxq->first_to_refill = 0;
3335 rxq->refill_num = 0;
3340 static int mvneta_txq_sw_init(struct mvneta_port *pp,
3341 struct mvneta_tx_queue *txq)
3345 txq->size = pp->tx_ring_size;
3347 /* A queue must always have room for at least one skb.
3348 * Therefore, stop the queue when the free entries reaches
3349 * the maximum number of descriptors per skb.
3351 txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS;
3352 txq->tx_wake_threshold = txq->tx_stop_threshold / 2;
3354 /* Allocate memory for TX descriptors */
3355 txq->descs = dma_alloc_coherent(pp->dev->dev.parent,
3356 txq->size * MVNETA_DESC_ALIGNED_SIZE,
3357 &txq->descs_phys, GFP_KERNEL);
3361 txq->last_desc = txq->size - 1;
3363 txq->buf = kmalloc_array(txq->size, sizeof(*txq->buf), GFP_KERNEL);
3365 dma_free_coherent(pp->dev->dev.parent,
3366 txq->size * MVNETA_DESC_ALIGNED_SIZE,
3367 txq->descs, txq->descs_phys);
3371 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
3372 txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent,
3373 txq->size * TSO_HEADER_SIZE,
3374 &txq->tso_hdrs_phys, GFP_KERNEL);
3375 if (!txq->tso_hdrs) {
3377 dma_free_coherent(pp->dev->dev.parent,
3378 txq->size * MVNETA_DESC_ALIGNED_SIZE,
3379 txq->descs, txq->descs_phys);
3383 /* Setup XPS mapping */
3385 cpu = txq->id % num_present_cpus();
3387 cpu = pp->rxq_def % num_present_cpus();
3388 cpumask_set_cpu(cpu, &txq->affinity_mask);
3389 netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id);
3394 static void mvneta_txq_hw_init(struct mvneta_port *pp,
3395 struct mvneta_tx_queue *txq)
3397 /* Set maximum bandwidth for enabled TXQs */
3398 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
3399 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
3401 /* Set Tx descriptors queue starting address */
3402 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
3403 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
3405 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
3408 /* Create and initialize a tx queue */
3409 static int mvneta_txq_init(struct mvneta_port *pp,
3410 struct mvneta_tx_queue *txq)
3414 ret = mvneta_txq_sw_init(pp, txq);
3418 mvneta_txq_hw_init(pp, txq);
3423 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
3424 static void mvneta_txq_sw_deinit(struct mvneta_port *pp,
3425 struct mvneta_tx_queue *txq)
3427 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
3432 dma_free_coherent(pp->dev->dev.parent,
3433 txq->size * TSO_HEADER_SIZE,
3434 txq->tso_hdrs, txq->tso_hdrs_phys);
3436 dma_free_coherent(pp->dev->dev.parent,
3437 txq->size * MVNETA_DESC_ALIGNED_SIZE,
3438 txq->descs, txq->descs_phys);
3440 netdev_tx_reset_queue(nq);
3444 txq->next_desc_to_proc = 0;
3445 txq->descs_phys = 0;
3448 static void mvneta_txq_hw_deinit(struct mvneta_port *pp,
3449 struct mvneta_tx_queue *txq)
3451 /* Set minimum bandwidth for disabled TXQs */
3452 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
3453 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
3455 /* Set Tx descriptors queue starting address and size */
3456 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
3457 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
3460 static void mvneta_txq_deinit(struct mvneta_port *pp,
3461 struct mvneta_tx_queue *txq)
3463 mvneta_txq_sw_deinit(pp, txq);
3464 mvneta_txq_hw_deinit(pp, txq);
3467 /* Cleanup all Tx queues */
3468 static void mvneta_cleanup_txqs(struct mvneta_port *pp)
3472 for (queue = 0; queue < txq_number; queue++)
3473 mvneta_txq_deinit(pp, &pp->txqs[queue]);
3476 /* Cleanup all Rx queues */
3477 static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
3481 for (queue = 0; queue < rxq_number; queue++)
3482 mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
3486 /* Init all Rx queues */
3487 static int mvneta_setup_rxqs(struct mvneta_port *pp)
3491 for (queue = 0; queue < rxq_number; queue++) {
3492 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
3495 netdev_err(pp->dev, "%s: can't create rxq=%d\n",
3497 mvneta_cleanup_rxqs(pp);
3505 /* Init all tx queues */
3506 static int mvneta_setup_txqs(struct mvneta_port *pp)
3510 for (queue = 0; queue < txq_number; queue++) {
3511 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
3513 netdev_err(pp->dev, "%s: can't create txq=%d\n",
3515 mvneta_cleanup_txqs(pp);
3523 static int mvneta_comphy_init(struct mvneta_port *pp)
3530 ret = phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET,
3535 return phy_power_on(pp->comphy);
3538 static void mvneta_start_dev(struct mvneta_port *pp)
3542 WARN_ON(mvneta_comphy_init(pp));
3544 mvneta_max_rx_size_set(pp, pp->pkt_size);
3545 mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
3547 /* start the Rx/Tx activity */
3548 mvneta_port_enable(pp);
3550 if (!pp->neta_armada3700) {
3551 /* Enable polling on the port */
3552 for_each_online_cpu(cpu) {
3553 struct mvneta_pcpu_port *port =
3554 per_cpu_ptr(pp->ports, cpu);
3556 napi_enable(&port->napi);
3559 napi_enable(&pp->napi);
3562 /* Unmask interrupts. It has to be done from each CPU */
3563 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
3565 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
3566 MVNETA_CAUSE_PHY_STATUS_CHANGE |
3567 MVNETA_CAUSE_LINK_CHANGE);
3569 phylink_start(pp->phylink);
3570 netif_tx_start_all_queues(pp->dev);
3573 static void mvneta_stop_dev(struct mvneta_port *pp)
3577 phylink_stop(pp->phylink);
3579 if (!pp->neta_armada3700) {
3580 for_each_online_cpu(cpu) {
3581 struct mvneta_pcpu_port *port =
3582 per_cpu_ptr(pp->ports, cpu);
3584 napi_disable(&port->napi);
3587 napi_disable(&pp->napi);
3590 netif_carrier_off(pp->dev);
3592 mvneta_port_down(pp);
3593 netif_tx_stop_all_queues(pp->dev);
3595 /* Stop the port activity */
3596 mvneta_port_disable(pp);
3598 /* Clear all ethernet port interrupts */
3599 on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
3601 /* Mask all ethernet port interrupts */
3602 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
3604 mvneta_tx_reset(pp);
3605 mvneta_rx_reset(pp);
3607 WARN_ON(phy_power_off(pp->comphy));
3610 static void mvneta_percpu_enable(void *arg)
3612 struct mvneta_port *pp = arg;
3614 enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE);
3617 static void mvneta_percpu_disable(void *arg)
3619 struct mvneta_port *pp = arg;
3621 disable_percpu_irq(pp->dev->irq);
3624 /* Change the device mtu */
3625 static int mvneta_change_mtu(struct net_device *dev, int mtu)
3627 struct mvneta_port *pp = netdev_priv(dev);
3630 if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) {
3631 netdev_info(dev, "Illegal MTU value %d, rounding to %d\n",
3632 mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8));
3633 mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8);
3636 if (pp->xdp_prog && mtu > MVNETA_MAX_RX_BUF_SIZE) {
3637 netdev_info(dev, "Illegal MTU value %d for XDP mode\n", mtu);
3643 if (!netif_running(dev)) {
3645 mvneta_bm_update_mtu(pp, mtu);
3647 netdev_update_features(dev);
3651 /* The interface is running, so we have to force a
3652 * reallocation of the queues
3654 mvneta_stop_dev(pp);
3655 on_each_cpu(mvneta_percpu_disable, pp, true);
3657 mvneta_cleanup_txqs(pp);
3658 mvneta_cleanup_rxqs(pp);
3661 mvneta_bm_update_mtu(pp, mtu);
3663 pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu);
3665 ret = mvneta_setup_rxqs(pp);
3667 netdev_err(dev, "unable to setup rxqs after MTU change\n");
3671 ret = mvneta_setup_txqs(pp);
3673 netdev_err(dev, "unable to setup txqs after MTU change\n");
3677 on_each_cpu(mvneta_percpu_enable, pp, true);
3678 mvneta_start_dev(pp);
3680 netdev_update_features(dev);
3685 static netdev_features_t mvneta_fix_features(struct net_device *dev,
3686 netdev_features_t features)
3688 struct mvneta_port *pp = netdev_priv(dev);
3690 if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) {
3691 features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO);
3693 "Disable IP checksum for MTU greater than %dB\n",
3700 /* Get mac address */
3701 static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr)
3703 u32 mac_addr_l, mac_addr_h;
3705 mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW);
3706 mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH);
3707 addr[0] = (mac_addr_h >> 24) & 0xFF;
3708 addr[1] = (mac_addr_h >> 16) & 0xFF;
3709 addr[2] = (mac_addr_h >> 8) & 0xFF;
3710 addr[3] = mac_addr_h & 0xFF;
3711 addr[4] = (mac_addr_l >> 8) & 0xFF;
3712 addr[5] = mac_addr_l & 0xFF;
3715 /* Handle setting mac address */
3716 static int mvneta_set_mac_addr(struct net_device *dev, void *addr)
3718 struct mvneta_port *pp = netdev_priv(dev);
3719 struct sockaddr *sockaddr = addr;
3722 ret = eth_prepare_mac_addr_change(dev, addr);
3725 /* Remove previous address table entry */
3726 mvneta_mac_addr_set(pp, dev->dev_addr, -1);
3728 /* Set new addr in hw */
3729 mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def);
3731 eth_commit_mac_addr_change(dev, addr);
3735 static void mvneta_validate(struct phylink_config *config,
3736 unsigned long *supported,
3737 struct phylink_link_state *state)
3739 struct net_device *ndev = to_net_dev(config->dev);
3740 struct mvneta_port *pp = netdev_priv(ndev);
3741 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
3743 /* We only support QSGMII, SGMII, 802.3z and RGMII modes */
3744 if (state->interface != PHY_INTERFACE_MODE_NA &&
3745 state->interface != PHY_INTERFACE_MODE_QSGMII &&
3746 state->interface != PHY_INTERFACE_MODE_SGMII &&
3747 !phy_interface_mode_is_8023z(state->interface) &&
3748 !phy_interface_mode_is_rgmii(state->interface)) {
3749 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
3753 /* Allow all the expected bits */
3754 phylink_set(mask, Autoneg);
3755 phylink_set_port_modes(mask);
3757 /* Asymmetric pause is unsupported */
3758 phylink_set(mask, Pause);
3760 /* Half-duplex at speeds higher than 100Mbit is unsupported */
3761 if (pp->comphy || state->interface != PHY_INTERFACE_MODE_2500BASEX) {
3762 phylink_set(mask, 1000baseT_Full);
3763 phylink_set(mask, 1000baseX_Full);
3765 if (pp->comphy || state->interface == PHY_INTERFACE_MODE_2500BASEX) {
3766 phylink_set(mask, 2500baseT_Full);
3767 phylink_set(mask, 2500baseX_Full);
3770 if (!phy_interface_mode_is_8023z(state->interface)) {
3771 /* 10M and 100M are only supported in non-802.3z mode */
3772 phylink_set(mask, 10baseT_Half);
3773 phylink_set(mask, 10baseT_Full);
3774 phylink_set(mask, 100baseT_Half);
3775 phylink_set(mask, 100baseT_Full);
3778 bitmap_and(supported, supported, mask,
3779 __ETHTOOL_LINK_MODE_MASK_NBITS);
3780 bitmap_and(state->advertising, state->advertising, mask,
3781 __ETHTOOL_LINK_MODE_MASK_NBITS);
3783 /* We can only operate at 2500BaseX or 1000BaseX. If requested
3784 * to advertise both, only report advertising at 2500BaseX.
3786 phylink_helper_basex_speed(state);
3789 static void mvneta_mac_pcs_get_state(struct phylink_config *config,
3790 struct phylink_link_state *state)
3792 struct net_device *ndev = to_net_dev(config->dev);
3793 struct mvneta_port *pp = netdev_priv(ndev);
3796 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
3798 if (gmac_stat & MVNETA_GMAC_SPEED_1000)
3800 state->interface == PHY_INTERFACE_MODE_2500BASEX ?
3801 SPEED_2500 : SPEED_1000;
3802 else if (gmac_stat & MVNETA_GMAC_SPEED_100)
3803 state->speed = SPEED_100;
3805 state->speed = SPEED_10;
3807 state->an_complete = !!(gmac_stat & MVNETA_GMAC_AN_COMPLETE);
3808 state->link = !!(gmac_stat & MVNETA_GMAC_LINK_UP);
3809 state->duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX);
3812 if (gmac_stat & MVNETA_GMAC_RX_FLOW_CTRL_ENABLE)
3813 state->pause |= MLO_PAUSE_RX;
3814 if (gmac_stat & MVNETA_GMAC_TX_FLOW_CTRL_ENABLE)
3815 state->pause |= MLO_PAUSE_TX;
3818 static void mvneta_mac_an_restart(struct phylink_config *config)
3820 struct net_device *ndev = to_net_dev(config->dev);
3821 struct mvneta_port *pp = netdev_priv(ndev);
3822 u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3824 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
3825 gmac_an | MVNETA_GMAC_INBAND_RESTART_AN);
3826 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
3827 gmac_an & ~MVNETA_GMAC_INBAND_RESTART_AN);
3830 static void mvneta_mac_config(struct phylink_config *config, unsigned int mode,
3831 const struct phylink_link_state *state)
3833 struct net_device *ndev = to_net_dev(config->dev);
3834 struct mvneta_port *pp = netdev_priv(ndev);
3835 u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
3836 u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
3837 u32 new_ctrl4, gmac_ctrl4 = mvreg_read(pp, MVNETA_GMAC_CTRL_4);
3838 u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
3839 u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3841 new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X;
3842 new_ctrl2 = gmac_ctrl2 & ~(MVNETA_GMAC2_INBAND_AN_ENABLE |
3843 MVNETA_GMAC2_PORT_RESET);
3844 new_ctrl4 = gmac_ctrl4 & ~(MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE);
3845 new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE;
3846 new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE |
3847 MVNETA_GMAC_INBAND_RESTART_AN |
3848 MVNETA_GMAC_AN_SPEED_EN |
3849 MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL |
3850 MVNETA_GMAC_AN_FLOW_CTRL_EN |
3851 MVNETA_GMAC_AN_DUPLEX_EN);
3853 /* Even though it might look weird, when we're configured in
3854 * SGMII or QSGMII mode, the RGMII bit needs to be set.
3856 new_ctrl2 |= MVNETA_GMAC2_PORT_RGMII;
3858 if (state->interface == PHY_INTERFACE_MODE_QSGMII ||
3859 state->interface == PHY_INTERFACE_MODE_SGMII ||
3860 phy_interface_mode_is_8023z(state->interface))
3861 new_ctrl2 |= MVNETA_GMAC2_PCS_ENABLE;
3863 if (phylink_test(state->advertising, Pause))
3864 new_an |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL;
3866 if (!phylink_autoneg_inband(mode)) {
3867 /* Phy or fixed speed - nothing to do, leave the
3868 * configured speed, duplex and flow control as-is.
3870 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
3871 /* SGMII mode receives the state from the PHY */
3872 new_ctrl2 |= MVNETA_GMAC2_INBAND_AN_ENABLE;
3873 new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
3874 new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN |
3875 MVNETA_GMAC_FORCE_LINK_PASS |
3876 MVNETA_GMAC_CONFIG_MII_SPEED |
3877 MVNETA_GMAC_CONFIG_GMII_SPEED |
3878 MVNETA_GMAC_CONFIG_FULL_DUPLEX)) |
3879 MVNETA_GMAC_INBAND_AN_ENABLE |
3880 MVNETA_GMAC_AN_SPEED_EN |
3881 MVNETA_GMAC_AN_DUPLEX_EN;
3883 /* 802.3z negotiation - only 1000base-X */
3884 new_ctrl0 |= MVNETA_GMAC0_PORT_1000BASE_X;
3885 new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
3886 new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN |
3887 MVNETA_GMAC_FORCE_LINK_PASS |
3888 MVNETA_GMAC_CONFIG_MII_SPEED)) |
3889 MVNETA_GMAC_INBAND_AN_ENABLE |
3890 MVNETA_GMAC_CONFIG_GMII_SPEED |
3891 /* The MAC only supports FD mode */
3892 MVNETA_GMAC_CONFIG_FULL_DUPLEX;
3894 if (state->pause & MLO_PAUSE_AN && state->an_enabled)
3895 new_an |= MVNETA_GMAC_AN_FLOW_CTRL_EN;
3898 /* Armada 370 documentation says we can only change the port mode
3899 * and in-band enable when the link is down, so force it down
3900 * while making these changes. We also do this for GMAC_CTRL2 */
3901 if ((new_ctrl0 ^ gmac_ctrl0) & MVNETA_GMAC0_PORT_1000BASE_X ||
3902 (new_ctrl2 ^ gmac_ctrl2) & MVNETA_GMAC2_INBAND_AN_ENABLE ||
3903 (new_an ^ gmac_an) & MVNETA_GMAC_INBAND_AN_ENABLE) {
3904 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
3905 (gmac_an & ~MVNETA_GMAC_FORCE_LINK_PASS) |
3906 MVNETA_GMAC_FORCE_LINK_DOWN);
3910 /* When at 2.5G, the link partner can send frames with shortened
3913 if (state->speed == SPEED_2500)
3914 new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE;
3916 if (pp->comphy && pp->phy_interface != state->interface &&
3917 (state->interface == PHY_INTERFACE_MODE_SGMII ||
3918 state->interface == PHY_INTERFACE_MODE_1000BASEX ||
3919 state->interface == PHY_INTERFACE_MODE_2500BASEX)) {
3920 pp->phy_interface = state->interface;
3922 WARN_ON(phy_power_off(pp->comphy));
3923 WARN_ON(mvneta_comphy_init(pp));
3926 if (new_ctrl0 != gmac_ctrl0)
3927 mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0);
3928 if (new_ctrl2 != gmac_ctrl2)
3929 mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2);
3930 if (new_ctrl4 != gmac_ctrl4)
3931 mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4);
3932 if (new_clk != gmac_clk)
3933 mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk);
3934 if (new_an != gmac_an)
3935 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an);
3937 if (gmac_ctrl2 & MVNETA_GMAC2_PORT_RESET) {
3938 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
3939 MVNETA_GMAC2_PORT_RESET) != 0)
3944 static void mvneta_set_eee(struct mvneta_port *pp, bool enable)
3948 lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1);
3950 lpi_ctl1 |= MVNETA_LPI_REQUEST_ENABLE;
3952 lpi_ctl1 &= ~MVNETA_LPI_REQUEST_ENABLE;
3953 mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1);
3956 static void mvneta_mac_link_down(struct phylink_config *config,
3957 unsigned int mode, phy_interface_t interface)
3959 struct net_device *ndev = to_net_dev(config->dev);
3960 struct mvneta_port *pp = netdev_priv(ndev);
3963 mvneta_port_down(pp);
3965 if (!phylink_autoneg_inband(mode)) {
3966 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3967 val &= ~MVNETA_GMAC_FORCE_LINK_PASS;
3968 val |= MVNETA_GMAC_FORCE_LINK_DOWN;
3969 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
3972 pp->eee_active = false;
3973 mvneta_set_eee(pp, false);
3976 static void mvneta_mac_link_up(struct phylink_config *config,
3977 struct phy_device *phy,
3978 unsigned int mode, phy_interface_t interface,
3979 int speed, int duplex,
3980 bool tx_pause, bool rx_pause)
3982 struct net_device *ndev = to_net_dev(config->dev);
3983 struct mvneta_port *pp = netdev_priv(ndev);
3986 if (!phylink_autoneg_inband(mode)) {
3987 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3988 val &= ~(MVNETA_GMAC_FORCE_LINK_DOWN |
3989 MVNETA_GMAC_CONFIG_MII_SPEED |
3990 MVNETA_GMAC_CONFIG_GMII_SPEED |
3991 MVNETA_GMAC_CONFIG_FLOW_CTRL |
3992 MVNETA_GMAC_CONFIG_FULL_DUPLEX);
3993 val |= MVNETA_GMAC_FORCE_LINK_PASS;
3995 if (speed == SPEED_1000 || speed == SPEED_2500)
3996 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
3997 else if (speed == SPEED_100)
3998 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
4000 if (duplex == DUPLEX_FULL)
4001 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
4003 if (tx_pause || rx_pause)
4004 val |= MVNETA_GMAC_CONFIG_FLOW_CTRL;
4006 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
4008 /* When inband doesn't cover flow control or flow control is
4009 * disabled, we need to manually configure it. This bit will
4010 * only have effect if MVNETA_GMAC_AN_FLOW_CTRL_EN is unset.
4012 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
4013 val &= ~MVNETA_GMAC_CONFIG_FLOW_CTRL;
4015 if (tx_pause || rx_pause)
4016 val |= MVNETA_GMAC_CONFIG_FLOW_CTRL;
4018 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
4023 if (phy && pp->eee_enabled) {
4024 pp->eee_active = phy_init_eee(phy, 0) >= 0;
4025 mvneta_set_eee(pp, pp->eee_active && pp->tx_lpi_enabled);
4029 static const struct phylink_mac_ops mvneta_phylink_ops = {
4030 .validate = mvneta_validate,
4031 .mac_pcs_get_state = mvneta_mac_pcs_get_state,
4032 .mac_an_restart = mvneta_mac_an_restart,
4033 .mac_config = mvneta_mac_config,
4034 .mac_link_down = mvneta_mac_link_down,
4035 .mac_link_up = mvneta_mac_link_up,
4038 static int mvneta_mdio_probe(struct mvneta_port *pp)
4040 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL };
4041 int err = phylink_of_phy_connect(pp->phylink, pp->dn, 0);
4044 netdev_err(pp->dev, "could not attach PHY: %d\n", err);
4046 phylink_ethtool_get_wol(pp->phylink, &wol);
4047 device_set_wakeup_capable(&pp->dev->dev, !!wol.supported);
4052 static void mvneta_mdio_remove(struct mvneta_port *pp)
4054 phylink_disconnect_phy(pp->phylink);
4057 /* Electing a CPU must be done in an atomic way: it should be done
4058 * after or before the removal/insertion of a CPU and this function is
4061 static void mvneta_percpu_elect(struct mvneta_port *pp)
4063 int elected_cpu = 0, max_cpu, cpu, i = 0;
4065 /* Use the cpu associated to the rxq when it is online, in all
4066 * the other cases, use the cpu 0 which can't be offline.
4068 if (cpu_online(pp->rxq_def))
4069 elected_cpu = pp->rxq_def;
4071 max_cpu = num_present_cpus();
4073 for_each_online_cpu(cpu) {
4074 int rxq_map = 0, txq_map = 0;
4077 for (rxq = 0; rxq < rxq_number; rxq++)
4078 if ((rxq % max_cpu) == cpu)
4079 rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
4081 if (cpu == elected_cpu)
4082 /* Map the default receive queue queue to the
4085 rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def);
4087 /* We update the TX queue map only if we have one
4088 * queue. In this case we associate the TX queue to
4089 * the CPU bound to the default RX queue
4091 if (txq_number == 1)
4092 txq_map = (cpu == elected_cpu) ?
4093 MVNETA_CPU_TXQ_ACCESS(1) : 0;
4095 txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) &
4096 MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
4098 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
4100 /* Update the interrupt mask on each CPU according the
4103 smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt,
4110 static int mvneta_cpu_online(unsigned int cpu, struct hlist_node *node)
4113 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
4115 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
4118 spin_lock(&pp->lock);
4120 * Configuring the driver for a new CPU while the driver is
4121 * stopping is racy, so just avoid it.
4123 if (pp->is_stopped) {
4124 spin_unlock(&pp->lock);
4127 netif_tx_stop_all_queues(pp->dev);
4130 * We have to synchronise on tha napi of each CPU except the one
4131 * just being woken up
4133 for_each_online_cpu(other_cpu) {
4134 if (other_cpu != cpu) {
4135 struct mvneta_pcpu_port *other_port =
4136 per_cpu_ptr(pp->ports, other_cpu);
4138 napi_synchronize(&other_port->napi);
4142 /* Mask all ethernet port interrupts */
4143 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
4144 napi_enable(&port->napi);
4147 * Enable per-CPU interrupts on the CPU that is
4150 mvneta_percpu_enable(pp);
4153 * Enable per-CPU interrupt on the one CPU we care
4156 mvneta_percpu_elect(pp);
4158 /* Unmask all ethernet port interrupts */
4159 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
4160 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
4161 MVNETA_CAUSE_PHY_STATUS_CHANGE |
4162 MVNETA_CAUSE_LINK_CHANGE);
4163 netif_tx_start_all_queues(pp->dev);
4164 spin_unlock(&pp->lock);
4168 static int mvneta_cpu_down_prepare(unsigned int cpu, struct hlist_node *node)
4170 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
4172 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
4175 * Thanks to this lock we are sure that any pending cpu election is
4178 spin_lock(&pp->lock);
4179 /* Mask all ethernet port interrupts */
4180 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
4181 spin_unlock(&pp->lock);
4183 napi_synchronize(&port->napi);
4184 napi_disable(&port->napi);
4185 /* Disable per-CPU interrupts on the CPU that is brought down. */
4186 mvneta_percpu_disable(pp);
4190 static int mvneta_cpu_dead(unsigned int cpu, struct hlist_node *node)
4192 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
4195 /* Check if a new CPU must be elected now this on is down */
4196 spin_lock(&pp->lock);
4197 mvneta_percpu_elect(pp);
4198 spin_unlock(&pp->lock);
4199 /* Unmask all ethernet port interrupts */
4200 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
4201 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
4202 MVNETA_CAUSE_PHY_STATUS_CHANGE |
4203 MVNETA_CAUSE_LINK_CHANGE);
4204 netif_tx_start_all_queues(pp->dev);
4208 static int mvneta_open(struct net_device *dev)
4210 struct mvneta_port *pp = netdev_priv(dev);
4213 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
4215 ret = mvneta_setup_rxqs(pp);
4219 ret = mvneta_setup_txqs(pp);
4221 goto err_cleanup_rxqs;
4223 /* Connect to port interrupt line */
4224 if (pp->neta_armada3700)
4225 ret = request_irq(pp->dev->irq, mvneta_isr, 0,
4228 ret = request_percpu_irq(pp->dev->irq, mvneta_percpu_isr,
4229 dev->name, pp->ports);
4231 netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq);
4232 goto err_cleanup_txqs;
4235 if (!pp->neta_armada3700) {
4236 /* Enable per-CPU interrupt on all the CPU to handle our RX
4239 on_each_cpu(mvneta_percpu_enable, pp, true);
4241 pp->is_stopped = false;
4242 /* Register a CPU notifier to handle the case where our CPU
4243 * might be taken offline.
4245 ret = cpuhp_state_add_instance_nocalls(online_hpstate,
4250 ret = cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
4253 goto err_free_online_hp;
4256 ret = mvneta_mdio_probe(pp);
4258 netdev_err(dev, "cannot probe MDIO bus\n");
4259 goto err_free_dead_hp;
4262 mvneta_start_dev(pp);
4267 if (!pp->neta_armada3700)
4268 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
4271 if (!pp->neta_armada3700)
4272 cpuhp_state_remove_instance_nocalls(online_hpstate,
4275 if (pp->neta_armada3700) {
4276 free_irq(pp->dev->irq, pp);
4278 on_each_cpu(mvneta_percpu_disable, pp, true);
4279 free_percpu_irq(pp->dev->irq, pp->ports);
4282 mvneta_cleanup_txqs(pp);
4284 mvneta_cleanup_rxqs(pp);
4288 /* Stop the port, free port interrupt line */
4289 static int mvneta_stop(struct net_device *dev)
4291 struct mvneta_port *pp = netdev_priv(dev);
4293 if (!pp->neta_armada3700) {
4294 /* Inform that we are stopping so we don't want to setup the
4295 * driver for new CPUs in the notifiers. The code of the
4296 * notifier for CPU online is protected by the same spinlock,
4297 * so when we get the lock, the notifer work is done.
4299 spin_lock(&pp->lock);
4300 pp->is_stopped = true;
4301 spin_unlock(&pp->lock);
4303 mvneta_stop_dev(pp);
4304 mvneta_mdio_remove(pp);
4306 cpuhp_state_remove_instance_nocalls(online_hpstate,
4308 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
4310 on_each_cpu(mvneta_percpu_disable, pp, true);
4311 free_percpu_irq(dev->irq, pp->ports);
4313 mvneta_stop_dev(pp);
4314 mvneta_mdio_remove(pp);
4315 free_irq(dev->irq, pp);
4318 mvneta_cleanup_rxqs(pp);
4319 mvneta_cleanup_txqs(pp);
4324 static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4326 struct mvneta_port *pp = netdev_priv(dev);
4328 return phylink_mii_ioctl(pp->phylink, ifr, cmd);
4331 static int mvneta_xdp_setup(struct net_device *dev, struct bpf_prog *prog,
4332 struct netlink_ext_ack *extack)
4334 bool need_update, running = netif_running(dev);
4335 struct mvneta_port *pp = netdev_priv(dev);
4336 struct bpf_prog *old_prog;
4338 if (prog && dev->mtu > MVNETA_MAX_RX_BUF_SIZE) {
4339 NL_SET_ERR_MSG_MOD(extack, "Jumbo frames not supported on XDP");
4344 NL_SET_ERR_MSG_MOD(extack,
4345 "Hardware Buffer Management not supported on XDP");
4349 need_update = !!pp->xdp_prog != !!prog;
4350 if (running && need_update)
4353 old_prog = xchg(&pp->xdp_prog, prog);
4355 bpf_prog_put(old_prog);
4357 if (running && need_update)
4358 return mvneta_open(dev);
4363 static int mvneta_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4365 struct mvneta_port *pp = netdev_priv(dev);
4367 switch (xdp->command) {
4368 case XDP_SETUP_PROG:
4369 return mvneta_xdp_setup(dev, xdp->prog, xdp->extack);
4370 case XDP_QUERY_PROG:
4371 xdp->prog_id = pp->xdp_prog ? pp->xdp_prog->aux->id : 0;
4378 /* Ethtool methods */
4380 /* Set link ksettings (phy address, speed) for ethtools */
4382 mvneta_ethtool_set_link_ksettings(struct net_device *ndev,
4383 const struct ethtool_link_ksettings *cmd)
4385 struct mvneta_port *pp = netdev_priv(ndev);
4387 return phylink_ethtool_ksettings_set(pp->phylink, cmd);
4390 /* Get link ksettings for ethtools */
4392 mvneta_ethtool_get_link_ksettings(struct net_device *ndev,
4393 struct ethtool_link_ksettings *cmd)
4395 struct mvneta_port *pp = netdev_priv(ndev);
4397 return phylink_ethtool_ksettings_get(pp->phylink, cmd);
4400 static int mvneta_ethtool_nway_reset(struct net_device *dev)
4402 struct mvneta_port *pp = netdev_priv(dev);
4404 return phylink_ethtool_nway_reset(pp->phylink);
4407 /* Set interrupt coalescing for ethtools */
4408 static int mvneta_ethtool_set_coalesce(struct net_device *dev,
4409 struct ethtool_coalesce *c)
4411 struct mvneta_port *pp = netdev_priv(dev);
4414 for (queue = 0; queue < rxq_number; queue++) {
4415 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
4416 rxq->time_coal = c->rx_coalesce_usecs;
4417 rxq->pkts_coal = c->rx_max_coalesced_frames;
4418 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
4419 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
4422 for (queue = 0; queue < txq_number; queue++) {
4423 struct mvneta_tx_queue *txq = &pp->txqs[queue];
4424 txq->done_pkts_coal = c->tx_max_coalesced_frames;
4425 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
4431 /* get coalescing for ethtools */
4432 static int mvneta_ethtool_get_coalesce(struct net_device *dev,
4433 struct ethtool_coalesce *c)
4435 struct mvneta_port *pp = netdev_priv(dev);
4437 c->rx_coalesce_usecs = pp->rxqs[0].time_coal;
4438 c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal;
4440 c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal;
4445 static void mvneta_ethtool_get_drvinfo(struct net_device *dev,
4446 struct ethtool_drvinfo *drvinfo)
4448 strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME,
4449 sizeof(drvinfo->driver));
4450 strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION,
4451 sizeof(drvinfo->version));
4452 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
4453 sizeof(drvinfo->bus_info));
4457 static void mvneta_ethtool_get_ringparam(struct net_device *netdev,
4458 struct ethtool_ringparam *ring)
4460 struct mvneta_port *pp = netdev_priv(netdev);
4462 ring->rx_max_pending = MVNETA_MAX_RXD;
4463 ring->tx_max_pending = MVNETA_MAX_TXD;
4464 ring->rx_pending = pp->rx_ring_size;
4465 ring->tx_pending = pp->tx_ring_size;
4468 static int mvneta_ethtool_set_ringparam(struct net_device *dev,
4469 struct ethtool_ringparam *ring)
4471 struct mvneta_port *pp = netdev_priv(dev);
4473 if ((ring->rx_pending == 0) || (ring->tx_pending == 0))
4475 pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ?
4476 ring->rx_pending : MVNETA_MAX_RXD;
4478 pp->tx_ring_size = clamp_t(u16, ring->tx_pending,
4479 MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD);
4480 if (pp->tx_ring_size != ring->tx_pending)
4481 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
4482 pp->tx_ring_size, ring->tx_pending);
4484 if (netif_running(dev)) {
4486 if (mvneta_open(dev)) {
4488 "error on opening device after ring param change\n");
4496 static void mvneta_ethtool_get_pauseparam(struct net_device *dev,
4497 struct ethtool_pauseparam *pause)
4499 struct mvneta_port *pp = netdev_priv(dev);
4501 phylink_ethtool_get_pauseparam(pp->phylink, pause);
4504 static int mvneta_ethtool_set_pauseparam(struct net_device *dev,
4505 struct ethtool_pauseparam *pause)
4507 struct mvneta_port *pp = netdev_priv(dev);
4509 return phylink_ethtool_set_pauseparam(pp->phylink, pause);
4512 static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset,
4515 if (sset == ETH_SS_STATS) {
4518 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
4519 memcpy(data + i * ETH_GSTRING_LEN,
4520 mvneta_statistics[i].name, ETH_GSTRING_LEN);
4525 mvneta_ethtool_update_pcpu_stats(struct mvneta_port *pp,
4526 struct mvneta_ethtool_stats *es)
4531 for_each_possible_cpu(cpu) {
4532 struct mvneta_pcpu_stats *stats;
4533 u64 skb_alloc_error;
4543 stats = per_cpu_ptr(pp->stats, cpu);
4545 start = u64_stats_fetch_begin_irq(&stats->syncp);
4546 skb_alloc_error = stats->es.skb_alloc_error;
4547 refill_error = stats->es.refill_error;
4548 xdp_redirect = stats->es.ps.xdp_redirect;
4549 xdp_pass = stats->es.ps.xdp_pass;
4550 xdp_drop = stats->es.ps.xdp_drop;
4551 xdp_xmit = stats->es.ps.xdp_xmit;
4552 xdp_xmit_err = stats->es.ps.xdp_xmit_err;
4553 xdp_tx = stats->es.ps.xdp_tx;
4554 xdp_tx_err = stats->es.ps.xdp_tx_err;
4555 } while (u64_stats_fetch_retry_irq(&stats->syncp, start));
4557 es->skb_alloc_error += skb_alloc_error;
4558 es->refill_error += refill_error;
4559 es->ps.xdp_redirect += xdp_redirect;
4560 es->ps.xdp_pass += xdp_pass;
4561 es->ps.xdp_drop += xdp_drop;
4562 es->ps.xdp_xmit += xdp_xmit;
4563 es->ps.xdp_xmit_err += xdp_xmit_err;
4564 es->ps.xdp_tx += xdp_tx;
4565 es->ps.xdp_tx_err += xdp_tx_err;
4569 static void mvneta_ethtool_update_stats(struct mvneta_port *pp)
4571 struct mvneta_ethtool_stats stats = {};
4572 const struct mvneta_statistic *s;
4573 void __iomem *base = pp->base;
4578 mvneta_ethtool_update_pcpu_stats(pp, &stats);
4579 for (i = 0, s = mvneta_statistics;
4580 s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics);
4584 val = readl_relaxed(base + s->offset);
4585 pp->ethtool_stats[i] += val;
4588 /* Docs say to read low 32-bit then high */
4589 low = readl_relaxed(base + s->offset);
4590 high = readl_relaxed(base + s->offset + 4);
4591 val = (u64)high << 32 | low;
4592 pp->ethtool_stats[i] += val;
4595 switch (s->offset) {
4596 case ETHTOOL_STAT_EEE_WAKEUP:
4597 val = phylink_get_eee_err(pp->phylink);
4598 pp->ethtool_stats[i] += val;
4600 case ETHTOOL_STAT_SKB_ALLOC_ERR:
4601 pp->ethtool_stats[i] = stats.skb_alloc_error;
4603 case ETHTOOL_STAT_REFILL_ERR:
4604 pp->ethtool_stats[i] = stats.refill_error;
4606 case ETHTOOL_XDP_REDIRECT:
4607 pp->ethtool_stats[i] = stats.ps.xdp_redirect;
4609 case ETHTOOL_XDP_PASS:
4610 pp->ethtool_stats[i] = stats.ps.xdp_pass;
4612 case ETHTOOL_XDP_DROP:
4613 pp->ethtool_stats[i] = stats.ps.xdp_drop;
4615 case ETHTOOL_XDP_TX:
4616 pp->ethtool_stats[i] = stats.ps.xdp_tx;
4618 case ETHTOOL_XDP_TX_ERR:
4619 pp->ethtool_stats[i] = stats.ps.xdp_tx_err;
4621 case ETHTOOL_XDP_XMIT:
4622 pp->ethtool_stats[i] = stats.ps.xdp_xmit;
4624 case ETHTOOL_XDP_XMIT_ERR:
4625 pp->ethtool_stats[i] = stats.ps.xdp_xmit_err;
4633 static void mvneta_ethtool_get_stats(struct net_device *dev,
4634 struct ethtool_stats *stats, u64 *data)
4636 struct mvneta_port *pp = netdev_priv(dev);
4639 mvneta_ethtool_update_stats(pp);
4641 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
4642 *data++ = pp->ethtool_stats[i];
4645 static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset)
4647 if (sset == ETH_SS_STATS)
4648 return ARRAY_SIZE(mvneta_statistics);
4652 static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev)
4654 return MVNETA_RSS_LU_TABLE_SIZE;
4657 static int mvneta_ethtool_get_rxnfc(struct net_device *dev,
4658 struct ethtool_rxnfc *info,
4659 u32 *rules __always_unused)
4661 switch (info->cmd) {
4662 case ETHTOOL_GRXRINGS:
4663 info->data = rxq_number;
4672 static int mvneta_config_rss(struct mvneta_port *pp)
4677 netif_tx_stop_all_queues(pp->dev);
4679 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
4681 if (!pp->neta_armada3700) {
4682 /* We have to synchronise on the napi of each CPU */
4683 for_each_online_cpu(cpu) {
4684 struct mvneta_pcpu_port *pcpu_port =
4685 per_cpu_ptr(pp->ports, cpu);
4687 napi_synchronize(&pcpu_port->napi);
4688 napi_disable(&pcpu_port->napi);
4691 napi_synchronize(&pp->napi);
4692 napi_disable(&pp->napi);
4695 pp->rxq_def = pp->indir[0];
4697 /* Update unicast mapping */
4698 mvneta_set_rx_mode(pp->dev);
4700 /* Update val of portCfg register accordingly with all RxQueue types */
4701 val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def);
4702 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
4704 /* Update the elected CPU matching the new rxq_def */
4705 spin_lock(&pp->lock);
4706 mvneta_percpu_elect(pp);
4707 spin_unlock(&pp->lock);
4709 if (!pp->neta_armada3700) {
4710 /* We have to synchronise on the napi of each CPU */
4711 for_each_online_cpu(cpu) {
4712 struct mvneta_pcpu_port *pcpu_port =
4713 per_cpu_ptr(pp->ports, cpu);
4715 napi_enable(&pcpu_port->napi);
4718 napi_enable(&pp->napi);
4721 netif_tx_start_all_queues(pp->dev);
4726 static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,
4727 const u8 *key, const u8 hfunc)
4729 struct mvneta_port *pp = netdev_priv(dev);
4731 /* Current code for Armada 3700 doesn't support RSS features yet */
4732 if (pp->neta_armada3700)
4735 /* We require at least one supported parameter to be changed
4736 * and no change in any of the unsupported parameters
4739 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
4745 memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE);
4747 return mvneta_config_rss(pp);
4750 static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
4753 struct mvneta_port *pp = netdev_priv(dev);
4755 /* Current code for Armada 3700 doesn't support RSS features yet */
4756 if (pp->neta_armada3700)
4760 *hfunc = ETH_RSS_HASH_TOP;
4765 memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE);
4770 static void mvneta_ethtool_get_wol(struct net_device *dev,
4771 struct ethtool_wolinfo *wol)
4773 struct mvneta_port *pp = netdev_priv(dev);
4775 phylink_ethtool_get_wol(pp->phylink, wol);
4778 static int mvneta_ethtool_set_wol(struct net_device *dev,
4779 struct ethtool_wolinfo *wol)
4781 struct mvneta_port *pp = netdev_priv(dev);
4784 ret = phylink_ethtool_set_wol(pp->phylink, wol);
4786 device_set_wakeup_enable(&dev->dev, !!wol->wolopts);
4791 static int mvneta_ethtool_get_eee(struct net_device *dev,
4792 struct ethtool_eee *eee)
4794 struct mvneta_port *pp = netdev_priv(dev);
4797 lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0);
4799 eee->eee_enabled = pp->eee_enabled;
4800 eee->eee_active = pp->eee_active;
4801 eee->tx_lpi_enabled = pp->tx_lpi_enabled;
4802 eee->tx_lpi_timer = (lpi_ctl0) >> 8; // * scale;
4804 return phylink_ethtool_get_eee(pp->phylink, eee);
4807 static int mvneta_ethtool_set_eee(struct net_device *dev,
4808 struct ethtool_eee *eee)
4810 struct mvneta_port *pp = netdev_priv(dev);
4813 /* The Armada 37x documents do not give limits for this other than
4814 * it being an 8-bit register. */
4815 if (eee->tx_lpi_enabled && eee->tx_lpi_timer > 255)
4818 lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0);
4819 lpi_ctl0 &= ~(0xff << 8);
4820 lpi_ctl0 |= eee->tx_lpi_timer << 8;
4821 mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0);
4823 pp->eee_enabled = eee->eee_enabled;
4824 pp->tx_lpi_enabled = eee->tx_lpi_enabled;
4826 mvneta_set_eee(pp, eee->tx_lpi_enabled && eee->eee_enabled);
4828 return phylink_ethtool_set_eee(pp->phylink, eee);
4831 static const struct net_device_ops mvneta_netdev_ops = {
4832 .ndo_open = mvneta_open,
4833 .ndo_stop = mvneta_stop,
4834 .ndo_start_xmit = mvneta_tx,
4835 .ndo_set_rx_mode = mvneta_set_rx_mode,
4836 .ndo_set_mac_address = mvneta_set_mac_addr,
4837 .ndo_change_mtu = mvneta_change_mtu,
4838 .ndo_fix_features = mvneta_fix_features,
4839 .ndo_get_stats64 = mvneta_get_stats64,
4840 .ndo_do_ioctl = mvneta_ioctl,
4841 .ndo_bpf = mvneta_xdp,
4842 .ndo_xdp_xmit = mvneta_xdp_xmit,
4845 static const struct ethtool_ops mvneta_eth_tool_ops = {
4846 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS |
4847 ETHTOOL_COALESCE_MAX_FRAMES,
4848 .nway_reset = mvneta_ethtool_nway_reset,
4849 .get_link = ethtool_op_get_link,
4850 .set_coalesce = mvneta_ethtool_set_coalesce,
4851 .get_coalesce = mvneta_ethtool_get_coalesce,
4852 .get_drvinfo = mvneta_ethtool_get_drvinfo,
4853 .get_ringparam = mvneta_ethtool_get_ringparam,
4854 .set_ringparam = mvneta_ethtool_set_ringparam,
4855 .get_pauseparam = mvneta_ethtool_get_pauseparam,
4856 .set_pauseparam = mvneta_ethtool_set_pauseparam,
4857 .get_strings = mvneta_ethtool_get_strings,
4858 .get_ethtool_stats = mvneta_ethtool_get_stats,
4859 .get_sset_count = mvneta_ethtool_get_sset_count,
4860 .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size,
4861 .get_rxnfc = mvneta_ethtool_get_rxnfc,
4862 .get_rxfh = mvneta_ethtool_get_rxfh,
4863 .set_rxfh = mvneta_ethtool_set_rxfh,
4864 .get_link_ksettings = mvneta_ethtool_get_link_ksettings,
4865 .set_link_ksettings = mvneta_ethtool_set_link_ksettings,
4866 .get_wol = mvneta_ethtool_get_wol,
4867 .set_wol = mvneta_ethtool_set_wol,
4868 .get_eee = mvneta_ethtool_get_eee,
4869 .set_eee = mvneta_ethtool_set_eee,
4873 static int mvneta_init(struct device *dev, struct mvneta_port *pp)
4878 mvneta_port_disable(pp);
4880 /* Set port default values */
4881 mvneta_defaults_set(pp);
4883 pp->txqs = devm_kcalloc(dev, txq_number, sizeof(*pp->txqs), GFP_KERNEL);
4887 /* Initialize TX descriptor rings */
4888 for (queue = 0; queue < txq_number; queue++) {
4889 struct mvneta_tx_queue *txq = &pp->txqs[queue];
4891 txq->size = pp->tx_ring_size;
4892 txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS;
4895 pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*pp->rxqs), GFP_KERNEL);
4899 /* Create Rx descriptor rings */
4900 for (queue = 0; queue < rxq_number; queue++) {
4901 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
4903 rxq->size = pp->rx_ring_size;
4904 rxq->pkts_coal = MVNETA_RX_COAL_PKTS;
4905 rxq->time_coal = MVNETA_RX_COAL_USEC;
4907 = devm_kmalloc_array(pp->dev->dev.parent,
4909 sizeof(*rxq->buf_virt_addr),
4911 if (!rxq->buf_virt_addr)
4918 /* platform glue : initialize decoding windows */
4919 static void mvneta_conf_mbus_windows(struct mvneta_port *pp,
4920 const struct mbus_dram_target_info *dram)
4926 for (i = 0; i < 6; i++) {
4927 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
4928 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
4931 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
4938 for (i = 0; i < dram->num_cs; i++) {
4939 const struct mbus_dram_window *cs = dram->cs + i;
4941 mvreg_write(pp, MVNETA_WIN_BASE(i),
4942 (cs->base & 0xffff0000) |
4943 (cs->mbus_attr << 8) |
4944 dram->mbus_dram_target_id);
4946 mvreg_write(pp, MVNETA_WIN_SIZE(i),
4947 (cs->size - 1) & 0xffff0000);
4949 win_enable &= ~(1 << i);
4950 win_protect |= 3 << (2 * i);
4953 /* For Armada3700 open default 4GB Mbus window, leaving
4954 * arbitration of target/attribute to a different layer
4957 mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000);
4958 win_enable &= ~BIT(0);
4962 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
4963 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
4966 /* Power up the port */
4967 static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
4969 /* MAC Cause register should be cleared */
4970 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
4972 if (phy_mode == PHY_INTERFACE_MODE_QSGMII)
4973 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
4974 else if (phy_mode == PHY_INTERFACE_MODE_SGMII ||
4975 phy_interface_mode_is_8023z(phy_mode))
4976 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
4977 else if (!phy_interface_mode_is_rgmii(phy_mode))
4983 /* Device initialization routine */
4984 static int mvneta_probe(struct platform_device *pdev)
4986 struct device_node *dn = pdev->dev.of_node;
4987 struct device_node *bm_node;
4988 struct mvneta_port *pp;
4989 struct net_device *dev;
4990 struct phylink *phylink;
4992 const char *dt_mac_addr;
4993 char hw_mac_addr[ETH_ALEN];
4994 phy_interface_t phy_mode;
4995 const char *mac_from;
5000 dev = devm_alloc_etherdev_mqs(&pdev->dev, sizeof(struct mvneta_port),
5001 txq_number, rxq_number);
5005 dev->irq = irq_of_parse_and_map(dn, 0);
5009 err = of_get_phy_mode(dn, &phy_mode);
5011 dev_err(&pdev->dev, "incorrect phy-mode\n");
5015 comphy = devm_of_phy_get(&pdev->dev, dn, NULL);
5016 if (comphy == ERR_PTR(-EPROBE_DEFER)) {
5017 err = -EPROBE_DEFER;
5019 } else if (IS_ERR(comphy)) {
5023 pp = netdev_priv(dev);
5024 spin_lock_init(&pp->lock);
5026 pp->phylink_config.dev = &dev->dev;
5027 pp->phylink_config.type = PHYLINK_NETDEV;
5029 phylink = phylink_create(&pp->phylink_config, pdev->dev.fwnode,
5030 phy_mode, &mvneta_phylink_ops);
5031 if (IS_ERR(phylink)) {
5032 err = PTR_ERR(phylink);
5036 dev->tx_queue_len = MVNETA_MAX_TXD;
5037 dev->watchdog_timeo = 5 * HZ;
5038 dev->netdev_ops = &mvneta_netdev_ops;
5040 dev->ethtool_ops = &mvneta_eth_tool_ops;
5042 pp->phylink = phylink;
5043 pp->comphy = comphy;
5044 pp->phy_interface = phy_mode;
5047 pp->rxq_def = rxq_def;
5048 pp->indir[0] = rxq_def;
5050 /* Get special SoC configurations */
5051 if (of_device_is_compatible(dn, "marvell,armada-3700-neta"))
5052 pp->neta_armada3700 = true;
5054 pp->clk = devm_clk_get(&pdev->dev, "core");
5055 if (IS_ERR(pp->clk))
5056 pp->clk = devm_clk_get(&pdev->dev, NULL);
5057 if (IS_ERR(pp->clk)) {
5058 err = PTR_ERR(pp->clk);
5059 goto err_free_phylink;
5062 clk_prepare_enable(pp->clk);
5064 pp->clk_bus = devm_clk_get(&pdev->dev, "bus");
5065 if (!IS_ERR(pp->clk_bus))
5066 clk_prepare_enable(pp->clk_bus);
5068 pp->base = devm_platform_ioremap_resource(pdev, 0);
5069 if (IS_ERR(pp->base)) {
5070 err = PTR_ERR(pp->base);
5074 /* Alloc per-cpu port structure */
5075 pp->ports = alloc_percpu(struct mvneta_pcpu_port);
5081 /* Alloc per-cpu stats */
5082 pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats);
5085 goto err_free_ports;
5088 dt_mac_addr = of_get_mac_address(dn);
5089 if (!IS_ERR(dt_mac_addr)) {
5090 mac_from = "device tree";
5091 ether_addr_copy(dev->dev_addr, dt_mac_addr);
5093 mvneta_get_mac_addr(pp, hw_mac_addr);
5094 if (is_valid_ether_addr(hw_mac_addr)) {
5095 mac_from = "hardware";
5096 memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN);
5098 mac_from = "random";
5099 eth_hw_addr_random(dev);
5103 if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) {
5104 if (tx_csum_limit < 0 ||
5105 tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) {
5106 tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE;
5107 dev_info(&pdev->dev,
5108 "Wrong TX csum limit in DT, set to %dB\n",
5109 MVNETA_TX_CSUM_DEF_SIZE);
5111 } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) {
5112 tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE;
5114 tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE;
5117 pp->tx_csum_limit = tx_csum_limit;
5119 pp->dram_target_info = mv_mbus_dram_info();
5120 /* Armada3700 requires setting default configuration of Mbus
5121 * windows, however without using filled mbus_dram_target_info
5124 if (pp->dram_target_info || pp->neta_armada3700)
5125 mvneta_conf_mbus_windows(pp, pp->dram_target_info);
5127 pp->tx_ring_size = MVNETA_MAX_TXD;
5128 pp->rx_ring_size = MVNETA_MAX_RXD;
5131 SET_NETDEV_DEV(dev, &pdev->dev);
5133 pp->id = global_port_id++;
5135 /* Obtain access to BM resources if enabled and already initialized */
5136 bm_node = of_parse_phandle(dn, "buffer-manager", 0);
5138 pp->bm_priv = mvneta_bm_get(bm_node);
5140 err = mvneta_bm_port_init(pdev, pp);
5142 dev_info(&pdev->dev,
5143 "use SW buffer management\n");
5144 mvneta_bm_put(pp->bm_priv);
5148 /* Set RX packet offset correction for platforms, whose
5149 * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit
5150 * platforms and 0B for 32-bit ones.
5152 pp->rx_offset_correction = max(0,
5154 MVNETA_RX_PKT_OFFSET_CORRECTION);
5156 of_node_put(bm_node);
5158 /* sw buffer management */
5160 pp->rx_offset_correction = MVNETA_SKB_HEADROOM;
5162 err = mvneta_init(&pdev->dev, pp);
5166 err = mvneta_port_power_up(pp, phy_mode);
5168 dev_err(&pdev->dev, "can't power up port\n");
5172 /* Armada3700 network controller does not support per-cpu
5173 * operation, so only single NAPI should be initialized.
5175 if (pp->neta_armada3700) {
5176 netif_napi_add(dev, &pp->napi, mvneta_poll, NAPI_POLL_WEIGHT);
5178 for_each_present_cpu(cpu) {
5179 struct mvneta_pcpu_port *port =
5180 per_cpu_ptr(pp->ports, cpu);
5182 netif_napi_add(dev, &port->napi, mvneta_poll,
5188 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
5189 NETIF_F_TSO | NETIF_F_RXCSUM;
5190 dev->hw_features |= dev->features;
5191 dev->vlan_features |= dev->features;
5192 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5193 dev->gso_max_segs = MVNETA_MAX_TSO_SEGS;
5195 /* MTU range: 68 - 9676 */
5196 dev->min_mtu = ETH_MIN_MTU;
5197 /* 9676 == 9700 - 20 and rounding to 8 */
5198 dev->max_mtu = 9676;
5200 err = register_netdev(dev);
5202 dev_err(&pdev->dev, "failed to register\n");
5206 netdev_info(dev, "Using %s mac address %pM\n", mac_from,
5209 platform_set_drvdata(pdev, pp->dev);
5215 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
5216 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short,
5218 mvneta_bm_put(pp->bm_priv);
5220 free_percpu(pp->stats);
5222 free_percpu(pp->ports);
5224 clk_disable_unprepare(pp->clk_bus);
5225 clk_disable_unprepare(pp->clk);
5228 phylink_destroy(pp->phylink);
5230 irq_dispose_mapping(dev->irq);
5234 /* Device removal routine */
5235 static int mvneta_remove(struct platform_device *pdev)
5237 struct net_device *dev = platform_get_drvdata(pdev);
5238 struct mvneta_port *pp = netdev_priv(dev);
5240 unregister_netdev(dev);
5241 clk_disable_unprepare(pp->clk_bus);
5242 clk_disable_unprepare(pp->clk);
5243 free_percpu(pp->ports);
5244 free_percpu(pp->stats);
5245 irq_dispose_mapping(dev->irq);
5246 phylink_destroy(pp->phylink);
5249 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
5250 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short,
5252 mvneta_bm_put(pp->bm_priv);
5258 #ifdef CONFIG_PM_SLEEP
5259 static int mvneta_suspend(struct device *device)
5262 struct net_device *dev = dev_get_drvdata(device);
5263 struct mvneta_port *pp = netdev_priv(dev);
5265 if (!netif_running(dev))
5268 if (!pp->neta_armada3700) {
5269 spin_lock(&pp->lock);
5270 pp->is_stopped = true;
5271 spin_unlock(&pp->lock);
5273 cpuhp_state_remove_instance_nocalls(online_hpstate,
5275 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
5280 mvneta_stop_dev(pp);
5283 for (queue = 0; queue < rxq_number; queue++) {
5284 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
5286 mvneta_rxq_drop_pkts(pp, rxq);
5289 for (queue = 0; queue < txq_number; queue++) {
5290 struct mvneta_tx_queue *txq = &pp->txqs[queue];
5292 mvneta_txq_hw_deinit(pp, txq);
5296 netif_device_detach(dev);
5297 clk_disable_unprepare(pp->clk_bus);
5298 clk_disable_unprepare(pp->clk);
5303 static int mvneta_resume(struct device *device)
5305 struct platform_device *pdev = to_platform_device(device);
5306 struct net_device *dev = dev_get_drvdata(device);
5307 struct mvneta_port *pp = netdev_priv(dev);
5310 clk_prepare_enable(pp->clk);
5311 if (!IS_ERR(pp->clk_bus))
5312 clk_prepare_enable(pp->clk_bus);
5313 if (pp->dram_target_info || pp->neta_armada3700)
5314 mvneta_conf_mbus_windows(pp, pp->dram_target_info);
5316 err = mvneta_bm_port_init(pdev, pp);
5318 dev_info(&pdev->dev, "use SW buffer management\n");
5319 pp->rx_offset_correction = MVNETA_SKB_HEADROOM;
5323 mvneta_defaults_set(pp);
5324 err = mvneta_port_power_up(pp, pp->phy_interface);
5326 dev_err(device, "can't power up port\n");
5330 netif_device_attach(dev);
5332 if (!netif_running(dev))
5335 for (queue = 0; queue < rxq_number; queue++) {
5336 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
5338 rxq->next_desc_to_proc = 0;
5339 mvneta_rxq_hw_init(pp, rxq);
5342 for (queue = 0; queue < txq_number; queue++) {
5343 struct mvneta_tx_queue *txq = &pp->txqs[queue];
5345 txq->next_desc_to_proc = 0;
5346 mvneta_txq_hw_init(pp, txq);
5349 if (!pp->neta_armada3700) {
5350 spin_lock(&pp->lock);
5351 pp->is_stopped = false;
5352 spin_unlock(&pp->lock);
5353 cpuhp_state_add_instance_nocalls(online_hpstate,
5355 cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
5360 mvneta_start_dev(pp);
5362 mvneta_set_rx_mode(dev);
5368 static SIMPLE_DEV_PM_OPS(mvneta_pm_ops, mvneta_suspend, mvneta_resume);
5370 static const struct of_device_id mvneta_match[] = {
5371 { .compatible = "marvell,armada-370-neta" },
5372 { .compatible = "marvell,armada-xp-neta" },
5373 { .compatible = "marvell,armada-3700-neta" },
5376 MODULE_DEVICE_TABLE(of, mvneta_match);
5378 static struct platform_driver mvneta_driver = {
5379 .probe = mvneta_probe,
5380 .remove = mvneta_remove,
5382 .name = MVNETA_DRIVER_NAME,
5383 .of_match_table = mvneta_match,
5384 .pm = &mvneta_pm_ops,
5388 static int __init mvneta_driver_init(void)
5392 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/mvneta:online",
5394 mvneta_cpu_down_prepare);
5397 online_hpstate = ret;
5398 ret = cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD, "net/mvneta:dead",
5399 NULL, mvneta_cpu_dead);
5403 ret = platform_driver_register(&mvneta_driver);
5409 cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD);
5411 cpuhp_remove_multi_state(online_hpstate);
5415 module_init(mvneta_driver_init);
5417 static void __exit mvneta_driver_exit(void)
5419 platform_driver_unregister(&mvneta_driver);
5420 cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD);
5421 cpuhp_remove_multi_state(online_hpstate);
5423 module_exit(mvneta_driver_exit);
5425 MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com");
5426 MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
5427 MODULE_LICENSE("GPL");
5429 module_param(rxq_number, int, 0444);
5430 module_param(txq_number, int, 0444);
5432 module_param(rxq_def, int, 0444);
5433 module_param(rx_copybreak, int, 0644);