2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
4 * Copyright (C) 2012 Marvell
6 * Rami Rosen <rosenr@marvell.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/clk.h>
15 #include <linux/cpu.h>
16 #include <linux/etherdevice.h>
17 #include <linux/if_vlan.h>
18 #include <linux/inetdevice.h>
19 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/mbus.h>
23 #include <linux/module.h>
24 #include <linux/netdevice.h>
26 #include <linux/of_address.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_mdio.h>
29 #include <linux/of_net.h>
30 #include <linux/phy/phy.h>
31 #include <linux/phy.h>
32 #include <linux/phylink.h>
33 #include <linux/platform_device.h>
34 #include <linux/skbuff.h>
36 #include "mvneta_bm.h"
40 #include <net/page_pool/helpers.h>
41 #include <net/pkt_sched.h>
42 #include <linux/bpf_trace.h>
45 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
46 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0)
47 #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4
48 #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30
49 #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6
50 #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0
51 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
52 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
53 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
54 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
55 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
56 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
57 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
58 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
59 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
60 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
61 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
62 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
63 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
64 #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2))
65 #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3
66 #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8
67 #define MVNETA_PORT_RX_RESET 0x1cc0
68 #define MVNETA_PORT_RX_DMA_RESET BIT(0)
69 #define MVNETA_PHY_ADDR 0x2000
70 #define MVNETA_PHY_ADDR_MASK 0x1f
71 #define MVNETA_MBUS_RETRY 0x2010
72 #define MVNETA_UNIT_INTR_CAUSE 0x2080
73 #define MVNETA_UNIT_CONTROL 0x20B0
74 #define MVNETA_PHY_POLLING_ENABLE BIT(1)
75 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
76 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
77 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
78 #define MVNETA_BASE_ADDR_ENABLE 0x2290
79 #define MVNETA_AC5_CNM_DDR_TARGET 0x2
80 #define MVNETA_AC5_CNM_DDR_ATTR 0xb
81 #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294
82 #define MVNETA_PORT_CONFIG 0x2400
83 #define MVNETA_UNI_PROMISC_MODE BIT(0)
84 #define MVNETA_DEF_RXQ(q) ((q) << 1)
85 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
86 #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
87 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
88 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
89 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
90 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
91 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
92 MVNETA_DEF_RXQ_ARP(q) | \
93 MVNETA_DEF_RXQ_TCP(q) | \
94 MVNETA_DEF_RXQ_UDP(q) | \
95 MVNETA_DEF_RXQ_BPDU(q) | \
96 MVNETA_TX_UNSET_ERR_SUM | \
97 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
98 #define MVNETA_PORT_CONFIG_EXTEND 0x2404
99 #define MVNETA_MAC_ADDR_LOW 0x2414
100 #define MVNETA_MAC_ADDR_HIGH 0x2418
101 #define MVNETA_SDMA_CONFIG 0x241c
102 #define MVNETA_SDMA_BRST_SIZE_16 4
103 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
104 #define MVNETA_RX_NO_DATA_SWAP BIT(4)
105 #define MVNETA_TX_NO_DATA_SWAP BIT(5)
106 #define MVNETA_DESC_SWAP BIT(6)
107 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
108 #define MVNETA_VLAN_PRIO_TO_RXQ 0x2440
109 #define MVNETA_VLAN_PRIO_RXQ_MAP(prio, rxq) ((rxq) << ((prio) * 3))
110 #define MVNETA_PORT_STATUS 0x2444
111 #define MVNETA_TX_IN_PRGRS BIT(0)
112 #define MVNETA_TX_FIFO_EMPTY BIT(8)
113 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
114 /* Only exists on Armada XP and Armada 370 */
115 #define MVNETA_SERDES_CFG 0x24A0
116 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
117 #define MVNETA_QSGMII_SERDES_PROTO 0x0667
118 #define MVNETA_HSGMII_SERDES_PROTO 0x1107
119 #define MVNETA_TYPE_PRIO 0x24bc
120 #define MVNETA_FORCE_UNI BIT(21)
121 #define MVNETA_TXQ_CMD_1 0x24e4
122 #define MVNETA_TXQ_CMD 0x2448
123 #define MVNETA_TXQ_DISABLE_SHIFT 8
124 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
125 #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484
126 #define MVNETA_OVERRUN_FRAME_COUNT 0x2488
127 #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4
128 #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31)
129 #define MVNETA_ACC_MODE 0x2500
130 #define MVNETA_BM_ADDRESS 0x2504
131 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
132 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
133 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
134 #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq)
135 #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8)
136 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
138 /* Exception Interrupt Port/Queue Cause register
140 * Their behavior depend of the mapping done using the PCPX2Q
141 * registers. For a given CPU if the bit associated to a queue is not
142 * set, then for the register a read from this CPU will always return
143 * 0 and a write won't do anything
146 #define MVNETA_INTR_NEW_CAUSE 0x25a0
147 #define MVNETA_INTR_NEW_MASK 0x25a4
149 /* bits 0..7 = TXQ SENT, one bit per queue.
150 * bits 8..15 = RXQ OCCUP, one bit per queue.
151 * bits 16..23 = RXQ FREE, one bit per queue.
152 * bit 29 = OLD_REG_SUM, see old reg ?
153 * bit 30 = TX_ERR_SUM, one bit for 4 ports
154 * bit 31 = MISC_SUM, one bit for 4 ports
156 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
157 #define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
158 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
159 #define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
160 #define MVNETA_MISCINTR_INTR_MASK BIT(31)
162 #define MVNETA_INTR_OLD_CAUSE 0x25a8
163 #define MVNETA_INTR_OLD_MASK 0x25ac
165 /* Data Path Port/Queue Cause Register */
166 #define MVNETA_INTR_MISC_CAUSE 0x25b0
167 #define MVNETA_INTR_MISC_MASK 0x25b4
169 #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0)
170 #define MVNETA_CAUSE_LINK_CHANGE BIT(1)
171 #define MVNETA_CAUSE_PTP BIT(4)
173 #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7)
174 #define MVNETA_CAUSE_RX_OVERRUN BIT(8)
175 #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9)
176 #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10)
177 #define MVNETA_CAUSE_TX_UNDERUN BIT(11)
178 #define MVNETA_CAUSE_PRBS_ERR BIT(12)
179 #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13)
180 #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14)
182 #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16
183 #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT)
184 #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool)))
186 #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24
187 #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT)
188 #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q)))
190 #define MVNETA_INTR_ENABLE 0x25b8
191 #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00
192 #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff
194 #define MVNETA_RXQ_CMD 0x2680
195 #define MVNETA_RXQ_DISABLE_SHIFT 8
196 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
197 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
198 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
199 #define MVNETA_GMAC_CTRL_0 0x2c00
200 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
201 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
202 #define MVNETA_GMAC0_PORT_1000BASE_X BIT(1)
203 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
204 #define MVNETA_GMAC_CTRL_2 0x2c08
205 #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0)
206 #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
207 #define MVNETA_GMAC2_PORT_RGMII BIT(4)
208 #define MVNETA_GMAC2_PORT_RESET BIT(6)
209 #define MVNETA_GMAC_STATUS 0x2c10
210 #define MVNETA_GMAC_LINK_UP BIT(0)
211 #define MVNETA_GMAC_SPEED_1000 BIT(1)
212 #define MVNETA_GMAC_SPEED_100 BIT(2)
213 #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
214 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
215 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
216 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
217 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
218 #define MVNETA_GMAC_AN_COMPLETE BIT(11)
219 #define MVNETA_GMAC_SYNC_OK BIT(14)
220 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
221 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
222 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
223 #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2)
224 #define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3)
225 #define MVNETA_GMAC_INBAND_RESTART_AN BIT(4)
226 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
227 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
228 #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
229 #define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8)
230 #define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9)
231 #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11)
232 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
233 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
234 #define MVNETA_GMAC_CTRL_4 0x2c90
235 #define MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE BIT(1)
236 #define MVNETA_MIB_COUNTERS_BASE 0x3000
237 #define MVNETA_MIB_LATE_COLLISION 0x7c
238 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
239 #define MVNETA_DA_FILT_OTH_MCAST 0x3500
240 #define MVNETA_DA_FILT_UCAST_BASE 0x3600
241 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
242 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
243 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
244 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
245 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
246 #define MVNETA_TXQ_DEC_SENT_SHIFT 16
247 #define MVNETA_TXQ_DEC_SENT_MASK 0xff
248 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
249 #define MVNETA_TXQ_SENT_DESC_SHIFT 16
250 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
251 #define MVNETA_PORT_TX_RESET 0x3cf0
252 #define MVNETA_PORT_TX_DMA_RESET BIT(0)
253 #define MVNETA_TXQ_CMD1_REG 0x3e00
254 #define MVNETA_TXQ_CMD1_BW_LIM_SEL_V1 BIT(3)
255 #define MVNETA_TXQ_CMD1_BW_LIM_EN BIT(0)
256 #define MVNETA_REFILL_NUM_CLK_REG 0x3e08
257 #define MVNETA_REFILL_MAX_NUM_CLK 0x0000ffff
258 #define MVNETA_TX_MTU 0x3e0c
259 #define MVNETA_TX_TOKEN_SIZE 0x3e14
260 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
261 #define MVNETA_TXQ_BUCKET_REFILL_REG(q) (0x3e20 + ((q) << 2))
262 #define MVNETA_TXQ_BUCKET_REFILL_PERIOD_MASK 0x3ff00000
263 #define MVNETA_TXQ_BUCKET_REFILL_PERIOD_SHIFT 20
264 #define MVNETA_TXQ_BUCKET_REFILL_VALUE_MAX 0x0007ffff
265 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
266 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
268 /* The values of the bucket refill base period and refill period are taken from
269 * the reference manual, and adds up to a base resolution of 10Kbps. This allows
270 * to cover all rate-limit values from 10Kbps up to 5Gbps
273 /* Base period for the rate limit algorithm */
274 #define MVNETA_TXQ_BUCKET_REFILL_BASE_PERIOD_NS 100
276 /* Number of Base Period to wait between each bucket refill */
277 #define MVNETA_TXQ_BUCKET_REFILL_PERIOD 1000
279 /* The base resolution for rate limiting, in bps. Any max_rate value should be
280 * a multiple of that value.
282 #define MVNETA_TXQ_RATE_LIMIT_RESOLUTION (NSEC_PER_SEC / \
283 (MVNETA_TXQ_BUCKET_REFILL_BASE_PERIOD_NS * \
284 MVNETA_TXQ_BUCKET_REFILL_PERIOD))
286 #define MVNETA_LPI_CTRL_0 0x2cc0
287 #define MVNETA_LPI_CTRL_1 0x2cc4
288 #define MVNETA_LPI_REQUEST_ENABLE BIT(0)
289 #define MVNETA_LPI_CTRL_2 0x2cc8
290 #define MVNETA_LPI_STATUS 0x2ccc
292 #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
294 /* Descriptor ring Macros */
295 #define MVNETA_QUEUE_NEXT_DESC(q, index) \
296 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
298 /* Various constants */
301 #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */
302 #define MVNETA_RX_COAL_PKTS 32
303 #define MVNETA_RX_COAL_USEC 100
305 /* The two bytes Marvell header. Either contains a special value used
306 * by Marvell switches when a specific hardware mode is enabled (not
307 * supported by this driver) or is filled automatically by zeroes on
308 * the RX side. Those two bytes being at the front of the Ethernet
309 * header, they allow to have the IP header aligned on a 4 bytes
310 * boundary automatically: the hardware skips those two bytes on its
313 #define MVNETA_MH_SIZE 2
315 #define MVNETA_VLAN_TAG_LEN 4
317 #define MVNETA_TX_CSUM_DEF_SIZE 1600
318 #define MVNETA_TX_CSUM_MAX_SIZE 9800
319 #define MVNETA_ACC_MODE_EXT1 1
320 #define MVNETA_ACC_MODE_EXT2 2
322 #define MVNETA_MAX_DECODE_WIN 6
324 /* Timeout constants */
325 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
326 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
327 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
329 #define MVNETA_TX_MTU_MAX 0x3ffff
331 /* The RSS lookup table actually has 256 entries but we do not use
334 #define MVNETA_RSS_LU_TABLE_SIZE 1
336 /* Max number of Rx descriptors */
337 #define MVNETA_MAX_RXD 512
339 /* Max number of Tx descriptors */
340 #define MVNETA_MAX_TXD 1024
342 /* Max number of allowed TCP segments for software TSO */
343 #define MVNETA_MAX_TSO_SEGS 100
345 #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
347 /* The size of a TSO header page */
348 #define MVNETA_TSO_PAGE_SIZE (2 * PAGE_SIZE)
350 /* Number of TSO headers per page. This should be a power of 2 */
351 #define MVNETA_TSO_PER_PAGE (MVNETA_TSO_PAGE_SIZE / TSO_HEADER_SIZE)
353 /* Maximum number of TSO header pages */
354 #define MVNETA_MAX_TSO_PAGES (MVNETA_MAX_TXD / MVNETA_TSO_PER_PAGE)
356 /* descriptor aligned size */
357 #define MVNETA_DESC_ALIGNED_SIZE 32
359 /* Number of bytes to be taken into account by HW when putting incoming data
360 * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet
361 * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers.
363 #define MVNETA_RX_PKT_OFFSET_CORRECTION 64
365 #define MVNETA_RX_PKT_SIZE(mtu) \
366 ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
367 ETH_HLEN + ETH_FCS_LEN, \
370 /* Driver assumes that the last 3 bits are 0 */
371 #define MVNETA_SKB_HEADROOM ALIGN(max(NET_SKB_PAD, XDP_PACKET_HEADROOM), 8)
372 #define MVNETA_SKB_PAD (SKB_DATA_ALIGN(sizeof(struct skb_shared_info) + \
373 MVNETA_SKB_HEADROOM))
374 #define MVNETA_MAX_RX_BUF_SIZE (PAGE_SIZE - MVNETA_SKB_PAD)
376 #define MVNETA_RX_GET_BM_POOL_ID(rxd) \
377 (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT)
380 ETHTOOL_STAT_EEE_WAKEUP,
381 ETHTOOL_STAT_SKB_ALLOC_ERR,
382 ETHTOOL_STAT_REFILL_ERR,
383 ETHTOOL_XDP_REDIRECT,
389 ETHTOOL_XDP_XMIT_ERR,
393 struct mvneta_statistic {
394 unsigned short offset;
396 const char name[ETH_GSTRING_LEN];
403 #define MVNETA_XDP_PASS 0
404 #define MVNETA_XDP_DROPPED BIT(0)
405 #define MVNETA_XDP_TX BIT(1)
406 #define MVNETA_XDP_REDIR BIT(2)
408 static const struct mvneta_statistic mvneta_statistics[] = {
409 { 0x3000, T_REG_64, "good_octets_received", },
410 { 0x3010, T_REG_32, "good_frames_received", },
411 { 0x3008, T_REG_32, "bad_octets_received", },
412 { 0x3014, T_REG_32, "bad_frames_received", },
413 { 0x3018, T_REG_32, "broadcast_frames_received", },
414 { 0x301c, T_REG_32, "multicast_frames_received", },
415 { 0x3050, T_REG_32, "unrec_mac_control_received", },
416 { 0x3058, T_REG_32, "good_fc_received", },
417 { 0x305c, T_REG_32, "bad_fc_received", },
418 { 0x3060, T_REG_32, "undersize_received", },
419 { 0x3064, T_REG_32, "fragments_received", },
420 { 0x3068, T_REG_32, "oversize_received", },
421 { 0x306c, T_REG_32, "jabber_received", },
422 { 0x3070, T_REG_32, "mac_receive_error", },
423 { 0x3074, T_REG_32, "bad_crc_event", },
424 { 0x3078, T_REG_32, "collision", },
425 { 0x307c, T_REG_32, "late_collision", },
426 { 0x2484, T_REG_32, "rx_discard", },
427 { 0x2488, T_REG_32, "rx_overrun", },
428 { 0x3020, T_REG_32, "frames_64_octets", },
429 { 0x3024, T_REG_32, "frames_65_to_127_octets", },
430 { 0x3028, T_REG_32, "frames_128_to_255_octets", },
431 { 0x302c, T_REG_32, "frames_256_to_511_octets", },
432 { 0x3030, T_REG_32, "frames_512_to_1023_octets", },
433 { 0x3034, T_REG_32, "frames_1024_to_max_octets", },
434 { 0x3038, T_REG_64, "good_octets_sent", },
435 { 0x3040, T_REG_32, "good_frames_sent", },
436 { 0x3044, T_REG_32, "excessive_collision", },
437 { 0x3048, T_REG_32, "multicast_frames_sent", },
438 { 0x304c, T_REG_32, "broadcast_frames_sent", },
439 { 0x3054, T_REG_32, "fc_sent", },
440 { 0x300c, T_REG_32, "internal_mac_transmit_err", },
441 { ETHTOOL_STAT_EEE_WAKEUP, T_SW, "eee_wakeup_errors", },
442 { ETHTOOL_STAT_SKB_ALLOC_ERR, T_SW, "skb_alloc_errors", },
443 { ETHTOOL_STAT_REFILL_ERR, T_SW, "refill_errors", },
444 { ETHTOOL_XDP_REDIRECT, T_SW, "rx_xdp_redirect", },
445 { ETHTOOL_XDP_PASS, T_SW, "rx_xdp_pass", },
446 { ETHTOOL_XDP_DROP, T_SW, "rx_xdp_drop", },
447 { ETHTOOL_XDP_TX, T_SW, "rx_xdp_tx", },
448 { ETHTOOL_XDP_TX_ERR, T_SW, "rx_xdp_tx_errors", },
449 { ETHTOOL_XDP_XMIT, T_SW, "tx_xdp_xmit", },
450 { ETHTOOL_XDP_XMIT_ERR, T_SW, "tx_xdp_xmit_errors", },
453 struct mvneta_stats {
468 struct mvneta_ethtool_stats {
469 struct mvneta_stats ps;
474 struct mvneta_pcpu_stats {
475 struct u64_stats_sync syncp;
477 struct mvneta_ethtool_stats es;
482 struct mvneta_pcpu_port {
483 /* Pointer to the shared port */
484 struct mvneta_port *pp;
486 /* Pointer to the CPU-local NAPI struct */
487 struct napi_struct napi;
489 /* Cause of the previous interrupt */
499 struct mvneta_pcpu_port __percpu *ports;
500 struct mvneta_pcpu_stats __percpu *stats;
506 struct mvneta_rx_queue *rxqs;
507 struct mvneta_tx_queue *txqs;
508 struct net_device *dev;
509 struct hlist_node node_online;
510 struct hlist_node node_dead;
512 /* Protect the access to the percpu interrupt registers,
513 * ensuring that the configuration remains coherent.
519 struct napi_struct napi;
521 struct bpf_prog *xdp_prog;
531 phy_interface_t phy_interface;
532 struct device_node *dn;
533 unsigned int tx_csum_limit;
534 struct phylink *phylink;
535 struct phylink_config phylink_config;
536 struct phylink_pcs phylink_pcs;
539 struct mvneta_bm *bm_priv;
540 struct mvneta_bm_pool *pool_long;
541 struct mvneta_bm_pool *pool_short;
548 u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
550 u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
552 /* Flags for special SoC configurations */
553 bool neta_armada3700;
555 u16 rx_offset_correction;
556 const struct mbus_dram_target_info *dram_target_info;
559 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
560 * layout of the transmit and reception DMA descriptors, and their
561 * layout is therefore defined by the hardware design
564 #define MVNETA_TX_L3_OFF_SHIFT 0
565 #define MVNETA_TX_IP_HLEN_SHIFT 8
566 #define MVNETA_TX_L4_UDP BIT(16)
567 #define MVNETA_TX_L3_IP6 BIT(17)
568 #define MVNETA_TXD_IP_CSUM BIT(18)
569 #define MVNETA_TXD_Z_PAD BIT(19)
570 #define MVNETA_TXD_L_DESC BIT(20)
571 #define MVNETA_TXD_F_DESC BIT(21)
572 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
573 MVNETA_TXD_L_DESC | \
575 #define MVNETA_TX_L4_CSUM_FULL BIT(30)
576 #define MVNETA_TX_L4_CSUM_NOT BIT(31)
578 #define MVNETA_RXD_ERR_CRC 0x0
579 #define MVNETA_RXD_BM_POOL_SHIFT 13
580 #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14))
581 #define MVNETA_RXD_ERR_SUMMARY BIT(16)
582 #define MVNETA_RXD_ERR_OVERRUN BIT(17)
583 #define MVNETA_RXD_ERR_LEN BIT(18)
584 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
585 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
586 #define MVNETA_RXD_L3_IP4 BIT(25)
587 #define MVNETA_RXD_LAST_DESC BIT(26)
588 #define MVNETA_RXD_FIRST_DESC BIT(27)
589 #define MVNETA_RXD_FIRST_LAST_DESC (MVNETA_RXD_FIRST_DESC | \
590 MVNETA_RXD_LAST_DESC)
591 #define MVNETA_RXD_L4_CSUM_OK BIT(30)
593 #if defined(__LITTLE_ENDIAN)
594 struct mvneta_tx_desc {
595 u32 command; /* Options used by HW for packet transmitting.*/
596 u16 reserved1; /* csum_l4 (for future use) */
597 u16 data_size; /* Data size of transmitted packet in bytes */
598 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
599 u32 reserved2; /* hw_cmd - (for future use, PMT) */
600 u32 reserved3[4]; /* Reserved - (for future use) */
603 struct mvneta_rx_desc {
604 u32 status; /* Info about received packet */
605 u16 reserved1; /* pnc_info - (for future use, PnC) */
606 u16 data_size; /* Size of received packet in bytes */
608 u32 buf_phys_addr; /* Physical address of the buffer */
609 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
611 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
612 u16 reserved3; /* prefetch_cmd, for future use */
613 u16 reserved4; /* csum_l4 - (for future use, PnC) */
615 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
616 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
619 struct mvneta_tx_desc {
620 u16 data_size; /* Data size of transmitted packet in bytes */
621 u16 reserved1; /* csum_l4 (for future use) */
622 u32 command; /* Options used by HW for packet transmitting.*/
623 u32 reserved2; /* hw_cmd - (for future use, PMT) */
624 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
625 u32 reserved3[4]; /* Reserved - (for future use) */
628 struct mvneta_rx_desc {
629 u16 data_size; /* Size of received packet in bytes */
630 u16 reserved1; /* pnc_info - (for future use, PnC) */
631 u32 status; /* Info about received packet */
633 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
634 u32 buf_phys_addr; /* Physical address of the buffer */
636 u16 reserved4; /* csum_l4 - (for future use, PnC) */
637 u16 reserved3; /* prefetch_cmd, for future use */
638 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
640 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
641 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
645 enum mvneta_tx_buf_type {
652 struct mvneta_tx_buf {
653 enum mvneta_tx_buf_type type;
655 struct xdp_frame *xdpf;
660 struct mvneta_tx_queue {
661 /* Number of this TX queue, in the range 0-7 */
664 /* Number of TX DMA descriptors in the descriptor ring */
667 /* Number of currently used TX DMA descriptor in the
672 int tx_stop_threshold;
673 int tx_wake_threshold;
675 /* Array of transmitted buffers */
676 struct mvneta_tx_buf *buf;
678 /* Index of last TX DMA descriptor that was inserted */
681 /* Index of the TX DMA descriptor to be cleaned up */
686 /* Virtual address of the TX DMA descriptors array */
687 struct mvneta_tx_desc *descs;
689 /* DMA address of the TX DMA descriptors array */
690 dma_addr_t descs_phys;
692 /* Index of the last TX DMA descriptor */
695 /* Index of the next TX DMA descriptor to process */
696 int next_desc_to_proc;
698 /* DMA buffers for TSO headers */
699 char *tso_hdrs[MVNETA_MAX_TSO_PAGES];
701 /* DMA address of TSO headers */
702 dma_addr_t tso_hdrs_phys[MVNETA_MAX_TSO_PAGES];
704 /* Affinity mask for CPUs*/
705 cpumask_t affinity_mask;
708 struct mvneta_rx_queue {
709 /* rx queue number, in the range 0-7 */
712 /* num of rx descriptors in the rx descriptor ring */
719 struct page_pool *page_pool;
720 struct xdp_rxq_info xdp_rxq;
722 /* Virtual address of the RX buffer */
723 void **buf_virt_addr;
725 /* Virtual address of the RX DMA descriptors array */
726 struct mvneta_rx_desc *descs;
728 /* DMA address of the RX DMA descriptors array */
729 dma_addr_t descs_phys;
731 /* Index of the last RX DMA descriptor */
734 /* Index of the next RX DMA descriptor to process */
735 int next_desc_to_proc;
737 /* Index of first RX DMA descriptor to refill */
742 static enum cpuhp_state online_hpstate;
743 /* The hardware supports eight (8) rx queues, but we are only allowing
744 * the first one to be used. Therefore, let's just allocate one queue.
746 static int rxq_number = 8;
747 static int txq_number = 8;
751 static int rx_copybreak __read_mostly = 256;
753 /* HW BM need that each port be identify by a unique ID */
754 static int global_port_id;
756 #define MVNETA_DRIVER_NAME "mvneta"
757 #define MVNETA_DRIVER_VERSION "1.0"
759 /* Utility/helper methods */
761 /* Write helper method */
762 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
764 writel(data, pp->base + offset);
767 /* Read helper method */
768 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
770 return readl(pp->base + offset);
773 /* Increment txq get counter */
774 static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq)
776 txq->txq_get_index++;
777 if (txq->txq_get_index == txq->size)
778 txq->txq_get_index = 0;
781 /* Increment txq put counter */
782 static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq)
784 txq->txq_put_index++;
785 if (txq->txq_put_index == txq->size)
786 txq->txq_put_index = 0;
790 /* Clear all MIB counters */
791 static void mvneta_mib_counters_clear(struct mvneta_port *pp)
795 /* Perform dummy reads from MIB counters */
796 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
797 mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
798 mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT);
799 mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT);
802 /* Get System Network Statistics */
804 mvneta_get_stats64(struct net_device *dev,
805 struct rtnl_link_stats64 *stats)
807 struct mvneta_port *pp = netdev_priv(dev);
811 for_each_possible_cpu(cpu) {
812 struct mvneta_pcpu_stats *cpu_stats;
820 cpu_stats = per_cpu_ptr(pp->stats, cpu);
822 start = u64_stats_fetch_begin(&cpu_stats->syncp);
823 rx_packets = cpu_stats->es.ps.rx_packets;
824 rx_bytes = cpu_stats->es.ps.rx_bytes;
825 rx_dropped = cpu_stats->rx_dropped;
826 rx_errors = cpu_stats->rx_errors;
827 tx_packets = cpu_stats->es.ps.tx_packets;
828 tx_bytes = cpu_stats->es.ps.tx_bytes;
829 } while (u64_stats_fetch_retry(&cpu_stats->syncp, start));
831 stats->rx_packets += rx_packets;
832 stats->rx_bytes += rx_bytes;
833 stats->rx_dropped += rx_dropped;
834 stats->rx_errors += rx_errors;
835 stats->tx_packets += tx_packets;
836 stats->tx_bytes += tx_bytes;
839 stats->tx_dropped = dev->stats.tx_dropped;
842 /* Rx descriptors helper methods */
844 /* Checks whether the RX descriptor having this status is both the first
845 * and the last descriptor for the RX packet. Each RX packet is currently
846 * received through a single RX descriptor, so not having each RX
847 * descriptor with its first and last bits set is an error
849 static int mvneta_rxq_desc_is_first_last(u32 status)
851 return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
852 MVNETA_RXD_FIRST_LAST_DESC;
855 /* Add number of descriptors ready to receive new packets */
856 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
857 struct mvneta_rx_queue *rxq,
860 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
863 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
864 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
865 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
866 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
867 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
870 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
871 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
874 /* Get number of RX descriptors occupied by received packets */
875 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
876 struct mvneta_rx_queue *rxq)
880 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
881 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
884 /* Update num of rx desc called upon return from rx path or
885 * from mvneta_rxq_drop_pkts().
887 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
888 struct mvneta_rx_queue *rxq,
889 int rx_done, int rx_filled)
893 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
895 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
896 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
900 /* Only 255 descriptors can be added at once */
901 while ((rx_done > 0) || (rx_filled > 0)) {
902 if (rx_done <= 0xff) {
909 if (rx_filled <= 0xff) {
910 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
913 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
916 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
920 /* Get pointer to next RX descriptor to be processed by SW */
921 static struct mvneta_rx_desc *
922 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
924 int rx_desc = rxq->next_desc_to_proc;
926 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
927 prefetch(rxq->descs + rxq->next_desc_to_proc);
928 return rxq->descs + rx_desc;
931 /* Change maximum receive size of the port. */
932 static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size)
936 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
937 val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK;
938 val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) <<
939 MVNETA_GMAC_MAX_RX_SIZE_SHIFT;
940 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
944 /* Set rx queue offset */
945 static void mvneta_rxq_offset_set(struct mvneta_port *pp,
946 struct mvneta_rx_queue *rxq,
951 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
952 val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK;
955 val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3);
956 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
960 /* Tx descriptors helper methods */
962 /* Update HW with number of TX descriptors to be sent */
963 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
964 struct mvneta_tx_queue *txq,
969 pend_desc += txq->pending;
971 /* Only 255 Tx descriptors can be added at once */
973 val = min(pend_desc, 255);
974 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
976 } while (pend_desc > 0);
980 /* Get pointer to next TX descriptor to be processed (send) by HW */
981 static struct mvneta_tx_desc *
982 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
984 int tx_desc = txq->next_desc_to_proc;
986 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
987 return txq->descs + tx_desc;
990 /* Release the last allocated TX descriptor. Useful to handle DMA
991 * mapping failures in the TX path.
993 static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq)
995 if (txq->next_desc_to_proc == 0)
996 txq->next_desc_to_proc = txq->last_desc - 1;
998 txq->next_desc_to_proc--;
1001 /* Set rxq buf size */
1002 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
1003 struct mvneta_rx_queue *rxq,
1008 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
1010 val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
1011 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
1013 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
1016 /* Disable buffer management (BM) */
1017 static void mvneta_rxq_bm_disable(struct mvneta_port *pp,
1018 struct mvneta_rx_queue *rxq)
1022 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
1023 val &= ~MVNETA_RXQ_HW_BUF_ALLOC;
1024 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
1027 /* Enable buffer management (BM) */
1028 static void mvneta_rxq_bm_enable(struct mvneta_port *pp,
1029 struct mvneta_rx_queue *rxq)
1033 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
1034 val |= MVNETA_RXQ_HW_BUF_ALLOC;
1035 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
1038 /* Notify HW about port's assignment of pool for bigger packets */
1039 static void mvneta_rxq_long_pool_set(struct mvneta_port *pp,
1040 struct mvneta_rx_queue *rxq)
1044 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
1045 val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK;
1046 val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT);
1048 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
1051 /* Notify HW about port's assignment of pool for smaller packets */
1052 static void mvneta_rxq_short_pool_set(struct mvneta_port *pp,
1053 struct mvneta_rx_queue *rxq)
1057 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
1058 val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK;
1059 val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT);
1061 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
1064 /* Set port's receive buffer size for assigned BM pool */
1065 static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp,
1071 if (!IS_ALIGNED(buf_size, 8)) {
1072 dev_warn(pp->dev->dev.parent,
1073 "illegal buf_size value %d, round to %d\n",
1074 buf_size, ALIGN(buf_size, 8));
1075 buf_size = ALIGN(buf_size, 8);
1078 val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id));
1079 val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK;
1080 mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val);
1083 /* Configure MBUS window in order to enable access BM internal SRAM */
1084 static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize,
1087 u32 win_enable, win_protect;
1090 win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE);
1092 if (pp->bm_win_id < 0) {
1093 /* Find first not occupied window */
1094 for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) {
1095 if (win_enable & (1 << i)) {
1100 if (i == MVNETA_MAX_DECODE_WIN)
1106 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
1107 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
1110 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
1112 mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) |
1113 (attr << 8) | target);
1115 mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000);
1117 win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE);
1118 win_protect |= 3 << (2 * i);
1119 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
1121 win_enable &= ~(1 << i);
1122 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
1127 static int mvneta_bm_port_mbus_init(struct mvneta_port *pp)
1133 /* Get BM window information */
1134 err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize,
1141 /* Open NETA -> BM window */
1142 err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize,
1145 netdev_info(pp->dev, "fail to configure mbus window to BM\n");
1151 /* Assign and initialize pools for port. In case of fail
1152 * buffer manager will remain disabled for current port.
1154 static int mvneta_bm_port_init(struct platform_device *pdev,
1155 struct mvneta_port *pp)
1157 struct device_node *dn = pdev->dev.of_node;
1158 u32 long_pool_id, short_pool_id;
1160 if (!pp->neta_armada3700) {
1163 ret = mvneta_bm_port_mbus_init(pp);
1168 if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) {
1169 netdev_info(pp->dev, "missing long pool id\n");
1173 /* Create port's long pool depending on mtu */
1174 pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id,
1175 MVNETA_BM_LONG, pp->id,
1176 MVNETA_RX_PKT_SIZE(pp->dev->mtu));
1177 if (!pp->pool_long) {
1178 netdev_info(pp->dev, "fail to obtain long pool for port\n");
1182 pp->pool_long->port_map |= 1 << pp->id;
1184 mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size,
1187 /* If short pool id is not defined, assume using single pool */
1188 if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id))
1189 short_pool_id = long_pool_id;
1191 /* Create port's short pool */
1192 pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id,
1193 MVNETA_BM_SHORT, pp->id,
1194 MVNETA_BM_SHORT_PKT_SIZE);
1195 if (!pp->pool_short) {
1196 netdev_info(pp->dev, "fail to obtain short pool for port\n");
1197 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
1201 if (short_pool_id != long_pool_id) {
1202 pp->pool_short->port_map |= 1 << pp->id;
1203 mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size,
1204 pp->pool_short->id);
1210 /* Update settings of a pool for bigger packets */
1211 static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu)
1213 struct mvneta_bm_pool *bm_pool = pp->pool_long;
1214 struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool;
1217 /* Release all buffers from long pool */
1218 mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id);
1219 if (hwbm_pool->buf_num) {
1220 WARN(1, "cannot free all buffers in pool %d\n",
1225 bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu);
1226 bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size);
1227 hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
1228 SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size));
1230 /* Fill entire long pool */
1231 num = hwbm_pool_add(hwbm_pool, hwbm_pool->size);
1232 if (num != hwbm_pool->size) {
1233 WARN(1, "pool %d: %d of %d allocated\n",
1234 bm_pool->id, num, hwbm_pool->size);
1237 mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id);
1242 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
1243 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id);
1246 pp->rx_offset_correction = MVNETA_SKB_HEADROOM;
1247 mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1);
1248 netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n");
1251 /* Start the Ethernet port RX and TX activity */
1252 static void mvneta_port_up(struct mvneta_port *pp)
1257 /* Enable all initialized TXs. */
1259 for (queue = 0; queue < txq_number; queue++) {
1260 struct mvneta_tx_queue *txq = &pp->txqs[queue];
1262 q_map |= (1 << queue);
1264 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
1267 /* Enable all initialized RXQs. */
1268 for (queue = 0; queue < rxq_number; queue++) {
1269 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
1272 q_map |= (1 << queue);
1274 mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
1277 /* Stop the Ethernet port activity */
1278 static void mvneta_port_down(struct mvneta_port *pp)
1283 /* Stop Rx port activity. Check port Rx activity. */
1284 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
1286 /* Issue stop command for active channels only */
1288 mvreg_write(pp, MVNETA_RXQ_CMD,
1289 val << MVNETA_RXQ_DISABLE_SHIFT);
1291 /* Wait for all Rx activity to terminate. */
1294 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
1295 netdev_warn(pp->dev,
1296 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n",
1302 val = mvreg_read(pp, MVNETA_RXQ_CMD);
1303 } while (val & MVNETA_RXQ_ENABLE_MASK);
1305 /* Stop Tx port activity. Check port Tx activity. Issue stop
1306 * command for active channels only
1308 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
1311 mvreg_write(pp, MVNETA_TXQ_CMD,
1312 (val << MVNETA_TXQ_DISABLE_SHIFT));
1314 /* Wait for all Tx activity to terminate. */
1317 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
1318 netdev_warn(pp->dev,
1319 "TIMEOUT for TX stopped status=0x%08x\n",
1325 /* Check TX Command reg that all Txqs are stopped */
1326 val = mvreg_read(pp, MVNETA_TXQ_CMD);
1328 } while (val & MVNETA_TXQ_ENABLE_MASK);
1330 /* Double check to verify that TX FIFO is empty */
1333 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
1334 netdev_warn(pp->dev,
1335 "TX FIFO empty timeout status=0x%08x\n",
1341 val = mvreg_read(pp, MVNETA_PORT_STATUS);
1342 } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
1343 (val & MVNETA_TX_IN_PRGRS));
1348 /* Enable the port by setting the port enable bit of the MAC control register */
1349 static void mvneta_port_enable(struct mvneta_port *pp)
1354 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
1355 val |= MVNETA_GMAC0_PORT_ENABLE;
1356 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
1359 /* Disable the port and wait for about 200 usec before retuning */
1360 static void mvneta_port_disable(struct mvneta_port *pp)
1364 /* Reset the Enable bit in the Serial Control Register */
1365 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
1366 val &= ~MVNETA_GMAC0_PORT_ENABLE;
1367 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
1372 /* Multicast tables methods */
1374 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
1375 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
1383 val = 0x1 | (queue << 1);
1384 val |= (val << 24) | (val << 16) | (val << 8);
1387 for (offset = 0; offset <= 0xc; offset += 4)
1388 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
1391 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
1392 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
1400 val = 0x1 | (queue << 1);
1401 val |= (val << 24) | (val << 16) | (val << 8);
1404 for (offset = 0; offset <= 0xfc; offset += 4)
1405 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
1409 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
1410 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
1416 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
1419 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
1420 val = 0x1 | (queue << 1);
1421 val |= (val << 24) | (val << 16) | (val << 8);
1424 for (offset = 0; offset <= 0xfc; offset += 4)
1425 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
1428 static void mvneta_percpu_unmask_interrupt(void *arg)
1430 struct mvneta_port *pp = arg;
1432 /* All the queue are unmasked, but actually only the ones
1433 * mapped to this CPU will be unmasked
1435 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
1436 MVNETA_RX_INTR_MASK_ALL |
1437 MVNETA_TX_INTR_MASK_ALL |
1438 MVNETA_MISCINTR_INTR_MASK);
1441 static void mvneta_percpu_mask_interrupt(void *arg)
1443 struct mvneta_port *pp = arg;
1445 /* All the queue are masked, but actually only the ones
1446 * mapped to this CPU will be masked
1448 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
1449 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
1450 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
1453 static void mvneta_percpu_clear_intr_cause(void *arg)
1455 struct mvneta_port *pp = arg;
1457 /* All the queue are cleared, but actually only the ones
1458 * mapped to this CPU will be cleared
1460 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
1461 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
1462 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
1465 /* This method sets defaults to the NETA port:
1466 * Clears interrupt Cause and Mask registers.
1467 * Clears all MAC tables.
1468 * Sets defaults to all registers.
1469 * Resets RX and TX descriptor rings.
1471 * This method can be called after mvneta_port_down() to return the port
1472 * settings to defaults.
1474 static void mvneta_defaults_set(struct mvneta_port *pp)
1479 int max_cpu = num_present_cpus();
1481 /* Clear all Cause registers */
1482 on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
1484 /* Mask all interrupts */
1485 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
1486 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
1488 /* Enable MBUS Retry bit16 */
1489 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
1491 /* Set CPU queue access map. CPUs are assigned to the RX and
1492 * TX queues modulo their number. If there is only one TX
1493 * queue then it is assigned to the CPU associated to the
1496 for_each_present_cpu(cpu) {
1497 int rxq_map = 0, txq_map = 0;
1499 if (!pp->neta_armada3700) {
1500 for (rxq = 0; rxq < rxq_number; rxq++)
1501 if ((rxq % max_cpu) == cpu)
1502 rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
1504 for (txq = 0; txq < txq_number; txq++)
1505 if ((txq % max_cpu) == cpu)
1506 txq_map |= MVNETA_CPU_TXQ_ACCESS(txq);
1508 /* With only one TX queue we configure a special case
1509 * which will allow to get all the irq on a single
1512 if (txq_number == 1)
1513 txq_map = (cpu == pp->rxq_def) ?
1514 MVNETA_CPU_TXQ_ACCESS(0) : 0;
1517 txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
1518 rxq_map = MVNETA_CPU_RXQ_ACCESS_ALL_MASK;
1521 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
1524 /* Reset RX and TX DMAs */
1525 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
1526 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
1528 /* Disable Legacy WRR, Disable EJP, Release from reset */
1529 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
1530 for (queue = 0; queue < txq_number; queue++) {
1531 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
1532 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
1535 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
1536 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
1538 /* Set Port Acceleration Mode */
1540 /* HW buffer management + legacy parser */
1541 val = MVNETA_ACC_MODE_EXT2;
1543 /* SW buffer management + legacy parser */
1544 val = MVNETA_ACC_MODE_EXT1;
1545 mvreg_write(pp, MVNETA_ACC_MODE, val);
1548 mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr);
1550 /* Update val of portCfg register accordingly with all RxQueue types */
1551 val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def);
1552 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
1555 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
1556 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
1558 /* Build PORT_SDMA_CONFIG_REG */
1561 /* Default burst size */
1562 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
1563 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
1564 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
1566 #if defined(__BIG_ENDIAN)
1567 val |= MVNETA_DESC_SWAP;
1570 /* Assign port SDMA configuration */
1571 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
1573 /* Disable PHY polling in hardware, since we're using the
1574 * kernel phylib to do this.
1576 val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
1577 val &= ~MVNETA_PHY_POLLING_ENABLE;
1578 mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
1580 mvneta_set_ucast_table(pp, -1);
1581 mvneta_set_special_mcast_table(pp, -1);
1582 mvneta_set_other_mcast_table(pp, -1);
1584 /* Set port interrupt enable register - default enable all */
1585 mvreg_write(pp, MVNETA_INTR_ENABLE,
1586 (MVNETA_RXQ_INTR_ENABLE_ALL_MASK
1587 | MVNETA_TXQ_INTR_ENABLE_ALL_MASK));
1589 mvneta_mib_counters_clear(pp);
1592 /* Set max sizes for tx queues */
1593 static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size)
1599 mtu = max_tx_size * 8;
1600 if (mtu > MVNETA_TX_MTU_MAX)
1601 mtu = MVNETA_TX_MTU_MAX;
1604 val = mvreg_read(pp, MVNETA_TX_MTU);
1605 val &= ~MVNETA_TX_MTU_MAX;
1607 mvreg_write(pp, MVNETA_TX_MTU, val);
1609 /* TX token size and all TXQs token size must be larger that MTU */
1610 val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE);
1612 size = val & MVNETA_TX_TOKEN_SIZE_MAX;
1615 val &= ~MVNETA_TX_TOKEN_SIZE_MAX;
1617 mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val);
1619 for (queue = 0; queue < txq_number; queue++) {
1620 val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue));
1622 size = val & MVNETA_TXQ_TOKEN_SIZE_MAX;
1625 val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX;
1627 mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val);
1632 /* Set unicast address */
1633 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
1636 unsigned int unicast_reg;
1637 unsigned int tbl_offset;
1638 unsigned int reg_offset;
1640 /* Locate the Unicast table entry */
1641 last_nibble = (0xf & last_nibble);
1643 /* offset from unicast tbl base */
1644 tbl_offset = (last_nibble / 4) * 4;
1646 /* offset within the above reg */
1647 reg_offset = last_nibble % 4;
1649 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
1652 /* Clear accepts frame bit at specified unicast DA tbl entry */
1653 unicast_reg &= ~(0xff << (8 * reg_offset));
1655 unicast_reg &= ~(0xff << (8 * reg_offset));
1656 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1659 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
1662 /* Set mac address */
1663 static void mvneta_mac_addr_set(struct mvneta_port *pp,
1664 const unsigned char *addr, int queue)
1670 mac_l = (addr[4] << 8) | (addr[5]);
1671 mac_h = (addr[0] << 24) | (addr[1] << 16) |
1672 (addr[2] << 8) | (addr[3] << 0);
1674 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
1675 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
1678 /* Accept frames of this address */
1679 mvneta_set_ucast_addr(pp, addr[5], queue);
1682 /* Set the number of packets that will be received before RX interrupt
1683 * will be generated by HW.
1685 static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp,
1686 struct mvneta_rx_queue *rxq, u32 value)
1688 mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id),
1689 value | MVNETA_RXQ_NON_OCCUPIED(0));
1692 /* Set the time delay in usec before RX interrupt will be generated by
1695 static void mvneta_rx_time_coal_set(struct mvneta_port *pp,
1696 struct mvneta_rx_queue *rxq, u32 value)
1699 unsigned long clk_rate;
1701 clk_rate = clk_get_rate(pp->clk);
1702 val = (clk_rate / 1000000) * value;
1704 mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);
1707 /* Set threshold for TX_DONE pkts coalescing */
1708 static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp,
1709 struct mvneta_tx_queue *txq, u32 value)
1713 val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id));
1715 val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK;
1716 val |= MVNETA_TXQ_SENT_THRESH_MASK(value);
1718 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val);
1721 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
1722 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
1723 u32 phys_addr, void *virt_addr,
1724 struct mvneta_rx_queue *rxq)
1728 rx_desc->buf_phys_addr = phys_addr;
1729 i = rx_desc - rxq->descs;
1730 rxq->buf_virt_addr[i] = virt_addr;
1733 /* Decrement sent descriptors counter */
1734 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
1735 struct mvneta_tx_queue *txq,
1740 /* Only 255 TX descriptors can be updated at once */
1741 while (sent_desc > 0xff) {
1742 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
1743 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1744 sent_desc = sent_desc - 0xff;
1747 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
1748 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1751 /* Get number of TX descriptors already sent by HW */
1752 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
1753 struct mvneta_tx_queue *txq)
1758 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
1759 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
1760 MVNETA_TXQ_SENT_DESC_SHIFT;
1765 /* Get number of sent descriptors and decrement counter.
1766 * The number of sent descriptors is returned.
1768 static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp,
1769 struct mvneta_tx_queue *txq)
1773 /* Get number of sent descriptors */
1774 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1776 /* Decrement sent descriptors counter */
1778 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
1783 /* Set TXQ descriptors fields relevant for CSUM calculation */
1784 static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto,
1785 int ip_hdr_len, int l4_proto)
1789 /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1790 * G_L4_chk, L4_type; required only for checksum
1793 command = l3_offs << MVNETA_TX_L3_OFF_SHIFT;
1794 command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT;
1796 if (l3_proto == htons(ETH_P_IP))
1797 command |= MVNETA_TXD_IP_CSUM;
1799 command |= MVNETA_TX_L3_IP6;
1801 if (l4_proto == IPPROTO_TCP)
1802 command |= MVNETA_TX_L4_CSUM_FULL;
1803 else if (l4_proto == IPPROTO_UDP)
1804 command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL;
1806 command |= MVNETA_TX_L4_CSUM_NOT;
1812 /* Display more error info */
1813 static void mvneta_rx_error(struct mvneta_port *pp,
1814 struct mvneta_rx_desc *rx_desc)
1816 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
1817 u32 status = rx_desc->status;
1819 /* update per-cpu counter */
1820 u64_stats_update_begin(&stats->syncp);
1822 u64_stats_update_end(&stats->syncp);
1824 switch (status & MVNETA_RXD_ERR_CODE_MASK) {
1825 case MVNETA_RXD_ERR_CRC:
1826 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
1827 status, rx_desc->data_size);
1829 case MVNETA_RXD_ERR_OVERRUN:
1830 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
1831 status, rx_desc->data_size);
1833 case MVNETA_RXD_ERR_LEN:
1834 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
1835 status, rx_desc->data_size);
1837 case MVNETA_RXD_ERR_RESOURCE:
1838 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
1839 status, rx_desc->data_size);
1844 /* Handle RX checksum offload based on the descriptor's status */
1845 static int mvneta_rx_csum(struct mvneta_port *pp, u32 status)
1847 if ((pp->dev->features & NETIF_F_RXCSUM) &&
1848 (status & MVNETA_RXD_L3_IP4) &&
1849 (status & MVNETA_RXD_L4_CSUM_OK))
1850 return CHECKSUM_UNNECESSARY;
1852 return CHECKSUM_NONE;
1855 /* Return tx queue pointer (find last set bit) according to <cause> returned
1856 * form tx_done reg. <cause> must not be null. The return value is always a
1857 * valid queue for matching the first one found in <cause>.
1859 static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp,
1862 int queue = fls(cause) - 1;
1864 return &pp->txqs[queue];
1867 /* Free tx queue skbuffs */
1868 static void mvneta_txq_bufs_free(struct mvneta_port *pp,
1869 struct mvneta_tx_queue *txq, int num,
1870 struct netdev_queue *nq, bool napi)
1872 unsigned int bytes_compl = 0, pkts_compl = 0;
1873 struct xdp_frame_bulk bq;
1876 xdp_frame_bulk_init(&bq);
1878 rcu_read_lock(); /* need for xdp_return_frame_bulk */
1880 for (i = 0; i < num; i++) {
1881 struct mvneta_tx_buf *buf = &txq->buf[txq->txq_get_index];
1882 struct mvneta_tx_desc *tx_desc = txq->descs +
1885 mvneta_txq_inc_get(txq);
1887 if (buf->type == MVNETA_TYPE_XDP_NDO ||
1888 buf->type == MVNETA_TYPE_SKB)
1889 dma_unmap_single(pp->dev->dev.parent,
1890 tx_desc->buf_phys_addr,
1891 tx_desc->data_size, DMA_TO_DEVICE);
1892 if ((buf->type == MVNETA_TYPE_TSO ||
1893 buf->type == MVNETA_TYPE_SKB) && buf->skb) {
1894 bytes_compl += buf->skb->len;
1896 dev_kfree_skb_any(buf->skb);
1897 } else if ((buf->type == MVNETA_TYPE_XDP_TX ||
1898 buf->type == MVNETA_TYPE_XDP_NDO) && buf->xdpf) {
1899 if (napi && buf->type == MVNETA_TYPE_XDP_TX)
1900 xdp_return_frame_rx_napi(buf->xdpf);
1902 xdp_return_frame_bulk(buf->xdpf, &bq);
1905 xdp_flush_frame_bulk(&bq);
1909 netdev_tx_completed_queue(nq, pkts_compl, bytes_compl);
1912 /* Handle end of transmission */
1913 static void mvneta_txq_done(struct mvneta_port *pp,
1914 struct mvneta_tx_queue *txq)
1916 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
1919 tx_done = mvneta_txq_sent_desc_proc(pp, txq);
1923 mvneta_txq_bufs_free(pp, txq, tx_done, nq, true);
1925 txq->count -= tx_done;
1927 if (netif_tx_queue_stopped(nq)) {
1928 if (txq->count <= txq->tx_wake_threshold)
1929 netif_tx_wake_queue(nq);
1933 /* Refill processing for SW buffer management */
1934 /* Allocate page per descriptor */
1935 static int mvneta_rx_refill(struct mvneta_port *pp,
1936 struct mvneta_rx_desc *rx_desc,
1937 struct mvneta_rx_queue *rxq,
1940 dma_addr_t phys_addr;
1943 page = page_pool_alloc_pages(rxq->page_pool,
1944 gfp_mask | __GFP_NOWARN);
1948 phys_addr = page_pool_get_dma_addr(page) + pp->rx_offset_correction;
1949 mvneta_rx_desc_fill(rx_desc, phys_addr, page, rxq);
1954 /* Handle tx checksum */
1955 static u32 mvneta_skb_tx_csum(struct sk_buff *skb)
1957 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1959 __be16 l3_proto = vlan_get_protocol(skb);
1962 if (l3_proto == htons(ETH_P_IP)) {
1963 struct iphdr *ip4h = ip_hdr(skb);
1965 /* Calculate IPv4 checksum and L4 checksum */
1966 ip_hdr_len = ip4h->ihl;
1967 l4_proto = ip4h->protocol;
1968 } else if (l3_proto == htons(ETH_P_IPV6)) {
1969 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1971 /* Read l4_protocol from one of IPv6 extra headers */
1972 if (skb_network_header_len(skb) > 0)
1973 ip_hdr_len = (skb_network_header_len(skb) >> 2);
1974 l4_proto = ip6h->nexthdr;
1976 return MVNETA_TX_L4_CSUM_NOT;
1978 return mvneta_txq_desc_csum(skb_network_offset(skb),
1979 l3_proto, ip_hdr_len, l4_proto);
1982 return MVNETA_TX_L4_CSUM_NOT;
1985 /* Drop packets received by the RXQ and free buffers */
1986 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
1987 struct mvneta_rx_queue *rxq)
1991 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1993 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1996 for (i = 0; i < rx_done; i++) {
1997 struct mvneta_rx_desc *rx_desc =
1998 mvneta_rxq_next_desc_get(rxq);
1999 u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
2000 struct mvneta_bm_pool *bm_pool;
2002 bm_pool = &pp->bm_priv->bm_pools[pool_id];
2003 /* Return dropped buffer to the pool */
2004 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
2005 rx_desc->buf_phys_addr);
2010 for (i = 0; i < rxq->size; i++) {
2011 struct mvneta_rx_desc *rx_desc = rxq->descs + i;
2012 void *data = rxq->buf_virt_addr[i];
2013 if (!data || !(rx_desc->buf_phys_addr))
2016 page_pool_put_full_page(rxq->page_pool, data, false);
2018 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq))
2019 xdp_rxq_info_unreg(&rxq->xdp_rxq);
2020 page_pool_destroy(rxq->page_pool);
2021 rxq->page_pool = NULL;
2025 mvneta_update_stats(struct mvneta_port *pp,
2026 struct mvneta_stats *ps)
2028 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2030 u64_stats_update_begin(&stats->syncp);
2031 stats->es.ps.rx_packets += ps->rx_packets;
2032 stats->es.ps.rx_bytes += ps->rx_bytes;
2034 stats->es.ps.xdp_redirect += ps->xdp_redirect;
2035 stats->es.ps.xdp_pass += ps->xdp_pass;
2036 stats->es.ps.xdp_drop += ps->xdp_drop;
2037 u64_stats_update_end(&stats->syncp);
2041 int mvneta_rx_refill_queue(struct mvneta_port *pp, struct mvneta_rx_queue *rxq)
2043 struct mvneta_rx_desc *rx_desc;
2044 int curr_desc = rxq->first_to_refill;
2047 for (i = 0; (i < rxq->refill_num) && (i < 64); i++) {
2048 rx_desc = rxq->descs + curr_desc;
2049 if (!(rx_desc->buf_phys_addr)) {
2050 if (mvneta_rx_refill(pp, rx_desc, rxq, GFP_ATOMIC)) {
2051 struct mvneta_pcpu_stats *stats;
2053 pr_err("Can't refill queue %d. Done %d from %d\n",
2054 rxq->id, i, rxq->refill_num);
2056 stats = this_cpu_ptr(pp->stats);
2057 u64_stats_update_begin(&stats->syncp);
2058 stats->es.refill_error++;
2059 u64_stats_update_end(&stats->syncp);
2063 curr_desc = MVNETA_QUEUE_NEXT_DESC(rxq, curr_desc);
2065 rxq->refill_num -= i;
2066 rxq->first_to_refill = curr_desc;
2072 mvneta_xdp_put_buff(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
2073 struct xdp_buff *xdp, int sync_len)
2075 struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp);
2078 if (likely(!xdp_buff_has_frags(xdp)))
2081 for (i = 0; i < sinfo->nr_frags; i++)
2082 page_pool_put_full_page(rxq->page_pool,
2083 skb_frag_page(&sinfo->frags[i]), true);
2086 page_pool_put_page(rxq->page_pool, virt_to_head_page(xdp->data),
2091 mvneta_xdp_submit_frame(struct mvneta_port *pp, struct mvneta_tx_queue *txq,
2092 struct xdp_frame *xdpf, int *nxmit_byte, bool dma_map)
2094 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf);
2095 struct device *dev = pp->dev->dev.parent;
2096 struct mvneta_tx_desc *tx_desc;
2097 int i, num_frames = 1;
2100 if (unlikely(xdp_frame_has_frags(xdpf)))
2101 num_frames += sinfo->nr_frags;
2103 if (txq->count + num_frames >= txq->size)
2104 return MVNETA_XDP_DROPPED;
2106 for (i = 0; i < num_frames; i++) {
2107 struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index];
2108 skb_frag_t *frag = NULL;
2109 int len = xdpf->len;
2110 dma_addr_t dma_addr;
2112 if (unlikely(i)) { /* paged area */
2113 frag = &sinfo->frags[i - 1];
2114 len = skb_frag_size(frag);
2117 tx_desc = mvneta_txq_next_desc_get(txq);
2122 data = unlikely(frag) ? skb_frag_address(frag)
2124 dma_addr = dma_map_single(dev, data, len,
2126 if (dma_mapping_error(dev, dma_addr)) {
2127 mvneta_txq_desc_put(txq);
2131 buf->type = MVNETA_TYPE_XDP_NDO;
2133 page = unlikely(frag) ? skb_frag_page(frag)
2134 : virt_to_page(xdpf->data);
2135 dma_addr = page_pool_get_dma_addr(page);
2137 dma_addr += skb_frag_off(frag);
2139 dma_addr += sizeof(*xdpf) + xdpf->headroom;
2140 dma_sync_single_for_device(dev, dma_addr, len,
2142 buf->type = MVNETA_TYPE_XDP_TX;
2144 buf->xdpf = unlikely(i) ? NULL : xdpf;
2146 tx_desc->command = unlikely(i) ? 0 : MVNETA_TXD_F_DESC;
2147 tx_desc->buf_phys_addr = dma_addr;
2148 tx_desc->data_size = len;
2151 mvneta_txq_inc_put(txq);
2153 /*last descriptor */
2154 tx_desc->command |= MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD;
2156 txq->pending += num_frames;
2157 txq->count += num_frames;
2159 return MVNETA_XDP_TX;
2162 for (i--; i >= 0; i--) {
2163 mvneta_txq_desc_put(txq);
2164 tx_desc = txq->descs + txq->next_desc_to_proc;
2165 dma_unmap_single(dev, tx_desc->buf_phys_addr,
2170 return MVNETA_XDP_DROPPED;
2174 mvneta_xdp_xmit_back(struct mvneta_port *pp, struct xdp_buff *xdp)
2176 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2177 struct mvneta_tx_queue *txq;
2178 struct netdev_queue *nq;
2179 int cpu, nxmit_byte = 0;
2180 struct xdp_frame *xdpf;
2183 xdpf = xdp_convert_buff_to_frame(xdp);
2184 if (unlikely(!xdpf))
2185 return MVNETA_XDP_DROPPED;
2187 cpu = smp_processor_id();
2188 txq = &pp->txqs[cpu % txq_number];
2189 nq = netdev_get_tx_queue(pp->dev, txq->id);
2191 __netif_tx_lock(nq, cpu);
2192 ret = mvneta_xdp_submit_frame(pp, txq, xdpf, &nxmit_byte, false);
2193 if (ret == MVNETA_XDP_TX) {
2194 u64_stats_update_begin(&stats->syncp);
2195 stats->es.ps.tx_bytes += nxmit_byte;
2196 stats->es.ps.tx_packets++;
2197 stats->es.ps.xdp_tx++;
2198 u64_stats_update_end(&stats->syncp);
2200 mvneta_txq_pend_desc_add(pp, txq, 0);
2202 u64_stats_update_begin(&stats->syncp);
2203 stats->es.ps.xdp_tx_err++;
2204 u64_stats_update_end(&stats->syncp);
2206 __netif_tx_unlock(nq);
2212 mvneta_xdp_xmit(struct net_device *dev, int num_frame,
2213 struct xdp_frame **frames, u32 flags)
2215 struct mvneta_port *pp = netdev_priv(dev);
2216 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2217 int i, nxmit_byte = 0, nxmit = 0;
2218 int cpu = smp_processor_id();
2219 struct mvneta_tx_queue *txq;
2220 struct netdev_queue *nq;
2223 if (unlikely(test_bit(__MVNETA_DOWN, &pp->state)))
2226 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
2229 txq = &pp->txqs[cpu % txq_number];
2230 nq = netdev_get_tx_queue(pp->dev, txq->id);
2232 __netif_tx_lock(nq, cpu);
2233 for (i = 0; i < num_frame; i++) {
2234 ret = mvneta_xdp_submit_frame(pp, txq, frames[i], &nxmit_byte,
2236 if (ret != MVNETA_XDP_TX)
2242 if (unlikely(flags & XDP_XMIT_FLUSH))
2243 mvneta_txq_pend_desc_add(pp, txq, 0);
2244 __netif_tx_unlock(nq);
2246 u64_stats_update_begin(&stats->syncp);
2247 stats->es.ps.tx_bytes += nxmit_byte;
2248 stats->es.ps.tx_packets += nxmit;
2249 stats->es.ps.xdp_xmit += nxmit;
2250 stats->es.ps.xdp_xmit_err += num_frame - nxmit;
2251 u64_stats_update_end(&stats->syncp);
2257 mvneta_run_xdp(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
2258 struct bpf_prog *prog, struct xdp_buff *xdp,
2259 u32 frame_sz, struct mvneta_stats *stats)
2261 unsigned int len, data_len, sync;
2264 len = xdp->data_end - xdp->data_hard_start - pp->rx_offset_correction;
2265 data_len = xdp->data_end - xdp->data;
2266 act = bpf_prog_run_xdp(prog, xdp);
2268 /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */
2269 sync = xdp->data_end - xdp->data_hard_start - pp->rx_offset_correction;
2270 sync = max(sync, len);
2275 return MVNETA_XDP_PASS;
2276 case XDP_REDIRECT: {
2279 err = xdp_do_redirect(pp->dev, xdp, prog);
2280 if (unlikely(err)) {
2281 mvneta_xdp_put_buff(pp, rxq, xdp, sync);
2282 ret = MVNETA_XDP_DROPPED;
2284 ret = MVNETA_XDP_REDIR;
2285 stats->xdp_redirect++;
2290 ret = mvneta_xdp_xmit_back(pp, xdp);
2291 if (ret != MVNETA_XDP_TX)
2292 mvneta_xdp_put_buff(pp, rxq, xdp, sync);
2295 bpf_warn_invalid_xdp_action(pp->dev, prog, act);
2298 trace_xdp_exception(pp->dev, prog, act);
2301 mvneta_xdp_put_buff(pp, rxq, xdp, sync);
2302 ret = MVNETA_XDP_DROPPED;
2307 stats->rx_bytes += frame_sz + xdp->data_end - xdp->data - data_len;
2308 stats->rx_packets++;
2314 mvneta_swbm_rx_frame(struct mvneta_port *pp,
2315 struct mvneta_rx_desc *rx_desc,
2316 struct mvneta_rx_queue *rxq,
2317 struct xdp_buff *xdp, int *size,
2320 unsigned char *data = page_address(page);
2321 int data_len = -MVNETA_MH_SIZE, len;
2322 struct net_device *dev = pp->dev;
2323 enum dma_data_direction dma_dir;
2325 if (*size > MVNETA_MAX_RX_BUF_SIZE) {
2326 len = MVNETA_MAX_RX_BUF_SIZE;
2330 data_len += len - ETH_FCS_LEN;
2332 *size = *size - len;
2334 dma_dir = page_pool_get_dma_dir(rxq->page_pool);
2335 dma_sync_single_for_cpu(dev->dev.parent,
2336 rx_desc->buf_phys_addr,
2339 rx_desc->buf_phys_addr = 0;
2341 /* Prefetch header */
2343 xdp_buff_clear_frags_flag(xdp);
2344 xdp_prepare_buff(xdp, data, pp->rx_offset_correction + MVNETA_MH_SIZE,
2349 mvneta_swbm_add_rx_fragment(struct mvneta_port *pp,
2350 struct mvneta_rx_desc *rx_desc,
2351 struct mvneta_rx_queue *rxq,
2352 struct xdp_buff *xdp, int *size,
2355 struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp);
2356 struct net_device *dev = pp->dev;
2357 enum dma_data_direction dma_dir;
2360 if (*size > MVNETA_MAX_RX_BUF_SIZE) {
2361 len = MVNETA_MAX_RX_BUF_SIZE;
2365 data_len = len - ETH_FCS_LEN;
2367 dma_dir = page_pool_get_dma_dir(rxq->page_pool);
2368 dma_sync_single_for_cpu(dev->dev.parent,
2369 rx_desc->buf_phys_addr,
2371 rx_desc->buf_phys_addr = 0;
2373 if (!xdp_buff_has_frags(xdp))
2374 sinfo->nr_frags = 0;
2376 if (data_len > 0 && sinfo->nr_frags < MAX_SKB_FRAGS) {
2377 skb_frag_t *frag = &sinfo->frags[sinfo->nr_frags++];
2379 skb_frag_fill_page_desc(frag, page,
2380 pp->rx_offset_correction, data_len);
2382 if (!xdp_buff_has_frags(xdp)) {
2383 sinfo->xdp_frags_size = *size;
2384 xdp_buff_set_frags_flag(xdp);
2386 if (page_is_pfmemalloc(page))
2387 xdp_buff_set_frag_pfmemalloc(xdp);
2389 page_pool_put_full_page(rxq->page_pool, page, true);
2394 static struct sk_buff *
2395 mvneta_swbm_build_skb(struct mvneta_port *pp, struct page_pool *pool,
2396 struct xdp_buff *xdp, u32 desc_status)
2398 struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp);
2399 struct sk_buff *skb;
2402 if (unlikely(xdp_buff_has_frags(xdp)))
2403 num_frags = sinfo->nr_frags;
2405 skb = build_skb(xdp->data_hard_start, PAGE_SIZE);
2407 return ERR_PTR(-ENOMEM);
2409 skb_mark_for_recycle(skb);
2411 skb_reserve(skb, xdp->data - xdp->data_hard_start);
2412 skb_put(skb, xdp->data_end - xdp->data);
2413 skb->ip_summed = mvneta_rx_csum(pp, desc_status);
2415 if (unlikely(xdp_buff_has_frags(xdp)))
2416 xdp_update_skb_shared_info(skb, num_frags,
2417 sinfo->xdp_frags_size,
2418 num_frags * xdp->frame_sz,
2419 xdp_buff_is_frag_pfmemalloc(xdp));
2424 /* Main rx processing when using software buffer management */
2425 static int mvneta_rx_swbm(struct napi_struct *napi,
2426 struct mvneta_port *pp, int budget,
2427 struct mvneta_rx_queue *rxq)
2429 int rx_proc = 0, rx_todo, refill, size = 0;
2430 struct net_device *dev = pp->dev;
2431 struct mvneta_stats ps = {};
2432 struct bpf_prog *xdp_prog;
2433 u32 desc_status, frame_sz;
2434 struct xdp_buff xdp_buf;
2436 xdp_init_buff(&xdp_buf, PAGE_SIZE, &rxq->xdp_rxq);
2437 xdp_buf.data_hard_start = NULL;
2439 /* Get number of received packets */
2440 rx_todo = mvneta_rxq_busy_desc_num_get(pp, rxq);
2442 xdp_prog = READ_ONCE(pp->xdp_prog);
2444 /* Fairness NAPI loop */
2445 while (rx_proc < budget && rx_proc < rx_todo) {
2446 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
2447 u32 rx_status, index;
2448 struct sk_buff *skb;
2451 index = rx_desc - rxq->descs;
2452 page = (struct page *)rxq->buf_virt_addr[index];
2454 rx_status = rx_desc->status;
2458 if (rx_status & MVNETA_RXD_FIRST_DESC) {
2459 /* Check errors only for FIRST descriptor */
2460 if (rx_status & MVNETA_RXD_ERR_SUMMARY) {
2461 mvneta_rx_error(pp, rx_desc);
2465 size = rx_desc->data_size;
2466 frame_sz = size - ETH_FCS_LEN;
2467 desc_status = rx_status;
2469 mvneta_swbm_rx_frame(pp, rx_desc, rxq, &xdp_buf,
2472 if (unlikely(!xdp_buf.data_hard_start)) {
2473 rx_desc->buf_phys_addr = 0;
2474 page_pool_put_full_page(rxq->page_pool, page,
2479 mvneta_swbm_add_rx_fragment(pp, rx_desc, rxq, &xdp_buf,
2481 } /* Middle or Last descriptor */
2483 if (!(rx_status & MVNETA_RXD_LAST_DESC))
2484 /* no last descriptor this time */
2488 mvneta_xdp_put_buff(pp, rxq, &xdp_buf, -1);
2493 mvneta_run_xdp(pp, rxq, xdp_prog, &xdp_buf, frame_sz, &ps))
2496 skb = mvneta_swbm_build_skb(pp, rxq->page_pool, &xdp_buf, desc_status);
2498 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2500 mvneta_xdp_put_buff(pp, rxq, &xdp_buf, -1);
2502 u64_stats_update_begin(&stats->syncp);
2503 stats->es.skb_alloc_error++;
2504 stats->rx_dropped++;
2505 u64_stats_update_end(&stats->syncp);
2510 ps.rx_bytes += skb->len;
2513 skb->protocol = eth_type_trans(skb, dev);
2514 napi_gro_receive(napi, skb);
2516 xdp_buf.data_hard_start = NULL;
2519 if (xdp_buf.data_hard_start)
2520 mvneta_xdp_put_buff(pp, rxq, &xdp_buf, -1);
2522 if (ps.xdp_redirect)
2526 mvneta_update_stats(pp, &ps);
2528 /* return some buffers to hardware queue, one at a time is too slow */
2529 refill = mvneta_rx_refill_queue(pp, rxq);
2531 /* Update rxq management counters */
2532 mvneta_rxq_desc_num_update(pp, rxq, rx_proc, refill);
2534 return ps.rx_packets;
2537 /* Main rx processing when using hardware buffer management */
2538 static int mvneta_rx_hwbm(struct napi_struct *napi,
2539 struct mvneta_port *pp, int rx_todo,
2540 struct mvneta_rx_queue *rxq)
2542 struct net_device *dev = pp->dev;
2547 /* Get number of received packets */
2548 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
2550 if (rx_todo > rx_done)
2555 /* Fairness NAPI loop */
2556 while (rx_done < rx_todo) {
2557 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
2558 struct mvneta_bm_pool *bm_pool = NULL;
2559 struct sk_buff *skb;
2560 unsigned char *data;
2561 dma_addr_t phys_addr;
2562 u32 rx_status, frag_size;
2567 rx_status = rx_desc->status;
2568 rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
2569 data = (u8 *)(uintptr_t)rx_desc->buf_cookie;
2570 phys_addr = rx_desc->buf_phys_addr;
2571 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
2572 bm_pool = &pp->bm_priv->bm_pools[pool_id];
2574 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
2575 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
2576 err_drop_frame_ret_pool:
2577 /* Return the buffer to the pool */
2578 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
2579 rx_desc->buf_phys_addr);
2581 mvneta_rx_error(pp, rx_desc);
2582 /* leave the descriptor untouched */
2586 if (rx_bytes <= rx_copybreak) {
2587 /* better copy a small frame and not unmap the DMA region */
2588 skb = netdev_alloc_skb_ip_align(dev, rx_bytes);
2590 goto err_drop_frame_ret_pool;
2592 dma_sync_single_range_for_cpu(&pp->bm_priv->pdev->dev,
2593 rx_desc->buf_phys_addr,
2594 MVNETA_MH_SIZE + NET_SKB_PAD,
2597 skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD,
2600 skb->protocol = eth_type_trans(skb, dev);
2601 skb->ip_summed = mvneta_rx_csum(pp, rx_status);
2602 napi_gro_receive(napi, skb);
2605 rcvd_bytes += rx_bytes;
2607 /* Return the buffer to the pool */
2608 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
2609 rx_desc->buf_phys_addr);
2611 /* leave the descriptor and buffer untouched */
2615 /* Refill processing */
2616 err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC);
2618 struct mvneta_pcpu_stats *stats;
2620 netdev_err(dev, "Linux processing - Can't refill\n");
2622 stats = this_cpu_ptr(pp->stats);
2623 u64_stats_update_begin(&stats->syncp);
2624 stats->es.refill_error++;
2625 u64_stats_update_end(&stats->syncp);
2627 goto err_drop_frame_ret_pool;
2630 frag_size = bm_pool->hwbm_pool.frag_size;
2632 skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size);
2634 /* After refill old buffer has to be unmapped regardless
2635 * the skb is successfully built or not.
2637 dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr,
2638 bm_pool->buf_size, DMA_FROM_DEVICE);
2640 goto err_drop_frame;
2643 rcvd_bytes += rx_bytes;
2645 /* Linux processing */
2646 skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD);
2647 skb_put(skb, rx_bytes);
2649 skb->protocol = eth_type_trans(skb, dev);
2650 skb->ip_summed = mvneta_rx_csum(pp, rx_status);
2652 napi_gro_receive(napi, skb);
2656 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2658 u64_stats_update_begin(&stats->syncp);
2659 stats->es.ps.rx_packets += rcvd_pkts;
2660 stats->es.ps.rx_bytes += rcvd_bytes;
2661 u64_stats_update_end(&stats->syncp);
2664 /* Update rxq management counters */
2665 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
2670 static void mvneta_free_tso_hdrs(struct mvneta_port *pp,
2671 struct mvneta_tx_queue *txq)
2673 struct device *dev = pp->dev->dev.parent;
2676 for (i = 0; i < MVNETA_MAX_TSO_PAGES; i++) {
2677 if (txq->tso_hdrs[i]) {
2678 dma_free_coherent(dev, MVNETA_TSO_PAGE_SIZE,
2680 txq->tso_hdrs_phys[i]);
2681 txq->tso_hdrs[i] = NULL;
2686 static int mvneta_alloc_tso_hdrs(struct mvneta_port *pp,
2687 struct mvneta_tx_queue *txq)
2689 struct device *dev = pp->dev->dev.parent;
2692 num = DIV_ROUND_UP(txq->size, MVNETA_TSO_PER_PAGE);
2693 for (i = 0; i < num; i++) {
2694 txq->tso_hdrs[i] = dma_alloc_coherent(dev, MVNETA_TSO_PAGE_SIZE,
2695 &txq->tso_hdrs_phys[i],
2697 if (!txq->tso_hdrs[i]) {
2698 mvneta_free_tso_hdrs(pp, txq);
2706 static char *mvneta_get_tso_hdr(struct mvneta_tx_queue *txq, dma_addr_t *dma)
2710 index = txq->txq_put_index / MVNETA_TSO_PER_PAGE;
2711 offset = (txq->txq_put_index % MVNETA_TSO_PER_PAGE) * TSO_HEADER_SIZE;
2713 *dma = txq->tso_hdrs_phys[index] + offset;
2715 return txq->tso_hdrs[index] + offset;
2718 static void mvneta_tso_put_hdr(struct sk_buff *skb, struct mvneta_tx_queue *txq,
2719 struct tso_t *tso, int size, bool is_last)
2721 struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index];
2722 int hdr_len = skb_tcp_all_headers(skb);
2723 struct mvneta_tx_desc *tx_desc;
2724 dma_addr_t hdr_phys;
2727 hdr = mvneta_get_tso_hdr(txq, &hdr_phys);
2728 tso_build_hdr(skb, hdr, tso, size, is_last);
2730 tx_desc = mvneta_txq_next_desc_get(txq);
2731 tx_desc->data_size = hdr_len;
2732 tx_desc->command = mvneta_skb_tx_csum(skb);
2733 tx_desc->command |= MVNETA_TXD_F_DESC;
2734 tx_desc->buf_phys_addr = hdr_phys;
2735 buf->type = MVNETA_TYPE_TSO;
2738 mvneta_txq_inc_put(txq);
2742 mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq,
2743 struct sk_buff *skb, char *data, int size,
2744 bool last_tcp, bool is_last)
2746 struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index];
2747 struct mvneta_tx_desc *tx_desc;
2749 tx_desc = mvneta_txq_next_desc_get(txq);
2750 tx_desc->data_size = size;
2751 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data,
2752 size, DMA_TO_DEVICE);
2753 if (unlikely(dma_mapping_error(dev->dev.parent,
2754 tx_desc->buf_phys_addr))) {
2755 mvneta_txq_desc_put(txq);
2759 tx_desc->command = 0;
2760 buf->type = MVNETA_TYPE_SKB;
2764 /* last descriptor in the TCP packet */
2765 tx_desc->command = MVNETA_TXD_L_DESC;
2767 /* last descriptor in SKB */
2771 mvneta_txq_inc_put(txq);
2775 static void mvneta_release_descs(struct mvneta_port *pp,
2776 struct mvneta_tx_queue *txq,
2781 desc_idx = first + num;
2782 if (desc_idx >= txq->size)
2783 desc_idx -= txq->size;
2785 for (i = num; i >= 0; i--) {
2786 struct mvneta_tx_desc *tx_desc = txq->descs + desc_idx;
2787 struct mvneta_tx_buf *buf = &txq->buf[desc_idx];
2789 if (buf->type == MVNETA_TYPE_SKB)
2790 dma_unmap_single(pp->dev->dev.parent,
2791 tx_desc->buf_phys_addr,
2795 mvneta_txq_desc_put(txq);
2798 desc_idx = txq->size;
2803 static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev,
2804 struct mvneta_tx_queue *txq)
2806 int hdr_len, total_len, data_left;
2807 int first_desc, desc_count = 0;
2808 struct mvneta_port *pp = netdev_priv(dev);
2811 /* Count needed descriptors */
2812 if ((txq->count + tso_count_descs(skb)) >= txq->size)
2815 if (skb_headlen(skb) < skb_tcp_all_headers(skb)) {
2816 pr_info("*** Is this even possible?\n");
2820 first_desc = txq->txq_put_index;
2822 /* Initialize the TSO handler, and prepare the first payload */
2823 hdr_len = tso_start(skb, &tso);
2825 total_len = skb->len - hdr_len;
2826 while (total_len > 0) {
2827 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
2828 total_len -= data_left;
2831 /* prepare packet headers: MAC + IP + TCP */
2832 mvneta_tso_put_hdr(skb, txq, &tso, data_left, total_len == 0);
2834 while (data_left > 0) {
2838 size = min_t(int, tso.size, data_left);
2840 if (mvneta_tso_put_data(dev, txq, skb,
2847 tso_build_data(skb, &tso, size);
2854 /* Release all used data descriptors; header descriptors must not
2857 mvneta_release_descs(pp, txq, first_desc, desc_count - 1);
2861 /* Handle tx fragmentation processing */
2862 static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb,
2863 struct mvneta_tx_queue *txq)
2865 struct mvneta_tx_desc *tx_desc;
2866 int i, nr_frags = skb_shinfo(skb)->nr_frags;
2867 int first_desc = txq->txq_put_index;
2869 for (i = 0; i < nr_frags; i++) {
2870 struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index];
2871 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2872 void *addr = skb_frag_address(frag);
2874 tx_desc = mvneta_txq_next_desc_get(txq);
2875 tx_desc->data_size = skb_frag_size(frag);
2877 tx_desc->buf_phys_addr =
2878 dma_map_single(pp->dev->dev.parent, addr,
2879 tx_desc->data_size, DMA_TO_DEVICE);
2881 if (dma_mapping_error(pp->dev->dev.parent,
2882 tx_desc->buf_phys_addr)) {
2883 mvneta_txq_desc_put(txq);
2887 if (i == nr_frags - 1) {
2888 /* Last descriptor */
2889 tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD;
2892 /* Descriptor in the middle: Not First, Not Last */
2893 tx_desc->command = 0;
2896 buf->type = MVNETA_TYPE_SKB;
2897 mvneta_txq_inc_put(txq);
2903 /* Release all descriptors that were used to map fragments of
2904 * this packet, as well as the corresponding DMA mappings
2906 mvneta_release_descs(pp, txq, first_desc, i - 1);
2910 /* Main tx processing */
2911 static netdev_tx_t mvneta_tx(struct sk_buff *skb, struct net_device *dev)
2913 struct mvneta_port *pp = netdev_priv(dev);
2914 u16 txq_id = skb_get_queue_mapping(skb);
2915 struct mvneta_tx_queue *txq = &pp->txqs[txq_id];
2916 struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index];
2917 struct mvneta_tx_desc *tx_desc;
2922 if (!netif_running(dev))
2925 if (skb_is_gso(skb)) {
2926 frags = mvneta_tx_tso(skb, dev, txq);
2930 frags = skb_shinfo(skb)->nr_frags + 1;
2932 /* Get a descriptor for the first part of the packet */
2933 tx_desc = mvneta_txq_next_desc_get(txq);
2935 tx_cmd = mvneta_skb_tx_csum(skb);
2937 tx_desc->data_size = skb_headlen(skb);
2939 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data,
2942 if (unlikely(dma_mapping_error(dev->dev.parent,
2943 tx_desc->buf_phys_addr))) {
2944 mvneta_txq_desc_put(txq);
2949 buf->type = MVNETA_TYPE_SKB;
2951 /* First and Last descriptor */
2952 tx_cmd |= MVNETA_TXD_FLZ_DESC;
2953 tx_desc->command = tx_cmd;
2955 mvneta_txq_inc_put(txq);
2957 /* First but not Last */
2958 tx_cmd |= MVNETA_TXD_F_DESC;
2960 mvneta_txq_inc_put(txq);
2961 tx_desc->command = tx_cmd;
2962 /* Continue with other skb fragments */
2963 if (mvneta_tx_frag_process(pp, skb, txq)) {
2964 dma_unmap_single(dev->dev.parent,
2965 tx_desc->buf_phys_addr,
2968 mvneta_txq_desc_put(txq);
2976 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
2977 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2979 netdev_tx_sent_queue(nq, len);
2981 txq->count += frags;
2982 if (txq->count >= txq->tx_stop_threshold)
2983 netif_tx_stop_queue(nq);
2985 if (!netdev_xmit_more() || netif_xmit_stopped(nq) ||
2986 txq->pending + frags > MVNETA_TXQ_DEC_SENT_MASK)
2987 mvneta_txq_pend_desc_add(pp, txq, frags);
2989 txq->pending += frags;
2991 u64_stats_update_begin(&stats->syncp);
2992 stats->es.ps.tx_bytes += len;
2993 stats->es.ps.tx_packets++;
2994 u64_stats_update_end(&stats->syncp);
2996 dev->stats.tx_dropped++;
2997 dev_kfree_skb_any(skb);
3000 return NETDEV_TX_OK;
3004 /* Free tx resources, when resetting a port */
3005 static void mvneta_txq_done_force(struct mvneta_port *pp,
3006 struct mvneta_tx_queue *txq)
3009 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
3010 int tx_done = txq->count;
3012 mvneta_txq_bufs_free(pp, txq, tx_done, nq, false);
3016 txq->txq_put_index = 0;
3017 txq->txq_get_index = 0;
3020 /* Handle tx done - called in softirq context. The <cause_tx_done> argument
3021 * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL.
3023 static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done)
3025 struct mvneta_tx_queue *txq;
3026 struct netdev_queue *nq;
3027 int cpu = smp_processor_id();
3029 while (cause_tx_done) {
3030 txq = mvneta_tx_done_policy(pp, cause_tx_done);
3032 nq = netdev_get_tx_queue(pp->dev, txq->id);
3033 __netif_tx_lock(nq, cpu);
3036 mvneta_txq_done(pp, txq);
3038 __netif_tx_unlock(nq);
3039 cause_tx_done &= ~((1 << txq->id));
3043 /* Compute crc8 of the specified address, using a unique algorithm ,
3044 * according to hw spec, different than generic crc8 algorithm
3046 static int mvneta_addr_crc(unsigned char *addr)
3051 for (i = 0; i < ETH_ALEN; i++) {
3054 crc = (crc ^ addr[i]) << 8;
3055 for (j = 7; j >= 0; j--) {
3056 if (crc & (0x100 << j))
3064 /* This method controls the net device special MAC multicast support.
3065 * The Special Multicast Table for MAC addresses supports MAC of the form
3066 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
3067 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
3068 * Table entries in the DA-Filter table. This method set the Special
3069 * Multicast Table appropriate entry.
3071 static void mvneta_set_special_mcast_addr(struct mvneta_port *pp,
3072 unsigned char last_byte,
3075 unsigned int smc_table_reg;
3076 unsigned int tbl_offset;
3077 unsigned int reg_offset;
3079 /* Register offset from SMC table base */
3080 tbl_offset = (last_byte / 4);
3081 /* Entry offset within the above reg */
3082 reg_offset = last_byte % 4;
3084 smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST
3088 smc_table_reg &= ~(0xff << (8 * reg_offset));
3090 smc_table_reg &= ~(0xff << (8 * reg_offset));
3091 smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
3094 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4,
3098 /* This method controls the network device Other MAC multicast support.
3099 * The Other Multicast Table is used for multicast of another type.
3100 * A CRC-8 is used as an index to the Other Multicast Table entries
3101 * in the DA-Filter table.
3102 * The method gets the CRC-8 value from the calling routine and
3103 * sets the Other Multicast Table appropriate entry according to the
3106 static void mvneta_set_other_mcast_addr(struct mvneta_port *pp,
3110 unsigned int omc_table_reg;
3111 unsigned int tbl_offset;
3112 unsigned int reg_offset;
3114 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
3115 reg_offset = crc8 % 4; /* Entry offset within the above reg */
3117 omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset);
3120 /* Clear accepts frame bit at specified Other DA table entry */
3121 omc_table_reg &= ~(0xff << (8 * reg_offset));
3123 omc_table_reg &= ~(0xff << (8 * reg_offset));
3124 omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
3127 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg);
3130 /* The network device supports multicast using two tables:
3131 * 1) Special Multicast Table for MAC addresses of the form
3132 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
3133 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
3134 * Table entries in the DA-Filter table.
3135 * 2) Other Multicast Table for multicast of another type. A CRC-8 value
3136 * is used as an index to the Other Multicast Table entries in the
3139 static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr,
3142 unsigned char crc_result = 0;
3144 if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) {
3145 mvneta_set_special_mcast_addr(pp, p_addr[5], queue);
3149 crc_result = mvneta_addr_crc(p_addr);
3151 if (pp->mcast_count[crc_result] == 0) {
3152 netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n",
3157 pp->mcast_count[crc_result]--;
3158 if (pp->mcast_count[crc_result] != 0) {
3159 netdev_info(pp->dev,
3160 "After delete there are %d valid Mcast for crc8=0x%02x\n",
3161 pp->mcast_count[crc_result], crc_result);
3165 pp->mcast_count[crc_result]++;
3167 mvneta_set_other_mcast_addr(pp, crc_result, queue);
3172 /* Configure Fitering mode of Ethernet port */
3173 static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp,
3176 u32 port_cfg_reg, val;
3178 port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG);
3180 val = mvreg_read(pp, MVNETA_TYPE_PRIO);
3182 /* Set / Clear UPM bit in port configuration register */
3184 /* Accept all Unicast addresses */
3185 port_cfg_reg |= MVNETA_UNI_PROMISC_MODE;
3186 val |= MVNETA_FORCE_UNI;
3187 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff);
3188 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff);
3190 /* Reject all Unicast addresses */
3191 port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE;
3192 val &= ~MVNETA_FORCE_UNI;
3195 mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg);
3196 mvreg_write(pp, MVNETA_TYPE_PRIO, val);
3199 /* register unicast and multicast addresses */
3200 static void mvneta_set_rx_mode(struct net_device *dev)
3202 struct mvneta_port *pp = netdev_priv(dev);
3203 struct netdev_hw_addr *ha;
3205 if (dev->flags & IFF_PROMISC) {
3206 /* Accept all: Multicast + Unicast */
3207 mvneta_rx_unicast_promisc_set(pp, 1);
3208 mvneta_set_ucast_table(pp, pp->rxq_def);
3209 mvneta_set_special_mcast_table(pp, pp->rxq_def);
3210 mvneta_set_other_mcast_table(pp, pp->rxq_def);
3212 /* Accept single Unicast */
3213 mvneta_rx_unicast_promisc_set(pp, 0);
3214 mvneta_set_ucast_table(pp, -1);
3215 mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def);
3217 if (dev->flags & IFF_ALLMULTI) {
3218 /* Accept all multicast */
3219 mvneta_set_special_mcast_table(pp, pp->rxq_def);
3220 mvneta_set_other_mcast_table(pp, pp->rxq_def);
3222 /* Accept only initialized multicast */
3223 mvneta_set_special_mcast_table(pp, -1);
3224 mvneta_set_other_mcast_table(pp, -1);
3226 if (!netdev_mc_empty(dev)) {
3227 netdev_for_each_mc_addr(ha, dev) {
3228 mvneta_mcast_addr_set(pp, ha->addr,
3236 /* Interrupt handling - the callback for request_irq() */
3237 static irqreturn_t mvneta_isr(int irq, void *dev_id)
3239 struct mvneta_port *pp = (struct mvneta_port *)dev_id;
3241 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
3242 napi_schedule(&pp->napi);
3247 /* Interrupt handling - the callback for request_percpu_irq() */
3248 static irqreturn_t mvneta_percpu_isr(int irq, void *dev_id)
3250 struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id;
3252 disable_percpu_irq(port->pp->dev->irq);
3253 napi_schedule(&port->napi);
3258 static void mvneta_link_change(struct mvneta_port *pp)
3260 u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
3262 phylink_mac_change(pp->phylink, !!(gmac_stat & MVNETA_GMAC_LINK_UP));
3266 * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
3267 * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
3268 * Bits 8 -15 of the cause Rx Tx register indicate that are received
3269 * packets on the corresponding RXQ (Bit 8 is for RX queue 0).
3270 * Each CPU has its own causeRxTx register
3272 static int mvneta_poll(struct napi_struct *napi, int budget)
3277 struct mvneta_port *pp = netdev_priv(napi->dev);
3278 struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
3280 if (!netif_running(pp->dev)) {
3281 napi_complete(napi);
3285 /* Read cause register */
3286 cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE);
3287 if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) {
3288 u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE);
3290 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
3292 if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE |
3293 MVNETA_CAUSE_LINK_CHANGE))
3294 mvneta_link_change(pp);
3297 /* Release Tx descriptors */
3298 if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) {
3299 mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL));
3300 cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL;
3303 /* For the case where the last mvneta_poll did not process all
3306 cause_rx_tx |= pp->neta_armada3700 ? pp->cause_rx_tx :
3309 rx_queue = fls(((cause_rx_tx >> 8) & 0xff));
3311 rx_queue = rx_queue - 1;
3313 rx_done = mvneta_rx_hwbm(napi, pp, budget,
3314 &pp->rxqs[rx_queue]);
3316 rx_done = mvneta_rx_swbm(napi, pp, budget,
3317 &pp->rxqs[rx_queue]);
3320 if (rx_done < budget) {
3322 napi_complete_done(napi, rx_done);
3324 if (pp->neta_armada3700) {
3325 unsigned long flags;
3327 local_irq_save(flags);
3328 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
3329 MVNETA_RX_INTR_MASK(rxq_number) |
3330 MVNETA_TX_INTR_MASK(txq_number) |
3331 MVNETA_MISCINTR_INTR_MASK);
3332 local_irq_restore(flags);
3334 enable_percpu_irq(pp->dev->irq, 0);
3338 if (pp->neta_armada3700)
3339 pp->cause_rx_tx = cause_rx_tx;
3341 port->cause_rx_tx = cause_rx_tx;
3346 static int mvneta_create_page_pool(struct mvneta_port *pp,
3347 struct mvneta_rx_queue *rxq, int size)
3349 struct bpf_prog *xdp_prog = READ_ONCE(pp->xdp_prog);
3350 struct page_pool_params pp_params = {
3352 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
3354 .nid = NUMA_NO_NODE,
3355 .dev = pp->dev->dev.parent,
3356 .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE,
3357 .offset = pp->rx_offset_correction,
3358 .max_len = MVNETA_MAX_RX_BUF_SIZE,
3362 rxq->page_pool = page_pool_create(&pp_params);
3363 if (IS_ERR(rxq->page_pool)) {
3364 err = PTR_ERR(rxq->page_pool);
3365 rxq->page_pool = NULL;
3369 err = __xdp_rxq_info_reg(&rxq->xdp_rxq, pp->dev, rxq->id, 0,
3374 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL,
3377 goto err_unregister_rxq;
3382 xdp_rxq_info_unreg(&rxq->xdp_rxq);
3384 page_pool_destroy(rxq->page_pool);
3385 rxq->page_pool = NULL;
3389 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
3390 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
3395 err = mvneta_create_page_pool(pp, rxq, num);
3399 for (i = 0; i < num; i++) {
3400 memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc));
3401 if (mvneta_rx_refill(pp, rxq->descs + i, rxq,
3404 "%s:rxq %d, %d of %d buffs filled\n",
3405 __func__, rxq->id, i, num);
3410 /* Add this number of RX descriptors as non occupied (ready to
3413 mvneta_rxq_non_occup_desc_add(pp, rxq, i);
3418 /* Free all packets pending transmit from all TXQs and reset TX port */
3419 static void mvneta_tx_reset(struct mvneta_port *pp)
3423 /* free the skb's in the tx ring */
3424 for (queue = 0; queue < txq_number; queue++)
3425 mvneta_txq_done_force(pp, &pp->txqs[queue]);
3427 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
3428 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
3431 static void mvneta_rx_reset(struct mvneta_port *pp)
3433 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
3434 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
3437 /* Rx/Tx queue initialization/cleanup methods */
3439 static int mvneta_rxq_sw_init(struct mvneta_port *pp,
3440 struct mvneta_rx_queue *rxq)
3442 rxq->size = pp->rx_ring_size;
3444 /* Allocate memory for RX descriptors */
3445 rxq->descs = dma_alloc_coherent(pp->dev->dev.parent,
3446 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
3447 &rxq->descs_phys, GFP_KERNEL);
3451 rxq->last_desc = rxq->size - 1;
3456 static void mvneta_rxq_hw_init(struct mvneta_port *pp,
3457 struct mvneta_rx_queue *rxq)
3459 /* Set Rx descriptors queue starting address */
3460 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
3461 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
3463 /* Set coalescing pkts and time */
3464 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
3465 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
3469 mvneta_rxq_offset_set(pp, rxq, 0);
3470 mvneta_rxq_buf_size_set(pp, rxq, PAGE_SIZE < SZ_64K ?
3471 MVNETA_MAX_RX_BUF_SIZE :
3472 MVNETA_RX_BUF_SIZE(pp->pkt_size));
3473 mvneta_rxq_bm_disable(pp, rxq);
3474 mvneta_rxq_fill(pp, rxq, rxq->size);
3477 mvneta_rxq_offset_set(pp, rxq,
3478 NET_SKB_PAD - pp->rx_offset_correction);
3480 mvneta_rxq_bm_enable(pp, rxq);
3481 /* Fill RXQ with buffers from RX pool */
3482 mvneta_rxq_long_pool_set(pp, rxq);
3483 mvneta_rxq_short_pool_set(pp, rxq);
3484 mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size);
3488 /* Create a specified RX queue */
3489 static int mvneta_rxq_init(struct mvneta_port *pp,
3490 struct mvneta_rx_queue *rxq)
3495 ret = mvneta_rxq_sw_init(pp, rxq);
3499 mvneta_rxq_hw_init(pp, rxq);
3504 /* Cleanup Rx queue */
3505 static void mvneta_rxq_deinit(struct mvneta_port *pp,
3506 struct mvneta_rx_queue *rxq)
3508 mvneta_rxq_drop_pkts(pp, rxq);
3511 dma_free_coherent(pp->dev->dev.parent,
3512 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
3518 rxq->next_desc_to_proc = 0;
3519 rxq->descs_phys = 0;
3520 rxq->first_to_refill = 0;
3521 rxq->refill_num = 0;
3524 static int mvneta_txq_sw_init(struct mvneta_port *pp,
3525 struct mvneta_tx_queue *txq)
3529 txq->size = pp->tx_ring_size;
3531 /* A queue must always have room for at least one skb.
3532 * Therefore, stop the queue when the free entries reaches
3533 * the maximum number of descriptors per skb.
3535 txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS;
3536 txq->tx_wake_threshold = txq->tx_stop_threshold / 2;
3538 /* Allocate memory for TX descriptors */
3539 txq->descs = dma_alloc_coherent(pp->dev->dev.parent,
3540 txq->size * MVNETA_DESC_ALIGNED_SIZE,
3541 &txq->descs_phys, GFP_KERNEL);
3545 txq->last_desc = txq->size - 1;
3547 txq->buf = kmalloc_array(txq->size, sizeof(*txq->buf), GFP_KERNEL);
3551 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
3552 err = mvneta_alloc_tso_hdrs(pp, txq);
3556 /* Setup XPS mapping */
3557 if (pp->neta_armada3700)
3559 else if (txq_number > 1)
3560 cpu = txq->id % num_present_cpus();
3562 cpu = pp->rxq_def % num_present_cpus();
3563 cpumask_set_cpu(cpu, &txq->affinity_mask);
3564 netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id);
3569 static void mvneta_txq_hw_init(struct mvneta_port *pp,
3570 struct mvneta_tx_queue *txq)
3572 /* Set maximum bandwidth for enabled TXQs */
3573 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
3574 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
3576 /* Set Tx descriptors queue starting address */
3577 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
3578 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
3580 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
3583 /* Create and initialize a tx queue */
3584 static int mvneta_txq_init(struct mvneta_port *pp,
3585 struct mvneta_tx_queue *txq)
3589 ret = mvneta_txq_sw_init(pp, txq);
3593 mvneta_txq_hw_init(pp, txq);
3598 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
3599 static void mvneta_txq_sw_deinit(struct mvneta_port *pp,
3600 struct mvneta_tx_queue *txq)
3602 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
3606 mvneta_free_tso_hdrs(pp, txq);
3608 dma_free_coherent(pp->dev->dev.parent,
3609 txq->size * MVNETA_DESC_ALIGNED_SIZE,
3610 txq->descs, txq->descs_phys);
3612 netdev_tx_reset_queue(nq);
3617 txq->next_desc_to_proc = 0;
3618 txq->descs_phys = 0;
3621 static void mvneta_txq_hw_deinit(struct mvneta_port *pp,
3622 struct mvneta_tx_queue *txq)
3624 /* Set minimum bandwidth for disabled TXQs */
3625 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
3626 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
3628 /* Set Tx descriptors queue starting address and size */
3629 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
3630 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
3633 static void mvneta_txq_deinit(struct mvneta_port *pp,
3634 struct mvneta_tx_queue *txq)
3636 mvneta_txq_sw_deinit(pp, txq);
3637 mvneta_txq_hw_deinit(pp, txq);
3640 /* Cleanup all Tx queues */
3641 static void mvneta_cleanup_txqs(struct mvneta_port *pp)
3645 for (queue = 0; queue < txq_number; queue++)
3646 mvneta_txq_deinit(pp, &pp->txqs[queue]);
3649 /* Cleanup all Rx queues */
3650 static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
3654 for (queue = 0; queue < rxq_number; queue++)
3655 mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
3659 /* Init all Rx queues */
3660 static int mvneta_setup_rxqs(struct mvneta_port *pp)
3664 for (queue = 0; queue < rxq_number; queue++) {
3665 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
3668 netdev_err(pp->dev, "%s: can't create rxq=%d\n",
3670 mvneta_cleanup_rxqs(pp);
3678 /* Init all tx queues */
3679 static int mvneta_setup_txqs(struct mvneta_port *pp)
3683 for (queue = 0; queue < txq_number; queue++) {
3684 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
3686 netdev_err(pp->dev, "%s: can't create txq=%d\n",
3688 mvneta_cleanup_txqs(pp);
3696 static int mvneta_comphy_init(struct mvneta_port *pp, phy_interface_t interface)
3700 ret = phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET, interface);
3704 return phy_power_on(pp->comphy);
3707 static int mvneta_config_interface(struct mvneta_port *pp,
3708 phy_interface_t interface)
3713 if (interface == PHY_INTERFACE_MODE_SGMII ||
3714 interface == PHY_INTERFACE_MODE_1000BASEX ||
3715 interface == PHY_INTERFACE_MODE_2500BASEX) {
3716 ret = mvneta_comphy_init(pp, interface);
3719 switch (interface) {
3720 case PHY_INTERFACE_MODE_QSGMII:
3721 mvreg_write(pp, MVNETA_SERDES_CFG,
3722 MVNETA_QSGMII_SERDES_PROTO);
3725 case PHY_INTERFACE_MODE_SGMII:
3726 case PHY_INTERFACE_MODE_1000BASEX:
3727 mvreg_write(pp, MVNETA_SERDES_CFG,
3728 MVNETA_SGMII_SERDES_PROTO);
3731 case PHY_INTERFACE_MODE_2500BASEX:
3732 mvreg_write(pp, MVNETA_SERDES_CFG,
3733 MVNETA_HSGMII_SERDES_PROTO);
3740 pp->phy_interface = interface;
3745 static void mvneta_start_dev(struct mvneta_port *pp)
3749 WARN_ON(mvneta_config_interface(pp, pp->phy_interface));
3751 mvneta_max_rx_size_set(pp, pp->pkt_size);
3752 mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
3754 /* start the Rx/Tx activity */
3755 mvneta_port_enable(pp);
3757 if (!pp->neta_armada3700) {
3758 /* Enable polling on the port */
3759 for_each_online_cpu(cpu) {
3760 struct mvneta_pcpu_port *port =
3761 per_cpu_ptr(pp->ports, cpu);
3763 napi_enable(&port->napi);
3766 napi_enable(&pp->napi);
3769 /* Unmask interrupts. It has to be done from each CPU */
3770 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
3772 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
3773 MVNETA_CAUSE_PHY_STATUS_CHANGE |
3774 MVNETA_CAUSE_LINK_CHANGE);
3776 phylink_start(pp->phylink);
3778 /* We may have called phylink_speed_down before */
3779 phylink_speed_up(pp->phylink);
3781 netif_tx_start_all_queues(pp->dev);
3783 clear_bit(__MVNETA_DOWN, &pp->state);
3786 static void mvneta_stop_dev(struct mvneta_port *pp)
3790 set_bit(__MVNETA_DOWN, &pp->state);
3792 if (device_may_wakeup(&pp->dev->dev))
3793 phylink_speed_down(pp->phylink, false);
3795 phylink_stop(pp->phylink);
3797 if (!pp->neta_armada3700) {
3798 for_each_online_cpu(cpu) {
3799 struct mvneta_pcpu_port *port =
3800 per_cpu_ptr(pp->ports, cpu);
3802 napi_disable(&port->napi);
3805 napi_disable(&pp->napi);
3808 netif_carrier_off(pp->dev);
3810 mvneta_port_down(pp);
3811 netif_tx_stop_all_queues(pp->dev);
3813 /* Stop the port activity */
3814 mvneta_port_disable(pp);
3816 /* Clear all ethernet port interrupts */
3817 on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
3819 /* Mask all ethernet port interrupts */
3820 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
3822 mvneta_tx_reset(pp);
3823 mvneta_rx_reset(pp);
3825 WARN_ON(phy_power_off(pp->comphy));
3828 static void mvneta_percpu_enable(void *arg)
3830 struct mvneta_port *pp = arg;
3832 enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE);
3835 static void mvneta_percpu_disable(void *arg)
3837 struct mvneta_port *pp = arg;
3839 disable_percpu_irq(pp->dev->irq);
3842 /* Change the device mtu */
3843 static int mvneta_change_mtu(struct net_device *dev, int mtu)
3845 struct mvneta_port *pp = netdev_priv(dev);
3846 struct bpf_prog *prog = pp->xdp_prog;
3849 if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) {
3850 netdev_info(dev, "Illegal MTU value %d, rounding to %d\n",
3851 mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8));
3852 mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8);
3855 if (prog && !prog->aux->xdp_has_frags &&
3856 mtu > MVNETA_MAX_RX_BUF_SIZE) {
3857 netdev_info(dev, "Illegal MTU %d for XDP prog without frags\n",
3865 if (!netif_running(dev)) {
3867 mvneta_bm_update_mtu(pp, mtu);
3869 netdev_update_features(dev);
3873 /* The interface is running, so we have to force a
3874 * reallocation of the queues
3876 mvneta_stop_dev(pp);
3877 on_each_cpu(mvneta_percpu_disable, pp, true);
3879 mvneta_cleanup_txqs(pp);
3880 mvneta_cleanup_rxqs(pp);
3883 mvneta_bm_update_mtu(pp, mtu);
3885 pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu);
3887 ret = mvneta_setup_rxqs(pp);
3889 netdev_err(dev, "unable to setup rxqs after MTU change\n");
3893 ret = mvneta_setup_txqs(pp);
3895 netdev_err(dev, "unable to setup txqs after MTU change\n");
3899 on_each_cpu(mvneta_percpu_enable, pp, true);
3900 mvneta_start_dev(pp);
3902 netdev_update_features(dev);
3907 static netdev_features_t mvneta_fix_features(struct net_device *dev,
3908 netdev_features_t features)
3910 struct mvneta_port *pp = netdev_priv(dev);
3912 if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) {
3913 features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO);
3915 "Disable IP checksum for MTU greater than %dB\n",
3922 /* Get mac address */
3923 static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr)
3925 u32 mac_addr_l, mac_addr_h;
3927 mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW);
3928 mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH);
3929 addr[0] = (mac_addr_h >> 24) & 0xFF;
3930 addr[1] = (mac_addr_h >> 16) & 0xFF;
3931 addr[2] = (mac_addr_h >> 8) & 0xFF;
3932 addr[3] = mac_addr_h & 0xFF;
3933 addr[4] = (mac_addr_l >> 8) & 0xFF;
3934 addr[5] = mac_addr_l & 0xFF;
3937 /* Handle setting mac address */
3938 static int mvneta_set_mac_addr(struct net_device *dev, void *addr)
3940 struct mvneta_port *pp = netdev_priv(dev);
3941 struct sockaddr *sockaddr = addr;
3944 ret = eth_prepare_mac_addr_change(dev, addr);
3947 /* Remove previous address table entry */
3948 mvneta_mac_addr_set(pp, dev->dev_addr, -1);
3950 /* Set new addr in hw */
3951 mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def);
3953 eth_commit_mac_addr_change(dev, addr);
3957 static struct mvneta_port *mvneta_pcs_to_port(struct phylink_pcs *pcs)
3959 return container_of(pcs, struct mvneta_port, phylink_pcs);
3962 static int mvneta_pcs_validate(struct phylink_pcs *pcs,
3963 unsigned long *supported,
3964 const struct phylink_link_state *state)
3966 /* We only support QSGMII, SGMII, 802.3z and RGMII modes.
3967 * When in 802.3z mode, we must have AN enabled:
3968 * "Bit 2 Field InBandAnEn In-band Auto-Negotiation enable. ...
3969 * When <PortType> = 1 (1000BASE-X) this field must be set to 1."
3971 if (phy_interface_mode_is_8023z(state->interface) &&
3972 !phylink_test(state->advertising, Autoneg))
3978 static void mvneta_pcs_get_state(struct phylink_pcs *pcs,
3979 struct phylink_link_state *state)
3981 struct mvneta_port *pp = mvneta_pcs_to_port(pcs);
3984 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
3986 if (gmac_stat & MVNETA_GMAC_SPEED_1000)
3988 state->interface == PHY_INTERFACE_MODE_2500BASEX ?
3989 SPEED_2500 : SPEED_1000;
3990 else if (gmac_stat & MVNETA_GMAC_SPEED_100)
3991 state->speed = SPEED_100;
3993 state->speed = SPEED_10;
3995 state->an_complete = !!(gmac_stat & MVNETA_GMAC_AN_COMPLETE);
3996 state->link = !!(gmac_stat & MVNETA_GMAC_LINK_UP);
3997 state->duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX);
3999 if (gmac_stat & MVNETA_GMAC_RX_FLOW_CTRL_ENABLE)
4000 state->pause |= MLO_PAUSE_RX;
4001 if (gmac_stat & MVNETA_GMAC_TX_FLOW_CTRL_ENABLE)
4002 state->pause |= MLO_PAUSE_TX;
4005 static int mvneta_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
4006 phy_interface_t interface,
4007 const unsigned long *advertising,
4008 bool permit_pause_to_mac)
4010 struct mvneta_port *pp = mvneta_pcs_to_port(pcs);
4011 u32 mask, val, an, old_an, changed;
4013 mask = MVNETA_GMAC_INBAND_AN_ENABLE |
4014 MVNETA_GMAC_INBAND_RESTART_AN |
4015 MVNETA_GMAC_AN_SPEED_EN |
4016 MVNETA_GMAC_AN_FLOW_CTRL_EN |
4017 MVNETA_GMAC_AN_DUPLEX_EN;
4019 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
4020 mask |= MVNETA_GMAC_CONFIG_MII_SPEED |
4021 MVNETA_GMAC_CONFIG_GMII_SPEED |
4022 MVNETA_GMAC_CONFIG_FULL_DUPLEX;
4023 val = MVNETA_GMAC_INBAND_AN_ENABLE;
4025 if (interface == PHY_INTERFACE_MODE_SGMII) {
4026 /* SGMII mode receives the speed and duplex from PHY */
4027 val |= MVNETA_GMAC_AN_SPEED_EN |
4028 MVNETA_GMAC_AN_DUPLEX_EN;
4030 /* 802.3z mode has fixed speed and duplex */
4031 val |= MVNETA_GMAC_CONFIG_GMII_SPEED |
4032 MVNETA_GMAC_CONFIG_FULL_DUPLEX;
4034 /* The FLOW_CTRL_EN bit selects either the hardware
4035 * automatically or the CONFIG_FLOW_CTRL manually
4036 * controls the GMAC pause mode.
4038 if (permit_pause_to_mac)
4039 val |= MVNETA_GMAC_AN_FLOW_CTRL_EN;
4041 /* Update the advertisement bits */
4042 mask |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL;
4043 if (phylink_test(advertising, Pause))
4044 val |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL;
4047 /* Phy or fixed speed - disable in-band AN modes */
4051 old_an = an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
4052 an = (an & ~mask) | val;
4053 changed = old_an ^ an;
4055 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, an);
4057 /* We are only interested in the advertisement bits changing */
4058 return !!(changed & MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL);
4061 static void mvneta_pcs_an_restart(struct phylink_pcs *pcs)
4063 struct mvneta_port *pp = mvneta_pcs_to_port(pcs);
4064 u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
4066 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
4067 gmac_an | MVNETA_GMAC_INBAND_RESTART_AN);
4068 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
4069 gmac_an & ~MVNETA_GMAC_INBAND_RESTART_AN);
4072 static const struct phylink_pcs_ops mvneta_phylink_pcs_ops = {
4073 .pcs_validate = mvneta_pcs_validate,
4074 .pcs_get_state = mvneta_pcs_get_state,
4075 .pcs_config = mvneta_pcs_config,
4076 .pcs_an_restart = mvneta_pcs_an_restart,
4079 static struct phylink_pcs *mvneta_mac_select_pcs(struct phylink_config *config,
4080 phy_interface_t interface)
4082 struct net_device *ndev = to_net_dev(config->dev);
4083 struct mvneta_port *pp = netdev_priv(ndev);
4085 return &pp->phylink_pcs;
4088 static int mvneta_mac_prepare(struct phylink_config *config, unsigned int mode,
4089 phy_interface_t interface)
4091 struct net_device *ndev = to_net_dev(config->dev);
4092 struct mvneta_port *pp = netdev_priv(ndev);
4095 if (pp->phy_interface != interface ||
4096 phylink_autoneg_inband(mode)) {
4097 /* Force the link down when changing the interface or if in
4098 * in-band mode. According to Armada 370 documentation, we
4099 * can only change the port mode and in-band enable when the
4102 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
4103 val &= ~MVNETA_GMAC_FORCE_LINK_PASS;
4104 val |= MVNETA_GMAC_FORCE_LINK_DOWN;
4105 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
4108 if (pp->phy_interface != interface)
4109 WARN_ON(phy_power_off(pp->comphy));
4111 /* Enable the 1ms clock */
4112 if (phylink_autoneg_inband(mode)) {
4113 unsigned long rate = clk_get_rate(pp->clk);
4115 mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER,
4116 MVNETA_GMAC_1MS_CLOCK_ENABLE | (rate / 1000));
4122 static void mvneta_mac_config(struct phylink_config *config, unsigned int mode,
4123 const struct phylink_link_state *state)
4125 struct net_device *ndev = to_net_dev(config->dev);
4126 struct mvneta_port *pp = netdev_priv(ndev);
4127 u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
4128 u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
4129 u32 new_ctrl4, gmac_ctrl4 = mvreg_read(pp, MVNETA_GMAC_CTRL_4);
4131 new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X;
4132 new_ctrl2 = gmac_ctrl2 & ~(MVNETA_GMAC2_INBAND_AN_ENABLE |
4133 MVNETA_GMAC2_PORT_RESET);
4134 new_ctrl4 = gmac_ctrl4 & ~(MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE);
4136 /* Even though it might look weird, when we're configured in
4137 * SGMII or QSGMII mode, the RGMII bit needs to be set.
4139 new_ctrl2 |= MVNETA_GMAC2_PORT_RGMII;
4141 if (state->interface == PHY_INTERFACE_MODE_QSGMII ||
4142 state->interface == PHY_INTERFACE_MODE_SGMII ||
4143 phy_interface_mode_is_8023z(state->interface))
4144 new_ctrl2 |= MVNETA_GMAC2_PCS_ENABLE;
4146 if (!phylink_autoneg_inband(mode)) {
4147 /* Phy or fixed speed - nothing to do, leave the
4148 * configured speed, duplex and flow control as-is.
4150 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
4151 /* SGMII mode receives the state from the PHY */
4152 new_ctrl2 |= MVNETA_GMAC2_INBAND_AN_ENABLE;
4154 /* 802.3z negotiation - only 1000base-X */
4155 new_ctrl0 |= MVNETA_GMAC0_PORT_1000BASE_X;
4158 /* When at 2.5G, the link partner can send frames with shortened
4161 if (state->interface == PHY_INTERFACE_MODE_2500BASEX)
4162 new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE;
4164 if (new_ctrl0 != gmac_ctrl0)
4165 mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0);
4166 if (new_ctrl2 != gmac_ctrl2)
4167 mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2);
4168 if (new_ctrl4 != gmac_ctrl4)
4169 mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4);
4171 if (gmac_ctrl2 & MVNETA_GMAC2_PORT_RESET) {
4172 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
4173 MVNETA_GMAC2_PORT_RESET) != 0)
4178 static int mvneta_mac_finish(struct phylink_config *config, unsigned int mode,
4179 phy_interface_t interface)
4181 struct net_device *ndev = to_net_dev(config->dev);
4182 struct mvneta_port *pp = netdev_priv(ndev);
4185 /* Disable 1ms clock if not in in-band mode */
4186 if (!phylink_autoneg_inband(mode)) {
4187 clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
4188 clk &= ~MVNETA_GMAC_1MS_CLOCK_ENABLE;
4189 mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, clk);
4192 if (pp->phy_interface != interface)
4193 /* Enable the Serdes PHY */
4194 WARN_ON(mvneta_config_interface(pp, interface));
4196 /* Allow the link to come up if in in-band mode, otherwise the
4197 * link is forced via mac_link_down()/mac_link_up()
4199 if (phylink_autoneg_inband(mode)) {
4200 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
4201 val &= ~MVNETA_GMAC_FORCE_LINK_DOWN;
4202 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
4208 static void mvneta_set_eee(struct mvneta_port *pp, bool enable)
4212 lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1);
4214 lpi_ctl1 |= MVNETA_LPI_REQUEST_ENABLE;
4216 lpi_ctl1 &= ~MVNETA_LPI_REQUEST_ENABLE;
4217 mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1);
4220 static void mvneta_mac_link_down(struct phylink_config *config,
4221 unsigned int mode, phy_interface_t interface)
4223 struct net_device *ndev = to_net_dev(config->dev);
4224 struct mvneta_port *pp = netdev_priv(ndev);
4227 mvneta_port_down(pp);
4229 if (!phylink_autoneg_inband(mode)) {
4230 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
4231 val &= ~MVNETA_GMAC_FORCE_LINK_PASS;
4232 val |= MVNETA_GMAC_FORCE_LINK_DOWN;
4233 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
4236 pp->eee_active = false;
4237 mvneta_set_eee(pp, false);
4240 static void mvneta_mac_link_up(struct phylink_config *config,
4241 struct phy_device *phy,
4242 unsigned int mode, phy_interface_t interface,
4243 int speed, int duplex,
4244 bool tx_pause, bool rx_pause)
4246 struct net_device *ndev = to_net_dev(config->dev);
4247 struct mvneta_port *pp = netdev_priv(ndev);
4250 if (!phylink_autoneg_inband(mode)) {
4251 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
4252 val &= ~(MVNETA_GMAC_FORCE_LINK_DOWN |
4253 MVNETA_GMAC_CONFIG_MII_SPEED |
4254 MVNETA_GMAC_CONFIG_GMII_SPEED |
4255 MVNETA_GMAC_CONFIG_FLOW_CTRL |
4256 MVNETA_GMAC_CONFIG_FULL_DUPLEX);
4257 val |= MVNETA_GMAC_FORCE_LINK_PASS;
4259 if (speed == SPEED_1000 || speed == SPEED_2500)
4260 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
4261 else if (speed == SPEED_100)
4262 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
4264 if (duplex == DUPLEX_FULL)
4265 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
4267 if (tx_pause || rx_pause)
4268 val |= MVNETA_GMAC_CONFIG_FLOW_CTRL;
4270 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
4272 /* When inband doesn't cover flow control or flow control is
4273 * disabled, we need to manually configure it. This bit will
4274 * only have effect if MVNETA_GMAC_AN_FLOW_CTRL_EN is unset.
4276 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
4277 val &= ~MVNETA_GMAC_CONFIG_FLOW_CTRL;
4279 if (tx_pause || rx_pause)
4280 val |= MVNETA_GMAC_CONFIG_FLOW_CTRL;
4282 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
4287 if (phy && pp->eee_enabled) {
4288 pp->eee_active = phy_init_eee(phy, false) >= 0;
4289 mvneta_set_eee(pp, pp->eee_active && pp->tx_lpi_enabled);
4293 static const struct phylink_mac_ops mvneta_phylink_ops = {
4294 .mac_select_pcs = mvneta_mac_select_pcs,
4295 .mac_prepare = mvneta_mac_prepare,
4296 .mac_config = mvneta_mac_config,
4297 .mac_finish = mvneta_mac_finish,
4298 .mac_link_down = mvneta_mac_link_down,
4299 .mac_link_up = mvneta_mac_link_up,
4302 static int mvneta_mdio_probe(struct mvneta_port *pp)
4304 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL };
4305 int err = phylink_of_phy_connect(pp->phylink, pp->dn, 0);
4308 netdev_err(pp->dev, "could not attach PHY: %d\n", err);
4310 phylink_ethtool_get_wol(pp->phylink, &wol);
4311 device_set_wakeup_capable(&pp->dev->dev, !!wol.supported);
4313 /* PHY WoL may be enabled but device wakeup disabled */
4315 device_set_wakeup_enable(&pp->dev->dev, !!wol.wolopts);
4320 static void mvneta_mdio_remove(struct mvneta_port *pp)
4322 phylink_disconnect_phy(pp->phylink);
4325 /* Electing a CPU must be done in an atomic way: it should be done
4326 * after or before the removal/insertion of a CPU and this function is
4329 static void mvneta_percpu_elect(struct mvneta_port *pp)
4331 int elected_cpu = 0, max_cpu, cpu;
4333 /* Use the cpu associated to the rxq when it is online, in all
4334 * the other cases, use the cpu 0 which can't be offline.
4336 if (pp->rxq_def < nr_cpu_ids && cpu_online(pp->rxq_def))
4337 elected_cpu = pp->rxq_def;
4339 max_cpu = num_present_cpus();
4341 for_each_online_cpu(cpu) {
4342 int rxq_map = 0, txq_map = 0;
4345 for (rxq = 0; rxq < rxq_number; rxq++)
4346 if ((rxq % max_cpu) == cpu)
4347 rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
4349 if (cpu == elected_cpu)
4350 /* Map the default receive queue to the elected CPU */
4351 rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def);
4353 /* We update the TX queue map only if we have one
4354 * queue. In this case we associate the TX queue to
4355 * the CPU bound to the default RX queue
4357 if (txq_number == 1)
4358 txq_map = (cpu == elected_cpu) ?
4359 MVNETA_CPU_TXQ_ACCESS(0) : 0;
4361 txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) &
4362 MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
4364 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
4366 /* Update the interrupt mask on each CPU according the
4369 smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt,
4374 static int mvneta_cpu_online(unsigned int cpu, struct hlist_node *node)
4377 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
4379 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
4381 /* Armada 3700's per-cpu interrupt for mvneta is broken, all interrupts
4382 * are routed to CPU 0, so we don't need all the cpu-hotplug support
4384 if (pp->neta_armada3700)
4387 spin_lock(&pp->lock);
4389 * Configuring the driver for a new CPU while the driver is
4390 * stopping is racy, so just avoid it.
4392 if (pp->is_stopped) {
4393 spin_unlock(&pp->lock);
4396 netif_tx_stop_all_queues(pp->dev);
4399 * We have to synchronise on tha napi of each CPU except the one
4400 * just being woken up
4402 for_each_online_cpu(other_cpu) {
4403 if (other_cpu != cpu) {
4404 struct mvneta_pcpu_port *other_port =
4405 per_cpu_ptr(pp->ports, other_cpu);
4407 napi_synchronize(&other_port->napi);
4411 /* Mask all ethernet port interrupts */
4412 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
4413 napi_enable(&port->napi);
4416 * Enable per-CPU interrupts on the CPU that is
4419 mvneta_percpu_enable(pp);
4422 * Enable per-CPU interrupt on the one CPU we care
4425 mvneta_percpu_elect(pp);
4427 /* Unmask all ethernet port interrupts */
4428 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
4429 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
4430 MVNETA_CAUSE_PHY_STATUS_CHANGE |
4431 MVNETA_CAUSE_LINK_CHANGE);
4432 netif_tx_start_all_queues(pp->dev);
4433 spin_unlock(&pp->lock);
4437 static int mvneta_cpu_down_prepare(unsigned int cpu, struct hlist_node *node)
4439 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
4441 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
4444 * Thanks to this lock we are sure that any pending cpu election is
4447 spin_lock(&pp->lock);
4448 /* Mask all ethernet port interrupts */
4449 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
4450 spin_unlock(&pp->lock);
4452 napi_synchronize(&port->napi);
4453 napi_disable(&port->napi);
4454 /* Disable per-CPU interrupts on the CPU that is brought down. */
4455 mvneta_percpu_disable(pp);
4459 static int mvneta_cpu_dead(unsigned int cpu, struct hlist_node *node)
4461 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
4464 /* Check if a new CPU must be elected now this on is down */
4465 spin_lock(&pp->lock);
4466 mvneta_percpu_elect(pp);
4467 spin_unlock(&pp->lock);
4468 /* Unmask all ethernet port interrupts */
4469 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
4470 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
4471 MVNETA_CAUSE_PHY_STATUS_CHANGE |
4472 MVNETA_CAUSE_LINK_CHANGE);
4473 netif_tx_start_all_queues(pp->dev);
4477 static int mvneta_open(struct net_device *dev)
4479 struct mvneta_port *pp = netdev_priv(dev);
4482 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
4484 ret = mvneta_setup_rxqs(pp);
4488 ret = mvneta_setup_txqs(pp);
4490 goto err_cleanup_rxqs;
4492 /* Connect to port interrupt line */
4493 if (pp->neta_armada3700)
4494 ret = request_irq(pp->dev->irq, mvneta_isr, 0,
4497 ret = request_percpu_irq(pp->dev->irq, mvneta_percpu_isr,
4498 dev->name, pp->ports);
4500 netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq);
4501 goto err_cleanup_txqs;
4504 if (!pp->neta_armada3700) {
4505 /* Enable per-CPU interrupt on all the CPU to handle our RX
4508 on_each_cpu(mvneta_percpu_enable, pp, true);
4510 pp->is_stopped = false;
4511 /* Register a CPU notifier to handle the case where our CPU
4512 * might be taken offline.
4514 ret = cpuhp_state_add_instance_nocalls(online_hpstate,
4519 ret = cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
4522 goto err_free_online_hp;
4525 ret = mvneta_mdio_probe(pp);
4527 netdev_err(dev, "cannot probe MDIO bus\n");
4528 goto err_free_dead_hp;
4531 mvneta_start_dev(pp);
4536 if (!pp->neta_armada3700)
4537 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
4540 if (!pp->neta_armada3700)
4541 cpuhp_state_remove_instance_nocalls(online_hpstate,
4544 if (pp->neta_armada3700) {
4545 free_irq(pp->dev->irq, pp);
4547 on_each_cpu(mvneta_percpu_disable, pp, true);
4548 free_percpu_irq(pp->dev->irq, pp->ports);
4551 mvneta_cleanup_txqs(pp);
4553 mvneta_cleanup_rxqs(pp);
4557 /* Stop the port, free port interrupt line */
4558 static int mvneta_stop(struct net_device *dev)
4560 struct mvneta_port *pp = netdev_priv(dev);
4562 if (!pp->neta_armada3700) {
4563 /* Inform that we are stopping so we don't want to setup the
4564 * driver for new CPUs in the notifiers. The code of the
4565 * notifier for CPU online is protected by the same spinlock,
4566 * so when we get the lock, the notifer work is done.
4568 spin_lock(&pp->lock);
4569 pp->is_stopped = true;
4570 spin_unlock(&pp->lock);
4572 mvneta_stop_dev(pp);
4573 mvneta_mdio_remove(pp);
4575 cpuhp_state_remove_instance_nocalls(online_hpstate,
4577 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
4579 on_each_cpu(mvneta_percpu_disable, pp, true);
4580 free_percpu_irq(dev->irq, pp->ports);
4582 mvneta_stop_dev(pp);
4583 mvneta_mdio_remove(pp);
4584 free_irq(dev->irq, pp);
4587 mvneta_cleanup_rxqs(pp);
4588 mvneta_cleanup_txqs(pp);
4593 static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4595 struct mvneta_port *pp = netdev_priv(dev);
4597 return phylink_mii_ioctl(pp->phylink, ifr, cmd);
4600 static int mvneta_xdp_setup(struct net_device *dev, struct bpf_prog *prog,
4601 struct netlink_ext_ack *extack)
4603 bool need_update, running = netif_running(dev);
4604 struct mvneta_port *pp = netdev_priv(dev);
4605 struct bpf_prog *old_prog;
4607 if (prog && !prog->aux->xdp_has_frags &&
4608 dev->mtu > MVNETA_MAX_RX_BUF_SIZE) {
4609 NL_SET_ERR_MSG_MOD(extack, "prog does not support XDP frags");
4614 NL_SET_ERR_MSG_MOD(extack,
4615 "Hardware Buffer Management not supported on XDP");
4619 need_update = !!pp->xdp_prog != !!prog;
4620 if (running && need_update)
4623 old_prog = xchg(&pp->xdp_prog, prog);
4625 bpf_prog_put(old_prog);
4627 if (running && need_update)
4628 return mvneta_open(dev);
4633 static int mvneta_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4635 switch (xdp->command) {
4636 case XDP_SETUP_PROG:
4637 return mvneta_xdp_setup(dev, xdp->prog, xdp->extack);
4643 /* Ethtool methods */
4645 /* Set link ksettings (phy address, speed) for ethtools */
4647 mvneta_ethtool_set_link_ksettings(struct net_device *ndev,
4648 const struct ethtool_link_ksettings *cmd)
4650 struct mvneta_port *pp = netdev_priv(ndev);
4652 return phylink_ethtool_ksettings_set(pp->phylink, cmd);
4655 /* Get link ksettings for ethtools */
4657 mvneta_ethtool_get_link_ksettings(struct net_device *ndev,
4658 struct ethtool_link_ksettings *cmd)
4660 struct mvneta_port *pp = netdev_priv(ndev);
4662 return phylink_ethtool_ksettings_get(pp->phylink, cmd);
4665 static int mvneta_ethtool_nway_reset(struct net_device *dev)
4667 struct mvneta_port *pp = netdev_priv(dev);
4669 return phylink_ethtool_nway_reset(pp->phylink);
4672 /* Set interrupt coalescing for ethtools */
4674 mvneta_ethtool_set_coalesce(struct net_device *dev,
4675 struct ethtool_coalesce *c,
4676 struct kernel_ethtool_coalesce *kernel_coal,
4677 struct netlink_ext_ack *extack)
4679 struct mvneta_port *pp = netdev_priv(dev);
4682 for (queue = 0; queue < rxq_number; queue++) {
4683 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
4684 rxq->time_coal = c->rx_coalesce_usecs;
4685 rxq->pkts_coal = c->rx_max_coalesced_frames;
4686 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
4687 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
4690 for (queue = 0; queue < txq_number; queue++) {
4691 struct mvneta_tx_queue *txq = &pp->txqs[queue];
4692 txq->done_pkts_coal = c->tx_max_coalesced_frames;
4693 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
4699 /* get coalescing for ethtools */
4701 mvneta_ethtool_get_coalesce(struct net_device *dev,
4702 struct ethtool_coalesce *c,
4703 struct kernel_ethtool_coalesce *kernel_coal,
4704 struct netlink_ext_ack *extack)
4706 struct mvneta_port *pp = netdev_priv(dev);
4708 c->rx_coalesce_usecs = pp->rxqs[0].time_coal;
4709 c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal;
4711 c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal;
4716 static void mvneta_ethtool_get_drvinfo(struct net_device *dev,
4717 struct ethtool_drvinfo *drvinfo)
4719 strscpy(drvinfo->driver, MVNETA_DRIVER_NAME,
4720 sizeof(drvinfo->driver));
4721 strscpy(drvinfo->version, MVNETA_DRIVER_VERSION,
4722 sizeof(drvinfo->version));
4723 strscpy(drvinfo->bus_info, dev_name(&dev->dev),
4724 sizeof(drvinfo->bus_info));
4729 mvneta_ethtool_get_ringparam(struct net_device *netdev,
4730 struct ethtool_ringparam *ring,
4731 struct kernel_ethtool_ringparam *kernel_ring,
4732 struct netlink_ext_ack *extack)
4734 struct mvneta_port *pp = netdev_priv(netdev);
4736 ring->rx_max_pending = MVNETA_MAX_RXD;
4737 ring->tx_max_pending = MVNETA_MAX_TXD;
4738 ring->rx_pending = pp->rx_ring_size;
4739 ring->tx_pending = pp->tx_ring_size;
4743 mvneta_ethtool_set_ringparam(struct net_device *dev,
4744 struct ethtool_ringparam *ring,
4745 struct kernel_ethtool_ringparam *kernel_ring,
4746 struct netlink_ext_ack *extack)
4748 struct mvneta_port *pp = netdev_priv(dev);
4750 if ((ring->rx_pending == 0) || (ring->tx_pending == 0))
4752 pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ?
4753 ring->rx_pending : MVNETA_MAX_RXD;
4755 pp->tx_ring_size = clamp_t(u16, ring->tx_pending,
4756 MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD);
4757 if (pp->tx_ring_size != ring->tx_pending)
4758 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
4759 pp->tx_ring_size, ring->tx_pending);
4761 if (netif_running(dev)) {
4763 if (mvneta_open(dev)) {
4765 "error on opening device after ring param change\n");
4773 static void mvneta_ethtool_get_pauseparam(struct net_device *dev,
4774 struct ethtool_pauseparam *pause)
4776 struct mvneta_port *pp = netdev_priv(dev);
4778 phylink_ethtool_get_pauseparam(pp->phylink, pause);
4781 static int mvneta_ethtool_set_pauseparam(struct net_device *dev,
4782 struct ethtool_pauseparam *pause)
4784 struct mvneta_port *pp = netdev_priv(dev);
4786 return phylink_ethtool_set_pauseparam(pp->phylink, pause);
4789 static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset,
4792 if (sset == ETH_SS_STATS) {
4795 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
4796 memcpy(data + i * ETH_GSTRING_LEN,
4797 mvneta_statistics[i].name, ETH_GSTRING_LEN);
4799 data += ETH_GSTRING_LEN * ARRAY_SIZE(mvneta_statistics);
4800 page_pool_ethtool_stats_get_strings(data);
4805 mvneta_ethtool_update_pcpu_stats(struct mvneta_port *pp,
4806 struct mvneta_ethtool_stats *es)
4811 for_each_possible_cpu(cpu) {
4812 struct mvneta_pcpu_stats *stats;
4813 u64 skb_alloc_error;
4823 stats = per_cpu_ptr(pp->stats, cpu);
4825 start = u64_stats_fetch_begin(&stats->syncp);
4826 skb_alloc_error = stats->es.skb_alloc_error;
4827 refill_error = stats->es.refill_error;
4828 xdp_redirect = stats->es.ps.xdp_redirect;
4829 xdp_pass = stats->es.ps.xdp_pass;
4830 xdp_drop = stats->es.ps.xdp_drop;
4831 xdp_xmit = stats->es.ps.xdp_xmit;
4832 xdp_xmit_err = stats->es.ps.xdp_xmit_err;
4833 xdp_tx = stats->es.ps.xdp_tx;
4834 xdp_tx_err = stats->es.ps.xdp_tx_err;
4835 } while (u64_stats_fetch_retry(&stats->syncp, start));
4837 es->skb_alloc_error += skb_alloc_error;
4838 es->refill_error += refill_error;
4839 es->ps.xdp_redirect += xdp_redirect;
4840 es->ps.xdp_pass += xdp_pass;
4841 es->ps.xdp_drop += xdp_drop;
4842 es->ps.xdp_xmit += xdp_xmit;
4843 es->ps.xdp_xmit_err += xdp_xmit_err;
4844 es->ps.xdp_tx += xdp_tx;
4845 es->ps.xdp_tx_err += xdp_tx_err;
4849 static void mvneta_ethtool_update_stats(struct mvneta_port *pp)
4851 struct mvneta_ethtool_stats stats = {};
4852 const struct mvneta_statistic *s;
4853 void __iomem *base = pp->base;
4858 mvneta_ethtool_update_pcpu_stats(pp, &stats);
4859 for (i = 0, s = mvneta_statistics;
4860 s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics);
4864 val = readl_relaxed(base + s->offset);
4865 pp->ethtool_stats[i] += val;
4868 /* Docs say to read low 32-bit then high */
4869 low = readl_relaxed(base + s->offset);
4870 high = readl_relaxed(base + s->offset + 4);
4871 val = (u64)high << 32 | low;
4872 pp->ethtool_stats[i] += val;
4875 switch (s->offset) {
4876 case ETHTOOL_STAT_EEE_WAKEUP:
4877 val = phylink_get_eee_err(pp->phylink);
4878 pp->ethtool_stats[i] += val;
4880 case ETHTOOL_STAT_SKB_ALLOC_ERR:
4881 pp->ethtool_stats[i] = stats.skb_alloc_error;
4883 case ETHTOOL_STAT_REFILL_ERR:
4884 pp->ethtool_stats[i] = stats.refill_error;
4886 case ETHTOOL_XDP_REDIRECT:
4887 pp->ethtool_stats[i] = stats.ps.xdp_redirect;
4889 case ETHTOOL_XDP_PASS:
4890 pp->ethtool_stats[i] = stats.ps.xdp_pass;
4892 case ETHTOOL_XDP_DROP:
4893 pp->ethtool_stats[i] = stats.ps.xdp_drop;
4895 case ETHTOOL_XDP_TX:
4896 pp->ethtool_stats[i] = stats.ps.xdp_tx;
4898 case ETHTOOL_XDP_TX_ERR:
4899 pp->ethtool_stats[i] = stats.ps.xdp_tx_err;
4901 case ETHTOOL_XDP_XMIT:
4902 pp->ethtool_stats[i] = stats.ps.xdp_xmit;
4904 case ETHTOOL_XDP_XMIT_ERR:
4905 pp->ethtool_stats[i] = stats.ps.xdp_xmit_err;
4913 static void mvneta_ethtool_pp_stats(struct mvneta_port *pp, u64 *data)
4915 struct page_pool_stats stats = {};
4918 for (i = 0; i < rxq_number; i++)
4919 page_pool_get_stats(pp->rxqs[i].page_pool, &stats);
4921 page_pool_ethtool_stats_get(data, &stats);
4924 static void mvneta_ethtool_get_stats(struct net_device *dev,
4925 struct ethtool_stats *stats, u64 *data)
4927 struct mvneta_port *pp = netdev_priv(dev);
4930 mvneta_ethtool_update_stats(pp);
4932 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
4933 *data++ = pp->ethtool_stats[i];
4935 mvneta_ethtool_pp_stats(pp, data);
4938 static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset)
4940 if (sset == ETH_SS_STATS)
4941 return ARRAY_SIZE(mvneta_statistics) +
4942 page_pool_ethtool_stats_get_count();
4947 static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev)
4949 return MVNETA_RSS_LU_TABLE_SIZE;
4952 static int mvneta_ethtool_get_rxnfc(struct net_device *dev,
4953 struct ethtool_rxnfc *info,
4954 u32 *rules __always_unused)
4956 switch (info->cmd) {
4957 case ETHTOOL_GRXRINGS:
4958 info->data = rxq_number;
4967 static int mvneta_config_rss(struct mvneta_port *pp)
4972 netif_tx_stop_all_queues(pp->dev);
4974 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
4976 if (!pp->neta_armada3700) {
4977 /* We have to synchronise on the napi of each CPU */
4978 for_each_online_cpu(cpu) {
4979 struct mvneta_pcpu_port *pcpu_port =
4980 per_cpu_ptr(pp->ports, cpu);
4982 napi_synchronize(&pcpu_port->napi);
4983 napi_disable(&pcpu_port->napi);
4986 napi_synchronize(&pp->napi);
4987 napi_disable(&pp->napi);
4990 pp->rxq_def = pp->indir[0];
4992 /* Update unicast mapping */
4993 mvneta_set_rx_mode(pp->dev);
4995 /* Update val of portCfg register accordingly with all RxQueue types */
4996 val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def);
4997 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
4999 /* Update the elected CPU matching the new rxq_def */
5000 spin_lock(&pp->lock);
5001 mvneta_percpu_elect(pp);
5002 spin_unlock(&pp->lock);
5004 if (!pp->neta_armada3700) {
5005 /* We have to synchronise on the napi of each CPU */
5006 for_each_online_cpu(cpu) {
5007 struct mvneta_pcpu_port *pcpu_port =
5008 per_cpu_ptr(pp->ports, cpu);
5010 napi_enable(&pcpu_port->napi);
5013 napi_enable(&pp->napi);
5016 netif_tx_start_all_queues(pp->dev);
5021 static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,
5022 const u8 *key, const u8 hfunc)
5024 struct mvneta_port *pp = netdev_priv(dev);
5026 /* Current code for Armada 3700 doesn't support RSS features yet */
5027 if (pp->neta_armada3700)
5030 /* We require at least one supported parameter to be changed
5031 * and no change in any of the unsupported parameters
5034 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
5040 memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE);
5042 return mvneta_config_rss(pp);
5045 static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
5048 struct mvneta_port *pp = netdev_priv(dev);
5050 /* Current code for Armada 3700 doesn't support RSS features yet */
5051 if (pp->neta_armada3700)
5055 *hfunc = ETH_RSS_HASH_TOP;
5060 memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE);
5065 static void mvneta_ethtool_get_wol(struct net_device *dev,
5066 struct ethtool_wolinfo *wol)
5068 struct mvneta_port *pp = netdev_priv(dev);
5070 phylink_ethtool_get_wol(pp->phylink, wol);
5073 static int mvneta_ethtool_set_wol(struct net_device *dev,
5074 struct ethtool_wolinfo *wol)
5076 struct mvneta_port *pp = netdev_priv(dev);
5079 ret = phylink_ethtool_set_wol(pp->phylink, wol);
5081 device_set_wakeup_enable(&dev->dev, !!wol->wolopts);
5086 static int mvneta_ethtool_get_eee(struct net_device *dev,
5087 struct ethtool_eee *eee)
5089 struct mvneta_port *pp = netdev_priv(dev);
5092 lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0);
5094 eee->eee_enabled = pp->eee_enabled;
5095 eee->eee_active = pp->eee_active;
5096 eee->tx_lpi_enabled = pp->tx_lpi_enabled;
5097 eee->tx_lpi_timer = (lpi_ctl0) >> 8; // * scale;
5099 return phylink_ethtool_get_eee(pp->phylink, eee);
5102 static int mvneta_ethtool_set_eee(struct net_device *dev,
5103 struct ethtool_eee *eee)
5105 struct mvneta_port *pp = netdev_priv(dev);
5108 /* The Armada 37x documents do not give limits for this other than
5109 * it being an 8-bit register.
5111 if (eee->tx_lpi_enabled && eee->tx_lpi_timer > 255)
5114 lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0);
5115 lpi_ctl0 &= ~(0xff << 8);
5116 lpi_ctl0 |= eee->tx_lpi_timer << 8;
5117 mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0);
5119 pp->eee_enabled = eee->eee_enabled;
5120 pp->tx_lpi_enabled = eee->tx_lpi_enabled;
5122 mvneta_set_eee(pp, eee->tx_lpi_enabled && eee->eee_enabled);
5124 return phylink_ethtool_set_eee(pp->phylink, eee);
5127 static void mvneta_clear_rx_prio_map(struct mvneta_port *pp)
5129 mvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, 0);
5132 static void mvneta_map_vlan_prio_to_rxq(struct mvneta_port *pp, u8 pri, u8 rxq)
5134 u32 val = mvreg_read(pp, MVNETA_VLAN_PRIO_TO_RXQ);
5136 val &= ~MVNETA_VLAN_PRIO_RXQ_MAP(pri, 0x7);
5137 val |= MVNETA_VLAN_PRIO_RXQ_MAP(pri, rxq);
5139 mvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, val);
5142 static int mvneta_enable_per_queue_rate_limit(struct mvneta_port *pp)
5144 unsigned long core_clk_rate;
5148 core_clk_rate = clk_get_rate(pp->clk);
5152 refill_cycles = MVNETA_TXQ_BUCKET_REFILL_BASE_PERIOD_NS /
5153 (NSEC_PER_SEC / core_clk_rate);
5155 if (refill_cycles > MVNETA_REFILL_MAX_NUM_CLK)
5158 /* Enable bw limit algorithm version 3 */
5159 val = mvreg_read(pp, MVNETA_TXQ_CMD1_REG);
5160 val &= ~(MVNETA_TXQ_CMD1_BW_LIM_SEL_V1 | MVNETA_TXQ_CMD1_BW_LIM_EN);
5161 mvreg_write(pp, MVNETA_TXQ_CMD1_REG, val);
5163 /* Set the base refill rate */
5164 mvreg_write(pp, MVNETA_REFILL_NUM_CLK_REG, refill_cycles);
5169 static void mvneta_disable_per_queue_rate_limit(struct mvneta_port *pp)
5171 u32 val = mvreg_read(pp, MVNETA_TXQ_CMD1_REG);
5173 val |= (MVNETA_TXQ_CMD1_BW_LIM_SEL_V1 | MVNETA_TXQ_CMD1_BW_LIM_EN);
5174 mvreg_write(pp, MVNETA_TXQ_CMD1_REG, val);
5177 static int mvneta_setup_queue_rates(struct mvneta_port *pp, int queue,
5178 u64 min_rate, u64 max_rate)
5180 u32 refill_val, rem;
5183 /* Convert to from Bps to bps */
5189 refill_val = div_u64_rem(max_rate, MVNETA_TXQ_RATE_LIMIT_RESOLUTION,
5192 if (rem || !refill_val ||
5193 refill_val > MVNETA_TXQ_BUCKET_REFILL_VALUE_MAX)
5197 val |= (MVNETA_TXQ_BUCKET_REFILL_PERIOD <<
5198 MVNETA_TXQ_BUCKET_REFILL_PERIOD_SHIFT);
5200 mvreg_write(pp, MVNETA_TXQ_BUCKET_REFILL_REG(queue), val);
5205 static int mvneta_setup_mqprio(struct net_device *dev,
5206 struct tc_mqprio_qopt_offload *mqprio)
5208 struct mvneta_port *pp = netdev_priv(dev);
5209 int rxq, txq, tc, ret;
5212 if (mqprio->qopt.hw != TC_MQPRIO_HW_OFFLOAD_TCS)
5215 num_tc = mqprio->qopt.num_tc;
5217 if (num_tc > rxq_number)
5220 mvneta_clear_rx_prio_map(pp);
5223 mvneta_disable_per_queue_rate_limit(pp);
5224 netdev_reset_tc(dev);
5228 netdev_set_num_tc(dev, mqprio->qopt.num_tc);
5230 for (tc = 0; tc < mqprio->qopt.num_tc; tc++) {
5231 netdev_set_tc_queue(dev, tc, mqprio->qopt.count[tc],
5232 mqprio->qopt.offset[tc]);
5234 for (rxq = mqprio->qopt.offset[tc];
5235 rxq < mqprio->qopt.count[tc] + mqprio->qopt.offset[tc];
5237 if (rxq >= rxq_number)
5240 mvneta_map_vlan_prio_to_rxq(pp, tc, rxq);
5244 if (mqprio->shaper != TC_MQPRIO_SHAPER_BW_RATE) {
5245 mvneta_disable_per_queue_rate_limit(pp);
5249 if (mqprio->qopt.num_tc > txq_number)
5252 ret = mvneta_enable_per_queue_rate_limit(pp);
5256 for (tc = 0; tc < mqprio->qopt.num_tc; tc++) {
5257 for (txq = mqprio->qopt.offset[tc];
5258 txq < mqprio->qopt.count[tc] + mqprio->qopt.offset[tc];
5260 if (txq >= txq_number)
5263 ret = mvneta_setup_queue_rates(pp, txq,
5264 mqprio->min_rate[tc],
5265 mqprio->max_rate[tc]);
5274 static int mvneta_setup_tc(struct net_device *dev, enum tc_setup_type type,
5278 case TC_SETUP_QDISC_MQPRIO:
5279 return mvneta_setup_mqprio(dev, type_data);
5285 static const struct net_device_ops mvneta_netdev_ops = {
5286 .ndo_open = mvneta_open,
5287 .ndo_stop = mvneta_stop,
5288 .ndo_start_xmit = mvneta_tx,
5289 .ndo_set_rx_mode = mvneta_set_rx_mode,
5290 .ndo_set_mac_address = mvneta_set_mac_addr,
5291 .ndo_change_mtu = mvneta_change_mtu,
5292 .ndo_fix_features = mvneta_fix_features,
5293 .ndo_get_stats64 = mvneta_get_stats64,
5294 .ndo_eth_ioctl = mvneta_ioctl,
5295 .ndo_bpf = mvneta_xdp,
5296 .ndo_xdp_xmit = mvneta_xdp_xmit,
5297 .ndo_setup_tc = mvneta_setup_tc,
5300 static const struct ethtool_ops mvneta_eth_tool_ops = {
5301 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS |
5302 ETHTOOL_COALESCE_MAX_FRAMES,
5303 .nway_reset = mvneta_ethtool_nway_reset,
5304 .get_link = ethtool_op_get_link,
5305 .set_coalesce = mvneta_ethtool_set_coalesce,
5306 .get_coalesce = mvneta_ethtool_get_coalesce,
5307 .get_drvinfo = mvneta_ethtool_get_drvinfo,
5308 .get_ringparam = mvneta_ethtool_get_ringparam,
5309 .set_ringparam = mvneta_ethtool_set_ringparam,
5310 .get_pauseparam = mvneta_ethtool_get_pauseparam,
5311 .set_pauseparam = mvneta_ethtool_set_pauseparam,
5312 .get_strings = mvneta_ethtool_get_strings,
5313 .get_ethtool_stats = mvneta_ethtool_get_stats,
5314 .get_sset_count = mvneta_ethtool_get_sset_count,
5315 .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size,
5316 .get_rxnfc = mvneta_ethtool_get_rxnfc,
5317 .get_rxfh = mvneta_ethtool_get_rxfh,
5318 .set_rxfh = mvneta_ethtool_set_rxfh,
5319 .get_link_ksettings = mvneta_ethtool_get_link_ksettings,
5320 .set_link_ksettings = mvneta_ethtool_set_link_ksettings,
5321 .get_wol = mvneta_ethtool_get_wol,
5322 .set_wol = mvneta_ethtool_set_wol,
5323 .get_eee = mvneta_ethtool_get_eee,
5324 .set_eee = mvneta_ethtool_set_eee,
5328 static int mvneta_init(struct device *dev, struct mvneta_port *pp)
5333 mvneta_port_disable(pp);
5335 /* Set port default values */
5336 mvneta_defaults_set(pp);
5338 pp->txqs = devm_kcalloc(dev, txq_number, sizeof(*pp->txqs), GFP_KERNEL);
5342 /* Initialize TX descriptor rings */
5343 for (queue = 0; queue < txq_number; queue++) {
5344 struct mvneta_tx_queue *txq = &pp->txqs[queue];
5346 txq->size = pp->tx_ring_size;
5347 txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS;
5350 pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*pp->rxqs), GFP_KERNEL);
5354 /* Create Rx descriptor rings */
5355 for (queue = 0; queue < rxq_number; queue++) {
5356 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
5358 rxq->size = pp->rx_ring_size;
5359 rxq->pkts_coal = MVNETA_RX_COAL_PKTS;
5360 rxq->time_coal = MVNETA_RX_COAL_USEC;
5362 = devm_kmalloc_array(pp->dev->dev.parent,
5364 sizeof(*rxq->buf_virt_addr),
5366 if (!rxq->buf_virt_addr)
5373 /* platform glue : initialize decoding windows */
5374 static void mvneta_conf_mbus_windows(struct mvneta_port *pp,
5375 const struct mbus_dram_target_info *dram)
5381 for (i = 0; i < 6; i++) {
5382 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
5383 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
5386 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
5393 for (i = 0; i < dram->num_cs; i++) {
5394 const struct mbus_dram_window *cs = dram->cs + i;
5396 mvreg_write(pp, MVNETA_WIN_BASE(i),
5397 (cs->base & 0xffff0000) |
5398 (cs->mbus_attr << 8) |
5399 dram->mbus_dram_target_id);
5401 mvreg_write(pp, MVNETA_WIN_SIZE(i),
5402 (cs->size - 1) & 0xffff0000);
5404 win_enable &= ~(1 << i);
5405 win_protect |= 3 << (2 * i);
5409 mvreg_write(pp, MVNETA_WIN_BASE(0),
5410 (MVNETA_AC5_CNM_DDR_ATTR << 8) |
5411 MVNETA_AC5_CNM_DDR_TARGET);
5412 /* For Armada3700 open default 4GB Mbus window, leaving
5413 * arbitration of target/attribute to a different layer
5416 mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000);
5417 win_enable &= ~BIT(0);
5421 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
5422 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
5425 /* Power up the port */
5426 static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
5428 /* MAC Cause register should be cleared */
5429 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
5431 if (phy_mode != PHY_INTERFACE_MODE_QSGMII &&
5432 phy_mode != PHY_INTERFACE_MODE_SGMII &&
5433 !phy_interface_mode_is_8023z(phy_mode) &&
5434 !phy_interface_mode_is_rgmii(phy_mode))
5440 /* Device initialization routine */
5441 static int mvneta_probe(struct platform_device *pdev)
5443 struct device_node *dn = pdev->dev.of_node;
5444 struct device_node *bm_node;
5445 struct mvneta_port *pp;
5446 struct net_device *dev;
5447 struct phylink *phylink;
5449 char hw_mac_addr[ETH_ALEN];
5450 phy_interface_t phy_mode;
5451 const char *mac_from;
5456 dev = devm_alloc_etherdev_mqs(&pdev->dev, sizeof(struct mvneta_port),
5457 txq_number, rxq_number);
5461 dev->tx_queue_len = MVNETA_MAX_TXD;
5462 dev->watchdog_timeo = 5 * HZ;
5463 dev->netdev_ops = &mvneta_netdev_ops;
5464 dev->ethtool_ops = &mvneta_eth_tool_ops;
5466 pp = netdev_priv(dev);
5467 spin_lock_init(&pp->lock);
5470 pp->rxq_def = rxq_def;
5471 pp->indir[0] = rxq_def;
5473 err = of_get_phy_mode(dn, &phy_mode);
5475 dev_err(&pdev->dev, "incorrect phy-mode\n");
5479 pp->phy_interface = phy_mode;
5481 comphy = devm_of_phy_get(&pdev->dev, dn, NULL);
5482 if (comphy == ERR_PTR(-EPROBE_DEFER))
5483 return -EPROBE_DEFER;
5488 pp->comphy = comphy;
5490 pp->base = devm_platform_ioremap_resource(pdev, 0);
5491 if (IS_ERR(pp->base))
5492 return PTR_ERR(pp->base);
5494 /* Get special SoC configurations */
5495 if (of_device_is_compatible(dn, "marvell,armada-3700-neta"))
5496 pp->neta_armada3700 = true;
5497 if (of_device_is_compatible(dn, "marvell,armada-ac5-neta")) {
5498 pp->neta_armada3700 = true;
5499 pp->neta_ac5 = true;
5502 dev->irq = irq_of_parse_and_map(dn, 0);
5506 pp->clk = devm_clk_get(&pdev->dev, "core");
5507 if (IS_ERR(pp->clk))
5508 pp->clk = devm_clk_get(&pdev->dev, NULL);
5509 if (IS_ERR(pp->clk)) {
5510 err = PTR_ERR(pp->clk);
5514 clk_prepare_enable(pp->clk);
5516 pp->clk_bus = devm_clk_get(&pdev->dev, "bus");
5517 if (!IS_ERR(pp->clk_bus))
5518 clk_prepare_enable(pp->clk_bus);
5520 pp->phylink_pcs.ops = &mvneta_phylink_pcs_ops;
5521 pp->phylink_pcs.neg_mode = true;
5523 pp->phylink_config.dev = &dev->dev;
5524 pp->phylink_config.type = PHYLINK_NETDEV;
5525 pp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 |
5526 MAC_100 | MAC_1000FD | MAC_2500FD;
5528 phy_interface_set_rgmii(pp->phylink_config.supported_interfaces);
5529 __set_bit(PHY_INTERFACE_MODE_QSGMII,
5530 pp->phylink_config.supported_interfaces);
5532 /* If a COMPHY is present, we can support any of the serdes
5533 * modes and switch between them.
5535 __set_bit(PHY_INTERFACE_MODE_SGMII,
5536 pp->phylink_config.supported_interfaces);
5537 __set_bit(PHY_INTERFACE_MODE_1000BASEX,
5538 pp->phylink_config.supported_interfaces);
5539 __set_bit(PHY_INTERFACE_MODE_2500BASEX,
5540 pp->phylink_config.supported_interfaces);
5541 } else if (phy_mode == PHY_INTERFACE_MODE_2500BASEX) {
5542 /* No COMPHY, with only 2500BASE-X mode supported */
5543 __set_bit(PHY_INTERFACE_MODE_2500BASEX,
5544 pp->phylink_config.supported_interfaces);
5545 } else if (phy_mode == PHY_INTERFACE_MODE_1000BASEX ||
5546 phy_mode == PHY_INTERFACE_MODE_SGMII) {
5547 /* No COMPHY, we can switch between 1000BASE-X and SGMII */
5548 __set_bit(PHY_INTERFACE_MODE_1000BASEX,
5549 pp->phylink_config.supported_interfaces);
5550 __set_bit(PHY_INTERFACE_MODE_SGMII,
5551 pp->phylink_config.supported_interfaces);
5554 phylink = phylink_create(&pp->phylink_config, pdev->dev.fwnode,
5555 phy_mode, &mvneta_phylink_ops);
5556 if (IS_ERR(phylink)) {
5557 err = PTR_ERR(phylink);
5561 pp->phylink = phylink;
5563 /* Alloc per-cpu port structure */
5564 pp->ports = alloc_percpu(struct mvneta_pcpu_port);
5567 goto err_free_phylink;
5570 /* Alloc per-cpu stats */
5571 pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats);
5574 goto err_free_ports;
5577 err = of_get_ethdev_address(dn, dev);
5579 mac_from = "device tree";
5581 mvneta_get_mac_addr(pp, hw_mac_addr);
5582 if (is_valid_ether_addr(hw_mac_addr)) {
5583 mac_from = "hardware";
5584 eth_hw_addr_set(dev, hw_mac_addr);
5586 mac_from = "random";
5587 eth_hw_addr_random(dev);
5591 if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) {
5592 if (tx_csum_limit < 0 ||
5593 tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) {
5594 tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE;
5595 dev_info(&pdev->dev,
5596 "Wrong TX csum limit in DT, set to %dB\n",
5597 MVNETA_TX_CSUM_DEF_SIZE);
5599 } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) {
5600 tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE;
5602 tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE;
5605 pp->tx_csum_limit = tx_csum_limit;
5607 pp->dram_target_info = mv_mbus_dram_info();
5608 /* Armada3700 requires setting default configuration of Mbus
5609 * windows, however without using filled mbus_dram_target_info
5612 if (pp->dram_target_info || pp->neta_armada3700)
5613 mvneta_conf_mbus_windows(pp, pp->dram_target_info);
5615 pp->tx_ring_size = MVNETA_MAX_TXD;
5616 pp->rx_ring_size = MVNETA_MAX_RXD;
5619 SET_NETDEV_DEV(dev, &pdev->dev);
5621 pp->id = global_port_id++;
5623 /* Obtain access to BM resources if enabled and already initialized */
5624 bm_node = of_parse_phandle(dn, "buffer-manager", 0);
5626 pp->bm_priv = mvneta_bm_get(bm_node);
5628 err = mvneta_bm_port_init(pdev, pp);
5630 dev_info(&pdev->dev,
5631 "use SW buffer management\n");
5632 mvneta_bm_put(pp->bm_priv);
5636 /* Set RX packet offset correction for platforms, whose
5637 * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit
5638 * platforms and 0B for 32-bit ones.
5640 pp->rx_offset_correction = max(0,
5642 MVNETA_RX_PKT_OFFSET_CORRECTION);
5644 of_node_put(bm_node);
5646 /* sw buffer management */
5648 pp->rx_offset_correction = MVNETA_SKB_HEADROOM;
5650 err = mvneta_init(&pdev->dev, pp);
5654 err = mvneta_port_power_up(pp, pp->phy_interface);
5656 dev_err(&pdev->dev, "can't power up port\n");
5660 /* Armada3700 network controller does not support per-cpu
5661 * operation, so only single NAPI should be initialized.
5663 if (pp->neta_armada3700) {
5664 netif_napi_add(dev, &pp->napi, mvneta_poll);
5666 for_each_present_cpu(cpu) {
5667 struct mvneta_pcpu_port *port =
5668 per_cpu_ptr(pp->ports, cpu);
5670 netif_napi_add(dev, &port->napi, mvneta_poll);
5675 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
5676 NETIF_F_TSO | NETIF_F_RXCSUM;
5677 dev->hw_features |= dev->features;
5678 dev->vlan_features |= dev->features;
5680 dev->xdp_features = NETDEV_XDP_ACT_BASIC |
5681 NETDEV_XDP_ACT_REDIRECT |
5682 NETDEV_XDP_ACT_NDO_XMIT |
5683 NETDEV_XDP_ACT_RX_SG |
5684 NETDEV_XDP_ACT_NDO_XMIT_SG;
5685 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5686 netif_set_tso_max_segs(dev, MVNETA_MAX_TSO_SEGS);
5688 /* MTU range: 68 - 9676 */
5689 dev->min_mtu = ETH_MIN_MTU;
5690 /* 9676 == 9700 - 20 and rounding to 8 */
5691 dev->max_mtu = 9676;
5693 err = register_netdev(dev);
5695 dev_err(&pdev->dev, "failed to register\n");
5699 netdev_info(dev, "Using %s mac address %pM\n", mac_from,
5702 platform_set_drvdata(pdev, pp->dev);
5708 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
5709 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short,
5711 mvneta_bm_put(pp->bm_priv);
5713 free_percpu(pp->stats);
5715 free_percpu(pp->ports);
5718 phylink_destroy(pp->phylink);
5720 clk_disable_unprepare(pp->clk_bus);
5721 clk_disable_unprepare(pp->clk);
5723 irq_dispose_mapping(dev->irq);
5727 /* Device removal routine */
5728 static int mvneta_remove(struct platform_device *pdev)
5730 struct net_device *dev = platform_get_drvdata(pdev);
5731 struct mvneta_port *pp = netdev_priv(dev);
5733 unregister_netdev(dev);
5734 clk_disable_unprepare(pp->clk_bus);
5735 clk_disable_unprepare(pp->clk);
5736 free_percpu(pp->ports);
5737 free_percpu(pp->stats);
5738 irq_dispose_mapping(dev->irq);
5739 phylink_destroy(pp->phylink);
5742 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
5743 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short,
5745 mvneta_bm_put(pp->bm_priv);
5751 #ifdef CONFIG_PM_SLEEP
5752 static int mvneta_suspend(struct device *device)
5755 struct net_device *dev = dev_get_drvdata(device);
5756 struct mvneta_port *pp = netdev_priv(dev);
5758 if (!netif_running(dev))
5761 if (!pp->neta_armada3700) {
5762 spin_lock(&pp->lock);
5763 pp->is_stopped = true;
5764 spin_unlock(&pp->lock);
5766 cpuhp_state_remove_instance_nocalls(online_hpstate,
5768 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
5773 mvneta_stop_dev(pp);
5776 for (queue = 0; queue < rxq_number; queue++) {
5777 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
5779 mvneta_rxq_drop_pkts(pp, rxq);
5782 for (queue = 0; queue < txq_number; queue++) {
5783 struct mvneta_tx_queue *txq = &pp->txqs[queue];
5785 mvneta_txq_hw_deinit(pp, txq);
5789 netif_device_detach(dev);
5790 clk_disable_unprepare(pp->clk_bus);
5791 clk_disable_unprepare(pp->clk);
5796 static int mvneta_resume(struct device *device)
5798 struct platform_device *pdev = to_platform_device(device);
5799 struct net_device *dev = dev_get_drvdata(device);
5800 struct mvneta_port *pp = netdev_priv(dev);
5803 clk_prepare_enable(pp->clk);
5804 if (!IS_ERR(pp->clk_bus))
5805 clk_prepare_enable(pp->clk_bus);
5806 if (pp->dram_target_info || pp->neta_armada3700)
5807 mvneta_conf_mbus_windows(pp, pp->dram_target_info);
5809 err = mvneta_bm_port_init(pdev, pp);
5811 dev_info(&pdev->dev, "use SW buffer management\n");
5812 pp->rx_offset_correction = MVNETA_SKB_HEADROOM;
5816 mvneta_defaults_set(pp);
5817 err = mvneta_port_power_up(pp, pp->phy_interface);
5819 dev_err(device, "can't power up port\n");
5823 netif_device_attach(dev);
5825 if (!netif_running(dev))
5828 for (queue = 0; queue < rxq_number; queue++) {
5829 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
5831 rxq->next_desc_to_proc = 0;
5832 mvneta_rxq_hw_init(pp, rxq);
5835 for (queue = 0; queue < txq_number; queue++) {
5836 struct mvneta_tx_queue *txq = &pp->txqs[queue];
5838 txq->next_desc_to_proc = 0;
5839 mvneta_txq_hw_init(pp, txq);
5842 if (!pp->neta_armada3700) {
5843 spin_lock(&pp->lock);
5844 pp->is_stopped = false;
5845 spin_unlock(&pp->lock);
5846 cpuhp_state_add_instance_nocalls(online_hpstate,
5848 cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
5853 mvneta_start_dev(pp);
5855 mvneta_set_rx_mode(dev);
5861 static SIMPLE_DEV_PM_OPS(mvneta_pm_ops, mvneta_suspend, mvneta_resume);
5863 static const struct of_device_id mvneta_match[] = {
5864 { .compatible = "marvell,armada-370-neta" },
5865 { .compatible = "marvell,armada-xp-neta" },
5866 { .compatible = "marvell,armada-3700-neta" },
5867 { .compatible = "marvell,armada-ac5-neta" },
5870 MODULE_DEVICE_TABLE(of, mvneta_match);
5872 static struct platform_driver mvneta_driver = {
5873 .probe = mvneta_probe,
5874 .remove = mvneta_remove,
5876 .name = MVNETA_DRIVER_NAME,
5877 .of_match_table = mvneta_match,
5878 .pm = &mvneta_pm_ops,
5882 static int __init mvneta_driver_init(void)
5886 BUILD_BUG_ON_NOT_POWER_OF_2(MVNETA_TSO_PER_PAGE);
5888 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/mvneta:online",
5890 mvneta_cpu_down_prepare);
5893 online_hpstate = ret;
5894 ret = cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD, "net/mvneta:dead",
5895 NULL, mvneta_cpu_dead);
5899 ret = platform_driver_register(&mvneta_driver);
5905 cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD);
5907 cpuhp_remove_multi_state(online_hpstate);
5911 module_init(mvneta_driver_init);
5913 static void __exit mvneta_driver_exit(void)
5915 platform_driver_unregister(&mvneta_driver);
5916 cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD);
5917 cpuhp_remove_multi_state(online_hpstate);
5919 module_exit(mvneta_driver_exit);
5921 MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com");
5922 MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
5923 MODULE_LICENSE("GPL");
5925 module_param(rxq_number, int, 0444);
5926 module_param(txq_number, int, 0444);
5928 module_param(rxq_def, int, 0444);
5929 module_param(rx_copybreak, int, 0644);