1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
4 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
6 * Based on the 64360 driver from:
7 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
8 * Rabeeh Khoury <rabeeh@marvell.com>
10 * Copyright (C) 2003 PMC-Sierra, Inc.,
11 * written by Manish Lachwani
13 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
15 * Copyright (C) 2004-2006 MontaVista Software, Inc.
16 * Dale Farnsworth <dale@farnsworth.org>
18 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
19 * <sjhill@realitydiluted.com>
21 * Copyright (C) 2007-2008 Marvell Semiconductor
22 * Lennert Buytenhek <buytenh@marvell.com>
24 * Copyright (C) 2013 Michael Stapelberg <michael@stapelberg.de>
27 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29 #include <linux/init.h>
30 #include <linux/dma-mapping.h>
34 #include <linux/tcp.h>
35 #include <linux/udp.h>
36 #include <linux/etherdevice.h>
37 #include <linux/delay.h>
38 #include <linux/ethtool.h>
39 #include <linux/platform_device.h>
40 #include <linux/module.h>
41 #include <linux/kernel.h>
42 #include <linux/spinlock.h>
43 #include <linux/workqueue.h>
44 #include <linux/phy.h>
45 #include <linux/mv643xx_eth.h>
47 #include <linux/interrupt.h>
48 #include <linux/types.h>
49 #include <linux/slab.h>
50 #include <linux/clk.h>
52 #include <linux/of_irq.h>
53 #include <linux/of_net.h>
54 #include <linux/of_mdio.h>
56 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
57 static char mv643xx_eth_driver_version[] = "1.4";
61 * Registers shared between all ports.
63 #define PHY_ADDR 0x0000
64 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
65 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
66 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
67 #define WINDOW_BAR_ENABLE 0x0290
68 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
71 * Main per-port registers. These live at offset 0x0400 for
72 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
74 #define PORT_CONFIG 0x0000
75 #define UNICAST_PROMISCUOUS_MODE 0x00000001
76 #define PORT_CONFIG_EXT 0x0004
77 #define MAC_ADDR_LOW 0x0014
78 #define MAC_ADDR_HIGH 0x0018
79 #define SDMA_CONFIG 0x001c
80 #define TX_BURST_SIZE_16_64BIT 0x01000000
81 #define TX_BURST_SIZE_4_64BIT 0x00800000
82 #define BLM_TX_NO_SWAP 0x00000020
83 #define BLM_RX_NO_SWAP 0x00000010
84 #define RX_BURST_SIZE_16_64BIT 0x00000008
85 #define RX_BURST_SIZE_4_64BIT 0x00000004
86 #define PORT_SERIAL_CONTROL 0x003c
87 #define SET_MII_SPEED_TO_100 0x01000000
88 #define SET_GMII_SPEED_TO_1000 0x00800000
89 #define SET_FULL_DUPLEX_MODE 0x00200000
90 #define MAX_RX_PACKET_9700BYTE 0x000a0000
91 #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
92 #define DO_NOT_FORCE_LINK_FAIL 0x00000400
93 #define SERIAL_PORT_CONTROL_RESERVED 0x00000200
94 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
95 #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
96 #define FORCE_LINK_PASS 0x00000002
97 #define SERIAL_PORT_ENABLE 0x00000001
98 #define PORT_STATUS 0x0044
99 #define TX_FIFO_EMPTY 0x00000400
100 #define TX_IN_PROGRESS 0x00000080
101 #define PORT_SPEED_MASK 0x00000030
102 #define PORT_SPEED_1000 0x00000010
103 #define PORT_SPEED_100 0x00000020
104 #define PORT_SPEED_10 0x00000000
105 #define FLOW_CONTROL_ENABLED 0x00000008
106 #define FULL_DUPLEX 0x00000004
107 #define LINK_UP 0x00000002
108 #define TXQ_COMMAND 0x0048
109 #define TXQ_FIX_PRIO_CONF 0x004c
110 #define PORT_SERIAL_CONTROL1 0x004c
111 #define CLK125_BYPASS_EN 0x00000010
112 #define TX_BW_RATE 0x0050
113 #define TX_BW_MTU 0x0058
114 #define TX_BW_BURST 0x005c
115 #define INT_CAUSE 0x0060
116 #define INT_TX_END 0x07f80000
117 #define INT_TX_END_0 0x00080000
118 #define INT_RX 0x000003fc
119 #define INT_RX_0 0x00000004
120 #define INT_EXT 0x00000002
121 #define INT_CAUSE_EXT 0x0064
122 #define INT_EXT_LINK_PHY 0x00110000
123 #define INT_EXT_TX 0x000000ff
124 #define INT_MASK 0x0068
125 #define INT_MASK_EXT 0x006c
126 #define TX_FIFO_URGENT_THRESHOLD 0x0074
127 #define RX_DISCARD_FRAME_CNT 0x0084
128 #define RX_OVERRUN_FRAME_CNT 0x0088
129 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
130 #define TX_BW_RATE_MOVED 0x00e0
131 #define TX_BW_MTU_MOVED 0x00e8
132 #define TX_BW_BURST_MOVED 0x00ec
133 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
134 #define RXQ_COMMAND 0x0280
135 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
136 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
137 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
138 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
141 * Misc per-port registers.
143 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
144 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
145 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
146 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
150 * SDMA configuration register default value.
152 #if defined(__BIG_ENDIAN)
153 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
154 (RX_BURST_SIZE_4_64BIT | \
155 TX_BURST_SIZE_4_64BIT)
156 #elif defined(__LITTLE_ENDIAN)
157 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
158 (RX_BURST_SIZE_4_64BIT | \
161 TX_BURST_SIZE_4_64BIT)
163 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
170 #define DEFAULT_RX_QUEUE_SIZE 128
171 #define DEFAULT_TX_QUEUE_SIZE 512
172 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
174 /* Max number of allowed TCP segments for software TSO */
175 #define MV643XX_MAX_TSO_SEGS 100
176 #define MV643XX_MAX_SKB_DESCS (MV643XX_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
178 #define IS_TSO_HEADER(txq, addr) \
179 ((addr >= txq->tso_hdrs_dma) && \
180 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
182 #define DESC_DMA_MAP_SINGLE 0
183 #define DESC_DMA_MAP_PAGE 1
188 #if defined(__BIG_ENDIAN)
190 u16 byte_cnt; /* Descriptor buffer byte count */
191 u16 buf_size; /* Buffer size */
192 u32 cmd_sts; /* Descriptor command status */
193 u32 next_desc_ptr; /* Next descriptor pointer */
194 u32 buf_ptr; /* Descriptor buffer pointer */
198 u16 byte_cnt; /* buffer byte count */
199 u16 l4i_chk; /* CPU provided TCP checksum */
200 u32 cmd_sts; /* Command/status field */
201 u32 next_desc_ptr; /* Pointer to next descriptor */
202 u32 buf_ptr; /* pointer to buffer for this descriptor*/
204 #elif defined(__LITTLE_ENDIAN)
206 u32 cmd_sts; /* Descriptor command status */
207 u16 buf_size; /* Buffer size */
208 u16 byte_cnt; /* Descriptor buffer byte count */
209 u32 buf_ptr; /* Descriptor buffer pointer */
210 u32 next_desc_ptr; /* Next descriptor pointer */
214 u32 cmd_sts; /* Command/status field */
215 u16 l4i_chk; /* CPU provided TCP checksum */
216 u16 byte_cnt; /* buffer byte count */
217 u32 buf_ptr; /* pointer to buffer for this descriptor*/
218 u32 next_desc_ptr; /* Pointer to next descriptor */
221 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
224 /* RX & TX descriptor command */
225 #define BUFFER_OWNED_BY_DMA 0x80000000
227 /* RX & TX descriptor status */
228 #define ERROR_SUMMARY 0x00000001
230 /* RX descriptor status */
231 #define LAYER_4_CHECKSUM_OK 0x40000000
232 #define RX_ENABLE_INTERRUPT 0x20000000
233 #define RX_FIRST_DESC 0x08000000
234 #define RX_LAST_DESC 0x04000000
235 #define RX_IP_HDR_OK 0x02000000
236 #define RX_PKT_IS_IPV4 0x01000000
237 #define RX_PKT_IS_ETHERNETV2 0x00800000
238 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000
239 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
240 #define RX_PKT_IS_VLAN_TAGGED 0x00080000
242 /* TX descriptor command */
243 #define TX_ENABLE_INTERRUPT 0x00800000
244 #define GEN_CRC 0x00400000
245 #define TX_FIRST_DESC 0x00200000
246 #define TX_LAST_DESC 0x00100000
247 #define ZERO_PADDING 0x00080000
248 #define GEN_IP_V4_CHECKSUM 0x00040000
249 #define GEN_TCP_UDP_CHECKSUM 0x00020000
250 #define UDP_FRAME 0x00010000
251 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
252 #define GEN_TCP_UDP_CHK_FULL 0x00000400
253 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
255 #define TX_IHL_SHIFT 11
258 /* global *******************************************************************/
259 struct mv643xx_eth_shared_private {
261 * Ethernet controller base address.
266 * Per-port MBUS window access register value.
271 * Hardware-specific parameters.
273 int extended_rx_coal_limit;
279 #define TX_BW_CONTROL_ABSENT 0
280 #define TX_BW_CONTROL_OLD_LAYOUT 1
281 #define TX_BW_CONTROL_NEW_LAYOUT 2
283 static int mv643xx_eth_open(struct net_device *dev);
284 static int mv643xx_eth_stop(struct net_device *dev);
287 /* per-port *****************************************************************/
288 struct mib_counters {
289 u64 good_octets_received;
290 u32 bad_octets_received;
291 u32 internal_mac_transmit_err;
292 u32 good_frames_received;
293 u32 bad_frames_received;
294 u32 broadcast_frames_received;
295 u32 multicast_frames_received;
296 u32 frames_64_octets;
297 u32 frames_65_to_127_octets;
298 u32 frames_128_to_255_octets;
299 u32 frames_256_to_511_octets;
300 u32 frames_512_to_1023_octets;
301 u32 frames_1024_to_max_octets;
302 u64 good_octets_sent;
303 u32 good_frames_sent;
304 u32 excessive_collision;
305 u32 multicast_frames_sent;
306 u32 broadcast_frames_sent;
307 u32 unrec_mac_control_received;
309 u32 good_fc_received;
311 u32 undersize_received;
312 u32 fragments_received;
313 u32 oversize_received;
315 u32 mac_receive_error;
319 /* Non MIB hardware counters */
333 struct rx_desc *rx_desc_area;
334 dma_addr_t rx_desc_dma;
335 int rx_desc_area_size;
336 struct sk_buff **rx_skb;
348 int tx_stop_threshold;
349 int tx_wake_threshold;
352 dma_addr_t tso_hdrs_dma;
354 struct tx_desc *tx_desc_area;
355 char *tx_desc_mapping; /* array to track the type of the dma mapping */
356 dma_addr_t tx_desc_dma;
357 int tx_desc_area_size;
359 struct sk_buff_head tx_skb;
361 unsigned long tx_packets;
362 unsigned long tx_bytes;
363 unsigned long tx_dropped;
366 struct mv643xx_eth_private {
367 struct mv643xx_eth_shared_private *shared;
371 struct net_device *dev;
373 struct timer_list mib_counters_timer;
374 spinlock_t mib_counters_lock;
375 struct mib_counters mib_counters;
377 struct work_struct tx_timeout_task;
379 struct napi_struct napi;
394 unsigned long rx_desc_sram_addr;
395 int rx_desc_sram_size;
397 struct timer_list rx_oom;
398 struct rx_queue rxq[8];
404 unsigned long tx_desc_sram_addr;
405 int tx_desc_sram_size;
407 struct tx_queue txq[8];
410 * Hardware-specific parameters.
417 /* port register accessors **************************************************/
418 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
420 return readl(mp->shared->base + offset);
423 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
425 return readl(mp->base + offset);
428 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
430 writel(data, mp->shared->base + offset);
433 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
435 writel(data, mp->base + offset);
439 /* rxq/txq helper functions *************************************************/
440 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
442 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
445 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
447 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
450 static void rxq_enable(struct rx_queue *rxq)
452 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
453 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
456 static void rxq_disable(struct rx_queue *rxq)
458 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
459 u8 mask = 1 << rxq->index;
461 wrlp(mp, RXQ_COMMAND, mask << 8);
462 while (rdlp(mp, RXQ_COMMAND) & mask)
466 static void txq_reset_hw_ptr(struct tx_queue *txq)
468 struct mv643xx_eth_private *mp = txq_to_mp(txq);
471 addr = (u32)txq->tx_desc_dma;
472 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
473 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
476 static void txq_enable(struct tx_queue *txq)
478 struct mv643xx_eth_private *mp = txq_to_mp(txq);
479 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
482 static void txq_disable(struct tx_queue *txq)
484 struct mv643xx_eth_private *mp = txq_to_mp(txq);
485 u8 mask = 1 << txq->index;
487 wrlp(mp, TXQ_COMMAND, mask << 8);
488 while (rdlp(mp, TXQ_COMMAND) & mask)
492 static void txq_maybe_wake(struct tx_queue *txq)
494 struct mv643xx_eth_private *mp = txq_to_mp(txq);
495 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
497 if (netif_tx_queue_stopped(nq)) {
498 __netif_tx_lock(nq, smp_processor_id());
499 if (txq->tx_desc_count <= txq->tx_wake_threshold)
500 netif_tx_wake_queue(nq);
501 __netif_tx_unlock(nq);
505 static int rxq_process(struct rx_queue *rxq, int budget)
507 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
508 struct net_device_stats *stats = &mp->dev->stats;
512 while (rx < budget && rxq->rx_desc_count) {
513 struct rx_desc *rx_desc;
514 unsigned int cmd_sts;
518 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
520 cmd_sts = rx_desc->cmd_sts;
521 if (cmd_sts & BUFFER_OWNED_BY_DMA)
525 skb = rxq->rx_skb[rxq->rx_curr_desc];
526 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
529 if (rxq->rx_curr_desc == rxq->rx_ring_size)
530 rxq->rx_curr_desc = 0;
532 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
533 rx_desc->buf_size, DMA_FROM_DEVICE);
534 rxq->rx_desc_count--;
537 mp->work_rx_refill |= 1 << rxq->index;
539 byte_cnt = rx_desc->byte_cnt;
544 * Note that the descriptor byte count includes 2 dummy
545 * bytes automatically inserted by the hardware at the
546 * start of the packet (which we don't count), and a 4
547 * byte CRC at the end of the packet (which we do count).
550 stats->rx_bytes += byte_cnt - 2;
553 * In case we received a packet without first / last bits
554 * on, or the error summary bit is set, the packet needs
557 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
558 != (RX_FIRST_DESC | RX_LAST_DESC))
562 * The -4 is for the CRC in the trailer of the
565 skb_put(skb, byte_cnt - 2 - 4);
567 if (cmd_sts & LAYER_4_CHECKSUM_OK)
568 skb->ip_summed = CHECKSUM_UNNECESSARY;
569 skb->protocol = eth_type_trans(skb, mp->dev);
571 napi_gro_receive(&mp->napi, skb);
578 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
579 (RX_FIRST_DESC | RX_LAST_DESC)) {
582 "received packet spanning multiple descriptors\n");
585 if (cmd_sts & ERROR_SUMMARY)
592 mp->work_rx &= ~(1 << rxq->index);
597 static int rxq_refill(struct rx_queue *rxq, int budget)
599 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
603 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
606 struct rx_desc *rx_desc;
609 skb = netdev_alloc_skb(mp->dev, mp->skb_size);
617 skb_reserve(skb, SKB_DMA_REALIGN);
620 rxq->rx_desc_count++;
622 rx = rxq->rx_used_desc++;
623 if (rxq->rx_used_desc == rxq->rx_ring_size)
624 rxq->rx_used_desc = 0;
626 rx_desc = rxq->rx_desc_area + rx;
628 size = skb_end_pointer(skb) - skb->data;
629 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
632 rx_desc->buf_size = size;
633 rxq->rx_skb[rx] = skb;
635 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
639 * The hardware automatically prepends 2 bytes of
640 * dummy data to each received packet, so that the
641 * IP header ends up 16-byte aligned.
646 if (refilled < budget)
647 mp->work_rx_refill &= ~(1 << rxq->index);
654 /* tx ***********************************************************************/
655 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
659 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
660 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
662 if (skb_frag_size(fragp) <= 8 && skb_frag_off(fragp) & 7)
669 static int skb_tx_csum(struct mv643xx_eth_private *mp, struct sk_buff *skb,
670 u16 *l4i_chk, u32 *command, int length)
675 if (skb->ip_summed == CHECKSUM_PARTIAL) {
679 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
680 skb->protocol != htons(ETH_P_8021Q));
682 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
683 tag_bytes = hdr_len - ETH_HLEN;
685 if (length - hdr_len > mp->shared->tx_csum_limit ||
686 unlikely(tag_bytes & ~12)) {
687 ret = skb_checksum_help(skb);
694 cmd |= MAC_HDR_EXTRA_4_BYTES;
696 cmd |= MAC_HDR_EXTRA_8_BYTES;
698 cmd |= GEN_TCP_UDP_CHECKSUM | GEN_TCP_UDP_CHK_FULL |
700 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
702 /* TODO: Revisit this. With the usage of GEN_TCP_UDP_CHK_FULL
703 * it seems we don't need to pass the initial checksum.
705 switch (ip_hdr(skb)->protocol) {
714 WARN(1, "protocol not supported");
718 /* Errata BTS #50, IHL must be 5 if no HW checksum */
719 cmd |= 5 << TX_IHL_SHIFT;
726 txq_put_data_tso(struct net_device *dev, struct tx_queue *txq,
727 struct sk_buff *skb, char *data, int length,
728 bool last_tcp, bool is_last)
732 struct tx_desc *desc;
734 tx_index = txq->tx_curr_desc++;
735 if (txq->tx_curr_desc == txq->tx_ring_size)
736 txq->tx_curr_desc = 0;
737 desc = &txq->tx_desc_area[tx_index];
738 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
741 desc->byte_cnt = length;
743 if (length <= 8 && (uintptr_t)data & 0x7) {
744 /* Copy unaligned small data fragment to TSO header data area */
745 memcpy(txq->tso_hdrs + tx_index * TSO_HEADER_SIZE,
747 desc->buf_ptr = txq->tso_hdrs_dma
748 + tx_index * TSO_HEADER_SIZE;
750 /* Alignment is okay, map buffer and hand off to hardware */
751 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
752 desc->buf_ptr = dma_map_single(dev->dev.parent, data,
753 length, DMA_TO_DEVICE);
754 if (unlikely(dma_mapping_error(dev->dev.parent,
756 WARN(1, "dma_map_single failed!\n");
761 cmd_sts = BUFFER_OWNED_BY_DMA;
763 /* last descriptor in the TCP packet */
764 cmd_sts |= ZERO_PADDING | TX_LAST_DESC;
765 /* last descriptor in SKB */
767 cmd_sts |= TX_ENABLE_INTERRUPT;
769 desc->cmd_sts = cmd_sts;
774 txq_put_hdr_tso(struct sk_buff *skb, struct tx_queue *txq, int length,
775 u32 *first_cmd_sts, bool first_desc)
777 struct mv643xx_eth_private *mp = txq_to_mp(txq);
778 int hdr_len = skb_tcp_all_headers(skb);
780 struct tx_desc *desc;
786 tx_index = txq->tx_curr_desc;
787 desc = &txq->tx_desc_area[tx_index];
789 ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_csum, length);
791 WARN(1, "failed to prepare checksum!");
793 /* Should we set this? Can't use the value from skb_tx_csum()
794 * as it's not the correct initial L4 checksum to use.
798 desc->byte_cnt = hdr_len;
799 desc->buf_ptr = txq->tso_hdrs_dma +
800 txq->tx_curr_desc * TSO_HEADER_SIZE;
801 cmd_sts = cmd_csum | BUFFER_OWNED_BY_DMA | TX_FIRST_DESC |
804 /* Defer updating the first command descriptor until all
805 * following descriptors have been written.
808 *first_cmd_sts = cmd_sts;
810 desc->cmd_sts = cmd_sts;
813 if (txq->tx_curr_desc == txq->tx_ring_size)
814 txq->tx_curr_desc = 0;
817 static int txq_submit_tso(struct tx_queue *txq, struct sk_buff *skb,
818 struct net_device *dev)
820 struct mv643xx_eth_private *mp = txq_to_mp(txq);
821 int hdr_len, total_len, data_left, ret;
824 struct tx_desc *first_tx_desc;
825 u32 first_cmd_sts = 0;
827 /* Count needed descriptors */
828 if ((txq->tx_desc_count + tso_count_descs(skb)) >= txq->tx_ring_size) {
829 netdev_dbg(dev, "not enough descriptors for TSO!\n");
833 first_tx_desc = &txq->tx_desc_area[txq->tx_curr_desc];
835 /* Initialize the TSO handler, and prepare the first payload */
836 hdr_len = tso_start(skb, &tso);
838 total_len = skb->len - hdr_len;
839 while (total_len > 0) {
840 bool first_desc = (desc_count == 0);
843 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
844 total_len -= data_left;
847 /* prepare packet headers: MAC + IP + TCP */
848 hdr = txq->tso_hdrs + txq->tx_curr_desc * TSO_HEADER_SIZE;
849 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
850 txq_put_hdr_tso(skb, txq, data_left, &first_cmd_sts,
853 while (data_left > 0) {
857 size = min_t(int, tso.size, data_left);
858 ret = txq_put_data_tso(dev, txq, skb, tso.data, size,
864 tso_build_data(skb, &tso, size);
868 __skb_queue_tail(&txq->tx_skb, skb);
869 skb_tx_timestamp(skb);
871 /* ensure all other descriptors are written before first cmd_sts */
873 first_tx_desc->cmd_sts = first_cmd_sts;
875 /* clear TX_END status */
876 mp->work_tx_end &= ~(1 << txq->index);
878 /* ensure all descriptors are written before poking hardware */
881 txq->tx_desc_count += desc_count;
884 /* TODO: Release all used data descriptors; header descriptors must not
890 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
892 struct mv643xx_eth_private *mp = txq_to_mp(txq);
893 int nr_frags = skb_shinfo(skb)->nr_frags;
896 for (frag = 0; frag < nr_frags; frag++) {
897 skb_frag_t *this_frag;
899 struct tx_desc *desc;
901 this_frag = &skb_shinfo(skb)->frags[frag];
902 tx_index = txq->tx_curr_desc++;
903 if (txq->tx_curr_desc == txq->tx_ring_size)
904 txq->tx_curr_desc = 0;
905 desc = &txq->tx_desc_area[tx_index];
906 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_PAGE;
909 * The last fragment will generate an interrupt
910 * which will free the skb on TX completion.
912 if (frag == nr_frags - 1) {
913 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
914 ZERO_PADDING | TX_LAST_DESC |
917 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
921 desc->byte_cnt = skb_frag_size(this_frag);
922 desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent,
923 this_frag, 0, desc->byte_cnt,
928 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb,
929 struct net_device *dev)
931 struct mv643xx_eth_private *mp = txq_to_mp(txq);
932 int nr_frags = skb_shinfo(skb)->nr_frags;
934 struct tx_desc *desc;
942 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
944 netdev_err(dev, "tx queue full?!\n");
948 ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_sts, skb->len);
951 cmd_sts |= TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
953 tx_index = txq->tx_curr_desc++;
954 if (txq->tx_curr_desc == txq->tx_ring_size)
955 txq->tx_curr_desc = 0;
956 desc = &txq->tx_desc_area[tx_index];
957 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
960 txq_submit_frag_skb(txq, skb);
961 length = skb_headlen(skb);
963 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
967 desc->l4i_chk = l4i_chk;
968 desc->byte_cnt = length;
969 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
970 length, DMA_TO_DEVICE);
972 __skb_queue_tail(&txq->tx_skb, skb);
974 skb_tx_timestamp(skb);
976 /* ensure all other descriptors are written before first cmd_sts */
978 desc->cmd_sts = cmd_sts;
980 /* clear TX_END status */
981 mp->work_tx_end &= ~(1 << txq->index);
983 /* ensure all descriptors are written before poking hardware */
987 txq->tx_desc_count += nr_frags + 1;
992 static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
994 struct mv643xx_eth_private *mp = netdev_priv(dev);
995 int length, queue, ret;
996 struct tx_queue *txq;
997 struct netdev_queue *nq;
999 queue = skb_get_queue_mapping(skb);
1000 txq = mp->txq + queue;
1001 nq = netdev_get_tx_queue(dev, queue);
1003 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
1004 netdev_printk(KERN_DEBUG, dev,
1005 "failed to linearize skb with tiny unaligned fragment\n");
1006 return NETDEV_TX_BUSY;
1011 if (skb_is_gso(skb))
1012 ret = txq_submit_tso(txq, skb, dev);
1014 ret = txq_submit_skb(txq, skb, dev);
1016 txq->tx_bytes += length;
1019 if (txq->tx_desc_count >= txq->tx_stop_threshold)
1020 netif_tx_stop_queue(nq);
1023 dev_kfree_skb_any(skb);
1026 return NETDEV_TX_OK;
1030 /* tx napi ******************************************************************/
1031 static void txq_kick(struct tx_queue *txq)
1033 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1034 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1038 __netif_tx_lock(nq, smp_processor_id());
1040 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
1043 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
1044 expected_ptr = (u32)txq->tx_desc_dma +
1045 txq->tx_curr_desc * sizeof(struct tx_desc);
1047 if (hw_desc_ptr != expected_ptr)
1051 __netif_tx_unlock(nq);
1053 mp->work_tx_end &= ~(1 << txq->index);
1056 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
1058 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1059 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1062 __netif_tx_lock_bh(nq);
1065 while (reclaimed < budget && txq->tx_desc_count > 0) {
1067 struct tx_desc *desc;
1071 tx_index = txq->tx_used_desc;
1072 desc = &txq->tx_desc_area[tx_index];
1073 desc_dma_map = txq->tx_desc_mapping[tx_index];
1075 cmd_sts = desc->cmd_sts;
1077 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1080 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1083 txq->tx_used_desc = tx_index + 1;
1084 if (txq->tx_used_desc == txq->tx_ring_size)
1085 txq->tx_used_desc = 0;
1088 txq->tx_desc_count--;
1090 if (!IS_TSO_HEADER(txq, desc->buf_ptr)) {
1092 if (desc_dma_map == DESC_DMA_MAP_PAGE)
1093 dma_unmap_page(mp->dev->dev.parent,
1098 dma_unmap_single(mp->dev->dev.parent,
1104 if (cmd_sts & TX_ENABLE_INTERRUPT) {
1105 struct sk_buff *skb = __skb_dequeue(&txq->tx_skb);
1108 dev_consume_skb_any(skb);
1111 if (cmd_sts & ERROR_SUMMARY) {
1112 netdev_info(mp->dev, "tx error\n");
1113 mp->dev->stats.tx_errors++;
1118 __netif_tx_unlock_bh(nq);
1120 if (reclaimed < budget)
1121 mp->work_tx &= ~(1 << txq->index);
1127 /* tx rate control **********************************************************/
1129 * Set total maximum TX rate (shared by all TX queues for this port)
1130 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
1132 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
1138 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
1139 if (token_rate > 1023)
1142 mtu = (mp->dev->mtu + 255) >> 8;
1146 bucket_size = (burst + 255) >> 8;
1147 if (bucket_size > 65535)
1148 bucket_size = 65535;
1150 switch (mp->shared->tx_bw_control) {
1151 case TX_BW_CONTROL_OLD_LAYOUT:
1152 wrlp(mp, TX_BW_RATE, token_rate);
1153 wrlp(mp, TX_BW_MTU, mtu);
1154 wrlp(mp, TX_BW_BURST, bucket_size);
1156 case TX_BW_CONTROL_NEW_LAYOUT:
1157 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1158 wrlp(mp, TX_BW_MTU_MOVED, mtu);
1159 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
1164 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1166 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1170 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
1171 if (token_rate > 1023)
1174 bucket_size = (burst + 255) >> 8;
1175 if (bucket_size > 65535)
1176 bucket_size = 65535;
1178 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1179 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
1182 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1184 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1189 * Turn on fixed priority mode.
1192 switch (mp->shared->tx_bw_control) {
1193 case TX_BW_CONTROL_OLD_LAYOUT:
1194 off = TXQ_FIX_PRIO_CONF;
1196 case TX_BW_CONTROL_NEW_LAYOUT:
1197 off = TXQ_FIX_PRIO_CONF_MOVED;
1202 val = rdlp(mp, off);
1203 val |= 1 << txq->index;
1209 /* mii management interface *************************************************/
1210 static void mv643xx_eth_adjust_link(struct net_device *dev)
1212 struct mv643xx_eth_private *mp = netdev_priv(dev);
1213 u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
1214 u32 autoneg_disable = FORCE_LINK_PASS |
1215 DISABLE_AUTO_NEG_SPEED_GMII |
1216 DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1217 DISABLE_AUTO_NEG_FOR_DUPLEX;
1219 if (dev->phydev->autoneg == AUTONEG_ENABLE) {
1220 /* enable auto negotiation */
1221 pscr &= ~autoneg_disable;
1225 pscr |= autoneg_disable;
1227 if (dev->phydev->speed == SPEED_1000) {
1228 /* force gigabit, half duplex not supported */
1229 pscr |= SET_GMII_SPEED_TO_1000;
1230 pscr |= SET_FULL_DUPLEX_MODE;
1234 pscr &= ~SET_GMII_SPEED_TO_1000;
1236 if (dev->phydev->speed == SPEED_100)
1237 pscr |= SET_MII_SPEED_TO_100;
1239 pscr &= ~SET_MII_SPEED_TO_100;
1241 if (dev->phydev->duplex == DUPLEX_FULL)
1242 pscr |= SET_FULL_DUPLEX_MODE;
1244 pscr &= ~SET_FULL_DUPLEX_MODE;
1247 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
1250 /* statistics ***************************************************************/
1251 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1253 struct mv643xx_eth_private *mp = netdev_priv(dev);
1254 struct net_device_stats *stats = &dev->stats;
1255 unsigned long tx_packets = 0;
1256 unsigned long tx_bytes = 0;
1257 unsigned long tx_dropped = 0;
1260 for (i = 0; i < mp->txq_count; i++) {
1261 struct tx_queue *txq = mp->txq + i;
1263 tx_packets += txq->tx_packets;
1264 tx_bytes += txq->tx_bytes;
1265 tx_dropped += txq->tx_dropped;
1268 stats->tx_packets = tx_packets;
1269 stats->tx_bytes = tx_bytes;
1270 stats->tx_dropped = tx_dropped;
1275 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1277 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1280 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1284 for (i = 0; i < 0x80; i += 4)
1287 /* Clear non MIB hw counters also */
1288 rdlp(mp, RX_DISCARD_FRAME_CNT);
1289 rdlp(mp, RX_OVERRUN_FRAME_CNT);
1292 static void mib_counters_update(struct mv643xx_eth_private *mp)
1294 struct mib_counters *p = &mp->mib_counters;
1296 spin_lock_bh(&mp->mib_counters_lock);
1297 p->good_octets_received += mib_read(mp, 0x00);
1298 p->bad_octets_received += mib_read(mp, 0x08);
1299 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1300 p->good_frames_received += mib_read(mp, 0x10);
1301 p->bad_frames_received += mib_read(mp, 0x14);
1302 p->broadcast_frames_received += mib_read(mp, 0x18);
1303 p->multicast_frames_received += mib_read(mp, 0x1c);
1304 p->frames_64_octets += mib_read(mp, 0x20);
1305 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1306 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1307 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1308 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1309 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1310 p->good_octets_sent += mib_read(mp, 0x38);
1311 p->good_frames_sent += mib_read(mp, 0x40);
1312 p->excessive_collision += mib_read(mp, 0x44);
1313 p->multicast_frames_sent += mib_read(mp, 0x48);
1314 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1315 p->unrec_mac_control_received += mib_read(mp, 0x50);
1316 p->fc_sent += mib_read(mp, 0x54);
1317 p->good_fc_received += mib_read(mp, 0x58);
1318 p->bad_fc_received += mib_read(mp, 0x5c);
1319 p->undersize_received += mib_read(mp, 0x60);
1320 p->fragments_received += mib_read(mp, 0x64);
1321 p->oversize_received += mib_read(mp, 0x68);
1322 p->jabber_received += mib_read(mp, 0x6c);
1323 p->mac_receive_error += mib_read(mp, 0x70);
1324 p->bad_crc_event += mib_read(mp, 0x74);
1325 p->collision += mib_read(mp, 0x78);
1326 p->late_collision += mib_read(mp, 0x7c);
1327 /* Non MIB hardware counters */
1328 p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT);
1329 p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT);
1330 spin_unlock_bh(&mp->mib_counters_lock);
1333 static void mib_counters_timer_wrapper(struct timer_list *t)
1335 struct mv643xx_eth_private *mp = from_timer(mp, t, mib_counters_timer);
1336 mib_counters_update(mp);
1337 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1341 /* interrupt coalescing *****************************************************/
1343 * Hardware coalescing parameters are set in units of 64 t_clk
1346 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1348 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1350 * In the ->set*() methods, we round the computed register value
1351 * to the nearest integer.
1353 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1355 u32 val = rdlp(mp, SDMA_CONFIG);
1358 if (mp->shared->extended_rx_coal_limit)
1359 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1361 temp = (val & 0x003fff00) >> 8;
1364 temp += mp->t_clk / 2;
1365 do_div(temp, mp->t_clk);
1367 return (unsigned int)temp;
1370 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1375 temp = (u64)usec * mp->t_clk;
1377 do_div(temp, 64000000);
1379 val = rdlp(mp, SDMA_CONFIG);
1380 if (mp->shared->extended_rx_coal_limit) {
1384 val |= (temp & 0x8000) << 10;
1385 val |= (temp & 0x7fff) << 7;
1390 val |= (temp & 0x3fff) << 8;
1392 wrlp(mp, SDMA_CONFIG, val);
1395 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1399 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1401 temp += mp->t_clk / 2;
1402 do_div(temp, mp->t_clk);
1404 return (unsigned int)temp;
1407 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1411 temp = (u64)usec * mp->t_clk;
1413 do_div(temp, 64000000);
1418 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1422 /* ethtool ******************************************************************/
1423 struct mv643xx_eth_stats {
1424 char stat_string[ETH_GSTRING_LEN];
1431 { #m, sizeof_field(struct net_device_stats, m), \
1432 offsetof(struct net_device, stats.m), -1 }
1434 #define MIBSTAT(m) \
1435 { #m, sizeof_field(struct mib_counters, m), \
1436 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1438 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1447 MIBSTAT(good_octets_received),
1448 MIBSTAT(bad_octets_received),
1449 MIBSTAT(internal_mac_transmit_err),
1450 MIBSTAT(good_frames_received),
1451 MIBSTAT(bad_frames_received),
1452 MIBSTAT(broadcast_frames_received),
1453 MIBSTAT(multicast_frames_received),
1454 MIBSTAT(frames_64_octets),
1455 MIBSTAT(frames_65_to_127_octets),
1456 MIBSTAT(frames_128_to_255_octets),
1457 MIBSTAT(frames_256_to_511_octets),
1458 MIBSTAT(frames_512_to_1023_octets),
1459 MIBSTAT(frames_1024_to_max_octets),
1460 MIBSTAT(good_octets_sent),
1461 MIBSTAT(good_frames_sent),
1462 MIBSTAT(excessive_collision),
1463 MIBSTAT(multicast_frames_sent),
1464 MIBSTAT(broadcast_frames_sent),
1465 MIBSTAT(unrec_mac_control_received),
1467 MIBSTAT(good_fc_received),
1468 MIBSTAT(bad_fc_received),
1469 MIBSTAT(undersize_received),
1470 MIBSTAT(fragments_received),
1471 MIBSTAT(oversize_received),
1472 MIBSTAT(jabber_received),
1473 MIBSTAT(mac_receive_error),
1474 MIBSTAT(bad_crc_event),
1476 MIBSTAT(late_collision),
1477 MIBSTAT(rx_discard),
1478 MIBSTAT(rx_overrun),
1482 mv643xx_eth_get_link_ksettings_phy(struct mv643xx_eth_private *mp,
1483 struct ethtool_link_ksettings *cmd)
1485 struct net_device *dev = mp->dev;
1487 phy_ethtool_ksettings_get(dev->phydev, cmd);
1490 * The MAC does not support 1000baseT_Half.
1492 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
1493 cmd->link_modes.supported);
1494 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
1495 cmd->link_modes.advertising);
1501 mv643xx_eth_get_link_ksettings_phyless(struct mv643xx_eth_private *mp,
1502 struct ethtool_link_ksettings *cmd)
1505 u32 supported, advertising;
1507 port_status = rdlp(mp, PORT_STATUS);
1509 supported = SUPPORTED_MII;
1510 advertising = ADVERTISED_MII;
1511 switch (port_status & PORT_SPEED_MASK) {
1513 cmd->base.speed = SPEED_10;
1515 case PORT_SPEED_100:
1516 cmd->base.speed = SPEED_100;
1518 case PORT_SPEED_1000:
1519 cmd->base.speed = SPEED_1000;
1522 cmd->base.speed = -1;
1525 cmd->base.duplex = (port_status & FULL_DUPLEX) ?
1526 DUPLEX_FULL : DUPLEX_HALF;
1527 cmd->base.port = PORT_MII;
1528 cmd->base.phy_address = 0;
1529 cmd->base.autoneg = AUTONEG_DISABLE;
1531 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1533 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1540 mv643xx_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1545 phy_ethtool_get_wol(dev->phydev, wol);
1549 mv643xx_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1556 err = phy_ethtool_set_wol(dev->phydev, wol);
1557 /* Given that mv643xx_eth works without the marvell-specific PHY driver,
1558 * this debugging hint is useful to have.
1560 if (err == -EOPNOTSUPP)
1561 netdev_info(dev, "The PHY does not support set_wol, was CONFIG_MARVELL_PHY enabled?\n");
1566 mv643xx_eth_get_link_ksettings(struct net_device *dev,
1567 struct ethtool_link_ksettings *cmd)
1569 struct mv643xx_eth_private *mp = netdev_priv(dev);
1572 return mv643xx_eth_get_link_ksettings_phy(mp, cmd);
1574 return mv643xx_eth_get_link_ksettings_phyless(mp, cmd);
1578 mv643xx_eth_set_link_ksettings(struct net_device *dev,
1579 const struct ethtool_link_ksettings *cmd)
1581 struct ethtool_link_ksettings c = *cmd;
1589 * The MAC does not support 1000baseT_Half.
1591 ethtool_convert_link_mode_to_legacy_u32(&advertising,
1592 c.link_modes.advertising);
1593 advertising &= ~ADVERTISED_1000baseT_Half;
1594 ethtool_convert_legacy_u32_to_link_mode(c.link_modes.advertising,
1597 ret = phy_ethtool_ksettings_set(dev->phydev, &c);
1599 mv643xx_eth_adjust_link(dev);
1603 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1604 struct ethtool_drvinfo *drvinfo)
1606 strlcpy(drvinfo->driver, mv643xx_eth_driver_name,
1607 sizeof(drvinfo->driver));
1608 strlcpy(drvinfo->version, mv643xx_eth_driver_version,
1609 sizeof(drvinfo->version));
1610 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1611 strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info));
1614 static int mv643xx_eth_get_coalesce(struct net_device *dev,
1615 struct ethtool_coalesce *ec,
1616 struct kernel_ethtool_coalesce *kernel_coal,
1617 struct netlink_ext_ack *extack)
1619 struct mv643xx_eth_private *mp = netdev_priv(dev);
1621 ec->rx_coalesce_usecs = get_rx_coal(mp);
1622 ec->tx_coalesce_usecs = get_tx_coal(mp);
1627 static int mv643xx_eth_set_coalesce(struct net_device *dev,
1628 struct ethtool_coalesce *ec,
1629 struct kernel_ethtool_coalesce *kernel_coal,
1630 struct netlink_ext_ack *extack)
1632 struct mv643xx_eth_private *mp = netdev_priv(dev);
1634 set_rx_coal(mp, ec->rx_coalesce_usecs);
1635 set_tx_coal(mp, ec->tx_coalesce_usecs);
1641 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er,
1642 struct kernel_ethtool_ringparam *kernel_er,
1643 struct netlink_ext_ack *extack)
1645 struct mv643xx_eth_private *mp = netdev_priv(dev);
1647 er->rx_max_pending = 4096;
1648 er->tx_max_pending = 4096;
1650 er->rx_pending = mp->rx_ring_size;
1651 er->tx_pending = mp->tx_ring_size;
1655 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er,
1656 struct kernel_ethtool_ringparam *kernel_er,
1657 struct netlink_ext_ack *extack)
1659 struct mv643xx_eth_private *mp = netdev_priv(dev);
1661 if (er->rx_mini_pending || er->rx_jumbo_pending)
1664 mp->rx_ring_size = min(er->rx_pending, 4096U);
1665 mp->tx_ring_size = clamp_t(unsigned int, er->tx_pending,
1666 MV643XX_MAX_SKB_DESCS * 2, 4096);
1667 if (mp->tx_ring_size != er->tx_pending)
1668 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
1669 mp->tx_ring_size, er->tx_pending);
1671 if (netif_running(dev)) {
1672 mv643xx_eth_stop(dev);
1673 if (mv643xx_eth_open(dev)) {
1675 "fatal error on re-opening device after ring param change\n");
1685 mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features)
1687 struct mv643xx_eth_private *mp = netdev_priv(dev);
1688 bool rx_csum = features & NETIF_F_RXCSUM;
1690 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1695 static void mv643xx_eth_get_strings(struct net_device *dev,
1696 uint32_t stringset, uint8_t *data)
1700 if (stringset == ETH_SS_STATS) {
1701 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1702 memcpy(data + i * ETH_GSTRING_LEN,
1703 mv643xx_eth_stats[i].stat_string,
1709 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1710 struct ethtool_stats *stats,
1713 struct mv643xx_eth_private *mp = netdev_priv(dev);
1716 mv643xx_eth_get_stats(dev);
1717 mib_counters_update(mp);
1719 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1720 const struct mv643xx_eth_stats *stat;
1723 stat = mv643xx_eth_stats + i;
1725 if (stat->netdev_off >= 0)
1726 p = ((void *)mp->dev) + stat->netdev_off;
1728 p = ((void *)mp) + stat->mp_off;
1730 data[i] = (stat->sizeof_stat == 8) ?
1731 *(uint64_t *)p : *(uint32_t *)p;
1735 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1737 if (sset == ETH_SS_STATS)
1738 return ARRAY_SIZE(mv643xx_eth_stats);
1743 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1744 .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
1745 .get_drvinfo = mv643xx_eth_get_drvinfo,
1746 .nway_reset = phy_ethtool_nway_reset,
1747 .get_link = ethtool_op_get_link,
1748 .get_coalesce = mv643xx_eth_get_coalesce,
1749 .set_coalesce = mv643xx_eth_set_coalesce,
1750 .get_ringparam = mv643xx_eth_get_ringparam,
1751 .set_ringparam = mv643xx_eth_set_ringparam,
1752 .get_strings = mv643xx_eth_get_strings,
1753 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1754 .get_sset_count = mv643xx_eth_get_sset_count,
1755 .get_ts_info = ethtool_op_get_ts_info,
1756 .get_wol = mv643xx_eth_get_wol,
1757 .set_wol = mv643xx_eth_set_wol,
1758 .get_link_ksettings = mv643xx_eth_get_link_ksettings,
1759 .set_link_ksettings = mv643xx_eth_set_link_ksettings,
1763 /* address handling *********************************************************/
1764 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1766 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1767 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1769 addr[0] = (mac_h >> 24) & 0xff;
1770 addr[1] = (mac_h >> 16) & 0xff;
1771 addr[2] = (mac_h >> 8) & 0xff;
1772 addr[3] = mac_h & 0xff;
1773 addr[4] = (mac_l >> 8) & 0xff;
1774 addr[5] = mac_l & 0xff;
1777 static void uc_addr_set(struct mv643xx_eth_private *mp, const u8 *addr)
1779 wrlp(mp, MAC_ADDR_HIGH,
1780 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1781 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
1784 static u32 uc_addr_filter_mask(struct net_device *dev)
1786 struct netdev_hw_addr *ha;
1789 if (dev->flags & IFF_PROMISC)
1792 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1793 netdev_for_each_uc_addr(ha, dev) {
1794 if (memcmp(dev->dev_addr, ha->addr, 5))
1796 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
1799 nibbles |= 1 << (ha->addr[5] & 0x0f);
1805 static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1807 struct mv643xx_eth_private *mp = netdev_priv(dev);
1812 uc_addr_set(mp, dev->dev_addr);
1814 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1816 nibbles = uc_addr_filter_mask(dev);
1818 port_config |= UNICAST_PROMISCUOUS_MODE;
1822 for (i = 0; i < 16; i += 4) {
1823 int off = UNICAST_TABLE(mp->port_num) + i;
1840 wrlp(mp, PORT_CONFIG, port_config);
1843 static int addr_crc(unsigned char *addr)
1848 for (i = 0; i < 6; i++) {
1851 crc = (crc ^ addr[i]) << 8;
1852 for (j = 7; j >= 0; j--) {
1853 if (crc & (0x100 << j))
1861 static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1863 struct mv643xx_eth_private *mp = netdev_priv(dev);
1866 struct netdev_hw_addr *ha;
1869 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI))
1872 /* Allocate both mc_spec and mc_other tables */
1873 mc_spec = kcalloc(128, sizeof(u32), GFP_ATOMIC);
1876 mc_other = &mc_spec[64];
1878 netdev_for_each_mc_addr(ha, dev) {
1883 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1888 entry = addr_crc(a);
1891 table[entry >> 2] |= 1 << (8 * (entry & 3));
1894 for (i = 0; i < 64; i++) {
1895 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1897 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1905 for (i = 0; i < 64; i++) {
1906 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1908 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1913 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1915 mv643xx_eth_program_unicast_filter(dev);
1916 mv643xx_eth_program_multicast_filter(dev);
1919 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1921 struct sockaddr *sa = addr;
1923 if (!is_valid_ether_addr(sa->sa_data))
1924 return -EADDRNOTAVAIL;
1926 eth_hw_addr_set(dev, sa->sa_data);
1928 netif_addr_lock_bh(dev);
1929 mv643xx_eth_program_unicast_filter(dev);
1930 netif_addr_unlock_bh(dev);
1936 /* rx/tx queue initialisation ***********************************************/
1937 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1939 struct rx_queue *rxq = mp->rxq + index;
1940 struct rx_desc *rx_desc;
1946 rxq->rx_ring_size = mp->rx_ring_size;
1948 rxq->rx_desc_count = 0;
1949 rxq->rx_curr_desc = 0;
1950 rxq->rx_used_desc = 0;
1952 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1954 if (index == 0 && size <= mp->rx_desc_sram_size) {
1955 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1956 mp->rx_desc_sram_size);
1957 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1959 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1960 size, &rxq->rx_desc_dma,
1964 if (rxq->rx_desc_area == NULL) {
1966 "can't allocate rx ring (%d bytes)\n", size);
1969 memset(rxq->rx_desc_area, 0, size);
1971 rxq->rx_desc_area_size = size;
1972 rxq->rx_skb = kcalloc(rxq->rx_ring_size, sizeof(*rxq->rx_skb),
1974 if (rxq->rx_skb == NULL)
1977 rx_desc = rxq->rx_desc_area;
1978 for (i = 0; i < rxq->rx_ring_size; i++) {
1982 if (nexti == rxq->rx_ring_size)
1985 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1986 nexti * sizeof(struct rx_desc);
1993 if (index == 0 && size <= mp->rx_desc_sram_size)
1994 iounmap(rxq->rx_desc_area);
1996 dma_free_coherent(mp->dev->dev.parent, size,
2004 static void rxq_deinit(struct rx_queue *rxq)
2006 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
2011 for (i = 0; i < rxq->rx_ring_size; i++) {
2012 if (rxq->rx_skb[i]) {
2013 dev_consume_skb_any(rxq->rx_skb[i]);
2014 rxq->rx_desc_count--;
2018 if (rxq->rx_desc_count) {
2019 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n",
2020 rxq->rx_desc_count);
2023 if (rxq->index == 0 &&
2024 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
2025 iounmap(rxq->rx_desc_area);
2027 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
2028 rxq->rx_desc_area, rxq->rx_desc_dma);
2033 static int txq_init(struct mv643xx_eth_private *mp, int index)
2035 struct tx_queue *txq = mp->txq + index;
2036 struct tx_desc *tx_desc;
2043 txq->tx_ring_size = mp->tx_ring_size;
2045 /* A queue must always have room for at least one skb.
2046 * Therefore, stop the queue when the free entries reaches
2047 * the maximum number of descriptors per skb.
2049 txq->tx_stop_threshold = txq->tx_ring_size - MV643XX_MAX_SKB_DESCS;
2050 txq->tx_wake_threshold = txq->tx_stop_threshold / 2;
2052 txq->tx_desc_count = 0;
2053 txq->tx_curr_desc = 0;
2054 txq->tx_used_desc = 0;
2056 size = txq->tx_ring_size * sizeof(struct tx_desc);
2058 if (index == 0 && size <= mp->tx_desc_sram_size) {
2059 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
2060 mp->tx_desc_sram_size);
2061 txq->tx_desc_dma = mp->tx_desc_sram_addr;
2063 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
2064 size, &txq->tx_desc_dma,
2068 if (txq->tx_desc_area == NULL) {
2070 "can't allocate tx ring (%d bytes)\n", size);
2073 memset(txq->tx_desc_area, 0, size);
2075 txq->tx_desc_area_size = size;
2077 tx_desc = txq->tx_desc_area;
2078 for (i = 0; i < txq->tx_ring_size; i++) {
2079 struct tx_desc *txd = tx_desc + i;
2083 if (nexti == txq->tx_ring_size)
2087 txd->next_desc_ptr = txq->tx_desc_dma +
2088 nexti * sizeof(struct tx_desc);
2091 txq->tx_desc_mapping = kcalloc(txq->tx_ring_size, sizeof(char),
2093 if (!txq->tx_desc_mapping) {
2095 goto err_free_desc_area;
2098 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
2099 txq->tso_hdrs = dma_alloc_coherent(mp->dev->dev.parent,
2100 txq->tx_ring_size * TSO_HEADER_SIZE,
2101 &txq->tso_hdrs_dma, GFP_KERNEL);
2102 if (txq->tso_hdrs == NULL) {
2104 goto err_free_desc_mapping;
2106 skb_queue_head_init(&txq->tx_skb);
2110 err_free_desc_mapping:
2111 kfree(txq->tx_desc_mapping);
2113 if (index == 0 && size <= mp->tx_desc_sram_size)
2114 iounmap(txq->tx_desc_area);
2116 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2117 txq->tx_desc_area, txq->tx_desc_dma);
2121 static void txq_deinit(struct tx_queue *txq)
2123 struct mv643xx_eth_private *mp = txq_to_mp(txq);
2126 txq_reclaim(txq, txq->tx_ring_size, 1);
2128 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
2130 if (txq->index == 0 &&
2131 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
2132 iounmap(txq->tx_desc_area);
2134 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2135 txq->tx_desc_area, txq->tx_desc_dma);
2136 kfree(txq->tx_desc_mapping);
2139 dma_free_coherent(mp->dev->dev.parent,
2140 txq->tx_ring_size * TSO_HEADER_SIZE,
2141 txq->tso_hdrs, txq->tso_hdrs_dma);
2145 /* netdev ops and related ***************************************************/
2146 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
2151 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
2156 if (int_cause & INT_EXT) {
2157 int_cause &= ~INT_EXT;
2158 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
2162 wrlp(mp, INT_CAUSE, ~int_cause);
2163 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
2164 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
2165 mp->work_rx |= (int_cause & INT_RX) >> 2;
2168 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2169 if (int_cause_ext) {
2170 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
2171 if (int_cause_ext & INT_EXT_LINK_PHY)
2173 mp->work_tx |= int_cause_ext & INT_EXT_TX;
2179 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2181 struct net_device *dev = (struct net_device *)dev_id;
2182 struct mv643xx_eth_private *mp = netdev_priv(dev);
2184 if (unlikely(!mv643xx_eth_collect_events(mp)))
2187 wrlp(mp, INT_MASK, 0);
2188 napi_schedule(&mp->napi);
2193 static void handle_link_event(struct mv643xx_eth_private *mp)
2195 struct net_device *dev = mp->dev;
2201 port_status = rdlp(mp, PORT_STATUS);
2202 if (!(port_status & LINK_UP)) {
2203 if (netif_carrier_ok(dev)) {
2206 netdev_info(dev, "link down\n");
2208 netif_carrier_off(dev);
2210 for (i = 0; i < mp->txq_count; i++) {
2211 struct tx_queue *txq = mp->txq + i;
2213 txq_reclaim(txq, txq->tx_ring_size, 1);
2214 txq_reset_hw_ptr(txq);
2220 switch (port_status & PORT_SPEED_MASK) {
2224 case PORT_SPEED_100:
2227 case PORT_SPEED_1000:
2234 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2235 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2237 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
2238 speed, duplex ? "full" : "half", fc ? "en" : "dis");
2240 if (!netif_carrier_ok(dev))
2241 netif_carrier_on(dev);
2244 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
2246 struct mv643xx_eth_private *mp;
2249 mp = container_of(napi, struct mv643xx_eth_private, napi);
2251 if (unlikely(mp->oom)) {
2253 del_timer(&mp->rx_oom);
2257 while (work_done < budget) {
2262 if (mp->work_link) {
2264 handle_link_event(mp);
2269 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2270 if (likely(!mp->oom))
2271 queue_mask |= mp->work_rx_refill;
2274 if (mv643xx_eth_collect_events(mp))
2279 queue = fls(queue_mask) - 1;
2280 queue_mask = 1 << queue;
2282 work_tbd = budget - work_done;
2286 if (mp->work_tx_end & queue_mask) {
2287 txq_kick(mp->txq + queue);
2288 } else if (mp->work_tx & queue_mask) {
2289 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2290 txq_maybe_wake(mp->txq + queue);
2291 } else if (mp->work_rx & queue_mask) {
2292 work_done += rxq_process(mp->rxq + queue, work_tbd);
2293 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
2294 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2300 if (work_done < budget) {
2302 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2303 napi_complete_done(napi, work_done);
2304 wrlp(mp, INT_MASK, mp->int_mask);
2310 static inline void oom_timer_wrapper(struct timer_list *t)
2312 struct mv643xx_eth_private *mp = from_timer(mp, t, rx_oom);
2314 napi_schedule(&mp->napi);
2317 static void port_start(struct mv643xx_eth_private *mp)
2319 struct net_device *dev = mp->dev;
2324 * Perform PHY reset, if there is a PHY.
2327 struct ethtool_link_ksettings cmd;
2329 mv643xx_eth_get_link_ksettings(dev, &cmd);
2330 phy_init_hw(dev->phydev);
2331 mv643xx_eth_set_link_ksettings(
2332 dev, (const struct ethtool_link_ksettings *)&cmd);
2333 phy_start(dev->phydev);
2337 * Configure basic link parameters.
2339 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2341 pscr |= SERIAL_PORT_ENABLE;
2342 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2344 pscr |= DO_NOT_FORCE_LINK_FAIL;
2346 pscr |= FORCE_LINK_PASS;
2347 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2350 * Configure TX path and queues.
2352 tx_set_rate(mp, 1000000000, 16777216);
2353 for (i = 0; i < mp->txq_count; i++) {
2354 struct tx_queue *txq = mp->txq + i;
2356 txq_reset_hw_ptr(txq);
2357 txq_set_rate(txq, 1000000000, 16777216);
2358 txq_set_fixed_prio_mode(txq);
2362 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2363 * frames to RX queue #0, and include the pseudo-header when
2364 * calculating receive checksums.
2366 mv643xx_eth_set_features(mp->dev, mp->dev->features);
2369 * Treat BPDUs as normal multicasts, and disable partition mode.
2371 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2374 * Add configured unicast addresses to address filter table.
2376 mv643xx_eth_program_unicast_filter(mp->dev);
2379 * Enable the receive queues.
2381 for (i = 0; i < mp->rxq_count; i++) {
2382 struct rx_queue *rxq = mp->rxq + i;
2385 addr = (u32)rxq->rx_desc_dma;
2386 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2387 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2393 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2398 * Reserve 2+14 bytes for an ethernet header (the hardware
2399 * automatically prepends 2 bytes of dummy data to each
2400 * received packet), 16 bytes for up to four VLAN tags, and
2401 * 4 bytes for the trailing FCS -- 36 bytes total.
2403 skb_size = mp->dev->mtu + 36;
2406 * Make sure that the skb size is a multiple of 8 bytes, as
2407 * the lower three bits of the receive descriptor's buffer
2408 * size field are ignored by the hardware.
2410 mp->skb_size = (skb_size + 7) & ~7;
2413 * If NET_SKB_PAD is smaller than a cache line,
2414 * netdev_alloc_skb() will cause skb->data to be misaligned
2415 * to a cache line boundary. If this is the case, include
2416 * some extra space to allow re-aligning the data area.
2418 mp->skb_size += SKB_DMA_REALIGN;
2421 static int mv643xx_eth_open(struct net_device *dev)
2423 struct mv643xx_eth_private *mp = netdev_priv(dev);
2427 wrlp(mp, INT_CAUSE, 0);
2428 wrlp(mp, INT_CAUSE_EXT, 0);
2429 rdlp(mp, INT_CAUSE_EXT);
2431 err = request_irq(dev->irq, mv643xx_eth_irq,
2432 IRQF_SHARED, dev->name, dev);
2434 netdev_err(dev, "can't assign irq\n");
2438 mv643xx_eth_recalc_skb_size(mp);
2440 napi_enable(&mp->napi);
2442 mp->int_mask = INT_EXT;
2444 for (i = 0; i < mp->rxq_count; i++) {
2445 err = rxq_init(mp, i);
2448 rxq_deinit(mp->rxq + i);
2452 rxq_refill(mp->rxq + i, INT_MAX);
2453 mp->int_mask |= INT_RX_0 << i;
2457 mp->rx_oom.expires = jiffies + (HZ / 10);
2458 add_timer(&mp->rx_oom);
2461 for (i = 0; i < mp->txq_count; i++) {
2462 err = txq_init(mp, i);
2465 txq_deinit(mp->txq + i);
2468 mp->int_mask |= INT_TX_END_0 << i;
2471 add_timer(&mp->mib_counters_timer);
2474 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2475 wrlp(mp, INT_MASK, mp->int_mask);
2481 for (i = 0; i < mp->rxq_count; i++)
2482 rxq_deinit(mp->rxq + i);
2484 free_irq(dev->irq, dev);
2489 static void port_reset(struct mv643xx_eth_private *mp)
2494 for (i = 0; i < mp->rxq_count; i++)
2495 rxq_disable(mp->rxq + i);
2496 for (i = 0; i < mp->txq_count; i++)
2497 txq_disable(mp->txq + i);
2500 u32 ps = rdlp(mp, PORT_STATUS);
2502 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2507 /* Reset the Enable bit in the Configuration Register */
2508 data = rdlp(mp, PORT_SERIAL_CONTROL);
2509 data &= ~(SERIAL_PORT_ENABLE |
2510 DO_NOT_FORCE_LINK_FAIL |
2512 wrlp(mp, PORT_SERIAL_CONTROL, data);
2515 static int mv643xx_eth_stop(struct net_device *dev)
2517 struct mv643xx_eth_private *mp = netdev_priv(dev);
2520 wrlp(mp, INT_MASK_EXT, 0x00000000);
2521 wrlp(mp, INT_MASK, 0x00000000);
2524 napi_disable(&mp->napi);
2526 del_timer_sync(&mp->rx_oom);
2528 netif_carrier_off(dev);
2530 phy_stop(dev->phydev);
2531 free_irq(dev->irq, dev);
2534 mv643xx_eth_get_stats(dev);
2535 mib_counters_update(mp);
2536 del_timer_sync(&mp->mib_counters_timer);
2538 for (i = 0; i < mp->rxq_count; i++)
2539 rxq_deinit(mp->rxq + i);
2540 for (i = 0; i < mp->txq_count; i++)
2541 txq_deinit(mp->txq + i);
2546 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2553 ret = phy_mii_ioctl(dev->phydev, ifr, cmd);
2555 mv643xx_eth_adjust_link(dev);
2559 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2561 struct mv643xx_eth_private *mp = netdev_priv(dev);
2564 mv643xx_eth_recalc_skb_size(mp);
2565 tx_set_rate(mp, 1000000000, 16777216);
2567 if (!netif_running(dev))
2571 * Stop and then re-open the interface. This will allocate RX
2572 * skbs of the new MTU.
2573 * There is a possible danger that the open will not succeed,
2574 * due to memory being full.
2576 mv643xx_eth_stop(dev);
2577 if (mv643xx_eth_open(dev)) {
2579 "fatal error on re-opening device after MTU change\n");
2585 static void tx_timeout_task(struct work_struct *ugly)
2587 struct mv643xx_eth_private *mp;
2589 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2590 if (netif_running(mp->dev)) {
2591 netif_tx_stop_all_queues(mp->dev);
2594 netif_tx_wake_all_queues(mp->dev);
2598 static void mv643xx_eth_tx_timeout(struct net_device *dev, unsigned int txqueue)
2600 struct mv643xx_eth_private *mp = netdev_priv(dev);
2602 netdev_info(dev, "tx timeout\n");
2604 schedule_work(&mp->tx_timeout_task);
2607 #ifdef CONFIG_NET_POLL_CONTROLLER
2608 static void mv643xx_eth_netpoll(struct net_device *dev)
2610 struct mv643xx_eth_private *mp = netdev_priv(dev);
2612 wrlp(mp, INT_MASK, 0x00000000);
2615 mv643xx_eth_irq(dev->irq, dev);
2617 wrlp(mp, INT_MASK, mp->int_mask);
2622 /* platform glue ************************************************************/
2624 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2625 const struct mbus_dram_target_info *dram)
2627 void __iomem *base = msp->base;
2632 for (i = 0; i < 6; i++) {
2633 writel(0, base + WINDOW_BASE(i));
2634 writel(0, base + WINDOW_SIZE(i));
2636 writel(0, base + WINDOW_REMAP_HIGH(i));
2642 for (i = 0; i < dram->num_cs; i++) {
2643 const struct mbus_dram_window *cs = dram->cs + i;
2645 writel((cs->base & 0xffff0000) |
2646 (cs->mbus_attr << 8) |
2647 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2648 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2650 win_enable &= ~(1 << i);
2651 win_protect |= 3 << (2 * i);
2654 writel(win_enable, base + WINDOW_BAR_ENABLE);
2655 msp->win_protect = win_protect;
2658 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2661 * Check whether we have a 14-bit coal limit field in bits
2662 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2663 * SDMA config register.
2665 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2666 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2667 msp->extended_rx_coal_limit = 1;
2669 msp->extended_rx_coal_limit = 0;
2672 * Check whether the MAC supports TX rate control, and if
2673 * yes, whether its associated registers are in the old or
2676 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2677 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2678 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2680 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2681 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2682 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2684 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2688 #if defined(CONFIG_OF)
2689 static const struct of_device_id mv643xx_eth_shared_ids[] = {
2690 { .compatible = "marvell,orion-eth", },
2691 { .compatible = "marvell,kirkwood-eth", },
2694 MODULE_DEVICE_TABLE(of, mv643xx_eth_shared_ids);
2697 #ifdef CONFIG_OF_IRQ
2698 #define mv643xx_eth_property(_np, _name, _v) \
2701 if (!of_property_read_u32(_np, "marvell," _name, &tmp)) \
2705 static struct platform_device *port_platdev[3];
2707 static void mv643xx_eth_shared_of_remove(void)
2711 for (n = 0; n < 3; n++) {
2712 platform_device_del(port_platdev[n]);
2713 port_platdev[n] = NULL;
2717 static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev,
2718 struct device_node *pnp)
2720 struct platform_device *ppdev;
2721 struct mv643xx_eth_platform_data ppd;
2722 struct resource res;
2726 memset(&ppd, 0, sizeof(ppd));
2729 memset(&res, 0, sizeof(res));
2730 if (of_irq_to_resource(pnp, 0, &res) <= 0) {
2731 dev_err(&pdev->dev, "missing interrupt on %pOFn\n", pnp);
2735 if (of_property_read_u32(pnp, "reg", &ppd.port_number)) {
2736 dev_err(&pdev->dev, "missing reg property on %pOFn\n", pnp);
2740 if (ppd.port_number >= 3) {
2741 dev_err(&pdev->dev, "invalid reg property on %pOFn\n", pnp);
2745 while (dev_num < 3 && port_platdev[dev_num])
2749 dev_err(&pdev->dev, "too many ports registered\n");
2753 ret = of_get_mac_address(pnp, ppd.mac_addr);
2754 if (ret == -EPROBE_DEFER)
2757 mv643xx_eth_property(pnp, "tx-queue-size", ppd.tx_queue_size);
2758 mv643xx_eth_property(pnp, "tx-sram-addr", ppd.tx_sram_addr);
2759 mv643xx_eth_property(pnp, "tx-sram-size", ppd.tx_sram_size);
2760 mv643xx_eth_property(pnp, "rx-queue-size", ppd.rx_queue_size);
2761 mv643xx_eth_property(pnp, "rx-sram-addr", ppd.rx_sram_addr);
2762 mv643xx_eth_property(pnp, "rx-sram-size", ppd.rx_sram_size);
2764 ppd.phy_node = of_parse_phandle(pnp, "phy-handle", 0);
2765 if (!ppd.phy_node) {
2766 ppd.phy_addr = MV643XX_ETH_PHY_NONE;
2767 of_property_read_u32(pnp, "speed", &ppd.speed);
2768 of_property_read_u32(pnp, "duplex", &ppd.duplex);
2771 ppdev = platform_device_alloc(MV643XX_ETH_NAME, dev_num);
2774 ppdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
2775 ppdev->dev.of_node = pnp;
2777 ret = platform_device_add_resources(ppdev, &res, 1);
2781 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
2785 ret = platform_device_add(ppdev);
2789 port_platdev[dev_num] = ppdev;
2794 platform_device_put(ppdev);
2798 static int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2800 struct mv643xx_eth_shared_platform_data *pd;
2801 struct device_node *pnp, *np = pdev->dev.of_node;
2804 /* bail out if not registered from DT */
2808 pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
2811 pdev->dev.platform_data = pd;
2813 mv643xx_eth_property(np, "tx-checksum-limit", pd->tx_csum_limit);
2815 for_each_available_child_of_node(np, pnp) {
2816 ret = mv643xx_eth_shared_of_add_port(pdev, pnp);
2819 mv643xx_eth_shared_of_remove();
2827 static inline int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2832 static inline void mv643xx_eth_shared_of_remove(void)
2837 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2839 static int mv643xx_eth_version_printed;
2840 struct mv643xx_eth_shared_platform_data *pd;
2841 struct mv643xx_eth_shared_private *msp;
2842 const struct mbus_dram_target_info *dram;
2843 struct resource *res;
2846 if (!mv643xx_eth_version_printed++)
2847 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
2848 mv643xx_eth_driver_version);
2850 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2854 msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL);
2857 platform_set_drvdata(pdev, msp);
2859 msp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
2860 if (msp->base == NULL)
2863 msp->clk = devm_clk_get(&pdev->dev, NULL);
2864 if (!IS_ERR(msp->clk))
2865 clk_prepare_enable(msp->clk);
2868 * (Re-)program MBUS remapping windows if we are asked to.
2870 dram = mv_mbus_dram_info();
2872 mv643xx_eth_conf_mbus_windows(msp, dram);
2874 ret = mv643xx_eth_shared_of_probe(pdev);
2877 pd = dev_get_platdata(&pdev->dev);
2879 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
2880 pd->tx_csum_limit : 9 * 1024;
2881 infer_hw_params(msp);
2886 if (!IS_ERR(msp->clk))
2887 clk_disable_unprepare(msp->clk);
2891 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2893 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2895 mv643xx_eth_shared_of_remove();
2896 if (!IS_ERR(msp->clk))
2897 clk_disable_unprepare(msp->clk);
2901 static struct platform_driver mv643xx_eth_shared_driver = {
2902 .probe = mv643xx_eth_shared_probe,
2903 .remove = mv643xx_eth_shared_remove,
2905 .name = MV643XX_ETH_SHARED_NAME,
2906 .of_match_table = of_match_ptr(mv643xx_eth_shared_ids),
2910 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2912 int addr_shift = 5 * mp->port_num;
2915 data = rdl(mp, PHY_ADDR);
2916 data &= ~(0x1f << addr_shift);
2917 data |= (phy_addr & 0x1f) << addr_shift;
2918 wrl(mp, PHY_ADDR, data);
2921 static int phy_addr_get(struct mv643xx_eth_private *mp)
2925 data = rdl(mp, PHY_ADDR);
2927 return (data >> (5 * mp->port_num)) & 0x1f;
2930 static void set_params(struct mv643xx_eth_private *mp,
2931 struct mv643xx_eth_platform_data *pd)
2933 struct net_device *dev = mp->dev;
2934 unsigned int tx_ring_size;
2936 if (is_valid_ether_addr(pd->mac_addr)) {
2937 eth_hw_addr_set(dev, pd->mac_addr);
2941 uc_addr_get(mp, addr);
2942 eth_hw_addr_set(dev, addr);
2945 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2946 if (pd->rx_queue_size)
2947 mp->rx_ring_size = pd->rx_queue_size;
2948 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2949 mp->rx_desc_sram_size = pd->rx_sram_size;
2951 mp->rxq_count = pd->rx_queue_count ? : 1;
2953 tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2954 if (pd->tx_queue_size)
2955 tx_ring_size = pd->tx_queue_size;
2957 mp->tx_ring_size = clamp_t(unsigned int, tx_ring_size,
2958 MV643XX_MAX_SKB_DESCS * 2, 4096);
2959 if (mp->tx_ring_size != tx_ring_size)
2960 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
2961 mp->tx_ring_size, tx_ring_size);
2963 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2964 mp->tx_desc_sram_size = pd->tx_sram_size;
2966 mp->txq_count = pd->tx_queue_count ? : 1;
2969 static int get_phy_mode(struct mv643xx_eth_private *mp)
2971 struct device *dev = mp->dev->dev.parent;
2972 phy_interface_t iface;
2976 err = of_get_phy_mode(dev->of_node, &iface);
2978 /* Historical default if unspecified. We could also read/write
2979 * the interface state in the PSC1
2981 if (!dev->of_node || err)
2982 iface = PHY_INTERFACE_MODE_GMII;
2986 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2989 struct phy_device *phydev;
2993 char phy_id[MII_BUS_ID_SIZE + 3];
2995 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2996 start = phy_addr_get(mp) & 0x1f;
2999 start = phy_addr & 0x1f;
3003 /* Attempt to connect to the PHY using orion-mdio */
3004 phydev = ERR_PTR(-ENODEV);
3005 for (i = 0; i < num; i++) {
3006 int addr = (start + i) & 0x1f;
3008 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
3009 "orion-mdio-mii", addr);
3011 phydev = phy_connect(mp->dev, phy_id, mv643xx_eth_adjust_link,
3013 if (!IS_ERR(phydev)) {
3014 phy_addr_set(mp, addr);
3022 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
3024 struct net_device *dev = mp->dev;
3025 struct phy_device *phy = dev->phydev;
3028 phy->autoneg = AUTONEG_ENABLE;
3031 linkmode_copy(phy->advertising, phy->supported);
3032 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
3035 phy->autoneg = AUTONEG_DISABLE;
3036 linkmode_zero(phy->advertising);
3038 phy->duplex = duplex;
3040 phy_start_aneg(phy);
3043 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
3045 struct net_device *dev = mp->dev;
3048 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
3049 if (pscr & SERIAL_PORT_ENABLE) {
3050 pscr &= ~SERIAL_PORT_ENABLE;
3051 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
3054 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
3056 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
3057 if (speed == SPEED_1000)
3058 pscr |= SET_GMII_SPEED_TO_1000;
3059 else if (speed == SPEED_100)
3060 pscr |= SET_MII_SPEED_TO_100;
3062 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
3064 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
3065 if (duplex == DUPLEX_FULL)
3066 pscr |= SET_FULL_DUPLEX_MODE;
3069 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
3072 static const struct net_device_ops mv643xx_eth_netdev_ops = {
3073 .ndo_open = mv643xx_eth_open,
3074 .ndo_stop = mv643xx_eth_stop,
3075 .ndo_start_xmit = mv643xx_eth_xmit,
3076 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
3077 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
3078 .ndo_validate_addr = eth_validate_addr,
3079 .ndo_eth_ioctl = mv643xx_eth_ioctl,
3080 .ndo_change_mtu = mv643xx_eth_change_mtu,
3081 .ndo_set_features = mv643xx_eth_set_features,
3082 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
3083 .ndo_get_stats = mv643xx_eth_get_stats,
3084 #ifdef CONFIG_NET_POLL_CONTROLLER
3085 .ndo_poll_controller = mv643xx_eth_netpoll,
3089 static int mv643xx_eth_probe(struct platform_device *pdev)
3091 struct mv643xx_eth_platform_data *pd;
3092 struct mv643xx_eth_private *mp;
3093 struct net_device *dev;
3094 struct phy_device *phydev = NULL;
3097 pd = dev_get_platdata(&pdev->dev);
3099 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
3103 if (pd->shared == NULL) {
3104 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n");
3108 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
3112 SET_NETDEV_DEV(dev, &pdev->dev);
3113 mp = netdev_priv(dev);
3114 platform_set_drvdata(pdev, mp);
3116 mp->shared = platform_get_drvdata(pd->shared);
3117 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
3118 mp->port_num = pd->port_number;
3122 /* Kirkwood resets some registers on gated clocks. Especially
3123 * CLK125_BYPASS_EN must be cleared but is not available on
3124 * all other SoCs/System Controllers using this driver.
3126 if (of_device_is_compatible(pdev->dev.of_node,
3127 "marvell,kirkwood-eth-port"))
3128 wrlp(mp, PORT_SERIAL_CONTROL1,
3129 rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN);
3132 * Start with a default rate, and if there is a clock, allow
3133 * it to override the default.
3135 mp->t_clk = 133000000;
3136 mp->clk = devm_clk_get(&pdev->dev, NULL);
3137 if (!IS_ERR(mp->clk)) {
3138 clk_prepare_enable(mp->clk);
3139 mp->t_clk = clk_get_rate(mp->clk);
3140 } else if (!IS_ERR(mp->shared->clk)) {
3141 mp->t_clk = clk_get_rate(mp->shared->clk);
3145 netif_set_real_num_tx_queues(dev, mp->txq_count);
3146 netif_set_real_num_rx_queues(dev, mp->rxq_count);
3150 phydev = of_phy_connect(mp->dev, pd->phy_node,
3151 mv643xx_eth_adjust_link, 0,
3156 phy_addr_set(mp, phydev->mdio.addr);
3157 } else if (pd->phy_addr != MV643XX_ETH_PHY_NONE) {
3158 phydev = phy_scan(mp, pd->phy_addr);
3161 err = PTR_ERR(phydev);
3163 phy_init(mp, pd->speed, pd->duplex);
3165 if (err == -ENODEV) {
3166 err = -EPROBE_DEFER;
3172 dev->ethtool_ops = &mv643xx_eth_ethtool_ops;
3174 init_pscr(mp, pd->speed, pd->duplex);
3177 mib_counters_clear(mp);
3179 timer_setup(&mp->mib_counters_timer, mib_counters_timer_wrapper, 0);
3180 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
3182 spin_lock_init(&mp->mib_counters_lock);
3184 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
3186 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, NAPI_POLL_WEIGHT);
3188 timer_setup(&mp->rx_oom, oom_timer_wrapper, 0);
3191 irq = platform_get_irq(pdev, 0);
3192 if (WARN_ON(irq < 0)) {
3198 dev->netdev_ops = &mv643xx_eth_netdev_ops;
3200 dev->watchdog_timeo = 2 * HZ;
3203 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
3204 dev->vlan_features = dev->features;
3206 dev->features |= NETIF_F_RXCSUM;
3207 dev->hw_features = dev->features;
3209 dev->priv_flags |= IFF_UNICAST_FLT;
3210 netif_set_tso_max_segs(dev, MV643XX_MAX_TSO_SEGS);
3212 /* MTU range: 64 - 9500 */
3214 dev->max_mtu = 9500;
3216 if (mp->shared->win_protect)
3217 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
3219 netif_carrier_off(dev);
3221 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
3223 set_rx_coal(mp, 250);
3226 err = register_netdev(dev);
3230 netdev_notice(dev, "port %d with MAC address %pM\n",
3231 mp->port_num, dev->dev_addr);
3233 if (mp->tx_desc_sram_size > 0)
3234 netdev_notice(dev, "configured with sram\n");
3239 if (!IS_ERR(mp->clk))
3240 clk_disable_unprepare(mp->clk);
3246 static int mv643xx_eth_remove(struct platform_device *pdev)
3248 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3249 struct net_device *dev = mp->dev;
3251 unregister_netdev(mp->dev);
3253 phy_disconnect(dev->phydev);
3254 cancel_work_sync(&mp->tx_timeout_task);
3256 if (!IS_ERR(mp->clk))
3257 clk_disable_unprepare(mp->clk);
3259 free_netdev(mp->dev);
3264 static void mv643xx_eth_shutdown(struct platform_device *pdev)
3266 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3268 /* Mask all interrupts on ethernet port */
3269 wrlp(mp, INT_MASK, 0);
3272 if (netif_running(mp->dev))
3276 static struct platform_driver mv643xx_eth_driver = {
3277 .probe = mv643xx_eth_probe,
3278 .remove = mv643xx_eth_remove,
3279 .shutdown = mv643xx_eth_shutdown,
3281 .name = MV643XX_ETH_NAME,
3285 static struct platform_driver * const drivers[] = {
3286 &mv643xx_eth_shared_driver,
3287 &mv643xx_eth_driver,
3290 static int __init mv643xx_eth_init_module(void)
3292 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
3294 module_init(mv643xx_eth_init_module);
3296 static void __exit mv643xx_eth_cleanup_module(void)
3298 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
3300 module_exit(mv643xx_eth_cleanup_module);
3302 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3303 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
3304 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
3305 MODULE_LICENSE("GPL");
3306 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
3307 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);