drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
   3
   4 #include "ixgbe_x540.h"
   5 #include "ixgbe_type.h"
   6 #include "ixgbe_common.h"
   7 #include "ixgbe_phy.h"
   8
   9 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *, ixgbe_link_speed);
  10 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *);
  11 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *);
  12 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *);
  13 static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *);
  14
  15 static s32 ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw)
  16 {
  17         struct ixgbe_mac_info *mac = &hw->mac;
  18         struct ixgbe_phy_info *phy = &hw->phy;
  19         struct ixgbe_link_info *link = &hw->link;
  20
  21         /* Start with X540 invariants, since so simular */
  22         ixgbe_get_invariants_X540(hw);
  23
  24         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
  25                 phy->ops.set_phy_power = NULL;
  26
  27         link->addr = IXGBE_CS4227;
  28
  29         return 0;
  30 }
  31
  32 static s32 ixgbe_get_invariants_X550_x_fw(struct ixgbe_hw *hw)
  33 {
  34         struct ixgbe_phy_info *phy = &hw->phy;
  35
  36         /* Start with X540 invariants, since so similar */
  37         ixgbe_get_invariants_X540(hw);
  38
  39         phy->ops.set_phy_power = NULL;
  40
  41         return 0;
  42 }
  43
  44 static s32 ixgbe_get_invariants_X550_a(struct ixgbe_hw *hw)
  45 {
  46         struct ixgbe_mac_info *mac = &hw->mac;
  47         struct ixgbe_phy_info *phy = &hw->phy;
  48
  49         /* Start with X540 invariants, since so simular */
  50         ixgbe_get_invariants_X540(hw);
  51
  52         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
  53                 phy->ops.set_phy_power = NULL;
  54
  55         return 0;
  56 }
  57
  58 static s32 ixgbe_get_invariants_X550_a_fw(struct ixgbe_hw *hw)
  59 {
  60         struct ixgbe_phy_info *phy = &hw->phy;
  61
  62         /* Start with X540 invariants, since so similar */
  63         ixgbe_get_invariants_X540(hw);
  64
  65         phy->ops.set_phy_power = NULL;
  66
  67         return 0;
  68 }
  69
  70 /** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
  71  *  @hw: pointer to hardware structure
  72  **/
  73 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
  74 {
  75         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
  76
  77         if (hw->bus.lan_id) {
  78                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
  79                 esdp |= IXGBE_ESDP_SDP1_DIR;
  80         }
  81         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
  82         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
  83         IXGBE_WRITE_FLUSH(hw);
  84 }
  85
  86 /**
  87  * ixgbe_read_cs4227 - Read CS4227 register
  88  * @hw: pointer to hardware structure
  89  * @reg: register number to write
  90  * @value: pointer to receive value read
  91  *
  92  * Returns status code
  93  */
  94 static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  95 {
  96         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
  97 }
  98
  99 /**
 100  * ixgbe_write_cs4227 - Write CS4227 register
 101  * @hw: pointer to hardware structure
 102  * @reg: register number to write
 103  * @value: value to write to register
 104  *
 105  * Returns status code
 106  */
 107 static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 108 {
 109         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 110 }
 111
 112 /**
 113  * ixgbe_read_pe - Read register from port expander
 114  * @hw: pointer to hardware structure
 115  * @reg: register number to read
 116  * @value: pointer to receive read value
 117  *
 118  * Returns status code
 119  */
 120 static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 121 {
 122         s32 status;
 123
 124         status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value);
 125         if (status)
 126                 hw_err(hw, "port expander access failed with %d\n", status);
 127         return status;
 128 }
 129
 130 /**
 131  * ixgbe_write_pe - Write register to port expander
 132  * @hw: pointer to hardware structure
 133  * @reg: register number to write
 134  * @value: value to write
 135  *
 136  * Returns status code
 137  */
 138 static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 139 {
 140         s32 status;
 141
 142         status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE,
 143                                                        value);
 144         if (status)
 145                 hw_err(hw, "port expander access failed with %d\n", status);
 146         return status;
 147 }
 148
 149 /**
 150  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 151  * @hw: pointer to hardware structure
 152  *
 153  * This function assumes that the caller has acquired the proper semaphore.
 154  * Returns error code
 155  */
 156 static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 157 {
 158         s32 status;
 159         u32 retry;
 160         u16 value;
 161         u8 reg;
 162
 163         /* Trigger hard reset. */
 164         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 165         if (status)
 166                 return status;
 167         reg |= IXGBE_PE_BIT1;
 168         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 169         if (status)
 170                 return status;
 171
 172         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 173         if (status)
 174                 return status;
 175         reg &= ~IXGBE_PE_BIT1;
 176         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 177         if (status)
 178                 return status;
 179
 180         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 181         if (status)
 182                 return status;
 183         reg &= ~IXGBE_PE_BIT1;
 184         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 185         if (status)
 186                 return status;
 187
 188         usleep_range(IXGBE_CS4227_RESET_HOLD, IXGBE_CS4227_RESET_HOLD + 100);
 189
 190         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 191         if (status)
 192                 return status;
 193         reg |= IXGBE_PE_BIT1;
 194         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 195         if (status)
 196                 return status;
 197
 198         /* Wait for the reset to complete. */
 199         msleep(IXGBE_CS4227_RESET_DELAY);
 200         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 201                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 202                                            &value);
 203                 if (!status && value == IXGBE_CS4227_EEPROM_LOAD_OK)
 204                         break;
 205                 msleep(IXGBE_CS4227_CHECK_DELAY);
 206         }
 207         if (retry == IXGBE_CS4227_RETRIES) {
 208                 hw_err(hw, "CS4227 reset did not complete\n");
 209                 return -EIO;
 210         }
 211
 212         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 213         if (status || !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 214                 hw_err(hw, "CS4227 EEPROM did not load successfully\n");
 215                 return -EIO;
 216         }
 217
 218         return 0;
 219 }
 220
 221 /**
 222  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 223  * @hw: pointer to hardware structure
 224  */
 225 static void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 226 {
 227         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 228         s32 status;
 229         u16 value;
 230         u8 retry;
 231
 232         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 233                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 234                 if (status) {
 235                         hw_err(hw, "semaphore failed with %d\n", status);
 236                         msleep(IXGBE_CS4227_CHECK_DELAY);
 237                         continue;
 238                 }
 239
 240                 /* Get status of reset flow. */
 241                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 242                 if (!status && value == IXGBE_CS4227_RESET_COMPLETE)
 243                         goto out;
 244
 245                 if (status || value != IXGBE_CS4227_RESET_PENDING)
 246                         break;
 247
 248                 /* Reset is pending. Wait and check again. */
 249                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 250                 msleep(IXGBE_CS4227_CHECK_DELAY);
 251         }
 252         /* If still pending, assume other instance failed. */
 253         if (retry == IXGBE_CS4227_RETRIES) {
 254                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 255                 if (status) {
 256                         hw_err(hw, "semaphore failed with %d\n", status);
 257                         return;
 258                 }
 259         }
 260
 261         /* Reset the CS4227. */
 262         status = ixgbe_reset_cs4227(hw);
 263         if (status) {
 264                 hw_err(hw, "CS4227 reset failed: %d", status);
 265                 goto out;
 266         }
 267
 268         /* Reset takes so long, temporarily release semaphore in case the
 269          * other driver instance is waiting for the reset indication.
 270          */
 271         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 272                            IXGBE_CS4227_RESET_PENDING);
 273         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 274         usleep_range(10000, 12000);
 275         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 276         if (status) {
 277                 hw_err(hw, "semaphore failed with %d", status);
 278                 return;
 279         }
 280
 281         /* Record completion for next time. */
 282         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 283                                     IXGBE_CS4227_RESET_COMPLETE);
 284
 285 out:
 286         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 287         msleep(hw->eeprom.semaphore_delay);
 288 }
 289
 290 /** ixgbe_identify_phy_x550em - Get PHY type based on device id
 291  *  @hw: pointer to hardware structure
 292  *
 293  *  Returns error code
 294  */
 295 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 296 {
 297         switch (hw->device_id) {
 298         case IXGBE_DEV_ID_X550EM_A_SFP:
 299                 if (hw->bus.lan_id)
 300                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 301                 else
 302                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 303                 return ixgbe_identify_module_generic(hw);
 304         case IXGBE_DEV_ID_X550EM_X_SFP:
 305                 /* set up for CS4227 usage */
 306                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 307                 ixgbe_setup_mux_ctl(hw);
 308                 ixgbe_check_cs4227(hw);
 309                 fallthrough;
 310         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 311                 return ixgbe_identify_module_generic(hw);
 312         case IXGBE_DEV_ID_X550EM_X_KX4:
 313                 hw->phy.type = ixgbe_phy_x550em_kx4;
 314                 break;
 315         case IXGBE_DEV_ID_X550EM_X_XFI:
 316                 hw->phy.type = ixgbe_phy_x550em_xfi;
 317                 break;
 318         case IXGBE_DEV_ID_X550EM_X_KR:
 319         case IXGBE_DEV_ID_X550EM_A_KR:
 320         case IXGBE_DEV_ID_X550EM_A_KR_L:
 321                 hw->phy.type = ixgbe_phy_x550em_kr;
 322                 break;
 323         case IXGBE_DEV_ID_X550EM_A_10G_T:
 324                 if (hw->bus.lan_id)
 325                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 326                 else
 327                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 328                 fallthrough;
 329         case IXGBE_DEV_ID_X550EM_X_10G_T:
 330                 return ixgbe_identify_phy_generic(hw);
 331         case IXGBE_DEV_ID_X550EM_X_1G_T:
 332                 hw->phy.type = ixgbe_phy_ext_1g_t;
 333                 break;
 334         case IXGBE_DEV_ID_X550EM_A_1G_T:
 335         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 336                 hw->phy.type = ixgbe_phy_fw;
 337                 hw->phy.ops.read_reg = NULL;
 338                 hw->phy.ops.write_reg = NULL;
 339                 if (hw->bus.lan_id)
 340                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 341                 else
 342                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 343                 break;
 344         default:
 345                 break;
 346         }
 347         return 0;
 348 }
 349
 350 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 351                                      u32 device_type, u16 *phy_data)
 352 {
 353         return -EOPNOTSUPP;
 354 }
 355
 356 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 357                                       u32 device_type, u16 phy_data)
 358 {
 359         return -EOPNOTSUPP;
 360 }
 361
 362 /**
 363  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 364  * @hw: pointer to the hardware structure
 365  * @addr: I2C bus address to read from
 366  * @reg: I2C device register to read from
 367  * @val: pointer to location to receive read value
 368  *
 369  * Returns an error code on error.
 370  **/
 371 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 372                                            u16 reg, u16 *val)
 373 {
 374         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 375 }
 376
 377 /**
 378  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 379  * @hw: pointer to the hardware structure
 380  * @addr: I2C bus address to read from
 381  * @reg: I2C device register to read from
 382  * @val: pointer to location to receive read value
 383  *
 384  * Returns an error code on error.
 385  **/
 386 static s32
 387 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 388                                          u16 reg, u16 *val)
 389 {
 390         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 391 }
 392
 393 /**
 394  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 395  * @hw: pointer to the hardware structure
 396  * @addr: I2C bus address to write to
 397  * @reg: I2C device register to write to
 398  * @val: value to write
 399  *
 400  * Returns an error code on error.
 401  **/
 402 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 403                                             u8 addr, u16 reg, u16 val)
 404 {
 405         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 406 }
 407
 408 /**
 409  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 410  * @hw: pointer to the hardware structure
 411  * @addr: I2C bus address to write to
 412  * @reg: I2C device register to write to
 413  * @val: value to write
 414  *
 415  * Returns an error code on error.
 416  **/
 417 static s32
 418 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 419                                           u8 addr, u16 reg, u16 val)
 420 {
 421         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 422 }
 423
 424 /**
 425  * ixgbe_fw_phy_activity - Perform an activity on a PHY
 426  * @hw: pointer to hardware structure
 427  * @activity: activity to perform
 428  * @data: Pointer to 4 32-bit words of data
 429  */
 430 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
 431                           u32 (*data)[FW_PHY_ACT_DATA_COUNT])
 432 {
 433         union {
 434                 struct ixgbe_hic_phy_activity_req cmd;
 435                 struct ixgbe_hic_phy_activity_resp rsp;
 436         } hic;
 437         u16 retries = FW_PHY_ACT_RETRIES;
 438         s32 rc;
 439         u32 i;
 440
 441         do {
 442                 memset(&hic, 0, sizeof(hic));
 443                 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;
 444                 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;
 445                 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 446                 hic.cmd.port_number = hw->bus.lan_id;
 447                 hic.cmd.activity_id = cpu_to_le16(activity);
 448                 for (i = 0; i < ARRAY_SIZE(hic.cmd.data); ++i)
 449                         hic.cmd.data[i] = cpu_to_be32((*data)[i]);
 450
 451                 rc = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd),
 452                                                   IXGBE_HI_COMMAND_TIMEOUT,
 453                                                   true);
 454                 if (rc)
 455                         return rc;
 456                 if (hic.rsp.hdr.cmd_or_resp.ret_status ==
 457                     FW_CEM_RESP_STATUS_SUCCESS) {
 458                         for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
 459                                 (*data)[i] = be32_to_cpu(hic.rsp.data[i]);
 460                         return 0;
 461                 }
 462                 usleep_range(20, 30);
 463                 --retries;
 464         } while (retries > 0);
 465
 466         return -EIO;
 467 }
 468
 469 static const struct {
 470         u16 fw_speed;
 471         ixgbe_link_speed phy_speed;
 472 } ixgbe_fw_map[] = {
 473         { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL },
 474         { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL },
 475         { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL },
 476         { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL },
 477         { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL },
 478         { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL },
 479 };
 480
 481 /**
 482  * ixgbe_get_phy_id_fw - Get the phy ID via firmware command
 483  * @hw: pointer to hardware structure
 484  *
 485  * Returns error code
 486  */
 487 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)
 488 {
 489         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
 490         u16 phy_speeds;
 491         u16 phy_id_lo;
 492         s32 rc;
 493         u16 i;
 494
 495         if (hw->phy.id)
 496                 return 0;
 497
 498         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info);
 499         if (rc)
 500                 return rc;
 501
 502         hw->phy.speeds_supported = 0;
 503         phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK;
 504         for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) {
 505                 if (phy_speeds & ixgbe_fw_map[i].fw_speed)
 506                         hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;
 507         }
 508
 509         hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;
 510         phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK;
 511         hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;
 512         hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;
 513         if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)
 514                 return -EFAULT;
 515
 516         hw->phy.autoneg_advertised = hw->phy.speeds_supported;
 517         hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL |
 518                                        IXGBE_LINK_SPEED_1GB_FULL;
 519         hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
 520         return 0;
 521 }
 522
 523 /**
 524  * ixgbe_identify_phy_fw - Get PHY type based on firmware command
 525  * @hw: pointer to hardware structure
 526  *
 527  * Returns error code
 528  */
 529 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw)
 530 {
 531         if (hw->bus.lan_id)
 532                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 533         else
 534                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 535
 536         hw->phy.type = ixgbe_phy_fw;
 537         hw->phy.ops.read_reg = NULL;
 538         hw->phy.ops.write_reg = NULL;
 539         return ixgbe_get_phy_id_fw(hw);
 540 }
 541
 542 /**
 543  * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY
 544  * @hw: pointer to hardware structure
 545  *
 546  * Returns error code
 547  */
 548 static s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)
 549 {
 550         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 551
 552         setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF;
 553         return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup);
 554 }
 555
 556 /**
 557  * ixgbe_setup_fw_link - Setup firmware-controlled PHYs
 558  * @hw: pointer to hardware structure
 559  */
 560 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)
 561 {
 562         u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
 563         s32 rc;
 564         u16 i;
 565
 566         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
 567                 return 0;
 568
 569         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
 570                 hw_err(hw, "rx_pause not valid in strict IEEE mode\n");
 571                 return -EINVAL;
 572         }
 573
 574         switch (hw->fc.requested_mode) {
 575         case ixgbe_fc_full:
 576                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX <<
 577                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 578                 break;
 579         case ixgbe_fc_rx_pause:
 580                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX <<
 581                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 582                 break;
 583         case ixgbe_fc_tx_pause:
 584                 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX <<
 585                             FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
 586                 break;
 587         default:
 588                 break;
 589         }
 590
 591         for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) {
 592                 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
 593                         setup[0] |= ixgbe_fw_map[i].fw_speed;
 594         }
 595         setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;
 596
 597         if (hw->phy.eee_speeds_advertised)
 598                 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE;
 599
 600         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup);
 601         if (rc)
 602                 return rc;
 603
 604         if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)
 605                 return -EIO;
 606
 607         return 0;
 608 }
 609
 610 /**
 611  * ixgbe_fc_autoneg_fw - Set up flow control for FW-controlled PHYs
 612  * @hw: pointer to hardware structure
 613  *
 614  * Called at init time to set up flow control.
 615  */
 616 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)
 617 {
 618         if (hw->fc.requested_mode == ixgbe_fc_default)
 619                 hw->fc.requested_mode = ixgbe_fc_full;
 620
 621         return ixgbe_setup_fw_link(hw);
 622 }
 623
 624 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 625  *  @hw: pointer to hardware structure
 626  *
 627  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 628  *  ixgbe_hw struct in order to set up EEPROM access.
 629  **/
 630 static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 631 {
 632         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 633         u32 eec;
 634         u16 eeprom_size;
 635
 636         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 637                 eeprom->semaphore_delay = 10;
 638                 eeprom->type = ixgbe_flash;
 639
 640                 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
 641                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 642                                     IXGBE_EEC_SIZE_SHIFT);
 643                 eeprom->word_size = BIT(eeprom_size +
 644                                         IXGBE_EEPROM_WORD_SIZE_SHIFT);
 645
 646                 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
 647                        eeprom->type, eeprom->word_size);
 648         }
 649
 650         return 0;
 651 }
 652
 653 /**
 654  * ixgbe_iosf_wait - Wait for IOSF command completion
 655  * @hw: pointer to hardware structure
 656  * @ctrl: pointer to location to receive final IOSF control value
 657  *
 658  * Return: failing status on timeout
 659  *
 660  * Note: ctrl can be NULL if the IOSF control register value is not needed
 661  */
 662 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
 663 {
 664         u32 i, command;
 665
 666         /* Check every 10 usec to see if the address cycle completed.
 667          * The SB IOSF BUSY bit will clear when the operation is
 668          * complete.
 669          */
 670         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 671                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 672                 if (!(command & IXGBE_SB_IOSF_CTRL_BUSY))
 673                         break;
 674                 udelay(10);
 675         }
 676         if (ctrl)
 677                 *ctrl = command;
 678         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 679                 hw_dbg(hw, "IOSF wait timed out\n");
 680                 return -EIO;
 681         }
 682
 683         return 0;
 684 }
 685
 686 /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the
 687  *  IOSF device
 688  *  @hw: pointer to hardware structure
 689  *  @reg_addr: 32 bit PHY register to write
 690  *  @device_type: 3 bit device type
 691  *  @phy_data: Pointer to read data from the register
 692  **/
 693 static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 694                                        u32 device_type, u32 *data)
 695 {
 696         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 697         u32 command, error;
 698         s32 ret;
 699
 700         ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
 701         if (ret)
 702                 return ret;
 703
 704         ret = ixgbe_iosf_wait(hw, NULL);
 705         if (ret)
 706                 goto out;
 707
 708         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 709                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 710
 711         /* Write IOSF control register */
 712         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 713
 714         ret = ixgbe_iosf_wait(hw, &command);
 715
 716         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 717                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 718                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 719                 hw_dbg(hw, "Failed to read, error %x\n", error);
 720                 ret = -EIO;
 721                 goto out;
 722         }
 723
 724         if (!ret)
 725                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 726
 727 out:
 728         hw->mac.ops.release_swfw_sync(hw, gssr);
 729         return ret;
 730 }
 731
 732 /**
 733  * ixgbe_get_phy_token - Get the token for shared PHY access
 734  * @hw: Pointer to hardware structure
 735  */
 736 static s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
 737 {
 738         struct ixgbe_hic_phy_token_req token_cmd;
 739         s32 status;
 740
 741         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
 742         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
 743         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
 744         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 745         token_cmd.port_number = hw->bus.lan_id;
 746         token_cmd.command_type = FW_PHY_TOKEN_REQ;
 747         token_cmd.pad = 0;
 748         status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
 749                                               IXGBE_HI_COMMAND_TIMEOUT,
 750                                               true);
 751         if (status)
 752                 return status;
 753         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
 754                 return 0;
 755         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
 756                 return -EIO;
 757
 758         return -EAGAIN;
 759 }
 760
 761 /**
 762  * ixgbe_put_phy_token - Put the token for shared PHY access
 763  * @hw: Pointer to hardware structure
 764  */
 765 static s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
 766 {
 767         struct ixgbe_hic_phy_token_req token_cmd;
 768         s32 status;
 769
 770         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
 771         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
 772         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
 773         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 774         token_cmd.port_number = hw->bus.lan_id;
 775         token_cmd.command_type = FW_PHY_TOKEN_REL;
 776         token_cmd.pad = 0;
 777         status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
 778                                               IXGBE_HI_COMMAND_TIMEOUT,
 779                                               true);
 780         if (status)
 781                 return status;
 782         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
 783                 return 0;
 784         return -EIO;
 785 }
 786
 787 /**
 788  *  ixgbe_write_iosf_sb_reg_x550a - Write to IOSF PHY register
 789  *  @hw: pointer to hardware structure
 790  *  @reg_addr: 32 bit PHY register to write
 791  *  @device_type: 3 bit device type
 792  *  @data: Data to write to the register
 793  **/
 794 static s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
 795                                          __always_unused u32 device_type,
 796                                          u32 data)
 797 {
 798         struct ixgbe_hic_internal_phy_req write_cmd;
 799
 800         memset(&write_cmd, 0, sizeof(write_cmd));
 801         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
 802         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
 803         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 804         write_cmd.port_number = hw->bus.lan_id;
 805         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
 806         write_cmd.address = cpu_to_be16(reg_addr);
 807         write_cmd.write_data = cpu_to_be32(data);
 808
 809         return ixgbe_host_interface_command(hw, &write_cmd, sizeof(write_cmd),
 810                                             IXGBE_HI_COMMAND_TIMEOUT, false);
 811 }
 812
 813 /**
 814  *  ixgbe_read_iosf_sb_reg_x550a - Read from IOSF PHY register
 815  *  @hw: pointer to hardware structure
 816  *  @reg_addr: 32 bit PHY register to write
 817  *  @device_type: 3 bit device type
 818  *  @data: Pointer to read data from the register
 819  **/
 820 static s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
 821                                         __always_unused u32 device_type,
 822                                         u32 *data)
 823 {
 824         union {
 825                 struct ixgbe_hic_internal_phy_req cmd;
 826                 struct ixgbe_hic_internal_phy_resp rsp;
 827         } hic;
 828         s32 status;
 829
 830         memset(&hic, 0, sizeof(hic));
 831         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
 832         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
 833         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 834         hic.cmd.port_number = hw->bus.lan_id;
 835         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
 836         hic.cmd.address = cpu_to_be16(reg_addr);
 837
 838         status = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd),
 839                                               IXGBE_HI_COMMAND_TIMEOUT, true);
 840
 841         /* Extract the register value from the response. */
 842         *data = be32_to_cpu(hic.rsp.read_data);
 843
 844         return status;
 845 }
 846
 847 /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
 848  *  @hw: pointer to hardware structure
 849  *  @offset: offset of  word in the EEPROM to read
 850  *  @words: number of words
 851  *  @data: word(s) read from the EEPROM
 852  *
 853  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
 854  **/
 855 static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
 856                                             u16 offset, u16 words, u16 *data)
 857 {
 858         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
 859         struct ixgbe_hic_read_shadow_ram buffer;
 860         u32 current_word = 0;
 861         u16 words_to_read;
 862         s32 status;
 863         u32 i;
 864
 865         /* Take semaphore for the entire operation. */
 866         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
 867         if (status) {
 868                 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n");
 869                 return status;
 870         }
 871
 872         while (words) {
 873                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
 874                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
 875                 else
 876                         words_to_read = words;
 877
 878                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
 879                 buffer.hdr.req.buf_lenh = 0;
 880                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
 881                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 882
 883                 /* convert offset from words to bytes */
 884                 buffer.address = (__force u32)cpu_to_be32((offset +
 885                                                            current_word) * 2);
 886                 buffer.length = (__force u16)cpu_to_be16(words_to_read * 2);
 887                 buffer.pad2 = 0;
 888                 buffer.pad3 = 0;
 889
 890                 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
 891                                             IXGBE_HI_COMMAND_TIMEOUT);
 892                 if (status) {
 893                         hw_dbg(hw, "Host interface command failed\n");
 894                         goto out;
 895                 }
 896
 897                 for (i = 0; i < words_to_read; i++) {
 898                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
 899                                   2 * i;
 900                         u32 value = IXGBE_READ_REG(hw, reg);
 901
 902                         data[current_word] = (u16)(value & 0xffff);
 903                         current_word++;
 904                         i++;
 905                         if (i < words_to_read) {
 906                                 value >>= 16;
 907                                 data[current_word] = (u16)(value & 0xffff);
 908                                 current_word++;
 909                         }
 910                 }
 911                 words -= words_to_read;
 912         }
 913
 914 out:
 915         hw->mac.ops.release_swfw_sync(hw, mask);
 916         return status;
 917 }
 918
 919 /** ixgbe_checksum_ptr_x550 - Checksum one pointer region
 920  *  @hw: pointer to hardware structure
 921  *  @ptr: pointer offset in eeprom
 922  *  @size: size of section pointed by ptr, if 0 first word will be used as size
 923  *  @csum: address of checksum to update
 924  *
 925  *  Returns error status for any failure
 926  **/
 927 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
 928                                    u16 size, u16 *csum, u16 *buffer,
 929                                    u32 buffer_size)
 930 {
 931         u16 buf[256];
 932         s32 status;
 933         u16 length, bufsz, i, start;
 934         u16 *local_buffer;
 935
 936         bufsz = ARRAY_SIZE(buf);
 937
 938         /* Read a chunk at the pointer location */
 939         if (!buffer) {
 940                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
 941                 if (status) {
 942                         hw_dbg(hw, "Failed to read EEPROM image\n");
 943                         return status;
 944                 }
 945                 local_buffer = buf;
 946         } else {
 947                 if (buffer_size < ptr)
 948                         return  -EINVAL;
 949                 local_buffer = &buffer[ptr];
 950         }
 951
 952         if (size) {
 953                 start = 0;
 954                 length = size;
 955         } else {
 956                 start = 1;
 957                 length = local_buffer[0];
 958
 959                 /* Skip pointer section if length is invalid. */
 960                 if (length == 0xFFFF || length == 0 ||
 961                     (ptr + length) >= hw->eeprom.word_size)
 962                         return 0;
 963         }
 964
 965         if (buffer && ((u32)start + (u32)length > buffer_size))
 966                 return -EINVAL;
 967
 968         for (i = start; length; i++, length--) {
 969                 if (i == bufsz && !buffer) {
 970                         ptr += bufsz;
 971                         i = 0;
 972                         if (length < bufsz)
 973                                 bufsz = length;
 974
 975                         /* Read a chunk at the pointer location */
 976                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
 977                                                                   bufsz, buf);
 978                         if (status) {
 979                                 hw_dbg(hw, "Failed to read EEPROM image\n");
 980                                 return status;
 981                         }
 982                 }
 983                 *csum += local_buffer[i];
 984         }
 985         return 0;
 986 }
 987
 988 /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum
 989  *  @hw: pointer to hardware structure
 990  *  @buffer: pointer to buffer containing calculated checksum
 991  *  @buffer_size: size of buffer
 992  *
 993  *  Returns a negative error code on error, or the 16-bit checksum
 994  **/
 995 static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer,
 996                                     u32 buffer_size)
 997 {
 998         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
 999         u16 *local_buffer;
1000         s32 status;
1001         u16 checksum = 0;
1002         u16 pointer, i, size;
1003
1004         hw->eeprom.ops.init_params(hw);
1005
1006         if (!buffer) {
1007                 /* Read pointer area */
1008                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
1009                                                 IXGBE_EEPROM_LAST_WORD + 1,
1010                                                 eeprom_ptrs);
1011                 if (status) {
1012                         hw_dbg(hw, "Failed to read EEPROM image\n");
1013                         return status;
1014                 }
1015                 local_buffer = eeprom_ptrs;
1016         } else {
1017                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
1018                         return -EINVAL;
1019                 local_buffer = buffer;
1020         }
1021
1022         /* For X550 hardware include 0x0-0x41 in the checksum, skip the
1023          * checksum word itself
1024          */
1025         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
1026                 if (i != IXGBE_EEPROM_CHECKSUM)
1027                         checksum += local_buffer[i];
1028
1029         /* Include all data from pointers 0x3, 0x6-0xE.  This excludes the
1030          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
1031          */
1032         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
1033                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
1034                         continue;
1035
1036                 pointer = local_buffer[i];
1037
1038                 /* Skip pointer section if the pointer is invalid. */
1039                 if (pointer == 0xFFFF || pointer == 0 ||
1040                     pointer >= hw->eeprom.word_size)
1041                         continue;
1042
1043                 switch (i) {
1044                 case IXGBE_PCIE_GENERAL_PTR:
1045                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
1046                         break;
1047                 case IXGBE_PCIE_CONFIG0_PTR:
1048                 case IXGBE_PCIE_CONFIG1_PTR:
1049                         size = IXGBE_PCIE_CONFIG_SIZE;
1050                         break;
1051                 default:
1052                         size = 0;
1053                         break;
1054                 }
1055
1056                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
1057                                                  buffer, buffer_size);
1058                 if (status)
1059                         return status;
1060         }
1061
1062         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1063
1064         return (s32)checksum;
1065 }
1066
1067 /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
1068  *  @hw: pointer to hardware structure
1069  *
1070  *  Returns a negative error code on error, or the 16-bit checksum
1071  **/
1072 static s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
1073 {
1074         return ixgbe_calc_checksum_X550(hw, NULL, 0);
1075 }
1076
1077 /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1078  *  @hw: pointer to hardware structure
1079  *  @offset: offset of  word in the EEPROM to read
1080  *  @data: word read from the EEPROM
1081  *
1082  *   Reads a 16 bit word from the EEPROM using the hostif.
1083  **/
1084 static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
1085 {
1086         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
1087         struct ixgbe_hic_read_shadow_ram buffer;
1088         s32 status;
1089
1090         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1091         buffer.hdr.req.buf_lenh = 0;
1092         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1093         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1094
1095         /* convert offset from words to bytes */
1096         buffer.address = (__force u32)cpu_to_be32(offset * 2);
1097         /* one word */
1098         buffer.length = (__force u16)cpu_to_be16(sizeof(u16));
1099
1100         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
1101         if (status)
1102                 return status;
1103
1104         status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
1105                                     IXGBE_HI_COMMAND_TIMEOUT);
1106         if (!status) {
1107                 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1108                                                   FW_NVM_DATA_OFFSET);
1109         }
1110
1111         hw->mac.ops.release_swfw_sync(hw, mask);
1112         return status;
1113 }
1114
1115 /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
1116  *  @hw: pointer to hardware structure
1117  *  @checksum_val: calculated checksum
1118  *
1119  *  Performs checksum calculation and validates the EEPROM checksum.  If the
1120  *  caller does not need checksum_val, the value can be NULL.
1121  **/
1122 static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw,
1123                                                u16 *checksum_val)
1124 {
1125         s32 status;
1126         u16 checksum;
1127         u16 read_checksum = 0;
1128
1129         /* Read the first word from the EEPROM. If this times out or fails, do
1130          * not continue or we could be in for a very long wait while every
1131          * EEPROM read fails
1132          */
1133         status = hw->eeprom.ops.read(hw, 0, &checksum);
1134         if (status) {
1135                 hw_dbg(hw, "EEPROM read failed\n");
1136                 return status;
1137         }
1138
1139         status = hw->eeprom.ops.calc_checksum(hw);
1140         if (status < 0)
1141                 return status;
1142
1143         checksum = (u16)(status & 0xffff);
1144
1145         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1146                                            &read_checksum);
1147         if (status)
1148                 return status;
1149
1150         /* Verify read checksum from EEPROM is the same as
1151          * calculated checksum
1152          */
1153         if (read_checksum != checksum) {
1154                 status = -EIO;
1155                 hw_dbg(hw, "Invalid EEPROM checksum");
1156         }
1157
1158         /* If the user cares, return the calculated checksum */
1159         if (checksum_val)
1160                 *checksum_val = checksum;
1161
1162         return status;
1163 }
1164
1165 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1166  *  @hw: pointer to hardware structure
1167  *  @offset: offset of  word in the EEPROM to write
1168  *  @data: word write to the EEPROM
1169  *
1170  *  Write a 16 bit word to the EEPROM using the hostif.
1171  **/
1172 static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1173                                            u16 data)
1174 {
1175         s32 status;
1176         struct ixgbe_hic_write_shadow_ram buffer;
1177
1178         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
1179         buffer.hdr.req.buf_lenh = 0;
1180         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
1181         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1182
1183         /* one word */
1184         buffer.length = cpu_to_be16(sizeof(u16));
1185         buffer.data = data;
1186         buffer.address = cpu_to_be32(offset * 2);
1187
1188         status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
1189                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1190         return status;
1191 }
1192
1193 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1194  *  @hw: pointer to hardware structure
1195  *  @offset: offset of  word in the EEPROM to write
1196  *  @data: word write to the EEPROM
1197  *
1198  *  Write a 16 bit word to the EEPROM using the hostif.
1199  **/
1200 static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data)
1201 {
1202         s32 status = 0;
1203
1204         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
1205                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1206                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1207         } else {
1208                 hw_dbg(hw, "write ee hostif failed to get semaphore");
1209                 status = -EBUSY;
1210         }
1211
1212         return status;
1213 }
1214
1215 /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
1216  *  @hw: pointer to hardware structure
1217  *
1218  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
1219  **/
1220 static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
1221 {
1222         s32 status = 0;
1223         union ixgbe_hic_hdr2 buffer;
1224
1225         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
1226         buffer.req.buf_lenh = 0;
1227         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
1228         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
1229
1230         status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
1231                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1232         return status;
1233 }
1234
1235 /**
1236  * ixgbe_get_bus_info_X550em - Set PCI bus info
1237  * @hw: pointer to hardware structure
1238  *
1239  * Sets bus link width and speed to unknown because X550em is
1240  * not a PCI device.
1241  **/
1242 static s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
1243 {
1244         hw->bus.type  = ixgbe_bus_type_internal;
1245         hw->bus.width = ixgbe_bus_width_unknown;
1246         hw->bus.speed = ixgbe_bus_speed_unknown;
1247
1248         hw->mac.ops.set_lan_id(hw);
1249
1250         return 0;
1251 }
1252
1253 /**
1254  * ixgbe_fw_recovery_mode_X550 - Check FW NVM recovery mode
1255  * @hw: pointer t hardware structure
1256  *
1257  * Returns true if in FW NVM recovery mode.
1258  */
1259 static bool ixgbe_fw_recovery_mode_X550(struct ixgbe_hw *hw)
1260 {
1261         u32 fwsm;
1262
1263         fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
1264         return !!(fwsm & IXGBE_FWSM_FW_NVM_RECOVERY_MODE);
1265 }
1266
1267 /** ixgbe_disable_rx_x550 - Disable RX unit
1268  *
1269  *  Enables the Rx DMA unit for x550
1270  **/
1271 static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
1272 {
1273         u32 rxctrl, pfdtxgswc;
1274         s32 status;
1275         struct ixgbe_hic_disable_rxen fw_cmd;
1276
1277         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1278         if (rxctrl & IXGBE_RXCTRL_RXEN) {
1279                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
1280                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
1281                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
1282                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
1283                         hw->mac.set_lben = true;
1284                 } else {
1285                         hw->mac.set_lben = false;
1286                 }
1287
1288                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
1289                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
1290                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1291                 fw_cmd.port_number = hw->bus.lan_id;
1292
1293                 status = ixgbe_host_interface_command(hw, &fw_cmd,
1294                                         sizeof(struct ixgbe_hic_disable_rxen),
1295                                         IXGBE_HI_COMMAND_TIMEOUT, true);
1296
1297                 /* If we fail - disable RX using register write */
1298                 if (status) {
1299                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1300                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
1301                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
1302                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
1303                         }
1304                 }
1305         }
1306 }
1307
1308 /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
1309  *  @hw: pointer to hardware structure
1310  *
1311  *  After writing EEPROM to shadow RAM using EEWR register, software calculates
1312  *  checksum and updates the EEPROM and instructs the hardware to update
1313  *  the flash.
1314  **/
1315 static s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
1316 {
1317         s32 status;
1318         u16 checksum = 0;
1319
1320         /* Read the first word from the EEPROM. If this times out or fails, do
1321          * not continue or we could be in for a very long wait while every
1322          * EEPROM read fails
1323          */
1324         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
1325         if (status) {
1326                 hw_dbg(hw, "EEPROM read failed\n");
1327                 return status;
1328         }
1329
1330         status = ixgbe_calc_eeprom_checksum_X550(hw);
1331         if (status < 0)
1332                 return status;
1333
1334         checksum = (u16)(status & 0xffff);
1335
1336         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1337                                             checksum);
1338         if (status)
1339                 return status;
1340
1341         status = ixgbe_update_flash_X550(hw);
1342
1343         return status;
1344 }
1345
1346 /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1347  *  @hw: pointer to hardware structure
1348  *  @offset: offset of  word in the EEPROM to write
1349  *  @words: number of words
1350  *  @data: word(s) write to the EEPROM
1351  *
1352  *
1353  *  Write a 16 bit word(s) to the EEPROM using the hostif.
1354  **/
1355 static s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1356                                              u16 offset, u16 words,
1357                                              u16 *data)
1358 {
1359         s32 status = 0;
1360         u32 i = 0;
1361
1362         /* Take semaphore for the entire operation. */
1363         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1364         if (status) {
1365                 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n");
1366                 return status;
1367         }
1368
1369         for (i = 0; i < words; i++) {
1370                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1371                                                          data[i]);
1372                 if (status) {
1373                         hw_dbg(hw, "Eeprom buffered write failed\n");
1374                         break;
1375                 }
1376         }
1377
1378         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1379
1380         return status;
1381 }
1382
1383 /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the
1384  *  IOSF device
1385  *
1386  *  @hw: pointer to hardware structure
1387  *  @reg_addr: 32 bit PHY register to write
1388  *  @device_type: 3 bit device type
1389  *  @data: Data to write to the register
1390  **/
1391 static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1392                                         u32 device_type, u32 data)
1393 {
1394         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1395         u32 command, error;
1396         s32 ret;
1397
1398         ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
1399         if (ret)
1400                 return ret;
1401
1402         ret = ixgbe_iosf_wait(hw, NULL);
1403         if (ret)
1404                 goto out;
1405
1406         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1407                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1408
1409         /* Write IOSF control register */
1410         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1411
1412         /* Write IOSF data register */
1413         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1414
1415         ret = ixgbe_iosf_wait(hw, &command);
1416
1417         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1418                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1419                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1420                 hw_dbg(hw, "Failed to write, error %x\n", error);
1421                 return -EIO;
1422         }
1423
1424 out:
1425         hw->mac.ops.release_swfw_sync(hw, gssr);
1426         return ret;
1427 }
1428
1429 /**
1430  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
1431  *  @hw: pointer to hardware structure
1432  *
1433  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
1434  **/
1435 static s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
1436 {
1437         s32 status;
1438         u32 reg_val;
1439
1440         /* Disable training protocol FSM. */
1441         status = ixgbe_read_iosf_sb_reg_x550(hw,
1442                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1443                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1444         if (status)
1445                 return status;
1446
1447         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1448         status = ixgbe_write_iosf_sb_reg_x550(hw,
1449                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1450                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1451         if (status)
1452                 return status;
1453
1454         /* Disable Flex from training TXFFE. */
1455         status = ixgbe_read_iosf_sb_reg_x550(hw,
1456                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1457                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1458         if (status)
1459                 return status;
1460
1461         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1462         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1463         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1464         status = ixgbe_write_iosf_sb_reg_x550(hw,
1465                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1466                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1467         if (status)
1468                 return status;
1469
1470         status = ixgbe_read_iosf_sb_reg_x550(hw,
1471                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1472                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1473         if (status)
1474                 return status;
1475
1476         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1477         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1478         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1479         status = ixgbe_write_iosf_sb_reg_x550(hw,
1480                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1481                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1482         if (status)
1483                 return status;
1484
1485         /* Enable override for coefficients. */
1486         status = ixgbe_read_iosf_sb_reg_x550(hw,
1487                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1488                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1489         if (status)
1490                 return status;
1491
1492         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1493         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1494         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1495         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1496         status = ixgbe_write_iosf_sb_reg_x550(hw,
1497                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1498                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1499         return status;
1500 }
1501
1502 /**
1503  *  ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1504  *  internal PHY
1505  *  @hw: pointer to hardware structure
1506  **/
1507 static s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1508 {
1509         s32 status;
1510         u32 link_ctrl;
1511
1512         /* Restart auto-negotiation. */
1513         status = hw->mac.ops.read_iosf_sb_reg(hw,
1514                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1515                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1516
1517         if (status) {
1518                 hw_dbg(hw, "Auto-negotiation did not complete\n");
1519                 return status;
1520         }
1521
1522         link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1523         status = hw->mac.ops.write_iosf_sb_reg(hw,
1524                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1525                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1526
1527         if (hw->mac.type == ixgbe_mac_x550em_a) {
1528                 u32 flx_mask_st20;
1529
1530                 /* Indicate to FW that AN restart has been asserted */
1531                 status = hw->mac.ops.read_iosf_sb_reg(hw,
1532                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1533                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1534
1535                 if (status) {
1536                         hw_dbg(hw, "Auto-negotiation did not complete\n");
1537                         return status;
1538                 }
1539
1540                 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1541                 status = hw->mac.ops.write_iosf_sb_reg(hw,
1542                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1543                                 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1544         }
1545
1546         return status;
1547 }
1548
1549 /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1550  *  @hw: pointer to hardware structure
1551  *  @speed: the link speed to force
1552  *
1553  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1554  *  internal and external PHY at a specific speed, without autonegotiation.
1555  **/
1556 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1557 {
1558         struct ixgbe_mac_info *mac = &hw->mac;
1559         s32 status;
1560         u32 reg_val;
1561
1562         /* iXFI is only supported with X552 */
1563         if (mac->type != ixgbe_mac_X550EM_x)
1564                 return -EIO;
1565
1566         /* Disable AN and force speed to 10G Serial. */
1567         status = ixgbe_read_iosf_sb_reg_x550(hw,
1568                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1569                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1570         if (status)
1571                 return status;
1572
1573         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1574         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1575
1576         /* Select forced link speed for internal PHY. */
1577         switch (*speed) {
1578         case IXGBE_LINK_SPEED_10GB_FULL:
1579                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1580                 break;
1581         case IXGBE_LINK_SPEED_1GB_FULL:
1582                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1583                 break;
1584         default:
1585                 /* Other link speeds are not supported by internal KR PHY. */
1586                 return -EINVAL;
1587         }
1588
1589         status = ixgbe_write_iosf_sb_reg_x550(hw,
1590                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1591                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1592         if (status)
1593                 return status;
1594
1595         /* Additional configuration needed for x550em_x */
1596         if (hw->mac.type == ixgbe_mac_X550EM_x) {
1597                 status = ixgbe_setup_ixfi_x550em_x(hw);
1598                 if (status)
1599                         return status;
1600         }
1601
1602         /* Toggle port SW reset by AN reset. */
1603         status = ixgbe_restart_an_internal_phy_x550em(hw);
1604
1605         return status;
1606 }
1607
1608 /**
1609  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1610  *  @hw: pointer to hardware structure
1611  *  @linear: true if SFP module is linear
1612  */
1613 static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1614 {
1615         switch (hw->phy.sfp_type) {
1616         case ixgbe_sfp_type_not_present:
1617                 return -ENOENT;
1618         case ixgbe_sfp_type_da_cu_core0:
1619         case ixgbe_sfp_type_da_cu_core1:
1620                 *linear = true;
1621                 break;
1622         case ixgbe_sfp_type_srlr_core0:
1623         case ixgbe_sfp_type_srlr_core1:
1624         case ixgbe_sfp_type_da_act_lmt_core0:
1625         case ixgbe_sfp_type_da_act_lmt_core1:
1626         case ixgbe_sfp_type_1g_sx_core0:
1627         case ixgbe_sfp_type_1g_sx_core1:
1628         case ixgbe_sfp_type_1g_lx_core0:
1629         case ixgbe_sfp_type_1g_lx_core1:
1630                 *linear = false;
1631                 break;
1632         case ixgbe_sfp_type_unknown:
1633         case ixgbe_sfp_type_1g_cu_core0:
1634         case ixgbe_sfp_type_1g_cu_core1:
1635         default:
1636                 return -EOPNOTSUPP;
1637         }
1638
1639         return 0;
1640 }
1641
1642 /**
1643  * ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1644  * @hw: pointer to hardware structure
1645  * @speed: the link speed to force
1646  * @autoneg_wait_to_complete: unused
1647  *
1648  * Configures the extern PHY and the integrated KR PHY for SFP support.
1649  */
1650 static s32
1651 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1652                                 ixgbe_link_speed speed,
1653                                 __always_unused bool autoneg_wait_to_complete)
1654 {
1655         s32 status;
1656         u16 reg_slice, reg_val;
1657         bool setup_linear = false;
1658
1659         /* Check if SFP module is supported and linear */
1660         status = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1661
1662         /* If no SFP module present, then return success. Return success since
1663          * there is no reason to configure CS4227 and SFP not present error is
1664          * not accepted in the setup MAC link flow.
1665          */
1666         if (status == -ENOENT)
1667                 return 0;
1668
1669         if (status)
1670                 return status;
1671
1672         /* Configure internal PHY for KR/KX. */
1673         ixgbe_setup_kr_speed_x550em(hw, speed);
1674
1675         /* Configure CS4227 LINE side to proper mode. */
1676         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1677         if (setup_linear)
1678                 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1679         else
1680                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1681
1682         status = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
1683                                          reg_val);
1684
1685         return status;
1686 }
1687
1688 /**
1689  * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
1690  * @hw: pointer to hardware structure
1691  * @speed: the link speed to force
1692  *
1693  * Configures the integrated PHY for native SFI mode. Used to connect the
1694  * internal PHY directly to an SFP cage, without autonegotiation.
1695  **/
1696 static s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1697 {
1698         struct ixgbe_mac_info *mac = &hw->mac;
1699         s32 status;
1700         u32 reg_val;
1701
1702         /* Disable all AN and force speed to 10G Serial. */
1703         status = mac->ops.read_iosf_sb_reg(hw,
1704                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1705                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1706         if (status)
1707                 return status;
1708
1709         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1710         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1711         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1712         reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1713
1714         /* Select forced link speed for internal PHY. */
1715         switch (*speed) {
1716         case IXGBE_LINK_SPEED_10GB_FULL:
1717                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
1718                 break;
1719         case IXGBE_LINK_SPEED_1GB_FULL:
1720                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1721                 break;
1722         default:
1723                 /* Other link speeds are not supported by internal PHY. */
1724                 return -EINVAL;
1725         }
1726
1727         (void)mac->ops.write_iosf_sb_reg(hw,
1728                         IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1729                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1730
1731         /* change mode enforcement rules to hybrid */
1732         (void)mac->ops.read_iosf_sb_reg(hw,
1733                         IXGBE_KRM_FLX_TMRS_CTRL_ST31(hw->bus.lan_id),
1734                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1735         reg_val |= 0x0400;
1736
1737         (void)mac->ops.write_iosf_sb_reg(hw,
1738                         IXGBE_KRM_FLX_TMRS_CTRL_ST31(hw->bus.lan_id),
1739                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1740
1741         /* manually control the config */
1742         (void)mac->ops.read_iosf_sb_reg(hw,
1743                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1744                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1745         reg_val |= 0x20002240;
1746
1747         (void)mac->ops.write_iosf_sb_reg(hw,
1748                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1749                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1750
1751         /* move the AN base page values */
1752         (void)mac->ops.read_iosf_sb_reg(hw,
1753                         IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
1754                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1755         reg_val |= 0x1;
1756
1757         (void)mac->ops.write_iosf_sb_reg(hw,
1758                         IXGBE_KRM_PCS_KX_AN(hw->bus.lan_id),
1759                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1760
1761         /* set the AN37 over CB mode */
1762         (void)mac->ops.read_iosf_sb_reg(hw,
1763                         IXGBE_KRM_AN_CNTL_4(hw->bus.lan_id),
1764                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1765         reg_val |= 0x20000000;
1766
1767         (void)mac->ops.write_iosf_sb_reg(hw,
1768                         IXGBE_KRM_AN_CNTL_4(hw->bus.lan_id),
1769                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1770
1771         /* restart AN manually */
1772         (void)mac->ops.read_iosf_sb_reg(hw,
1773                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1774                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1775         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1776
1777         (void)mac->ops.write_iosf_sb_reg(hw,
1778                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1779                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1780
1781         /* Toggle port SW reset by AN reset. */
1782         status = ixgbe_restart_an_internal_phy_x550em(hw);
1783
1784         return status;
1785 }
1786
1787 /**
1788  * ixgbe_setup_mac_link_sfp_n - Setup internal PHY for native SFP
1789  * @hw: pointer to hardware structure
1790  * @speed: link speed
1791  * @autoneg_wait_to_complete: unused
1792  *
1793  * Configure the integrated PHY for native SFP support.
1794  */
1795 static s32
1796 ixgbe_setup_mac_link_sfp_n(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1797                            __always_unused bool autoneg_wait_to_complete)
1798 {
1799         bool setup_linear = false;
1800         u32 reg_phy_int;
1801         s32 ret_val;
1802
1803         /* Check if SFP module is supported and linear */
1804         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1805
1806         /* If no SFP module present, then return success. Return success since
1807          * SFP not present error is not excepted in the setup MAC link flow.
1808          */
1809         if (ret_val == -ENOENT)
1810                 return 0;
1811
1812         if (ret_val)
1813                 return ret_val;
1814
1815         /* Configure internal PHY for native SFI based on module type */
1816         ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
1817                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1818                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
1819         if (ret_val)
1820                 return ret_val;
1821
1822         reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
1823         if (!setup_linear)
1824                 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
1825
1826         ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
1827                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1828                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
1829         if (ret_val)
1830                 return ret_val;
1831
1832         /* Setup SFI internal link. */
1833         return ixgbe_setup_sfi_x550a(hw, &speed);
1834 }
1835
1836 /**
1837  * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
1838  * @hw: pointer to hardware structure
1839  * @speed: link speed
1840  * @autoneg_wait_to_complete: unused
1841  *
1842  * Configure the integrated PHY for SFP support.
1843  */
1844 static s32
1845 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1846                                __always_unused bool autoneg_wait_to_complete)
1847 {
1848         u32 reg_slice, slice_offset;
1849         bool setup_linear = false;
1850         u16 reg_phy_ext;
1851         s32 ret_val;
1852
1853         /* Check if SFP module is supported and linear */
1854         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1855
1856         /* If no SFP module present, then return success. Return success since
1857          * SFP not present error is not excepted in the setup MAC link flow.
1858          */
1859         if (ret_val == -ENOENT)
1860                 return 0;
1861
1862         if (ret_val)
1863                 return ret_val;
1864
1865         /* Configure internal PHY for KR/KX. */
1866         ixgbe_setup_kr_speed_x550em(hw, speed);
1867
1868         if (hw->phy.mdio.prtad == MDIO_PRTAD_NONE)
1869                 return -EFAULT;
1870
1871         /* Get external PHY SKU id */
1872         ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
1873                                        IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
1874         if (ret_val)
1875                 return ret_val;
1876
1877         /* When configuring quad port CS4223, the MAC instance is part
1878          * of the slice offset.
1879          */
1880         if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
1881                 slice_offset = (hw->bus.lan_id +
1882                                 (hw->bus.instance_id << 1)) << 12;
1883         else
1884                 slice_offset = hw->bus.lan_id << 12;
1885
1886         /* Configure CS4227/CS4223 LINE side to proper mode. */
1887         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
1888
1889         ret_val = hw->phy.ops.read_reg(hw, reg_slice,
1890                                        IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
1891         if (ret_val)
1892                 return ret_val;
1893
1894         reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) |
1895                          (IXGBE_CS4227_EDC_MODE_SR << 1));
1896
1897         if (setup_linear)
1898                 reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;
1899         else
1900                 reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1901
1902         ret_val = hw->phy.ops.write_reg(hw, reg_slice,
1903                                         IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
1904         if (ret_val)
1905                 return ret_val;
1906
1907         /* Flush previous write with a read */
1908         return hw->phy.ops.read_reg(hw, reg_slice,
1909                                     IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
1910 }
1911
1912 /**
1913  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
1914  * @hw: pointer to hardware structure
1915  * @speed: new link speed
1916  * @autoneg_wait: true when waiting for completion is needed
1917  *
1918  * Setup internal/external PHY link speed based on link speed, then set
1919  * external PHY auto advertised link speed.
1920  *
1921  * Returns error status for any failure
1922  **/
1923 static s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
1924                                          ixgbe_link_speed speed,
1925                                          bool autoneg_wait)
1926 {
1927         s32 status;
1928         ixgbe_link_speed force_speed;
1929
1930         /* Setup internal/external PHY link speed to iXFI (10G), unless
1931          * only 1G is auto advertised then setup KX link.
1932          */
1933         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1934                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1935         else
1936                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1937
1938         /* If X552 and internal link mode is XFI, then setup XFI internal link.
1939          */
1940         if (hw->mac.type == ixgbe_mac_X550EM_x &&
1941             !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1942                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
1943
1944                 if (status)
1945                         return status;
1946         }
1947
1948         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1949 }
1950
1951 /** ixgbe_check_link_t_X550em - Determine link and speed status
1952   * @hw: pointer to hardware structure
1953   * @speed: pointer to link speed
1954   * @link_up: true when link is up
1955   * @link_up_wait_to_complete: bool used to wait for link up or not
1956   *
1957   * Check that both the MAC and X557 external PHY have link.
1958   **/
1959 static s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw,
1960                                      ixgbe_link_speed *speed,
1961                                      bool *link_up,
1962                                      bool link_up_wait_to_complete)
1963 {
1964         u32 status;
1965         u16 i, autoneg_status;
1966
1967         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1968                 return -EIO;
1969
1970         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
1971                                               link_up_wait_to_complete);
1972
1973         /* If check link fails or MAC link is not up, then return */
1974         if (status || !(*link_up))
1975                 return status;
1976
1977         /* MAC link is up, so check external PHY link.
1978          * Link status is latching low, and can only be used to detect link
1979          * drop, and not the current status of the link without performing
1980          * back-to-back reads.
1981          */
1982         for (i = 0; i < 2; i++) {
1983                 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
1984                                               &autoneg_status);
1985
1986                 if (status)
1987                         return status;
1988         }
1989
1990         /* If external PHY link is not up, then indicate link not up */
1991         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1992                 *link_up = false;
1993
1994         return 0;
1995 }
1996
1997 /**
1998  * ixgbe_setup_sgmii - Set up link for sgmii
1999  * @hw: pointer to hardware structure
2000  * @speed: unused
2001  * @autoneg_wait_to_complete: unused
2002  */
2003 static s32
2004 ixgbe_setup_sgmii(struct ixgbe_hw *hw, __always_unused ixgbe_link_speed speed,
2005                   __always_unused bool autoneg_wait_to_complete)
2006 {
2007         struct ixgbe_mac_info *mac = &hw->mac;
2008         u32 lval, sval, flx_val;
2009         s32 rc;
2010
2011         rc = mac->ops.read_iosf_sb_reg(hw,
2012                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2013                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
2014         if (rc)
2015                 return rc;
2016
2017         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2018         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2019         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
2020         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
2021         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2022         rc = mac->ops.write_iosf_sb_reg(hw,
2023                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2024                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
2025         if (rc)
2026                 return rc;
2027
2028         rc = mac->ops.read_iosf_sb_reg(hw,
2029                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
2030                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
2031         if (rc)
2032                 return rc;
2033
2034         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
2035         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
2036         rc = mac->ops.write_iosf_sb_reg(hw,
2037                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
2038                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
2039         if (rc)
2040                 return rc;
2041
2042         rc = mac->ops.read_iosf_sb_reg(hw,
2043                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2044                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
2045         if (rc)
2046                 return rc;
2047
2048         rc = mac->ops.read_iosf_sb_reg(hw,
2049                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2050                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
2051         if (rc)
2052                 return rc;
2053
2054         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2055         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2056         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2057         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2058         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2059
2060         rc = mac->ops.write_iosf_sb_reg(hw,
2061                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2062                                 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
2063         if (rc)
2064                 return rc;
2065
2066         rc = ixgbe_restart_an_internal_phy_x550em(hw);
2067         return rc;
2068 }
2069
2070 /**
2071  * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs
2072  * @hw: pointer to hardware structure
2073  * @speed: the link speed to force
2074  * @autoneg_wait: true when waiting for completion is needed
2075  */
2076 static s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed,
2077                                 bool autoneg_wait)
2078 {
2079         struct ixgbe_mac_info *mac = &hw->mac;
2080         u32 lval, sval, flx_val;
2081         s32 rc;
2082
2083         rc = mac->ops.read_iosf_sb_reg(hw,
2084                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2085                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
2086         if (rc)
2087                 return rc;
2088
2089         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2090         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2091         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
2092         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
2093         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2094         rc = mac->ops.write_iosf_sb_reg(hw,
2095                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2096                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
2097         if (rc)
2098                 return rc;
2099
2100         rc = mac->ops.read_iosf_sb_reg(hw,
2101                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
2102                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
2103         if (rc)
2104                 return rc;
2105
2106         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
2107         sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
2108         rc = mac->ops.write_iosf_sb_reg(hw,
2109                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
2110                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
2111         if (rc)
2112                 return rc;
2113
2114         rc = mac->ops.write_iosf_sb_reg(hw,
2115                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2116                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
2117         if (rc)
2118                 return rc;
2119
2120         rc = mac->ops.read_iosf_sb_reg(hw,
2121                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2122                                     IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
2123         if (rc)
2124                 return rc;
2125
2126         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2127         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2128         flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2129         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2130         flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2131
2132         rc = mac->ops.write_iosf_sb_reg(hw,
2133                                     IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2134                                     IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
2135         if (rc)
2136                 return rc;
2137
2138         ixgbe_restart_an_internal_phy_x550em(hw);
2139
2140         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
2141 }
2142
2143 /**
2144  * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
2145  * @hw: pointer to hardware structure
2146  *
2147  * Enable flow control according to IEEE clause 37.
2148  */
2149 static void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
2150 {
2151         u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
2152         ixgbe_link_speed speed;
2153         s32 status = -EIO;
2154         bool link_up;
2155
2156         /* AN should have completed when the cable was plugged in.
2157          * Look for reasons to bail out.  Bail out if:
2158          * - FC autoneg is disabled, or if
2159          * - link is not up.
2160          */
2161         if (hw->fc.disable_fc_autoneg)
2162                 goto out;
2163
2164         hw->mac.ops.check_link(hw, &speed, &link_up, false);
2165         if (!link_up)
2166                 goto out;
2167
2168         /* Check if auto-negotiation has completed */
2169         status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info);
2170         if (status || !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) {
2171                 status = -EIO;
2172                 goto out;
2173         }
2174
2175         /* Negotiate the flow control */
2176         status = ixgbe_negotiate_fc(hw, info[0], info[0],
2177                                     FW_PHY_ACT_GET_LINK_INFO_FC_RX,
2178                                     FW_PHY_ACT_GET_LINK_INFO_FC_TX,
2179                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX,
2180                                     FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX);
2181
2182 out:
2183         if (!status) {
2184                 hw->fc.fc_was_autonegged = true;
2185         } else {
2186                 hw->fc.fc_was_autonegged = false;
2187                 hw->fc.current_mode = hw->fc.requested_mode;
2188         }
2189 }
2190
2191 /** ixgbe_init_mac_link_ops_X550em_a - Init mac link function pointers
2192  *  @hw: pointer to hardware structure
2193  **/
2194 static void ixgbe_init_mac_link_ops_X550em_a(struct ixgbe_hw *hw)
2195 {
2196         struct ixgbe_mac_info *mac = &hw->mac;
2197
2198         switch (mac->ops.get_media_type(hw)) {
2199         case ixgbe_media_type_fiber:
2200                 mac->ops.setup_fc = NULL;
2201                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
2202                 break;
2203         case ixgbe_media_type_copper:
2204                 if (hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T &&
2205                     hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T_L) {
2206                         mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
2207                         break;
2208                 }
2209                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
2210                 mac->ops.setup_fc = ixgbe_fc_autoneg_fw;
2211                 mac->ops.setup_link = ixgbe_setup_sgmii_fw;
2212                 mac->ops.check_link = ixgbe_check_mac_link_generic;
2213                 break;
2214         case ixgbe_media_type_backplane:
2215                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
2216                 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
2217                 break;
2218         default:
2219                 break;
2220         }
2221 }
2222
2223 /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers
2224  *  @hw: pointer to hardware structure
2225  **/
2226 static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
2227 {
2228         struct ixgbe_mac_info *mac = &hw->mac;
2229
2230         mac->ops.setup_fc = ixgbe_setup_fc_x550em;
2231
2232         switch (mac->ops.get_media_type(hw)) {
2233         case ixgbe_media_type_fiber:
2234                 /* CS4227 does not support autoneg, so disable the laser control
2235                  * functions for SFP+ fiber
2236                  */
2237                 mac->ops.disable_tx_laser = NULL;
2238                 mac->ops.enable_tx_laser = NULL;
2239                 mac->ops.flap_tx_laser = NULL;
2240                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
2241                 switch (hw->device_id) {
2242                 case IXGBE_DEV_ID_X550EM_A_SFP_N:
2243                         mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_n;
2244                         break;
2245                 case IXGBE_DEV_ID_X550EM_A_SFP:
2246                         mac->ops.setup_mac_link =
2247                                                 ixgbe_setup_mac_link_sfp_x550a;
2248                         break;
2249                 default:
2250                         mac->ops.setup_mac_link =
2251                                                 ixgbe_setup_mac_link_sfp_x550em;
2252                         break;
2253                 }
2254                 mac->ops.set_rate_select_speed =
2255                                         ixgbe_set_soft_rate_select_speed;
2256                 break;
2257         case ixgbe_media_type_copper:
2258                 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T)
2259                         break;
2260                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
2261                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
2262                 mac->ops.check_link = ixgbe_check_link_t_X550em;
2263                 break;
2264         case ixgbe_media_type_backplane:
2265                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
2266                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
2267                         mac->ops.setup_link = ixgbe_setup_sgmii;
2268                 break;
2269         default:
2270                 break;
2271         }
2272
2273         /* Additional modification for X550em_a devices */
2274         if (hw->mac.type == ixgbe_mac_x550em_a)
2275                 ixgbe_init_mac_link_ops_X550em_a(hw);
2276 }
2277
2278 /** ixgbe_setup_sfp_modules_X550em - Setup SFP module
2279  * @hw: pointer to hardware structure
2280  */
2281 static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
2282 {
2283         s32 status;
2284         bool linear;
2285
2286         /* Check if SFP module is supported */
2287         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
2288         if (status)
2289                 return status;
2290
2291         ixgbe_init_mac_link_ops_X550em(hw);
2292         hw->phy.ops.reset = NULL;
2293
2294         return 0;
2295 }
2296
2297 /** ixgbe_get_link_capabilities_x550em - Determines link capabilities
2298  * @hw: pointer to hardware structure
2299  * @speed: pointer to link speed
2300  * @autoneg: true when autoneg or autotry is enabled
2301  **/
2302 static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
2303                                               ixgbe_link_speed *speed,
2304                                               bool *autoneg)
2305 {
2306         if (hw->phy.type == ixgbe_phy_fw) {
2307                 *autoneg = true;
2308                 *speed = hw->phy.speeds_supported;
2309                 return 0;
2310         }
2311
2312         /* SFP */
2313         if (hw->phy.media_type == ixgbe_media_type_fiber) {
2314                 /* CS4227 SFP must not enable auto-negotiation */
2315                 *autoneg = false;
2316
2317                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
2318                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 ||
2319                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
2320                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
2321                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
2322                         return 0;
2323                 }
2324
2325                 /* Link capabilities are based on SFP */
2326                 if (hw->phy.multispeed_fiber)
2327                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
2328                                  IXGBE_LINK_SPEED_1GB_FULL;
2329                 else
2330                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
2331         } else {
2332                 switch (hw->phy.type) {
2333                 case ixgbe_phy_x550em_kx4:
2334                         *speed = IXGBE_LINK_SPEED_1GB_FULL |
2335                                  IXGBE_LINK_SPEED_2_5GB_FULL |
2336                                  IXGBE_LINK_SPEED_10GB_FULL;
2337                         break;
2338                 case ixgbe_phy_x550em_xfi:
2339                         *speed = IXGBE_LINK_SPEED_1GB_FULL |
2340                                  IXGBE_LINK_SPEED_10GB_FULL;
2341                         break;
2342                 case ixgbe_phy_ext_1g_t:
2343                 case ixgbe_phy_sgmii:
2344                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
2345                         break;
2346                 case ixgbe_phy_x550em_kr:
2347                         if (hw->mac.type == ixgbe_mac_x550em_a) {
2348                                 /* check different backplane modes */
2349                                 if (hw->phy.nw_mng_if_sel &
2350                                     IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
2351                                         *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
2352                                         break;
2353                                 } else if (hw->device_id ==
2354                                            IXGBE_DEV_ID_X550EM_A_KR_L) {
2355                                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
2356                                         break;
2357                                 }
2358                         }
2359                         fallthrough;
2360                 default:
2361                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
2362                                  IXGBE_LINK_SPEED_1GB_FULL;
2363                         break;
2364                 }
2365                 *autoneg = true;
2366         }
2367         return 0;
2368 }
2369
2370 /**
2371  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
2372  * @hw: pointer to hardware structure
2373  * @lsc: pointer to boolean flag which indicates whether external Base T
2374  *       PHY interrupt is lsc
2375  * @is_overtemp: indicate whether an overtemp event encountered
2376  *
2377  * Determime if external Base T PHY interrupt cause is high temperature
2378  * failure alarm or link status change.
2379  **/
2380 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc,
2381                                        bool *is_overtemp)
2382 {
2383         u32 status;
2384         u16 reg;
2385
2386         *is_overtemp = false;
2387         *lsc = false;
2388
2389         /* Vendor alarm triggered */
2390         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2391                                       MDIO_MMD_VEND1,
2392                                       &reg);
2393
2394         if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
2395                 return status;
2396
2397         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
2398         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
2399                                       MDIO_MMD_VEND1,
2400                                       &reg);
2401
2402         if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2403                                 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
2404                 return status;
2405
2406         /* Global alarm triggered */
2407         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
2408                                       MDIO_MMD_VEND1,
2409                                       &reg);
2410
2411         if (status)
2412                 return status;
2413
2414         /* If high temperature failure, then return over temp error and exit */
2415         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
2416                 /* power down the PHY in case the PHY FW didn't already */
2417                 ixgbe_set_copper_phy_power(hw, false);
2418                 *is_overtemp = true;
2419                 return -EIO;
2420         }
2421         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
2422                 /*  device fault alarm triggered */
2423                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
2424                                           MDIO_MMD_VEND1,
2425                                           &reg);
2426                 if (status)
2427                         return status;
2428
2429                 /* if device fault was due to high temp alarm handle and exit */
2430                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
2431                         /* power down the PHY in case the PHY FW didn't */
2432                         ixgbe_set_copper_phy_power(hw, false);
2433                         *is_overtemp = true;
2434                         return -EIO;
2435                 }
2436         }
2437
2438         /* Vendor alarm 2 triggered */
2439         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2440                                       MDIO_MMD_AN, &reg);
2441
2442         if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
2443                 return status;
2444
2445         /* link connect/disconnect event occurred */
2446         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
2447                                       MDIO_MMD_AN, &reg);
2448
2449         if (status)
2450                 return status;
2451
2452         /* Indicate LSC */
2453         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2454                 *lsc = true;
2455
2456         return 0;
2457 }
2458
2459 /**
2460  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2461  * @hw: pointer to hardware structure
2462  *
2463  * Enable link status change and temperature failure alarm for the external
2464  * Base T PHY
2465  *
2466  * Returns PHY access status
2467  **/
2468 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2469 {
2470         bool lsc, overtemp;
2471         u32 status;
2472         u16 reg;
2473
2474         /* Clear interrupt flags */
2475         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc, &overtemp);
2476
2477         /* Enable link status change alarm */
2478
2479         /* Enable the LASI interrupts on X552 devices to receive notifications
2480          * of the link configurations of the external PHY and correspondingly
2481          * support the configuration of the internal iXFI link, since iXFI does
2482          * not support auto-negotiation. This is not required for X553 devices
2483          * having KR support, which performs auto-negotiations and which is used
2484          * as the internal link to the external PHY. Hence adding a check here
2485          * to avoid enabling LASI interrupts for X553 devices.
2486          */
2487         if (hw->mac.type != ixgbe_mac_x550em_a) {
2488                 status = hw->phy.ops.read_reg(hw,
2489                                             IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2490                                             MDIO_MMD_AN, &reg);
2491                 if (status)
2492                         return status;
2493
2494                 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2495
2496                 status = hw->phy.ops.write_reg(hw,
2497                                             IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2498                                             MDIO_MMD_AN, reg);
2499                 if (status)
2500                         return status;
2501         }
2502
2503         /* Enable high temperature failure and global fault alarms */
2504         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2505                                       MDIO_MMD_VEND1,
2506                                       &reg);
2507         if (status)
2508                 return status;
2509
2510         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2511                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2512
2513         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2514                                        MDIO_MMD_VEND1,
2515                                        reg);
2516         if (status)
2517                 return status;
2518
2519         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2520         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2521                                       MDIO_MMD_VEND1,
2522                                       &reg);
2523         if (status)
2524                 return status;
2525
2526         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2527                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2528
2529         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2530                                        MDIO_MMD_VEND1,
2531                                        reg);
2532         if (status)
2533                 return status;
2534
2535         /* Enable chip-wide vendor alarm */
2536         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2537                                       MDIO_MMD_VEND1,
2538                                       &reg);
2539         if (status)
2540                 return status;
2541
2542         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2543
2544         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2545                                        MDIO_MMD_VEND1,
2546                                        reg);
2547
2548         return status;
2549 }
2550
2551 /**
2552  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2553  * @hw: pointer to hardware structure
2554  * @is_overtemp: indicate whether an overtemp event encountered
2555  *
2556  * Handle external Base T PHY interrupt. If high temperature
2557  * failure alarm then return error, else if link status change
2558  * then setup internal/external PHY link
2559  **/
2560 static s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw,
2561                                           bool *is_overtemp)
2562 {
2563         struct ixgbe_phy_info *phy = &hw->phy;
2564         bool lsc;
2565         u32 status;
2566
2567         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc, is_overtemp);
2568         if (status)
2569                 return status;
2570
2571         if (lsc && phy->ops.setup_internal_link)
2572                 return phy->ops.setup_internal_link(hw);
2573
2574         return 0;
2575 }
2576
2577 /**
2578  * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2579  * @hw: pointer to hardware structure
2580  * @speed: link speed
2581  *
2582  * Configures the integrated KR PHY.
2583  **/
2584 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2585                                        ixgbe_link_speed speed)
2586 {
2587         s32 status;
2588         u32 reg_val;
2589
2590         status = hw->mac.ops.read_iosf_sb_reg(hw,
2591                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2592                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2593         if (status)
2594                 return status;
2595
2596         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2597         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2598                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2599
2600         /* Advertise 10G support. */
2601         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2602                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2603
2604         /* Advertise 1G support. */
2605         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2606                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2607
2608         status = hw->mac.ops.write_iosf_sb_reg(hw,
2609                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2610                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2611
2612         if (hw->mac.type == ixgbe_mac_x550em_a) {
2613                 /* Set lane mode  to KR auto negotiation */
2614                 status = hw->mac.ops.read_iosf_sb_reg(hw,
2615                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2616                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2617
2618                 if (status)
2619                         return status;
2620
2621                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2622                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2623                 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2624                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2625                 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2626
2627                 status = hw->mac.ops.write_iosf_sb_reg(hw,
2628                                 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2629                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2630         }
2631
2632         return ixgbe_restart_an_internal_phy_x550em(hw);
2633 }
2634
2635 /**
2636  * ixgbe_setup_kr_x550em - Configure the KR PHY
2637  * @hw: pointer to hardware structure
2638  **/
2639 static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2640 {
2641         /* leave link alone for 2.5G */
2642         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)
2643                 return 0;
2644
2645         if (ixgbe_check_reset_blocked(hw))
2646                 return 0;
2647
2648         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2649 }
2650
2651 /** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2652  *  @hw: address of hardware structure
2653  *  @link_up: address of boolean to indicate link status
2654  *
2655  *  Returns error code if unable to get link status.
2656  **/
2657 static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2658 {
2659         u32 ret;
2660         u16 autoneg_status;
2661
2662         *link_up = false;
2663
2664         /* read this twice back to back to indicate current status */
2665         ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
2666                                    &autoneg_status);
2667         if (ret)
2668                 return ret;
2669
2670         ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
2671                                    &autoneg_status);
2672         if (ret)
2673                 return ret;
2674
2675         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2676
2677         return 0;
2678 }
2679
2680 /** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2681  *  @hw: point to hardware structure
2682  *
2683  *  Configures the link between the integrated KR PHY and the external X557 PHY
2684  *  The driver will call this function when it gets a link status change
2685  *  interrupt from the X557 PHY. This function configures the link speed
2686  *  between the PHYs to match the link speed of the BASE-T link.
2687  *
2688  * A return of a non-zero value indicates an error, and the base driver should
2689  * not report link up.
2690  **/
2691 static s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2692 {
2693         ixgbe_link_speed force_speed;
2694         bool link_up;
2695         u32 status;
2696         u16 speed;
2697
2698         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2699                 return -EIO;
2700
2701         if (!(hw->mac.type == ixgbe_mac_X550EM_x &&
2702               !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE))) {
2703                 speed = IXGBE_LINK_SPEED_10GB_FULL |
2704                         IXGBE_LINK_SPEED_1GB_FULL;
2705                 return ixgbe_setup_kr_speed_x550em(hw, speed);
2706         }
2707
2708         /* If link is not up, then there is no setup necessary so return  */
2709         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2710         if (status)
2711                 return status;
2712
2713         if (!link_up)
2714                 return 0;
2715
2716         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2717                                       MDIO_MMD_AN,
2718                                       &speed);
2719         if (status)
2720                 return status;
2721
2722         /* If link is not still up, then no setup is necessary so return */
2723         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2724         if (status)
2725                 return status;
2726
2727         if (!link_up)
2728                 return 0;
2729
2730         /* clear everything but the speed and duplex bits */
2731         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2732
2733         switch (speed) {
2734         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2735                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2736                 break;
2737         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2738                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2739                 break;
2740         default:
2741                 /* Internal PHY does not support anything else */
2742                 return -EINVAL;
2743         }
2744
2745         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2746 }
2747
2748 /** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
2749  *  @hw: pointer to hardware structure
2750  **/
2751 static s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
2752 {
2753         s32 status;
2754
2755         status = ixgbe_reset_phy_generic(hw);
2756
2757         if (status)
2758                 return status;
2759
2760         /* Configure Link Status Alarm and Temperature Threshold interrupts */
2761         return ixgbe_enable_lasi_ext_t_x550em(hw);
2762 }
2763
2764 /**
2765  *  ixgbe_led_on_t_x550em - Turns on the software controllable LEDs.
2766  *  @hw: pointer to hardware structure
2767  *  @led_idx: led number to turn on
2768  **/
2769 static s32 ixgbe_led_on_t_x550em(struct ixgbe_hw *hw, u32 led_idx)
2770 {
2771         u16 phy_data;
2772
2773         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
2774                 return -EINVAL;
2775
2776         /* To turn on the LED, set mode to ON. */
2777         hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2778                              MDIO_MMD_VEND1, &phy_data);
2779         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
2780         hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2781                               MDIO_MMD_VEND1, phy_data);
2782
2783         return 0;
2784 }
2785
2786 /**
2787  *  ixgbe_led_off_t_x550em - Turns off the software controllable LEDs.
2788  *  @hw: pointer to hardware structure
2789  *  @led_idx: led number to turn off
2790  **/
2791 static s32 ixgbe_led_off_t_x550em(struct ixgbe_hw *hw, u32 led_idx)
2792 {
2793         u16 phy_data;
2794
2795         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
2796                 return -EINVAL;
2797
2798         /* To turn on the LED, set mode to ON. */
2799         hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2800                              MDIO_MMD_VEND1, &phy_data);
2801         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
2802         hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2803                               MDIO_MMD_VEND1, phy_data);
2804
2805         return 0;
2806 }
2807
2808 /**
2809  *  ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
2810  *  @hw: pointer to the HW structure
2811  *  @maj: driver version major number
2812  *  @min: driver version minor number
2813  *  @build: driver version build number
2814  *  @sub: driver version sub build number
2815  *  @len: length of driver_ver string
2816  *  @driver_ver: driver string
2817  *
2818  *  Sends driver version number to firmware through the manageability
2819  *  block.  On success return 0
2820  *  else returns -EBUSY when encountering an error acquiring
2821  *  semaphore, -EIO when command fails or -ENIVAL when incorrect
2822  *  params passed.
2823  **/
2824 static s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
2825                                      u8 build, u8 sub, u16 len,
2826                                      const char *driver_ver)
2827 {
2828         struct ixgbe_hic_drv_info2 fw_cmd;
2829         s32 ret_val;
2830         int i;
2831
2832         if (!len || !driver_ver || (len > sizeof(fw_cmd.driver_string)))
2833                 return -EINVAL;
2834
2835         fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
2836         fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
2837         fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
2838         fw_cmd.port_num = (u8)hw->bus.func;
2839         fw_cmd.ver_maj = maj;
2840         fw_cmd.ver_min = min;
2841         fw_cmd.ver_build = build;
2842         fw_cmd.ver_sub = sub;
2843         fw_cmd.hdr.checksum = 0;
2844         memcpy(fw_cmd.driver_string, driver_ver, len);
2845         fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
2846                               (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
2847
2848         for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
2849                 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2850                                                        sizeof(fw_cmd),
2851                                                        IXGBE_HI_COMMAND_TIMEOUT,
2852                                                        true);
2853                 if (ret_val)
2854                         continue;
2855
2856                 if (fw_cmd.hdr.cmd_or_resp.ret_status !=
2857                     FW_CEM_RESP_STATUS_SUCCESS)
2858                         return -EIO;
2859                 return 0;
2860         }
2861
2862         return ret_val;
2863 }
2864
2865 /** ixgbe_get_lcd_x550em - Determine lowest common denominator
2866  *  @hw: pointer to hardware structure
2867  *  @lcd_speed: pointer to lowest common link speed
2868  *
2869  *  Determine lowest common link speed with link partner.
2870  **/
2871 static s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw,
2872                                   ixgbe_link_speed *lcd_speed)
2873 {
2874         u16 an_lp_status;
2875         s32 status;
2876         u16 word = hw->eeprom.ctrl_word_3;
2877
2878         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2879
2880         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2881                                       MDIO_MMD_AN,
2882                                       &an_lp_status);
2883         if (status)
2884                 return status;
2885
2886         /* If link partner advertised 1G, return 1G */
2887         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2888                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2889                 return status;
2890         }
2891
2892         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2893         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2894             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2895                 return status;
2896
2897         /* Link partner not capable of lower speeds, return 10G */
2898         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2899         return status;
2900 }
2901
2902 /**
2903  * ixgbe_setup_fc_x550em - Set up flow control
2904  * @hw: pointer to hardware structure
2905  */
2906 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *hw)
2907 {
2908         bool pause, asm_dir;
2909         u32 reg_val;
2910         s32 rc = 0;
2911
2912         /* Validate the requested mode */
2913         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2914                 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2915                 return -EINVAL;
2916         }
2917
2918         /* 10gig parts do not have a word in the EEPROM to determine the
2919          * default flow control setting, so we explicitly set it to full.
2920          */
2921         if (hw->fc.requested_mode == ixgbe_fc_default)
2922                 hw->fc.requested_mode = ixgbe_fc_full;
2923
2924         /* Determine PAUSE and ASM_DIR bits. */
2925         switch (hw->fc.requested_mode) {
2926         case ixgbe_fc_none:
2927                 pause = false;
2928                 asm_dir = false;
2929                 break;
2930         case ixgbe_fc_tx_pause:
2931                 pause = false;
2932                 asm_dir = true;
2933                 break;
2934         case ixgbe_fc_rx_pause:
2935                 /* Rx Flow control is enabled and Tx Flow control is
2936                  * disabled by software override. Since there really
2937                  * isn't a way to advertise that we are capable of RX
2938                  * Pause ONLY, we will advertise that we support both
2939                  * symmetric and asymmetric Rx PAUSE, as such we fall
2940                  * through to the fc_full statement.  Later, we will
2941                  * disable the adapter's ability to send PAUSE frames.
2942                  */
2943                 fallthrough;
2944         case ixgbe_fc_full:
2945                 pause = true;
2946                 asm_dir = true;
2947                 break;
2948         default:
2949                 hw_err(hw, "Flow control param set incorrectly\n");
2950                 return -EIO;
2951         }
2952
2953         switch (hw->device_id) {
2954         case IXGBE_DEV_ID_X550EM_X_KR:
2955         case IXGBE_DEV_ID_X550EM_A_KR:
2956         case IXGBE_DEV_ID_X550EM_A_KR_L:
2957                 rc = hw->mac.ops.read_iosf_sb_reg(hw,
2958                                             IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2959                                             IXGBE_SB_IOSF_TARGET_KR_PHY,
2960                                             &reg_val);
2961                 if (rc)
2962                         return rc;
2963
2964                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2965                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2966                 if (pause)
2967                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2968                 if (asm_dir)
2969                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2970                 rc = hw->mac.ops.write_iosf_sb_reg(hw,
2971                                             IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2972                                             IXGBE_SB_IOSF_TARGET_KR_PHY,
2973                                             reg_val);
2974
2975                 /* This device does not fully support AN. */
2976                 hw->fc.disable_fc_autoneg = true;
2977                 break;
2978         case IXGBE_DEV_ID_X550EM_X_XFI:
2979                 hw->fc.disable_fc_autoneg = true;
2980                 break;
2981         default:
2982                 break;
2983         }
2984         return rc;
2985 }
2986
2987 /**
2988  *  ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
2989  *  @hw: pointer to hardware structure
2990  **/
2991 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
2992 {
2993         u32 link_s1, lp_an_page_low, an_cntl_1;
2994         ixgbe_link_speed speed;
2995         s32 status = -EIO;
2996         bool link_up;
2997
2998         /* AN should have completed when the cable was plugged in.
2999          * Look for reasons to bail out.  Bail out if:
3000          * - FC autoneg is disabled, or if
3001          * - link is not up.
3002          */
3003         if (hw->fc.disable_fc_autoneg) {
3004                 hw_err(hw, "Flow control autoneg is disabled");
3005                 goto out;
3006         }
3007
3008         hw->mac.ops.check_link(hw, &speed, &link_up, false);
3009         if (!link_up) {
3010                 hw_err(hw, "The link is down");
3011                 goto out;
3012         }
3013
3014         /* Check at auto-negotiation has completed */
3015         status = hw->mac.ops.read_iosf_sb_reg(hw,
3016                                         IXGBE_KRM_LINK_S1(hw->bus.lan_id),
3017                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
3018
3019         if (status || (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
3020                 hw_dbg(hw, "Auto-Negotiation did not complete\n");
3021                 status = -EIO;
3022                 goto out;
3023         }
3024
3025         /* Read the 10g AN autoc and LP ability registers and resolve
3026          * local flow control settings accordingly
3027          */
3028         status = hw->mac.ops.read_iosf_sb_reg(hw,
3029                                 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3030                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
3031
3032         if (status) {
3033                 hw_dbg(hw, "Auto-Negotiation did not complete\n");
3034                 goto out;
3035         }
3036
3037         status = hw->mac.ops.read_iosf_sb_reg(hw,
3038                                 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
3039                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
3040
3041         if (status) {
3042                 hw_dbg(hw, "Auto-Negotiation did not complete\n");
3043                 goto out;
3044         }
3045
3046         status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
3047                                     IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
3048                                     IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
3049                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
3050                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
3051
3052 out:
3053         if (!status) {
3054                 hw->fc.fc_was_autonegged = true;
3055         } else {
3056                 hw->fc.fc_was_autonegged = false;
3057                 hw->fc.current_mode = hw->fc.requested_mode;
3058         }
3059 }
3060
3061 /**
3062  *  ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
3063  *  @hw: pointer to hardware structure
3064  **/
3065 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
3066 {
3067         hw->fc.fc_was_autonegged = false;
3068         hw->fc.current_mode = hw->fc.requested_mode;
3069 }
3070
3071 /** ixgbe_enter_lplu_x550em - Transition to low power states
3072  *  @hw: pointer to hardware structure
3073  *
3074  *  Configures Low Power Link Up on transition to low power states
3075  *  (from D0 to non-D0). Link is required to enter LPLU so avoid resetting
3076  *  the X557 PHY immediately prior to entering LPLU.
3077  **/
3078 static s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3079 {
3080         u16 an_10g_cntl_reg, autoneg_reg, speed;
3081         s32 status;
3082         ixgbe_link_speed lcd_speed;
3083         u32 save_autoneg;
3084         bool link_up;
3085
3086         /* If blocked by MNG FW, then don't restart AN */
3087         if (ixgbe_check_reset_blocked(hw))
3088                 return 0;
3089
3090         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3091         if (status)
3092                 return status;
3093
3094         status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3,
3095                                      &hw->eeprom.ctrl_word_3);
3096         if (status)
3097                 return status;
3098
3099         /* If link is down, LPLU disabled in NVM, WoL disabled, or
3100          * manageability disabled, then force link down by entering
3101          * low power mode.
3102          */
3103         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3104             !(hw->wol_enabled || ixgbe_mng_present(hw)))
3105                 return ixgbe_set_copper_phy_power(hw, false);
3106
3107         /* Determine LCD */
3108         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3109         if (status)
3110                 return status;
3111
3112         /* If no valid LCD link speed, then force link down and exit. */
3113         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3114                 return ixgbe_set_copper_phy_power(hw, false);
3115
3116         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3117                                       MDIO_MMD_AN,
3118                                       &speed);
3119         if (status)
3120                 return status;
3121
3122         /* If no link now, speed is invalid so take link down */
3123         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3124         if (status)
3125                 return ixgbe_set_copper_phy_power(hw, false);
3126
3127         /* clear everything but the speed bits */
3128         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3129
3130         /* If current speed is already LCD, then exit. */
3131         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3132              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3133             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3134              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3135                 return status;
3136
3137         /* Clear AN completed indication */
3138         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3139                                       MDIO_MMD_AN,
3140                                       &autoneg_reg);
3141         if (status)
3142                 return status;
3143
3144         status = hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
3145                                       MDIO_MMD_AN,
3146                                       &an_10g_cntl_reg);
3147         if (status)
3148                 return status;
3149
3150         status = hw->phy.ops.read_reg(hw,
3151                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3152                                       MDIO_MMD_AN,
3153                                       &autoneg_reg);
3154         if (status)
3155                 return status;
3156
3157         save_autoneg = hw->phy.autoneg_advertised;
3158
3159         /* Setup link at least common link speed */
3160         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3161
3162         /* restore autoneg from before setting lplu speed */
3163         hw->phy.autoneg_advertised = save_autoneg;
3164
3165         return status;
3166 }
3167
3168 /**
3169  * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs
3170  * @hw: pointer to hardware structure
3171  */
3172 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw)
3173 {
3174         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
3175         s32 rc;
3176
3177         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
3178                 return 0;
3179
3180         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store);
3181         if (rc)
3182                 return rc;
3183         memset(store, 0, sizeof(store));
3184
3185         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store);
3186         if (rc)
3187                 return rc;
3188
3189         return ixgbe_setup_fw_link(hw);
3190 }
3191
3192 /**
3193  * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp
3194  * @hw: pointer to hardware structure
3195  *
3196  * Return true when an overtemp event detected, otherwise false.
3197  */
3198 static bool ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)
3199 {
3200         u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
3201         s32 rc;
3202
3203         rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store);
3204         if (rc)
3205                 return false;
3206
3207         if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) {
3208                 ixgbe_shutdown_fw_phy(hw);
3209                 return true;
3210         }
3211         return false;
3212 }
3213
3214 /**
3215  * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
3216  * @hw: pointer to hardware structure
3217  *
3218  * Read NW_MNG_IF_SEL register and save field values.
3219  */
3220 static void ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
3221 {
3222         /* Save NW management interface connected on board. This is used
3223          * to determine internal PHY mode.
3224          */
3225         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
3226
3227         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
3228          * PHY address. This register field was has only been used for X552.
3229          */
3230         if (hw->mac.type == ixgbe_mac_x550em_a &&
3231             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
3232                 hw->phy.mdio.prtad = (hw->phy.nw_mng_if_sel &
3233                                       IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
3234                                      IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
3235         }
3236 }
3237
3238 /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init
3239  *  @hw: pointer to hardware structure
3240  *
3241  *  Initialize any function pointers that were not able to be
3242  *  set during init_shared_code because the PHY/SFP type was
3243  *  not known.  Perform the SFP init if necessary.
3244  **/
3245 static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
3246 {
3247         struct ixgbe_phy_info *phy = &hw->phy;
3248         s32 ret_val;
3249
3250         hw->mac.ops.set_lan_id(hw);
3251
3252         ixgbe_read_mng_if_sel_x550em(hw);
3253
3254         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
3255                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
3256                 ixgbe_setup_mux_ctl(hw);
3257         }
3258
3259         /* Identify the PHY or SFP module */
3260         ret_val = phy->ops.identify(hw);
3261         if (ret_val == -EOPNOTSUPP || ret_val == -EFAULT)
3262                 return ret_val;
3263
3264         /* Setup function pointers based on detected hardware */
3265         ixgbe_init_mac_link_ops_X550em(hw);
3266         if (phy->sfp_type != ixgbe_sfp_type_unknown)
3267                 phy->ops.reset = NULL;
3268
3269         /* Set functions pointers based on phy type */
3270         switch (hw->phy.type) {
3271         case ixgbe_phy_x550em_kx4:
3272                 phy->ops.setup_link = NULL;
3273                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
3274                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
3275                 break;
3276         case ixgbe_phy_x550em_kr:
3277                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
3278                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
3279                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
3280                 break;
3281         case ixgbe_phy_x550em_xfi:
3282                 /* link is managed by HW */
3283                 phy->ops.setup_link = NULL;
3284                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
3285                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
3286                 break;
3287         case ixgbe_phy_x550em_ext_t:
3288                 /* Save NW management interface connected on board. This is used
3289                  * to determine internal PHY mode
3290                  */
3291                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
3292
3293                 /* If internal link mode is XFI, then setup iXFI internal link,
3294                  * else setup KR now.
3295                  */
3296                 phy->ops.setup_internal_link =
3297                                               ixgbe_setup_internal_phy_t_x550em;
3298
3299                 /* setup SW LPLU only for first revision */
3300                 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3301                     !(IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)) &
3302                       IXGBE_FUSES0_REV_MASK))
3303                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
3304
3305                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
3306                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
3307                 break;
3308         case ixgbe_phy_sgmii:
3309                 phy->ops.setup_link = NULL;
3310                 break;
3311         case ixgbe_phy_fw:
3312                 phy->ops.setup_link = ixgbe_setup_fw_link;
3313                 phy->ops.reset = ixgbe_reset_phy_fw;
3314                 break;
3315         case ixgbe_phy_ext_1g_t:
3316                 phy->ops.setup_link = NULL;
3317                 phy->ops.read_reg = NULL;
3318                 phy->ops.write_reg = NULL;
3319                 phy->ops.reset = NULL;
3320                 break;
3321         default:
3322                 break;
3323         }
3324
3325         return ret_val;
3326 }
3327
3328 /** ixgbe_get_media_type_X550em - Get media type
3329  *  @hw: pointer to hardware structure
3330  *
3331  *  Returns the media type (fiber, copper, backplane)
3332  *
3333  */
3334 static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
3335 {
3336         enum ixgbe_media_type media_type;
3337
3338         /* Detect if there is a copper PHY attached. */
3339         switch (hw->device_id) {
3340         case IXGBE_DEV_ID_X550EM_A_SGMII:
3341         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
3342                 hw->phy.type = ixgbe_phy_sgmii;
3343                 fallthrough;
3344         case IXGBE_DEV_ID_X550EM_X_KR:
3345         case IXGBE_DEV_ID_X550EM_X_KX4:
3346         case IXGBE_DEV_ID_X550EM_X_XFI:
3347         case IXGBE_DEV_ID_X550EM_A_KR:
3348         case IXGBE_DEV_ID_X550EM_A_KR_L:
3349                 media_type = ixgbe_media_type_backplane;
3350                 break;
3351         case IXGBE_DEV_ID_X550EM_X_SFP:
3352         case IXGBE_DEV_ID_X550EM_A_SFP:
3353         case IXGBE_DEV_ID_X550EM_A_SFP_N:
3354                 media_type = ixgbe_media_type_fiber;
3355                 break;
3356         case IXGBE_DEV_ID_X550EM_X_1G_T:
3357         case IXGBE_DEV_ID_X550EM_X_10G_T:
3358         case IXGBE_DEV_ID_X550EM_A_10G_T:
3359         case IXGBE_DEV_ID_X550EM_A_1G_T:
3360         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
3361                 media_type = ixgbe_media_type_copper;
3362                 break;
3363         default:
3364                 media_type = ixgbe_media_type_unknown;
3365                 break;
3366         }
3367         return media_type;
3368 }
3369
3370 /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
3371  ** @hw: pointer to hardware structure
3372  **/
3373 static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
3374 {
3375         s32 status;
3376         u16 reg;
3377
3378         status = hw->phy.ops.read_reg(hw,
3379                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
3380                                       MDIO_MMD_PMAPMD,
3381                                       &reg);
3382         if (status)
3383                 return status;
3384
3385         /* If PHY FW reset completed bit is set then this is the first
3386          * SW instance after a power on so the PHY FW must be un-stalled.
3387          */
3388         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
3389                 status = hw->phy.ops.read_reg(hw,
3390                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
3391                                         MDIO_MMD_VEND1,
3392                                         &reg);
3393                 if (status)
3394                         return status;
3395
3396                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
3397
3398                 status = hw->phy.ops.write_reg(hw,
3399                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
3400                                         MDIO_MMD_VEND1,
3401                                         reg);
3402                 if (status)
3403                         return status;
3404         }
3405
3406         return status;
3407 }
3408
3409 /**
3410  * ixgbe_set_mdio_speed - Set MDIO clock speed
3411  * @hw: pointer to hardware structure
3412  */
3413 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
3414 {
3415         u32 hlreg0;
3416
3417         switch (hw->device_id) {
3418         case IXGBE_DEV_ID_X550EM_X_10G_T:
3419         case IXGBE_DEV_ID_X550EM_A_SGMII:
3420         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
3421         case IXGBE_DEV_ID_X550EM_A_10G_T:
3422         case IXGBE_DEV_ID_X550EM_A_SFP:
3423                 /* Config MDIO clock speed before the first MDIO PHY access */
3424                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3425                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
3426                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3427                 break;
3428         case IXGBE_DEV_ID_X550EM_A_1G_T:
3429         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
3430                 /* Select fast MDIO clock speed for these devices */
3431                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3432                 hlreg0 |= IXGBE_HLREG0_MDCSPD;
3433                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3434                 break;
3435         default:
3436                 break;
3437         }
3438 }
3439
3440 /**  ixgbe_reset_hw_X550em - Perform hardware reset
3441  **  @hw: pointer to hardware structure
3442  **
3443  **  Resets the hardware by resetting the transmit and receive units, masks
3444  **  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
3445  **  reset.
3446  **/
3447 static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
3448 {
3449         ixgbe_link_speed link_speed;
3450         s32 status;
3451         u32 ctrl = 0;
3452         u32 i;
3453         bool link_up = false;
3454         u32 swfw_mask = hw->phy.phy_semaphore_mask;
3455
3456         /* Call adapter stop to disable Tx/Rx and clear interrupts */
3457         status = hw->mac.ops.stop_adapter(hw);
3458         if (status)
3459                 return status;
3460
3461         /* flush pending Tx transactions */
3462         ixgbe_clear_tx_pending(hw);
3463
3464         /* set MDIO speed before talking to the PHY in case it's the 1st time */
3465         ixgbe_set_mdio_speed(hw);
3466
3467         /* PHY ops must be identified and initialized prior to reset */
3468         status = hw->phy.ops.init(hw);
3469         if (status == -EOPNOTSUPP || status == -EFAULT)
3470                 return status;
3471
3472         /* start the external PHY */
3473         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
3474                 status = ixgbe_init_ext_t_x550em(hw);
3475                 if (status)
3476                         return status;
3477         }
3478
3479         /* Setup SFP module if there is one present. */
3480         if (hw->phy.sfp_setup_needed) {
3481                 status = hw->mac.ops.setup_sfp(hw);
3482                 hw->phy.sfp_setup_needed = false;
3483         }
3484
3485         if (status == -EOPNOTSUPP)
3486                 return status;
3487
3488         /* Reset PHY */
3489         if (!hw->phy.reset_disable && hw->phy.ops.reset)
3490                 hw->phy.ops.reset(hw);
3491
3492 mac_reset_top:
3493         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
3494          * If link reset is used when link is up, it might reset the PHY when
3495          * mng is using it.  If link is down or the flag to force full link
3496          * reset is set, then perform link reset.
3497          */
3498         ctrl = IXGBE_CTRL_LNK_RST;
3499
3500         if (!hw->force_full_reset) {
3501                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
3502                 if (link_up)
3503                         ctrl = IXGBE_CTRL_RST;
3504         }
3505
3506         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
3507         if (status) {
3508                 hw_dbg(hw, "semaphore failed with %d", status);
3509                 return -EBUSY;
3510         }
3511
3512         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
3513         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
3514         IXGBE_WRITE_FLUSH(hw);
3515         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3516         usleep_range(1000, 1200);
3517
3518         /* Poll for reset bit to self-clear meaning reset is complete */
3519         for (i = 0; i < 10; i++) {
3520                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
3521                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
3522                         break;
3523                 udelay(1);
3524         }
3525
3526         if (ctrl & IXGBE_CTRL_RST_MASK) {
3527                 status = -EIO;
3528                 hw_dbg(hw, "Reset polling failed to complete.\n");
3529         }
3530
3531         msleep(50);
3532
3533         /* Double resets are required for recovery from certain error
3534          * clear the multicast table.  Also reset num_rar_entries to 128,
3535          * since we modify this value when programming the SAN MAC address.
3536          */
3537         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
3538                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3539                 goto mac_reset_top;
3540         }
3541
3542         /* Store the permanent mac address */
3543         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
3544
3545         /* Store MAC address from RAR0, clear receive address registers, and
3546          * clear the multicast table.  Also reset num_rar_entries to 128,
3547          * since we modify this value when programming the SAN MAC address.
3548          */
3549         hw->mac.num_rar_entries = 128;
3550         hw->mac.ops.init_rx_addrs(hw);
3551
3552         ixgbe_set_mdio_speed(hw);
3553
3554         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
3555                 ixgbe_setup_mux_ctl(hw);
3556
3557         return status;
3558 }
3559
3560 /** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype
3561  *      anti-spoofing
3562  *  @hw:  pointer to hardware structure
3563  *  @enable: enable or disable switch for Ethertype anti-spoofing
3564  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
3565  **/
3566 static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
3567                                                    bool enable, int vf)
3568 {
3569         int vf_target_reg = vf >> 3;
3570         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
3571         u32 pfvfspoof;
3572
3573         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3574         if (enable)
3575                 pfvfspoof |= BIT(vf_target_shift);
3576         else
3577                 pfvfspoof &= ~BIT(vf_target_shift);
3578
3579         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3580 }
3581
3582 /** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning
3583  *  @hw: pointer to hardware structure
3584  *  @enable: enable or disable source address pruning
3585  *  @pool: Rx pool to set source address pruning for
3586  **/
3587 static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw,
3588                                                   bool enable,
3589                                                   unsigned int pool)
3590 {
3591         u64 pfflp;
3592
3593         /* max rx pool is 63 */
3594         if (pool > 63)
3595                 return;
3596
3597         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
3598         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
3599
3600         if (enable)
3601                 pfflp |= (1ULL << pool);
3602         else
3603                 pfflp &= ~(1ULL << pool);
3604
3605         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
3606         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
3607 }
3608
3609 /**
3610  *  ixgbe_setup_fc_backplane_x550em_a - Set up flow control
3611  *  @hw: pointer to hardware structure
3612  *
3613  *  Called at init time to set up flow control.
3614  **/
3615 static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
3616 {
3617         s32 status = 0;
3618         u32 an_cntl = 0;
3619
3620         /* Validate the requested mode */
3621         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3622                 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3623                 return -EINVAL;
3624         }
3625
3626         if (hw->fc.requested_mode == ixgbe_fc_default)
3627                 hw->fc.requested_mode = ixgbe_fc_full;
3628
3629         /* Set up the 1G and 10G flow control advertisement registers so the
3630          * HW will be able to do FC autoneg once the cable is plugged in.  If
3631          * we link at 10G, the 1G advertisement is harmless and vice versa.
3632          */
3633         status = hw->mac.ops.read_iosf_sb_reg(hw,
3634                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3635                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
3636
3637         if (status) {
3638                 hw_dbg(hw, "Auto-Negotiation did not complete\n");
3639                 return status;
3640         }
3641
3642         /* The possible values of fc.requested_mode are:
3643          * 0: Flow control is completely disabled
3644          * 1: Rx flow control is enabled (we can receive pause frames,
3645          *    but not send pause frames).
3646          * 2: Tx flow control is enabled (we can send pause frames but
3647          *    we do not support receiving pause frames).
3648          * 3: Both Rx and Tx flow control (symmetric) are enabled.
3649          * other: Invalid.
3650          */
3651         switch (hw->fc.requested_mode) {
3652         case ixgbe_fc_none:
3653                 /* Flow control completely disabled by software override. */
3654                 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3655                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3656                 break;
3657         case ixgbe_fc_tx_pause:
3658                 /* Tx Flow control is enabled, and Rx Flow control is
3659                  * disabled by software override.
3660                  */
3661                 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3662                 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3663                 break;
3664         case ixgbe_fc_rx_pause:
3665                 /* Rx Flow control is enabled and Tx Flow control is
3666                  * disabled by software override. Since there really
3667                  * isn't a way to advertise that we are capable of RX
3668                  * Pause ONLY, we will advertise that we support both
3669                  * symmetric and asymmetric Rx PAUSE, as such we fall
3670                  * through to the fc_full statement.  Later, we will
3671                  * disable the adapter's ability to send PAUSE frames.
3672                  */
3673         case ixgbe_fc_full:
3674                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3675                 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3676                            IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3677                 break;
3678         default:
3679                 hw_err(hw, "Flow control param set incorrectly\n");
3680                 return -EIO;
3681         }
3682
3683         status = hw->mac.ops.write_iosf_sb_reg(hw,
3684                                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3685                                         IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
3686
3687         /* Restart auto-negotiation. */
3688         status = ixgbe_restart_an_internal_phy_x550em(hw);
3689
3690         return status;
3691 }
3692
3693 /**
3694  * ixgbe_set_mux - Set mux for port 1 access with CS4227
3695  * @hw: pointer to hardware structure
3696  * @state: set mux if 1, clear if 0
3697  */
3698 static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
3699 {
3700         u32 esdp;
3701
3702         if (!hw->bus.lan_id)
3703                 return;
3704         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3705         if (state)
3706                 esdp |= IXGBE_ESDP_SDP1;
3707         else
3708                 esdp &= ~IXGBE_ESDP_SDP1;
3709         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
3710         IXGBE_WRITE_FLUSH(hw);
3711 }
3712
3713 /**
3714  * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
3715  * @hw: pointer to hardware structure
3716  * @mask: Mask to specify which semaphore to acquire
3717  *
3718  * Acquires the SWFW semaphore and sets the I2C MUX
3719  */
3720 static s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3721 {
3722         s32 status;
3723
3724         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3725         if (status)
3726                 return status;
3727
3728         if (mask & IXGBE_GSSR_I2C_MASK)
3729                 ixgbe_set_mux(hw, 1);
3730
3731         return 0;
3732 }
3733
3734 /**
3735  * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3736  * @hw: pointer to hardware structure
3737  * @mask: Mask to specify which semaphore to release
3738  *
3739  * Releases the SWFW semaphore and sets the I2C MUX
3740  */
3741 static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3742 {
3743         if (mask & IXGBE_GSSR_I2C_MASK)
3744                 ixgbe_set_mux(hw, 0);
3745
3746         ixgbe_release_swfw_sync_X540(hw, mask);
3747 }
3748
3749 /**
3750  * ixgbe_acquire_swfw_sync_x550em_a - Acquire SWFW semaphore
3751  * @hw: pointer to hardware structure
3752  * @mask: Mask to specify which semaphore to acquire
3753  *
3754  * Acquires the SWFW semaphore and get the shared PHY token as needed
3755  */
3756 static s32 ixgbe_acquire_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
3757 {
3758         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3759         int retries = FW_PHY_TOKEN_RETRIES;
3760         s32 status;
3761
3762         while (--retries) {
3763                 status = 0;
3764                 if (hmask)
3765                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
3766                 if (status)
3767                         return status;
3768                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
3769                         return 0;
3770
3771                 status = ixgbe_get_phy_token(hw);
3772                 if (!status)
3773                         return 0;
3774                 if (hmask)
3775                         ixgbe_release_swfw_sync_X540(hw, hmask);
3776                 if (status != -EAGAIN)
3777                         return status;
3778                 msleep(FW_PHY_TOKEN_DELAY);
3779         }
3780
3781         return status;
3782 }
3783
3784 /**
3785  * ixgbe_release_swfw_sync_x550em_a - Release SWFW semaphore
3786  * @hw: pointer to hardware structure
3787  * @mask: Mask to specify which semaphore to release
3788  *
3789  * Release the SWFW semaphore and puts the shared PHY token as needed
3790  */
3791 static void ixgbe_release_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
3792 {
3793         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3794
3795         if (mask & IXGBE_GSSR_TOKEN_SM)
3796                 ixgbe_put_phy_token(hw);
3797
3798         if (hmask)
3799                 ixgbe_release_swfw_sync_X540(hw, hmask);
3800 }
3801
3802 /**
3803  * ixgbe_read_phy_reg_x550a - Reads specified PHY register
3804  * @hw: pointer to hardware structure
3805  * @reg_addr: 32 bit address of PHY register to read
3806  * @device_type: 5 bit device type
3807  * @phy_data: Pointer to read data from PHY register
3808  *
3809  * Reads a value from a specified PHY register using the SWFW lock and PHY
3810  * Token. The PHY Token is needed since the MDIO is shared between to MAC
3811  * instances.
3812  */
3813 static s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
3814                                     u32 device_type, u16 *phy_data)
3815 {
3816         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
3817         s32 status;
3818
3819         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
3820                 return -EBUSY;
3821
3822         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
3823
3824         hw->mac.ops.release_swfw_sync(hw, mask);
3825
3826         return status;
3827 }
3828
3829 /**
3830  * ixgbe_write_phy_reg_x550a - Writes specified PHY register
3831  * @hw: pointer to hardware structure
3832  * @reg_addr: 32 bit PHY register to write
3833  * @device_type: 5 bit device type
3834  * @phy_data: Data to write to the PHY register
3835  *
3836  * Writes a value to specified PHY register using the SWFW lock and PHY Token.
3837  * The PHY Token is needed since the MDIO is shared between to MAC instances.
3838  */
3839 static s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
3840                                      u32 device_type, u16 phy_data)
3841 {
3842         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
3843         s32 status;
3844
3845         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
3846                 return -EBUSY;
3847
3848         status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, phy_data);
3849         hw->mac.ops.release_swfw_sync(hw, mask);
3850
3851         return status;
3852 }
3853
3854 #define X550_COMMON_MAC \
3855         .init_hw                        = &ixgbe_init_hw_generic, \
3856         .start_hw                       = &ixgbe_start_hw_X540, \
3857         .clear_hw_cntrs                 = &ixgbe_clear_hw_cntrs_generic, \
3858         .enable_rx_dma                  = &ixgbe_enable_rx_dma_generic, \
3859         .get_mac_addr                   = &ixgbe_get_mac_addr_generic, \
3860         .get_device_caps                = &ixgbe_get_device_caps_generic, \
3861         .stop_adapter                   = &ixgbe_stop_adapter_generic, \
3862         .set_lan_id                     = &ixgbe_set_lan_id_multi_port_pcie, \
3863         .read_analog_reg8               = NULL, \
3864         .write_analog_reg8              = NULL, \
3865         .set_rxpba                      = &ixgbe_set_rxpba_generic, \
3866         .check_link                     = &ixgbe_check_mac_link_generic, \
3867         .blink_led_start                = &ixgbe_blink_led_start_X540, \
3868         .blink_led_stop                 = &ixgbe_blink_led_stop_X540, \
3869         .set_rar                        = &ixgbe_set_rar_generic, \
3870         .clear_rar                      = &ixgbe_clear_rar_generic, \
3871         .set_vmdq                       = &ixgbe_set_vmdq_generic, \
3872         .set_vmdq_san_mac               = &ixgbe_set_vmdq_san_mac_generic, \
3873         .clear_vmdq                     = &ixgbe_clear_vmdq_generic, \
3874         .init_rx_addrs                  = &ixgbe_init_rx_addrs_generic, \
3875         .update_mc_addr_list            = &ixgbe_update_mc_addr_list_generic, \
3876         .enable_mc                      = &ixgbe_enable_mc_generic, \
3877         .disable_mc                     = &ixgbe_disable_mc_generic, \
3878         .clear_vfta                     = &ixgbe_clear_vfta_generic, \
3879         .set_vfta                       = &ixgbe_set_vfta_generic, \
3880         .fc_enable                      = &ixgbe_fc_enable_generic, \
3881         .set_fw_drv_ver                 = &ixgbe_set_fw_drv_ver_x550, \
3882         .init_uta_tables                = &ixgbe_init_uta_tables_generic, \
3883         .set_mac_anti_spoofing          = &ixgbe_set_mac_anti_spoofing, \
3884         .set_vlan_anti_spoofing         = &ixgbe_set_vlan_anti_spoofing, \
3885         .set_source_address_pruning     = \
3886                                 &ixgbe_set_source_address_pruning_X550, \
3887         .set_ethertype_anti_spoofing    = \
3888                                 &ixgbe_set_ethertype_anti_spoofing_X550, \
3889         .disable_rx_buff                = &ixgbe_disable_rx_buff_generic, \
3890         .enable_rx_buff                 = &ixgbe_enable_rx_buff_generic, \
3891         .get_thermal_sensor_data        = NULL, \
3892         .init_thermal_sensor_thresh     = NULL, \
3893         .fw_recovery_mode               = &ixgbe_fw_recovery_mode_X550, \
3894         .enable_rx                      = &ixgbe_enable_rx_generic, \
3895         .disable_rx                     = &ixgbe_disable_rx_x550, \
3896
3897 static const struct ixgbe_mac_operations mac_ops_X550 = {
3898         X550_COMMON_MAC
3899         .led_on                 = ixgbe_led_on_generic,
3900         .led_off                = ixgbe_led_off_generic,
3901         .init_led_link_act      = ixgbe_init_led_link_act_generic,
3902         .reset_hw               = &ixgbe_reset_hw_X540,
3903         .get_media_type         = &ixgbe_get_media_type_X540,
3904         .get_san_mac_addr       = &ixgbe_get_san_mac_addr_generic,
3905         .get_wwn_prefix         = &ixgbe_get_wwn_prefix_generic,
3906         .setup_link             = &ixgbe_setup_mac_link_X540,
3907         .get_link_capabilities  = &ixgbe_get_copper_link_capabilities_generic,
3908         .get_bus_info           = &ixgbe_get_bus_info_generic,
3909         .setup_sfp              = NULL,
3910         .acquire_swfw_sync      = &ixgbe_acquire_swfw_sync_X540,
3911         .release_swfw_sync      = &ixgbe_release_swfw_sync_X540,
3912         .init_swfw_sync         = &ixgbe_init_swfw_sync_X540,
3913         .prot_autoc_read        = prot_autoc_read_generic,
3914         .prot_autoc_write       = prot_autoc_write_generic,
3915         .setup_fc               = ixgbe_setup_fc_generic,
3916         .fc_autoneg             = ixgbe_fc_autoneg,
3917 };
3918
3919 static const struct ixgbe_mac_operations mac_ops_X550EM_x = {
3920         X550_COMMON_MAC
3921         .led_on                 = ixgbe_led_on_t_x550em,
3922         .led_off                = ixgbe_led_off_t_x550em,
3923         .init_led_link_act      = ixgbe_init_led_link_act_generic,
3924         .reset_hw               = &ixgbe_reset_hw_X550em,
3925         .get_media_type         = &ixgbe_get_media_type_X550em,
3926         .get_san_mac_addr       = NULL,
3927         .get_wwn_prefix         = NULL,
3928         .setup_link             = &ixgbe_setup_mac_link_X540,
3929         .get_link_capabilities  = &ixgbe_get_link_capabilities_X550em,
3930         .get_bus_info           = &ixgbe_get_bus_info_X550em,
3931         .setup_sfp              = ixgbe_setup_sfp_modules_X550em,
3932         .acquire_swfw_sync      = &ixgbe_acquire_swfw_sync_X550em,
3933         .release_swfw_sync      = &ixgbe_release_swfw_sync_X550em,
3934         .init_swfw_sync         = &ixgbe_init_swfw_sync_X540,
3935         .setup_fc               = NULL, /* defined later */
3936         .fc_autoneg             = ixgbe_fc_autoneg,
3937         .read_iosf_sb_reg       = ixgbe_read_iosf_sb_reg_x550,
3938         .write_iosf_sb_reg      = ixgbe_write_iosf_sb_reg_x550,
3939 };
3940
3941 static const struct ixgbe_mac_operations mac_ops_X550EM_x_fw = {
3942         X550_COMMON_MAC
3943         .led_on                 = NULL,
3944         .led_off                = NULL,
3945         .init_led_link_act      = NULL,
3946         .reset_hw               = &ixgbe_reset_hw_X550em,
3947         .get_media_type         = &ixgbe_get_media_type_X550em,
3948         .get_san_mac_addr       = NULL,
3949         .get_wwn_prefix         = NULL,
3950         .setup_link             = &ixgbe_setup_mac_link_X540,
3951         .get_link_capabilities  = &ixgbe_get_link_capabilities_X550em,
3952         .get_bus_info           = &ixgbe_get_bus_info_X550em,
3953         .setup_sfp              = ixgbe_setup_sfp_modules_X550em,
3954         .acquire_swfw_sync      = &ixgbe_acquire_swfw_sync_X550em,
3955         .release_swfw_sync      = &ixgbe_release_swfw_sync_X550em,
3956         .init_swfw_sync         = &ixgbe_init_swfw_sync_X540,
3957         .setup_fc               = NULL,
3958         .fc_autoneg             = ixgbe_fc_autoneg,
3959         .read_iosf_sb_reg       = ixgbe_read_iosf_sb_reg_x550,
3960         .write_iosf_sb_reg      = ixgbe_write_iosf_sb_reg_x550,
3961 };
3962
3963 static const struct ixgbe_mac_operations mac_ops_x550em_a = {
3964         X550_COMMON_MAC
3965         .led_on                 = ixgbe_led_on_t_x550em,
3966         .led_off                = ixgbe_led_off_t_x550em,
3967         .init_led_link_act      = ixgbe_init_led_link_act_generic,
3968         .reset_hw               = ixgbe_reset_hw_X550em,
3969         .get_media_type         = ixgbe_get_media_type_X550em,
3970         .get_san_mac_addr       = NULL,
3971         .get_wwn_prefix         = NULL,
3972         .setup_link             = &ixgbe_setup_mac_link_X540,
3973         .get_link_capabilities  = ixgbe_get_link_capabilities_X550em,
3974         .get_bus_info           = ixgbe_get_bus_info_X550em,
3975         .setup_sfp              = ixgbe_setup_sfp_modules_X550em,
3976         .acquire_swfw_sync      = ixgbe_acquire_swfw_sync_x550em_a,
3977         .release_swfw_sync      = ixgbe_release_swfw_sync_x550em_a,
3978         .setup_fc               = ixgbe_setup_fc_x550em,
3979         .fc_autoneg             = ixgbe_fc_autoneg,
3980         .read_iosf_sb_reg       = ixgbe_read_iosf_sb_reg_x550a,
3981         .write_iosf_sb_reg      = ixgbe_write_iosf_sb_reg_x550a,
3982 };
3983
3984 static const struct ixgbe_mac_operations mac_ops_x550em_a_fw = {
3985         X550_COMMON_MAC
3986         .led_on                 = ixgbe_led_on_generic,
3987         .led_off                = ixgbe_led_off_generic,
3988         .init_led_link_act      = ixgbe_init_led_link_act_generic,
3989         .reset_hw               = ixgbe_reset_hw_X550em,
3990         .get_media_type         = ixgbe_get_media_type_X550em,
3991         .get_san_mac_addr       = NULL,
3992         .get_wwn_prefix         = NULL,
3993         .setup_link             = NULL, /* defined later */
3994         .get_link_capabilities  = ixgbe_get_link_capabilities_X550em,
3995         .get_bus_info           = ixgbe_get_bus_info_X550em,
3996         .setup_sfp              = ixgbe_setup_sfp_modules_X550em,
3997         .acquire_swfw_sync      = ixgbe_acquire_swfw_sync_x550em_a,
3998         .release_swfw_sync      = ixgbe_release_swfw_sync_x550em_a,
3999         .setup_fc               = ixgbe_setup_fc_x550em,
4000         .fc_autoneg             = ixgbe_fc_autoneg,
4001         .read_iosf_sb_reg       = ixgbe_read_iosf_sb_reg_x550a,
4002         .write_iosf_sb_reg      = ixgbe_write_iosf_sb_reg_x550a,
4003 };
4004
4005 #define X550_COMMON_EEP \
4006         .read                   = &ixgbe_read_ee_hostif_X550, \
4007         .read_buffer            = &ixgbe_read_ee_hostif_buffer_X550, \
4008         .write                  = &ixgbe_write_ee_hostif_X550, \
4009         .write_buffer           = &ixgbe_write_ee_hostif_buffer_X550, \
4010         .validate_checksum      = &ixgbe_validate_eeprom_checksum_X550, \
4011         .update_checksum        = &ixgbe_update_eeprom_checksum_X550, \
4012         .calc_checksum          = &ixgbe_calc_eeprom_checksum_X550, \
4013
4014 static const struct ixgbe_eeprom_operations eeprom_ops_X550 = {
4015         X550_COMMON_EEP
4016         .init_params            = &ixgbe_init_eeprom_params_X550,
4017 };
4018
4019 static const struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = {
4020         X550_COMMON_EEP
4021         .init_params            = &ixgbe_init_eeprom_params_X540,
4022 };
4023
4024 #define X550_COMMON_PHY \
4025         .identify_sfp           = &ixgbe_identify_module_generic, \
4026         .reset                  = NULL, \
4027         .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic, \
4028         .read_i2c_byte          = &ixgbe_read_i2c_byte_generic, \
4029         .write_i2c_byte         = &ixgbe_write_i2c_byte_generic, \
4030         .read_i2c_sff8472       = &ixgbe_read_i2c_sff8472_generic, \
4031         .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_generic, \
4032         .write_i2c_eeprom       = &ixgbe_write_i2c_eeprom_generic, \
4033         .setup_link             = &ixgbe_setup_phy_link_generic, \
4034         .set_phy_power          = NULL,
4035
4036 static const struct ixgbe_phy_operations phy_ops_X550 = {
4037         X550_COMMON_PHY
4038         .check_overtemp         = &ixgbe_tn_check_overtemp,
4039         .init                   = NULL,
4040         .identify               = &ixgbe_identify_phy_generic,
4041         .read_reg               = &ixgbe_read_phy_reg_generic,
4042         .write_reg              = &ixgbe_write_phy_reg_generic,
4043 };
4044
4045 static const struct ixgbe_phy_operations phy_ops_X550EM_x = {
4046         X550_COMMON_PHY
4047         .check_overtemp         = &ixgbe_tn_check_overtemp,
4048         .init                   = &ixgbe_init_phy_ops_X550em,
4049         .identify               = &ixgbe_identify_phy_x550em,
4050         .read_reg               = &ixgbe_read_phy_reg_generic,
4051         .write_reg              = &ixgbe_write_phy_reg_generic,
4052 };
4053
4054 static const struct ixgbe_phy_operations phy_ops_x550em_x_fw = {
4055         X550_COMMON_PHY
4056         .check_overtemp         = NULL,
4057         .init                   = ixgbe_init_phy_ops_X550em,
4058         .identify               = ixgbe_identify_phy_x550em,
4059         .read_reg               = NULL,
4060         .write_reg              = NULL,
4061         .read_reg_mdi           = NULL,
4062         .write_reg_mdi          = NULL,
4063 };
4064
4065 static const struct ixgbe_phy_operations phy_ops_x550em_a = {
4066         X550_COMMON_PHY
4067         .check_overtemp         = &ixgbe_tn_check_overtemp,
4068         .init                   = &ixgbe_init_phy_ops_X550em,
4069         .identify               = &ixgbe_identify_phy_x550em,
4070         .read_reg               = &ixgbe_read_phy_reg_x550a,
4071         .write_reg              = &ixgbe_write_phy_reg_x550a,
4072         .read_reg_mdi           = &ixgbe_read_phy_reg_mdi,
4073         .write_reg_mdi          = &ixgbe_write_phy_reg_mdi,
4074 };
4075
4076 static const struct ixgbe_phy_operations phy_ops_x550em_a_fw = {
4077         X550_COMMON_PHY
4078         .check_overtemp         = ixgbe_check_overtemp_fw,
4079         .init                   = ixgbe_init_phy_ops_X550em,
4080         .identify               = ixgbe_identify_phy_fw,
4081         .read_reg               = NULL,
4082         .write_reg              = NULL,
4083         .read_reg_mdi           = NULL,
4084         .write_reg_mdi          = NULL,
4085 };
4086
4087 static const struct ixgbe_link_operations link_ops_x550em_x = {
4088         .read_link              = &ixgbe_read_i2c_combined_generic,
4089         .read_link_unlocked     = &ixgbe_read_i2c_combined_generic_unlocked,
4090         .write_link             = &ixgbe_write_i2c_combined_generic,
4091         .write_link_unlocked    = &ixgbe_write_i2c_combined_generic_unlocked,
4092 };
4093
4094 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
4095         IXGBE_MVALS_INIT(X550)
4096 };
4097
4098 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {
4099         IXGBE_MVALS_INIT(X550EM_x)
4100 };
4101
4102 static const u32 ixgbe_mvals_x550em_a[IXGBE_MVALS_IDX_LIMIT] = {
4103         IXGBE_MVALS_INIT(X550EM_a)
4104 };
4105
4106 const struct ixgbe_info ixgbe_X550_info = {
4107         .mac                    = ixgbe_mac_X550,
4108         .get_invariants         = &ixgbe_get_invariants_X540,
4109         .mac_ops                = &mac_ops_X550,
4110         .eeprom_ops             = &eeprom_ops_X550,
4111         .phy_ops                = &phy_ops_X550,
4112         .mbx_ops                = &mbx_ops_generic,
4113         .mvals                  = ixgbe_mvals_X550,
4114 };
4115
4116 const struct ixgbe_info ixgbe_X550EM_x_info = {
4117         .mac                    = ixgbe_mac_X550EM_x,
4118         .get_invariants         = &ixgbe_get_invariants_X550_x,
4119         .mac_ops                = &mac_ops_X550EM_x,
4120         .eeprom_ops             = &eeprom_ops_X550EM_x,
4121         .phy_ops                = &phy_ops_X550EM_x,
4122         .mbx_ops                = &mbx_ops_generic,
4123         .mvals                  = ixgbe_mvals_X550EM_x,
4124         .link_ops               = &link_ops_x550em_x,
4125 };
4126
4127 const struct ixgbe_info ixgbe_x550em_x_fw_info = {
4128         .mac                    = ixgbe_mac_X550EM_x,
4129         .get_invariants         = ixgbe_get_invariants_X550_x_fw,
4130         .mac_ops                = &mac_ops_X550EM_x_fw,
4131         .eeprom_ops             = &eeprom_ops_X550EM_x,
4132         .phy_ops                = &phy_ops_x550em_x_fw,
4133         .mbx_ops                = &mbx_ops_generic,
4134         .mvals                  = ixgbe_mvals_X550EM_x,
4135 };
4136
4137 const struct ixgbe_info ixgbe_x550em_a_info = {
4138         .mac                    = ixgbe_mac_x550em_a,
4139         .get_invariants         = &ixgbe_get_invariants_X550_a,
4140         .mac_ops                = &mac_ops_x550em_a,
4141         .eeprom_ops             = &eeprom_ops_X550EM_x,
4142         .phy_ops                = &phy_ops_x550em_a,
4143         .mbx_ops                = &mbx_ops_generic,
4144         .mvals                  = ixgbe_mvals_x550em_a,
4145 };
4146
4147 const struct ixgbe_info ixgbe_x550em_a_fw_info = {
4148         .mac                    = ixgbe_mac_x550em_a,
4149         .get_invariants         = ixgbe_get_invariants_X550_a_fw,
4150         .mac_ops                = &mac_ops_x550em_a_fw,
4151         .eeprom_ops             = &eeprom_ops_X550EM_x,
4152         .phy_ops                = &phy_ops_x550em_a_fw,
4153         .mbx_ops                = &mbx_ops_generic,
4154         .mvals                  = ixgbe_mvals_x550em_a,
4155 };