1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
35 #include <linux/interrupt.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
46 #include <linux/if_vlan.h>
47 #include <linux/if_bridge.h>
48 #include <linux/prefetch.h>
49 #include <scsi/fc/fc_fcoe.h>
52 #include "ixgbe_common.h"
53 #include "ixgbe_dcb_82599.h"
54 #include "ixgbe_sriov.h"
56 char ixgbe_driver_name[] = "ixgbe";
57 static const char ixgbe_driver_string[] =
58 "Intel(R) 10 Gigabit PCI Express Network Driver";
60 char ixgbe_default_device_descr[] =
61 "Intel(R) 10 Gigabit Network Connection";
63 static char ixgbe_default_device_descr[] =
64 "Intel(R) 10 Gigabit Network Connection";
69 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
70 __stringify(BUILD) "-k"
71 const char ixgbe_driver_version[] = DRV_VERSION;
72 static const char ixgbe_copyright[] =
73 "Copyright (c) 1999-2012 Intel Corporation.";
75 static const struct ixgbe_info *ixgbe_info_tbl[] = {
76 [board_82598] = &ixgbe_82598_info,
77 [board_82599] = &ixgbe_82599_info,
78 [board_X540] = &ixgbe_X540_info,
81 /* ixgbe_pci_tbl - PCI Device ID Table
83 * Wildcard entries (PCI_ANY_ID) should come last
84 * Last entry must be all 0s
86 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
87 * Class, Class Mask, private data (not used) }
89 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
119 /* required last entry */
122 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
124 #ifdef CONFIG_IXGBE_DCA
125 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
127 static struct notifier_block dca_notifier = {
128 .notifier_call = ixgbe_notify_dca,
134 #ifdef CONFIG_PCI_IOV
135 static unsigned int max_vfs;
136 module_param(max_vfs, uint, 0);
137 MODULE_PARM_DESC(max_vfs,
138 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
139 #endif /* CONFIG_PCI_IOV */
141 static unsigned int allow_unsupported_sfp;
142 module_param(allow_unsupported_sfp, uint, 0);
143 MODULE_PARM_DESC(allow_unsupported_sfp,
144 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
146 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
147 static int debug = -1;
148 module_param(debug, int, 0);
149 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
151 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
152 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
153 MODULE_LICENSE("GPL");
154 MODULE_VERSION(DRV_VERSION);
156 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
158 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
159 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
160 schedule_work(&adapter->service_task);
163 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
165 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
167 /* flush memory to make sure state is correct before next watchdog */
168 smp_mb__before_clear_bit();
169 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
172 struct ixgbe_reg_info {
177 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
179 /* General Registers */
180 {IXGBE_CTRL, "CTRL"},
181 {IXGBE_STATUS, "STATUS"},
182 {IXGBE_CTRL_EXT, "CTRL_EXT"},
184 /* Interrupt Registers */
185 {IXGBE_EICR, "EICR"},
188 {IXGBE_SRRCTL(0), "SRRCTL"},
189 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
190 {IXGBE_RDLEN(0), "RDLEN"},
191 {IXGBE_RDH(0), "RDH"},
192 {IXGBE_RDT(0), "RDT"},
193 {IXGBE_RXDCTL(0), "RXDCTL"},
194 {IXGBE_RDBAL(0), "RDBAL"},
195 {IXGBE_RDBAH(0), "RDBAH"},
198 {IXGBE_TDBAL(0), "TDBAL"},
199 {IXGBE_TDBAH(0), "TDBAH"},
200 {IXGBE_TDLEN(0), "TDLEN"},
201 {IXGBE_TDH(0), "TDH"},
202 {IXGBE_TDT(0), "TDT"},
203 {IXGBE_TXDCTL(0), "TXDCTL"},
205 /* List Terminator */
211 * ixgbe_regdump - register printout routine
213 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
219 switch (reginfo->ofs) {
220 case IXGBE_SRRCTL(0):
221 for (i = 0; i < 64; i++)
222 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
224 case IXGBE_DCA_RXCTRL(0):
225 for (i = 0; i < 64; i++)
226 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
229 for (i = 0; i < 64; i++)
230 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
233 for (i = 0; i < 64; i++)
234 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
240 case IXGBE_RXDCTL(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
272 case IXGBE_TXDCTL(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
277 pr_info("%-15s %08x\n", reginfo->name,
278 IXGBE_READ_REG(hw, reginfo->ofs));
282 for (i = 0; i < 8; i++) {
283 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
284 pr_err("%-15s", rname);
285 for (j = 0; j < 8; j++)
286 pr_cont(" %08x", regs[i*8+j]);
293 * ixgbe_dump - Print registers, tx-rings and rx-rings
295 static void ixgbe_dump(struct ixgbe_adapter *adapter)
297 struct net_device *netdev = adapter->netdev;
298 struct ixgbe_hw *hw = &adapter->hw;
299 struct ixgbe_reg_info *reginfo;
301 struct ixgbe_ring *tx_ring;
302 struct ixgbe_tx_buffer *tx_buffer;
303 union ixgbe_adv_tx_desc *tx_desc;
304 struct my_u0 { u64 a; u64 b; } *u0;
305 struct ixgbe_ring *rx_ring;
306 union ixgbe_adv_rx_desc *rx_desc;
307 struct ixgbe_rx_buffer *rx_buffer_info;
311 if (!netif_msg_hw(adapter))
314 /* Print netdevice Info */
316 dev_info(&adapter->pdev->dev, "Net device Info\n");
317 pr_info("Device Name state "
318 "trans_start last_rx\n");
319 pr_info("%-15s %016lX %016lX %016lX\n",
326 /* Print Registers */
327 dev_info(&adapter->pdev->dev, "Register Dump\n");
328 pr_info(" Register Name Value\n");
329 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
330 reginfo->name; reginfo++) {
331 ixgbe_regdump(hw, reginfo);
334 /* Print TX Ring Summary */
335 if (!netdev || !netif_running(netdev))
338 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
339 pr_info(" %s %s %s %s\n",
340 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
341 "leng", "ntw", "timestamp");
342 for (n = 0; n < adapter->num_tx_queues; n++) {
343 tx_ring = adapter->tx_ring[n];
344 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
345 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
346 n, tx_ring->next_to_use, tx_ring->next_to_clean,
347 (u64)dma_unmap_addr(tx_buffer, dma),
348 dma_unmap_len(tx_buffer, len),
349 tx_buffer->next_to_watch,
350 (u64)tx_buffer->time_stamp);
354 if (!netif_msg_tx_done(adapter))
355 goto rx_ring_summary;
357 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
359 /* Transmit Descriptor Formats
361 * 82598 Advanced Transmit Descriptor
362 * +--------------------------------------------------------------+
363 * 0 | Buffer Address [63:0] |
364 * +--------------------------------------------------------------+
365 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
366 * +--------------------------------------------------------------+
367 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
369 * 82598 Advanced Transmit Descriptor (Write-Back Format)
370 * +--------------------------------------------------------------+
372 * +--------------------------------------------------------------+
373 * 8 | RSV | STA | NXTSEQ |
374 * +--------------------------------------------------------------+
377 * 82599+ Advanced Transmit Descriptor
378 * +--------------------------------------------------------------+
379 * 0 | Buffer Address [63:0] |
380 * +--------------------------------------------------------------+
381 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
382 * +--------------------------------------------------------------+
383 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
385 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
386 * +--------------------------------------------------------------+
388 * +--------------------------------------------------------------+
389 * 8 | RSV | STA | RSV |
390 * +--------------------------------------------------------------+
394 for (n = 0; n < adapter->num_tx_queues; n++) {
395 tx_ring = adapter->tx_ring[n];
396 pr_info("------------------------------------\n");
397 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
398 pr_info("------------------------------------\n");
399 pr_info("%s%s %s %s %s %s\n",
400 "T [desc] [address 63:0 ] ",
401 "[PlPOIdStDDt Ln] [bi->dma ] ",
402 "leng", "ntw", "timestamp", "bi->skb");
404 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
405 tx_desc = IXGBE_TX_DESC(tx_ring, i);
406 tx_buffer = &tx_ring->tx_buffer_info[i];
407 u0 = (struct my_u0 *)tx_desc;
408 if (dma_unmap_len(tx_buffer, len) > 0) {
409 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
413 (u64)dma_unmap_addr(tx_buffer, dma),
414 dma_unmap_len(tx_buffer, len),
415 tx_buffer->next_to_watch,
416 (u64)tx_buffer->time_stamp,
418 if (i == tx_ring->next_to_use &&
419 i == tx_ring->next_to_clean)
421 else if (i == tx_ring->next_to_use)
423 else if (i == tx_ring->next_to_clean)
428 if (netif_msg_pktdata(adapter) &&
430 print_hex_dump(KERN_INFO, "",
431 DUMP_PREFIX_ADDRESS, 16, 1,
432 tx_buffer->skb->data,
433 dma_unmap_len(tx_buffer, len),
439 /* Print RX Rings Summary */
441 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
442 pr_info("Queue [NTU] [NTC]\n");
443 for (n = 0; n < adapter->num_rx_queues; n++) {
444 rx_ring = adapter->rx_ring[n];
445 pr_info("%5d %5X %5X\n",
446 n, rx_ring->next_to_use, rx_ring->next_to_clean);
450 if (!netif_msg_rx_status(adapter))
453 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
455 /* Receive Descriptor Formats
457 * 82598 Advanced Receive Descriptor (Read) Format
459 * +-----------------------------------------------------+
460 * 0 | Packet Buffer Address [63:1] |A0/NSE|
461 * +----------------------------------------------+------+
462 * 8 | Header Buffer Address [63:1] | DD |
463 * +-----------------------------------------------------+
466 * 82598 Advanced Receive Descriptor (Write-Back) Format
468 * 63 48 47 32 31 30 21 20 16 15 4 3 0
469 * +------------------------------------------------------+
470 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
471 * | Packet | IP | | | | Type | Type |
472 * | Checksum | Ident | | | | | |
473 * +------------------------------------------------------+
474 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
475 * +------------------------------------------------------+
476 * 63 48 47 32 31 20 19 0
478 * 82599+ Advanced Receive Descriptor (Read) Format
480 * +-----------------------------------------------------+
481 * 0 | Packet Buffer Address [63:1] |A0/NSE|
482 * +----------------------------------------------+------+
483 * 8 | Header Buffer Address [63:1] | DD |
484 * +-----------------------------------------------------+
487 * 82599+ Advanced Receive Descriptor (Write-Back) Format
489 * 63 48 47 32 31 30 21 20 17 16 4 3 0
490 * +------------------------------------------------------+
491 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
492 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
493 * |/ Flow Dir Flt ID | | | | | |
494 * +------------------------------------------------------+
495 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
496 * +------------------------------------------------------+
497 * 63 48 47 32 31 20 19 0
500 for (n = 0; n < adapter->num_rx_queues; n++) {
501 rx_ring = adapter->rx_ring[n];
502 pr_info("------------------------------------\n");
503 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
504 pr_info("------------------------------------\n");
506 "R [desc] [ PktBuf A0] ",
507 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
508 "<-- Adv Rx Read format\n");
510 "RWB[desc] [PcsmIpSHl PtRs] ",
511 "[vl er S cks ln] ---------------- [bi->skb ] ",
512 "<-- Adv Rx Write-Back format\n");
514 for (i = 0; i < rx_ring->count; i++) {
515 rx_buffer_info = &rx_ring->rx_buffer_info[i];
516 rx_desc = IXGBE_RX_DESC(rx_ring, i);
517 u0 = (struct my_u0 *)rx_desc;
518 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
519 if (staterr & IXGBE_RXD_STAT_DD) {
520 /* Descriptor Done */
521 pr_info("RWB[0x%03X] %016llX "
522 "%016llX ---------------- %p", i,
525 rx_buffer_info->skb);
527 pr_info("R [0x%03X] %016llX "
528 "%016llX %016llX %p", i,
531 (u64)rx_buffer_info->dma,
532 rx_buffer_info->skb);
534 if (netif_msg_pktdata(adapter) &&
535 rx_buffer_info->dma) {
536 print_hex_dump(KERN_INFO, "",
537 DUMP_PREFIX_ADDRESS, 16, 1,
538 page_address(rx_buffer_info->page) +
539 rx_buffer_info->page_offset,
540 ixgbe_rx_bufsz(rx_ring), true);
544 if (i == rx_ring->next_to_use)
546 else if (i == rx_ring->next_to_clean)
558 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
562 /* Let firmware take over control of h/w */
563 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
564 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
565 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
568 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
572 /* Let firmware know the driver has taken over */
573 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
574 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
575 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
579 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
580 * @adapter: pointer to adapter struct
581 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
582 * @queue: queue to map the corresponding interrupt to
583 * @msix_vector: the vector to map to the corresponding queue
586 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
587 u8 queue, u8 msix_vector)
590 struct ixgbe_hw *hw = &adapter->hw;
591 switch (hw->mac.type) {
592 case ixgbe_mac_82598EB:
593 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
596 index = (((direction * 64) + queue) >> 2) & 0x1F;
597 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
598 ivar &= ~(0xFF << (8 * (queue & 0x3)));
599 ivar |= (msix_vector << (8 * (queue & 0x3)));
600 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
602 case ixgbe_mac_82599EB:
604 if (direction == -1) {
606 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
607 index = ((queue & 1) * 8);
608 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
609 ivar &= ~(0xFF << index);
610 ivar |= (msix_vector << index);
611 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
614 /* tx or rx causes */
615 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
616 index = ((16 * (queue & 1)) + (8 * direction));
617 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
618 ivar &= ~(0xFF << index);
619 ivar |= (msix_vector << index);
620 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
628 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
633 switch (adapter->hw.mac.type) {
634 case ixgbe_mac_82598EB:
635 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
636 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
638 case ixgbe_mac_82599EB:
640 mask = (qmask & 0xFFFFFFFF);
641 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
642 mask = (qmask >> 32);
643 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
650 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
651 struct ixgbe_tx_buffer *tx_buffer)
653 if (tx_buffer->skb) {
654 dev_kfree_skb_any(tx_buffer->skb);
655 if (dma_unmap_len(tx_buffer, len))
656 dma_unmap_single(ring->dev,
657 dma_unmap_addr(tx_buffer, dma),
658 dma_unmap_len(tx_buffer, len),
660 } else if (dma_unmap_len(tx_buffer, len)) {
661 dma_unmap_page(ring->dev,
662 dma_unmap_addr(tx_buffer, dma),
663 dma_unmap_len(tx_buffer, len),
666 tx_buffer->next_to_watch = NULL;
667 tx_buffer->skb = NULL;
668 dma_unmap_len_set(tx_buffer, len, 0);
669 /* tx_buffer must be completely set up in the transmit path */
672 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
674 struct ixgbe_hw *hw = &adapter->hw;
675 struct ixgbe_hw_stats *hwstats = &adapter->stats;
679 if ((hw->fc.current_mode != ixgbe_fc_full) &&
680 (hw->fc.current_mode != ixgbe_fc_rx_pause))
683 switch (hw->mac.type) {
684 case ixgbe_mac_82598EB:
685 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
688 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
690 hwstats->lxoffrxc += data;
692 /* refill credits (no tx hang) if we received xoff */
696 for (i = 0; i < adapter->num_tx_queues; i++)
697 clear_bit(__IXGBE_HANG_CHECK_ARMED,
698 &adapter->tx_ring[i]->state);
701 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
703 struct ixgbe_hw *hw = &adapter->hw;
704 struct ixgbe_hw_stats *hwstats = &adapter->stats;
707 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
709 if (adapter->ixgbe_ieee_pfc)
710 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
712 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
713 ixgbe_update_xoff_rx_lfc(adapter);
717 /* update stats for each tc, only valid with PFC enabled */
718 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
719 switch (hw->mac.type) {
720 case ixgbe_mac_82598EB:
721 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
724 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
726 hwstats->pxoffrxc[i] += xoff[i];
729 /* disarm tx queues that have received xoff frames */
730 for (i = 0; i < adapter->num_tx_queues; i++) {
731 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
732 u8 tc = tx_ring->dcb_tc;
735 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
739 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
741 return ring->stats.packets;
744 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
746 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
747 struct ixgbe_hw *hw = &adapter->hw;
749 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
750 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
753 return (head < tail) ?
754 tail - head : (tail + ring->count - head);
759 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
761 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
762 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
763 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
766 clear_check_for_tx_hang(tx_ring);
769 * Check for a hung queue, but be thorough. This verifies
770 * that a transmit has been completed since the previous
771 * check AND there is at least one packet pending. The
772 * ARMED bit is set to indicate a potential hang. The
773 * bit is cleared if a pause frame is received to remove
774 * false hang detection due to PFC or 802.3x frames. By
775 * requiring this to fail twice we avoid races with
776 * pfc clearing the ARMED bit and conditions where we
777 * run the check_tx_hang logic with a transmit completion
778 * pending but without time to complete it yet.
780 if ((tx_done_old == tx_done) && tx_pending) {
781 /* make sure it is true for two checks in a row */
782 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
785 /* update completed stats and continue */
786 tx_ring->tx_stats.tx_done_old = tx_done;
787 /* reset the countdown */
788 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
795 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
796 * @adapter: driver private struct
798 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
801 /* Do the reset outside of interrupt context */
802 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
803 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
804 ixgbe_service_event_schedule(adapter);
809 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
810 * @q_vector: structure containing interrupt and ring information
811 * @tx_ring: tx ring to clean
813 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
814 struct ixgbe_ring *tx_ring)
816 struct ixgbe_adapter *adapter = q_vector->adapter;
817 struct ixgbe_tx_buffer *tx_buffer;
818 union ixgbe_adv_tx_desc *tx_desc;
819 unsigned int total_bytes = 0, total_packets = 0;
820 unsigned int budget = q_vector->tx.work_limit;
821 unsigned int i = tx_ring->next_to_clean;
823 if (test_bit(__IXGBE_DOWN, &adapter->state))
826 tx_buffer = &tx_ring->tx_buffer_info[i];
827 tx_desc = IXGBE_TX_DESC(tx_ring, i);
831 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
833 /* if next_to_watch is not set then there is no work pending */
837 /* prevent any other reads prior to eop_desc */
840 /* if DD is not set pending work has not been completed */
841 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
844 /* clear next_to_watch to prevent false hangs */
845 tx_buffer->next_to_watch = NULL;
847 /* update the statistics for this packet */
848 total_bytes += tx_buffer->bytecount;
849 total_packets += tx_buffer->gso_segs;
851 if (unlikely(tx_buffer->tx_flags & IXGBE_TX_FLAGS_TSTAMP))
852 ixgbe_ptp_tx_hwtstamp(q_vector, tx_buffer->skb);
855 dev_kfree_skb_any(tx_buffer->skb);
857 /* unmap skb header data */
858 dma_unmap_single(tx_ring->dev,
859 dma_unmap_addr(tx_buffer, dma),
860 dma_unmap_len(tx_buffer, len),
863 /* clear tx_buffer data */
864 tx_buffer->skb = NULL;
865 dma_unmap_len_set(tx_buffer, len, 0);
867 /* unmap remaining buffers */
868 while (tx_desc != eop_desc) {
874 tx_buffer = tx_ring->tx_buffer_info;
875 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
878 /* unmap any remaining paged data */
879 if (dma_unmap_len(tx_buffer, len)) {
880 dma_unmap_page(tx_ring->dev,
881 dma_unmap_addr(tx_buffer, dma),
882 dma_unmap_len(tx_buffer, len),
884 dma_unmap_len_set(tx_buffer, len, 0);
888 /* move us one more past the eop_desc for start of next pkt */
894 tx_buffer = tx_ring->tx_buffer_info;
895 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
898 /* issue prefetch for next Tx descriptor */
901 /* update budget accounting */
903 } while (likely(budget));
906 tx_ring->next_to_clean = i;
907 u64_stats_update_begin(&tx_ring->syncp);
908 tx_ring->stats.bytes += total_bytes;
909 tx_ring->stats.packets += total_packets;
910 u64_stats_update_end(&tx_ring->syncp);
911 q_vector->tx.total_bytes += total_bytes;
912 q_vector->tx.total_packets += total_packets;
914 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
915 /* schedule immediate reset if we believe we hung */
916 struct ixgbe_hw *hw = &adapter->hw;
917 e_err(drv, "Detected Tx Unit Hang\n"
919 " TDH, TDT <%x>, <%x>\n"
920 " next_to_use <%x>\n"
921 " next_to_clean <%x>\n"
922 "tx_buffer_info[next_to_clean]\n"
923 " time_stamp <%lx>\n"
925 tx_ring->queue_index,
926 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
927 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
928 tx_ring->next_to_use, i,
929 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
931 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
934 "tx hang %d detected on queue %d, resetting adapter\n",
935 adapter->tx_timeout_count + 1, tx_ring->queue_index);
937 /* schedule immediate reset if we believe we hung */
938 ixgbe_tx_timeout_reset(adapter);
940 /* the adapter is about to reset, no point in enabling stuff */
944 netdev_tx_completed_queue(txring_txq(tx_ring),
945 total_packets, total_bytes);
947 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
948 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
949 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
950 /* Make sure that anybody stopping the queue after this
951 * sees the new next_to_clean.
954 if (__netif_subqueue_stopped(tx_ring->netdev,
955 tx_ring->queue_index)
956 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
957 netif_wake_subqueue(tx_ring->netdev,
958 tx_ring->queue_index);
959 ++tx_ring->tx_stats.restart_queue;
966 #ifdef CONFIG_IXGBE_DCA
967 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
968 struct ixgbe_ring *tx_ring,
971 struct ixgbe_hw *hw = &adapter->hw;
972 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
975 switch (hw->mac.type) {
976 case ixgbe_mac_82598EB:
977 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
979 case ixgbe_mac_82599EB:
981 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
982 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
985 /* for unknown hardware do not write register */
990 * We can enable relaxed ordering for reads, but not writes when
991 * DCA is enabled. This is due to a known issue in some chipsets
992 * which will cause the DCA tag to be cleared.
994 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
995 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
996 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
998 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
1001 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1002 struct ixgbe_ring *rx_ring,
1005 struct ixgbe_hw *hw = &adapter->hw;
1006 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1007 u8 reg_idx = rx_ring->reg_idx;
1010 switch (hw->mac.type) {
1011 case ixgbe_mac_82599EB:
1012 case ixgbe_mac_X540:
1013 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1020 * We can enable relaxed ordering for reads, but not writes when
1021 * DCA is enabled. This is due to a known issue in some chipsets
1022 * which will cause the DCA tag to be cleared.
1024 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1025 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1027 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1030 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1032 struct ixgbe_adapter *adapter = q_vector->adapter;
1033 struct ixgbe_ring *ring;
1034 int cpu = get_cpu();
1036 if (q_vector->cpu == cpu)
1039 ixgbe_for_each_ring(ring, q_vector->tx)
1040 ixgbe_update_tx_dca(adapter, ring, cpu);
1042 ixgbe_for_each_ring(ring, q_vector->rx)
1043 ixgbe_update_rx_dca(adapter, ring, cpu);
1045 q_vector->cpu = cpu;
1050 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1054 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1057 /* always use CB2 mode, difference is masked in the CB driver */
1058 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1060 for (i = 0; i < adapter->num_q_vectors; i++) {
1061 adapter->q_vector[i]->cpu = -1;
1062 ixgbe_update_dca(adapter->q_vector[i]);
1066 static int __ixgbe_notify_dca(struct device *dev, void *data)
1068 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1069 unsigned long event = *(unsigned long *)data;
1071 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1075 case DCA_PROVIDER_ADD:
1076 /* if we're already enabled, don't do it again */
1077 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1079 if (dca_add_requester(dev) == 0) {
1080 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1081 ixgbe_setup_dca(adapter);
1084 /* Fall Through since DCA is disabled. */
1085 case DCA_PROVIDER_REMOVE:
1086 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1087 dca_remove_requester(dev);
1088 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1089 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1097 #endif /* CONFIG_IXGBE_DCA */
1098 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1099 union ixgbe_adv_rx_desc *rx_desc,
1100 struct sk_buff *skb)
1102 if (ring->netdev->features & NETIF_F_RXHASH)
1103 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1108 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1109 * @ring: structure containing ring specific data
1110 * @rx_desc: advanced rx descriptor
1112 * Returns : true if it is FCoE pkt
1114 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1115 union ixgbe_adv_rx_desc *rx_desc)
1117 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1119 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1120 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1121 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1122 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1125 #endif /* IXGBE_FCOE */
1127 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1128 * @ring: structure containing ring specific data
1129 * @rx_desc: current Rx descriptor being processed
1130 * @skb: skb currently being received and modified
1132 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1133 union ixgbe_adv_rx_desc *rx_desc,
1134 struct sk_buff *skb)
1136 skb_checksum_none_assert(skb);
1138 /* Rx csum disabled */
1139 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1142 /* if IP and error */
1143 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1144 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1145 ring->rx_stats.csum_err++;
1149 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1152 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1153 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1156 * 82599 errata, UDP frames with a 0 checksum can be marked as
1159 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1160 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1163 ring->rx_stats.csum_err++;
1167 /* It must be a TCP or UDP packet with a valid checksum */
1168 skb->ip_summed = CHECKSUM_UNNECESSARY;
1171 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1173 rx_ring->next_to_use = val;
1175 /* update next to alloc since we have filled the ring */
1176 rx_ring->next_to_alloc = val;
1178 * Force memory writes to complete before letting h/w
1179 * know there are new descriptors to fetch. (Only
1180 * applicable for weak-ordered memory model archs,
1184 writel(val, rx_ring->tail);
1187 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1188 struct ixgbe_rx_buffer *bi)
1190 struct page *page = bi->page;
1191 dma_addr_t dma = bi->dma;
1193 /* since we are recycling buffers we should seldom need to alloc */
1197 /* alloc new page for storage */
1198 if (likely(!page)) {
1199 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1200 bi->skb, ixgbe_rx_pg_order(rx_ring));
1201 if (unlikely(!page)) {
1202 rx_ring->rx_stats.alloc_rx_page_failed++;
1208 /* map page for use */
1209 dma = dma_map_page(rx_ring->dev, page, 0,
1210 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1213 * if mapping failed free memory back to system since
1214 * there isn't much point in holding memory we can't use
1216 if (dma_mapping_error(rx_ring->dev, dma)) {
1217 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1220 rx_ring->rx_stats.alloc_rx_page_failed++;
1225 bi->page_offset = 0;
1231 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1232 * @rx_ring: ring to place buffers on
1233 * @cleaned_count: number of buffers to replace
1235 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1237 union ixgbe_adv_rx_desc *rx_desc;
1238 struct ixgbe_rx_buffer *bi;
1239 u16 i = rx_ring->next_to_use;
1245 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1246 bi = &rx_ring->rx_buffer_info[i];
1247 i -= rx_ring->count;
1250 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1254 * Refresh the desc even if buffer_addrs didn't change
1255 * because each write-back erases this info.
1257 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1263 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1264 bi = rx_ring->rx_buffer_info;
1265 i -= rx_ring->count;
1268 /* clear the hdr_addr for the next_to_use descriptor */
1269 rx_desc->read.hdr_addr = 0;
1272 } while (cleaned_count);
1274 i += rx_ring->count;
1276 if (rx_ring->next_to_use != i)
1277 ixgbe_release_rx_desc(rx_ring, i);
1281 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1282 * @data: pointer to the start of the headers
1283 * @max_len: total length of section to find headers in
1285 * This function is meant to determine the length of headers that will
1286 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1287 * motivation of doing this is to only perform one pull for IPv4 TCP
1288 * packets so that we can do basic things like calculating the gso_size
1289 * based on the average data per packet.
1291 static unsigned int ixgbe_get_headlen(unsigned char *data,
1292 unsigned int max_len)
1295 unsigned char *network;
1298 struct vlan_hdr *vlan;
1301 struct ipv6hdr *ipv6;
1304 u8 nexthdr = 0; /* default to not TCP */
1307 /* this should never happen, but better safe than sorry */
1308 if (max_len < ETH_HLEN)
1311 /* initialize network frame pointer */
1314 /* set first protocol and move network header forward */
1315 protocol = hdr.eth->h_proto;
1316 hdr.network += ETH_HLEN;
1318 /* handle any vlan tag if present */
1319 if (protocol == __constant_htons(ETH_P_8021Q)) {
1320 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1323 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1324 hdr.network += VLAN_HLEN;
1327 /* handle L3 protocols */
1328 if (protocol == __constant_htons(ETH_P_IP)) {
1329 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1332 /* access ihl as a u8 to avoid unaligned access on ia64 */
1333 hlen = (hdr.network[0] & 0x0F) << 2;
1335 /* verify hlen meets minimum size requirements */
1336 if (hlen < sizeof(struct iphdr))
1337 return hdr.network - data;
1339 /* record next protocol */
1340 nexthdr = hdr.ipv4->protocol;
1341 hdr.network += hlen;
1342 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
1343 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1346 /* record next protocol */
1347 nexthdr = hdr.ipv6->nexthdr;
1348 hdr.network += sizeof(struct ipv6hdr);
1350 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1351 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1353 hdr.network += FCOE_HEADER_LEN;
1356 return hdr.network - data;
1359 /* finally sort out TCP/UDP */
1360 if (nexthdr == IPPROTO_TCP) {
1361 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1364 /* access doff as a u8 to avoid unaligned access on ia64 */
1365 hlen = (hdr.network[12] & 0xF0) >> 2;
1367 /* verify hlen meets minimum size requirements */
1368 if (hlen < sizeof(struct tcphdr))
1369 return hdr.network - data;
1371 hdr.network += hlen;
1372 } else if (nexthdr == IPPROTO_UDP) {
1373 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1376 hdr.network += sizeof(struct udphdr);
1380 * If everything has gone correctly hdr.network should be the
1381 * data section of the packet and will be the end of the header.
1382 * If not then it probably represents the end of the last recognized
1385 if ((hdr.network - data) < max_len)
1386 return hdr.network - data;
1391 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1392 struct sk_buff *skb)
1394 u16 hdr_len = skb_headlen(skb);
1396 /* set gso_size to avoid messing up TCP MSS */
1397 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1398 IXGBE_CB(skb)->append_cnt);
1401 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1402 struct sk_buff *skb)
1404 /* if append_cnt is 0 then frame is not RSC */
1405 if (!IXGBE_CB(skb)->append_cnt)
1408 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1409 rx_ring->rx_stats.rsc_flush++;
1411 ixgbe_set_rsc_gso_size(rx_ring, skb);
1413 /* gso_size is computed using append_cnt so always clear it last */
1414 IXGBE_CB(skb)->append_cnt = 0;
1418 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1419 * @rx_ring: rx descriptor ring packet is being transacted on
1420 * @rx_desc: pointer to the EOP Rx descriptor
1421 * @skb: pointer to current skb being populated
1423 * This function checks the ring, descriptor, and packet information in
1424 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1425 * other fields within the skb.
1427 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1428 union ixgbe_adv_rx_desc *rx_desc,
1429 struct sk_buff *skb)
1431 struct net_device *dev = rx_ring->netdev;
1433 ixgbe_update_rsc_stats(rx_ring, skb);
1435 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1437 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1439 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
1441 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
1442 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1443 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1444 __vlan_hwaccel_put_tag(skb, vid);
1447 skb_record_rx_queue(skb, rx_ring->queue_index);
1449 skb->protocol = eth_type_trans(skb, dev);
1452 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1453 struct sk_buff *skb)
1455 struct ixgbe_adapter *adapter = q_vector->adapter;
1457 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1458 napi_gro_receive(&q_vector->napi, skb);
1464 * ixgbe_is_non_eop - process handling of non-EOP buffers
1465 * @rx_ring: Rx ring being processed
1466 * @rx_desc: Rx descriptor for current buffer
1467 * @skb: Current socket buffer containing buffer in progress
1469 * This function updates next to clean. If the buffer is an EOP buffer
1470 * this function exits returning false, otherwise it will place the
1471 * sk_buff in the next buffer to be chained and return true indicating
1472 * that this is in fact a non-EOP buffer.
1474 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1475 union ixgbe_adv_rx_desc *rx_desc,
1476 struct sk_buff *skb)
1478 u32 ntc = rx_ring->next_to_clean + 1;
1480 /* fetch, update, and store next to clean */
1481 ntc = (ntc < rx_ring->count) ? ntc : 0;
1482 rx_ring->next_to_clean = ntc;
1484 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1486 /* update RSC append count if present */
1487 if (ring_is_rsc_enabled(rx_ring)) {
1488 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1489 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1491 if (unlikely(rsc_enabled)) {
1492 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1494 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1495 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1497 /* update ntc based on RSC value */
1498 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1499 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1500 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1504 /* if we are the last buffer then there is nothing else to do */
1505 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1508 /* place skb in next buffer to be received */
1509 rx_ring->rx_buffer_info[ntc].skb = skb;
1510 rx_ring->rx_stats.non_eop_descs++;
1516 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1517 * @rx_ring: rx descriptor ring packet is being transacted on
1518 * @skb: pointer to current skb being adjusted
1520 * This function is an ixgbe specific version of __pskb_pull_tail. The
1521 * main difference between this version and the original function is that
1522 * this function can make several assumptions about the state of things
1523 * that allow for significant optimizations versus the standard function.
1524 * As a result we can do things like drop a frag and maintain an accurate
1525 * truesize for the skb.
1527 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1528 struct sk_buff *skb)
1530 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1532 unsigned int pull_len;
1535 * it is valid to use page_address instead of kmap since we are
1536 * working with pages allocated out of the lomem pool per
1537 * alloc_page(GFP_ATOMIC)
1539 va = skb_frag_address(frag);
1542 * we need the header to contain the greater of either ETH_HLEN or
1543 * 60 bytes if the skb->len is less than 60 for skb_pad.
1545 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
1547 /* align pull length to size of long to optimize memcpy performance */
1548 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1550 /* update all of the pointers */
1551 skb_frag_size_sub(frag, pull_len);
1552 frag->page_offset += pull_len;
1553 skb->data_len -= pull_len;
1554 skb->tail += pull_len;
1558 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1559 * @rx_ring: rx descriptor ring packet is being transacted on
1560 * @skb: pointer to current skb being updated
1562 * This function provides a basic DMA sync up for the first fragment of an
1563 * skb. The reason for doing this is that the first fragment cannot be
1564 * unmapped until we have reached the end of packet descriptor for a buffer
1567 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1568 struct sk_buff *skb)
1570 /* if the page was released unmap it, else just sync our portion */
1571 if (unlikely(IXGBE_CB(skb)->page_released)) {
1572 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1573 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1574 IXGBE_CB(skb)->page_released = false;
1576 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1578 dma_sync_single_range_for_cpu(rx_ring->dev,
1581 ixgbe_rx_bufsz(rx_ring),
1584 IXGBE_CB(skb)->dma = 0;
1588 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1589 * @rx_ring: rx descriptor ring packet is being transacted on
1590 * @rx_desc: pointer to the EOP Rx descriptor
1591 * @skb: pointer to current skb being fixed
1593 * Check for corrupted packet headers caused by senders on the local L2
1594 * embedded NIC switch not setting up their Tx Descriptors right. These
1595 * should be very rare.
1597 * Also address the case where we are pulling data in on pages only
1598 * and as such no data is present in the skb header.
1600 * In addition if skb is not at least 60 bytes we need to pad it so that
1601 * it is large enough to qualify as a valid Ethernet frame.
1603 * Returns true if an error was encountered and skb was freed.
1605 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1606 union ixgbe_adv_rx_desc *rx_desc,
1607 struct sk_buff *skb)
1609 struct net_device *netdev = rx_ring->netdev;
1611 /* verify that the packet does not have any known errors */
1612 if (unlikely(ixgbe_test_staterr(rx_desc,
1613 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1614 !(netdev->features & NETIF_F_RXALL))) {
1615 dev_kfree_skb_any(skb);
1619 /* place header in linear portion of buffer */
1620 if (skb_is_nonlinear(skb))
1621 ixgbe_pull_tail(rx_ring, skb);
1624 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1625 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1629 /* if skb_pad returns an error the skb was freed */
1630 if (unlikely(skb->len < 60)) {
1631 int pad_len = 60 - skb->len;
1633 if (skb_pad(skb, pad_len))
1635 __skb_put(skb, pad_len);
1642 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1643 * @rx_ring: rx descriptor ring to store buffers on
1644 * @old_buff: donor buffer to have page reused
1646 * Synchronizes page for reuse by the adapter
1648 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1649 struct ixgbe_rx_buffer *old_buff)
1651 struct ixgbe_rx_buffer *new_buff;
1652 u16 nta = rx_ring->next_to_alloc;
1654 new_buff = &rx_ring->rx_buffer_info[nta];
1656 /* update, and store next to alloc */
1658 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1660 /* transfer page from old buffer to new buffer */
1661 new_buff->page = old_buff->page;
1662 new_buff->dma = old_buff->dma;
1663 new_buff->page_offset = old_buff->page_offset;
1665 /* sync the buffer for use by the device */
1666 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1667 new_buff->page_offset,
1668 ixgbe_rx_bufsz(rx_ring),
1673 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1674 * @rx_ring: rx descriptor ring to transact packets on
1675 * @rx_buffer: buffer containing page to add
1676 * @rx_desc: descriptor containing length of buffer written by hardware
1677 * @skb: sk_buff to place the data into
1679 * This function will add the data contained in rx_buffer->page to the skb.
1680 * This is done either through a direct copy if the data in the buffer is
1681 * less than the skb header size, otherwise it will just attach the page as
1682 * a frag to the skb.
1684 * The function will then update the page offset if necessary and return
1685 * true if the buffer can be reused by the adapter.
1687 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1688 struct ixgbe_rx_buffer *rx_buffer,
1689 union ixgbe_adv_rx_desc *rx_desc,
1690 struct sk_buff *skb)
1692 struct page *page = rx_buffer->page;
1693 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
1694 #if (PAGE_SIZE < 8192)
1695 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
1697 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1698 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1699 ixgbe_rx_bufsz(rx_ring);
1702 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1703 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1705 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1707 /* we can reuse buffer as-is, just make sure it is local */
1708 if (likely(page_to_nid(page) == numa_node_id()))
1711 /* this page cannot be reused so discard it */
1716 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1717 rx_buffer->page_offset, size, truesize);
1719 /* avoid re-using remote pages */
1720 if (unlikely(page_to_nid(page) != numa_node_id()))
1723 #if (PAGE_SIZE < 8192)
1724 /* if we are only owner of page we can reuse it */
1725 if (unlikely(page_count(page) != 1))
1728 /* flip page offset to other buffer */
1729 rx_buffer->page_offset ^= truesize;
1732 * since we are the only owner of the page and we need to
1733 * increment it, just set the value to 2 in order to avoid
1734 * an unecessary locked operation
1736 atomic_set(&page->_count, 2);
1738 /* move offset up to the next cache line */
1739 rx_buffer->page_offset += truesize;
1741 if (rx_buffer->page_offset > last_offset)
1744 /* bump ref count on page before it is given to the stack */
1751 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1752 union ixgbe_adv_rx_desc *rx_desc)
1754 struct ixgbe_rx_buffer *rx_buffer;
1755 struct sk_buff *skb;
1758 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1759 page = rx_buffer->page;
1762 skb = rx_buffer->skb;
1765 void *page_addr = page_address(page) +
1766 rx_buffer->page_offset;
1768 /* prefetch first cache line of first page */
1769 prefetch(page_addr);
1770 #if L1_CACHE_BYTES < 128
1771 prefetch(page_addr + L1_CACHE_BYTES);
1774 /* allocate a skb to store the frags */
1775 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1777 if (unlikely(!skb)) {
1778 rx_ring->rx_stats.alloc_rx_buff_failed++;
1783 * we will be copying header into skb->data in
1784 * pskb_may_pull so it is in our interest to prefetch
1785 * it now to avoid a possible cache miss
1787 prefetchw(skb->data);
1790 * Delay unmapping of the first packet. It carries the
1791 * header information, HW may still access the header
1792 * after the writeback. Only unmap it when EOP is
1795 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1798 IXGBE_CB(skb)->dma = rx_buffer->dma;
1800 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1801 ixgbe_dma_sync_frag(rx_ring, skb);
1804 /* we are reusing so sync this buffer for CPU use */
1805 dma_sync_single_range_for_cpu(rx_ring->dev,
1807 rx_buffer->page_offset,
1808 ixgbe_rx_bufsz(rx_ring),
1812 /* pull page into skb */
1813 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1814 /* hand second half of page back to the ring */
1815 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1816 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1817 /* the page has been released from the ring */
1818 IXGBE_CB(skb)->page_released = true;
1820 /* we are not reusing the buffer so unmap it */
1821 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1822 ixgbe_rx_pg_size(rx_ring),
1826 /* clear contents of buffer_info */
1827 rx_buffer->skb = NULL;
1829 rx_buffer->page = NULL;
1835 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1836 * @q_vector: structure containing interrupt and ring information
1837 * @rx_ring: rx descriptor ring to transact packets on
1838 * @budget: Total limit on number of packets to process
1840 * This function provides a "bounce buffer" approach to Rx interrupt
1841 * processing. The advantage to this is that on systems that have
1842 * expensive overhead for IOMMU access this provides a means of avoiding
1843 * it by maintaining the mapping of the page to the syste.
1845 * Returns true if all work is completed without reaching budget
1847 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1848 struct ixgbe_ring *rx_ring,
1851 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1853 struct ixgbe_adapter *adapter = q_vector->adapter;
1855 unsigned int mss = 0;
1856 #endif /* IXGBE_FCOE */
1857 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
1860 union ixgbe_adv_rx_desc *rx_desc;
1861 struct sk_buff *skb;
1863 /* return some buffers to hardware, one at a time is too slow */
1864 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1865 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1869 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
1871 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1875 * This memory barrier is needed to keep us from reading
1876 * any other fields out of the rx_desc until we know the
1877 * RXD_STAT_DD bit is set
1881 /* retrieve a buffer from the ring */
1882 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
1884 /* exit if we failed to retrieve a buffer */
1890 /* place incomplete frames back on ring for completion */
1891 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1894 /* verify the packet layout is correct */
1895 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1898 /* probably a little skewed due to removing CRC */
1899 total_rx_bytes += skb->len;
1901 /* populate checksum, timestamp, VLAN, and protocol */
1902 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1905 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1906 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
1907 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1908 /* include DDPed FCoE data */
1909 if (ddp_bytes > 0) {
1911 mss = rx_ring->netdev->mtu -
1912 sizeof(struct fcoe_hdr) -
1913 sizeof(struct fc_frame_header) -
1914 sizeof(struct fcoe_crc_eof);
1918 total_rx_bytes += ddp_bytes;
1919 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
1923 dev_kfree_skb_any(skb);
1928 #endif /* IXGBE_FCOE */
1929 ixgbe_rx_skb(q_vector, skb);
1931 /* update budget accounting */
1933 } while (likely(total_rx_packets < budget));
1935 u64_stats_update_begin(&rx_ring->syncp);
1936 rx_ring->stats.packets += total_rx_packets;
1937 rx_ring->stats.bytes += total_rx_bytes;
1938 u64_stats_update_end(&rx_ring->syncp);
1939 q_vector->rx.total_packets += total_rx_packets;
1940 q_vector->rx.total_bytes += total_rx_bytes;
1943 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1945 return (total_rx_packets < budget);
1949 * ixgbe_configure_msix - Configure MSI-X hardware
1950 * @adapter: board private structure
1952 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1955 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1957 struct ixgbe_q_vector *q_vector;
1961 /* Populate MSIX to EITR Select */
1962 if (adapter->num_vfs > 32) {
1963 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1964 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1968 * Populate the IVAR table and set the ITR values to the
1969 * corresponding register.
1971 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
1972 struct ixgbe_ring *ring;
1973 q_vector = adapter->q_vector[v_idx];
1975 ixgbe_for_each_ring(ring, q_vector->rx)
1976 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1978 ixgbe_for_each_ring(ring, q_vector->tx)
1979 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1981 ixgbe_write_eitr(q_vector);
1984 switch (adapter->hw.mac.type) {
1985 case ixgbe_mac_82598EB:
1986 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1989 case ixgbe_mac_82599EB:
1990 case ixgbe_mac_X540:
1991 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1996 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1998 /* set up to autoclear timer, and the vectors */
1999 mask = IXGBE_EIMS_ENABLE_MASK;
2000 mask &= ~(IXGBE_EIMS_OTHER |
2001 IXGBE_EIMS_MAILBOX |
2004 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2007 enum latency_range {
2011 latency_invalid = 255
2015 * ixgbe_update_itr - update the dynamic ITR value based on statistics
2016 * @q_vector: structure containing interrupt and ring information
2017 * @ring_container: structure containing ring performance data
2019 * Stores a new ITR value based on packets and byte
2020 * counts during the last interrupt. The advantage of per interrupt
2021 * computation is faster updates and more accurate ITR for the current
2022 * traffic pattern. Constants in this function were computed
2023 * based on theoretical maximum wire speed and thresholds were set based
2024 * on testing data as well as attempting to minimize response time
2025 * while increasing bulk throughput.
2026 * this functionality is controlled by the InterruptThrottleRate module
2027 * parameter (see ixgbe_param.c)
2029 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2030 struct ixgbe_ring_container *ring_container)
2032 int bytes = ring_container->total_bytes;
2033 int packets = ring_container->total_packets;
2036 u8 itr_setting = ring_container->itr;
2041 /* simple throttlerate management
2042 * 0-10MB/s lowest (100000 ints/s)
2043 * 10-20MB/s low (20000 ints/s)
2044 * 20-1249MB/s bulk (8000 ints/s)
2046 /* what was last interrupt timeslice? */
2047 timepassed_us = q_vector->itr >> 2;
2048 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2050 switch (itr_setting) {
2051 case lowest_latency:
2052 if (bytes_perint > 10)
2053 itr_setting = low_latency;
2056 if (bytes_perint > 20)
2057 itr_setting = bulk_latency;
2058 else if (bytes_perint <= 10)
2059 itr_setting = lowest_latency;
2062 if (bytes_perint <= 20)
2063 itr_setting = low_latency;
2067 /* clear work counters since we have the values we need */
2068 ring_container->total_bytes = 0;
2069 ring_container->total_packets = 0;
2071 /* write updated itr to ring container */
2072 ring_container->itr = itr_setting;
2076 * ixgbe_write_eitr - write EITR register in hardware specific way
2077 * @q_vector: structure containing interrupt and ring information
2079 * This function is made to be called by ethtool and by the driver
2080 * when it needs to update EITR registers at runtime. Hardware
2081 * specific quirks/differences are taken care of here.
2083 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2085 struct ixgbe_adapter *adapter = q_vector->adapter;
2086 struct ixgbe_hw *hw = &adapter->hw;
2087 int v_idx = q_vector->v_idx;
2088 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2090 switch (adapter->hw.mac.type) {
2091 case ixgbe_mac_82598EB:
2092 /* must write high and low 16 bits to reset counter */
2093 itr_reg |= (itr_reg << 16);
2095 case ixgbe_mac_82599EB:
2096 case ixgbe_mac_X540:
2098 * set the WDIS bit to not clear the timer bits and cause an
2099 * immediate assertion of the interrupt
2101 itr_reg |= IXGBE_EITR_CNT_WDIS;
2106 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2109 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2111 u32 new_itr = q_vector->itr;
2114 ixgbe_update_itr(q_vector, &q_vector->tx);
2115 ixgbe_update_itr(q_vector, &q_vector->rx);
2117 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2119 switch (current_itr) {
2120 /* counts and packets in update_itr are dependent on these numbers */
2121 case lowest_latency:
2122 new_itr = IXGBE_100K_ITR;
2125 new_itr = IXGBE_20K_ITR;
2128 new_itr = IXGBE_8K_ITR;
2134 if (new_itr != q_vector->itr) {
2135 /* do an exponential smoothing */
2136 new_itr = (10 * new_itr * q_vector->itr) /
2137 ((9 * new_itr) + q_vector->itr);
2139 /* save the algorithm value here */
2140 q_vector->itr = new_itr;
2142 ixgbe_write_eitr(q_vector);
2147 * ixgbe_check_overtemp_subtask - check for over temperature
2148 * @adapter: pointer to adapter
2150 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2152 struct ixgbe_hw *hw = &adapter->hw;
2153 u32 eicr = adapter->interrupt_event;
2155 if (test_bit(__IXGBE_DOWN, &adapter->state))
2158 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2159 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2162 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2164 switch (hw->device_id) {
2165 case IXGBE_DEV_ID_82599_T3_LOM:
2167 * Since the warning interrupt is for both ports
2168 * we don't have to check if:
2169 * - This interrupt wasn't for our port.
2170 * - We may have missed the interrupt so always have to
2171 * check if we got a LSC
2173 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2174 !(eicr & IXGBE_EICR_LSC))
2177 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2179 bool link_up = false;
2181 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2187 /* Check if this is not due to overtemp */
2188 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2193 if (!(eicr & IXGBE_EICR_GPI_SDP0))
2198 "Network adapter has been stopped because it has over heated. "
2199 "Restart the computer. If the problem persists, "
2200 "power off the system and replace the adapter\n");
2202 adapter->interrupt_event = 0;
2205 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2207 struct ixgbe_hw *hw = &adapter->hw;
2209 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2210 (eicr & IXGBE_EICR_GPI_SDP1)) {
2211 e_crit(probe, "Fan has stopped, replace the adapter\n");
2212 /* write to clear the interrupt */
2213 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2217 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2219 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2222 switch (adapter->hw.mac.type) {
2223 case ixgbe_mac_82599EB:
2225 * Need to check link state so complete overtemp check
2228 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2229 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2230 adapter->interrupt_event = eicr;
2231 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2232 ixgbe_service_event_schedule(adapter);
2236 case ixgbe_mac_X540:
2237 if (!(eicr & IXGBE_EICR_TS))
2245 "Network adapter has been stopped because it has over heated. "
2246 "Restart the computer. If the problem persists, "
2247 "power off the system and replace the adapter\n");
2250 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2252 struct ixgbe_hw *hw = &adapter->hw;
2254 if (eicr & IXGBE_EICR_GPI_SDP2) {
2255 /* Clear the interrupt */
2256 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
2257 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2258 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2259 ixgbe_service_event_schedule(adapter);
2263 if (eicr & IXGBE_EICR_GPI_SDP1) {
2264 /* Clear the interrupt */
2265 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2266 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2267 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2268 ixgbe_service_event_schedule(adapter);
2273 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2275 struct ixgbe_hw *hw = &adapter->hw;
2278 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2279 adapter->link_check_timeout = jiffies;
2280 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2281 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2282 IXGBE_WRITE_FLUSH(hw);
2283 ixgbe_service_event_schedule(adapter);
2287 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2291 struct ixgbe_hw *hw = &adapter->hw;
2293 switch (hw->mac.type) {
2294 case ixgbe_mac_82598EB:
2295 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2296 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2298 case ixgbe_mac_82599EB:
2299 case ixgbe_mac_X540:
2300 mask = (qmask & 0xFFFFFFFF);
2302 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2303 mask = (qmask >> 32);
2305 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2310 /* skip the flush */
2313 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2317 struct ixgbe_hw *hw = &adapter->hw;
2319 switch (hw->mac.type) {
2320 case ixgbe_mac_82598EB:
2321 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2322 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2324 case ixgbe_mac_82599EB:
2325 case ixgbe_mac_X540:
2326 mask = (qmask & 0xFFFFFFFF);
2328 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2329 mask = (qmask >> 32);
2331 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2336 /* skip the flush */
2340 * ixgbe_irq_enable - Enable default interrupt generation settings
2341 * @adapter: board private structure
2343 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2346 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2348 /* don't reenable LSC while waiting for link */
2349 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2350 mask &= ~IXGBE_EIMS_LSC;
2352 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2353 switch (adapter->hw.mac.type) {
2354 case ixgbe_mac_82599EB:
2355 mask |= IXGBE_EIMS_GPI_SDP0;
2357 case ixgbe_mac_X540:
2358 mask |= IXGBE_EIMS_TS;
2363 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2364 mask |= IXGBE_EIMS_GPI_SDP1;
2365 switch (adapter->hw.mac.type) {
2366 case ixgbe_mac_82599EB:
2367 mask |= IXGBE_EIMS_GPI_SDP1;
2368 mask |= IXGBE_EIMS_GPI_SDP2;
2369 case ixgbe_mac_X540:
2370 mask |= IXGBE_EIMS_ECC;
2371 mask |= IXGBE_EIMS_MAILBOX;
2377 if (adapter->hw.mac.type == ixgbe_mac_X540)
2378 mask |= IXGBE_EIMS_TIMESYNC;
2380 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2381 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2382 mask |= IXGBE_EIMS_FLOW_DIR;
2384 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2386 ixgbe_irq_enable_queues(adapter, ~0);
2388 IXGBE_WRITE_FLUSH(&adapter->hw);
2391 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2393 struct ixgbe_adapter *adapter = data;
2394 struct ixgbe_hw *hw = &adapter->hw;
2398 * Workaround for Silicon errata. Use clear-by-write instead
2399 * of clear-by-read. Reading with EICS will return the
2400 * interrupt causes without clearing, which later be done
2401 * with the write to EICR.
2403 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2404 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2406 if (eicr & IXGBE_EICR_LSC)
2407 ixgbe_check_lsc(adapter);
2409 if (eicr & IXGBE_EICR_MAILBOX)
2410 ixgbe_msg_task(adapter);
2412 switch (hw->mac.type) {
2413 case ixgbe_mac_82599EB:
2414 case ixgbe_mac_X540:
2415 if (eicr & IXGBE_EICR_ECC)
2416 e_info(link, "Received unrecoverable ECC Err, please "
2418 /* Handle Flow Director Full threshold interrupt */
2419 if (eicr & IXGBE_EICR_FLOW_DIR) {
2420 int reinit_count = 0;
2422 for (i = 0; i < adapter->num_tx_queues; i++) {
2423 struct ixgbe_ring *ring = adapter->tx_ring[i];
2424 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2429 /* no more flow director interrupts until after init */
2430 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2431 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2432 ixgbe_service_event_schedule(adapter);
2435 ixgbe_check_sfp_event(adapter, eicr);
2436 ixgbe_check_overtemp_event(adapter, eicr);
2442 ixgbe_check_fan_failure(adapter, eicr);
2444 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2445 ixgbe_ptp_check_pps_event(adapter, eicr);
2447 /* re-enable the original interrupt state, no lsc, no queues */
2448 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2449 ixgbe_irq_enable(adapter, false, false);
2454 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2456 struct ixgbe_q_vector *q_vector = data;
2458 /* EIAM disabled interrupts (on this vector) for us */
2460 if (q_vector->rx.ring || q_vector->tx.ring)
2461 napi_schedule(&q_vector->napi);
2467 * ixgbe_poll - NAPI Rx polling callback
2468 * @napi: structure for representing this polling device
2469 * @budget: how many packets driver is allowed to clean
2471 * This function is used for legacy and MSI, NAPI mode
2473 int ixgbe_poll(struct napi_struct *napi, int budget)
2475 struct ixgbe_q_vector *q_vector =
2476 container_of(napi, struct ixgbe_q_vector, napi);
2477 struct ixgbe_adapter *adapter = q_vector->adapter;
2478 struct ixgbe_ring *ring;
2479 int per_ring_budget;
2480 bool clean_complete = true;
2482 #ifdef CONFIG_IXGBE_DCA
2483 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2484 ixgbe_update_dca(q_vector);
2487 ixgbe_for_each_ring(ring, q_vector->tx)
2488 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2490 /* attempt to distribute budget to each queue fairly, but don't allow
2491 * the budget to go below 1 because we'll exit polling */
2492 if (q_vector->rx.count > 1)
2493 per_ring_budget = max(budget/q_vector->rx.count, 1);
2495 per_ring_budget = budget;
2497 ixgbe_for_each_ring(ring, q_vector->rx)
2498 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2501 /* If all work not completed, return budget and keep polling */
2502 if (!clean_complete)
2505 /* all work done, exit the polling mode */
2506 napi_complete(napi);
2507 if (adapter->rx_itr_setting & 1)
2508 ixgbe_set_itr(q_vector);
2509 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2510 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2516 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2517 * @adapter: board private structure
2519 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2520 * interrupts from the kernel.
2522 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2524 struct net_device *netdev = adapter->netdev;
2528 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2529 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2530 struct msix_entry *entry = &adapter->msix_entries[vector];
2532 if (q_vector->tx.ring && q_vector->rx.ring) {
2533 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2534 "%s-%s-%d", netdev->name, "TxRx", ri++);
2536 } else if (q_vector->rx.ring) {
2537 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2538 "%s-%s-%d", netdev->name, "rx", ri++);
2539 } else if (q_vector->tx.ring) {
2540 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2541 "%s-%s-%d", netdev->name, "tx", ti++);
2543 /* skip this unused q_vector */
2546 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2547 q_vector->name, q_vector);
2549 e_err(probe, "request_irq failed for MSIX interrupt "
2550 "Error: %d\n", err);
2551 goto free_queue_irqs;
2553 /* If Flow Director is enabled, set interrupt affinity */
2554 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2555 /* assign the mask for this irq */
2556 irq_set_affinity_hint(entry->vector,
2557 &q_vector->affinity_mask);
2561 err = request_irq(adapter->msix_entries[vector].vector,
2562 ixgbe_msix_other, 0, netdev->name, adapter);
2564 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2565 goto free_queue_irqs;
2573 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2575 free_irq(adapter->msix_entries[vector].vector,
2576 adapter->q_vector[vector]);
2578 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2579 pci_disable_msix(adapter->pdev);
2580 kfree(adapter->msix_entries);
2581 adapter->msix_entries = NULL;
2586 * ixgbe_intr - legacy mode Interrupt Handler
2587 * @irq: interrupt number
2588 * @data: pointer to a network interface device structure
2590 static irqreturn_t ixgbe_intr(int irq, void *data)
2592 struct ixgbe_adapter *adapter = data;
2593 struct ixgbe_hw *hw = &adapter->hw;
2594 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2598 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2599 * before the read of EICR.
2601 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2603 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2604 * therefore no explicit interrupt disable is necessary */
2605 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2608 * shared interrupt alert!
2609 * make sure interrupts are enabled because the read will
2610 * have disabled interrupts due to EIAM
2611 * finish the workaround of silicon errata on 82598. Unmask
2612 * the interrupt that we masked before the EICR read.
2614 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2615 ixgbe_irq_enable(adapter, true, true);
2616 return IRQ_NONE; /* Not our interrupt */
2619 if (eicr & IXGBE_EICR_LSC)
2620 ixgbe_check_lsc(adapter);
2622 switch (hw->mac.type) {
2623 case ixgbe_mac_82599EB:
2624 ixgbe_check_sfp_event(adapter, eicr);
2626 case ixgbe_mac_X540:
2627 if (eicr & IXGBE_EICR_ECC)
2628 e_info(link, "Received unrecoverable ECC err, please "
2630 ixgbe_check_overtemp_event(adapter, eicr);
2636 ixgbe_check_fan_failure(adapter, eicr);
2637 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2638 ixgbe_ptp_check_pps_event(adapter, eicr);
2640 /* would disable interrupts here but EIAM disabled it */
2641 napi_schedule(&q_vector->napi);
2644 * re-enable link(maybe) and non-queue interrupts, no flush.
2645 * ixgbe_poll will re-enable the queue interrupts
2647 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2648 ixgbe_irq_enable(adapter, false, false);
2654 * ixgbe_request_irq - initialize interrupts
2655 * @adapter: board private structure
2657 * Attempts to configure interrupts using the best available
2658 * capabilities of the hardware and kernel.
2660 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2662 struct net_device *netdev = adapter->netdev;
2665 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2666 err = ixgbe_request_msix_irqs(adapter);
2667 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2668 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2669 netdev->name, adapter);
2671 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2672 netdev->name, adapter);
2675 e_err(probe, "request_irq failed, Error %d\n", err);
2680 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2684 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2685 free_irq(adapter->pdev->irq, adapter);
2689 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2690 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2691 struct msix_entry *entry = &adapter->msix_entries[vector];
2693 /* free only the irqs that were actually requested */
2694 if (!q_vector->rx.ring && !q_vector->tx.ring)
2697 /* clear the affinity_mask in the IRQ descriptor */
2698 irq_set_affinity_hint(entry->vector, NULL);
2700 free_irq(entry->vector, q_vector);
2703 free_irq(adapter->msix_entries[vector++].vector, adapter);
2707 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2708 * @adapter: board private structure
2710 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2712 switch (adapter->hw.mac.type) {
2713 case ixgbe_mac_82598EB:
2714 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2716 case ixgbe_mac_82599EB:
2717 case ixgbe_mac_X540:
2718 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2719 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2720 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2725 IXGBE_WRITE_FLUSH(&adapter->hw);
2726 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2729 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2730 synchronize_irq(adapter->msix_entries[vector].vector);
2732 synchronize_irq(adapter->msix_entries[vector++].vector);
2734 synchronize_irq(adapter->pdev->irq);
2739 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2742 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2744 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2746 ixgbe_write_eitr(q_vector);
2748 ixgbe_set_ivar(adapter, 0, 0, 0);
2749 ixgbe_set_ivar(adapter, 1, 0, 0);
2751 e_info(hw, "Legacy interrupt IVAR setup done\n");
2755 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2756 * @adapter: board private structure
2757 * @ring: structure containing ring specific data
2759 * Configure the Tx descriptor ring after a reset.
2761 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2762 struct ixgbe_ring *ring)
2764 struct ixgbe_hw *hw = &adapter->hw;
2765 u64 tdba = ring->dma;
2767 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2768 u8 reg_idx = ring->reg_idx;
2770 /* disable queue to avoid issues while updating state */
2771 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2772 IXGBE_WRITE_FLUSH(hw);
2774 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2775 (tdba & DMA_BIT_MASK(32)));
2776 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2777 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2778 ring->count * sizeof(union ixgbe_adv_tx_desc));
2779 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2780 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2781 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2784 * set WTHRESH to encourage burst writeback, it should not be set
2785 * higher than 1 when ITR is 0 as it could cause false TX hangs
2787 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2788 * to or less than the number of on chip descriptors, which is
2791 if (!ring->q_vector || (ring->q_vector->itr < 8))
2792 txdctl |= (1 << 16); /* WTHRESH = 1 */
2794 txdctl |= (8 << 16); /* WTHRESH = 8 */
2797 * Setting PTHRESH to 32 both improves performance
2798 * and avoids a TX hang with DFP enabled
2800 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2801 32; /* PTHRESH = 32 */
2803 /* reinitialize flowdirector state */
2804 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2805 ring->atr_sample_rate = adapter->atr_sample_rate;
2806 ring->atr_count = 0;
2807 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2809 ring->atr_sample_rate = 0;
2812 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2815 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2817 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2818 if (hw->mac.type == ixgbe_mac_82598EB &&
2819 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2822 /* poll to verify queue is enabled */
2824 usleep_range(1000, 2000);
2825 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2826 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2828 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2831 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2833 struct ixgbe_hw *hw = &adapter->hw;
2835 u8 tcs = netdev_get_num_tc(adapter->netdev);
2837 if (hw->mac.type == ixgbe_mac_82598EB)
2840 /* disable the arbiter while setting MTQC */
2841 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2842 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2843 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2845 /* set transmit pool layout */
2846 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2847 mtqc = IXGBE_MTQC_VT_ENA;
2849 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2851 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2852 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
2853 mtqc |= IXGBE_MTQC_32VF;
2855 mtqc |= IXGBE_MTQC_64VF;
2858 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2860 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2862 mtqc = IXGBE_MTQC_64Q_1PB;
2865 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
2867 /* Enable Security TX Buffer IFG for multiple pb */
2869 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2870 sectx |= IXGBE_SECTX_DCB;
2871 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
2874 /* re-enable the arbiter */
2875 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2876 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2880 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2881 * @adapter: board private structure
2883 * Configure the Tx unit of the MAC after a reset.
2885 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2887 struct ixgbe_hw *hw = &adapter->hw;
2891 ixgbe_setup_mtqc(adapter);
2893 if (hw->mac.type != ixgbe_mac_82598EB) {
2894 /* DMATXCTL.EN must be before Tx queues are enabled */
2895 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2896 dmatxctl |= IXGBE_DMATXCTL_TE;
2897 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2900 /* Setup the HW Tx Head and Tail descriptor pointers */
2901 for (i = 0; i < adapter->num_tx_queues; i++)
2902 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2905 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
2906 struct ixgbe_ring *ring)
2908 struct ixgbe_hw *hw = &adapter->hw;
2909 u8 reg_idx = ring->reg_idx;
2910 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2912 srrctl |= IXGBE_SRRCTL_DROP_EN;
2914 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2917 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
2918 struct ixgbe_ring *ring)
2920 struct ixgbe_hw *hw = &adapter->hw;
2921 u8 reg_idx = ring->reg_idx;
2922 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2924 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
2926 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2929 #ifdef CONFIG_IXGBE_DCB
2930 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2932 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2936 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
2938 if (adapter->ixgbe_ieee_pfc)
2939 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
2942 * We should set the drop enable bit if:
2945 * Number of Rx queues > 1 and flow control is disabled
2947 * This allows us to avoid head of line blocking for security
2948 * and performance reasons.
2950 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
2951 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
2952 for (i = 0; i < adapter->num_rx_queues; i++)
2953 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
2955 for (i = 0; i < adapter->num_rx_queues; i++)
2956 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
2960 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2962 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2963 struct ixgbe_ring *rx_ring)
2965 struct ixgbe_hw *hw = &adapter->hw;
2967 u8 reg_idx = rx_ring->reg_idx;
2969 if (hw->mac.type == ixgbe_mac_82598EB) {
2970 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
2973 * if VMDq is not active we must program one srrctl register
2974 * per RSS queue since we have enabled RDRXCTL.MVMEN
2979 /* configure header buffer length, needed for RSC */
2980 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
2982 /* configure the packet buffer length */
2983 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2985 /* configure descriptor type */
2986 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2988 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2991 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2993 struct ixgbe_hw *hw = &adapter->hw;
2994 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2995 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2996 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2997 u32 mrqc = 0, reta = 0;
3000 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3003 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3004 * make full use of any rings they may have. We will use the
3005 * PSRTYPE register to control how many rings we use within the PF.
3007 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3010 /* Fill out hash function seeds */
3011 for (i = 0; i < 10; i++)
3012 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3014 /* Fill out redirection table */
3015 for (i = 0, j = 0; i < 128; i++, j++) {
3018 /* reta = 4-byte sliding window of
3019 * 0x00..(indices-1)(indices-1)00..etc. */
3020 reta = (reta << 8) | (j * 0x11);
3022 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3025 /* Disable indicating checksum in descriptor, enables RSS hash */
3026 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3027 rxcsum |= IXGBE_RXCSUM_PCSD;
3028 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3030 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3031 if (adapter->ring_feature[RING_F_RSS].mask)
3032 mrqc = IXGBE_MRQC_RSSEN;
3034 u8 tcs = netdev_get_num_tc(adapter->netdev);
3036 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3038 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3040 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3041 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3042 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3044 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3047 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3049 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3051 mrqc = IXGBE_MRQC_RSSEN;
3055 /* Perform hash on these packet types */
3056 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3057 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3058 IXGBE_MRQC_RSS_FIELD_IPV6 |
3059 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3061 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3062 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3063 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3064 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3066 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3070 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3071 * @adapter: address of board private structure
3072 * @index: index of ring to set
3074 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3075 struct ixgbe_ring *ring)
3077 struct ixgbe_hw *hw = &adapter->hw;
3079 u8 reg_idx = ring->reg_idx;
3081 if (!ring_is_rsc_enabled(ring))
3084 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3085 rscctrl |= IXGBE_RSCCTL_RSCEN;
3087 * we must limit the number of descriptors so that the
3088 * total size of max desc * buf_len is not greater
3091 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3092 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3095 #define IXGBE_MAX_RX_DESC_POLL 10
3096 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3097 struct ixgbe_ring *ring)
3099 struct ixgbe_hw *hw = &adapter->hw;
3100 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3102 u8 reg_idx = ring->reg_idx;
3104 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3105 if (hw->mac.type == ixgbe_mac_82598EB &&
3106 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3110 usleep_range(1000, 2000);
3111 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3112 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3115 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3116 "the polling period\n", reg_idx);
3120 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3121 struct ixgbe_ring *ring)
3123 struct ixgbe_hw *hw = &adapter->hw;
3124 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3126 u8 reg_idx = ring->reg_idx;
3128 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3129 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3131 /* write value back with RXDCTL.ENABLE bit cleared */
3132 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3134 if (hw->mac.type == ixgbe_mac_82598EB &&
3135 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3138 /* the hardware may take up to 100us to really disable the rx queue */
3141 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3142 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3145 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3146 "the polling period\n", reg_idx);
3150 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3151 struct ixgbe_ring *ring)
3153 struct ixgbe_hw *hw = &adapter->hw;
3154 u64 rdba = ring->dma;
3156 u8 reg_idx = ring->reg_idx;
3158 /* disable queue to avoid issues while updating state */
3159 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3160 ixgbe_disable_rx_queue(adapter, ring);
3162 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3163 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3164 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3165 ring->count * sizeof(union ixgbe_adv_rx_desc));
3166 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3167 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3168 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3170 ixgbe_configure_srrctl(adapter, ring);
3171 ixgbe_configure_rscctl(adapter, ring);
3173 /* If operating in IOV mode set RLPML for X540 */
3174 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3175 hw->mac.type == ixgbe_mac_X540) {
3176 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3177 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3178 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3181 if (hw->mac.type == ixgbe_mac_82598EB) {
3183 * enable cache line friendly hardware writes:
3184 * PTHRESH=32 descriptors (half the internal cache),
3185 * this also removes ugly rx_no_buffer_count increment
3186 * HTHRESH=4 descriptors (to minimize latency on fetch)
3187 * WTHRESH=8 burst writeback up to two cache lines
3189 rxdctl &= ~0x3FFFFF;
3193 /* enable receive descriptor ring */
3194 rxdctl |= IXGBE_RXDCTL_ENABLE;
3195 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3197 ixgbe_rx_desc_queue_enable(adapter, ring);
3198 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3201 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3203 struct ixgbe_hw *hw = &adapter->hw;
3204 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
3207 /* PSRTYPE must be initialized in non 82598 adapters */
3208 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3209 IXGBE_PSRTYPE_UDPHDR |
3210 IXGBE_PSRTYPE_IPV4HDR |
3211 IXGBE_PSRTYPE_L2HDR |
3212 IXGBE_PSRTYPE_IPV6HDR;
3214 if (hw->mac.type == ixgbe_mac_82598EB)
3222 for (p = 0; p < adapter->num_rx_pools; p++)
3223 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(p)),
3227 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3229 struct ixgbe_hw *hw = &adapter->hw;
3230 u32 reg_offset, vf_shift;
3231 u32 gcr_ext, vmdctl;
3234 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3237 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3238 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3239 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
3240 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
3241 vmdctl |= IXGBE_VT_CTL_REPLEN;
3242 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
3244 vf_shift = VMDQ_P(0) % 32;
3245 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
3247 /* Enable only the PF's pool for Tx/Rx */
3248 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3249 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3250 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3251 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
3253 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3254 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
3257 * Set up VF register offsets for selected VT Mode,
3258 * i.e. 32 or 64 VFs for SR-IOV
3260 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3261 case IXGBE_82599_VMDQ_8Q_MASK:
3262 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3264 case IXGBE_82599_VMDQ_4Q_MASK:
3265 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3268 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3272 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3275 /* Enable MAC Anti-Spoofing */
3276 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3278 /* For VFs that have spoof checking turned off */
3279 for (i = 0; i < adapter->num_vfs; i++) {
3280 if (!adapter->vfinfo[i].spoofchk_enabled)
3281 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3285 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3287 struct ixgbe_hw *hw = &adapter->hw;
3288 struct net_device *netdev = adapter->netdev;
3289 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3290 struct ixgbe_ring *rx_ring;
3295 /* adjust max frame to be able to do baby jumbo for FCoE */
3296 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3297 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3298 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3300 #endif /* IXGBE_FCOE */
3302 /* adjust max frame to be at least the size of a standard frame */
3303 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3304 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3306 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3307 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3308 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3309 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3311 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3314 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3315 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3316 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3317 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3320 * Setup the HW Rx Head and Tail Descriptor Pointers and
3321 * the Base and Length of the Rx Descriptor Ring
3323 for (i = 0; i < adapter->num_rx_queues; i++) {
3324 rx_ring = adapter->rx_ring[i];
3325 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3326 set_ring_rsc_enabled(rx_ring);
3328 clear_ring_rsc_enabled(rx_ring);
3332 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3334 struct ixgbe_hw *hw = &adapter->hw;
3335 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3337 switch (hw->mac.type) {
3338 case ixgbe_mac_82598EB:
3340 * For VMDq support of different descriptor types or
3341 * buffer sizes through the use of multiple SRRCTL
3342 * registers, RDRXCTL.MVMEN must be set to 1
3344 * also, the manual doesn't mention it clearly but DCA hints
3345 * will only use queue 0's tags unless this bit is set. Side
3346 * effects of setting this bit are only that SRRCTL must be
3347 * fully programmed [0..15]
3349 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3351 case ixgbe_mac_82599EB:
3352 case ixgbe_mac_X540:
3353 /* Disable RSC for ACK packets */
3354 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3355 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3356 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3357 /* hardware requires some bits to be set by default */
3358 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3359 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3362 /* We should do nothing since we don't know this hardware */
3366 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3370 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3371 * @adapter: board private structure
3373 * Configure the Rx unit of the MAC after a reset.
3375 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3377 struct ixgbe_hw *hw = &adapter->hw;
3381 /* disable receives while setting up the descriptors */
3382 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3383 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3385 ixgbe_setup_psrtype(adapter);
3386 ixgbe_setup_rdrxctl(adapter);
3388 /* Program registers for the distribution of queues */
3389 ixgbe_setup_mrqc(adapter);
3391 /* set_rx_buffer_len must be called before ring initialization */
3392 ixgbe_set_rx_buffer_len(adapter);
3395 * Setup the HW Rx Head and Tail Descriptor Pointers and
3396 * the Base and Length of the Rx Descriptor Ring
3398 for (i = 0; i < adapter->num_rx_queues; i++)
3399 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3401 /* disable drop enable for 82598 parts */
3402 if (hw->mac.type == ixgbe_mac_82598EB)
3403 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3405 /* enable all receives */
3406 rxctrl |= IXGBE_RXCTRL_RXEN;
3407 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3410 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3412 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3413 struct ixgbe_hw *hw = &adapter->hw;
3415 /* add VID to filter table */
3416 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
3417 set_bit(vid, adapter->active_vlans);
3422 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3424 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3425 struct ixgbe_hw *hw = &adapter->hw;
3427 /* remove VID from filter table */
3428 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
3429 clear_bit(vid, adapter->active_vlans);
3435 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3436 * @adapter: driver data
3438 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3440 struct ixgbe_hw *hw = &adapter->hw;
3443 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3444 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3445 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3449 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3450 * @adapter: driver data
3452 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3454 struct ixgbe_hw *hw = &adapter->hw;
3457 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3458 vlnctrl |= IXGBE_VLNCTRL_VFE;
3459 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3460 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3464 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3465 * @adapter: driver data
3467 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3469 struct ixgbe_hw *hw = &adapter->hw;
3473 switch (hw->mac.type) {
3474 case ixgbe_mac_82598EB:
3475 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3476 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3477 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3479 case ixgbe_mac_82599EB:
3480 case ixgbe_mac_X540:
3481 for (i = 0; i < adapter->num_rx_queues; i++) {
3482 j = adapter->rx_ring[i]->reg_idx;
3483 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3484 vlnctrl &= ~IXGBE_RXDCTL_VME;
3485 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3494 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3495 * @adapter: driver data
3497 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3499 struct ixgbe_hw *hw = &adapter->hw;
3503 switch (hw->mac.type) {
3504 case ixgbe_mac_82598EB:
3505 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3506 vlnctrl |= IXGBE_VLNCTRL_VME;
3507 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3509 case ixgbe_mac_82599EB:
3510 case ixgbe_mac_X540:
3511 for (i = 0; i < adapter->num_rx_queues; i++) {
3512 j = adapter->rx_ring[i]->reg_idx;
3513 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3514 vlnctrl |= IXGBE_RXDCTL_VME;
3515 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3523 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3527 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3529 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3530 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3534 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3535 * @netdev: network interface device structure
3537 * Writes unicast address list to the RAR table.
3538 * Returns: -ENOMEM on failure/insufficient address space
3539 * 0 on no addresses written
3540 * X on writing X addresses to the RAR table
3542 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3544 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3545 struct ixgbe_hw *hw = &adapter->hw;
3546 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
3549 /* In SR-IOV mode significantly less RAR entries are available */
3550 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3551 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3553 /* return ENOMEM indicating insufficient memory for addresses */
3554 if (netdev_uc_count(netdev) > rar_entries)
3557 if (!netdev_uc_empty(netdev)) {
3558 struct netdev_hw_addr *ha;
3559 /* return error if we do not support writing to RAR table */
3560 if (!hw->mac.ops.set_rar)
3563 netdev_for_each_uc_addr(ha, netdev) {
3566 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3567 VMDQ_P(0), IXGBE_RAH_AV);
3571 /* write the addresses in reverse order to avoid write combining */
3572 for (; rar_entries > 0 ; rar_entries--)
3573 hw->mac.ops.clear_rar(hw, rar_entries);
3579 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3580 * @netdev: network interface device structure
3582 * The set_rx_method entry point is called whenever the unicast/multicast
3583 * address list or the network interface flags are updated. This routine is
3584 * responsible for configuring the hardware for proper unicast, multicast and
3587 void ixgbe_set_rx_mode(struct net_device *netdev)
3589 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3590 struct ixgbe_hw *hw = &adapter->hw;
3591 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3594 /* Check for Promiscuous and All Multicast modes */
3596 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3598 /* set all bits that we expect to always be set */
3599 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
3600 fctrl |= IXGBE_FCTRL_BAM;
3601 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3602 fctrl |= IXGBE_FCTRL_PMCF;
3604 /* clear the bits we are changing the status of */
3605 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3607 if (netdev->flags & IFF_PROMISC) {
3608 hw->addr_ctrl.user_set_promisc = true;
3609 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3610 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3611 /* don't hardware filter vlans in promisc mode */
3612 ixgbe_vlan_filter_disable(adapter);
3614 if (netdev->flags & IFF_ALLMULTI) {
3615 fctrl |= IXGBE_FCTRL_MPE;
3616 vmolr |= IXGBE_VMOLR_MPE;
3619 * Write addresses to the MTA, if the attempt fails
3620 * then we should just turn on promiscuous mode so
3621 * that we can at least receive multicast traffic
3623 hw->mac.ops.update_mc_addr_list(hw, netdev);
3624 vmolr |= IXGBE_VMOLR_ROMPE;
3626 ixgbe_vlan_filter_enable(adapter);
3627 hw->addr_ctrl.user_set_promisc = false;
3631 * Write addresses to available RAR registers, if there is not
3632 * sufficient space to store all the addresses then enable
3633 * unicast promiscuous mode
3635 count = ixgbe_write_uc_addr_list(netdev);
3637 fctrl |= IXGBE_FCTRL_UPE;
3638 vmolr |= IXGBE_VMOLR_ROPE;
3641 if (adapter->num_vfs)
3642 ixgbe_restore_vf_multicasts(adapter);
3644 if (hw->mac.type != ixgbe_mac_82598EB) {
3645 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
3646 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3648 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
3651 /* This is useful for sniffing bad packets. */
3652 if (adapter->netdev->features & NETIF_F_RXALL) {
3653 /* UPE and MPE will be handled by normal PROMISC logic
3654 * in e1000e_set_rx_mode */
3655 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3656 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3657 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3659 fctrl &= ~(IXGBE_FCTRL_DPF);
3660 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3663 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3665 if (netdev->features & NETIF_F_HW_VLAN_RX)
3666 ixgbe_vlan_strip_enable(adapter);
3668 ixgbe_vlan_strip_disable(adapter);
3671 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3675 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3676 napi_enable(&adapter->q_vector[q_idx]->napi);
3679 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3683 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3684 napi_disable(&adapter->q_vector[q_idx]->napi);
3687 #ifdef CONFIG_IXGBE_DCB
3689 * ixgbe_configure_dcb - Configure DCB hardware
3690 * @adapter: ixgbe adapter struct
3692 * This is called by the driver on open to configure the DCB hardware.
3693 * This is also called by the gennetlink interface when reconfiguring
3696 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3698 struct ixgbe_hw *hw = &adapter->hw;
3699 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3701 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3702 if (hw->mac.type == ixgbe_mac_82598EB)
3703 netif_set_gso_max_size(adapter->netdev, 65536);
3707 if (hw->mac.type == ixgbe_mac_82598EB)
3708 netif_set_gso_max_size(adapter->netdev, 32768);
3711 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3712 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3715 /* reconfigure the hardware */
3716 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3717 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3719 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3721 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3722 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3723 ixgbe_dcb_hw_ets(&adapter->hw,
3724 adapter->ixgbe_ieee_ets,
3726 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3727 adapter->ixgbe_ieee_pfc->pfc_en,
3728 adapter->ixgbe_ieee_ets->prio_tc);
3731 /* Enable RSS Hash per TC */
3732 if (hw->mac.type != ixgbe_mac_82598EB) {
3734 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
3741 /* write msb to all 8 TCs in one write */
3742 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
3747 /* Additional bittime to account for IXGBE framing */
3748 #define IXGBE_ETH_FRAMING 20
3751 * ixgbe_hpbthresh - calculate high water mark for flow control
3753 * @adapter: board private structure to calculate for
3754 * @pb: packet buffer to calculate
3756 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3758 struct ixgbe_hw *hw = &adapter->hw;
3759 struct net_device *dev = adapter->netdev;
3760 int link, tc, kb, marker;
3763 /* Calculate max LAN frame size */
3764 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3767 /* FCoE traffic class uses FCOE jumbo frames */
3768 if ((dev->features & NETIF_F_FCOE_MTU) &&
3769 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
3770 (pb == ixgbe_fcoe_get_tc(adapter)))
3771 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3774 /* Calculate delay value for device */
3775 switch (hw->mac.type) {
3776 case ixgbe_mac_X540:
3777 dv_id = IXGBE_DV_X540(link, tc);
3780 dv_id = IXGBE_DV(link, tc);
3784 /* Loopback switch introduces additional latency */
3785 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3786 dv_id += IXGBE_B2BT(tc);
3788 /* Delay value is calculated in bit times convert to KB */
3789 kb = IXGBE_BT2KB(dv_id);
3790 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3792 marker = rx_pba - kb;
3794 /* It is possible that the packet buffer is not large enough
3795 * to provide required headroom. In this case throw an error
3796 * to user and a do the best we can.
3799 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3800 "headroom to support flow control."
3801 "Decrease MTU or number of traffic classes\n", pb);
3809 * ixgbe_lpbthresh - calculate low water mark for for flow control
3811 * @adapter: board private structure to calculate for
3812 * @pb: packet buffer to calculate
3814 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3816 struct ixgbe_hw *hw = &adapter->hw;
3817 struct net_device *dev = adapter->netdev;
3821 /* Calculate max LAN frame size */
3822 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3824 /* Calculate delay value for device */
3825 switch (hw->mac.type) {
3826 case ixgbe_mac_X540:
3827 dv_id = IXGBE_LOW_DV_X540(tc);
3830 dv_id = IXGBE_LOW_DV(tc);
3834 /* Delay value is calculated in bit times convert to KB */
3835 return IXGBE_BT2KB(dv_id);
3839 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3841 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3843 struct ixgbe_hw *hw = &adapter->hw;
3844 int num_tc = netdev_get_num_tc(adapter->netdev);
3850 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3852 for (i = 0; i < num_tc; i++) {
3853 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3855 /* Low water marks must not be larger than high water marks */
3856 if (hw->fc.low_water > hw->fc.high_water[i])
3857 hw->fc.low_water = 0;
3861 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3863 struct ixgbe_hw *hw = &adapter->hw;
3865 u8 tc = netdev_get_num_tc(adapter->netdev);
3867 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3868 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3869 hdrm = 32 << adapter->fdir_pballoc;
3873 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
3874 ixgbe_pbthresh_setup(adapter);
3877 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3879 struct ixgbe_hw *hw = &adapter->hw;
3880 struct hlist_node *node, *node2;
3881 struct ixgbe_fdir_filter *filter;
3883 spin_lock(&adapter->fdir_perfect_lock);
3885 if (!hlist_empty(&adapter->fdir_filter_list))
3886 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3888 hlist_for_each_entry_safe(filter, node, node2,
3889 &adapter->fdir_filter_list, fdir_node) {
3890 ixgbe_fdir_write_perfect_filter_82599(hw,
3893 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3894 IXGBE_FDIR_DROP_QUEUE :
3895 adapter->rx_ring[filter->action]->reg_idx);
3898 spin_unlock(&adapter->fdir_perfect_lock);
3901 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3903 struct ixgbe_hw *hw = &adapter->hw;
3905 ixgbe_configure_pb(adapter);
3906 #ifdef CONFIG_IXGBE_DCB
3907 ixgbe_configure_dcb(adapter);
3910 * We must restore virtualization before VLANs or else
3911 * the VLVF registers will not be populated
3913 ixgbe_configure_virtualization(adapter);
3915 ixgbe_set_rx_mode(adapter->netdev);
3916 ixgbe_restore_vlan(adapter);
3918 switch (hw->mac.type) {
3919 case ixgbe_mac_82599EB:
3920 case ixgbe_mac_X540:
3921 hw->mac.ops.disable_rx_buff(hw);
3927 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3928 ixgbe_init_fdir_signature_82599(&adapter->hw,
3929 adapter->fdir_pballoc);
3930 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3931 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3932 adapter->fdir_pballoc);
3933 ixgbe_fdir_filter_restore(adapter);
3936 switch (hw->mac.type) {
3937 case ixgbe_mac_82599EB:
3938 case ixgbe_mac_X540:
3939 hw->mac.ops.enable_rx_buff(hw);
3946 /* configure FCoE L2 filters, redirection table, and Rx control */
3947 ixgbe_configure_fcoe(adapter);
3949 #endif /* IXGBE_FCOE */
3950 ixgbe_configure_tx(adapter);
3951 ixgbe_configure_rx(adapter);
3954 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3956 switch (hw->phy.type) {
3957 case ixgbe_phy_sfp_avago:
3958 case ixgbe_phy_sfp_ftl:
3959 case ixgbe_phy_sfp_intel:
3960 case ixgbe_phy_sfp_unknown:
3961 case ixgbe_phy_sfp_passive_tyco:
3962 case ixgbe_phy_sfp_passive_unknown:
3963 case ixgbe_phy_sfp_active_unknown:
3964 case ixgbe_phy_sfp_ftl_active:
3967 if (hw->mac.type == ixgbe_mac_82598EB)
3975 * ixgbe_sfp_link_config - set up SFP+ link
3976 * @adapter: pointer to private adapter struct
3978 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3981 * We are assuming the worst case scenario here, and that
3982 * is that an SFP was inserted/removed after the reset
3983 * but before SFP detection was enabled. As such the best
3984 * solution is to just start searching as soon as we start
3986 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3987 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3989 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3993 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3994 * @hw: pointer to private hardware struct
3996 * Returns 0 on success, negative on failure
3998 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
4001 bool negotiation, link_up = false;
4002 u32 ret = IXGBE_ERR_LINK_SETUP;
4004 if (hw->mac.ops.check_link)
4005 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
4010 autoneg = hw->phy.autoneg_advertised;
4011 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
4012 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
4017 if (hw->mac.ops.setup_link)
4018 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
4023 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
4025 struct ixgbe_hw *hw = &adapter->hw;
4028 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4029 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4031 gpie |= IXGBE_GPIE_EIAME;
4033 * use EIAM to auto-mask when MSI-X interrupt is asserted
4034 * this saves a register write for every interrupt
4036 switch (hw->mac.type) {
4037 case ixgbe_mac_82598EB:
4038 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4040 case ixgbe_mac_82599EB:
4041 case ixgbe_mac_X540:
4043 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4044 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4048 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4049 * specifically only auto mask tx and rx interrupts */
4050 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4053 /* XXX: to interrupt immediately for EICS writes, enable this */
4054 /* gpie |= IXGBE_GPIE_EIMEN; */
4056 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4057 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
4059 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4060 case IXGBE_82599_VMDQ_8Q_MASK:
4061 gpie |= IXGBE_GPIE_VTMODE_16;
4063 case IXGBE_82599_VMDQ_4Q_MASK:
4064 gpie |= IXGBE_GPIE_VTMODE_32;
4067 gpie |= IXGBE_GPIE_VTMODE_64;
4072 /* Enable Thermal over heat sensor interrupt */
4073 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4074 switch (adapter->hw.mac.type) {
4075 case ixgbe_mac_82599EB:
4076 gpie |= IXGBE_SDP0_GPIEN;
4078 case ixgbe_mac_X540:
4079 gpie |= IXGBE_EIMS_TS;
4086 /* Enable fan failure interrupt */
4087 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
4088 gpie |= IXGBE_SDP1_GPIEN;
4090 if (hw->mac.type == ixgbe_mac_82599EB) {
4091 gpie |= IXGBE_SDP1_GPIEN;
4092 gpie |= IXGBE_SDP2_GPIEN;
4095 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4098 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
4100 struct ixgbe_hw *hw = &adapter->hw;
4104 ixgbe_get_hw_control(adapter);
4105 ixgbe_setup_gpie(adapter);
4107 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4108 ixgbe_configure_msix(adapter);
4110 ixgbe_configure_msi_and_legacy(adapter);
4112 /* enable the optics for 82599 SFP+ fiber */
4113 if (hw->mac.ops.enable_tx_laser)
4114 hw->mac.ops.enable_tx_laser(hw);
4116 clear_bit(__IXGBE_DOWN, &adapter->state);
4117 ixgbe_napi_enable_all(adapter);
4119 if (ixgbe_is_sfp(hw)) {
4120 ixgbe_sfp_link_config(adapter);
4122 err = ixgbe_non_sfp_link_config(hw);
4124 e_err(probe, "link_config FAILED %d\n", err);
4127 /* clear any pending interrupts, may auto mask */
4128 IXGBE_READ_REG(hw, IXGBE_EICR);
4129 ixgbe_irq_enable(adapter, true, true);
4132 * If this adapter has a fan, check to see if we had a failure
4133 * before we enabled the interrupt.
4135 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4136 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4137 if (esdp & IXGBE_ESDP_SDP1)
4138 e_crit(drv, "Fan has stopped, replace the adapter\n");
4141 /* enable transmits */
4142 netif_tx_start_all_queues(adapter->netdev);
4144 /* bring the link up in the watchdog, this could race with our first
4145 * link up interrupt but shouldn't be a problem */
4146 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4147 adapter->link_check_timeout = jiffies;
4148 mod_timer(&adapter->service_timer, jiffies);
4150 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4151 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4152 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4153 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
4156 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4158 WARN_ON(in_interrupt());
4159 /* put off any impending NetWatchDogTimeout */
4160 adapter->netdev->trans_start = jiffies;
4162 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
4163 usleep_range(1000, 2000);
4164 ixgbe_down(adapter);
4166 * If SR-IOV enabled then wait a bit before bringing the adapter
4167 * back up to give the VFs time to respond to the reset. The
4168 * two second wait is based upon the watchdog timer cycle in
4171 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4174 clear_bit(__IXGBE_RESETTING, &adapter->state);
4177 void ixgbe_up(struct ixgbe_adapter *adapter)
4179 /* hardware has been reset, we need to reload some things */
4180 ixgbe_configure(adapter);
4182 ixgbe_up_complete(adapter);
4185 void ixgbe_reset(struct ixgbe_adapter *adapter)
4187 struct ixgbe_hw *hw = &adapter->hw;
4190 /* lock SFP init bit to prevent race conditions with the watchdog */
4191 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4192 usleep_range(1000, 2000);
4194 /* clear all SFP and link config related flags while holding SFP_INIT */
4195 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4196 IXGBE_FLAG2_SFP_NEEDS_RESET);
4197 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4199 err = hw->mac.ops.init_hw(hw);
4202 case IXGBE_ERR_SFP_NOT_PRESENT:
4203 case IXGBE_ERR_SFP_NOT_SUPPORTED:
4205 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4206 e_dev_err("master disable timed out\n");
4208 case IXGBE_ERR_EEPROM_VERSION:
4209 /* We are running on a pre-production device, log a warning */
4210 e_dev_warn("This device is a pre-production adapter/LOM. "
4211 "Please be aware there may be issues associated with "
4212 "your hardware. If you are experiencing problems "
4213 "please contact your Intel or hardware "
4214 "representative who provided you with this "
4218 e_dev_err("Hardware Error: %d\n", err);
4221 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4223 /* reprogram the RAR[0] in case user changed it. */
4224 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
4226 /* update SAN MAC vmdq pool selection */
4227 if (hw->mac.san_mac_rar_index)
4228 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
4230 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
4231 ixgbe_ptp_reset(adapter);
4235 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4236 * @rx_ring: ring to free buffers from
4238 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4240 struct device *dev = rx_ring->dev;
4244 /* ring already cleared, nothing to do */
4245 if (!rx_ring->rx_buffer_info)
4248 /* Free all the Rx ring sk_buffs */
4249 for (i = 0; i < rx_ring->count; i++) {
4250 struct ixgbe_rx_buffer *rx_buffer;
4252 rx_buffer = &rx_ring->rx_buffer_info[i];
4253 if (rx_buffer->skb) {
4254 struct sk_buff *skb = rx_buffer->skb;
4255 if (IXGBE_CB(skb)->page_released) {
4258 ixgbe_rx_bufsz(rx_ring),
4260 IXGBE_CB(skb)->page_released = false;
4264 rx_buffer->skb = NULL;
4266 dma_unmap_page(dev, rx_buffer->dma,
4267 ixgbe_rx_pg_size(rx_ring),
4270 if (rx_buffer->page)
4271 __free_pages(rx_buffer->page,
4272 ixgbe_rx_pg_order(rx_ring));
4273 rx_buffer->page = NULL;
4276 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4277 memset(rx_ring->rx_buffer_info, 0, size);
4279 /* Zero out the descriptor ring */
4280 memset(rx_ring->desc, 0, rx_ring->size);
4282 rx_ring->next_to_alloc = 0;
4283 rx_ring->next_to_clean = 0;
4284 rx_ring->next_to_use = 0;
4288 * ixgbe_clean_tx_ring - Free Tx Buffers
4289 * @tx_ring: ring to be cleaned
4291 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4293 struct ixgbe_tx_buffer *tx_buffer_info;
4297 /* ring already cleared, nothing to do */
4298 if (!tx_ring->tx_buffer_info)
4301 /* Free all the Tx ring sk_buffs */
4302 for (i = 0; i < tx_ring->count; i++) {
4303 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4304 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4307 netdev_tx_reset_queue(txring_txq(tx_ring));
4309 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4310 memset(tx_ring->tx_buffer_info, 0, size);
4312 /* Zero out the descriptor ring */
4313 memset(tx_ring->desc, 0, tx_ring->size);
4315 tx_ring->next_to_use = 0;
4316 tx_ring->next_to_clean = 0;
4320 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4321 * @adapter: board private structure
4323 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4327 for (i = 0; i < adapter->num_rx_queues; i++)
4328 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4332 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4333 * @adapter: board private structure
4335 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4339 for (i = 0; i < adapter->num_tx_queues; i++)
4340 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4343 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4345 struct hlist_node *node, *node2;
4346 struct ixgbe_fdir_filter *filter;
4348 spin_lock(&adapter->fdir_perfect_lock);
4350 hlist_for_each_entry_safe(filter, node, node2,
4351 &adapter->fdir_filter_list, fdir_node) {
4352 hlist_del(&filter->fdir_node);
4355 adapter->fdir_filter_count = 0;
4357 spin_unlock(&adapter->fdir_perfect_lock);
4360 void ixgbe_down(struct ixgbe_adapter *adapter)
4362 struct net_device *netdev = adapter->netdev;
4363 struct ixgbe_hw *hw = &adapter->hw;
4367 /* signal that we are down to the interrupt handler */
4368 set_bit(__IXGBE_DOWN, &adapter->state);
4370 /* disable receives */
4371 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4372 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4374 /* disable all enabled rx queues */
4375 for (i = 0; i < adapter->num_rx_queues; i++)
4376 /* this call also flushes the previous write */
4377 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4379 usleep_range(10000, 20000);
4381 netif_tx_stop_all_queues(netdev);
4383 /* call carrier off first to avoid false dev_watchdog timeouts */
4384 netif_carrier_off(netdev);
4385 netif_tx_disable(netdev);
4387 ixgbe_irq_disable(adapter);
4389 ixgbe_napi_disable_all(adapter);
4391 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4392 IXGBE_FLAG2_RESET_REQUESTED);
4393 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4395 del_timer_sync(&adapter->service_timer);
4397 if (adapter->num_vfs) {
4398 /* Clear EITR Select mapping */
4399 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4401 /* Mark all the VFs as inactive */
4402 for (i = 0 ; i < adapter->num_vfs; i++)
4403 adapter->vfinfo[i].clear_to_send = false;
4405 /* ping all the active vfs to let them know we are going down */
4406 ixgbe_ping_all_vfs(adapter);
4408 /* Disable all VFTE/VFRE TX/RX */
4409 ixgbe_disable_tx_rx(adapter);
4412 /* disable transmits in the hardware now that interrupts are off */
4413 for (i = 0; i < adapter->num_tx_queues; i++) {
4414 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4415 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4418 /* Disable the Tx DMA engine on 82599 and X540 */
4419 switch (hw->mac.type) {
4420 case ixgbe_mac_82599EB:
4421 case ixgbe_mac_X540:
4422 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4423 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4424 ~IXGBE_DMATXCTL_TE));
4430 if (!pci_channel_offline(adapter->pdev))
4431 ixgbe_reset(adapter);
4433 /* power down the optics for 82599 SFP+ fiber */
4434 if (hw->mac.ops.disable_tx_laser)
4435 hw->mac.ops.disable_tx_laser(hw);
4437 ixgbe_clean_all_tx_rings(adapter);
4438 ixgbe_clean_all_rx_rings(adapter);
4440 #ifdef CONFIG_IXGBE_DCA
4441 /* since we reset the hardware DCA settings were cleared */
4442 ixgbe_setup_dca(adapter);
4447 * ixgbe_tx_timeout - Respond to a Tx Hang
4448 * @netdev: network interface device structure
4450 static void ixgbe_tx_timeout(struct net_device *netdev)
4452 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4454 /* Do the reset outside of interrupt context */
4455 ixgbe_tx_timeout_reset(adapter);
4459 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4460 * @adapter: board private structure to initialize
4462 * ixgbe_sw_init initializes the Adapter private data structure.
4463 * Fields are initialized based on PCI device information and
4464 * OS network device settings (MTU size).
4466 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4468 struct ixgbe_hw *hw = &adapter->hw;
4469 struct pci_dev *pdev = adapter->pdev;
4471 #ifdef CONFIG_IXGBE_DCB
4473 struct tc_configuration *tc;
4476 /* PCI config space info */
4478 hw->vendor_id = pdev->vendor;
4479 hw->device_id = pdev->device;
4480 hw->revision_id = pdev->revision;
4481 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4482 hw->subsystem_device_id = pdev->subsystem_device;
4484 /* Set capability flags */
4485 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
4486 adapter->ring_feature[RING_F_RSS].limit = rss;
4487 switch (hw->mac.type) {
4488 case ixgbe_mac_82598EB:
4489 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4490 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4491 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
4493 case ixgbe_mac_X540:
4494 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4495 case ixgbe_mac_82599EB:
4496 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
4497 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4498 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4499 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4500 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4501 /* Flow Director hash filters enabled */
4502 adapter->atr_sample_rate = 20;
4503 adapter->ring_feature[RING_F_FDIR].limit =
4504 IXGBE_MAX_FDIR_INDICES;
4505 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4507 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4508 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4509 #ifdef CONFIG_IXGBE_DCB
4510 /* Default traffic class to use for FCoE */
4511 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4513 #endif /* IXGBE_FCOE */
4520 /* FCoE support exists, always init the FCoE lock */
4521 spin_lock_init(&adapter->fcoe.lock);
4524 /* n-tuple support exists, always init our spinlock */
4525 spin_lock_init(&adapter->fdir_perfect_lock);
4527 #ifdef CONFIG_IXGBE_DCB
4528 switch (hw->mac.type) {
4529 case ixgbe_mac_X540:
4530 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4531 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4534 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4535 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4539 /* Configure DCB traffic classes */
4540 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4541 tc = &adapter->dcb_cfg.tc_config[j];
4542 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4543 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4544 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4545 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4546 tc->dcb_pfc = pfc_disabled;
4549 /* Initialize default user to priority mapping, UPx->TC0 */
4550 tc = &adapter->dcb_cfg.tc_config[0];
4551 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4552 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4554 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4555 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4556 adapter->dcb_cfg.pfc_mode_enable = false;
4557 adapter->dcb_set_bitmap = 0x00;
4558 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
4559 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4560 sizeof(adapter->temp_dcb_cfg));
4564 /* default flow control settings */
4565 hw->fc.requested_mode = ixgbe_fc_full;
4566 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4567 ixgbe_pbthresh_setup(adapter);
4568 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4569 hw->fc.send_xon = true;
4570 hw->fc.disable_fc_autoneg =
4571 (ixgbe_device_supports_autoneg_fc(hw) == 0) ? false : true;
4573 #ifdef CONFIG_PCI_IOV
4574 /* assign number of SR-IOV VFs */
4575 if (hw->mac.type != ixgbe_mac_82598EB)
4576 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
4579 /* enable itr by default in dynamic mode */
4580 adapter->rx_itr_setting = 1;
4581 adapter->tx_itr_setting = 1;
4583 /* set default ring sizes */
4584 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4585 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4587 /* set default work limits */
4588 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
4590 /* initialize eeprom parameters */
4591 if (ixgbe_init_eeprom_params_generic(hw)) {
4592 e_dev_err("EEPROM initialization failed\n");
4596 set_bit(__IXGBE_DOWN, &adapter->state);
4602 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4603 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4605 * Return 0 on success, negative on failure
4607 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4609 struct device *dev = tx_ring->dev;
4610 int orig_node = dev_to_node(dev);
4614 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4616 if (tx_ring->q_vector)
4617 numa_node = tx_ring->q_vector->numa_node;
4619 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
4620 if (!tx_ring->tx_buffer_info)
4621 tx_ring->tx_buffer_info = vzalloc(size);
4622 if (!tx_ring->tx_buffer_info)
4625 /* round up to nearest 4K */
4626 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4627 tx_ring->size = ALIGN(tx_ring->size, 4096);
4629 set_dev_node(dev, numa_node);
4630 tx_ring->desc = dma_alloc_coherent(dev,
4634 set_dev_node(dev, orig_node);
4636 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4637 &tx_ring->dma, GFP_KERNEL);
4641 tx_ring->next_to_use = 0;
4642 tx_ring->next_to_clean = 0;
4646 vfree(tx_ring->tx_buffer_info);
4647 tx_ring->tx_buffer_info = NULL;
4648 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4653 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4654 * @adapter: board private structure
4656 * If this function returns with an error, then it's possible one or
4657 * more of the rings is populated (while the rest are not). It is the
4658 * callers duty to clean those orphaned rings.
4660 * Return 0 on success, negative on failure
4662 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4666 for (i = 0; i < adapter->num_tx_queues; i++) {
4667 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
4671 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4677 /* rewind the index freeing the rings as we go */
4679 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4684 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4685 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4687 * Returns 0 on success, negative on failure
4689 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
4691 struct device *dev = rx_ring->dev;
4692 int orig_node = dev_to_node(dev);
4696 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4698 if (rx_ring->q_vector)
4699 numa_node = rx_ring->q_vector->numa_node;
4701 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
4702 if (!rx_ring->rx_buffer_info)
4703 rx_ring->rx_buffer_info = vzalloc(size);
4704 if (!rx_ring->rx_buffer_info)
4707 /* Round up to nearest 4K */
4708 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4709 rx_ring->size = ALIGN(rx_ring->size, 4096);
4711 set_dev_node(dev, numa_node);
4712 rx_ring->desc = dma_alloc_coherent(dev,
4716 set_dev_node(dev, orig_node);
4718 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4719 &rx_ring->dma, GFP_KERNEL);
4723 rx_ring->next_to_clean = 0;
4724 rx_ring->next_to_use = 0;
4728 vfree(rx_ring->rx_buffer_info);
4729 rx_ring->rx_buffer_info = NULL;
4730 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4735 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4736 * @adapter: board private structure
4738 * If this function returns with an error, then it's possible one or
4739 * more of the rings is populated (while the rest are not). It is the
4740 * callers duty to clean those orphaned rings.
4742 * Return 0 on success, negative on failure
4744 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4748 for (i = 0; i < adapter->num_rx_queues; i++) {
4749 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
4753 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
4758 err = ixgbe_setup_fcoe_ddp_resources(adapter);
4763 /* rewind the index freeing the rings as we go */
4765 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4770 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4771 * @tx_ring: Tx descriptor ring for a specific queue
4773 * Free all transmit software resources
4775 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
4777 ixgbe_clean_tx_ring(tx_ring);
4779 vfree(tx_ring->tx_buffer_info);
4780 tx_ring->tx_buffer_info = NULL;
4782 /* if not set, then don't free */
4786 dma_free_coherent(tx_ring->dev, tx_ring->size,
4787 tx_ring->desc, tx_ring->dma);
4789 tx_ring->desc = NULL;
4793 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4794 * @adapter: board private structure
4796 * Free all transmit software resources
4798 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4802 for (i = 0; i < adapter->num_tx_queues; i++)
4803 if (adapter->tx_ring[i]->desc)
4804 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4808 * ixgbe_free_rx_resources - Free Rx Resources
4809 * @rx_ring: ring to clean the resources from
4811 * Free all receive software resources
4813 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
4815 ixgbe_clean_rx_ring(rx_ring);
4817 vfree(rx_ring->rx_buffer_info);
4818 rx_ring->rx_buffer_info = NULL;
4820 /* if not set, then don't free */
4824 dma_free_coherent(rx_ring->dev, rx_ring->size,
4825 rx_ring->desc, rx_ring->dma);
4827 rx_ring->desc = NULL;
4831 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4832 * @adapter: board private structure
4834 * Free all receive software resources
4836 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4841 ixgbe_free_fcoe_ddp_resources(adapter);
4844 for (i = 0; i < adapter->num_rx_queues; i++)
4845 if (adapter->rx_ring[i]->desc)
4846 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4850 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4851 * @netdev: network interface device structure
4852 * @new_mtu: new value for maximum frame size
4854 * Returns 0 on success, negative on failure
4856 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4858 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4859 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4861 /* MTU < 68 is an error and causes problems on some kernels */
4862 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4866 * For 82599EB we cannot allow legacy VFs to enable their receive
4867 * paths when MTU greater than 1500 is configured. So display a
4868 * warning that legacy VFs will be disabled.
4870 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4871 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4872 (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
4873 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
4875 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
4877 /* must set new MTU before calling down or up */
4878 netdev->mtu = new_mtu;
4880 if (netif_running(netdev))
4881 ixgbe_reinit_locked(adapter);
4887 * ixgbe_open - Called when a network interface is made active
4888 * @netdev: network interface device structure
4890 * Returns 0 on success, negative value on failure
4892 * The open entry point is called when a network interface is made
4893 * active by the system (IFF_UP). At this point all resources needed
4894 * for transmit and receive operations are allocated, the interrupt
4895 * handler is registered with the OS, the watchdog timer is started,
4896 * and the stack is notified that the interface is ready.
4898 static int ixgbe_open(struct net_device *netdev)
4900 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4903 /* disallow open during test */
4904 if (test_bit(__IXGBE_TESTING, &adapter->state))
4907 netif_carrier_off(netdev);
4909 /* allocate transmit descriptors */
4910 err = ixgbe_setup_all_tx_resources(adapter);
4914 /* allocate receive descriptors */
4915 err = ixgbe_setup_all_rx_resources(adapter);
4919 ixgbe_configure(adapter);
4921 err = ixgbe_request_irq(adapter);
4925 /* Notify the stack of the actual queue counts. */
4926 err = netif_set_real_num_tx_queues(netdev,
4927 adapter->num_rx_pools > 1 ? 1 :
4928 adapter->num_tx_queues);
4930 goto err_set_queues;
4933 err = netif_set_real_num_rx_queues(netdev,
4934 adapter->num_rx_pools > 1 ? 1 :
4935 adapter->num_rx_queues);
4937 goto err_set_queues;
4939 ixgbe_ptp_init(adapter);
4941 ixgbe_up_complete(adapter);
4946 ixgbe_free_irq(adapter);
4948 ixgbe_free_all_rx_resources(adapter);
4950 ixgbe_free_all_tx_resources(adapter);
4952 ixgbe_reset(adapter);
4958 * ixgbe_close - Disables a network interface
4959 * @netdev: network interface device structure
4961 * Returns 0, this is not allowed to fail
4963 * The close entry point is called when an interface is de-activated
4964 * by the OS. The hardware is still under the drivers control, but
4965 * needs to be disabled. A global MAC reset is issued to stop the
4966 * hardware, and all transmit and receive resources are freed.
4968 static int ixgbe_close(struct net_device *netdev)
4970 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4972 ixgbe_ptp_stop(adapter);
4974 ixgbe_down(adapter);
4975 ixgbe_free_irq(adapter);
4977 ixgbe_fdir_filter_exit(adapter);
4979 ixgbe_free_all_tx_resources(adapter);
4980 ixgbe_free_all_rx_resources(adapter);
4982 ixgbe_release_hw_control(adapter);
4988 static int ixgbe_resume(struct pci_dev *pdev)
4990 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4991 struct net_device *netdev = adapter->netdev;
4994 pci_set_power_state(pdev, PCI_D0);
4995 pci_restore_state(pdev);
4997 * pci_restore_state clears dev->state_saved so call
4998 * pci_save_state to restore it.
5000 pci_save_state(pdev);
5002 err = pci_enable_device_mem(pdev);
5004 e_dev_err("Cannot enable PCI device from suspend\n");
5007 pci_set_master(pdev);
5009 pci_wake_from_d3(pdev, false);
5011 ixgbe_reset(adapter);
5013 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5016 err = ixgbe_init_interrupt_scheme(adapter);
5017 if (!err && netif_running(netdev))
5018 err = ixgbe_open(netdev);
5025 netif_device_attach(netdev);
5029 #endif /* CONFIG_PM */
5031 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5033 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5034 struct net_device *netdev = adapter->netdev;
5035 struct ixgbe_hw *hw = &adapter->hw;
5037 u32 wufc = adapter->wol;
5042 netif_device_detach(netdev);
5044 if (netif_running(netdev)) {
5046 ixgbe_down(adapter);
5047 ixgbe_free_irq(adapter);
5048 ixgbe_free_all_tx_resources(adapter);
5049 ixgbe_free_all_rx_resources(adapter);
5053 ixgbe_clear_interrupt_scheme(adapter);
5056 retval = pci_save_state(pdev);
5062 ixgbe_set_rx_mode(netdev);
5064 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5065 if (hw->mac.ops.enable_tx_laser)
5066 hw->mac.ops.enable_tx_laser(hw);
5068 /* turn on all-multi mode if wake on multicast is enabled */
5069 if (wufc & IXGBE_WUFC_MC) {
5070 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5071 fctrl |= IXGBE_FCTRL_MPE;
5072 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5075 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5076 ctrl |= IXGBE_CTRL_GIO_DIS;
5077 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5079 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5081 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5082 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5085 switch (hw->mac.type) {
5086 case ixgbe_mac_82598EB:
5087 pci_wake_from_d3(pdev, false);
5089 case ixgbe_mac_82599EB:
5090 case ixgbe_mac_X540:
5091 pci_wake_from_d3(pdev, !!wufc);
5097 *enable_wake = !!wufc;
5099 ixgbe_release_hw_control(adapter);
5101 pci_disable_device(pdev);
5107 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5112 retval = __ixgbe_shutdown(pdev, &wake);
5117 pci_prepare_to_sleep(pdev);
5119 pci_wake_from_d3(pdev, false);
5120 pci_set_power_state(pdev, PCI_D3hot);
5125 #endif /* CONFIG_PM */
5127 static void ixgbe_shutdown(struct pci_dev *pdev)
5131 __ixgbe_shutdown(pdev, &wake);
5133 if (system_state == SYSTEM_POWER_OFF) {
5134 pci_wake_from_d3(pdev, wake);
5135 pci_set_power_state(pdev, PCI_D3hot);
5140 * ixgbe_update_stats - Update the board statistics counters.
5141 * @adapter: board private structure
5143 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5145 struct net_device *netdev = adapter->netdev;
5146 struct ixgbe_hw *hw = &adapter->hw;
5147 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5149 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5150 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5151 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5152 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
5154 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5155 test_bit(__IXGBE_RESETTING, &adapter->state))
5158 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5161 for (i = 0; i < adapter->num_rx_queues; i++) {
5162 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5163 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5165 adapter->rsc_total_count = rsc_count;
5166 adapter->rsc_total_flush = rsc_flush;
5169 for (i = 0; i < adapter->num_rx_queues; i++) {
5170 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5171 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5172 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5173 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5174 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5175 bytes += rx_ring->stats.bytes;
5176 packets += rx_ring->stats.packets;
5178 adapter->non_eop_descs = non_eop_descs;
5179 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5180 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5181 adapter->hw_csum_rx_error = hw_csum_rx_error;
5182 netdev->stats.rx_bytes = bytes;
5183 netdev->stats.rx_packets = packets;
5187 /* gather some stats to the adapter struct that are per queue */
5188 for (i = 0; i < adapter->num_tx_queues; i++) {
5189 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5190 restart_queue += tx_ring->tx_stats.restart_queue;
5191 tx_busy += tx_ring->tx_stats.tx_busy;
5192 bytes += tx_ring->stats.bytes;
5193 packets += tx_ring->stats.packets;
5195 adapter->restart_queue = restart_queue;
5196 adapter->tx_busy = tx_busy;
5197 netdev->stats.tx_bytes = bytes;
5198 netdev->stats.tx_packets = packets;
5200 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5202 /* 8 register reads */
5203 for (i = 0; i < 8; i++) {
5204 /* for packet buffers not used, the register should read 0 */
5205 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5207 hwstats->mpc[i] += mpc;
5208 total_mpc += hwstats->mpc[i];
5209 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5210 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5211 switch (hw->mac.type) {
5212 case ixgbe_mac_82598EB:
5213 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5214 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5215 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5216 hwstats->pxonrxc[i] +=
5217 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5219 case ixgbe_mac_82599EB:
5220 case ixgbe_mac_X540:
5221 hwstats->pxonrxc[i] +=
5222 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5229 /*16 register reads */
5230 for (i = 0; i < 16; i++) {
5231 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5232 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5233 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5234 (hw->mac.type == ixgbe_mac_X540)) {
5235 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5236 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5237 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5238 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5242 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5243 /* work around hardware counting issue */
5244 hwstats->gprc -= missed_rx;
5246 ixgbe_update_xoff_received(adapter);
5248 /* 82598 hardware only has a 32 bit counter in the high register */
5249 switch (hw->mac.type) {
5250 case ixgbe_mac_82598EB:
5251 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5252 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5253 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5254 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5256 case ixgbe_mac_X540:
5257 /* OS2BMC stats are X540 only*/
5258 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5259 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5260 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5261 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5262 case ixgbe_mac_82599EB:
5263 for (i = 0; i < 16; i++)
5264 adapter->hw_rx_no_dma_resources +=
5265 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5266 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5267 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5268 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5269 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5270 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5271 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5272 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5273 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5274 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5276 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5277 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5278 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5279 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5280 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5281 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5282 /* Add up per cpu counters for total ddp aloc fail */
5283 if (adapter->fcoe.ddp_pool) {
5284 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5285 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5287 u64 noddp = 0, noddp_ext_buff = 0;
5288 for_each_possible_cpu(cpu) {
5289 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5290 noddp += ddp_pool->noddp;
5291 noddp_ext_buff += ddp_pool->noddp_ext_buff;
5293 hwstats->fcoe_noddp = noddp;
5294 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
5296 #endif /* IXGBE_FCOE */
5301 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5302 hwstats->bprc += bprc;
5303 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5304 if (hw->mac.type == ixgbe_mac_82598EB)
5305 hwstats->mprc -= bprc;
5306 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5307 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5308 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5309 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5310 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5311 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5312 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5313 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5314 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5315 hwstats->lxontxc += lxon;
5316 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5317 hwstats->lxofftxc += lxoff;
5318 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5319 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5321 * 82598 errata - tx of flow control packets is included in tx counters
5323 xon_off_tot = lxon + lxoff;
5324 hwstats->gptc -= xon_off_tot;
5325 hwstats->mptc -= xon_off_tot;
5326 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5327 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5328 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5329 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5330 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5331 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5332 hwstats->ptc64 -= xon_off_tot;
5333 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5334 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5335 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5336 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5337 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5338 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5340 /* Fill out the OS statistics structure */
5341 netdev->stats.multicast = hwstats->mprc;
5344 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5345 netdev->stats.rx_dropped = 0;
5346 netdev->stats.rx_length_errors = hwstats->rlec;
5347 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5348 netdev->stats.rx_missed_errors = total_mpc;
5352 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5353 * @adapter: pointer to the device adapter structure
5355 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5357 struct ixgbe_hw *hw = &adapter->hw;
5360 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5363 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5365 /* if interface is down do nothing */
5366 if (test_bit(__IXGBE_DOWN, &adapter->state))
5369 /* do nothing if we are not using signature filters */
5370 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5373 adapter->fdir_overflow++;
5375 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5376 for (i = 0; i < adapter->num_tx_queues; i++)
5377 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5378 &(adapter->tx_ring[i]->state));
5379 /* re-enable flow director interrupts */
5380 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5382 e_err(probe, "failed to finish FDIR re-initialization, "
5383 "ignored adding FDIR ATR filters\n");
5388 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5389 * @adapter: pointer to the device adapter structure
5391 * This function serves two purposes. First it strobes the interrupt lines
5392 * in order to make certain interrupts are occurring. Secondly it sets the
5393 * bits needed to check for TX hangs. As a result we should immediately
5394 * determine if a hang has occurred.
5396 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5398 struct ixgbe_hw *hw = &adapter->hw;
5402 /* If we're down or resetting, just bail */
5403 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5404 test_bit(__IXGBE_RESETTING, &adapter->state))
5407 /* Force detection of hung controller */
5408 if (netif_carrier_ok(adapter->netdev)) {
5409 for (i = 0; i < adapter->num_tx_queues; i++)
5410 set_check_for_tx_hang(adapter->tx_ring[i]);
5413 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5415 * for legacy and MSI interrupts don't set any bits
5416 * that are enabled for EIAM, because this operation
5417 * would set *both* EIMS and EICS for any bit in EIAM
5419 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5420 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5422 /* get one bit for every active tx/rx interrupt vector */
5423 for (i = 0; i < adapter->num_q_vectors; i++) {
5424 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5425 if (qv->rx.ring || qv->tx.ring)
5426 eics |= ((u64)1 << i);
5430 /* Cause software interrupt to ensure rings are cleaned */
5431 ixgbe_irq_rearm_queues(adapter, eics);
5436 * ixgbe_watchdog_update_link - update the link status
5437 * @adapter: pointer to the device adapter structure
5438 * @link_speed: pointer to a u32 to store the link_speed
5440 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5442 struct ixgbe_hw *hw = &adapter->hw;
5443 u32 link_speed = adapter->link_speed;
5444 bool link_up = adapter->link_up;
5445 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
5447 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5450 if (hw->mac.ops.check_link) {
5451 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5453 /* always assume link is up, if no check link function */
5454 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5458 if (adapter->ixgbe_ieee_pfc)
5459 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5461 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
5462 hw->mac.ops.fc_enable(hw);
5463 ixgbe_set_rx_drop_en(adapter);
5467 time_after(jiffies, (adapter->link_check_timeout +
5468 IXGBE_TRY_LINK_TIMEOUT))) {
5469 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5470 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5471 IXGBE_WRITE_FLUSH(hw);
5474 adapter->link_up = link_up;
5475 adapter->link_speed = link_speed;
5478 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
5480 #ifdef CONFIG_IXGBE_DCB
5481 struct net_device *netdev = adapter->netdev;
5482 struct dcb_app app = {
5483 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
5488 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
5489 up = dcb_ieee_getapp_mask(netdev, &app);
5491 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
5496 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5497 * print link up message
5498 * @adapter: pointer to the device adapter structure
5500 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5502 struct net_device *netdev = adapter->netdev;
5503 struct ixgbe_hw *hw = &adapter->hw;
5504 u32 link_speed = adapter->link_speed;
5505 bool flow_rx, flow_tx;
5507 /* only continue if link was previously down */
5508 if (netif_carrier_ok(netdev))
5511 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5513 switch (hw->mac.type) {
5514 case ixgbe_mac_82598EB: {
5515 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5516 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5517 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5518 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5521 case ixgbe_mac_X540:
5522 case ixgbe_mac_82599EB: {
5523 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5524 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5525 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5526 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5535 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5536 ixgbe_ptp_start_cyclecounter(adapter);
5538 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5539 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5541 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5543 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5546 ((flow_rx && flow_tx) ? "RX/TX" :
5548 (flow_tx ? "TX" : "None"))));
5550 netif_carrier_on(netdev);
5551 ixgbe_check_vf_rate_limit(adapter);
5553 /* update the default user priority for VFs */
5554 ixgbe_update_default_up(adapter);
5556 /* ping all the active vfs to let them know link has changed */
5557 ixgbe_ping_all_vfs(adapter);
5561 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5562 * print link down message
5563 * @adapter: pointer to the adapter structure
5565 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
5567 struct net_device *netdev = adapter->netdev;
5568 struct ixgbe_hw *hw = &adapter->hw;
5570 adapter->link_up = false;
5571 adapter->link_speed = 0;
5573 /* only continue if link was up previously */
5574 if (!netif_carrier_ok(netdev))
5577 /* poll for SFP+ cable when link is down */
5578 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5579 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5581 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5582 ixgbe_ptp_start_cyclecounter(adapter);
5584 e_info(drv, "NIC Link is Down\n");
5585 netif_carrier_off(netdev);
5587 /* ping all the active vfs to let them know link has changed */
5588 ixgbe_ping_all_vfs(adapter);
5592 * ixgbe_watchdog_flush_tx - flush queues on link down
5593 * @adapter: pointer to the device adapter structure
5595 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5598 int some_tx_pending = 0;
5600 if (!netif_carrier_ok(adapter->netdev)) {
5601 for (i = 0; i < adapter->num_tx_queues; i++) {
5602 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5603 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5604 some_tx_pending = 1;
5609 if (some_tx_pending) {
5610 /* We've lost link, so the controller stops DMA,
5611 * but we've got queued Tx work that's never going
5612 * to get done, so reset controller to flush Tx.
5613 * (Do the reset outside of interrupt context).
5615 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5620 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5624 /* Do not perform spoof check for 82598 or if not in IOV mode */
5625 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
5626 adapter->num_vfs == 0)
5629 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5632 * ssvpc register is cleared on read, if zero then no
5633 * spoofed packets in the last interval.
5638 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
5642 * ixgbe_watchdog_subtask - check and bring link up
5643 * @adapter: pointer to the device adapter structure
5645 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5647 /* if interface is down do nothing */
5648 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5649 test_bit(__IXGBE_RESETTING, &adapter->state))
5652 ixgbe_watchdog_update_link(adapter);
5654 if (adapter->link_up)
5655 ixgbe_watchdog_link_is_up(adapter);
5657 ixgbe_watchdog_link_is_down(adapter);
5659 ixgbe_spoof_check(adapter);
5660 ixgbe_update_stats(adapter);
5662 ixgbe_watchdog_flush_tx(adapter);
5666 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5667 * @adapter: the ixgbe adapter structure
5669 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
5671 struct ixgbe_hw *hw = &adapter->hw;
5674 /* not searching for SFP so there is nothing to do here */
5675 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5676 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5679 /* someone else is in init, wait until next service event */
5680 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5683 err = hw->phy.ops.identify_sfp(hw);
5684 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5687 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5688 /* If no cable is present, then we need to reset
5689 * the next time we find a good cable. */
5690 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5697 /* exit if reset not needed */
5698 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5701 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
5704 * A module may be identified correctly, but the EEPROM may not have
5705 * support for that module. setup_sfp() will fail in that case, so
5706 * we should not allow that module to load.
5708 if (hw->mac.type == ixgbe_mac_82598EB)
5709 err = hw->phy.ops.reset(hw);
5711 err = hw->mac.ops.setup_sfp(hw);
5713 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5716 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5717 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5720 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5722 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5723 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5724 e_dev_err("failed to initialize because an unsupported "
5725 "SFP+ module type was detected.\n");
5726 e_dev_err("Reload the driver after installing a "
5727 "supported module.\n");
5728 unregister_netdev(adapter->netdev);
5733 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
5734 * @adapter: the ixgbe adapter structure
5736 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5738 struct ixgbe_hw *hw = &adapter->hw;
5742 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5745 /* someone else is in init, wait until next service event */
5746 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5749 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5751 autoneg = hw->phy.autoneg_advertised;
5752 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5753 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5754 if (hw->mac.ops.setup_link)
5755 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5757 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5758 adapter->link_check_timeout = jiffies;
5759 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5762 #ifdef CONFIG_PCI_IOV
5763 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5766 struct ixgbe_hw *hw = &adapter->hw;
5767 struct net_device *netdev = adapter->netdev;
5771 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5772 if (gpc) /* If incrementing then no need for the check below */
5775 * Check to see if a bad DMA write target from an errant or
5776 * malicious VF has caused a PCIe error. If so then we can
5777 * issue a VFLR to the offending VF(s) and then resume without
5778 * requesting a full slot reset.
5781 for (vf = 0; vf < adapter->num_vfs; vf++) {
5782 ciaa = (vf << 16) | 0x80000000;
5783 /* 32 bit read so align, we really want status at offset 6 */
5784 ciaa |= PCI_COMMAND;
5785 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5786 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5788 /* disable debug mode asap after reading data */
5789 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5790 /* Get the upper 16 bits which will be the PCI status reg */
5792 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5793 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5795 ciaa = (vf << 16) | 0x80000000;
5797 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5798 ciad = 0x00008000; /* VFLR */
5799 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5801 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5808 * ixgbe_service_timer - Timer Call-back
5809 * @data: pointer to adapter cast into an unsigned long
5811 static void ixgbe_service_timer(unsigned long data)
5813 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5814 unsigned long next_event_offset;
5817 /* poll faster when waiting for link */
5818 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5819 next_event_offset = HZ / 10;
5821 next_event_offset = HZ * 2;
5823 #ifdef CONFIG_PCI_IOV
5825 * don't bother with SR-IOV VF DMA hang check if there are
5826 * no VFs or the link is down
5828 if (!adapter->num_vfs ||
5829 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5830 goto normal_timer_service;
5832 /* If we have VFs allocated then we must check for DMA hangs */
5833 ixgbe_check_for_bad_vf(adapter);
5834 next_event_offset = HZ / 50;
5835 adapter->timer_event_accumulator++;
5837 if (adapter->timer_event_accumulator >= 100)
5838 adapter->timer_event_accumulator = 0;
5842 normal_timer_service:
5844 /* Reset the timer */
5845 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5848 ixgbe_service_event_schedule(adapter);
5851 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5853 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5856 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5858 /* If we're already down or resetting, just bail */
5859 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5860 test_bit(__IXGBE_RESETTING, &adapter->state))
5863 ixgbe_dump(adapter);
5864 netdev_err(adapter->netdev, "Reset adapter\n");
5865 adapter->tx_timeout_count++;
5867 ixgbe_reinit_locked(adapter);
5871 * ixgbe_service_task - manages and runs subtasks
5872 * @work: pointer to work_struct containing our data
5874 static void ixgbe_service_task(struct work_struct *work)
5876 struct ixgbe_adapter *adapter = container_of(work,
5877 struct ixgbe_adapter,
5880 ixgbe_reset_subtask(adapter);
5881 ixgbe_sfp_detection_subtask(adapter);
5882 ixgbe_sfp_link_config_subtask(adapter);
5883 ixgbe_check_overtemp_subtask(adapter);
5884 ixgbe_watchdog_subtask(adapter);
5885 ixgbe_fdir_reinit_subtask(adapter);
5886 ixgbe_check_hang_subtask(adapter);
5887 ixgbe_ptp_overflow_check(adapter);
5889 ixgbe_service_event_complete(adapter);
5892 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
5893 struct ixgbe_tx_buffer *first,
5896 struct sk_buff *skb = first->skb;
5897 u32 vlan_macip_lens, type_tucmd;
5898 u32 mss_l4len_idx, l4len;
5900 if (!skb_is_gso(skb))
5903 if (skb_header_cloned(skb)) {
5904 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5909 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5910 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
5912 if (first->protocol == __constant_htons(ETH_P_IP)) {
5913 struct iphdr *iph = ip_hdr(skb);
5916 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5920 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5921 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5922 IXGBE_TX_FLAGS_CSUM |
5923 IXGBE_TX_FLAGS_IPV4;
5924 } else if (skb_is_gso_v6(skb)) {
5925 ipv6_hdr(skb)->payload_len = 0;
5926 tcp_hdr(skb)->check =
5927 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5928 &ipv6_hdr(skb)->daddr,
5930 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5931 IXGBE_TX_FLAGS_CSUM;
5934 /* compute header lengths */
5935 l4len = tcp_hdrlen(skb);
5936 *hdr_len = skb_transport_offset(skb) + l4len;
5938 /* update gso size and bytecount with header size */
5939 first->gso_segs = skb_shinfo(skb)->gso_segs;
5940 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5942 /* mss_l4len_id: use 1 as index for TSO */
5943 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
5944 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
5945 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
5947 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
5948 vlan_macip_lens = skb_network_header_len(skb);
5949 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
5950 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
5952 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
5958 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
5959 struct ixgbe_tx_buffer *first)
5961 struct sk_buff *skb = first->skb;
5962 u32 vlan_macip_lens = 0;
5963 u32 mss_l4len_idx = 0;
5966 if (skb->ip_summed != CHECKSUM_PARTIAL) {
5967 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN)) {
5968 if (unlikely(skb->no_fcs))
5969 first->tx_flags |= IXGBE_TX_FLAGS_NO_IFCS;
5970 if (!(first->tx_flags & IXGBE_TX_FLAGS_TXSW))
5975 switch (first->protocol) {
5976 case __constant_htons(ETH_P_IP):
5977 vlan_macip_lens |= skb_network_header_len(skb);
5978 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5979 l4_hdr = ip_hdr(skb)->protocol;
5981 case __constant_htons(ETH_P_IPV6):
5982 vlan_macip_lens |= skb_network_header_len(skb);
5983 l4_hdr = ipv6_hdr(skb)->nexthdr;
5986 if (unlikely(net_ratelimit())) {
5987 dev_warn(tx_ring->dev,
5988 "partial checksum but proto=%x!\n",
5996 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5997 mss_l4len_idx = tcp_hdrlen(skb) <<
5998 IXGBE_ADVTXD_L4LEN_SHIFT;
6001 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6002 mss_l4len_idx = sizeof(struct sctphdr) <<
6003 IXGBE_ADVTXD_L4LEN_SHIFT;
6006 mss_l4len_idx = sizeof(struct udphdr) <<
6007 IXGBE_ADVTXD_L4LEN_SHIFT;
6010 if (unlikely(net_ratelimit())) {
6011 dev_warn(tx_ring->dev,
6012 "partial checksum but l4 proto=%x!\n",
6018 /* update TX checksum flag */
6019 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
6022 /* vlan_macip_lens: MACLEN, VLAN tag */
6023 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6024 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6026 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6027 type_tucmd, mss_l4len_idx);
6030 static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
6032 /* set type for advanced descriptor with frame checksum insertion */
6033 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6034 IXGBE_ADVTXD_DCMD_DEXT);
6036 /* set HW vlan bit if vlan is present */
6037 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
6038 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
6040 if (tx_flags & IXGBE_TX_FLAGS_TSTAMP)
6041 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_MAC_TSTAMP);
6043 /* set segmentation enable bits for TSO/FSO */
6045 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO))
6047 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6049 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
6051 /* insert frame checksum */
6052 if (!(tx_flags & IXGBE_TX_FLAGS_NO_IFCS))
6053 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS);
6058 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6059 u32 tx_flags, unsigned int paylen)
6061 __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
6063 /* enable L4 checksum for TSO and TX checksum offload */
6064 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6065 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
6067 /* enble IPv4 checksum for TSO */
6068 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6069 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
6071 /* use index 1 context for TSO/FSO/FCOE */
6073 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE))
6075 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6077 olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT);
6080 * Check Context must be set if Tx switch is enabled, which it
6081 * always is for case where virtual functions are running
6084 if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE))
6086 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6088 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6090 tx_desc->read.olinfo_status = olinfo_status;
6093 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6096 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6097 struct ixgbe_tx_buffer *first,
6101 struct sk_buff *skb = first->skb;
6102 struct ixgbe_tx_buffer *tx_buffer;
6103 union ixgbe_adv_tx_desc *tx_desc;
6104 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6105 unsigned int data_len = skb->data_len;
6106 unsigned int size = skb_headlen(skb);
6107 unsigned int paylen = skb->len - hdr_len;
6108 u32 tx_flags = first->tx_flags;
6110 u16 i = tx_ring->next_to_use;
6112 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6114 ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen);
6115 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6118 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6119 if (data_len < sizeof(struct fcoe_crc_eof)) {
6120 size -= sizeof(struct fcoe_crc_eof) - data_len;
6123 data_len -= sizeof(struct fcoe_crc_eof);
6128 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6129 if (dma_mapping_error(tx_ring->dev, dma))
6132 /* record length, and DMA address */
6133 dma_unmap_len_set(first, len, size);
6134 dma_unmap_addr_set(first, dma, dma);
6136 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6139 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
6140 tx_desc->read.cmd_type_len =
6141 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6145 if (i == tx_ring->count) {
6146 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6150 dma += IXGBE_MAX_DATA_PER_TXD;
6151 size -= IXGBE_MAX_DATA_PER_TXD;
6153 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6154 tx_desc->read.olinfo_status = 0;
6157 if (likely(!data_len))
6160 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6164 if (i == tx_ring->count) {
6165 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6170 size = min_t(unsigned int, data_len, skb_frag_size(frag));
6172 size = skb_frag_size(frag);
6176 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6178 if (dma_mapping_error(tx_ring->dev, dma))
6181 tx_buffer = &tx_ring->tx_buffer_info[i];
6182 dma_unmap_len_set(tx_buffer, len, size);
6183 dma_unmap_addr_set(tx_buffer, dma, dma);
6185 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6186 tx_desc->read.olinfo_status = 0;
6191 /* write last descriptor with RS and EOP bits */
6192 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD);
6193 tx_desc->read.cmd_type_len = cmd_type;
6195 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6197 /* set the timestamp */
6198 first->time_stamp = jiffies;
6201 * Force memory writes to complete before letting h/w know there
6202 * are new descriptors to fetch. (Only applicable for weak-ordered
6203 * memory model archs, such as IA-64).
6205 * We also need this memory barrier to make certain all of the
6206 * status bits have been updated before next_to_watch is written.
6210 /* set next_to_watch value indicating a packet is present */
6211 first->next_to_watch = tx_desc;
6214 if (i == tx_ring->count)
6217 tx_ring->next_to_use = i;
6219 /* notify HW of packet */
6220 writel(i, tx_ring->tail);
6224 dev_err(tx_ring->dev, "TX DMA map failed\n");
6226 /* clear dma mappings for failed tx_buffer_info map */
6228 tx_buffer = &tx_ring->tx_buffer_info[i];
6229 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6230 if (tx_buffer == first)
6237 tx_ring->next_to_use = i;
6240 static void ixgbe_atr(struct ixgbe_ring *ring,
6241 struct ixgbe_tx_buffer *first)
6243 struct ixgbe_q_vector *q_vector = ring->q_vector;
6244 union ixgbe_atr_hash_dword input = { .dword = 0 };
6245 union ixgbe_atr_hash_dword common = { .dword = 0 };
6247 unsigned char *network;
6249 struct ipv6hdr *ipv6;
6254 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6258 /* do nothing if sampling is disabled */
6259 if (!ring->atr_sample_rate)
6264 /* snag network header to get L4 type and address */
6265 hdr.network = skb_network_header(first->skb);
6267 /* Currently only IPv4/IPv6 with TCP is supported */
6268 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
6269 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6270 (first->protocol != __constant_htons(ETH_P_IP) ||
6271 hdr.ipv4->protocol != IPPROTO_TCP))
6274 th = tcp_hdr(first->skb);
6276 /* skip this packet since it is invalid or the socket is closing */
6280 /* sample on all syn packets or once every atr sample count */
6281 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6284 /* reset sample count */
6285 ring->atr_count = 0;
6287 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6290 * src and dst are inverted, think how the receiver sees them
6292 * The input is broken into two sections, a non-compressed section
6293 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6294 * is XORed together and stored in the compressed dword.
6296 input.formatted.vlan_id = vlan_id;
6299 * since src port and flex bytes occupy the same word XOR them together
6300 * and write the value to source port portion of compressed dword
6302 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6303 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6305 common.port.src ^= th->dest ^ first->protocol;
6306 common.port.dst ^= th->source;
6308 if (first->protocol == __constant_htons(ETH_P_IP)) {
6309 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6310 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6312 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6313 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6314 hdr.ipv6->saddr.s6_addr32[1] ^
6315 hdr.ipv6->saddr.s6_addr32[2] ^
6316 hdr.ipv6->saddr.s6_addr32[3] ^
6317 hdr.ipv6->daddr.s6_addr32[0] ^
6318 hdr.ipv6->daddr.s6_addr32[1] ^
6319 hdr.ipv6->daddr.s6_addr32[2] ^
6320 hdr.ipv6->daddr.s6_addr32[3];
6323 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6324 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6325 input, common, ring->queue_index);
6328 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6330 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6331 /* Herbert's original patch had:
6332 * smp_mb__after_netif_stop_queue();
6333 * but since that doesn't exist yet, just open code it. */
6336 /* We need to check again in a case another CPU has just
6337 * made room available. */
6338 if (likely(ixgbe_desc_unused(tx_ring) < size))
6341 /* A reprieve! - use start_queue because it doesn't call schedule */
6342 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6343 ++tx_ring->tx_stats.restart_queue;
6347 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6349 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6351 return __ixgbe_maybe_stop_tx(tx_ring, size);
6354 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6356 struct ixgbe_adapter *adapter = netdev_priv(dev);
6357 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6360 __be16 protocol = vlan_get_protocol(skb);
6362 if (((protocol == htons(ETH_P_FCOE)) ||
6363 (protocol == htons(ETH_P_FIP))) &&
6364 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6365 struct ixgbe_ring_feature *f;
6367 f = &adapter->ring_feature[RING_F_FCOE];
6369 while (txq >= f->indices)
6371 txq += adapter->ring_feature[RING_F_FCOE].offset;
6377 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6378 while (unlikely(txq >= dev->real_num_tx_queues))
6379 txq -= dev->real_num_tx_queues;
6383 return skb_tx_hash(dev, skb);
6386 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6387 struct ixgbe_adapter *adapter,
6388 struct ixgbe_ring *tx_ring)
6390 struct ixgbe_tx_buffer *first;
6393 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6396 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6397 __be16 protocol = skb->protocol;
6401 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6402 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
6403 * + 2 desc gap to keep tail from touching head,
6404 * + 1 desc for context descriptor,
6405 * otherwise try next time
6407 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6408 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6409 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6411 count += skb_shinfo(skb)->nr_frags;
6413 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6414 tx_ring->tx_stats.tx_busy++;
6415 return NETDEV_TX_BUSY;
6418 /* record the location of the first descriptor for this packet */
6419 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6421 first->bytecount = skb->len;
6422 first->gso_segs = 1;
6424 /* if we have a HW VLAN tag being added default to the HW one */
6425 if (vlan_tx_tag_present(skb)) {
6426 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6427 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6428 /* else if it is a SW VLAN check the next protocol and store the tag */
6429 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6430 struct vlan_hdr *vhdr, _vhdr;
6431 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6435 protocol = vhdr->h_vlan_encapsulated_proto;
6436 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6437 IXGBE_TX_FLAGS_VLAN_SHIFT;
6438 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6441 skb_tx_timestamp(skb);
6443 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6444 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6445 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
6448 #ifdef CONFIG_PCI_IOV
6450 * Use the l2switch_enable flag - would be false if the DMA
6451 * Tx switch had been disabled.
6453 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6454 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6457 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
6458 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6459 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6460 (skb->priority != TC_PRIO_CONTROL))) {
6461 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6462 tx_flags |= (skb->priority & 0x7) <<
6463 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6464 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6465 struct vlan_ethhdr *vhdr;
6466 if (skb_header_cloned(skb) &&
6467 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6469 vhdr = (struct vlan_ethhdr *)skb->data;
6470 vhdr->h_vlan_TCI = htons(tx_flags >>
6471 IXGBE_TX_FLAGS_VLAN_SHIFT);
6473 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6477 /* record initial flags and protocol */
6478 first->tx_flags = tx_flags;
6479 first->protocol = protocol;
6482 /* setup tx offload for FCoE */
6483 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6484 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
6485 tso = ixgbe_fso(tx_ring, first, &hdr_len);
6492 #endif /* IXGBE_FCOE */
6493 tso = ixgbe_tso(tx_ring, first, &hdr_len);
6497 ixgbe_tx_csum(tx_ring, first);
6499 /* add the ATR filter if ATR is on */
6500 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6501 ixgbe_atr(tx_ring, first);
6505 #endif /* IXGBE_FCOE */
6506 ixgbe_tx_map(tx_ring, first, hdr_len);
6508 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6510 return NETDEV_TX_OK;
6513 dev_kfree_skb_any(first->skb);
6516 return NETDEV_TX_OK;
6519 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6520 struct net_device *netdev)
6522 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6523 struct ixgbe_ring *tx_ring;
6526 * The minimum packet size for olinfo paylen is 17 so pad the skb
6527 * in order to meet this minimum size requirement.
6529 if (unlikely(skb->len < 17)) {
6530 if (skb_pad(skb, 17 - skb->len))
6531 return NETDEV_TX_OK;
6533 skb_set_tail_pointer(skb, 17);
6536 tx_ring = adapter->tx_ring[skb->queue_mapping];
6537 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6541 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6542 * @netdev: network interface device structure
6543 * @p: pointer to an address structure
6545 * Returns 0 on success, negative on failure
6547 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6549 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6550 struct ixgbe_hw *hw = &adapter->hw;
6551 struct sockaddr *addr = p;
6553 if (!is_valid_ether_addr(addr->sa_data))
6554 return -EADDRNOTAVAIL;
6556 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6557 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6559 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
6565 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6567 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6568 struct ixgbe_hw *hw = &adapter->hw;
6572 if (prtad != hw->phy.mdio.prtad)
6574 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6580 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6581 u16 addr, u16 value)
6583 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6584 struct ixgbe_hw *hw = &adapter->hw;
6586 if (prtad != hw->phy.mdio.prtad)
6588 return hw->phy.ops.write_reg(hw, addr, devad, value);
6591 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6593 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6597 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
6599 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6604 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6606 * @netdev: network interface device structure
6608 * Returns non-zero on failure
6610 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6613 struct ixgbe_adapter *adapter = netdev_priv(dev);
6614 struct ixgbe_hw *hw = &adapter->hw;
6616 if (is_valid_ether_addr(hw->mac.san_addr)) {
6618 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
6621 /* update SAN MAC vmdq pool selection */
6622 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
6628 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6630 * @netdev: network interface device structure
6632 * Returns non-zero on failure
6634 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6637 struct ixgbe_adapter *adapter = netdev_priv(dev);
6638 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6640 if (is_valid_ether_addr(mac->san_addr)) {
6642 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6648 #ifdef CONFIG_NET_POLL_CONTROLLER
6650 * Polling 'interrupt' - used by things like netconsole to send skbs
6651 * without having to re-enable interrupts. It's not called while
6652 * the interrupt routine is executing.
6654 static void ixgbe_netpoll(struct net_device *netdev)
6656 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6659 /* if interface is down do nothing */
6660 if (test_bit(__IXGBE_DOWN, &adapter->state))
6663 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6664 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6665 for (i = 0; i < adapter->num_q_vectors; i++)
6666 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
6668 ixgbe_intr(adapter->pdev->irq, netdev);
6670 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6674 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6675 struct rtnl_link_stats64 *stats)
6677 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6681 for (i = 0; i < adapter->num_rx_queues; i++) {
6682 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6688 start = u64_stats_fetch_begin_bh(&ring->syncp);
6689 packets = ring->stats.packets;
6690 bytes = ring->stats.bytes;
6691 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6692 stats->rx_packets += packets;
6693 stats->rx_bytes += bytes;
6697 for (i = 0; i < adapter->num_tx_queues; i++) {
6698 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6704 start = u64_stats_fetch_begin_bh(&ring->syncp);
6705 packets = ring->stats.packets;
6706 bytes = ring->stats.bytes;
6707 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6708 stats->tx_packets += packets;
6709 stats->tx_bytes += bytes;
6713 /* following stats updated by ixgbe_watchdog_task() */
6714 stats->multicast = netdev->stats.multicast;
6715 stats->rx_errors = netdev->stats.rx_errors;
6716 stats->rx_length_errors = netdev->stats.rx_length_errors;
6717 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6718 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6722 #ifdef CONFIG_IXGBE_DCB
6724 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6725 * @adapter: pointer to ixgbe_adapter
6726 * @tc: number of traffic classes currently enabled
6728 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6729 * 802.1Q priority maps to a packet buffer that exists.
6731 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6733 struct ixgbe_hw *hw = &adapter->hw;
6737 /* 82598 have a static priority to TC mapping that can not
6738 * be changed so no validation is needed.
6740 if (hw->mac.type == ixgbe_mac_82598EB)
6743 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6746 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6747 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6749 /* If up2tc is out of bounds default to zero */
6751 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6755 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6761 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
6762 * @adapter: Pointer to adapter struct
6764 * Populate the netdev user priority to tc map
6766 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
6768 struct net_device *dev = adapter->netdev;
6769 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
6770 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
6773 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
6776 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
6777 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
6779 tc = ets->prio_tc[prio];
6781 netdev_set_prio_tc_map(dev, prio, tc);
6786 * ixgbe_setup_tc - configure net_device for multiple traffic classes
6788 * @netdev: net device to configure
6789 * @tc: number of traffic classes to enable
6791 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6793 struct ixgbe_adapter *adapter = netdev_priv(dev);
6794 struct ixgbe_hw *hw = &adapter->hw;
6796 /* Hardware supports up to 8 traffic classes */
6797 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
6798 (hw->mac.type == ixgbe_mac_82598EB &&
6799 tc < MAX_TRAFFIC_CLASS))
6802 /* Hardware has to reinitialize queues and interrupts to
6803 * match packet buffer alignment. Unfortunately, the
6804 * hardware is not flexible enough to do this dynamically.
6806 if (netif_running(dev))
6808 ixgbe_clear_interrupt_scheme(adapter);
6811 netdev_set_num_tc(dev, tc);
6812 ixgbe_set_prio_tc_map(adapter);
6814 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6816 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
6817 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
6818 adapter->hw.fc.requested_mode = ixgbe_fc_none;
6821 netdev_reset_tc(dev);
6823 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6824 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
6826 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6828 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6829 adapter->dcb_cfg.pfc_mode_enable = false;
6832 ixgbe_init_interrupt_scheme(adapter);
6833 ixgbe_validate_rtr(adapter, tc);
6834 if (netif_running(dev))
6840 #endif /* CONFIG_IXGBE_DCB */
6841 void ixgbe_do_reset(struct net_device *netdev)
6843 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6845 if (netif_running(netdev))
6846 ixgbe_reinit_locked(adapter);
6848 ixgbe_reset(adapter);
6851 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
6852 netdev_features_t features)
6854 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6856 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6857 if (!(features & NETIF_F_RXCSUM))
6858 features &= ~NETIF_F_LRO;
6860 /* Turn off LRO if not RSC capable */
6861 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6862 features &= ~NETIF_F_LRO;
6867 static int ixgbe_set_features(struct net_device *netdev,
6868 netdev_features_t features)
6870 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6871 netdev_features_t changed = netdev->features ^ features;
6872 bool need_reset = false;
6874 /* Make sure RSC matches LRO, reset if change */
6875 if (!(features & NETIF_F_LRO)) {
6876 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6878 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6879 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6880 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6881 if (adapter->rx_itr_setting == 1 ||
6882 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6883 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6885 } else if ((changed ^ features) & NETIF_F_LRO) {
6886 e_info(probe, "rx-usecs set too low, "
6892 * Check if Flow Director n-tuple support was enabled or disabled. If
6893 * the state changed, we need to reset.
6895 switch (features & NETIF_F_NTUPLE) {
6896 case NETIF_F_NTUPLE:
6897 /* turn off ATR, enable perfect filters and reset */
6898 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
6901 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6902 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6905 /* turn off perfect filters, enable ATR and reset */
6906 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6909 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6911 /* We cannot enable ATR if SR-IOV is enabled */
6912 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6915 /* We cannot enable ATR if we have 2 or more traffic classes */
6916 if (netdev_get_num_tc(netdev) > 1)
6919 /* We cannot enable ATR if RSS is disabled */
6920 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
6923 /* A sample rate of 0 indicates ATR disabled */
6924 if (!adapter->atr_sample_rate)
6927 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6931 if (features & NETIF_F_HW_VLAN_RX)
6932 ixgbe_vlan_strip_enable(adapter);
6934 ixgbe_vlan_strip_disable(adapter);
6936 if (changed & NETIF_F_RXALL)
6939 netdev->features = features;
6941 ixgbe_do_reset(netdev);
6946 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
6947 struct net_device *dev,
6948 const unsigned char *addr,
6951 struct ixgbe_adapter *adapter = netdev_priv(dev);
6954 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
6957 if (ndm->ndm_state & NUD_PERMANENT) {
6958 pr_info("%s: FDB only supports static addresses\n",
6963 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
6964 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
6966 if (netdev_uc_count(dev) < rar_uc_entries)
6967 err = dev_uc_add_excl(dev, addr);
6970 } else if (is_multicast_ether_addr(addr)) {
6971 err = dev_mc_add_excl(dev, addr);
6976 /* Only return duplicate errors if NLM_F_EXCL is set */
6977 if (err == -EEXIST && !(flags & NLM_F_EXCL))
6983 static int ixgbe_ndo_fdb_del(struct ndmsg *ndm,
6984 struct net_device *dev,
6985 const unsigned char *addr)
6987 struct ixgbe_adapter *adapter = netdev_priv(dev);
6988 int err = -EOPNOTSUPP;
6990 if (ndm->ndm_state & NUD_PERMANENT) {
6991 pr_info("%s: FDB only supports static addresses\n",
6996 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6997 if (is_unicast_ether_addr(addr))
6998 err = dev_uc_del(dev, addr);
6999 else if (is_multicast_ether_addr(addr))
7000 err = dev_mc_del(dev, addr);
7008 static int ixgbe_ndo_fdb_dump(struct sk_buff *skb,
7009 struct netlink_callback *cb,
7010 struct net_device *dev,
7013 struct ixgbe_adapter *adapter = netdev_priv(dev);
7015 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7016 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
7021 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7022 struct nlmsghdr *nlh)
7024 struct ixgbe_adapter *adapter = netdev_priv(dev);
7025 struct nlattr *attr, *br_spec;
7028 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7031 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7033 nla_for_each_nested(attr, br_spec, rem) {
7037 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7040 mode = nla_get_u16(attr);
7041 if (mode == BRIDGE_MODE_VEPA)
7043 else if (mode == BRIDGE_MODE_VEB)
7044 reg = IXGBE_PFDTXGSWC_VT_LBEN;
7048 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7050 e_info(drv, "enabling bridge mode: %s\n",
7051 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7057 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7058 struct net_device *dev)
7060 struct ixgbe_adapter *adapter = netdev_priv(dev);
7063 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7066 if (IXGBE_READ_REG(&adapter->hw, IXGBE_PFDTXGSWC) & 1)
7067 mode = BRIDGE_MODE_VEB;
7069 mode = BRIDGE_MODE_VEPA;
7071 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7074 static const struct net_device_ops ixgbe_netdev_ops = {
7075 .ndo_open = ixgbe_open,
7076 .ndo_stop = ixgbe_close,
7077 .ndo_start_xmit = ixgbe_xmit_frame,
7078 .ndo_select_queue = ixgbe_select_queue,
7079 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7080 .ndo_validate_addr = eth_validate_addr,
7081 .ndo_set_mac_address = ixgbe_set_mac,
7082 .ndo_change_mtu = ixgbe_change_mtu,
7083 .ndo_tx_timeout = ixgbe_tx_timeout,
7084 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7085 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7086 .ndo_do_ioctl = ixgbe_ioctl,
7087 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7088 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7089 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7090 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7091 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7092 .ndo_get_stats64 = ixgbe_get_stats64,
7093 #ifdef CONFIG_IXGBE_DCB
7094 .ndo_setup_tc = ixgbe_setup_tc,
7096 #ifdef CONFIG_NET_POLL_CONTROLLER
7097 .ndo_poll_controller = ixgbe_netpoll,
7100 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7101 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7102 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7103 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7104 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7105 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7106 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
7107 #endif /* IXGBE_FCOE */
7108 .ndo_set_features = ixgbe_set_features,
7109 .ndo_fix_features = ixgbe_fix_features,
7110 .ndo_fdb_add = ixgbe_ndo_fdb_add,
7111 .ndo_fdb_del = ixgbe_ndo_fdb_del,
7112 .ndo_fdb_dump = ixgbe_ndo_fdb_dump,
7113 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7114 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
7118 * ixgbe_wol_supported - Check whether device supports WoL
7119 * @hw: hw specific details
7120 * @device_id: the device ID
7121 * @subdev_id: the subsystem device ID
7123 * This function is used by probe and ethtool to determine
7124 * which devices have WoL support
7127 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7130 struct ixgbe_hw *hw = &adapter->hw;
7131 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7132 int is_wol_supported = 0;
7134 switch (device_id) {
7135 case IXGBE_DEV_ID_82599_SFP:
7136 /* Only these subdevices could supports WOL */
7137 switch (subdevice_id) {
7138 case IXGBE_SUBDEV_ID_82599_560FLR:
7139 /* only support first port */
7140 if (hw->bus.func != 0)
7142 case IXGBE_SUBDEV_ID_82599_SFP:
7143 case IXGBE_SUBDEV_ID_82599_RNDC:
7144 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
7145 is_wol_supported = 1;
7149 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7150 /* All except this subdevice support WOL */
7151 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7152 is_wol_supported = 1;
7154 case IXGBE_DEV_ID_82599_KX4:
7155 is_wol_supported = 1;
7157 case IXGBE_DEV_ID_X540T:
7158 case IXGBE_DEV_ID_X540T1:
7159 /* check eeprom to see if enabled wol */
7160 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7161 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7162 (hw->bus.func == 0))) {
7163 is_wol_supported = 1;
7168 return is_wol_supported;
7172 * ixgbe_probe - Device Initialization Routine
7173 * @pdev: PCI device information struct
7174 * @ent: entry in ixgbe_pci_tbl
7176 * Returns 0 on success, negative on failure
7178 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7179 * The OS initialization, configuring of the adapter private structure,
7180 * and a hardware reset occur.
7182 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7183 const struct pci_device_id *ent)
7185 struct net_device *netdev;
7186 struct ixgbe_adapter *adapter = NULL;
7187 struct ixgbe_hw *hw;
7188 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7189 static int cards_found;
7190 int i, err, pci_using_dac;
7191 u8 part_str[IXGBE_PBANUM_LENGTH];
7192 unsigned int indices = num_possible_cpus();
7193 unsigned int dcb_max = 0;
7199 /* Catch broken hardware that put the wrong VF device ID in
7200 * the PCIe SR-IOV capability.
7202 if (pdev->is_virtfn) {
7203 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7204 pci_name(pdev), pdev->vendor, pdev->device);
7208 err = pci_enable_device_mem(pdev);
7212 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7213 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7216 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7218 err = dma_set_coherent_mask(&pdev->dev,
7222 "No usable DMA configuration, aborting\n");
7229 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7230 IORESOURCE_MEM), ixgbe_driver_name);
7233 "pci_request_selected_regions failed 0x%x\n", err);
7237 pci_enable_pcie_error_reporting(pdev);
7239 pci_set_master(pdev);
7240 pci_save_state(pdev);
7242 #ifdef CONFIG_IXGBE_DCB
7243 if (ii->mac == ixgbe_mac_82598EB)
7244 dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS,
7245 IXGBE_MAX_RSS_INDICES);
7247 dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS,
7248 IXGBE_MAX_FDIR_INDICES);
7251 if (ii->mac == ixgbe_mac_82598EB)
7252 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7254 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7257 indices += min_t(unsigned int, num_possible_cpus(),
7258 IXGBE_MAX_FCOE_INDICES);
7260 indices = max_t(unsigned int, dcb_max, indices);
7261 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7264 goto err_alloc_etherdev;
7267 SET_NETDEV_DEV(netdev, &pdev->dev);
7269 adapter = netdev_priv(netdev);
7270 pci_set_drvdata(pdev, adapter);
7272 adapter->netdev = netdev;
7273 adapter->pdev = pdev;
7276 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7278 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7279 pci_resource_len(pdev, 0));
7285 netdev->netdev_ops = &ixgbe_netdev_ops;
7286 ixgbe_set_ethtool_ops(netdev);
7287 netdev->watchdog_timeo = 5 * HZ;
7288 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7290 adapter->bd_number = cards_found;
7293 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7294 hw->mac.type = ii->mac;
7297 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7298 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7299 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7300 if (!(eec & (1 << 8)))
7301 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7304 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7305 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7306 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7307 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7308 hw->phy.mdio.mmds = 0;
7309 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7310 hw->phy.mdio.dev = netdev;
7311 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7312 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7314 ii->get_invariants(hw);
7316 /* setup the private structure */
7317 err = ixgbe_sw_init(adapter);
7321 /* Make it possible the adapter to be woken up via WOL */
7322 switch (adapter->hw.mac.type) {
7323 case ixgbe_mac_82599EB:
7324 case ixgbe_mac_X540:
7325 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7332 * If there is a fan on this device and it has failed log the
7335 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7336 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7337 if (esdp & IXGBE_ESDP_SDP1)
7338 e_crit(probe, "Fan has stopped, replace the adapter\n");
7341 if (allow_unsupported_sfp)
7342 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7344 /* reset_hw fills in the perm_addr as well */
7345 hw->phy.reset_if_overtemp = true;
7346 err = hw->mac.ops.reset_hw(hw);
7347 hw->phy.reset_if_overtemp = false;
7348 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7349 hw->mac.type == ixgbe_mac_82598EB) {
7351 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7352 e_dev_err("failed to load because an unsupported SFP+ "
7353 "module type was detected.\n");
7354 e_dev_err("Reload the driver after installing a supported "
7358 e_dev_err("HW Init failed: %d\n", err);
7362 #ifdef CONFIG_PCI_IOV
7363 ixgbe_enable_sriov(adapter, ii);
7366 netdev->features = NETIF_F_SG |
7369 NETIF_F_HW_VLAN_TX |
7370 NETIF_F_HW_VLAN_RX |
7371 NETIF_F_HW_VLAN_FILTER |
7377 netdev->hw_features = netdev->features;
7379 switch (adapter->hw.mac.type) {
7380 case ixgbe_mac_82599EB:
7381 case ixgbe_mac_X540:
7382 netdev->features |= NETIF_F_SCTP_CSUM;
7383 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7390 netdev->hw_features |= NETIF_F_RXALL;
7392 netdev->vlan_features |= NETIF_F_TSO;
7393 netdev->vlan_features |= NETIF_F_TSO6;
7394 netdev->vlan_features |= NETIF_F_IP_CSUM;
7395 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7396 netdev->vlan_features |= NETIF_F_SG;
7398 netdev->priv_flags |= IFF_UNICAST_FLT;
7399 netdev->priv_flags |= IFF_SUPP_NOFCS;
7401 #ifdef CONFIG_IXGBE_DCB
7402 netdev->dcbnl_ops = &dcbnl_ops;
7406 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7407 if (hw->mac.ops.get_device_caps) {
7408 hw->mac.ops.get_device_caps(hw, &device_caps);
7409 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7410 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7413 adapter->ring_feature[RING_F_FCOE].limit = IXGBE_FCRETA_SIZE;
7415 netdev->features |= NETIF_F_FSO |
7418 netdev->vlan_features |= NETIF_F_FSO |
7422 #endif /* IXGBE_FCOE */
7423 if (pci_using_dac) {
7424 netdev->features |= NETIF_F_HIGHDMA;
7425 netdev->vlan_features |= NETIF_F_HIGHDMA;
7428 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7429 netdev->hw_features |= NETIF_F_LRO;
7430 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7431 netdev->features |= NETIF_F_LRO;
7433 /* make sure the EEPROM is good */
7434 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7435 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7440 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7441 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7443 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7444 e_dev_err("invalid MAC address\n");
7449 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7450 (unsigned long) adapter);
7452 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7453 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7455 err = ixgbe_init_interrupt_scheme(adapter);
7459 /* WOL not supported for all devices */
7461 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7462 if (ixgbe_wol_supported(adapter, pdev->device, pdev->subsystem_device))
7463 adapter->wol = IXGBE_WUFC_MAG;
7465 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7467 /* save off EEPROM version number */
7468 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7469 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7471 /* pick up the PCI bus settings for reporting later */
7472 hw->mac.ops.get_bus_info(hw);
7474 /* print bus type/speed/width info */
7475 e_dev_info("(PCI Express:%s:%s) %pM\n",
7476 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7477 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7479 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7480 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7481 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7485 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7487 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7488 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7489 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7490 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7493 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7494 hw->mac.type, hw->phy.type, part_str);
7496 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7497 e_dev_warn("PCI-Express bandwidth available for this card is "
7498 "not sufficient for optimal performance.\n");
7499 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7503 /* reset the hardware with the new settings */
7504 err = hw->mac.ops.start_hw(hw);
7505 if (err == IXGBE_ERR_EEPROM_VERSION) {
7506 /* We are running on a pre-production device, log a warning */
7507 e_dev_warn("This device is a pre-production adapter/LOM. "
7508 "Please be aware there may be issues associated "
7509 "with your hardware. If you are experiencing "
7510 "problems please contact your Intel or hardware "
7511 "representative who provided you with this "
7514 strcpy(netdev->name, "eth%d");
7515 err = register_netdev(netdev);
7519 /* power down the optics for 82599 SFP+ fiber */
7520 if (hw->mac.ops.disable_tx_laser)
7521 hw->mac.ops.disable_tx_laser(hw);
7523 /* carrier off reporting is important to ethtool even BEFORE open */
7524 netif_carrier_off(netdev);
7526 #ifdef CONFIG_IXGBE_DCA
7527 if (dca_add_requester(&pdev->dev) == 0) {
7528 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7529 ixgbe_setup_dca(adapter);
7532 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7533 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7534 for (i = 0; i < adapter->num_vfs; i++)
7535 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7538 /* firmware requires driver version to be 0xFFFFFFFF
7539 * since os does not support feature
7541 if (hw->mac.ops.set_fw_drv_ver)
7542 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7545 /* add san mac addr to netdev */
7546 ixgbe_add_sanmac_netdev(netdev);
7548 e_dev_info("%s\n", ixgbe_default_device_descr);
7551 #ifdef CONFIG_IXGBE_HWMON
7552 if (ixgbe_sysfs_init(adapter))
7553 e_err(probe, "failed to allocate sysfs resources\n");
7554 #endif /* CONFIG_IXGBE_HWMON */
7556 #ifdef CONFIG_DEBUG_FS
7557 ixgbe_dbg_adapter_init(adapter);
7558 #endif /* CONFIG_DEBUG_FS */
7563 ixgbe_release_hw_control(adapter);
7564 ixgbe_clear_interrupt_scheme(adapter);
7566 ixgbe_disable_sriov(adapter);
7567 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7568 iounmap(hw->hw_addr);
7570 free_netdev(netdev);
7572 pci_release_selected_regions(pdev,
7573 pci_select_bars(pdev, IORESOURCE_MEM));
7576 pci_disable_device(pdev);
7581 * ixgbe_remove - Device Removal Routine
7582 * @pdev: PCI device information struct
7584 * ixgbe_remove is called by the PCI subsystem to alert the driver
7585 * that it should release a PCI device. The could be caused by a
7586 * Hot-Plug event, or because the driver is going to be removed from
7589 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7591 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7592 struct net_device *netdev = adapter->netdev;
7594 #ifdef CONFIG_DEBUG_FS
7595 ixgbe_dbg_adapter_exit(adapter);
7596 #endif /*CONFIG_DEBUG_FS */
7598 set_bit(__IXGBE_DOWN, &adapter->state);
7599 cancel_work_sync(&adapter->service_task);
7602 #ifdef CONFIG_IXGBE_DCA
7603 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7604 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7605 dca_remove_requester(&pdev->dev);
7606 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7610 #ifdef CONFIG_IXGBE_HWMON
7611 ixgbe_sysfs_exit(adapter);
7612 #endif /* CONFIG_IXGBE_HWMON */
7614 /* remove the added san mac */
7615 ixgbe_del_sanmac_netdev(netdev);
7617 if (netdev->reg_state == NETREG_REGISTERED)
7618 unregister_netdev(netdev);
7620 ixgbe_disable_sriov(adapter);
7622 ixgbe_clear_interrupt_scheme(adapter);
7624 ixgbe_release_hw_control(adapter);
7627 kfree(adapter->ixgbe_ieee_pfc);
7628 kfree(adapter->ixgbe_ieee_ets);
7631 iounmap(adapter->hw.hw_addr);
7632 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7635 e_dev_info("complete\n");
7637 free_netdev(netdev);
7639 pci_disable_pcie_error_reporting(pdev);
7641 pci_disable_device(pdev);
7645 * ixgbe_io_error_detected - called when PCI error is detected
7646 * @pdev: Pointer to PCI device
7647 * @state: The current pci connection state
7649 * This function is called after a PCI bus error affecting
7650 * this device has been detected.
7652 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7653 pci_channel_state_t state)
7655 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7656 struct net_device *netdev = adapter->netdev;
7658 #ifdef CONFIG_PCI_IOV
7659 struct pci_dev *bdev, *vfdev;
7660 u32 dw0, dw1, dw2, dw3;
7662 u16 req_id, pf_func;
7664 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7665 adapter->num_vfs == 0)
7666 goto skip_bad_vf_detection;
7668 bdev = pdev->bus->self;
7669 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
7670 bdev = bdev->bus->self;
7673 goto skip_bad_vf_detection;
7675 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7677 goto skip_bad_vf_detection;
7679 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7680 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7681 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7682 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7685 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7686 if (!(req_id & 0x0080))
7687 goto skip_bad_vf_detection;
7689 pf_func = req_id & 0x01;
7690 if ((pf_func & 1) == (pdev->devfn & 1)) {
7691 unsigned int device_id;
7693 vf = (req_id & 0x7F) >> 1;
7694 e_dev_err("VF %d has caused a PCIe error\n", vf);
7695 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7696 "%8.8x\tdw3: %8.8x\n",
7697 dw0, dw1, dw2, dw3);
7698 switch (adapter->hw.mac.type) {
7699 case ixgbe_mac_82599EB:
7700 device_id = IXGBE_82599_VF_DEVICE_ID;
7702 case ixgbe_mac_X540:
7703 device_id = IXGBE_X540_VF_DEVICE_ID;
7710 /* Find the pci device of the offending VF */
7711 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
7713 if (vfdev->devfn == (req_id & 0xFF))
7715 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
7719 * There's a slim chance the VF could have been hot plugged,
7720 * so if it is no longer present we don't need to issue the
7721 * VFLR. Just clean up the AER in that case.
7724 e_dev_err("Issuing VFLR to VF %d\n", vf);
7725 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7728 pci_cleanup_aer_uncorrect_error_status(pdev);
7732 * Even though the error may have occurred on the other port
7733 * we still need to increment the vf error reference count for
7734 * both ports because the I/O resume function will be called
7737 adapter->vferr_refcount++;
7739 return PCI_ERS_RESULT_RECOVERED;
7741 skip_bad_vf_detection:
7742 #endif /* CONFIG_PCI_IOV */
7743 netif_device_detach(netdev);
7745 if (state == pci_channel_io_perm_failure)
7746 return PCI_ERS_RESULT_DISCONNECT;
7748 if (netif_running(netdev))
7749 ixgbe_down(adapter);
7750 pci_disable_device(pdev);
7752 /* Request a slot reset. */
7753 return PCI_ERS_RESULT_NEED_RESET;
7757 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7758 * @pdev: Pointer to PCI device
7760 * Restart the card from scratch, as if from a cold-boot.
7762 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7764 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7765 pci_ers_result_t result;
7768 if (pci_enable_device_mem(pdev)) {
7769 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7770 result = PCI_ERS_RESULT_DISCONNECT;
7772 pci_set_master(pdev);
7773 pci_restore_state(pdev);
7774 pci_save_state(pdev);
7776 pci_wake_from_d3(pdev, false);
7778 ixgbe_reset(adapter);
7779 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7780 result = PCI_ERS_RESULT_RECOVERED;
7783 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7785 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7786 "failed 0x%0x\n", err);
7787 /* non-fatal, continue */
7794 * ixgbe_io_resume - called when traffic can start flowing again.
7795 * @pdev: Pointer to PCI device
7797 * This callback is called when the error recovery driver tells us that
7798 * its OK to resume normal operation.
7800 static void ixgbe_io_resume(struct pci_dev *pdev)
7802 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7803 struct net_device *netdev = adapter->netdev;
7805 #ifdef CONFIG_PCI_IOV
7806 if (adapter->vferr_refcount) {
7807 e_info(drv, "Resuming after VF err\n");
7808 adapter->vferr_refcount--;
7813 if (netif_running(netdev))
7816 netif_device_attach(netdev);
7819 static const struct pci_error_handlers ixgbe_err_handler = {
7820 .error_detected = ixgbe_io_error_detected,
7821 .slot_reset = ixgbe_io_slot_reset,
7822 .resume = ixgbe_io_resume,
7825 static struct pci_driver ixgbe_driver = {
7826 .name = ixgbe_driver_name,
7827 .id_table = ixgbe_pci_tbl,
7828 .probe = ixgbe_probe,
7829 .remove = __devexit_p(ixgbe_remove),
7831 .suspend = ixgbe_suspend,
7832 .resume = ixgbe_resume,
7834 .shutdown = ixgbe_shutdown,
7835 .err_handler = &ixgbe_err_handler
7839 * ixgbe_init_module - Driver Registration Routine
7841 * ixgbe_init_module is the first routine called when the driver is
7842 * loaded. All it does is register with the PCI subsystem.
7844 static int __init ixgbe_init_module(void)
7847 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7848 pr_info("%s\n", ixgbe_copyright);
7850 #ifdef CONFIG_DEBUG_FS
7852 #endif /* CONFIG_DEBUG_FS */
7854 #ifdef CONFIG_IXGBE_DCA
7855 dca_register_notify(&dca_notifier);
7858 ret = pci_register_driver(&ixgbe_driver);
7862 module_init(ixgbe_init_module);
7865 * ixgbe_exit_module - Driver Exit Cleanup Routine
7867 * ixgbe_exit_module is called just before the driver is removed
7870 static void __exit ixgbe_exit_module(void)
7872 #ifdef CONFIG_IXGBE_DCA
7873 dca_unregister_notify(&dca_notifier);
7875 pci_unregister_driver(&ixgbe_driver);
7877 #ifdef CONFIG_DEBUG_FS
7879 #endif /* CONFIG_DEBUG_FS */
7881 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7884 #ifdef CONFIG_IXGBE_DCA
7885 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7890 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7891 __ixgbe_notify_dca);
7893 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7896 #endif /* CONFIG_IXGBE_DCA */
7898 module_exit(ixgbe_exit_module);