1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
35 #include <linux/interrupt.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
46 #include <linux/if_vlan.h>
47 #include <linux/prefetch.h>
48 #include <scsi/fc/fc_fcoe.h>
51 #include "ixgbe_common.h"
52 #include "ixgbe_dcb_82599.h"
53 #include "ixgbe_sriov.h"
55 char ixgbe_driver_name[] = "ixgbe";
56 static const char ixgbe_driver_string[] =
57 "Intel(R) 10 Gigabit PCI Express Network Driver";
58 char ixgbe_default_device_descr[] =
59 "Intel(R) 10 Gigabit Network Connection";
63 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
64 __stringify(BUILD) "-k"
65 const char ixgbe_driver_version[] = DRV_VERSION;
66 static const char ixgbe_copyright[] =
67 "Copyright (c) 1999-2012 Intel Corporation.";
69 static const struct ixgbe_info *ixgbe_info_tbl[] = {
70 [board_82598] = &ixgbe_82598_info,
71 [board_82599] = &ixgbe_82599_info,
72 [board_X540] = &ixgbe_X540_info,
75 /* ixgbe_pci_tbl - PCI Device ID Table
77 * Wildcard entries (PCI_ANY_ID) should come last
78 * Last entry must be all 0s
80 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
81 * Class, Class Mask, private data (not used) }
83 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
112 /* required last entry */
115 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
117 #ifdef CONFIG_IXGBE_DCA
118 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
120 static struct notifier_block dca_notifier = {
121 .notifier_call = ixgbe_notify_dca,
127 #ifdef CONFIG_PCI_IOV
128 static unsigned int max_vfs;
129 module_param(max_vfs, uint, 0);
130 MODULE_PARM_DESC(max_vfs,
131 "Maximum number of virtual functions to allocate per physical function");
132 #endif /* CONFIG_PCI_IOV */
134 static unsigned int allow_unsupported_sfp;
135 module_param(allow_unsupported_sfp, uint, 0);
136 MODULE_PARM_DESC(allow_unsupported_sfp,
137 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
139 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
140 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
141 MODULE_LICENSE("GPL");
142 MODULE_VERSION(DRV_VERSION);
144 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
146 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
148 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
149 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
150 schedule_work(&adapter->service_task);
153 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
155 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
157 /* flush memory to make sure state is correct before next watchdog */
158 smp_mb__before_clear_bit();
159 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
162 struct ixgbe_reg_info {
167 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
169 /* General Registers */
170 {IXGBE_CTRL, "CTRL"},
171 {IXGBE_STATUS, "STATUS"},
172 {IXGBE_CTRL_EXT, "CTRL_EXT"},
174 /* Interrupt Registers */
175 {IXGBE_EICR, "EICR"},
178 {IXGBE_SRRCTL(0), "SRRCTL"},
179 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
180 {IXGBE_RDLEN(0), "RDLEN"},
181 {IXGBE_RDH(0), "RDH"},
182 {IXGBE_RDT(0), "RDT"},
183 {IXGBE_RXDCTL(0), "RXDCTL"},
184 {IXGBE_RDBAL(0), "RDBAL"},
185 {IXGBE_RDBAH(0), "RDBAH"},
188 {IXGBE_TDBAL(0), "TDBAL"},
189 {IXGBE_TDBAH(0), "TDBAH"},
190 {IXGBE_TDLEN(0), "TDLEN"},
191 {IXGBE_TDH(0), "TDH"},
192 {IXGBE_TDT(0), "TDT"},
193 {IXGBE_TXDCTL(0), "TXDCTL"},
195 /* List Terminator */
201 * ixgbe_regdump - register printout routine
203 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
209 switch (reginfo->ofs) {
210 case IXGBE_SRRCTL(0):
211 for (i = 0; i < 64; i++)
212 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
214 case IXGBE_DCA_RXCTRL(0):
215 for (i = 0; i < 64; i++)
216 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
219 for (i = 0; i < 64; i++)
220 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
223 for (i = 0; i < 64; i++)
224 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
227 for (i = 0; i < 64; i++)
228 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
230 case IXGBE_RXDCTL(0):
231 for (i = 0; i < 64; i++)
232 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
235 for (i = 0; i < 64; i++)
236 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
239 for (i = 0; i < 64; i++)
240 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
243 for (i = 0; i < 64; i++)
244 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
247 for (i = 0; i < 64; i++)
248 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
251 for (i = 0; i < 64; i++)
252 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
255 for (i = 0; i < 64; i++)
256 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
259 for (i = 0; i < 64; i++)
260 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
262 case IXGBE_TXDCTL(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
267 pr_info("%-15s %08x\n", reginfo->name,
268 IXGBE_READ_REG(hw, reginfo->ofs));
272 for (i = 0; i < 8; i++) {
273 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
274 pr_err("%-15s", rname);
275 for (j = 0; j < 8; j++)
276 pr_cont(" %08x", regs[i*8+j]);
283 * ixgbe_dump - Print registers, tx-rings and rx-rings
285 static void ixgbe_dump(struct ixgbe_adapter *adapter)
287 struct net_device *netdev = adapter->netdev;
288 struct ixgbe_hw *hw = &adapter->hw;
289 struct ixgbe_reg_info *reginfo;
291 struct ixgbe_ring *tx_ring;
292 struct ixgbe_tx_buffer *tx_buffer_info;
293 union ixgbe_adv_tx_desc *tx_desc;
294 struct my_u0 { u64 a; u64 b; } *u0;
295 struct ixgbe_ring *rx_ring;
296 union ixgbe_adv_rx_desc *rx_desc;
297 struct ixgbe_rx_buffer *rx_buffer_info;
301 if (!netif_msg_hw(adapter))
304 /* Print netdevice Info */
306 dev_info(&adapter->pdev->dev, "Net device Info\n");
307 pr_info("Device Name state "
308 "trans_start last_rx\n");
309 pr_info("%-15s %016lX %016lX %016lX\n",
316 /* Print Registers */
317 dev_info(&adapter->pdev->dev, "Register Dump\n");
318 pr_info(" Register Name Value\n");
319 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
320 reginfo->name; reginfo++) {
321 ixgbe_regdump(hw, reginfo);
324 /* Print TX Ring Summary */
325 if (!netdev || !netif_running(netdev))
328 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
329 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
330 for (n = 0; n < adapter->num_tx_queues; n++) {
331 tx_ring = adapter->tx_ring[n];
333 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
334 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
335 n, tx_ring->next_to_use, tx_ring->next_to_clean,
336 (u64)tx_buffer_info->dma,
337 tx_buffer_info->length,
338 tx_buffer_info->next_to_watch,
339 (u64)tx_buffer_info->time_stamp);
343 if (!netif_msg_tx_done(adapter))
344 goto rx_ring_summary;
346 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
348 /* Transmit Descriptor Formats
350 * Advanced Transmit Descriptor
351 * +--------------------------------------------------------------+
352 * 0 | Buffer Address [63:0] |
353 * +--------------------------------------------------------------+
354 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
355 * +--------------------------------------------------------------+
356 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
359 for (n = 0; n < adapter->num_tx_queues; n++) {
360 tx_ring = adapter->tx_ring[n];
361 pr_info("------------------------------------\n");
362 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
363 pr_info("------------------------------------\n");
364 pr_info("T [desc] [address 63:0 ] "
365 "[PlPOIdStDDt Ln] [bi->dma ] "
366 "leng ntw timestamp bi->skb\n");
368 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
369 tx_desc = IXGBE_TX_DESC(tx_ring, i);
370 tx_buffer_info = &tx_ring->tx_buffer_info[i];
371 u0 = (struct my_u0 *)tx_desc;
372 pr_info("T [0x%03X] %016llX %016llX %016llX"
373 " %04X %p %016llX %p", i,
376 (u64)tx_buffer_info->dma,
377 tx_buffer_info->length,
378 tx_buffer_info->next_to_watch,
379 (u64)tx_buffer_info->time_stamp,
380 tx_buffer_info->skb);
381 if (i == tx_ring->next_to_use &&
382 i == tx_ring->next_to_clean)
384 else if (i == tx_ring->next_to_use)
386 else if (i == tx_ring->next_to_clean)
391 if (netif_msg_pktdata(adapter) &&
392 tx_buffer_info->dma != 0)
393 print_hex_dump(KERN_INFO, "",
394 DUMP_PREFIX_ADDRESS, 16, 1,
395 phys_to_virt(tx_buffer_info->dma),
396 tx_buffer_info->length, true);
400 /* Print RX Rings Summary */
402 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
403 pr_info("Queue [NTU] [NTC]\n");
404 for (n = 0; n < adapter->num_rx_queues; n++) {
405 rx_ring = adapter->rx_ring[n];
406 pr_info("%5d %5X %5X\n",
407 n, rx_ring->next_to_use, rx_ring->next_to_clean);
411 if (!netif_msg_rx_status(adapter))
414 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
416 /* Advanced Receive Descriptor (Read) Format
418 * +-----------------------------------------------------+
419 * 0 | Packet Buffer Address [63:1] |A0/NSE|
420 * +----------------------------------------------+------+
421 * 8 | Header Buffer Address [63:1] | DD |
422 * +-----------------------------------------------------+
425 * Advanced Receive Descriptor (Write-Back) Format
427 * 63 48 47 32 31 30 21 20 16 15 4 3 0
428 * +------------------------------------------------------+
429 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
430 * | Checksum Ident | | | | Type | Type |
431 * +------------------------------------------------------+
432 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
433 * +------------------------------------------------------+
434 * 63 48 47 32 31 20 19 0
436 for (n = 0; n < adapter->num_rx_queues; n++) {
437 rx_ring = adapter->rx_ring[n];
438 pr_info("------------------------------------\n");
439 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
440 pr_info("------------------------------------\n");
441 pr_info("R [desc] [ PktBuf A0] "
442 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
443 "<-- Adv Rx Read format\n");
444 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
445 "[vl er S cks ln] ---------------- [bi->skb] "
446 "<-- Adv Rx Write-Back format\n");
448 for (i = 0; i < rx_ring->count; i++) {
449 rx_buffer_info = &rx_ring->rx_buffer_info[i];
450 rx_desc = IXGBE_RX_DESC(rx_ring, i);
451 u0 = (struct my_u0 *)rx_desc;
452 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
453 if (staterr & IXGBE_RXD_STAT_DD) {
454 /* Descriptor Done */
455 pr_info("RWB[0x%03X] %016llX "
456 "%016llX ---------------- %p", i,
459 rx_buffer_info->skb);
461 pr_info("R [0x%03X] %016llX "
462 "%016llX %016llX %p", i,
465 (u64)rx_buffer_info->dma,
466 rx_buffer_info->skb);
468 if (netif_msg_pktdata(adapter)) {
469 print_hex_dump(KERN_INFO, "",
470 DUMP_PREFIX_ADDRESS, 16, 1,
471 phys_to_virt(rx_buffer_info->dma),
472 rx_ring->rx_buf_len, true);
474 if (rx_ring->rx_buf_len
476 print_hex_dump(KERN_INFO, "",
477 DUMP_PREFIX_ADDRESS, 16, 1,
479 rx_buffer_info->page_dma +
480 rx_buffer_info->page_offset
486 if (i == rx_ring->next_to_use)
488 else if (i == rx_ring->next_to_clean)
500 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
504 /* Let firmware take over control of h/w */
505 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
506 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
507 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
510 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
514 /* Let firmware know the driver has taken over */
515 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
516 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
517 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
521 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
522 * @adapter: pointer to adapter struct
523 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
524 * @queue: queue to map the corresponding interrupt to
525 * @msix_vector: the vector to map to the corresponding queue
528 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
529 u8 queue, u8 msix_vector)
532 struct ixgbe_hw *hw = &adapter->hw;
533 switch (hw->mac.type) {
534 case ixgbe_mac_82598EB:
535 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
538 index = (((direction * 64) + queue) >> 2) & 0x1F;
539 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
540 ivar &= ~(0xFF << (8 * (queue & 0x3)));
541 ivar |= (msix_vector << (8 * (queue & 0x3)));
542 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
544 case ixgbe_mac_82599EB:
546 if (direction == -1) {
548 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
549 index = ((queue & 1) * 8);
550 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
551 ivar &= ~(0xFF << index);
552 ivar |= (msix_vector << index);
553 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
556 /* tx or rx causes */
557 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
558 index = ((16 * (queue & 1)) + (8 * direction));
559 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
560 ivar &= ~(0xFF << index);
561 ivar |= (msix_vector << index);
562 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
570 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
575 switch (adapter->hw.mac.type) {
576 case ixgbe_mac_82598EB:
577 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
578 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
580 case ixgbe_mac_82599EB:
582 mask = (qmask & 0xFFFFFFFF);
583 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
584 mask = (qmask >> 32);
585 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
592 static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
593 struct ixgbe_tx_buffer *tx_buffer)
595 if (tx_buffer->dma) {
596 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
597 dma_unmap_page(ring->dev,
602 dma_unmap_single(ring->dev,
610 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
611 struct ixgbe_tx_buffer *tx_buffer_info)
613 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
614 if (tx_buffer_info->skb)
615 dev_kfree_skb_any(tx_buffer_info->skb);
616 tx_buffer_info->skb = NULL;
617 /* tx_buffer_info must be completely set up in the transmit path */
620 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
622 struct ixgbe_hw *hw = &adapter->hw;
623 struct ixgbe_hw_stats *hwstats = &adapter->stats;
628 if ((hw->fc.current_mode == ixgbe_fc_full) ||
629 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
630 switch (hw->mac.type) {
631 case ixgbe_mac_82598EB:
632 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
635 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
637 hwstats->lxoffrxc += data;
639 /* refill credits (no tx hang) if we received xoff */
643 for (i = 0; i < adapter->num_tx_queues; i++)
644 clear_bit(__IXGBE_HANG_CHECK_ARMED,
645 &adapter->tx_ring[i]->state);
647 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
650 /* update stats for each tc, only valid with PFC enabled */
651 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
652 switch (hw->mac.type) {
653 case ixgbe_mac_82598EB:
654 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
657 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
659 hwstats->pxoffrxc[i] += xoff[i];
662 /* disarm tx queues that have received xoff frames */
663 for (i = 0; i < adapter->num_tx_queues; i++) {
664 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
665 u8 tc = tx_ring->dcb_tc;
668 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
672 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
674 return ring->tx_stats.completed;
677 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
679 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
680 struct ixgbe_hw *hw = &adapter->hw;
682 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
683 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
686 return (head < tail) ?
687 tail - head : (tail + ring->count - head);
692 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
694 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
695 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
696 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
699 clear_check_for_tx_hang(tx_ring);
702 * Check for a hung queue, but be thorough. This verifies
703 * that a transmit has been completed since the previous
704 * check AND there is at least one packet pending. The
705 * ARMED bit is set to indicate a potential hang. The
706 * bit is cleared if a pause frame is received to remove
707 * false hang detection due to PFC or 802.3x frames. By
708 * requiring this to fail twice we avoid races with
709 * pfc clearing the ARMED bit and conditions where we
710 * run the check_tx_hang logic with a transmit completion
711 * pending but without time to complete it yet.
713 if ((tx_done_old == tx_done) && tx_pending) {
714 /* make sure it is true for two checks in a row */
715 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
718 /* update completed stats and continue */
719 tx_ring->tx_stats.tx_done_old = tx_done;
720 /* reset the countdown */
721 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
728 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
729 * @adapter: driver private struct
731 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
734 /* Do the reset outside of interrupt context */
735 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
736 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
737 ixgbe_service_event_schedule(adapter);
742 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
743 * @q_vector: structure containing interrupt and ring information
744 * @tx_ring: tx ring to clean
746 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
747 struct ixgbe_ring *tx_ring)
749 struct ixgbe_adapter *adapter = q_vector->adapter;
750 struct ixgbe_tx_buffer *tx_buffer;
751 union ixgbe_adv_tx_desc *tx_desc;
752 unsigned int total_bytes = 0, total_packets = 0;
753 unsigned int budget = q_vector->tx.work_limit;
754 u16 i = tx_ring->next_to_clean;
756 tx_buffer = &tx_ring->tx_buffer_info[i];
757 tx_desc = IXGBE_TX_DESC(tx_ring, i);
759 for (; budget; budget--) {
760 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
762 /* if next_to_watch is not set then there is no work pending */
766 /* if DD is not set pending work has not been completed */
767 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
770 /* count the packet as being completed */
771 tx_ring->tx_stats.completed++;
773 /* clear next_to_watch to prevent false hangs */
774 tx_buffer->next_to_watch = NULL;
776 /* prevent any other reads prior to eop_desc being verified */
780 ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
781 tx_desc->wb.status = 0;
782 if (likely(tx_desc == eop_desc)) {
784 dev_kfree_skb_any(tx_buffer->skb);
785 tx_buffer->skb = NULL;
787 total_bytes += tx_buffer->bytecount;
788 total_packets += tx_buffer->gso_segs;
794 if (unlikely(i == tx_ring->count)) {
797 tx_buffer = tx_ring->tx_buffer_info;
798 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
804 tx_ring->next_to_clean = i;
805 u64_stats_update_begin(&tx_ring->syncp);
806 tx_ring->stats.bytes += total_bytes;
807 tx_ring->stats.packets += total_packets;
808 u64_stats_update_end(&tx_ring->syncp);
809 q_vector->tx.total_bytes += total_bytes;
810 q_vector->tx.total_packets += total_packets;
812 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
813 /* schedule immediate reset if we believe we hung */
814 struct ixgbe_hw *hw = &adapter->hw;
815 tx_desc = IXGBE_TX_DESC(tx_ring, i);
816 e_err(drv, "Detected Tx Unit Hang\n"
818 " TDH, TDT <%x>, <%x>\n"
819 " next_to_use <%x>\n"
820 " next_to_clean <%x>\n"
821 "tx_buffer_info[next_to_clean]\n"
822 " time_stamp <%lx>\n"
824 tx_ring->queue_index,
825 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
826 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
827 tx_ring->next_to_use, i,
828 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
830 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
833 "tx hang %d detected on queue %d, resetting adapter\n",
834 adapter->tx_timeout_count + 1, tx_ring->queue_index);
836 /* schedule immediate reset if we believe we hung */
837 ixgbe_tx_timeout_reset(adapter);
839 /* the adapter is about to reset, no point in enabling stuff */
843 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
844 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
845 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
846 /* Make sure that anybody stopping the queue after this
847 * sees the new next_to_clean.
850 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
851 !test_bit(__IXGBE_DOWN, &adapter->state)) {
852 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
853 ++tx_ring->tx_stats.restart_queue;
860 #ifdef CONFIG_IXGBE_DCA
861 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
862 struct ixgbe_ring *rx_ring,
865 struct ixgbe_hw *hw = &adapter->hw;
867 u8 reg_idx = rx_ring->reg_idx;
869 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
870 switch (hw->mac.type) {
871 case ixgbe_mac_82598EB:
872 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
873 rxctrl |= dca3_get_tag(rx_ring->dev, cpu);
875 case ixgbe_mac_82599EB:
877 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
878 rxctrl |= (dca3_get_tag(rx_ring->dev, cpu) <<
879 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
884 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
885 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
886 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
887 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
890 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
891 struct ixgbe_ring *tx_ring,
894 struct ixgbe_hw *hw = &adapter->hw;
896 u8 reg_idx = tx_ring->reg_idx;
898 switch (hw->mac.type) {
899 case ixgbe_mac_82598EB:
900 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
901 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
902 txctrl |= dca3_get_tag(tx_ring->dev, cpu);
903 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
904 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
906 case ixgbe_mac_82599EB:
908 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
909 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
910 txctrl |= (dca3_get_tag(tx_ring->dev, cpu) <<
911 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
912 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
913 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
920 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
922 struct ixgbe_adapter *adapter = q_vector->adapter;
923 struct ixgbe_ring *ring;
926 if (q_vector->cpu == cpu)
929 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
930 ixgbe_update_tx_dca(adapter, ring, cpu);
932 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
933 ixgbe_update_rx_dca(adapter, ring, cpu);
940 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
945 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
948 /* always use CB2 mode, difference is masked in the CB driver */
949 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
951 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
952 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
956 for (i = 0; i < num_q_vectors; i++) {
957 adapter->q_vector[i]->cpu = -1;
958 ixgbe_update_dca(adapter->q_vector[i]);
962 static int __ixgbe_notify_dca(struct device *dev, void *data)
964 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
965 unsigned long event = *(unsigned long *)data;
967 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
971 case DCA_PROVIDER_ADD:
972 /* if we're already enabled, don't do it again */
973 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
975 if (dca_add_requester(dev) == 0) {
976 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
977 ixgbe_setup_dca(adapter);
980 /* Fall Through since DCA is disabled. */
981 case DCA_PROVIDER_REMOVE:
982 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
983 dca_remove_requester(dev);
984 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
985 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
992 #endif /* CONFIG_IXGBE_DCA */
994 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
995 union ixgbe_adv_rx_desc *rx_desc,
998 if (ring->netdev->features & NETIF_F_RXHASH)
999 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1003 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1004 * @adapter: address of board private structure
1005 * @rx_desc: advanced rx descriptor
1007 * Returns : true if it is FCoE pkt
1009 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1010 union ixgbe_adv_rx_desc *rx_desc)
1012 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1014 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1015 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1016 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1017 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1021 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1022 * @ring: structure containing ring specific data
1023 * @rx_desc: current Rx descriptor being processed
1024 * @skb: skb currently being received and modified
1026 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1027 union ixgbe_adv_rx_desc *rx_desc,
1028 struct sk_buff *skb)
1030 skb_checksum_none_assert(skb);
1032 /* Rx csum disabled */
1033 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1036 /* if IP and error */
1037 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1038 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1039 ring->rx_stats.csum_err++;
1043 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1046 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1047 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1050 * 82599 errata, UDP frames with a 0 checksum can be marked as
1053 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1054 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1057 ring->rx_stats.csum_err++;
1061 /* It must be a TCP or UDP packet with a valid checksum */
1062 skb->ip_summed = CHECKSUM_UNNECESSARY;
1065 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1067 rx_ring->next_to_use = val;
1069 * Force memory writes to complete before letting h/w
1070 * know there are new descriptors to fetch. (Only
1071 * applicable for weak-ordered memory model archs,
1075 writel(val, rx_ring->tail);
1078 static bool ixgbe_alloc_mapped_skb(struct ixgbe_ring *rx_ring,
1079 struct ixgbe_rx_buffer *bi)
1081 struct sk_buff *skb = bi->skb;
1082 dma_addr_t dma = bi->dma;
1088 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1089 rx_ring->rx_buf_len);
1092 rx_ring->rx_stats.alloc_rx_buff_failed++;
1097 dma = dma_map_single(rx_ring->dev, skb->data,
1098 rx_ring->rx_buf_len, DMA_FROM_DEVICE);
1100 if (dma_mapping_error(rx_ring->dev, dma)) {
1101 rx_ring->rx_stats.alloc_rx_buff_failed++;
1109 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1110 struct ixgbe_rx_buffer *bi)
1112 struct page *page = bi->page;
1113 dma_addr_t page_dma = bi->page_dma;
1114 unsigned int page_offset = bi->page_offset ^ (PAGE_SIZE / 2);
1120 page = alloc_page(GFP_ATOMIC | __GFP_COLD);
1122 if (unlikely(!page)) {
1123 rx_ring->rx_stats.alloc_rx_page_failed++;
1128 page_dma = dma_map_page(rx_ring->dev, page,
1129 page_offset, PAGE_SIZE / 2,
1132 if (dma_mapping_error(rx_ring->dev, page_dma)) {
1133 rx_ring->rx_stats.alloc_rx_page_failed++;
1137 bi->page_dma = page_dma;
1138 bi->page_offset = page_offset;
1143 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1144 * @rx_ring: ring to place buffers on
1145 * @cleaned_count: number of buffers to replace
1147 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1149 union ixgbe_adv_rx_desc *rx_desc;
1150 struct ixgbe_rx_buffer *bi;
1151 u16 i = rx_ring->next_to_use;
1153 /* nothing to do or no valid netdev defined */
1154 if (!cleaned_count || !rx_ring->netdev)
1157 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1158 bi = &rx_ring->rx_buffer_info[i];
1159 i -= rx_ring->count;
1161 while (cleaned_count--) {
1162 if (!ixgbe_alloc_mapped_skb(rx_ring, bi))
1165 /* Refresh the desc even if buffer_addrs didn't change
1166 * because each write-back erases this info. */
1167 if (ring_is_ps_enabled(rx_ring)) {
1168 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1170 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1173 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1175 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1182 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1183 bi = rx_ring->rx_buffer_info;
1184 i -= rx_ring->count;
1187 /* clear the hdr_addr for the next_to_use descriptor */
1188 rx_desc->read.hdr_addr = 0;
1191 i += rx_ring->count;
1193 if (rx_ring->next_to_use != i)
1194 ixgbe_release_rx_desc(rx_ring, i);
1197 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1199 /* HW will not DMA in data larger than the given buffer, even if it
1200 * parses the (NFS, of course) header to be larger. In that case, it
1201 * fills the header buffer and spills the rest into the page.
1203 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1204 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1205 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1206 if (hlen > IXGBE_RX_HDR_SIZE)
1207 hlen = IXGBE_RX_HDR_SIZE;
1212 * ixgbe_merge_active_tail - merge active tail into lro skb
1213 * @tail: pointer to active tail in frag_list
1215 * This function merges the length and data of an active tail into the
1216 * skb containing the frag_list. It resets the tail's pointer to the head,
1217 * but it leaves the heads pointer to tail intact.
1219 static inline struct sk_buff *ixgbe_merge_active_tail(struct sk_buff *tail)
1221 struct sk_buff *head = IXGBE_CB(tail)->head;
1226 head->len += tail->len;
1227 head->data_len += tail->len;
1228 head->truesize += tail->len;
1230 IXGBE_CB(tail)->head = NULL;
1236 * ixgbe_add_active_tail - adds an active tail into the skb frag_list
1237 * @head: pointer to the start of the skb
1238 * @tail: pointer to active tail to add to frag_list
1240 * This function adds an active tail to the end of the frag list. This tail
1241 * will still be receiving data so we cannot yet ad it's stats to the main
1242 * skb. That is done via ixgbe_merge_active_tail.
1244 static inline void ixgbe_add_active_tail(struct sk_buff *head,
1245 struct sk_buff *tail)
1247 struct sk_buff *old_tail = IXGBE_CB(head)->tail;
1250 ixgbe_merge_active_tail(old_tail);
1251 old_tail->next = tail;
1253 skb_shinfo(head)->frag_list = tail;
1256 IXGBE_CB(tail)->head = head;
1257 IXGBE_CB(head)->tail = tail;
1261 * ixgbe_close_active_frag_list - cleanup pointers on a frag_list skb
1262 * @head: pointer to head of an active frag list
1264 * This function will clear the frag_tail_tracker pointer on an active
1265 * frag_list and returns true if the pointer was actually set
1267 static inline bool ixgbe_close_active_frag_list(struct sk_buff *head)
1269 struct sk_buff *tail = IXGBE_CB(head)->tail;
1274 ixgbe_merge_active_tail(tail);
1276 IXGBE_CB(head)->tail = NULL;
1282 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1283 * @data: pointer to the start of the headers
1284 * @max_len: total length of section to find headers in
1286 * This function is meant to determine the length of headers that will
1287 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1288 * motivation of doing this is to only perform one pull for IPv4 TCP
1289 * packets so that we can do basic things like calculating the gso_size
1290 * based on the average data per packet.
1292 static unsigned int ixgbe_get_headlen(unsigned char *data,
1293 unsigned int max_len)
1296 unsigned char *network;
1299 struct vlan_hdr *vlan;
1304 u8 nexthdr = 0; /* default to not TCP */
1307 /* this should never happen, but better safe than sorry */
1308 if (max_len < ETH_HLEN)
1311 /* initialize network frame pointer */
1314 /* set first protocol and move network header forward */
1315 protocol = hdr.eth->h_proto;
1316 hdr.network += ETH_HLEN;
1318 /* handle any vlan tag if present */
1319 if (protocol == __constant_htons(ETH_P_8021Q)) {
1320 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1323 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1324 hdr.network += VLAN_HLEN;
1327 /* handle L3 protocols */
1328 if (protocol == __constant_htons(ETH_P_IP)) {
1329 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1332 /* access ihl as a u8 to avoid unaligned access on ia64 */
1333 hlen = (hdr.network[0] & 0x0F) << 2;
1335 /* verify hlen meets minimum size requirements */
1336 if (hlen < sizeof(struct iphdr))
1337 return hdr.network - data;
1339 /* record next protocol */
1340 nexthdr = hdr.ipv4->protocol;
1341 hdr.network += hlen;
1343 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1344 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1346 hdr.network += FCOE_HEADER_LEN;
1349 return hdr.network - data;
1352 /* finally sort out TCP */
1353 if (nexthdr == IPPROTO_TCP) {
1354 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1357 /* access doff as a u8 to avoid unaligned access on ia64 */
1358 hlen = (hdr.network[12] & 0xF0) >> 2;
1360 /* verify hlen meets minimum size requirements */
1361 if (hlen < sizeof(struct tcphdr))
1362 return hdr.network - data;
1364 hdr.network += hlen;
1368 * If everything has gone correctly hdr.network should be the
1369 * data section of the packet and will be the end of the header.
1370 * If not then it probably represents the end of the last recognized
1373 if ((hdr.network - data) < max_len)
1374 return hdr.network - data;
1379 static void ixgbe_get_rsc_cnt(struct ixgbe_ring *rx_ring,
1380 union ixgbe_adv_rx_desc *rx_desc,
1381 struct sk_buff *skb)
1386 if (!ring_is_rsc_enabled(rx_ring))
1389 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1390 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1392 /* If this is an RSC frame rsc_cnt should be non-zero */
1396 rsc_cnt = le32_to_cpu(rsc_enabled);
1397 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1399 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1402 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1403 struct sk_buff *skb)
1405 u16 hdr_len = ixgbe_get_headlen(skb->data, skb_headlen(skb));
1407 /* set gso_size to avoid messing up TCP MSS */
1408 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1409 IXGBE_CB(skb)->append_cnt);
1412 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1413 struct sk_buff *skb)
1415 /* if append_cnt is 0 then frame is not RSC */
1416 if (!IXGBE_CB(skb)->append_cnt)
1419 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1420 rx_ring->rx_stats.rsc_flush++;
1422 ixgbe_set_rsc_gso_size(rx_ring, skb);
1424 /* gso_size is computed using append_cnt so always clear it last */
1425 IXGBE_CB(skb)->append_cnt = 0;
1429 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1430 * @rx_ring: rx descriptor ring packet is being transacted on
1431 * @rx_desc: pointer to the EOP Rx descriptor
1432 * @skb: pointer to current skb being populated
1434 * This function checks the ring, descriptor, and packet information in
1435 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1436 * other fields within the skb.
1438 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1439 union ixgbe_adv_rx_desc *rx_desc,
1440 struct sk_buff *skb)
1442 ixgbe_update_rsc_stats(rx_ring, skb);
1444 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1446 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1448 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1449 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1450 __vlan_hwaccel_put_tag(skb, vid);
1453 skb_record_rx_queue(skb, rx_ring->queue_index);
1455 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1458 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1459 struct sk_buff *skb)
1461 struct ixgbe_adapter *adapter = q_vector->adapter;
1463 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1464 napi_gro_receive(&q_vector->napi, skb);
1469 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1470 struct ixgbe_ring *rx_ring,
1473 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1474 struct ixgbe_rx_buffer *rx_buffer_info;
1475 struct sk_buff *skb;
1476 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1477 const int current_node = numa_node_id();
1479 struct ixgbe_adapter *adapter = q_vector->adapter;
1481 #endif /* IXGBE_FCOE */
1483 u16 cleaned_count = 0;
1485 i = rx_ring->next_to_clean;
1486 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1488 while (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) {
1491 rmb(); /* read descriptor and rx_buffer_info after status DD */
1493 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1495 skb = rx_buffer_info->skb;
1496 rx_buffer_info->skb = NULL;
1497 prefetch(skb->data);
1499 /* linear means we are building an skb from multiple pages */
1500 if (!skb_is_nonlinear(skb)) {
1502 if (ring_is_ps_enabled(rx_ring)) {
1503 hlen = ixgbe_get_hlen(rx_desc);
1504 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1506 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1512 * Delay unmapping of the first packet. It carries the
1513 * header information, HW may still access the header
1514 * after writeback. Only unmap it when EOP is reached
1516 if (!IXGBE_CB(skb)->head) {
1517 IXGBE_CB(skb)->delay_unmap = true;
1518 IXGBE_CB(skb)->dma = rx_buffer_info->dma;
1520 skb = ixgbe_merge_active_tail(skb);
1521 dma_unmap_single(rx_ring->dev,
1522 rx_buffer_info->dma,
1523 rx_ring->rx_buf_len,
1526 rx_buffer_info->dma = 0;
1528 /* assume packet split since header is unmapped */
1529 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1533 dma_unmap_page(rx_ring->dev,
1534 rx_buffer_info->page_dma,
1537 rx_buffer_info->page_dma = 0;
1538 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1539 rx_buffer_info->page,
1540 rx_buffer_info->page_offset,
1543 if ((page_count(rx_buffer_info->page) == 1) &&
1544 (page_to_nid(rx_buffer_info->page) == current_node))
1545 get_page(rx_buffer_info->page);
1547 rx_buffer_info->page = NULL;
1549 skb->len += upper_len;
1550 skb->data_len += upper_len;
1551 skb->truesize += PAGE_SIZE / 2;
1554 ixgbe_get_rsc_cnt(rx_ring, rx_desc, skb);
1557 if (i == rx_ring->count)
1560 next_rxd = IXGBE_RX_DESC(rx_ring, i);
1564 if ((!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) {
1565 struct ixgbe_rx_buffer *next_buffer;
1568 if (IXGBE_CB(skb)->append_cnt) {
1569 nextp = le32_to_cpu(
1570 rx_desc->wb.upper.status_error);
1571 nextp >>= IXGBE_RXDADV_NEXTP_SHIFT;
1576 next_buffer = &rx_ring->rx_buffer_info[nextp];
1578 if (ring_is_ps_enabled(rx_ring)) {
1579 rx_buffer_info->skb = next_buffer->skb;
1580 rx_buffer_info->dma = next_buffer->dma;
1581 next_buffer->skb = skb;
1582 next_buffer->dma = 0;
1584 struct sk_buff *next_skb = next_buffer->skb;
1585 ixgbe_add_active_tail(skb, next_skb);
1586 IXGBE_CB(next_skb)->head = skb;
1588 rx_ring->rx_stats.non_eop_descs++;
1592 dma_unmap_single(rx_ring->dev,
1594 rx_ring->rx_buf_len,
1596 IXGBE_CB(skb)->dma = 0;
1597 IXGBE_CB(skb)->delay_unmap = false;
1599 if (ixgbe_close_active_frag_list(skb) &&
1600 !IXGBE_CB(skb)->append_cnt) {
1601 /* if we got here without RSC the packet is invalid */
1602 dev_kfree_skb_any(skb);
1606 /* ERR_MASK will only have valid bits if EOP set */
1607 if (unlikely(ixgbe_test_staterr(rx_desc,
1608 IXGBE_RXDADV_ERR_FRAME_ERR_MASK))) {
1609 dev_kfree_skb_any(skb);
1613 /* probably a little skewed due to removing CRC */
1614 total_rx_bytes += skb->len;
1617 /* populate checksum, timestamp, VLAN, and protocol */
1618 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1621 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1622 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1623 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1625 dev_kfree_skb_any(skb);
1629 #endif /* IXGBE_FCOE */
1630 ixgbe_rx_skb(q_vector, skb);
1637 /* return some buffers to hardware, one at a time is too slow */
1638 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1639 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1643 /* use prefetched values */
1647 rx_ring->next_to_clean = i;
1648 cleaned_count = ixgbe_desc_unused(rx_ring);
1651 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1654 /* include DDPed FCoE data */
1655 if (ddp_bytes > 0) {
1658 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1659 sizeof(struct fc_frame_header) -
1660 sizeof(struct fcoe_crc_eof);
1663 total_rx_bytes += ddp_bytes;
1664 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1666 #endif /* IXGBE_FCOE */
1668 u64_stats_update_begin(&rx_ring->syncp);
1669 rx_ring->stats.packets += total_rx_packets;
1670 rx_ring->stats.bytes += total_rx_bytes;
1671 u64_stats_update_end(&rx_ring->syncp);
1672 q_vector->rx.total_packets += total_rx_packets;
1673 q_vector->rx.total_bytes += total_rx_bytes;
1679 * ixgbe_configure_msix - Configure MSI-X hardware
1680 * @adapter: board private structure
1682 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1685 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1687 struct ixgbe_q_vector *q_vector;
1688 int q_vectors, v_idx;
1691 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1693 /* Populate MSIX to EITR Select */
1694 if (adapter->num_vfs > 32) {
1695 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1696 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1700 * Populate the IVAR table and set the ITR values to the
1701 * corresponding register.
1703 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1704 struct ixgbe_ring *ring;
1705 q_vector = adapter->q_vector[v_idx];
1707 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
1708 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1710 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
1711 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1713 if (q_vector->tx.ring && !q_vector->rx.ring) {
1714 /* tx only vector */
1715 if (adapter->tx_itr_setting == 1)
1716 q_vector->itr = IXGBE_10K_ITR;
1718 q_vector->itr = adapter->tx_itr_setting;
1720 /* rx or rx/tx vector */
1721 if (adapter->rx_itr_setting == 1)
1722 q_vector->itr = IXGBE_20K_ITR;
1724 q_vector->itr = adapter->rx_itr_setting;
1727 ixgbe_write_eitr(q_vector);
1730 switch (adapter->hw.mac.type) {
1731 case ixgbe_mac_82598EB:
1732 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1735 case ixgbe_mac_82599EB:
1736 case ixgbe_mac_X540:
1737 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1742 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1744 /* set up to autoclear timer, and the vectors */
1745 mask = IXGBE_EIMS_ENABLE_MASK;
1746 mask &= ~(IXGBE_EIMS_OTHER |
1747 IXGBE_EIMS_MAILBOX |
1750 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1753 enum latency_range {
1757 latency_invalid = 255
1761 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1762 * @q_vector: structure containing interrupt and ring information
1763 * @ring_container: structure containing ring performance data
1765 * Stores a new ITR value based on packets and byte
1766 * counts during the last interrupt. The advantage of per interrupt
1767 * computation is faster updates and more accurate ITR for the current
1768 * traffic pattern. Constants in this function were computed
1769 * based on theoretical maximum wire speed and thresholds were set based
1770 * on testing data as well as attempting to minimize response time
1771 * while increasing bulk throughput.
1772 * this functionality is controlled by the InterruptThrottleRate module
1773 * parameter (see ixgbe_param.c)
1775 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1776 struct ixgbe_ring_container *ring_container)
1779 struct ixgbe_adapter *adapter = q_vector->adapter;
1780 int bytes = ring_container->total_bytes;
1781 int packets = ring_container->total_packets;
1783 u8 itr_setting = ring_container->itr;
1788 /* simple throttlerate management
1789 * 0-20MB/s lowest (100000 ints/s)
1790 * 20-100MB/s low (20000 ints/s)
1791 * 100-1249MB/s bulk (8000 ints/s)
1793 /* what was last interrupt timeslice? */
1794 timepassed_us = q_vector->itr >> 2;
1795 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1797 switch (itr_setting) {
1798 case lowest_latency:
1799 if (bytes_perint > adapter->eitr_low)
1800 itr_setting = low_latency;
1803 if (bytes_perint > adapter->eitr_high)
1804 itr_setting = bulk_latency;
1805 else if (bytes_perint <= adapter->eitr_low)
1806 itr_setting = lowest_latency;
1809 if (bytes_perint <= adapter->eitr_high)
1810 itr_setting = low_latency;
1814 /* clear work counters since we have the values we need */
1815 ring_container->total_bytes = 0;
1816 ring_container->total_packets = 0;
1818 /* write updated itr to ring container */
1819 ring_container->itr = itr_setting;
1823 * ixgbe_write_eitr - write EITR register in hardware specific way
1824 * @q_vector: structure containing interrupt and ring information
1826 * This function is made to be called by ethtool and by the driver
1827 * when it needs to update EITR registers at runtime. Hardware
1828 * specific quirks/differences are taken care of here.
1830 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1832 struct ixgbe_adapter *adapter = q_vector->adapter;
1833 struct ixgbe_hw *hw = &adapter->hw;
1834 int v_idx = q_vector->v_idx;
1835 u32 itr_reg = q_vector->itr;
1837 switch (adapter->hw.mac.type) {
1838 case ixgbe_mac_82598EB:
1839 /* must write high and low 16 bits to reset counter */
1840 itr_reg |= (itr_reg << 16);
1842 case ixgbe_mac_82599EB:
1843 case ixgbe_mac_X540:
1845 * set the WDIS bit to not clear the timer bits and cause an
1846 * immediate assertion of the interrupt
1848 itr_reg |= IXGBE_EITR_CNT_WDIS;
1853 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1856 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
1858 u32 new_itr = q_vector->itr;
1861 ixgbe_update_itr(q_vector, &q_vector->tx);
1862 ixgbe_update_itr(q_vector, &q_vector->rx);
1864 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
1866 switch (current_itr) {
1867 /* counts and packets in update_itr are dependent on these numbers */
1868 case lowest_latency:
1869 new_itr = IXGBE_100K_ITR;
1872 new_itr = IXGBE_20K_ITR;
1875 new_itr = IXGBE_8K_ITR;
1881 if (new_itr != q_vector->itr) {
1882 /* do an exponential smoothing */
1883 new_itr = (10 * new_itr * q_vector->itr) /
1884 ((9 * new_itr) + q_vector->itr);
1886 /* save the algorithm value here */
1887 q_vector->itr = new_itr & IXGBE_MAX_EITR;
1889 ixgbe_write_eitr(q_vector);
1894 * ixgbe_check_overtemp_subtask - check for over tempurature
1895 * @adapter: pointer to adapter
1897 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
1899 struct ixgbe_hw *hw = &adapter->hw;
1900 u32 eicr = adapter->interrupt_event;
1902 if (test_bit(__IXGBE_DOWN, &adapter->state))
1905 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1906 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1909 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1911 switch (hw->device_id) {
1912 case IXGBE_DEV_ID_82599_T3_LOM:
1914 * Since the warning interrupt is for both ports
1915 * we don't have to check if:
1916 * - This interrupt wasn't for our port.
1917 * - We may have missed the interrupt so always have to
1918 * check if we got a LSC
1920 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1921 !(eicr & IXGBE_EICR_LSC))
1924 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1926 bool link_up = false;
1928 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1934 /* Check if this is not due to overtemp */
1935 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1940 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1945 "Network adapter has been stopped because it has over heated. "
1946 "Restart the computer. If the problem persists, "
1947 "power off the system and replace the adapter\n");
1949 adapter->interrupt_event = 0;
1952 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1954 struct ixgbe_hw *hw = &adapter->hw;
1956 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1957 (eicr & IXGBE_EICR_GPI_SDP1)) {
1958 e_crit(probe, "Fan has stopped, replace the adapter\n");
1959 /* write to clear the interrupt */
1960 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1964 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
1966 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1969 switch (adapter->hw.mac.type) {
1970 case ixgbe_mac_82599EB:
1972 * Need to check link state so complete overtemp check
1975 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
1976 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
1977 adapter->interrupt_event = eicr;
1978 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1979 ixgbe_service_event_schedule(adapter);
1983 case ixgbe_mac_X540:
1984 if (!(eicr & IXGBE_EICR_TS))
1992 "Network adapter has been stopped because it has over heated. "
1993 "Restart the computer. If the problem persists, "
1994 "power off the system and replace the adapter\n");
1997 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1999 struct ixgbe_hw *hw = &adapter->hw;
2001 if (eicr & IXGBE_EICR_GPI_SDP2) {
2002 /* Clear the interrupt */
2003 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
2004 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2005 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2006 ixgbe_service_event_schedule(adapter);
2010 if (eicr & IXGBE_EICR_GPI_SDP1) {
2011 /* Clear the interrupt */
2012 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2013 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2014 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2015 ixgbe_service_event_schedule(adapter);
2020 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2022 struct ixgbe_hw *hw = &adapter->hw;
2025 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2026 adapter->link_check_timeout = jiffies;
2027 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2028 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2029 IXGBE_WRITE_FLUSH(hw);
2030 ixgbe_service_event_schedule(adapter);
2034 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2038 struct ixgbe_hw *hw = &adapter->hw;
2040 switch (hw->mac.type) {
2041 case ixgbe_mac_82598EB:
2042 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2043 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2045 case ixgbe_mac_82599EB:
2046 case ixgbe_mac_X540:
2047 mask = (qmask & 0xFFFFFFFF);
2049 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2050 mask = (qmask >> 32);
2052 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2057 /* skip the flush */
2060 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2064 struct ixgbe_hw *hw = &adapter->hw;
2066 switch (hw->mac.type) {
2067 case ixgbe_mac_82598EB:
2068 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2069 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2071 case ixgbe_mac_82599EB:
2072 case ixgbe_mac_X540:
2073 mask = (qmask & 0xFFFFFFFF);
2075 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2076 mask = (qmask >> 32);
2078 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2083 /* skip the flush */
2087 * ixgbe_irq_enable - Enable default interrupt generation settings
2088 * @adapter: board private structure
2090 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2093 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2095 /* don't reenable LSC while waiting for link */
2096 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2097 mask &= ~IXGBE_EIMS_LSC;
2099 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2100 switch (adapter->hw.mac.type) {
2101 case ixgbe_mac_82599EB:
2102 mask |= IXGBE_EIMS_GPI_SDP0;
2104 case ixgbe_mac_X540:
2105 mask |= IXGBE_EIMS_TS;
2110 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2111 mask |= IXGBE_EIMS_GPI_SDP1;
2112 switch (adapter->hw.mac.type) {
2113 case ixgbe_mac_82599EB:
2114 mask |= IXGBE_EIMS_GPI_SDP1;
2115 mask |= IXGBE_EIMS_GPI_SDP2;
2116 case ixgbe_mac_X540:
2117 mask |= IXGBE_EIMS_ECC;
2118 mask |= IXGBE_EIMS_MAILBOX;
2123 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2124 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2125 mask |= IXGBE_EIMS_FLOW_DIR;
2127 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2129 ixgbe_irq_enable_queues(adapter, ~0);
2131 IXGBE_WRITE_FLUSH(&adapter->hw);
2134 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2136 struct ixgbe_adapter *adapter = data;
2137 struct ixgbe_hw *hw = &adapter->hw;
2141 * Workaround for Silicon errata. Use clear-by-write instead
2142 * of clear-by-read. Reading with EICS will return the
2143 * interrupt causes without clearing, which later be done
2144 * with the write to EICR.
2146 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2147 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2149 if (eicr & IXGBE_EICR_LSC)
2150 ixgbe_check_lsc(adapter);
2152 if (eicr & IXGBE_EICR_MAILBOX)
2153 ixgbe_msg_task(adapter);
2155 switch (hw->mac.type) {
2156 case ixgbe_mac_82599EB:
2157 case ixgbe_mac_X540:
2158 if (eicr & IXGBE_EICR_ECC)
2159 e_info(link, "Received unrecoverable ECC Err, please "
2161 /* Handle Flow Director Full threshold interrupt */
2162 if (eicr & IXGBE_EICR_FLOW_DIR) {
2163 int reinit_count = 0;
2165 for (i = 0; i < adapter->num_tx_queues; i++) {
2166 struct ixgbe_ring *ring = adapter->tx_ring[i];
2167 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2172 /* no more flow director interrupts until after init */
2173 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2174 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2175 ixgbe_service_event_schedule(adapter);
2178 ixgbe_check_sfp_event(adapter, eicr);
2179 ixgbe_check_overtemp_event(adapter, eicr);
2185 ixgbe_check_fan_failure(adapter, eicr);
2187 /* re-enable the original interrupt state, no lsc, no queues */
2188 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2189 ixgbe_irq_enable(adapter, false, false);
2194 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2196 struct ixgbe_q_vector *q_vector = data;
2198 /* EIAM disabled interrupts (on this vector) for us */
2200 if (q_vector->rx.ring || q_vector->tx.ring)
2201 napi_schedule(&q_vector->napi);
2206 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2209 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2210 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2212 rx_ring->q_vector = q_vector;
2213 rx_ring->next = q_vector->rx.ring;
2214 q_vector->rx.ring = rx_ring;
2215 q_vector->rx.count++;
2218 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2221 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2222 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2224 tx_ring->q_vector = q_vector;
2225 tx_ring->next = q_vector->tx.ring;
2226 q_vector->tx.ring = tx_ring;
2227 q_vector->tx.count++;
2228 q_vector->tx.work_limit = a->tx_work_limit;
2232 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2233 * @adapter: board private structure to initialize
2235 * This function maps descriptor rings to the queue-specific vectors
2236 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2237 * one vector per ring/queue, but on a constrained vector budget, we
2238 * group the rings as "efficiently" as possible. You would add new
2239 * mapping configurations in here.
2241 static void ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2243 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2244 int rxr_remaining = adapter->num_rx_queues, rxr_idx = 0;
2245 int txr_remaining = adapter->num_tx_queues, txr_idx = 0;
2248 /* only one q_vector if MSI-X is disabled. */
2249 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2253 * If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2254 * group them so there are multiple queues per vector.
2256 * Re-adjusting *qpv takes care of the remainder.
2258 for (; v_start < q_vectors && rxr_remaining; v_start++) {
2259 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_start);
2260 for (; rqpv; rqpv--, rxr_idx++, rxr_remaining--)
2261 map_vector_to_rxq(adapter, v_start, rxr_idx);
2265 * If there are not enough q_vectors for each ring to have it's own
2266 * vector then we must pair up Rx/Tx on a each vector
2268 if ((v_start + txr_remaining) > q_vectors)
2271 for (; v_start < q_vectors && txr_remaining; v_start++) {
2272 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_start);
2273 for (; tqpv; tqpv--, txr_idx++, txr_remaining--)
2274 map_vector_to_txq(adapter, v_start, txr_idx);
2279 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2280 * @adapter: board private structure
2282 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2283 * interrupts from the kernel.
2285 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2287 struct net_device *netdev = adapter->netdev;
2288 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2292 for (vector = 0; vector < q_vectors; vector++) {
2293 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2294 struct msix_entry *entry = &adapter->msix_entries[vector];
2296 if (q_vector->tx.ring && q_vector->rx.ring) {
2297 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2298 "%s-%s-%d", netdev->name, "TxRx", ri++);
2300 } else if (q_vector->rx.ring) {
2301 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2302 "%s-%s-%d", netdev->name, "rx", ri++);
2303 } else if (q_vector->tx.ring) {
2304 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2305 "%s-%s-%d", netdev->name, "tx", ti++);
2307 /* skip this unused q_vector */
2310 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2311 q_vector->name, q_vector);
2313 e_err(probe, "request_irq failed for MSIX interrupt "
2314 "Error: %d\n", err);
2315 goto free_queue_irqs;
2317 /* If Flow Director is enabled, set interrupt affinity */
2318 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2319 /* assign the mask for this irq */
2320 irq_set_affinity_hint(entry->vector,
2321 q_vector->affinity_mask);
2325 err = request_irq(adapter->msix_entries[vector].vector,
2326 ixgbe_msix_other, 0, netdev->name, adapter);
2328 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2329 goto free_queue_irqs;
2337 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2339 free_irq(adapter->msix_entries[vector].vector,
2340 adapter->q_vector[vector]);
2342 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2343 pci_disable_msix(adapter->pdev);
2344 kfree(adapter->msix_entries);
2345 adapter->msix_entries = NULL;
2350 * ixgbe_intr - legacy mode Interrupt Handler
2351 * @irq: interrupt number
2352 * @data: pointer to a network interface device structure
2354 static irqreturn_t ixgbe_intr(int irq, void *data)
2356 struct ixgbe_adapter *adapter = data;
2357 struct ixgbe_hw *hw = &adapter->hw;
2358 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2362 * Workaround for silicon errata on 82598. Mask the interrupts
2363 * before the read of EICR.
2365 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2367 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2368 * therefore no explicit interrupt disable is necessary */
2369 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2372 * shared interrupt alert!
2373 * make sure interrupts are enabled because the read will
2374 * have disabled interrupts due to EIAM
2375 * finish the workaround of silicon errata on 82598. Unmask
2376 * the interrupt that we masked before the EICR read.
2378 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2379 ixgbe_irq_enable(adapter, true, true);
2380 return IRQ_NONE; /* Not our interrupt */
2383 if (eicr & IXGBE_EICR_LSC)
2384 ixgbe_check_lsc(adapter);
2386 switch (hw->mac.type) {
2387 case ixgbe_mac_82599EB:
2388 ixgbe_check_sfp_event(adapter, eicr);
2390 case ixgbe_mac_X540:
2391 if (eicr & IXGBE_EICR_ECC)
2392 e_info(link, "Received unrecoverable ECC err, please "
2394 ixgbe_check_overtemp_event(adapter, eicr);
2400 ixgbe_check_fan_failure(adapter, eicr);
2402 if (napi_schedule_prep(&(q_vector->napi))) {
2403 /* would disable interrupts here but EIAM disabled it */
2404 __napi_schedule(&(q_vector->napi));
2408 * re-enable link(maybe) and non-queue interrupts, no flush.
2409 * ixgbe_poll will re-enable the queue interrupts
2412 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2413 ixgbe_irq_enable(adapter, false, false);
2418 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2420 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2423 /* legacy and MSI only use one vector */
2424 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2427 for (i = 0; i < adapter->num_rx_queues; i++) {
2428 adapter->rx_ring[i]->q_vector = NULL;
2429 adapter->rx_ring[i]->next = NULL;
2431 for (i = 0; i < adapter->num_tx_queues; i++) {
2432 adapter->tx_ring[i]->q_vector = NULL;
2433 adapter->tx_ring[i]->next = NULL;
2436 for (i = 0; i < q_vectors; i++) {
2437 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2438 memset(&q_vector->rx, 0, sizeof(struct ixgbe_ring_container));
2439 memset(&q_vector->tx, 0, sizeof(struct ixgbe_ring_container));
2444 * ixgbe_request_irq - initialize interrupts
2445 * @adapter: board private structure
2447 * Attempts to configure interrupts using the best available
2448 * capabilities of the hardware and kernel.
2450 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2452 struct net_device *netdev = adapter->netdev;
2455 /* map all of the rings to the q_vectors */
2456 ixgbe_map_rings_to_vectors(adapter);
2458 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2459 err = ixgbe_request_msix_irqs(adapter);
2460 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2461 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2462 netdev->name, adapter);
2464 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2465 netdev->name, adapter);
2468 e_err(probe, "request_irq failed, Error %d\n", err);
2470 /* place q_vectors and rings back into a known good state */
2471 ixgbe_reset_q_vectors(adapter);
2477 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2479 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2482 q_vectors = adapter->num_msix_vectors;
2484 free_irq(adapter->msix_entries[i].vector, adapter);
2487 for (; i >= 0; i--) {
2488 /* free only the irqs that were actually requested */
2489 if (!adapter->q_vector[i]->rx.ring &&
2490 !adapter->q_vector[i]->tx.ring)
2493 /* clear the affinity_mask in the IRQ descriptor */
2494 irq_set_affinity_hint(adapter->msix_entries[i].vector,
2497 free_irq(adapter->msix_entries[i].vector,
2498 adapter->q_vector[i]);
2501 free_irq(adapter->pdev->irq, adapter);
2504 /* clear q_vector state information */
2505 ixgbe_reset_q_vectors(adapter);
2509 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2510 * @adapter: board private structure
2512 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2514 switch (adapter->hw.mac.type) {
2515 case ixgbe_mac_82598EB:
2516 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2518 case ixgbe_mac_82599EB:
2519 case ixgbe_mac_X540:
2520 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2521 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2522 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2527 IXGBE_WRITE_FLUSH(&adapter->hw);
2528 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2530 for (i = 0; i < adapter->num_msix_vectors; i++)
2531 synchronize_irq(adapter->msix_entries[i].vector);
2533 synchronize_irq(adapter->pdev->irq);
2538 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2541 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2543 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2546 if (adapter->rx_itr_setting == 1)
2547 q_vector->itr = IXGBE_20K_ITR;
2549 q_vector->itr = adapter->rx_itr_setting;
2551 ixgbe_write_eitr(q_vector);
2553 ixgbe_set_ivar(adapter, 0, 0, 0);
2554 ixgbe_set_ivar(adapter, 1, 0, 0);
2556 e_info(hw, "Legacy interrupt IVAR setup done\n");
2560 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2561 * @adapter: board private structure
2562 * @ring: structure containing ring specific data
2564 * Configure the Tx descriptor ring after a reset.
2566 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2567 struct ixgbe_ring *ring)
2569 struct ixgbe_hw *hw = &adapter->hw;
2570 u64 tdba = ring->dma;
2572 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2573 u8 reg_idx = ring->reg_idx;
2575 /* disable queue to avoid issues while updating state */
2576 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2577 IXGBE_WRITE_FLUSH(hw);
2579 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2580 (tdba & DMA_BIT_MASK(32)));
2581 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2582 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2583 ring->count * sizeof(union ixgbe_adv_tx_desc));
2584 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2585 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2586 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2589 * set WTHRESH to encourage burst writeback, it should not be set
2590 * higher than 1 when ITR is 0 as it could cause false TX hangs
2592 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2593 * to or less than the number of on chip descriptors, which is
2596 if (!adapter->tx_itr_setting || !adapter->rx_itr_setting)
2597 txdctl |= (1 << 16); /* WTHRESH = 1 */
2599 txdctl |= (8 << 16); /* WTHRESH = 8 */
2601 /* PTHRESH=32 is needed to avoid a Tx hang with DFP enabled. */
2602 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2603 32; /* PTHRESH = 32 */
2605 /* reinitialize flowdirector state */
2606 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2607 adapter->atr_sample_rate) {
2608 ring->atr_sample_rate = adapter->atr_sample_rate;
2609 ring->atr_count = 0;
2610 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2612 ring->atr_sample_rate = 0;
2615 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2618 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2620 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2621 if (hw->mac.type == ixgbe_mac_82598EB &&
2622 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2625 /* poll to verify queue is enabled */
2627 usleep_range(1000, 2000);
2628 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2629 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2631 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2634 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2636 struct ixgbe_hw *hw = &adapter->hw;
2639 u8 tcs = netdev_get_num_tc(adapter->netdev);
2641 if (hw->mac.type == ixgbe_mac_82598EB)
2644 /* disable the arbiter while setting MTQC */
2645 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2646 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2647 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2649 /* set transmit pool layout */
2650 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2651 case (IXGBE_FLAG_SRIOV_ENABLED):
2652 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2653 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2657 reg = IXGBE_MTQC_64Q_1PB;
2659 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2661 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2663 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2665 /* Enable Security TX Buffer IFG for multiple pb */
2667 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2668 reg |= IXGBE_SECTX_DCB;
2669 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2674 /* re-enable the arbiter */
2675 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2676 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2680 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2681 * @adapter: board private structure
2683 * Configure the Tx unit of the MAC after a reset.
2685 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2687 struct ixgbe_hw *hw = &adapter->hw;
2691 ixgbe_setup_mtqc(adapter);
2693 if (hw->mac.type != ixgbe_mac_82598EB) {
2694 /* DMATXCTL.EN must be before Tx queues are enabled */
2695 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2696 dmatxctl |= IXGBE_DMATXCTL_TE;
2697 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2700 /* Setup the HW Tx Head and Tail descriptor pointers */
2701 for (i = 0; i < adapter->num_tx_queues; i++)
2702 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2705 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2707 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2708 struct ixgbe_ring *rx_ring)
2711 u8 reg_idx = rx_ring->reg_idx;
2713 switch (adapter->hw.mac.type) {
2714 case ixgbe_mac_82598EB: {
2715 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2716 const int mask = feature[RING_F_RSS].mask;
2717 reg_idx = reg_idx & mask;
2720 case ixgbe_mac_82599EB:
2721 case ixgbe_mac_X540:
2726 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2728 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2729 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2730 if (adapter->num_vfs)
2731 srrctl |= IXGBE_SRRCTL_DROP_EN;
2733 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2734 IXGBE_SRRCTL_BSIZEHDR_MASK;
2736 if (ring_is_ps_enabled(rx_ring)) {
2737 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2738 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2740 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2742 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2744 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2745 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2746 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2749 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2752 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2754 struct ixgbe_hw *hw = &adapter->hw;
2755 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2756 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2757 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2758 u32 mrqc = 0, reta = 0;
2761 u8 tcs = netdev_get_num_tc(adapter->netdev);
2762 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2765 maxq = min(maxq, adapter->num_tx_queues / tcs);
2767 /* Fill out hash function seeds */
2768 for (i = 0; i < 10; i++)
2769 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2771 /* Fill out redirection table */
2772 for (i = 0, j = 0; i < 128; i++, j++) {
2775 /* reta = 4-byte sliding window of
2776 * 0x00..(indices-1)(indices-1)00..etc. */
2777 reta = (reta << 8) | (j * 0x11);
2779 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2782 /* Disable indicating checksum in descriptor, enables RSS hash */
2783 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2784 rxcsum |= IXGBE_RXCSUM_PCSD;
2785 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2787 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2788 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
2789 mrqc = IXGBE_MRQC_RSSEN;
2791 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2792 | IXGBE_FLAG_SRIOV_ENABLED);
2795 case (IXGBE_FLAG_RSS_ENABLED):
2797 mrqc = IXGBE_MRQC_RSSEN;
2799 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2801 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2803 case (IXGBE_FLAG_SRIOV_ENABLED):
2804 mrqc = IXGBE_MRQC_VMDQEN;
2811 /* Perform hash on these packet types */
2812 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2813 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2814 | IXGBE_MRQC_RSS_FIELD_IPV6
2815 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2817 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2821 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2822 * @adapter: address of board private structure
2823 * @index: index of ring to set
2825 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2826 struct ixgbe_ring *ring)
2828 struct ixgbe_hw *hw = &adapter->hw;
2831 u8 reg_idx = ring->reg_idx;
2833 if (!ring_is_rsc_enabled(ring))
2836 rx_buf_len = ring->rx_buf_len;
2837 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2838 rscctrl |= IXGBE_RSCCTL_RSCEN;
2840 * we must limit the number of descriptors so that the
2841 * total size of max desc * buf_len is not greater
2844 if (ring_is_ps_enabled(ring)) {
2845 #if (PAGE_SIZE < 8192)
2846 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2847 #elif (PAGE_SIZE < 16384)
2848 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2849 #elif (PAGE_SIZE < 32768)
2850 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2852 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2855 if (rx_buf_len <= IXGBE_RXBUFFER_4K)
2856 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2857 else if (rx_buf_len <= IXGBE_RXBUFFER_8K)
2858 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2860 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2862 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2866 * ixgbe_set_uta - Set unicast filter table address
2867 * @adapter: board private structure
2869 * The unicast table address is a register array of 32-bit registers.
2870 * The table is meant to be used in a way similar to how the MTA is used
2871 * however due to certain limitations in the hardware it is necessary to
2872 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2873 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2875 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2877 struct ixgbe_hw *hw = &adapter->hw;
2880 /* The UTA table only exists on 82599 hardware and newer */
2881 if (hw->mac.type < ixgbe_mac_82599EB)
2884 /* we only need to do this if VMDq is enabled */
2885 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2888 for (i = 0; i < 128; i++)
2889 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2892 #define IXGBE_MAX_RX_DESC_POLL 10
2893 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2894 struct ixgbe_ring *ring)
2896 struct ixgbe_hw *hw = &adapter->hw;
2897 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2899 u8 reg_idx = ring->reg_idx;
2901 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2902 if (hw->mac.type == ixgbe_mac_82598EB &&
2903 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2907 usleep_range(1000, 2000);
2908 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2909 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2912 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2913 "the polling period\n", reg_idx);
2917 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2918 struct ixgbe_ring *ring)
2920 struct ixgbe_hw *hw = &adapter->hw;
2921 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2923 u8 reg_idx = ring->reg_idx;
2925 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2926 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2928 /* write value back with RXDCTL.ENABLE bit cleared */
2929 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2931 if (hw->mac.type == ixgbe_mac_82598EB &&
2932 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2935 /* the hardware may take up to 100us to really disable the rx queue */
2938 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2939 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2942 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2943 "the polling period\n", reg_idx);
2947 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2948 struct ixgbe_ring *ring)
2950 struct ixgbe_hw *hw = &adapter->hw;
2951 u64 rdba = ring->dma;
2953 u8 reg_idx = ring->reg_idx;
2955 /* disable queue to avoid issues while updating state */
2956 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2957 ixgbe_disable_rx_queue(adapter, ring);
2959 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2960 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2961 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2962 ring->count * sizeof(union ixgbe_adv_rx_desc));
2963 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2964 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2965 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
2967 ixgbe_configure_srrctl(adapter, ring);
2968 ixgbe_configure_rscctl(adapter, ring);
2970 /* If operating in IOV mode set RLPML for X540 */
2971 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2972 hw->mac.type == ixgbe_mac_X540) {
2973 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
2974 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
2975 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
2978 if (hw->mac.type == ixgbe_mac_82598EB) {
2980 * enable cache line friendly hardware writes:
2981 * PTHRESH=32 descriptors (half the internal cache),
2982 * this also removes ugly rx_no_buffer_count increment
2983 * HTHRESH=4 descriptors (to minimize latency on fetch)
2984 * WTHRESH=8 burst writeback up to two cache lines
2986 rxdctl &= ~0x3FFFFF;
2990 /* enable receive descriptor ring */
2991 rxdctl |= IXGBE_RXDCTL_ENABLE;
2992 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2994 ixgbe_rx_desc_queue_enable(adapter, ring);
2995 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
2998 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3000 struct ixgbe_hw *hw = &adapter->hw;
3003 /* PSRTYPE must be initialized in non 82598 adapters */
3004 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3005 IXGBE_PSRTYPE_UDPHDR |
3006 IXGBE_PSRTYPE_IPV4HDR |
3007 IXGBE_PSRTYPE_L2HDR |
3008 IXGBE_PSRTYPE_IPV6HDR;
3010 if (hw->mac.type == ixgbe_mac_82598EB)
3013 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3014 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3016 for (p = 0; p < adapter->num_rx_pools; p++)
3017 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3021 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3023 struct ixgbe_hw *hw = &adapter->hw;
3026 u32 reg_offset, vf_shift;
3030 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3033 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3034 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3035 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3036 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3038 vf_shift = adapter->num_vfs % 32;
3039 reg_offset = (adapter->num_vfs >= 32) ? 1 : 0;
3041 /* Enable only the PF's pool for Tx/Rx */
3042 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3043 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3044 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3045 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3046 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3048 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3049 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3052 * Set up VF register offsets for selected VT Mode,
3053 * i.e. 32 or 64 VFs for SR-IOV
3055 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3056 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3057 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3058 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3060 /* enable Tx loopback for VF/PF communication */
3061 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3062 /* Enable MAC Anti-Spoofing */
3063 hw->mac.ops.set_mac_anti_spoofing(hw,
3064 (adapter->num_vfs != 0),
3066 /* For VFs that have spoof checking turned off */
3067 for (i = 0; i < adapter->num_vfs; i++) {
3068 if (!adapter->vfinfo[i].spoofchk_enabled)
3069 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3073 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3075 struct ixgbe_hw *hw = &adapter->hw;
3076 struct net_device *netdev = adapter->netdev;
3077 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3079 struct ixgbe_ring *rx_ring;
3083 /* Decide whether to use packet split mode or not */
3085 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3087 /* Do not use packet split if we're in SR-IOV Mode */
3088 if (adapter->num_vfs)
3089 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3091 /* Disable packet split due to 82599 erratum #45 */
3092 if (hw->mac.type == ixgbe_mac_82599EB)
3093 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3096 /* adjust max frame to be able to do baby jumbo for FCoE */
3097 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3098 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3099 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3101 #endif /* IXGBE_FCOE */
3102 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3103 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3104 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3105 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3107 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3110 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
3111 max_frame += VLAN_HLEN;
3113 /* Set the RX buffer length according to the mode */
3114 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3115 rx_buf_len = IXGBE_RX_HDR_SIZE;
3117 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3118 (netdev->mtu <= ETH_DATA_LEN))
3119 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3121 * Make best use of allocation by using all but 1K of a
3122 * power of 2 allocation that will be used for skb->head.
3124 else if (max_frame <= IXGBE_RXBUFFER_3K)
3125 rx_buf_len = IXGBE_RXBUFFER_3K;
3126 else if (max_frame <= IXGBE_RXBUFFER_7K)
3127 rx_buf_len = IXGBE_RXBUFFER_7K;
3128 else if (max_frame <= IXGBE_RXBUFFER_15K)
3129 rx_buf_len = IXGBE_RXBUFFER_15K;
3131 rx_buf_len = IXGBE_MAX_RXBUFFER;
3134 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3135 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3136 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3137 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3140 * Setup the HW Rx Head and Tail Descriptor Pointers and
3141 * the Base and Length of the Rx Descriptor Ring
3143 for (i = 0; i < adapter->num_rx_queues; i++) {
3144 rx_ring = adapter->rx_ring[i];
3145 rx_ring->rx_buf_len = rx_buf_len;
3147 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
3148 set_ring_ps_enabled(rx_ring);
3150 clear_ring_ps_enabled(rx_ring);
3152 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3153 set_ring_rsc_enabled(rx_ring);
3155 clear_ring_rsc_enabled(rx_ring);
3158 if (netdev->features & NETIF_F_FCOE_MTU) {
3159 struct ixgbe_ring_feature *f;
3160 f = &adapter->ring_feature[RING_F_FCOE];
3161 if ((i >= f->mask) && (i < f->mask + f->indices)) {
3162 clear_ring_ps_enabled(rx_ring);
3163 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3164 rx_ring->rx_buf_len =
3165 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3166 } else if (!ring_is_rsc_enabled(rx_ring) &&
3167 !ring_is_ps_enabled(rx_ring)) {
3168 rx_ring->rx_buf_len =
3169 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3172 #endif /* IXGBE_FCOE */
3176 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3178 struct ixgbe_hw *hw = &adapter->hw;
3179 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3181 switch (hw->mac.type) {
3182 case ixgbe_mac_82598EB:
3184 * For VMDq support of different descriptor types or
3185 * buffer sizes through the use of multiple SRRCTL
3186 * registers, RDRXCTL.MVMEN must be set to 1
3188 * also, the manual doesn't mention it clearly but DCA hints
3189 * will only use queue 0's tags unless this bit is set. Side
3190 * effects of setting this bit are only that SRRCTL must be
3191 * fully programmed [0..15]
3193 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3195 case ixgbe_mac_82599EB:
3196 case ixgbe_mac_X540:
3197 /* Disable RSC for ACK packets */
3198 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3199 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3200 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3201 /* hardware requires some bits to be set by default */
3202 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3203 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3206 /* We should do nothing since we don't know this hardware */
3210 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3214 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3215 * @adapter: board private structure
3217 * Configure the Rx unit of the MAC after a reset.
3219 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3221 struct ixgbe_hw *hw = &adapter->hw;
3225 /* disable receives while setting up the descriptors */
3226 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3227 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3229 ixgbe_setup_psrtype(adapter);
3230 ixgbe_setup_rdrxctl(adapter);
3232 /* Program registers for the distribution of queues */
3233 ixgbe_setup_mrqc(adapter);
3235 ixgbe_set_uta(adapter);
3237 /* set_rx_buffer_len must be called before ring initialization */
3238 ixgbe_set_rx_buffer_len(adapter);
3241 * Setup the HW Rx Head and Tail Descriptor Pointers and
3242 * the Base and Length of the Rx Descriptor Ring
3244 for (i = 0; i < adapter->num_rx_queues; i++)
3245 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3247 /* disable drop enable for 82598 parts */
3248 if (hw->mac.type == ixgbe_mac_82598EB)
3249 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3251 /* enable all receives */
3252 rxctrl |= IXGBE_RXCTRL_RXEN;
3253 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3256 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3258 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3259 struct ixgbe_hw *hw = &adapter->hw;
3260 int pool_ndx = adapter->num_vfs;
3262 /* add VID to filter table */
3263 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3264 set_bit(vid, adapter->active_vlans);
3269 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3271 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3272 struct ixgbe_hw *hw = &adapter->hw;
3273 int pool_ndx = adapter->num_vfs;
3275 /* remove VID from filter table */
3276 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3277 clear_bit(vid, adapter->active_vlans);
3283 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3284 * @adapter: driver data
3286 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3288 struct ixgbe_hw *hw = &adapter->hw;
3291 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3292 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3293 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3297 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3298 * @adapter: driver data
3300 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3302 struct ixgbe_hw *hw = &adapter->hw;
3305 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3306 vlnctrl |= IXGBE_VLNCTRL_VFE;
3307 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3308 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3312 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3313 * @adapter: driver data
3315 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3317 struct ixgbe_hw *hw = &adapter->hw;
3321 switch (hw->mac.type) {
3322 case ixgbe_mac_82598EB:
3323 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3324 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3325 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3327 case ixgbe_mac_82599EB:
3328 case ixgbe_mac_X540:
3329 for (i = 0; i < adapter->num_rx_queues; i++) {
3330 j = adapter->rx_ring[i]->reg_idx;
3331 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3332 vlnctrl &= ~IXGBE_RXDCTL_VME;
3333 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3342 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3343 * @adapter: driver data
3345 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3347 struct ixgbe_hw *hw = &adapter->hw;
3351 switch (hw->mac.type) {
3352 case ixgbe_mac_82598EB:
3353 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3354 vlnctrl |= IXGBE_VLNCTRL_VME;
3355 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3357 case ixgbe_mac_82599EB:
3358 case ixgbe_mac_X540:
3359 for (i = 0; i < adapter->num_rx_queues; i++) {
3360 j = adapter->rx_ring[i]->reg_idx;
3361 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3362 vlnctrl |= IXGBE_RXDCTL_VME;
3363 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3371 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3375 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3377 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3378 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3382 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3383 * @netdev: network interface device structure
3385 * Writes unicast address list to the RAR table.
3386 * Returns: -ENOMEM on failure/insufficient address space
3387 * 0 on no addresses written
3388 * X on writing X addresses to the RAR table
3390 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3392 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3393 struct ixgbe_hw *hw = &adapter->hw;
3394 unsigned int vfn = adapter->num_vfs;
3395 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3398 /* return ENOMEM indicating insufficient memory for addresses */
3399 if (netdev_uc_count(netdev) > rar_entries)
3402 if (!netdev_uc_empty(netdev) && rar_entries) {
3403 struct netdev_hw_addr *ha;
3404 /* return error if we do not support writing to RAR table */
3405 if (!hw->mac.ops.set_rar)
3408 netdev_for_each_uc_addr(ha, netdev) {
3411 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3416 /* write the addresses in reverse order to avoid write combining */
3417 for (; rar_entries > 0 ; rar_entries--)
3418 hw->mac.ops.clear_rar(hw, rar_entries);
3424 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3425 * @netdev: network interface device structure
3427 * The set_rx_method entry point is called whenever the unicast/multicast
3428 * address list or the network interface flags are updated. This routine is
3429 * responsible for configuring the hardware for proper unicast, multicast and
3432 void ixgbe_set_rx_mode(struct net_device *netdev)
3434 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3435 struct ixgbe_hw *hw = &adapter->hw;
3436 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3439 /* Check for Promiscuous and All Multicast modes */
3441 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3443 /* set all bits that we expect to always be set */
3444 fctrl |= IXGBE_FCTRL_BAM;
3445 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3446 fctrl |= IXGBE_FCTRL_PMCF;
3448 /* clear the bits we are changing the status of */
3449 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3451 if (netdev->flags & IFF_PROMISC) {
3452 hw->addr_ctrl.user_set_promisc = true;
3453 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3454 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3455 /* don't hardware filter vlans in promisc mode */
3456 ixgbe_vlan_filter_disable(adapter);
3458 if (netdev->flags & IFF_ALLMULTI) {
3459 fctrl |= IXGBE_FCTRL_MPE;
3460 vmolr |= IXGBE_VMOLR_MPE;
3463 * Write addresses to the MTA, if the attempt fails
3464 * then we should just turn on promiscuous mode so
3465 * that we can at least receive multicast traffic
3467 hw->mac.ops.update_mc_addr_list(hw, netdev);
3468 vmolr |= IXGBE_VMOLR_ROMPE;
3470 ixgbe_vlan_filter_enable(adapter);
3471 hw->addr_ctrl.user_set_promisc = false;
3473 * Write addresses to available RAR registers, if there is not
3474 * sufficient space to store all the addresses then enable
3475 * unicast promiscuous mode
3477 count = ixgbe_write_uc_addr_list(netdev);
3479 fctrl |= IXGBE_FCTRL_UPE;
3480 vmolr |= IXGBE_VMOLR_ROPE;
3484 if (adapter->num_vfs) {
3485 ixgbe_restore_vf_multicasts(adapter);
3486 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3487 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3489 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3492 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3494 if (netdev->features & NETIF_F_HW_VLAN_RX)
3495 ixgbe_vlan_strip_enable(adapter);
3497 ixgbe_vlan_strip_disable(adapter);
3500 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3503 struct ixgbe_q_vector *q_vector;
3504 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3506 /* legacy and MSI only use one vector */
3507 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3510 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3511 q_vector = adapter->q_vector[q_idx];
3512 napi_enable(&q_vector->napi);
3516 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3519 struct ixgbe_q_vector *q_vector;
3520 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3522 /* legacy and MSI only use one vector */
3523 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3526 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3527 q_vector = adapter->q_vector[q_idx];
3528 napi_disable(&q_vector->napi);
3532 #ifdef CONFIG_IXGBE_DCB
3534 * ixgbe_configure_dcb - Configure DCB hardware
3535 * @adapter: ixgbe adapter struct
3537 * This is called by the driver on open to configure the DCB hardware.
3538 * This is also called by the gennetlink interface when reconfiguring
3541 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3543 struct ixgbe_hw *hw = &adapter->hw;
3544 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3546 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3547 if (hw->mac.type == ixgbe_mac_82598EB)
3548 netif_set_gso_max_size(adapter->netdev, 65536);
3552 if (hw->mac.type == ixgbe_mac_82598EB)
3553 netif_set_gso_max_size(adapter->netdev, 32768);
3556 /* Enable VLAN tag insert/strip */
3557 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3559 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3562 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3563 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3566 /* reconfigure the hardware */
3567 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3568 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3570 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3572 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3573 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3574 ixgbe_dcb_hw_ets(&adapter->hw,
3575 adapter->ixgbe_ieee_ets,
3577 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3578 adapter->ixgbe_ieee_pfc->pfc_en,
3579 adapter->ixgbe_ieee_ets->prio_tc);
3582 /* Enable RSS Hash per TC */
3583 if (hw->mac.type != ixgbe_mac_82598EB) {
3587 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3589 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3594 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3596 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3601 /* Additional bittime to account for IXGBE framing */
3602 #define IXGBE_ETH_FRAMING 20
3605 * ixgbe_hpbthresh - calculate high water mark for flow control
3607 * @adapter: board private structure to calculate for
3608 * @pb - packet buffer to calculate
3610 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3612 struct ixgbe_hw *hw = &adapter->hw;
3613 struct net_device *dev = adapter->netdev;
3614 int link, tc, kb, marker;
3617 /* Calculate max LAN frame size */
3618 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3621 /* FCoE traffic class uses FCOE jumbo frames */
3622 if (dev->features & NETIF_F_FCOE_MTU) {
3625 #ifdef CONFIG_IXGBE_DCB
3626 fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
3629 if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3630 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3634 /* Calculate delay value for device */
3635 switch (hw->mac.type) {
3636 case ixgbe_mac_X540:
3637 dv_id = IXGBE_DV_X540(link, tc);
3640 dv_id = IXGBE_DV(link, tc);
3644 /* Loopback switch introduces additional latency */
3645 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3646 dv_id += IXGBE_B2BT(tc);
3648 /* Delay value is calculated in bit times convert to KB */
3649 kb = IXGBE_BT2KB(dv_id);
3650 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3652 marker = rx_pba - kb;
3654 /* It is possible that the packet buffer is not large enough
3655 * to provide required headroom. In this case throw an error
3656 * to user and a do the best we can.
3659 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3660 "headroom to support flow control."
3661 "Decrease MTU or number of traffic classes\n", pb);
3669 * ixgbe_lpbthresh - calculate low water mark for for flow control
3671 * @adapter: board private structure to calculate for
3672 * @pb - packet buffer to calculate
3674 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3676 struct ixgbe_hw *hw = &adapter->hw;
3677 struct net_device *dev = adapter->netdev;
3681 /* Calculate max LAN frame size */
3682 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3684 /* Calculate delay value for device */
3685 switch (hw->mac.type) {
3686 case ixgbe_mac_X540:
3687 dv_id = IXGBE_LOW_DV_X540(tc);
3690 dv_id = IXGBE_LOW_DV(tc);
3694 /* Delay value is calculated in bit times convert to KB */
3695 return IXGBE_BT2KB(dv_id);
3699 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3701 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3703 struct ixgbe_hw *hw = &adapter->hw;
3704 int num_tc = netdev_get_num_tc(adapter->netdev);
3710 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3712 for (i = 0; i < num_tc; i++) {
3713 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3715 /* Low water marks must not be larger than high water marks */
3716 if (hw->fc.low_water > hw->fc.high_water[i])
3717 hw->fc.low_water = 0;
3721 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3723 struct ixgbe_hw *hw = &adapter->hw;
3725 u8 tc = netdev_get_num_tc(adapter->netdev);
3727 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3728 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3729 hdrm = 32 << adapter->fdir_pballoc;
3733 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
3734 ixgbe_pbthresh_setup(adapter);
3737 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3739 struct ixgbe_hw *hw = &adapter->hw;
3740 struct hlist_node *node, *node2;
3741 struct ixgbe_fdir_filter *filter;
3743 spin_lock(&adapter->fdir_perfect_lock);
3745 if (!hlist_empty(&adapter->fdir_filter_list))
3746 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3748 hlist_for_each_entry_safe(filter, node, node2,
3749 &adapter->fdir_filter_list, fdir_node) {
3750 ixgbe_fdir_write_perfect_filter_82599(hw,
3753 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3754 IXGBE_FDIR_DROP_QUEUE :
3755 adapter->rx_ring[filter->action]->reg_idx);
3758 spin_unlock(&adapter->fdir_perfect_lock);
3761 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3763 ixgbe_configure_pb(adapter);
3764 #ifdef CONFIG_IXGBE_DCB
3765 ixgbe_configure_dcb(adapter);
3768 ixgbe_set_rx_mode(adapter->netdev);
3769 ixgbe_restore_vlan(adapter);
3772 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3773 ixgbe_configure_fcoe(adapter);
3775 #endif /* IXGBE_FCOE */
3776 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3777 ixgbe_init_fdir_signature_82599(&adapter->hw,
3778 adapter->fdir_pballoc);
3779 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3780 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3781 adapter->fdir_pballoc);
3782 ixgbe_fdir_filter_restore(adapter);
3785 ixgbe_configure_virtualization(adapter);
3787 ixgbe_configure_tx(adapter);
3788 ixgbe_configure_rx(adapter);
3791 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3793 switch (hw->phy.type) {
3794 case ixgbe_phy_sfp_avago:
3795 case ixgbe_phy_sfp_ftl:
3796 case ixgbe_phy_sfp_intel:
3797 case ixgbe_phy_sfp_unknown:
3798 case ixgbe_phy_sfp_passive_tyco:
3799 case ixgbe_phy_sfp_passive_unknown:
3800 case ixgbe_phy_sfp_active_unknown:
3801 case ixgbe_phy_sfp_ftl_active:
3804 if (hw->mac.type == ixgbe_mac_82598EB)
3812 * ixgbe_sfp_link_config - set up SFP+ link
3813 * @adapter: pointer to private adapter struct
3815 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3818 * We are assuming the worst case scenario here, and that
3819 * is that an SFP was inserted/removed after the reset
3820 * but before SFP detection was enabled. As such the best
3821 * solution is to just start searching as soon as we start
3823 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3824 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3826 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3830 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3831 * @hw: pointer to private hardware struct
3833 * Returns 0 on success, negative on failure
3835 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3838 bool negotiation, link_up = false;
3839 u32 ret = IXGBE_ERR_LINK_SETUP;
3841 if (hw->mac.ops.check_link)
3842 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3847 autoneg = hw->phy.autoneg_advertised;
3848 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3849 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3854 if (hw->mac.ops.setup_link)
3855 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3860 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3862 struct ixgbe_hw *hw = &adapter->hw;
3865 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3866 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3868 gpie |= IXGBE_GPIE_EIAME;
3870 * use EIAM to auto-mask when MSI-X interrupt is asserted
3871 * this saves a register write for every interrupt
3873 switch (hw->mac.type) {
3874 case ixgbe_mac_82598EB:
3875 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3877 case ixgbe_mac_82599EB:
3878 case ixgbe_mac_X540:
3880 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3881 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3885 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3886 * specifically only auto mask tx and rx interrupts */
3887 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3890 /* XXX: to interrupt immediately for EICS writes, enable this */
3891 /* gpie |= IXGBE_GPIE_EIMEN; */
3893 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3894 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3895 gpie |= IXGBE_GPIE_VTMODE_64;
3898 /* Enable Thermal over heat sensor interrupt */
3899 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3900 switch (adapter->hw.mac.type) {
3901 case ixgbe_mac_82599EB:
3902 gpie |= IXGBE_SDP0_GPIEN;
3904 case ixgbe_mac_X540:
3905 gpie |= IXGBE_EIMS_TS;
3912 /* Enable fan failure interrupt */
3913 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3914 gpie |= IXGBE_SDP1_GPIEN;
3916 if (hw->mac.type == ixgbe_mac_82599EB) {
3917 gpie |= IXGBE_SDP1_GPIEN;
3918 gpie |= IXGBE_SDP2_GPIEN;
3921 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3924 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
3926 struct ixgbe_hw *hw = &adapter->hw;
3930 ixgbe_get_hw_control(adapter);
3931 ixgbe_setup_gpie(adapter);
3933 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3934 ixgbe_configure_msix(adapter);
3936 ixgbe_configure_msi_and_legacy(adapter);
3938 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3939 if (hw->mac.ops.enable_tx_laser &&
3940 ((hw->phy.multispeed_fiber) ||
3941 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3942 (hw->mac.type == ixgbe_mac_82599EB))))
3943 hw->mac.ops.enable_tx_laser(hw);
3945 clear_bit(__IXGBE_DOWN, &adapter->state);
3946 ixgbe_napi_enable_all(adapter);
3948 if (ixgbe_is_sfp(hw)) {
3949 ixgbe_sfp_link_config(adapter);
3951 err = ixgbe_non_sfp_link_config(hw);
3953 e_err(probe, "link_config FAILED %d\n", err);
3956 /* clear any pending interrupts, may auto mask */
3957 IXGBE_READ_REG(hw, IXGBE_EICR);
3958 ixgbe_irq_enable(adapter, true, true);
3961 * If this adapter has a fan, check to see if we had a failure
3962 * before we enabled the interrupt.
3964 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3965 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3966 if (esdp & IXGBE_ESDP_SDP1)
3967 e_crit(drv, "Fan has stopped, replace the adapter\n");
3970 /* enable transmits */
3971 netif_tx_start_all_queues(adapter->netdev);
3973 /* bring the link up in the watchdog, this could race with our first
3974 * link up interrupt but shouldn't be a problem */
3975 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3976 adapter->link_check_timeout = jiffies;
3977 mod_timer(&adapter->service_timer, jiffies);
3979 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3980 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3981 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3982 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3985 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3987 WARN_ON(in_interrupt());
3988 /* put off any impending NetWatchDogTimeout */
3989 adapter->netdev->trans_start = jiffies;
3991 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3992 usleep_range(1000, 2000);
3993 ixgbe_down(adapter);
3995 * If SR-IOV enabled then wait a bit before bringing the adapter
3996 * back up to give the VFs time to respond to the reset. The
3997 * two second wait is based upon the watchdog timer cycle in
4000 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4003 clear_bit(__IXGBE_RESETTING, &adapter->state);
4006 void ixgbe_up(struct ixgbe_adapter *adapter)
4008 /* hardware has been reset, we need to reload some things */
4009 ixgbe_configure(adapter);
4011 ixgbe_up_complete(adapter);
4014 void ixgbe_reset(struct ixgbe_adapter *adapter)
4016 struct ixgbe_hw *hw = &adapter->hw;
4019 /* lock SFP init bit to prevent race conditions with the watchdog */
4020 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4021 usleep_range(1000, 2000);
4023 /* clear all SFP and link config related flags while holding SFP_INIT */
4024 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4025 IXGBE_FLAG2_SFP_NEEDS_RESET);
4026 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4028 err = hw->mac.ops.init_hw(hw);
4031 case IXGBE_ERR_SFP_NOT_PRESENT:
4032 case IXGBE_ERR_SFP_NOT_SUPPORTED:
4034 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4035 e_dev_err("master disable timed out\n");
4037 case IXGBE_ERR_EEPROM_VERSION:
4038 /* We are running on a pre-production device, log a warning */
4039 e_dev_warn("This device is a pre-production adapter/LOM. "
4040 "Please be aware there may be issues associated with "
4041 "your hardware. If you are experiencing problems "
4042 "please contact your Intel or hardware "
4043 "representative who provided you with this "
4047 e_dev_err("Hardware Error: %d\n", err);
4050 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4052 /* reprogram the RAR[0] in case user changed it. */
4053 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
4058 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4059 * @rx_ring: ring to free buffers from
4061 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4063 struct device *dev = rx_ring->dev;
4067 /* ring already cleared, nothing to do */
4068 if (!rx_ring->rx_buffer_info)
4071 /* Free all the Rx ring sk_buffs */
4072 for (i = 0; i < rx_ring->count; i++) {
4073 struct ixgbe_rx_buffer *rx_buffer_info;
4075 rx_buffer_info = &rx_ring->rx_buffer_info[i];
4076 if (rx_buffer_info->dma) {
4077 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
4078 rx_ring->rx_buf_len,
4080 rx_buffer_info->dma = 0;
4082 if (rx_buffer_info->skb) {
4083 struct sk_buff *skb = rx_buffer_info->skb;
4084 rx_buffer_info->skb = NULL;
4085 /* We need to clean up RSC frag lists */
4086 skb = ixgbe_merge_active_tail(skb);
4087 ixgbe_close_active_frag_list(skb);
4088 if (IXGBE_CB(skb)->delay_unmap) {
4089 dma_unmap_single(dev,
4091 rx_ring->rx_buf_len,
4093 IXGBE_CB(skb)->dma = 0;
4094 IXGBE_CB(skb)->delay_unmap = false;
4098 if (!rx_buffer_info->page)
4100 if (rx_buffer_info->page_dma) {
4101 dma_unmap_page(dev, rx_buffer_info->page_dma,
4102 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4103 rx_buffer_info->page_dma = 0;
4105 put_page(rx_buffer_info->page);
4106 rx_buffer_info->page = NULL;
4107 rx_buffer_info->page_offset = 0;
4110 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4111 memset(rx_ring->rx_buffer_info, 0, size);
4113 /* Zero out the descriptor ring */
4114 memset(rx_ring->desc, 0, rx_ring->size);
4116 rx_ring->next_to_clean = 0;
4117 rx_ring->next_to_use = 0;
4121 * ixgbe_clean_tx_ring - Free Tx Buffers
4122 * @tx_ring: ring to be cleaned
4124 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4126 struct ixgbe_tx_buffer *tx_buffer_info;
4130 /* ring already cleared, nothing to do */
4131 if (!tx_ring->tx_buffer_info)
4134 /* Free all the Tx ring sk_buffs */
4135 for (i = 0; i < tx_ring->count; i++) {
4136 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4137 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4140 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4141 memset(tx_ring->tx_buffer_info, 0, size);
4143 /* Zero out the descriptor ring */
4144 memset(tx_ring->desc, 0, tx_ring->size);
4146 tx_ring->next_to_use = 0;
4147 tx_ring->next_to_clean = 0;
4151 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4152 * @adapter: board private structure
4154 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4158 for (i = 0; i < adapter->num_rx_queues; i++)
4159 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4163 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4164 * @adapter: board private structure
4166 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4170 for (i = 0; i < adapter->num_tx_queues; i++)
4171 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4174 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4176 struct hlist_node *node, *node2;
4177 struct ixgbe_fdir_filter *filter;
4179 spin_lock(&adapter->fdir_perfect_lock);
4181 hlist_for_each_entry_safe(filter, node, node2,
4182 &adapter->fdir_filter_list, fdir_node) {
4183 hlist_del(&filter->fdir_node);
4186 adapter->fdir_filter_count = 0;
4188 spin_unlock(&adapter->fdir_perfect_lock);
4191 void ixgbe_down(struct ixgbe_adapter *adapter)
4193 struct net_device *netdev = adapter->netdev;
4194 struct ixgbe_hw *hw = &adapter->hw;
4198 /* signal that we are down to the interrupt handler */
4199 set_bit(__IXGBE_DOWN, &adapter->state);
4201 /* disable receives */
4202 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4203 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4205 /* disable all enabled rx queues */
4206 for (i = 0; i < adapter->num_rx_queues; i++)
4207 /* this call also flushes the previous write */
4208 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4210 usleep_range(10000, 20000);
4212 netif_tx_stop_all_queues(netdev);
4214 /* call carrier off first to avoid false dev_watchdog timeouts */
4215 netif_carrier_off(netdev);
4216 netif_tx_disable(netdev);
4218 ixgbe_irq_disable(adapter);
4220 ixgbe_napi_disable_all(adapter);
4222 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4223 IXGBE_FLAG2_RESET_REQUESTED);
4224 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4226 del_timer_sync(&adapter->service_timer);
4228 if (adapter->num_vfs) {
4229 /* Clear EITR Select mapping */
4230 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4232 /* Mark all the VFs as inactive */
4233 for (i = 0 ; i < adapter->num_vfs; i++)
4234 adapter->vfinfo[i].clear_to_send = false;
4236 /* ping all the active vfs to let them know we are going down */
4237 ixgbe_ping_all_vfs(adapter);
4239 /* Disable all VFTE/VFRE TX/RX */
4240 ixgbe_disable_tx_rx(adapter);
4243 /* disable transmits in the hardware now that interrupts are off */
4244 for (i = 0; i < adapter->num_tx_queues; i++) {
4245 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4246 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4249 /* Disable the Tx DMA engine on 82599 and X540 */
4250 switch (hw->mac.type) {
4251 case ixgbe_mac_82599EB:
4252 case ixgbe_mac_X540:
4253 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4254 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4255 ~IXGBE_DMATXCTL_TE));
4261 if (!pci_channel_offline(adapter->pdev))
4262 ixgbe_reset(adapter);
4264 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4265 if (hw->mac.ops.disable_tx_laser &&
4266 ((hw->phy.multispeed_fiber) ||
4267 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4268 (hw->mac.type == ixgbe_mac_82599EB))))
4269 hw->mac.ops.disable_tx_laser(hw);
4271 ixgbe_clean_all_tx_rings(adapter);
4272 ixgbe_clean_all_rx_rings(adapter);
4274 #ifdef CONFIG_IXGBE_DCA
4275 /* since we reset the hardware DCA settings were cleared */
4276 ixgbe_setup_dca(adapter);
4281 * ixgbe_poll - NAPI Rx polling callback
4282 * @napi: structure for representing this polling device
4283 * @budget: how many packets driver is allowed to clean
4285 * This function is used for legacy and MSI, NAPI mode
4287 static int ixgbe_poll(struct napi_struct *napi, int budget)
4289 struct ixgbe_q_vector *q_vector =
4290 container_of(napi, struct ixgbe_q_vector, napi);
4291 struct ixgbe_adapter *adapter = q_vector->adapter;
4292 struct ixgbe_ring *ring;
4293 int per_ring_budget;
4294 bool clean_complete = true;
4296 #ifdef CONFIG_IXGBE_DCA
4297 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4298 ixgbe_update_dca(q_vector);
4301 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
4302 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
4304 /* attempt to distribute budget to each queue fairly, but don't allow
4305 * the budget to go below 1 because we'll exit polling */
4306 if (q_vector->rx.count > 1)
4307 per_ring_budget = max(budget/q_vector->rx.count, 1);
4309 per_ring_budget = budget;
4311 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
4312 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
4315 /* If all work not completed, return budget and keep polling */
4316 if (!clean_complete)
4319 /* all work done, exit the polling mode */
4320 napi_complete(napi);
4321 if (adapter->rx_itr_setting & 1)
4322 ixgbe_set_itr(q_vector);
4323 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4324 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
4330 * ixgbe_tx_timeout - Respond to a Tx Hang
4331 * @netdev: network interface device structure
4333 static void ixgbe_tx_timeout(struct net_device *netdev)
4335 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4337 /* Do the reset outside of interrupt context */
4338 ixgbe_tx_timeout_reset(adapter);
4342 * ixgbe_set_rss_queues: Allocate queues for RSS
4343 * @adapter: board private structure to initialize
4345 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4346 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4349 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4352 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4354 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4356 adapter->num_rx_queues = f->indices;
4357 adapter->num_tx_queues = f->indices;
4367 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4368 * @adapter: board private structure to initialize
4370 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4371 * to the original CPU that initiated the Tx session. This runs in addition
4372 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4373 * Rx load across CPUs using RSS.
4376 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4379 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4381 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4384 /* Flow Director must have RSS enabled */
4385 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4386 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4387 adapter->num_tx_queues = f_fdir->indices;
4388 adapter->num_rx_queues = f_fdir->indices;
4391 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4398 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4399 * @adapter: board private structure to initialize
4401 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4402 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4403 * rx queues out of the max number of rx queues, instead, it is used as the
4404 * index of the first rx queue used by FCoE.
4407 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4409 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4411 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4414 f->indices = min((int)num_online_cpus(), f->indices);
4416 adapter->num_rx_queues = 1;
4417 adapter->num_tx_queues = 1;
4419 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4420 e_info(probe, "FCoE enabled with RSS\n");
4421 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4422 ixgbe_set_fdir_queues(adapter);
4424 ixgbe_set_rss_queues(adapter);
4427 /* adding FCoE rx rings to the end */
4428 f->mask = adapter->num_rx_queues;
4429 adapter->num_rx_queues += f->indices;
4430 adapter->num_tx_queues += f->indices;
4434 #endif /* IXGBE_FCOE */
4436 /* Artificial max queue cap per traffic class in DCB mode */
4437 #define DCB_QUEUE_CAP 8
4439 #ifdef CONFIG_IXGBE_DCB
4440 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4442 int per_tc_q, q, i, offset = 0;
4443 struct net_device *dev = adapter->netdev;
4444 int tcs = netdev_get_num_tc(dev);
4449 /* Map queue offset and counts onto allocated tx queues */
4450 per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4451 q = min((int)num_online_cpus(), per_tc_q);
4453 for (i = 0; i < tcs; i++) {
4454 netdev_set_tc_queue(dev, i, q, offset);
4458 adapter->num_tx_queues = q * tcs;
4459 adapter->num_rx_queues = q * tcs;
4462 /* FCoE enabled queues require special configuration indexed
4463 * by feature specific indices and mask. Here we map FCoE
4464 * indices onto the DCB queue pairs allowing FCoE to own
4465 * configuration later.
4467 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4469 struct ixgbe_ring_feature *f =
4470 &adapter->ring_feature[RING_F_FCOE];
4472 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4473 f->indices = dev->tc_to_txq[tc].count;
4474 f->mask = dev->tc_to_txq[tc].offset;
4483 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4484 * @adapter: board private structure to initialize
4486 * IOV doesn't actually use anything, so just NAK the
4487 * request for now and let the other queue routines
4488 * figure out what to do.
4490 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4496 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4497 * @adapter: board private structure to initialize
4499 * This is the top level queue allocation routine. The order here is very
4500 * important, starting with the "most" number of features turned on at once,
4501 * and ending with the smallest set of features. This way large combinations
4502 * can be allocated if they're turned on, and smaller combinations are the
4503 * fallthrough conditions.
4506 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4508 /* Start with base case */
4509 adapter->num_rx_queues = 1;
4510 adapter->num_tx_queues = 1;
4511 adapter->num_rx_pools = adapter->num_rx_queues;
4512 adapter->num_rx_queues_per_pool = 1;
4514 if (ixgbe_set_sriov_queues(adapter))
4517 #ifdef CONFIG_IXGBE_DCB
4518 if (ixgbe_set_dcb_queues(adapter))
4523 if (ixgbe_set_fcoe_queues(adapter))
4526 #endif /* IXGBE_FCOE */
4527 if (ixgbe_set_fdir_queues(adapter))
4530 if (ixgbe_set_rss_queues(adapter))
4533 /* fallback to base case */
4534 adapter->num_rx_queues = 1;
4535 adapter->num_tx_queues = 1;
4538 if ((adapter->netdev->reg_state == NETREG_UNREGISTERED) ||
4539 (adapter->netdev->reg_state == NETREG_UNREGISTERING))
4542 /* Notify the stack of the (possibly) reduced queue counts. */
4543 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4544 return netif_set_real_num_rx_queues(adapter->netdev,
4545 adapter->num_rx_queues);
4548 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4551 int err, vector_threshold;
4553 /* We'll want at least 3 (vector_threshold):
4556 * 3) Other (Link Status Change, etc.)
4557 * 4) TCP Timer (optional)
4559 vector_threshold = MIN_MSIX_COUNT;
4561 /* The more we get, the more we will assign to Tx/Rx Cleanup
4562 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4563 * Right now, we simply care about how many we'll get; we'll
4564 * set them up later while requesting irq's.
4566 while (vectors >= vector_threshold) {
4567 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4569 if (!err) /* Success in acquiring all requested vectors. */
4572 vectors = 0; /* Nasty failure, quit now */
4573 else /* err == number of vectors we should try again with */
4577 if (vectors < vector_threshold) {
4578 /* Can't allocate enough MSI-X interrupts? Oh well.
4579 * This just means we'll go with either a single MSI
4580 * vector or fall back to legacy interrupts.
4582 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4583 "Unable to allocate MSI-X interrupts\n");
4584 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4585 kfree(adapter->msix_entries);
4586 adapter->msix_entries = NULL;
4588 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4590 * Adjust for only the vectors we'll use, which is minimum
4591 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4592 * vectors we were allocated.
4594 adapter->num_msix_vectors = min(vectors,
4595 adapter->max_msix_q_vectors + NON_Q_VECTORS);
4600 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4601 * @adapter: board private structure to initialize
4603 * Cache the descriptor ring offsets for RSS to the assigned rings.
4606 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4610 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4613 for (i = 0; i < adapter->num_rx_queues; i++)
4614 adapter->rx_ring[i]->reg_idx = i;
4615 for (i = 0; i < adapter->num_tx_queues; i++)
4616 adapter->tx_ring[i]->reg_idx = i;
4621 #ifdef CONFIG_IXGBE_DCB
4623 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4624 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4625 unsigned int *tx, unsigned int *rx)
4627 struct net_device *dev = adapter->netdev;
4628 struct ixgbe_hw *hw = &adapter->hw;
4629 u8 num_tcs = netdev_get_num_tc(dev);
4634 switch (hw->mac.type) {
4635 case ixgbe_mac_82598EB:
4639 case ixgbe_mac_82599EB:
4640 case ixgbe_mac_X540:
4645 } else if (tc < 5) {
4646 *tx = ((tc + 2) << 4);
4648 } else if (tc < num_tcs) {
4649 *tx = ((tc + 8) << 3);
4678 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4679 * @adapter: board private structure to initialize
4681 * Cache the descriptor ring offsets for DCB to the assigned rings.
4684 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4686 struct net_device *dev = adapter->netdev;
4688 u8 num_tcs = netdev_get_num_tc(dev);
4693 for (i = 0, k = 0; i < num_tcs; i++) {
4694 unsigned int tx_s, rx_s;
4695 u16 count = dev->tc_to_txq[i].count;
4697 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4698 for (j = 0; j < count; j++, k++) {
4699 adapter->tx_ring[k]->reg_idx = tx_s + j;
4700 adapter->rx_ring[k]->reg_idx = rx_s + j;
4701 adapter->tx_ring[k]->dcb_tc = i;
4702 adapter->rx_ring[k]->dcb_tc = i;
4711 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4712 * @adapter: board private structure to initialize
4714 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4717 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4722 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4723 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4724 for (i = 0; i < adapter->num_rx_queues; i++)
4725 adapter->rx_ring[i]->reg_idx = i;
4726 for (i = 0; i < adapter->num_tx_queues; i++)
4727 adapter->tx_ring[i]->reg_idx = i;
4736 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4737 * @adapter: board private structure to initialize
4739 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4742 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4744 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4746 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4748 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4751 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4752 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4753 ixgbe_cache_ring_fdir(adapter);
4755 ixgbe_cache_ring_rss(adapter);
4757 fcoe_rx_i = f->mask;
4758 fcoe_tx_i = f->mask;
4760 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4761 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4762 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4767 #endif /* IXGBE_FCOE */
4769 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4770 * @adapter: board private structure to initialize
4772 * SR-IOV doesn't use any descriptor rings but changes the default if
4773 * no other mapping is used.
4776 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4778 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4779 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4780 if (adapter->num_vfs)
4787 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4788 * @adapter: board private structure to initialize
4790 * Once we know the feature-set enabled for the device, we'll cache
4791 * the register offset the descriptor ring is assigned to.
4793 * Note, the order the various feature calls is important. It must start with
4794 * the "most" features enabled at the same time, then trickle down to the
4795 * least amount of features turned on at once.
4797 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4799 /* start with default case */
4800 adapter->rx_ring[0]->reg_idx = 0;
4801 adapter->tx_ring[0]->reg_idx = 0;
4803 if (ixgbe_cache_ring_sriov(adapter))
4806 #ifdef CONFIG_IXGBE_DCB
4807 if (ixgbe_cache_ring_dcb(adapter))
4812 if (ixgbe_cache_ring_fcoe(adapter))
4814 #endif /* IXGBE_FCOE */
4816 if (ixgbe_cache_ring_fdir(adapter))
4819 if (ixgbe_cache_ring_rss(adapter))
4824 * ixgbe_alloc_queues - Allocate memory for all rings
4825 * @adapter: board private structure to initialize
4827 * We allocate one ring per queue at run-time since we don't know the
4828 * number of queues at compile-time. The polling_netdev array is
4829 * intended for Multiqueue, but should work fine with a single queue.
4831 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4833 int rx = 0, tx = 0, nid = adapter->node;
4835 if (nid < 0 || !node_online(nid))
4836 nid = first_online_node;
4838 for (; tx < adapter->num_tx_queues; tx++) {
4839 struct ixgbe_ring *ring;
4841 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4843 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4845 goto err_allocation;
4846 ring->count = adapter->tx_ring_count;
4847 ring->queue_index = tx;
4848 ring->numa_node = nid;
4849 ring->dev = &adapter->pdev->dev;
4850 ring->netdev = adapter->netdev;
4852 adapter->tx_ring[tx] = ring;
4855 for (; rx < adapter->num_rx_queues; rx++) {
4856 struct ixgbe_ring *ring;
4858 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4860 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4862 goto err_allocation;
4863 ring->count = adapter->rx_ring_count;
4864 ring->queue_index = rx;
4865 ring->numa_node = nid;
4866 ring->dev = &adapter->pdev->dev;
4867 ring->netdev = adapter->netdev;
4870 * 82599 errata, UDP frames with a 0 checksum can be marked as
4873 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
4874 set_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state);
4876 adapter->rx_ring[rx] = ring;
4879 ixgbe_cache_ring_register(adapter);
4885 kfree(adapter->tx_ring[--tx]);
4888 kfree(adapter->rx_ring[--rx]);
4893 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4894 * @adapter: board private structure to initialize
4896 * Attempt to configure the interrupts using the best available
4897 * capabilities of the hardware and the kernel.
4899 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4901 struct ixgbe_hw *hw = &adapter->hw;
4903 int vector, v_budget;
4906 * It's easy to be greedy for MSI-X vectors, but it really
4907 * doesn't do us much good if we have a lot more vectors
4908 * than CPU's. So let's be conservative and only ask for
4909 * (roughly) the same number of vectors as there are CPU's.
4911 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4912 (int)num_online_cpus()) + NON_Q_VECTORS;
4915 * At the same time, hardware can only support a maximum of
4916 * hw.mac->max_msix_vectors vectors. With features
4917 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4918 * descriptor queues supported by our device. Thus, we cap it off in
4919 * those rare cases where the cpu count also exceeds our vector limit.
4921 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4923 /* A failure in MSI-X entry allocation isn't fatal, but it does
4924 * mean we disable MSI-X capabilities of the adapter. */
4925 adapter->msix_entries = kcalloc(v_budget,
4926 sizeof(struct msix_entry), GFP_KERNEL);
4927 if (adapter->msix_entries) {
4928 for (vector = 0; vector < v_budget; vector++)
4929 adapter->msix_entries[vector].entry = vector;
4931 ixgbe_acquire_msix_vectors(adapter, v_budget);
4933 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4937 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4938 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4939 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4941 "ATR is not supported while multiple "
4942 "queues are disabled. Disabling Flow Director\n");
4944 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4945 adapter->atr_sample_rate = 0;
4946 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4947 ixgbe_disable_sriov(adapter);
4949 err = ixgbe_set_num_queues(adapter);
4953 err = pci_enable_msi(adapter->pdev);
4955 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4957 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4958 "Unable to allocate MSI interrupt, "
4959 "falling back to legacy. Error: %d\n", err);
4969 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4970 * @adapter: board private structure to initialize
4972 * We allocate one q_vector per queue interrupt. If allocation fails we
4975 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4977 int v_idx, num_q_vectors;
4978 struct ixgbe_q_vector *q_vector;
4980 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4981 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4985 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4986 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4987 GFP_KERNEL, adapter->node);
4989 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4994 q_vector->adapter = adapter;
4995 q_vector->v_idx = v_idx;
4997 /* Allocate the affinity_hint cpumask, configure the mask */
4998 if (!alloc_cpumask_var(&q_vector->affinity_mask, GFP_KERNEL))
5000 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
5001 netif_napi_add(adapter->netdev, &q_vector->napi,
5003 adapter->q_vector[v_idx] = q_vector;
5011 q_vector = adapter->q_vector[v_idx];
5012 netif_napi_del(&q_vector->napi);
5013 free_cpumask_var(q_vector->affinity_mask);
5015 adapter->q_vector[v_idx] = NULL;
5021 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
5022 * @adapter: board private structure to initialize
5024 * This function frees the memory allocated to the q_vectors. In addition if
5025 * NAPI is enabled it will delete any references to the NAPI struct prior
5026 * to freeing the q_vector.
5028 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
5030 int v_idx, num_q_vectors;
5032 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
5033 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5037 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
5038 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx];
5039 adapter->q_vector[v_idx] = NULL;
5040 netif_napi_del(&q_vector->napi);
5041 free_cpumask_var(q_vector->affinity_mask);
5046 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
5048 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5049 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
5050 pci_disable_msix(adapter->pdev);
5051 kfree(adapter->msix_entries);
5052 adapter->msix_entries = NULL;
5053 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
5054 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
5055 pci_disable_msi(adapter->pdev);
5060 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
5061 * @adapter: board private structure to initialize
5063 * We determine which interrupt scheme to use based on...
5064 * - Kernel support (MSI, MSI-X)
5065 * - which can be user-defined (via MODULE_PARAM)
5066 * - Hardware queue count (num_*_queues)
5067 * - defined by miscellaneous hardware support/features (RSS, etc.)
5069 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
5073 /* Number of supported queues */
5074 err = ixgbe_set_num_queues(adapter);
5078 err = ixgbe_set_interrupt_capability(adapter);
5080 e_dev_err("Unable to setup interrupt capabilities\n");
5081 goto err_set_interrupt;
5084 err = ixgbe_alloc_q_vectors(adapter);
5086 e_dev_err("Unable to allocate memory for queue vectors\n");
5087 goto err_alloc_q_vectors;
5090 err = ixgbe_alloc_queues(adapter);
5092 e_dev_err("Unable to allocate memory for queues\n");
5093 goto err_alloc_queues;
5096 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
5097 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5098 adapter->num_rx_queues, adapter->num_tx_queues);
5100 set_bit(__IXGBE_DOWN, &adapter->state);
5105 ixgbe_free_q_vectors(adapter);
5106 err_alloc_q_vectors:
5107 ixgbe_reset_interrupt_capability(adapter);
5113 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5114 * @adapter: board private structure to clear interrupt scheme on
5116 * We go through and clear interrupt specific resources and reset the structure
5117 * to pre-load conditions
5119 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5123 for (i = 0; i < adapter->num_tx_queues; i++) {
5124 kfree(adapter->tx_ring[i]);
5125 adapter->tx_ring[i] = NULL;
5127 for (i = 0; i < adapter->num_rx_queues; i++) {
5128 struct ixgbe_ring *ring = adapter->rx_ring[i];
5130 /* ixgbe_get_stats64() might access this ring, we must wait
5131 * a grace period before freeing it.
5133 kfree_rcu(ring, rcu);
5134 adapter->rx_ring[i] = NULL;
5137 adapter->num_tx_queues = 0;
5138 adapter->num_rx_queues = 0;
5140 ixgbe_free_q_vectors(adapter);
5141 ixgbe_reset_interrupt_capability(adapter);
5145 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5146 * @adapter: board private structure to initialize
5148 * ixgbe_sw_init initializes the Adapter private data structure.
5149 * Fields are initialized based on PCI device information and
5150 * OS network device settings (MTU size).
5152 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5154 struct ixgbe_hw *hw = &adapter->hw;
5155 struct pci_dev *pdev = adapter->pdev;
5157 #ifdef CONFIG_IXGBE_DCB
5159 struct tc_configuration *tc;
5162 /* PCI config space info */
5164 hw->vendor_id = pdev->vendor;
5165 hw->device_id = pdev->device;
5166 hw->revision_id = pdev->revision;
5167 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5168 hw->subsystem_device_id = pdev->subsystem_device;
5170 /* Set capability flags */
5171 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5172 adapter->ring_feature[RING_F_RSS].indices = rss;
5173 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
5174 switch (hw->mac.type) {
5175 case ixgbe_mac_82598EB:
5176 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5177 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5178 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
5180 case ixgbe_mac_X540:
5181 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5182 case ixgbe_mac_82599EB:
5183 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
5184 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5185 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5186 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5187 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5188 /* Flow Director hash filters enabled */
5189 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5190 adapter->atr_sample_rate = 20;
5191 adapter->ring_feature[RING_F_FDIR].indices =
5192 IXGBE_MAX_FDIR_INDICES;
5193 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5195 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5196 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5197 adapter->ring_feature[RING_F_FCOE].indices = 0;
5198 #ifdef CONFIG_IXGBE_DCB
5199 /* Default traffic class to use for FCoE */
5200 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5202 #endif /* IXGBE_FCOE */
5208 /* n-tuple support exists, always init our spinlock */
5209 spin_lock_init(&adapter->fdir_perfect_lock);
5211 #ifdef CONFIG_IXGBE_DCB
5212 switch (hw->mac.type) {
5213 case ixgbe_mac_X540:
5214 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5215 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5218 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5219 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5223 /* Configure DCB traffic classes */
5224 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5225 tc = &adapter->dcb_cfg.tc_config[j];
5226 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5227 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5228 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5229 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5230 tc->dcb_pfc = pfc_disabled;
5233 /* Initialize default user to priority mapping, UPx->TC0 */
5234 tc = &adapter->dcb_cfg.tc_config[0];
5235 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5236 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5238 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5239 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5240 adapter->dcb_cfg.pfc_mode_enable = false;
5241 adapter->dcb_set_bitmap = 0x00;
5242 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5243 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5248 /* default flow control settings */
5249 hw->fc.requested_mode = ixgbe_fc_full;
5250 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
5252 adapter->last_lfc_mode = hw->fc.current_mode;
5254 ixgbe_pbthresh_setup(adapter);
5255 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5256 hw->fc.send_xon = true;
5257 hw->fc.disable_fc_autoneg = false;
5259 /* enable itr by default in dynamic mode */
5260 adapter->rx_itr_setting = 1;
5261 adapter->tx_itr_setting = 1;
5263 /* set defaults for eitr in MegaBytes */
5264 adapter->eitr_low = 10;
5265 adapter->eitr_high = 20;
5267 /* set default ring sizes */
5268 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5269 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5271 /* set default work limits */
5272 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
5274 /* initialize eeprom parameters */
5275 if (ixgbe_init_eeprom_params_generic(hw)) {
5276 e_dev_err("EEPROM initialization failed\n");
5280 /* get assigned NUMA node */
5281 adapter->node = dev_to_node(&pdev->dev);
5283 set_bit(__IXGBE_DOWN, &adapter->state);
5289 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5290 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5292 * Return 0 on success, negative on failure
5294 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5296 struct device *dev = tx_ring->dev;
5299 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5300 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
5301 if (!tx_ring->tx_buffer_info)
5302 tx_ring->tx_buffer_info = vzalloc(size);
5303 if (!tx_ring->tx_buffer_info)
5306 /* round up to nearest 4K */
5307 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5308 tx_ring->size = ALIGN(tx_ring->size, 4096);
5310 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5311 &tx_ring->dma, GFP_KERNEL);
5315 tx_ring->next_to_use = 0;
5316 tx_ring->next_to_clean = 0;
5320 vfree(tx_ring->tx_buffer_info);
5321 tx_ring->tx_buffer_info = NULL;
5322 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5327 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5328 * @adapter: board private structure
5330 * If this function returns with an error, then it's possible one or
5331 * more of the rings is populated (while the rest are not). It is the
5332 * callers duty to clean those orphaned rings.
5334 * Return 0 on success, negative on failure
5336 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5340 for (i = 0; i < adapter->num_tx_queues; i++) {
5341 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5344 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5352 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5353 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5355 * Returns 0 on success, negative on failure
5357 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5359 struct device *dev = rx_ring->dev;
5362 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5363 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5364 if (!rx_ring->rx_buffer_info)
5365 rx_ring->rx_buffer_info = vzalloc(size);
5366 if (!rx_ring->rx_buffer_info)
5369 /* Round up to nearest 4K */
5370 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5371 rx_ring->size = ALIGN(rx_ring->size, 4096);
5373 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5374 &rx_ring->dma, GFP_KERNEL);
5379 rx_ring->next_to_clean = 0;
5380 rx_ring->next_to_use = 0;
5384 vfree(rx_ring->rx_buffer_info);
5385 rx_ring->rx_buffer_info = NULL;
5386 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5391 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5392 * @adapter: board private structure
5394 * If this function returns with an error, then it's possible one or
5395 * more of the rings is populated (while the rest are not). It is the
5396 * callers duty to clean those orphaned rings.
5398 * Return 0 on success, negative on failure
5400 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5404 for (i = 0; i < adapter->num_rx_queues; i++) {
5405 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5408 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5416 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5417 * @tx_ring: Tx descriptor ring for a specific queue
5419 * Free all transmit software resources
5421 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5423 ixgbe_clean_tx_ring(tx_ring);
5425 vfree(tx_ring->tx_buffer_info);
5426 tx_ring->tx_buffer_info = NULL;
5428 /* if not set, then don't free */
5432 dma_free_coherent(tx_ring->dev, tx_ring->size,
5433 tx_ring->desc, tx_ring->dma);
5435 tx_ring->desc = NULL;
5439 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5440 * @adapter: board private structure
5442 * Free all transmit software resources
5444 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5448 for (i = 0; i < adapter->num_tx_queues; i++)
5449 if (adapter->tx_ring[i]->desc)
5450 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5454 * ixgbe_free_rx_resources - Free Rx Resources
5455 * @rx_ring: ring to clean the resources from
5457 * Free all receive software resources
5459 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5461 ixgbe_clean_rx_ring(rx_ring);
5463 vfree(rx_ring->rx_buffer_info);
5464 rx_ring->rx_buffer_info = NULL;
5466 /* if not set, then don't free */
5470 dma_free_coherent(rx_ring->dev, rx_ring->size,
5471 rx_ring->desc, rx_ring->dma);
5473 rx_ring->desc = NULL;
5477 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5478 * @adapter: board private structure
5480 * Free all receive software resources
5482 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5486 for (i = 0; i < adapter->num_rx_queues; i++)
5487 if (adapter->rx_ring[i]->desc)
5488 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5492 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5493 * @netdev: network interface device structure
5494 * @new_mtu: new value for maximum frame size
5496 * Returns 0 on success, negative on failure
5498 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5500 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5501 struct ixgbe_hw *hw = &adapter->hw;
5502 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5504 /* MTU < 68 is an error and causes problems on some kernels */
5505 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5506 hw->mac.type != ixgbe_mac_X540) {
5507 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5510 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5514 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5515 /* must set new MTU before calling down or up */
5516 netdev->mtu = new_mtu;
5518 if (netif_running(netdev))
5519 ixgbe_reinit_locked(adapter);
5525 * ixgbe_open - Called when a network interface is made active
5526 * @netdev: network interface device structure
5528 * Returns 0 on success, negative value on failure
5530 * The open entry point is called when a network interface is made
5531 * active by the system (IFF_UP). At this point all resources needed
5532 * for transmit and receive operations are allocated, the interrupt
5533 * handler is registered with the OS, the watchdog timer is started,
5534 * and the stack is notified that the interface is ready.
5536 static int ixgbe_open(struct net_device *netdev)
5538 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5541 /* disallow open during test */
5542 if (test_bit(__IXGBE_TESTING, &adapter->state))
5545 netif_carrier_off(netdev);
5547 /* allocate transmit descriptors */
5548 err = ixgbe_setup_all_tx_resources(adapter);
5552 /* allocate receive descriptors */
5553 err = ixgbe_setup_all_rx_resources(adapter);
5557 ixgbe_configure(adapter);
5559 err = ixgbe_request_irq(adapter);
5563 ixgbe_up_complete(adapter);
5569 ixgbe_free_all_rx_resources(adapter);
5571 ixgbe_free_all_tx_resources(adapter);
5572 ixgbe_reset(adapter);
5578 * ixgbe_close - Disables a network interface
5579 * @netdev: network interface device structure
5581 * Returns 0, this is not allowed to fail
5583 * The close entry point is called when an interface is de-activated
5584 * by the OS. The hardware is still under the drivers control, but
5585 * needs to be disabled. A global MAC reset is issued to stop the
5586 * hardware, and all transmit and receive resources are freed.
5588 static int ixgbe_close(struct net_device *netdev)
5590 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5592 ixgbe_down(adapter);
5593 ixgbe_free_irq(adapter);
5595 ixgbe_fdir_filter_exit(adapter);
5597 ixgbe_free_all_tx_resources(adapter);
5598 ixgbe_free_all_rx_resources(adapter);
5600 ixgbe_release_hw_control(adapter);
5606 static int ixgbe_resume(struct pci_dev *pdev)
5608 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5609 struct net_device *netdev = adapter->netdev;
5612 pci_set_power_state(pdev, PCI_D0);
5613 pci_restore_state(pdev);
5615 * pci_restore_state clears dev->state_saved so call
5616 * pci_save_state to restore it.
5618 pci_save_state(pdev);
5620 err = pci_enable_device_mem(pdev);
5622 e_dev_err("Cannot enable PCI device from suspend\n");
5625 pci_set_master(pdev);
5627 pci_wake_from_d3(pdev, false);
5629 err = ixgbe_init_interrupt_scheme(adapter);
5631 e_dev_err("Cannot initialize interrupts for device\n");
5635 ixgbe_reset(adapter);
5637 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5639 if (netif_running(netdev)) {
5640 err = ixgbe_open(netdev);
5645 netif_device_attach(netdev);
5649 #endif /* CONFIG_PM */
5651 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5653 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5654 struct net_device *netdev = adapter->netdev;
5655 struct ixgbe_hw *hw = &adapter->hw;
5657 u32 wufc = adapter->wol;
5662 netif_device_detach(netdev);
5664 if (netif_running(netdev)) {
5665 ixgbe_down(adapter);
5666 ixgbe_free_irq(adapter);
5667 ixgbe_free_all_tx_resources(adapter);
5668 ixgbe_free_all_rx_resources(adapter);
5671 ixgbe_clear_interrupt_scheme(adapter);
5673 kfree(adapter->ixgbe_ieee_pfc);
5674 kfree(adapter->ixgbe_ieee_ets);
5678 retval = pci_save_state(pdev);
5684 ixgbe_set_rx_mode(netdev);
5686 /* turn on all-multi mode if wake on multicast is enabled */
5687 if (wufc & IXGBE_WUFC_MC) {
5688 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5689 fctrl |= IXGBE_FCTRL_MPE;
5690 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5693 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5694 ctrl |= IXGBE_CTRL_GIO_DIS;
5695 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5697 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5699 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5700 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5703 switch (hw->mac.type) {
5704 case ixgbe_mac_82598EB:
5705 pci_wake_from_d3(pdev, false);
5707 case ixgbe_mac_82599EB:
5708 case ixgbe_mac_X540:
5709 pci_wake_from_d3(pdev, !!wufc);
5715 *enable_wake = !!wufc;
5717 ixgbe_release_hw_control(adapter);
5719 pci_disable_device(pdev);
5725 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5730 retval = __ixgbe_shutdown(pdev, &wake);
5735 pci_prepare_to_sleep(pdev);
5737 pci_wake_from_d3(pdev, false);
5738 pci_set_power_state(pdev, PCI_D3hot);
5743 #endif /* CONFIG_PM */
5745 static void ixgbe_shutdown(struct pci_dev *pdev)
5749 __ixgbe_shutdown(pdev, &wake);
5751 if (system_state == SYSTEM_POWER_OFF) {
5752 pci_wake_from_d3(pdev, wake);
5753 pci_set_power_state(pdev, PCI_D3hot);
5758 * ixgbe_update_stats - Update the board statistics counters.
5759 * @adapter: board private structure
5761 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5763 struct net_device *netdev = adapter->netdev;
5764 struct ixgbe_hw *hw = &adapter->hw;
5765 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5767 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5768 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5769 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5770 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
5772 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5774 u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0;
5775 #endif /* IXGBE_FCOE */
5777 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5778 test_bit(__IXGBE_RESETTING, &adapter->state))
5781 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5784 for (i = 0; i < 16; i++)
5785 adapter->hw_rx_no_dma_resources +=
5786 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5787 for (i = 0; i < adapter->num_rx_queues; i++) {
5788 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5789 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5791 adapter->rsc_total_count = rsc_count;
5792 adapter->rsc_total_flush = rsc_flush;
5795 for (i = 0; i < adapter->num_rx_queues; i++) {
5796 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5797 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5798 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5799 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5800 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5801 bytes += rx_ring->stats.bytes;
5802 packets += rx_ring->stats.packets;
5804 adapter->non_eop_descs = non_eop_descs;
5805 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5806 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5807 adapter->hw_csum_rx_error = hw_csum_rx_error;
5808 netdev->stats.rx_bytes = bytes;
5809 netdev->stats.rx_packets = packets;
5813 /* gather some stats to the adapter struct that are per queue */
5814 for (i = 0; i < adapter->num_tx_queues; i++) {
5815 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5816 restart_queue += tx_ring->tx_stats.restart_queue;
5817 tx_busy += tx_ring->tx_stats.tx_busy;
5818 bytes += tx_ring->stats.bytes;
5819 packets += tx_ring->stats.packets;
5821 adapter->restart_queue = restart_queue;
5822 adapter->tx_busy = tx_busy;
5823 netdev->stats.tx_bytes = bytes;
5824 netdev->stats.tx_packets = packets;
5826 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5828 /* 8 register reads */
5829 for (i = 0; i < 8; i++) {
5830 /* for packet buffers not used, the register should read 0 */
5831 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5833 hwstats->mpc[i] += mpc;
5834 total_mpc += hwstats->mpc[i];
5835 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5836 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5837 switch (hw->mac.type) {
5838 case ixgbe_mac_82598EB:
5839 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5840 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5841 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5842 hwstats->pxonrxc[i] +=
5843 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5845 case ixgbe_mac_82599EB:
5846 case ixgbe_mac_X540:
5847 hwstats->pxonrxc[i] +=
5848 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5855 /*16 register reads */
5856 for (i = 0; i < 16; i++) {
5857 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5858 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5859 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5860 (hw->mac.type == ixgbe_mac_X540)) {
5861 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5862 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5863 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5864 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5868 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5869 /* work around hardware counting issue */
5870 hwstats->gprc -= missed_rx;
5872 ixgbe_update_xoff_received(adapter);
5874 /* 82598 hardware only has a 32 bit counter in the high register */
5875 switch (hw->mac.type) {
5876 case ixgbe_mac_82598EB:
5877 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5878 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5879 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5880 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5882 case ixgbe_mac_X540:
5883 /* OS2BMC stats are X540 only*/
5884 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5885 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5886 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5887 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5888 case ixgbe_mac_82599EB:
5889 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5890 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5891 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5892 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5893 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5894 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5895 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5896 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5897 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5899 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5900 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5901 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5902 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5903 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5904 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5905 /* Add up per cpu counters for total ddp aloc fail */
5906 if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) {
5907 for_each_possible_cpu(cpu) {
5908 fcoe_noddp_counts_sum +=
5909 *per_cpu_ptr(fcoe->pcpu_noddp, cpu);
5910 fcoe_noddp_ext_buff_counts_sum +=
5912 pcpu_noddp_ext_buff, cpu);
5915 hwstats->fcoe_noddp = fcoe_noddp_counts_sum;
5916 hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum;
5917 #endif /* IXGBE_FCOE */
5922 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5923 hwstats->bprc += bprc;
5924 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5925 if (hw->mac.type == ixgbe_mac_82598EB)
5926 hwstats->mprc -= bprc;
5927 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5928 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5929 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5930 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5931 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5932 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5933 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5934 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5935 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5936 hwstats->lxontxc += lxon;
5937 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5938 hwstats->lxofftxc += lxoff;
5939 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5940 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5942 * 82598 errata - tx of flow control packets is included in tx counters
5944 xon_off_tot = lxon + lxoff;
5945 hwstats->gptc -= xon_off_tot;
5946 hwstats->mptc -= xon_off_tot;
5947 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5948 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5949 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5950 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5951 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5952 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5953 hwstats->ptc64 -= xon_off_tot;
5954 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5955 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5956 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5957 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5958 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5959 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5961 /* Fill out the OS statistics structure */
5962 netdev->stats.multicast = hwstats->mprc;
5965 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5966 netdev->stats.rx_dropped = 0;
5967 netdev->stats.rx_length_errors = hwstats->rlec;
5968 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5969 netdev->stats.rx_missed_errors = total_mpc;
5973 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5974 * @adapter - pointer to the device adapter structure
5976 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5978 struct ixgbe_hw *hw = &adapter->hw;
5981 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5984 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5986 /* if interface is down do nothing */
5987 if (test_bit(__IXGBE_DOWN, &adapter->state))
5990 /* do nothing if we are not using signature filters */
5991 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5994 adapter->fdir_overflow++;
5996 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5997 for (i = 0; i < adapter->num_tx_queues; i++)
5998 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5999 &(adapter->tx_ring[i]->state));
6000 /* re-enable flow director interrupts */
6001 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
6003 e_err(probe, "failed to finish FDIR re-initialization, "
6004 "ignored adding FDIR ATR filters\n");
6009 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
6010 * @adapter - pointer to the device adapter structure
6012 * This function serves two purposes. First it strobes the interrupt lines
6013 * in order to make certain interrupts are occurring. Secondly it sets the
6014 * bits needed to check for TX hangs. As a result we should immediately
6015 * determine if a hang has occurred.
6017 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
6019 struct ixgbe_hw *hw = &adapter->hw;
6023 /* If we're down or resetting, just bail */
6024 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6025 test_bit(__IXGBE_RESETTING, &adapter->state))
6028 /* Force detection of hung controller */
6029 if (netif_carrier_ok(adapter->netdev)) {
6030 for (i = 0; i < adapter->num_tx_queues; i++)
6031 set_check_for_tx_hang(adapter->tx_ring[i]);
6034 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6036 * for legacy and MSI interrupts don't set any bits
6037 * that are enabled for EIAM, because this operation
6038 * would set *both* EIMS and EICS for any bit in EIAM
6040 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6041 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
6043 /* get one bit for every active tx/rx interrupt vector */
6044 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
6045 struct ixgbe_q_vector *qv = adapter->q_vector[i];
6046 if (qv->rx.ring || qv->tx.ring)
6047 eics |= ((u64)1 << i);
6051 /* Cause software interrupt to ensure rings are cleaned */
6052 ixgbe_irq_rearm_queues(adapter, eics);
6057 * ixgbe_watchdog_update_link - update the link status
6058 * @adapter - pointer to the device adapter structure
6059 * @link_speed - pointer to a u32 to store the link_speed
6061 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
6063 struct ixgbe_hw *hw = &adapter->hw;
6064 u32 link_speed = adapter->link_speed;
6065 bool link_up = adapter->link_up;
6068 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6071 if (hw->mac.ops.check_link) {
6072 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
6074 /* always assume link is up, if no check link function */
6075 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6079 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6080 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
6081 hw->mac.ops.fc_enable(hw, i);
6083 hw->mac.ops.fc_enable(hw, 0);
6088 time_after(jiffies, (adapter->link_check_timeout +
6089 IXGBE_TRY_LINK_TIMEOUT))) {
6090 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6091 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6092 IXGBE_WRITE_FLUSH(hw);
6095 adapter->link_up = link_up;
6096 adapter->link_speed = link_speed;
6100 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6101 * print link up message
6102 * @adapter - pointer to the device adapter structure
6104 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
6106 struct net_device *netdev = adapter->netdev;
6107 struct ixgbe_hw *hw = &adapter->hw;
6108 u32 link_speed = adapter->link_speed;
6109 bool flow_rx, flow_tx;
6111 /* only continue if link was previously down */
6112 if (netif_carrier_ok(netdev))
6115 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
6117 switch (hw->mac.type) {
6118 case ixgbe_mac_82598EB: {
6119 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6120 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6121 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6122 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6125 case ixgbe_mac_X540:
6126 case ixgbe_mac_82599EB: {
6127 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6128 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6129 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6130 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6138 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6139 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6141 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6143 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6146 ((flow_rx && flow_tx) ? "RX/TX" :
6148 (flow_tx ? "TX" : "None"))));
6150 netif_carrier_on(netdev);
6151 ixgbe_check_vf_rate_limit(adapter);
6155 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6156 * print link down message
6157 * @adapter - pointer to the adapter structure
6159 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
6161 struct net_device *netdev = adapter->netdev;
6162 struct ixgbe_hw *hw = &adapter->hw;
6164 adapter->link_up = false;
6165 adapter->link_speed = 0;
6167 /* only continue if link was up previously */
6168 if (!netif_carrier_ok(netdev))
6171 /* poll for SFP+ cable when link is down */
6172 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6173 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
6175 e_info(drv, "NIC Link is Down\n");
6176 netif_carrier_off(netdev);
6180 * ixgbe_watchdog_flush_tx - flush queues on link down
6181 * @adapter - pointer to the device adapter structure
6183 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6186 int some_tx_pending = 0;
6188 if (!netif_carrier_ok(adapter->netdev)) {
6189 for (i = 0; i < adapter->num_tx_queues; i++) {
6190 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6191 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6192 some_tx_pending = 1;
6197 if (some_tx_pending) {
6198 /* We've lost link, so the controller stops DMA,
6199 * but we've got queued Tx work that's never going
6200 * to get done, so reset controller to flush Tx.
6201 * (Do the reset outside of interrupt context).
6203 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
6208 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6212 /* Do not perform spoof check for 82598 */
6213 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6216 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6219 * ssvpc register is cleared on read, if zero then no
6220 * spoofed packets in the last interval.
6225 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6229 * ixgbe_watchdog_subtask - check and bring link up
6230 * @adapter - pointer to the device adapter structure
6232 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6234 /* if interface is down do nothing */
6235 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6236 test_bit(__IXGBE_RESETTING, &adapter->state))
6239 ixgbe_watchdog_update_link(adapter);
6241 if (adapter->link_up)
6242 ixgbe_watchdog_link_is_up(adapter);
6244 ixgbe_watchdog_link_is_down(adapter);
6246 ixgbe_spoof_check(adapter);
6247 ixgbe_update_stats(adapter);
6249 ixgbe_watchdog_flush_tx(adapter);
6253 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6254 * @adapter - the ixgbe adapter structure
6256 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6258 struct ixgbe_hw *hw = &adapter->hw;
6261 /* not searching for SFP so there is nothing to do here */
6262 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6263 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6266 /* someone else is in init, wait until next service event */
6267 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6270 err = hw->phy.ops.identify_sfp(hw);
6271 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6274 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6275 /* If no cable is present, then we need to reset
6276 * the next time we find a good cable. */
6277 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6284 /* exit if reset not needed */
6285 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6288 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6291 * A module may be identified correctly, but the EEPROM may not have
6292 * support for that module. setup_sfp() will fail in that case, so
6293 * we should not allow that module to load.
6295 if (hw->mac.type == ixgbe_mac_82598EB)
6296 err = hw->phy.ops.reset(hw);
6298 err = hw->mac.ops.setup_sfp(hw);
6300 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6303 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6304 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6307 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6309 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6310 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6311 e_dev_err("failed to initialize because an unsupported "
6312 "SFP+ module type was detected.\n");
6313 e_dev_err("Reload the driver after installing a "
6314 "supported module.\n");
6315 unregister_netdev(adapter->netdev);
6320 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6321 * @adapter - the ixgbe adapter structure
6323 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6325 struct ixgbe_hw *hw = &adapter->hw;
6329 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6332 /* someone else is in init, wait until next service event */
6333 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6336 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6338 autoneg = hw->phy.autoneg_advertised;
6339 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6340 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6341 if (hw->mac.ops.setup_link)
6342 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6344 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6345 adapter->link_check_timeout = jiffies;
6346 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6349 #ifdef CONFIG_PCI_IOV
6350 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6353 struct ixgbe_hw *hw = &adapter->hw;
6354 struct net_device *netdev = adapter->netdev;
6358 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6359 if (gpc) /* If incrementing then no need for the check below */
6362 * Check to see if a bad DMA write target from an errant or
6363 * malicious VF has caused a PCIe error. If so then we can
6364 * issue a VFLR to the offending VF(s) and then resume without
6365 * requesting a full slot reset.
6368 for (vf = 0; vf < adapter->num_vfs; vf++) {
6369 ciaa = (vf << 16) | 0x80000000;
6370 /* 32 bit read so align, we really want status at offset 6 */
6371 ciaa |= PCI_COMMAND;
6372 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6373 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6375 /* disable debug mode asap after reading data */
6376 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6377 /* Get the upper 16 bits which will be the PCI status reg */
6379 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6380 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6382 ciaa = (vf << 16) | 0x80000000;
6384 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6385 ciad = 0x00008000; /* VFLR */
6386 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6388 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6395 * ixgbe_service_timer - Timer Call-back
6396 * @data: pointer to adapter cast into an unsigned long
6398 static void ixgbe_service_timer(unsigned long data)
6400 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6401 unsigned long next_event_offset;
6404 #ifdef CONFIG_PCI_IOV
6408 * don't bother with SR-IOV VF DMA hang check if there are
6409 * no VFs or the link is down
6411 if (!adapter->num_vfs ||
6412 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) {
6414 goto normal_timer_service;
6417 /* If we have VFs allocated then we must check for DMA hangs */
6418 ixgbe_check_for_bad_vf(adapter);
6419 next_event_offset = HZ / 50;
6420 adapter->timer_event_accumulator++;
6422 if (adapter->timer_event_accumulator >= 100) {
6424 adapter->timer_event_accumulator = 0;
6427 goto schedule_event;
6429 normal_timer_service:
6431 /* poll faster when waiting for link */
6432 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6433 next_event_offset = HZ / 10;
6435 next_event_offset = HZ * 2;
6437 #ifdef CONFIG_PCI_IOV
6440 /* Reset the timer */
6441 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6444 ixgbe_service_event_schedule(adapter);
6447 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6449 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6452 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6454 /* If we're already down or resetting, just bail */
6455 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6456 test_bit(__IXGBE_RESETTING, &adapter->state))
6459 ixgbe_dump(adapter);
6460 netdev_err(adapter->netdev, "Reset adapter\n");
6461 adapter->tx_timeout_count++;
6463 ixgbe_reinit_locked(adapter);
6467 * ixgbe_service_task - manages and runs subtasks
6468 * @work: pointer to work_struct containing our data
6470 static void ixgbe_service_task(struct work_struct *work)
6472 struct ixgbe_adapter *adapter = container_of(work,
6473 struct ixgbe_adapter,
6476 ixgbe_reset_subtask(adapter);
6477 ixgbe_sfp_detection_subtask(adapter);
6478 ixgbe_sfp_link_config_subtask(adapter);
6479 ixgbe_check_overtemp_subtask(adapter);
6480 ixgbe_watchdog_subtask(adapter);
6481 ixgbe_fdir_reinit_subtask(adapter);
6482 ixgbe_check_hang_subtask(adapter);
6484 ixgbe_service_event_complete(adapter);
6487 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6488 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
6490 struct ixgbe_adv_tx_context_desc *context_desc;
6491 u16 i = tx_ring->next_to_use;
6493 context_desc = IXGBE_TX_CTXTDESC(tx_ring, i);
6496 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
6498 /* set bits to identify this as an advanced context descriptor */
6499 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
6501 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6502 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
6503 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
6504 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6507 static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6508 u32 tx_flags, __be16 protocol, u8 *hdr_len)
6511 u32 vlan_macip_lens, type_tucmd;
6512 u32 mss_l4len_idx, l4len;
6514 if (!skb_is_gso(skb))
6517 if (skb_header_cloned(skb)) {
6518 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6523 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6524 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6526 if (protocol == __constant_htons(ETH_P_IP)) {
6527 struct iphdr *iph = ip_hdr(skb);
6530 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6534 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6535 } else if (skb_is_gso_v6(skb)) {
6536 ipv6_hdr(skb)->payload_len = 0;
6537 tcp_hdr(skb)->check =
6538 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6539 &ipv6_hdr(skb)->daddr,
6543 l4len = tcp_hdrlen(skb);
6544 *hdr_len = skb_transport_offset(skb) + l4len;
6546 /* mss_l4len_id: use 1 as index for TSO */
6547 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6548 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6549 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6551 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6552 vlan_macip_lens = skb_network_header_len(skb);
6553 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6554 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6556 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6562 static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6563 struct sk_buff *skb, u32 tx_flags,
6566 u32 vlan_macip_lens = 0;
6567 u32 mss_l4len_idx = 0;
6570 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6571 if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6572 !(tx_flags & IXGBE_TX_FLAGS_TXSW))
6577 case __constant_htons(ETH_P_IP):
6578 vlan_macip_lens |= skb_network_header_len(skb);
6579 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6580 l4_hdr = ip_hdr(skb)->protocol;
6582 case __constant_htons(ETH_P_IPV6):
6583 vlan_macip_lens |= skb_network_header_len(skb);
6584 l4_hdr = ipv6_hdr(skb)->nexthdr;
6587 if (unlikely(net_ratelimit())) {
6588 dev_warn(tx_ring->dev,
6589 "partial checksum but proto=%x!\n",
6597 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6598 mss_l4len_idx = tcp_hdrlen(skb) <<
6599 IXGBE_ADVTXD_L4LEN_SHIFT;
6602 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6603 mss_l4len_idx = sizeof(struct sctphdr) <<
6604 IXGBE_ADVTXD_L4LEN_SHIFT;
6607 mss_l4len_idx = sizeof(struct udphdr) <<
6608 IXGBE_ADVTXD_L4LEN_SHIFT;
6611 if (unlikely(net_ratelimit())) {
6612 dev_warn(tx_ring->dev,
6613 "partial checksum but l4 proto=%x!\n",
6620 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6621 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6623 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6624 type_tucmd, mss_l4len_idx);
6626 return (skb->ip_summed == CHECKSUM_PARTIAL);
6629 static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
6631 /* set type for advanced descriptor with frame checksum insertion */
6632 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6633 IXGBE_ADVTXD_DCMD_IFCS |
6634 IXGBE_ADVTXD_DCMD_DEXT);
6636 /* set HW vlan bit if vlan is present */
6637 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
6638 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
6640 /* set segmentation enable bits for TSO/FSO */
6642 if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
6644 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6646 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
6651 static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
6653 __le32 olinfo_status =
6654 cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
6656 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6657 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
6658 (1 << IXGBE_ADVTXD_IDX_SHIFT));
6659 /* enble IPv4 checksum for TSO */
6660 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6661 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
6664 /* enable L4 checksum for TSO and TX checksum offload */
6665 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6666 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
6669 /* use index 1 context for FCOE/FSO */
6670 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6671 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
6672 (1 << IXGBE_ADVTXD_IDX_SHIFT));
6676 * Check Context must be set if Tx switch is enabled, which it
6677 * always is for case where virtual functions are running
6679 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6680 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6682 return olinfo_status;
6685 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6688 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6689 struct sk_buff *skb,
6690 struct ixgbe_tx_buffer *first,
6694 struct device *dev = tx_ring->dev;
6695 struct ixgbe_tx_buffer *tx_buffer_info;
6696 union ixgbe_adv_tx_desc *tx_desc;
6698 __le32 cmd_type, olinfo_status;
6699 struct skb_frag_struct *frag;
6701 unsigned int data_len = skb->data_len;
6702 unsigned int size = skb_headlen(skb);
6704 u32 paylen = skb->len - hdr_len;
6705 u16 i = tx_ring->next_to_use;
6709 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6710 if (data_len >= sizeof(struct fcoe_crc_eof)) {
6711 data_len -= sizeof(struct fcoe_crc_eof);
6713 size -= sizeof(struct fcoe_crc_eof) - data_len;
6719 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
6720 if (dma_mapping_error(dev, dma))
6723 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6724 olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
6726 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6729 while (size > IXGBE_MAX_DATA_PER_TXD) {
6730 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6731 tx_desc->read.cmd_type_len =
6732 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6733 tx_desc->read.olinfo_status = olinfo_status;
6735 offset += IXGBE_MAX_DATA_PER_TXD;
6736 size -= IXGBE_MAX_DATA_PER_TXD;
6740 if (i == tx_ring->count) {
6741 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6746 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6747 tx_buffer_info->length = offset + size;
6748 tx_buffer_info->tx_flags = tx_flags;
6749 tx_buffer_info->dma = dma;
6751 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6752 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6753 tx_desc->read.olinfo_status = olinfo_status;
6758 frag = &skb_shinfo(skb)->frags[f];
6760 size = min_t(unsigned int, data_len, skb_frag_size(frag));
6762 size = skb_frag_size(frag);
6768 tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
6770 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
6771 if (dma_mapping_error(dev, dma))
6776 if (i == tx_ring->count) {
6777 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6782 tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
6785 if (i == tx_ring->count)
6788 tx_ring->next_to_use = i;
6790 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6791 gso_segs = skb_shinfo(skb)->gso_segs;
6793 /* adjust for FCoE Sequence Offload */
6794 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6795 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6796 skb_shinfo(skb)->gso_size);
6797 #endif /* IXGBE_FCOE */
6801 /* multiply data chunks by size of headers */
6802 tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
6803 tx_buffer_info->gso_segs = gso_segs;
6804 tx_buffer_info->skb = skb;
6806 /* set the timestamp */
6807 first->time_stamp = jiffies;
6810 * Force memory writes to complete before letting h/w
6811 * know there are new descriptors to fetch. (Only
6812 * applicable for weak-ordered memory model archs,
6817 /* set next_to_watch value indicating a packet is present */
6818 first->next_to_watch = tx_desc;
6820 /* notify HW of packet */
6821 writel(i, tx_ring->tail);
6825 dev_err(dev, "TX DMA map failed\n");
6827 /* clear dma mappings for failed tx_buffer_info map */
6829 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6830 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
6831 if (tx_buffer_info == first)
6838 dev_kfree_skb_any(skb);
6840 tx_ring->next_to_use = i;
6843 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6844 u32 tx_flags, __be16 protocol)
6846 struct ixgbe_q_vector *q_vector = ring->q_vector;
6847 union ixgbe_atr_hash_dword input = { .dword = 0 };
6848 union ixgbe_atr_hash_dword common = { .dword = 0 };
6850 unsigned char *network;
6852 struct ipv6hdr *ipv6;
6857 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6861 /* do nothing if sampling is disabled */
6862 if (!ring->atr_sample_rate)
6867 /* snag network header to get L4 type and address */
6868 hdr.network = skb_network_header(skb);
6870 /* Currently only IPv4/IPv6 with TCP is supported */
6871 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6872 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6873 (protocol != __constant_htons(ETH_P_IP) ||
6874 hdr.ipv4->protocol != IPPROTO_TCP))
6879 /* skip this packet since it is invalid or the socket is closing */
6883 /* sample on all syn packets or once every atr sample count */
6884 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6887 /* reset sample count */
6888 ring->atr_count = 0;
6890 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6893 * src and dst are inverted, think how the receiver sees them
6895 * The input is broken into two sections, a non-compressed section
6896 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6897 * is XORed together and stored in the compressed dword.
6899 input.formatted.vlan_id = vlan_id;
6902 * since src port and flex bytes occupy the same word XOR them together
6903 * and write the value to source port portion of compressed dword
6905 if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6906 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6908 common.port.src ^= th->dest ^ protocol;
6909 common.port.dst ^= th->source;
6911 if (protocol == __constant_htons(ETH_P_IP)) {
6912 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6913 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6915 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6916 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6917 hdr.ipv6->saddr.s6_addr32[1] ^
6918 hdr.ipv6->saddr.s6_addr32[2] ^
6919 hdr.ipv6->saddr.s6_addr32[3] ^
6920 hdr.ipv6->daddr.s6_addr32[0] ^
6921 hdr.ipv6->daddr.s6_addr32[1] ^
6922 hdr.ipv6->daddr.s6_addr32[2] ^
6923 hdr.ipv6->daddr.s6_addr32[3];
6926 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6927 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6928 input, common, ring->queue_index);
6931 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6933 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6934 /* Herbert's original patch had:
6935 * smp_mb__after_netif_stop_queue();
6936 * but since that doesn't exist yet, just open code it. */
6939 /* We need to check again in a case another CPU has just
6940 * made room available. */
6941 if (likely(ixgbe_desc_unused(tx_ring) < size))
6944 /* A reprieve! - use start_queue because it doesn't call schedule */
6945 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6946 ++tx_ring->tx_stats.restart_queue;
6950 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6952 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6954 return __ixgbe_maybe_stop_tx(tx_ring, size);
6957 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6959 struct ixgbe_adapter *adapter = netdev_priv(dev);
6960 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6963 __be16 protocol = vlan_get_protocol(skb);
6965 if (((protocol == htons(ETH_P_FCOE)) ||
6966 (protocol == htons(ETH_P_FIP))) &&
6967 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6968 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6969 txq += adapter->ring_feature[RING_F_FCOE].mask;
6974 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6975 while (unlikely(txq >= dev->real_num_tx_queues))
6976 txq -= dev->real_num_tx_queues;
6980 return skb_tx_hash(dev, skb);
6983 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6984 struct ixgbe_adapter *adapter,
6985 struct ixgbe_ring *tx_ring)
6987 struct ixgbe_tx_buffer *first;
6990 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6993 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6994 __be16 protocol = skb->protocol;
6998 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6999 * + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
7000 * + 2 desc gap to keep tail from touching head,
7001 * + 1 desc for context descriptor,
7002 * otherwise try next time
7004 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
7005 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7006 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7008 count += skb_shinfo(skb)->nr_frags;
7010 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7011 tx_ring->tx_stats.tx_busy++;
7012 return NETDEV_TX_BUSY;
7015 #ifdef CONFIG_PCI_IOV
7016 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7017 tx_flags |= IXGBE_TX_FLAGS_TXSW;
7020 /* if we have a HW VLAN tag being added default to the HW one */
7021 if (vlan_tx_tag_present(skb)) {
7022 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
7023 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7024 /* else if it is a SW VLAN check the next protocol and store the tag */
7025 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
7026 struct vlan_hdr *vhdr, _vhdr;
7027 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7031 protocol = vhdr->h_vlan_encapsulated_proto;
7032 tx_flags |= ntohs(vhdr->h_vlan_TCI) << IXGBE_TX_FLAGS_VLAN_SHIFT;
7033 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7036 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
7037 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
7038 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7039 (skb->priority != TC_PRIO_CONTROL))) {
7040 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
7041 tx_flags |= (skb->priority & 0x7) <<
7042 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
7043 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7044 struct vlan_ethhdr *vhdr;
7045 if (skb_header_cloned(skb) &&
7046 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
7048 vhdr = (struct vlan_ethhdr *)skb->data;
7049 vhdr->h_vlan_TCI = htons(tx_flags >>
7050 IXGBE_TX_FLAGS_VLAN_SHIFT);
7052 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7056 /* record the location of the first descriptor for this packet */
7057 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7060 /* setup tx offload for FCoE */
7061 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
7062 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
7063 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
7067 tx_flags |= IXGBE_TX_FLAGS_FSO |
7068 IXGBE_TX_FLAGS_FCOE;
7070 tx_flags |= IXGBE_TX_FLAGS_FCOE;
7075 #endif /* IXGBE_FCOE */
7076 /* setup IPv4/IPv6 offloads */
7077 if (protocol == __constant_htons(ETH_P_IP))
7078 tx_flags |= IXGBE_TX_FLAGS_IPV4;
7080 tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
7084 tx_flags |= IXGBE_TX_FLAGS_TSO;
7085 else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
7086 tx_flags |= IXGBE_TX_FLAGS_CSUM;
7088 /* add the ATR filter if ATR is on */
7089 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
7090 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
7094 #endif /* IXGBE_FCOE */
7095 ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
7097 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
7099 return NETDEV_TX_OK;
7102 dev_kfree_skb_any(skb);
7103 return NETDEV_TX_OK;
7106 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
7108 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7109 struct ixgbe_ring *tx_ring;
7111 tx_ring = adapter->tx_ring[skb->queue_mapping];
7112 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
7116 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7117 * @netdev: network interface device structure
7118 * @p: pointer to an address structure
7120 * Returns 0 on success, negative on failure
7122 static int ixgbe_set_mac(struct net_device *netdev, void *p)
7124 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7125 struct ixgbe_hw *hw = &adapter->hw;
7126 struct sockaddr *addr = p;
7128 if (!is_valid_ether_addr(addr->sa_data))
7129 return -EADDRNOTAVAIL;
7131 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
7132 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
7134 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
7141 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7143 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7144 struct ixgbe_hw *hw = &adapter->hw;
7148 if (prtad != hw->phy.mdio.prtad)
7150 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7156 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7157 u16 addr, u16 value)
7159 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7160 struct ixgbe_hw *hw = &adapter->hw;
7162 if (prtad != hw->phy.mdio.prtad)
7164 return hw->phy.ops.write_reg(hw, addr, devad, value);
7167 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7169 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7171 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7175 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
7177 * @netdev: network interface device structure
7179 * Returns non-zero on failure
7181 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7184 struct ixgbe_adapter *adapter = netdev_priv(dev);
7185 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7187 if (is_valid_ether_addr(mac->san_addr)) {
7189 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7196 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
7198 * @netdev: network interface device structure
7200 * Returns non-zero on failure
7202 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7205 struct ixgbe_adapter *adapter = netdev_priv(dev);
7206 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7208 if (is_valid_ether_addr(mac->san_addr)) {
7210 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7216 #ifdef CONFIG_NET_POLL_CONTROLLER
7218 * Polling 'interrupt' - used by things like netconsole to send skbs
7219 * without having to re-enable interrupts. It's not called while
7220 * the interrupt routine is executing.
7222 static void ixgbe_netpoll(struct net_device *netdev)
7224 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7227 /* if interface is down do nothing */
7228 if (test_bit(__IXGBE_DOWN, &adapter->state))
7231 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
7232 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7233 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7234 for (i = 0; i < num_q_vectors; i++) {
7235 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
7236 ixgbe_msix_clean_rings(0, q_vector);
7239 ixgbe_intr(adapter->pdev->irq, netdev);
7241 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
7245 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7246 struct rtnl_link_stats64 *stats)
7248 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7252 for (i = 0; i < adapter->num_rx_queues; i++) {
7253 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
7259 start = u64_stats_fetch_begin_bh(&ring->syncp);
7260 packets = ring->stats.packets;
7261 bytes = ring->stats.bytes;
7262 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7263 stats->rx_packets += packets;
7264 stats->rx_bytes += bytes;
7268 for (i = 0; i < adapter->num_tx_queues; i++) {
7269 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7275 start = u64_stats_fetch_begin_bh(&ring->syncp);
7276 packets = ring->stats.packets;
7277 bytes = ring->stats.bytes;
7278 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7279 stats->tx_packets += packets;
7280 stats->tx_bytes += bytes;
7284 /* following stats updated by ixgbe_watchdog_task() */
7285 stats->multicast = netdev->stats.multicast;
7286 stats->rx_errors = netdev->stats.rx_errors;
7287 stats->rx_length_errors = netdev->stats.rx_length_errors;
7288 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7289 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7293 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7294 * #adapter: pointer to ixgbe_adapter
7295 * @tc: number of traffic classes currently enabled
7297 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7298 * 802.1Q priority maps to a packet buffer that exists.
7300 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7302 struct ixgbe_hw *hw = &adapter->hw;
7306 /* 82598 have a static priority to TC mapping that can not
7307 * be changed so no validation is needed.
7309 if (hw->mac.type == ixgbe_mac_82598EB)
7312 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7315 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7316 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7318 /* If up2tc is out of bounds default to zero */
7320 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7324 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7330 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7333 * @netdev: net device to configure
7334 * @tc: number of traffic classes to enable
7336 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7338 struct ixgbe_adapter *adapter = netdev_priv(dev);
7339 struct ixgbe_hw *hw = &adapter->hw;
7341 /* Multiple traffic classes requires multiple queues */
7342 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
7343 e_err(drv, "Enable failed, needs MSI-X\n");
7347 /* Hardware supports up to 8 traffic classes */
7348 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
7349 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7352 /* Hardware has to reinitialize queues and interrupts to
7353 * match packet buffer alignment. Unfortunately, the
7354 * hardware is not flexible enough to do this dynamically.
7356 if (netif_running(dev))
7358 ixgbe_clear_interrupt_scheme(adapter);
7361 netdev_set_num_tc(dev, tc);
7362 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
7364 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
7365 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7367 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7368 adapter->hw.fc.requested_mode = ixgbe_fc_none;
7370 netdev_reset_tc(dev);
7372 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
7374 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
7375 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7377 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7378 adapter->dcb_cfg.pfc_mode_enable = false;
7381 ixgbe_init_interrupt_scheme(adapter);
7382 ixgbe_validate_rtr(adapter, tc);
7383 if (netif_running(dev))
7389 void ixgbe_do_reset(struct net_device *netdev)
7391 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7393 if (netif_running(netdev))
7394 ixgbe_reinit_locked(adapter);
7396 ixgbe_reset(adapter);
7399 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
7400 netdev_features_t data)
7402 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7405 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7406 data &= ~NETIF_F_HW_VLAN_RX;
7409 /* return error if RXHASH is being enabled when RSS is not supported */
7410 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7411 data &= ~NETIF_F_RXHASH;
7413 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7414 if (!(data & NETIF_F_RXCSUM))
7415 data &= ~NETIF_F_LRO;
7417 /* Turn off LRO if not RSC capable or invalid ITR settings */
7418 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
7419 data &= ~NETIF_F_LRO;
7420 } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
7421 (adapter->rx_itr_setting != 1 &&
7422 adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
7423 data &= ~NETIF_F_LRO;
7424 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
7430 static int ixgbe_set_features(struct net_device *netdev,
7431 netdev_features_t data)
7433 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7434 bool need_reset = false;
7436 /* Make sure RSC matches LRO, reset if change */
7437 if (!!(data & NETIF_F_LRO) !=
7438 !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7439 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
7440 switch (adapter->hw.mac.type) {
7441 case ixgbe_mac_X540:
7442 case ixgbe_mac_82599EB:
7451 * Check if Flow Director n-tuple support was enabled or disabled. If
7452 * the state changed, we need to reset.
7454 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
7455 /* turn off ATR, enable perfect filters and reset */
7456 if (data & NETIF_F_NTUPLE) {
7457 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7458 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7461 } else if (!(data & NETIF_F_NTUPLE)) {
7462 /* turn off Flow Director, set ATR and reset */
7463 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7464 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
7465 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7466 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7471 ixgbe_do_reset(netdev);
7477 static const struct net_device_ops ixgbe_netdev_ops = {
7478 .ndo_open = ixgbe_open,
7479 .ndo_stop = ixgbe_close,
7480 .ndo_start_xmit = ixgbe_xmit_frame,
7481 .ndo_select_queue = ixgbe_select_queue,
7482 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7483 .ndo_validate_addr = eth_validate_addr,
7484 .ndo_set_mac_address = ixgbe_set_mac,
7485 .ndo_change_mtu = ixgbe_change_mtu,
7486 .ndo_tx_timeout = ixgbe_tx_timeout,
7487 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7488 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7489 .ndo_do_ioctl = ixgbe_ioctl,
7490 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7491 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7492 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7493 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7494 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7495 .ndo_get_stats64 = ixgbe_get_stats64,
7496 .ndo_setup_tc = ixgbe_setup_tc,
7497 #ifdef CONFIG_NET_POLL_CONTROLLER
7498 .ndo_poll_controller = ixgbe_netpoll,
7501 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7502 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7503 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7504 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7505 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7506 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7507 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
7508 #endif /* IXGBE_FCOE */
7509 .ndo_set_features = ixgbe_set_features,
7510 .ndo_fix_features = ixgbe_fix_features,
7513 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7514 const struct ixgbe_info *ii)
7516 #ifdef CONFIG_PCI_IOV
7517 struct ixgbe_hw *hw = &adapter->hw;
7519 if (hw->mac.type == ixgbe_mac_82598EB)
7522 /* The 82599 supports up to 64 VFs per physical function
7523 * but this implementation limits allocation to 63 so that
7524 * basic networking resources are still available to the
7527 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7528 ixgbe_enable_sriov(adapter, ii);
7529 #endif /* CONFIG_PCI_IOV */
7533 * ixgbe_probe - Device Initialization Routine
7534 * @pdev: PCI device information struct
7535 * @ent: entry in ixgbe_pci_tbl
7537 * Returns 0 on success, negative on failure
7539 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7540 * The OS initialization, configuring of the adapter private structure,
7541 * and a hardware reset occur.
7543 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7544 const struct pci_device_id *ent)
7546 struct net_device *netdev;
7547 struct ixgbe_adapter *adapter = NULL;
7548 struct ixgbe_hw *hw;
7549 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7550 static int cards_found;
7551 int i, err, pci_using_dac;
7552 u8 part_str[IXGBE_PBANUM_LENGTH];
7553 unsigned int indices = num_possible_cpus();
7560 /* Catch broken hardware that put the wrong VF device ID in
7561 * the PCIe SR-IOV capability.
7563 if (pdev->is_virtfn) {
7564 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7565 pci_name(pdev), pdev->vendor, pdev->device);
7569 err = pci_enable_device_mem(pdev);
7573 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7574 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7577 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7579 err = dma_set_coherent_mask(&pdev->dev,
7583 "No usable DMA configuration, aborting\n");
7590 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7591 IORESOURCE_MEM), ixgbe_driver_name);
7594 "pci_request_selected_regions failed 0x%x\n", err);
7598 pci_enable_pcie_error_reporting(pdev);
7600 pci_set_master(pdev);
7601 pci_save_state(pdev);
7603 #ifdef CONFIG_IXGBE_DCB
7604 indices *= MAX_TRAFFIC_CLASS;
7607 if (ii->mac == ixgbe_mac_82598EB)
7608 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7610 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7613 indices += min_t(unsigned int, num_possible_cpus(),
7614 IXGBE_MAX_FCOE_INDICES);
7616 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7619 goto err_alloc_etherdev;
7622 SET_NETDEV_DEV(netdev, &pdev->dev);
7624 adapter = netdev_priv(netdev);
7625 pci_set_drvdata(pdev, adapter);
7627 adapter->netdev = netdev;
7628 adapter->pdev = pdev;
7631 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7633 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7634 pci_resource_len(pdev, 0));
7640 for (i = 1; i <= 5; i++) {
7641 if (pci_resource_len(pdev, i) == 0)
7645 netdev->netdev_ops = &ixgbe_netdev_ops;
7646 ixgbe_set_ethtool_ops(netdev);
7647 netdev->watchdog_timeo = 5 * HZ;
7648 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7650 adapter->bd_number = cards_found;
7653 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7654 hw->mac.type = ii->mac;
7657 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7658 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7659 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7660 if (!(eec & (1 << 8)))
7661 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7664 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7665 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7666 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7667 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7668 hw->phy.mdio.mmds = 0;
7669 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7670 hw->phy.mdio.dev = netdev;
7671 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7672 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7674 ii->get_invariants(hw);
7676 /* setup the private structure */
7677 err = ixgbe_sw_init(adapter);
7681 /* Make it possible the adapter to be woken up via WOL */
7682 switch (adapter->hw.mac.type) {
7683 case ixgbe_mac_82599EB:
7684 case ixgbe_mac_X540:
7685 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7692 * If there is a fan on this device and it has failed log the
7695 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7696 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7697 if (esdp & IXGBE_ESDP_SDP1)
7698 e_crit(probe, "Fan has stopped, replace the adapter\n");
7701 if (allow_unsupported_sfp)
7702 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7704 /* reset_hw fills in the perm_addr as well */
7705 hw->phy.reset_if_overtemp = true;
7706 err = hw->mac.ops.reset_hw(hw);
7707 hw->phy.reset_if_overtemp = false;
7708 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7709 hw->mac.type == ixgbe_mac_82598EB) {
7711 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7712 e_dev_err("failed to load because an unsupported SFP+ "
7713 "module type was detected.\n");
7714 e_dev_err("Reload the driver after installing a supported "
7718 e_dev_err("HW Init failed: %d\n", err);
7722 ixgbe_probe_vf(adapter, ii);
7724 netdev->features = NETIF_F_SG |
7727 NETIF_F_HW_VLAN_TX |
7728 NETIF_F_HW_VLAN_RX |
7729 NETIF_F_HW_VLAN_FILTER |
7735 netdev->hw_features = netdev->features;
7737 switch (adapter->hw.mac.type) {
7738 case ixgbe_mac_82599EB:
7739 case ixgbe_mac_X540:
7740 netdev->features |= NETIF_F_SCTP_CSUM;
7741 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7748 netdev->vlan_features |= NETIF_F_TSO;
7749 netdev->vlan_features |= NETIF_F_TSO6;
7750 netdev->vlan_features |= NETIF_F_IP_CSUM;
7751 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7752 netdev->vlan_features |= NETIF_F_SG;
7754 netdev->priv_flags |= IFF_UNICAST_FLT;
7756 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7757 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7758 IXGBE_FLAG_DCB_ENABLED);
7760 #ifdef CONFIG_IXGBE_DCB
7761 netdev->dcbnl_ops = &dcbnl_ops;
7765 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7766 if (hw->mac.ops.get_device_caps) {
7767 hw->mac.ops.get_device_caps(hw, &device_caps);
7768 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7769 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7772 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7773 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7774 netdev->vlan_features |= NETIF_F_FSO;
7775 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7777 #endif /* IXGBE_FCOE */
7778 if (pci_using_dac) {
7779 netdev->features |= NETIF_F_HIGHDMA;
7780 netdev->vlan_features |= NETIF_F_HIGHDMA;
7783 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7784 netdev->hw_features |= NETIF_F_LRO;
7785 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7786 netdev->features |= NETIF_F_LRO;
7788 /* make sure the EEPROM is good */
7789 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7790 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7795 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7796 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7798 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7799 e_dev_err("invalid MAC address\n");
7804 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7805 (unsigned long) adapter);
7807 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7808 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7810 err = ixgbe_init_interrupt_scheme(adapter);
7814 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7815 netdev->hw_features &= ~NETIF_F_RXHASH;
7816 netdev->features &= ~NETIF_F_RXHASH;
7819 /* WOL not supported for all but the following */
7821 switch (pdev->device) {
7822 case IXGBE_DEV_ID_82599_SFP:
7823 /* Only these subdevice supports WOL */
7824 switch (pdev->subsystem_device) {
7825 case IXGBE_SUBDEV_ID_82599_560FLR:
7826 /* only support first port */
7827 if (hw->bus.func != 0)
7829 case IXGBE_SUBDEV_ID_82599_SFP:
7830 adapter->wol = IXGBE_WUFC_MAG;
7834 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7835 /* All except this subdevice support WOL */
7836 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7837 adapter->wol = IXGBE_WUFC_MAG;
7839 case IXGBE_DEV_ID_82599_KX4:
7840 adapter->wol = IXGBE_WUFC_MAG;
7842 case IXGBE_DEV_ID_X540T:
7843 /* Check eeprom to see if it is enabled */
7844 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7845 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7847 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7848 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7849 (hw->bus.func == 0)))
7850 adapter->wol = IXGBE_WUFC_MAG;
7853 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7855 /* save off EEPROM version number */
7856 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7857 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7859 /* pick up the PCI bus settings for reporting later */
7860 hw->mac.ops.get_bus_info(hw);
7862 /* print bus type/speed/width info */
7863 e_dev_info("(PCI Express:%s:%s) %pM\n",
7864 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7865 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7867 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7868 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7869 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7873 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7875 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7876 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7877 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7878 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7881 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7882 hw->mac.type, hw->phy.type, part_str);
7884 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7885 e_dev_warn("PCI-Express bandwidth available for this card is "
7886 "not sufficient for optimal performance.\n");
7887 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7891 /* reset the hardware with the new settings */
7892 err = hw->mac.ops.start_hw(hw);
7894 if (err == IXGBE_ERR_EEPROM_VERSION) {
7895 /* We are running on a pre-production device, log a warning */
7896 e_dev_warn("This device is a pre-production adapter/LOM. "
7897 "Please be aware there may be issues associated "
7898 "with your hardware. If you are experiencing "
7899 "problems please contact your Intel or hardware "
7900 "representative who provided you with this "
7903 strcpy(netdev->name, "eth%d");
7904 err = register_netdev(netdev);
7908 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7909 if (hw->mac.ops.disable_tx_laser &&
7910 ((hw->phy.multispeed_fiber) ||
7911 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7912 (hw->mac.type == ixgbe_mac_82599EB))))
7913 hw->mac.ops.disable_tx_laser(hw);
7915 /* carrier off reporting is important to ethtool even BEFORE open */
7916 netif_carrier_off(netdev);
7918 #ifdef CONFIG_IXGBE_DCA
7919 if (dca_add_requester(&pdev->dev) == 0) {
7920 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7921 ixgbe_setup_dca(adapter);
7924 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7925 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7926 for (i = 0; i < adapter->num_vfs; i++)
7927 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7930 /* firmware requires driver version to be 0xFFFFFFFF
7931 * since os does not support feature
7933 if (hw->mac.ops.set_fw_drv_ver)
7934 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7937 /* add san mac addr to netdev */
7938 ixgbe_add_sanmac_netdev(netdev);
7940 e_dev_info("%s\n", ixgbe_default_device_descr);
7945 ixgbe_release_hw_control(adapter);
7946 ixgbe_clear_interrupt_scheme(adapter);
7949 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7950 ixgbe_disable_sriov(adapter);
7951 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7952 iounmap(hw->hw_addr);
7954 free_netdev(netdev);
7956 pci_release_selected_regions(pdev,
7957 pci_select_bars(pdev, IORESOURCE_MEM));
7960 pci_disable_device(pdev);
7965 * ixgbe_remove - Device Removal Routine
7966 * @pdev: PCI device information struct
7968 * ixgbe_remove is called by the PCI subsystem to alert the driver
7969 * that it should release a PCI device. The could be caused by a
7970 * Hot-Plug event, or because the driver is going to be removed from
7973 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7975 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7976 struct net_device *netdev = adapter->netdev;
7978 set_bit(__IXGBE_DOWN, &adapter->state);
7979 cancel_work_sync(&adapter->service_task);
7981 #ifdef CONFIG_IXGBE_DCA
7982 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7983 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7984 dca_remove_requester(&pdev->dev);
7985 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7990 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7991 ixgbe_cleanup_fcoe(adapter);
7993 #endif /* IXGBE_FCOE */
7995 /* remove the added san mac */
7996 ixgbe_del_sanmac_netdev(netdev);
7998 if (netdev->reg_state == NETREG_REGISTERED)
7999 unregister_netdev(netdev);
8001 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
8002 if (!(ixgbe_check_vf_assignment(adapter)))
8003 ixgbe_disable_sriov(adapter);
8005 e_dev_warn("Unloading driver while VFs are assigned "
8006 "- VFs will not be deallocated\n");
8009 ixgbe_clear_interrupt_scheme(adapter);
8011 ixgbe_release_hw_control(adapter);
8013 iounmap(adapter->hw.hw_addr);
8014 pci_release_selected_regions(pdev, pci_select_bars(pdev,
8017 e_dev_info("complete\n");
8019 free_netdev(netdev);
8021 pci_disable_pcie_error_reporting(pdev);
8023 pci_disable_device(pdev);
8027 * ixgbe_io_error_detected - called when PCI error is detected
8028 * @pdev: Pointer to PCI device
8029 * @state: The current pci connection state
8031 * This function is called after a PCI bus error affecting
8032 * this device has been detected.
8034 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
8035 pci_channel_state_t state)
8037 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8038 struct net_device *netdev = adapter->netdev;
8040 #ifdef CONFIG_PCI_IOV
8041 struct pci_dev *bdev, *vfdev;
8042 u32 dw0, dw1, dw2, dw3;
8044 u16 req_id, pf_func;
8046 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
8047 adapter->num_vfs == 0)
8048 goto skip_bad_vf_detection;
8050 bdev = pdev->bus->self;
8051 while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
8052 bdev = bdev->bus->self;
8055 goto skip_bad_vf_detection;
8057 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
8059 goto skip_bad_vf_detection;
8061 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
8062 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
8063 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
8064 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
8067 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
8068 if (!(req_id & 0x0080))
8069 goto skip_bad_vf_detection;
8071 pf_func = req_id & 0x01;
8072 if ((pf_func & 1) == (pdev->devfn & 1)) {
8073 unsigned int device_id;
8075 vf = (req_id & 0x7F) >> 1;
8076 e_dev_err("VF %d has caused a PCIe error\n", vf);
8077 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
8078 "%8.8x\tdw3: %8.8x\n",
8079 dw0, dw1, dw2, dw3);
8080 switch (adapter->hw.mac.type) {
8081 case ixgbe_mac_82599EB:
8082 device_id = IXGBE_82599_VF_DEVICE_ID;
8084 case ixgbe_mac_X540:
8085 device_id = IXGBE_X540_VF_DEVICE_ID;
8092 /* Find the pci device of the offending VF */
8093 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL);
8095 if (vfdev->devfn == (req_id & 0xFF))
8097 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID,
8101 * There's a slim chance the VF could have been hot plugged,
8102 * so if it is no longer present we don't need to issue the
8103 * VFLR. Just clean up the AER in that case.
8106 e_dev_err("Issuing VFLR to VF %d\n", vf);
8107 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
8110 pci_cleanup_aer_uncorrect_error_status(pdev);
8114 * Even though the error may have occurred on the other port
8115 * we still need to increment the vf error reference count for
8116 * both ports because the I/O resume function will be called
8119 adapter->vferr_refcount++;
8121 return PCI_ERS_RESULT_RECOVERED;
8123 skip_bad_vf_detection:
8124 #endif /* CONFIG_PCI_IOV */
8125 netif_device_detach(netdev);
8127 if (state == pci_channel_io_perm_failure)
8128 return PCI_ERS_RESULT_DISCONNECT;
8130 if (netif_running(netdev))
8131 ixgbe_down(adapter);
8132 pci_disable_device(pdev);
8134 /* Request a slot reset. */
8135 return PCI_ERS_RESULT_NEED_RESET;
8139 * ixgbe_io_slot_reset - called after the pci bus has been reset.
8140 * @pdev: Pointer to PCI device
8142 * Restart the card from scratch, as if from a cold-boot.
8144 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
8146 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8147 pci_ers_result_t result;
8150 if (pci_enable_device_mem(pdev)) {
8151 e_err(probe, "Cannot re-enable PCI device after reset.\n");
8152 result = PCI_ERS_RESULT_DISCONNECT;
8154 pci_set_master(pdev);
8155 pci_restore_state(pdev);
8156 pci_save_state(pdev);
8158 pci_wake_from_d3(pdev, false);
8160 ixgbe_reset(adapter);
8161 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
8162 result = PCI_ERS_RESULT_RECOVERED;
8165 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8167 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
8168 "failed 0x%0x\n", err);
8169 /* non-fatal, continue */
8176 * ixgbe_io_resume - called when traffic can start flowing again.
8177 * @pdev: Pointer to PCI device
8179 * This callback is called when the error recovery driver tells us that
8180 * its OK to resume normal operation.
8182 static void ixgbe_io_resume(struct pci_dev *pdev)
8184 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8185 struct net_device *netdev = adapter->netdev;
8187 #ifdef CONFIG_PCI_IOV
8188 if (adapter->vferr_refcount) {
8189 e_info(drv, "Resuming after VF err\n");
8190 adapter->vferr_refcount--;
8195 if (netif_running(netdev))
8198 netif_device_attach(netdev);
8201 static struct pci_error_handlers ixgbe_err_handler = {
8202 .error_detected = ixgbe_io_error_detected,
8203 .slot_reset = ixgbe_io_slot_reset,
8204 .resume = ixgbe_io_resume,
8207 static struct pci_driver ixgbe_driver = {
8208 .name = ixgbe_driver_name,
8209 .id_table = ixgbe_pci_tbl,
8210 .probe = ixgbe_probe,
8211 .remove = __devexit_p(ixgbe_remove),
8213 .suspend = ixgbe_suspend,
8214 .resume = ixgbe_resume,
8216 .shutdown = ixgbe_shutdown,
8217 .err_handler = &ixgbe_err_handler
8221 * ixgbe_init_module - Driver Registration Routine
8223 * ixgbe_init_module is the first routine called when the driver is
8224 * loaded. All it does is register with the PCI subsystem.
8226 static int __init ixgbe_init_module(void)
8229 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
8230 pr_info("%s\n", ixgbe_copyright);
8232 #ifdef CONFIG_IXGBE_DCA
8233 dca_register_notify(&dca_notifier);
8236 ret = pci_register_driver(&ixgbe_driver);
8240 module_init(ixgbe_init_module);
8243 * ixgbe_exit_module - Driver Exit Cleanup Routine
8245 * ixgbe_exit_module is called just before the driver is removed
8248 static void __exit ixgbe_exit_module(void)
8250 #ifdef CONFIG_IXGBE_DCA
8251 dca_unregister_notify(&dca_notifier);
8253 pci_unregister_driver(&ixgbe_driver);
8254 rcu_barrier(); /* Wait for completion of call_rcu()'s */
8257 #ifdef CONFIG_IXGBE_DCA
8258 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
8263 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
8264 __ixgbe_notify_dca);
8266 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8269 #endif /* CONFIG_IXGBE_DCA */
8271 module_exit(ixgbe_exit_module);