1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
33 #include "ixgbe_phy.h"
35 #define IXGBE_82598_MAX_TX_QUEUES 32
36 #define IXGBE_82598_MAX_RX_QUEUES 64
37 #define IXGBE_82598_RAR_ENTRIES 16
38 #define IXGBE_82598_MC_TBL_SIZE 128
39 #define IXGBE_82598_VFT_TBL_SIZE 128
40 #define IXGBE_82598_RX_PB_SIZE 512
42 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
43 ixgbe_link_speed speed,
45 bool autoneg_wait_to_complete);
46 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
50 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
51 * @hw: pointer to the HW structure
53 * The defaults for 82598 should be in the range of 50us to 50ms,
54 * however the hardware default for these parts is 500us to 1ms which is less
55 * than the 10ms recommended by the pci-e spec. To address this we need to
56 * increase the value to either 10ms to 250ms for capability version 1 config,
57 * or 16ms to 55ms for version 2.
59 static void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)
61 struct ixgbe_adapter *adapter = hw->back;
62 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);
65 /* only take action if timeout value is defaulted to 0 */
66 if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK)
70 * if capababilities version is type 1 we can write the
71 * timeout of 10ms to 250ms through the GCR register
73 if (!(gcr & IXGBE_GCR_CAP_VER2)) {
74 gcr |= IXGBE_GCR_CMPL_TMOUT_10ms;
79 * for version 2 capabilities we need to write the config space
80 * directly in order to set the completion timeout value for
83 pci_read_config_word(adapter->pdev,
84 IXGBE_PCI_DEVICE_CONTROL2, &pcie_devctl2);
85 pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms;
86 pci_write_config_word(adapter->pdev,
87 IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2);
89 /* disable completion timeout resend */
90 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND;
91 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);
95 * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
96 * @hw: pointer to hardware structure
98 * Read PCIe configuration space, and get the MSI-X vector count from
99 * the capabilities table.
101 static u16 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
103 struct ixgbe_adapter *adapter = hw->back;
105 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82598_CAPS,
107 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
109 /* MSI-X count is zero-based in HW, so increment to give proper value */
117 static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
119 struct ixgbe_mac_info *mac = &hw->mac;
121 /* Call PHY identify routine to get the phy type */
122 ixgbe_identify_phy_generic(hw);
124 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
125 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
126 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
127 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
128 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
129 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw);
135 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
136 * @hw: pointer to hardware structure
138 * Initialize any function pointers that were not able to be
139 * set during get_invariants because the PHY/SFP type was
140 * not known. Perform the SFP init if necessary.
143 static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
145 struct ixgbe_mac_info *mac = &hw->mac;
146 struct ixgbe_phy_info *phy = &hw->phy;
148 u16 list_offset, data_offset;
150 /* Identify the PHY */
151 phy->ops.identify(hw);
153 /* Overwrite the link function pointers if copper PHY */
154 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
155 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
156 mac->ops.get_link_capabilities =
157 &ixgbe_get_copper_link_capabilities_generic;
160 switch (hw->phy.type) {
162 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
163 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
164 phy->ops.get_firmware_version =
165 &ixgbe_get_phy_firmware_version_tnx;
168 phy->ops.reset = &ixgbe_reset_phy_nl;
170 /* Call SFP+ identify routine to get the SFP+ module type */
171 ret_val = phy->ops.identify_sfp(hw);
174 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
175 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
179 /* Check to see if SFP+ module is supported */
180 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
184 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
197 * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx
198 * @hw: pointer to hardware structure
200 * Starts the hardware using the generic start_hw function.
201 * Disables relaxed ordering Then set pcie completion timeout
204 static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
210 ret_val = ixgbe_start_hw_generic(hw);
212 /* Disable relaxed ordering */
213 for (i = 0; ((i < hw->mac.max_tx_queues) &&
214 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
215 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
216 regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
217 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
220 for (i = 0; ((i < hw->mac.max_rx_queues) &&
221 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
222 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
223 regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
224 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
225 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
228 hw->mac.rx_pb_size = IXGBE_82598_RX_PB_SIZE;
230 /* set the completion timeout for interface */
232 ixgbe_set_pcie_completion_timeout(hw);
238 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
239 * @hw: pointer to hardware structure
240 * @speed: pointer to link speed
241 * @autoneg: boolean auto-negotiation value
243 * Determines the link capabilities by reading the AUTOC register.
245 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
246 ixgbe_link_speed *speed,
253 * Determine link capabilities based on the stored value of AUTOC,
254 * which represents EEPROM defaults. If AUTOC value has not been
255 * stored, use the current register value.
257 if (hw->mac.orig_link_settings_stored)
258 autoc = hw->mac.orig_autoc;
260 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
262 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
263 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
264 *speed = IXGBE_LINK_SPEED_1GB_FULL;
268 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
269 *speed = IXGBE_LINK_SPEED_10GB_FULL;
273 case IXGBE_AUTOC_LMS_1G_AN:
274 *speed = IXGBE_LINK_SPEED_1GB_FULL;
278 case IXGBE_AUTOC_LMS_KX4_AN:
279 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
280 *speed = IXGBE_LINK_SPEED_UNKNOWN;
281 if (autoc & IXGBE_AUTOC_KX4_SUPP)
282 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
283 if (autoc & IXGBE_AUTOC_KX_SUPP)
284 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
289 status = IXGBE_ERR_LINK_SETUP;
297 * ixgbe_get_media_type_82598 - Determines media type
298 * @hw: pointer to hardware structure
300 * Returns the media type (fiber, copper, backplane)
302 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
304 enum ixgbe_media_type media_type;
306 /* Detect if there is a copper PHY attached. */
307 switch (hw->phy.type) {
308 case ixgbe_phy_cu_unknown:
311 media_type = ixgbe_media_type_copper;
317 /* Media type for I82598 is based on device ID */
318 switch (hw->device_id) {
319 case IXGBE_DEV_ID_82598:
320 case IXGBE_DEV_ID_82598_BX:
321 /* Default device ID is mezzanine card KX/KX4 */
322 media_type = ixgbe_media_type_backplane;
324 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
325 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
326 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
327 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
328 case IXGBE_DEV_ID_82598EB_XF_LR:
329 case IXGBE_DEV_ID_82598EB_SFP_LOM:
330 media_type = ixgbe_media_type_fiber;
332 case IXGBE_DEV_ID_82598EB_CX4:
333 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
334 media_type = ixgbe_media_type_cx4;
336 case IXGBE_DEV_ID_82598AT:
337 case IXGBE_DEV_ID_82598AT2:
338 media_type = ixgbe_media_type_copper;
341 media_type = ixgbe_media_type_unknown;
349 * ixgbe_fc_enable_82598 - Enable flow control
350 * @hw: pointer to hardware structure
351 * @packetbuf_num: packet buffer number (0-7)
353 * Enable flow control according to the current settings.
355 static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
365 if (hw->fc.requested_mode == ixgbe_fc_pfc)
368 #endif /* CONFIG_DCB */
370 * On 82598 having Rx FC on causes resets while doing 1G
371 * so if it's on turn it off once we know link_speed. For
372 * more details see 82598 Specification update.
374 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
375 if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) {
376 switch (hw->fc.requested_mode) {
378 hw->fc.requested_mode = ixgbe_fc_tx_pause;
380 case ixgbe_fc_rx_pause:
381 hw->fc.requested_mode = ixgbe_fc_none;
389 /* Negotiate the fc mode to use */
390 ret_val = ixgbe_fc_autoneg(hw);
391 if (ret_val == IXGBE_ERR_FLOW_CONTROL)
394 /* Disable any previous flow control settings */
395 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
396 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
398 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
399 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
402 * The possible values of fc.current_mode are:
403 * 0: Flow control is completely disabled
404 * 1: Rx flow control is enabled (we can receive pause frames,
405 * but not send pause frames).
406 * 2: Tx flow control is enabled (we can send pause frames but
407 * we do not support receiving pause frames).
408 * 3: Both Rx and Tx flow control (symmetric) are enabled.
410 * 4: Priority Flow Control is enabled.
414 switch (hw->fc.current_mode) {
417 * Flow control is disabled by software override or autoneg.
418 * The code below will actually disable it in the HW.
421 case ixgbe_fc_rx_pause:
423 * Rx Flow control is enabled and Tx Flow control is
424 * disabled by software override. Since there really
425 * isn't a way to advertise that we are capable of RX
426 * Pause ONLY, we will advertise that we support both
427 * symmetric and asymmetric Rx PAUSE. Later, we will
428 * disable the adapter's ability to send PAUSE frames.
430 fctrl_reg |= IXGBE_FCTRL_RFCE;
432 case ixgbe_fc_tx_pause:
434 * Tx Flow control is enabled, and Rx Flow control is
435 * disabled by software override.
437 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
440 /* Flow control (both Rx and Tx) is enabled by SW override. */
441 fctrl_reg |= IXGBE_FCTRL_RFCE;
442 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
448 #endif /* CONFIG_DCB */
450 hw_dbg(hw, "Flow control param set incorrectly\n");
451 ret_val = IXGBE_ERR_CONFIG;
456 /* Set 802.3x based flow control settings. */
457 fctrl_reg |= IXGBE_FCTRL_DPF;
458 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
459 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
461 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
462 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
463 reg = hw->fc.low_water << 6;
465 reg |= IXGBE_FCRTL_XONE;
467 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), reg);
469 reg = hw->fc.high_water[packetbuf_num] << 6;
470 reg |= IXGBE_FCRTH_FCEN;
472 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), reg);
475 /* Configure pause time (2 TCs per register) */
476 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
477 if ((packetbuf_num & 1) == 0)
478 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
480 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
481 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
483 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
490 * ixgbe_start_mac_link_82598 - Configures MAC link settings
491 * @hw: pointer to hardware structure
493 * Configures link settings based on values in the ixgbe_hw struct.
494 * Restarts the link. Performs autonegotiation if needed.
496 static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
497 bool autoneg_wait_to_complete)
505 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
506 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
507 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
509 /* Only poll for autoneg to complete if specified to do so */
510 if (autoneg_wait_to_complete) {
511 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
512 IXGBE_AUTOC_LMS_KX4_AN ||
513 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
514 IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
515 links_reg = 0; /* Just in case Autoneg time = 0 */
516 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
517 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
518 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
522 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
523 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
524 hw_dbg(hw, "Autonegotiation did not complete.\n");
529 /* Add delay to filter out noises during initial link setup */
536 * ixgbe_validate_link_ready - Function looks for phy link
537 * @hw: pointer to hardware structure
539 * Function indicates success when phy link is available. If phy is not ready
540 * within 5 seconds of MAC indicating link, the function returns error.
542 static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw)
547 if (hw->device_id != IXGBE_DEV_ID_82598AT2)
551 timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) {
552 hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, &an_reg);
554 if ((an_reg & MDIO_AN_STAT1_COMPLETE) &&
555 (an_reg & MDIO_STAT1_LSTATUS))
561 if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) {
562 hw_dbg(hw, "Link was indicated but link is down\n");
563 return IXGBE_ERR_LINK_SETUP;
570 * ixgbe_check_mac_link_82598 - Get link/speed status
571 * @hw: pointer to hardware structure
572 * @speed: pointer to link speed
573 * @link_up: true is link is up, false otherwise
574 * @link_up_wait_to_complete: bool used to wait for link up or not
576 * Reads the links register to determine if link is up and the current speed
578 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
579 ixgbe_link_speed *speed, bool *link_up,
580 bool link_up_wait_to_complete)
584 u16 link_reg, adapt_comp_reg;
587 * SERDES PHY requires us to read link status from register 0xC79F.
588 * Bit 0 set indicates link is up/ready; clear indicates link down.
589 * 0xC00C is read to check that the XAUI lanes are active. Bit 0
590 * clear indicates active; set indicates inactive.
592 if (hw->phy.type == ixgbe_phy_nl) {
593 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
594 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
595 hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD,
597 if (link_up_wait_to_complete) {
598 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
599 if ((link_reg & 1) &&
600 ((adapt_comp_reg & 1) == 0)) {
607 hw->phy.ops.read_reg(hw, 0xC79F,
610 hw->phy.ops.read_reg(hw, 0xC00C,
615 if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
621 if (*link_up == false)
625 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
626 if (link_up_wait_to_complete) {
627 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
628 if (links_reg & IXGBE_LINKS_UP) {
635 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
638 if (links_reg & IXGBE_LINKS_UP)
644 if (links_reg & IXGBE_LINKS_SPEED)
645 *speed = IXGBE_LINK_SPEED_10GB_FULL;
647 *speed = IXGBE_LINK_SPEED_1GB_FULL;
649 if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == true) &&
650 (ixgbe_validate_link_ready(hw) != 0))
653 /* if link is down, zero out the current_mode */
654 if (*link_up == false) {
655 hw->fc.current_mode = ixgbe_fc_none;
656 hw->fc.fc_was_autonegged = false;
663 * ixgbe_setup_mac_link_82598 - Set MAC link speed
664 * @hw: pointer to hardware structure
665 * @speed: new link speed
666 * @autoneg: true if auto-negotiation enabled
667 * @autoneg_wait_to_complete: true when waiting for completion is needed
669 * Set the link speed in the AUTOC register and restarts link.
671 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
672 ixgbe_link_speed speed, bool autoneg,
673 bool autoneg_wait_to_complete)
676 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
677 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
678 u32 autoc = curr_autoc;
679 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
681 /* Check to see if speed passed in is supported. */
682 ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg);
683 speed &= link_capabilities;
685 if (speed == IXGBE_LINK_SPEED_UNKNOWN)
686 status = IXGBE_ERR_LINK_SETUP;
688 /* Set KX4/KX support according to speed requested */
689 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
690 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
691 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
692 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
693 autoc |= IXGBE_AUTOC_KX4_SUPP;
694 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
695 autoc |= IXGBE_AUTOC_KX_SUPP;
696 if (autoc != curr_autoc)
697 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
702 * Setup and restart the link based on the new values in
703 * ixgbe_hw This will write the AUTOC register based on the new
706 status = ixgbe_start_mac_link_82598(hw,
707 autoneg_wait_to_complete);
715 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
716 * @hw: pointer to hardware structure
717 * @speed: new link speed
718 * @autoneg: true if autonegotiation enabled
719 * @autoneg_wait_to_complete: true if waiting is needed to complete
721 * Sets the link speed in the AUTOC register in the MAC and restarts link.
723 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
724 ixgbe_link_speed speed,
726 bool autoneg_wait_to_complete)
730 /* Setup the PHY according to input speed */
731 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
732 autoneg_wait_to_complete);
734 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
740 * ixgbe_reset_hw_82598 - Performs hardware reset
741 * @hw: pointer to hardware structure
743 * Resets the hardware by resetting the transmit and receive units, masks and
744 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
747 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
757 /* Call adapter stop to disable tx/rx and clear interrupts */
758 status = hw->mac.ops.stop_adapter(hw);
763 * Power up the Atlas Tx lanes if they are currently powered down.
764 * Atlas Tx lanes are powered down for MAC loopback tests, but
765 * they are not automatically restored on reset.
767 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
768 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
769 /* Enable Tx Atlas so packets can be transmitted again */
770 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
772 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
773 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
776 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
778 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
779 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
782 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
784 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
785 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
788 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
790 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
791 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
796 if (hw->phy.reset_disable == false) {
797 /* PHY ops must be identified and initialized prior to reset */
799 /* Init PHY and function pointers, perform SFP setup */
800 phy_status = hw->phy.ops.init(hw);
801 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED)
803 if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)
806 hw->phy.ops.reset(hw);
811 * Issue global reset to the MAC. This needs to be a SW reset.
812 * If link reset is used, it might reset the MAC when mng is using it
814 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST;
815 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
816 IXGBE_WRITE_FLUSH(hw);
818 /* Poll for reset bit to self-clear indicating reset is complete */
819 for (i = 0; i < 10; i++) {
821 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
822 if (!(ctrl & IXGBE_CTRL_RST))
825 if (ctrl & IXGBE_CTRL_RST) {
826 status = IXGBE_ERR_RESET_FAILED;
827 hw_dbg(hw, "Reset polling failed to complete.\n");
833 * Double resets are required for recovery from certain error
834 * conditions. Between resets, it is necessary to stall to allow time
835 * for any pending HW events to complete.
837 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
838 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
842 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
843 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
844 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
847 * Store the original AUTOC value if it has not been
848 * stored off yet. Otherwise restore the stored original
849 * AUTOC value since the reset operation sets back to deaults.
851 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
852 if (hw->mac.orig_link_settings_stored == false) {
853 hw->mac.orig_autoc = autoc;
854 hw->mac.orig_link_settings_stored = true;
855 } else if (autoc != hw->mac.orig_autoc) {
856 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
859 /* Store the permanent mac address */
860 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
863 * Store MAC address from RAR0, clear receive address registers, and
864 * clear the multicast table
866 hw->mac.ops.init_rx_addrs(hw);
876 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
877 * @hw: pointer to hardware struct
878 * @rar: receive address register index to associate with a VMDq index
879 * @vmdq: VMDq set index
881 static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
884 u32 rar_entries = hw->mac.num_rar_entries;
886 /* Make sure we are using a valid rar index range */
887 if (rar >= rar_entries) {
888 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
889 return IXGBE_ERR_INVALID_ARGUMENT;
892 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
893 rar_high &= ~IXGBE_RAH_VIND_MASK;
894 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
895 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
900 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
901 * @hw: pointer to hardware struct
902 * @rar: receive address register index to associate with a VMDq index
903 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
905 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
908 u32 rar_entries = hw->mac.num_rar_entries;
911 /* Make sure we are using a valid rar index range */
912 if (rar >= rar_entries) {
913 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
914 return IXGBE_ERR_INVALID_ARGUMENT;
917 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
918 if (rar_high & IXGBE_RAH_VIND_MASK) {
919 rar_high &= ~IXGBE_RAH_VIND_MASK;
920 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
927 * ixgbe_set_vfta_82598 - Set VLAN filter table
928 * @hw: pointer to hardware structure
929 * @vlan: VLAN id to write to VLAN filter
930 * @vind: VMDq output index that maps queue to VLAN id in VFTA
931 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
933 * Turn on/off specified VLAN in the VLAN filter table.
935 static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
944 return IXGBE_ERR_PARAM;
946 /* Determine 32-bit word position in array */
947 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */
949 /* Determine the location of the (VMD) queue index */
950 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
951 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */
953 /* Set the nibble for VMD queue index */
954 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
955 bits &= (~(0x0F << bitindex));
956 bits |= (vind << bitindex);
957 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
959 /* Determine the location of the bit for this VLAN id */
960 bitindex = vlan & 0x1F; /* lower five bits */
962 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
964 /* Turn on this VLAN id */
965 bits |= (1 << bitindex);
967 /* Turn off this VLAN id */
968 bits &= ~(1 << bitindex);
969 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
975 * ixgbe_clear_vfta_82598 - Clear VLAN filter table
976 * @hw: pointer to hardware structure
978 * Clears the VLAN filer table, and the VMDq index associated with the filter
980 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
985 for (offset = 0; offset < hw->mac.vft_size; offset++)
986 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
988 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
989 for (offset = 0; offset < hw->mac.vft_size; offset++)
990 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
997 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
998 * @hw: pointer to hardware structure
999 * @reg: analog register to read
1002 * Performs read operation to Atlas analog register specified.
1004 static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
1008 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
1009 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
1010 IXGBE_WRITE_FLUSH(hw);
1012 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
1013 *val = (u8)atlas_ctl;
1019 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
1020 * @hw: pointer to hardware structure
1021 * @reg: atlas register to write
1022 * @val: value to write
1024 * Performs write operation to Atlas analog register specified.
1026 static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
1030 atlas_ctl = (reg << 8) | val;
1031 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
1032 IXGBE_WRITE_FLUSH(hw);
1039 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
1040 * @hw: pointer to hardware structure
1041 * @byte_offset: EEPROM byte offset to read
1042 * @eeprom_data: value read
1044 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
1046 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
1055 if (hw->phy.type == ixgbe_phy_nl) {
1057 * phy SDA/SCL registers are at addresses 0xC30A to
1058 * 0xC30D. These registers are used to talk to the SFP+
1059 * module's EEPROM through the SDA/SCL (I2C) interface.
1061 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
1062 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
1063 hw->phy.ops.write_reg(hw,
1064 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
1069 for (i = 0; i < 100; i++) {
1070 hw->phy.ops.read_reg(hw,
1071 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
1074 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
1075 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
1077 usleep_range(10000, 20000);
1080 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
1081 hw_dbg(hw, "EEPROM read did not pass.\n");
1082 status = IXGBE_ERR_SFP_NOT_PRESENT;
1087 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1088 MDIO_MMD_PMAPMD, &sfp_data);
1090 *eeprom_data = (u8)(sfp_data >> 8);
1092 status = IXGBE_ERR_PHY;
1101 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1102 * @hw: pointer to hardware structure
1104 * Determines physical layer capabilities of the current configuration.
1106 static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1108 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1109 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1110 u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1111 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1112 u16 ext_ability = 0;
1114 hw->phy.ops.identify(hw);
1116 /* Copper PHY must be checked before AUTOC LMS to determine correct
1117 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
1118 switch (hw->phy.type) {
1121 case ixgbe_phy_cu_unknown:
1122 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE,
1123 MDIO_MMD_PMAPMD, &ext_ability);
1124 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
1125 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1126 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
1127 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1128 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
1129 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1135 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1136 case IXGBE_AUTOC_LMS_1G_AN:
1137 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1138 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX)
1139 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1141 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1143 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1144 if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4)
1145 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1146 else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4)
1147 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1149 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1151 case IXGBE_AUTOC_LMS_KX4_AN:
1152 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
1153 if (autoc & IXGBE_AUTOC_KX_SUPP)
1154 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1155 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1156 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1162 if (hw->phy.type == ixgbe_phy_nl) {
1163 hw->phy.ops.identify_sfp(hw);
1165 switch (hw->phy.sfp_type) {
1166 case ixgbe_sfp_type_da_cu:
1167 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1169 case ixgbe_sfp_type_sr:
1170 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1172 case ixgbe_sfp_type_lr:
1173 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1176 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1181 switch (hw->device_id) {
1182 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1183 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1185 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
1186 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1187 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
1188 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1190 case IXGBE_DEV_ID_82598EB_XF_LR:
1191 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1198 return physical_layer;
1202 * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple
1204 * @hw: pointer to the HW structure
1206 * Calls common function and corrects issue with some single port devices
1207 * that enable LAN1 but not LAN0.
1209 static void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw)
1211 struct ixgbe_bus_info *bus = &hw->bus;
1215 ixgbe_set_lan_id_multi_port_pcie(hw);
1217 /* check if LAN0 is disabled */
1218 hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen);
1219 if ((pci_gen != 0) && (pci_gen != 0xFFFF)) {
1221 hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2);
1223 /* if LAN0 is completely disabled force function to 0 */
1224 if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) &&
1225 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) &&
1226 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) {
1234 * ixgbe_set_rxpba_82598 - Configure packet buffers
1235 * @hw: pointer to hardware structure
1236 * @dcb_config: pointer to ixgbe_dcb_config structure
1238 * Configure packet buffers.
1240 static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb, u32 headroom,
1243 u32 rxpktsize = IXGBE_RXPBSIZE_64KB;
1249 /* Setup Rx packet buffer sizes */
1251 case PBA_STRATEGY_WEIGHTED:
1252 /* Setup the first four at 80KB */
1253 rxpktsize = IXGBE_RXPBSIZE_80KB;
1255 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1256 /* Setup the last four at 48KB...don't re-init i */
1257 rxpktsize = IXGBE_RXPBSIZE_48KB;
1259 case PBA_STRATEGY_EQUAL:
1261 /* Divide the remaining Rx packet buffer evenly among the TCs */
1262 for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1263 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1267 /* Setup Tx packet buffer sizes */
1268 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1269 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB);
1274 static struct ixgbe_mac_operations mac_ops_82598 = {
1275 .init_hw = &ixgbe_init_hw_generic,
1276 .reset_hw = &ixgbe_reset_hw_82598,
1277 .start_hw = &ixgbe_start_hw_82598,
1278 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
1279 .get_media_type = &ixgbe_get_media_type_82598,
1280 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598,
1281 .enable_rx_dma = &ixgbe_enable_rx_dma_generic,
1282 .get_mac_addr = &ixgbe_get_mac_addr_generic,
1283 .stop_adapter = &ixgbe_stop_adapter_generic,
1284 .get_bus_info = &ixgbe_get_bus_info_generic,
1285 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598,
1286 .read_analog_reg8 = &ixgbe_read_analog_reg8_82598,
1287 .write_analog_reg8 = &ixgbe_write_analog_reg8_82598,
1288 .setup_link = &ixgbe_setup_mac_link_82598,
1289 .set_rxpba = &ixgbe_set_rxpba_82598,
1290 .check_link = &ixgbe_check_mac_link_82598,
1291 .get_link_capabilities = &ixgbe_get_link_capabilities_82598,
1292 .led_on = &ixgbe_led_on_generic,
1293 .led_off = &ixgbe_led_off_generic,
1294 .blink_led_start = &ixgbe_blink_led_start_generic,
1295 .blink_led_stop = &ixgbe_blink_led_stop_generic,
1296 .set_rar = &ixgbe_set_rar_generic,
1297 .clear_rar = &ixgbe_clear_rar_generic,
1298 .set_vmdq = &ixgbe_set_vmdq_82598,
1299 .clear_vmdq = &ixgbe_clear_vmdq_82598,
1300 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
1301 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
1302 .enable_mc = &ixgbe_enable_mc_generic,
1303 .disable_mc = &ixgbe_disable_mc_generic,
1304 .clear_vfta = &ixgbe_clear_vfta_82598,
1305 .set_vfta = &ixgbe_set_vfta_82598,
1306 .fc_enable = &ixgbe_fc_enable_82598,
1307 .set_fw_drv_ver = NULL,
1308 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
1309 .release_swfw_sync = &ixgbe_release_swfw_sync,
1312 static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
1313 .init_params = &ixgbe_init_eeprom_params_generic,
1314 .read = &ixgbe_read_eerd_generic,
1315 .read_buffer = &ixgbe_read_eerd_buffer_generic,
1316 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
1317 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
1318 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
1321 static struct ixgbe_phy_operations phy_ops_82598 = {
1322 .identify = &ixgbe_identify_phy_generic,
1323 .identify_sfp = &ixgbe_identify_sfp_module_generic,
1324 .init = &ixgbe_init_phy_ops_82598,
1325 .reset = &ixgbe_reset_phy_generic,
1326 .read_reg = &ixgbe_read_phy_reg_generic,
1327 .write_reg = &ixgbe_write_phy_reg_generic,
1328 .setup_link = &ixgbe_setup_phy_link_generic,
1329 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
1330 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598,
1331 .check_overtemp = &ixgbe_tn_check_overtemp,
1334 struct ixgbe_info ixgbe_82598_info = {
1335 .mac = ixgbe_mac_82598EB,
1336 .get_invariants = &ixgbe_get_invariants_82598,
1337 .mac_ops = &mac_ops_82598,
1338 .eeprom_ops = &eeprom_ops_82598,
1339 .phy_ops = &phy_ops_82598,