1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
31 #include <linux/bitops.h>
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/netdevice.h>
35 #include <linux/cpumask.h>
36 #include <linux/aer.h>
37 #include <linux/if_vlan.h>
38 #include <linux/jiffies.h>
40 #include <linux/clocksource.h>
41 #include <linux/net_tstamp.h>
42 #include <linux/ptp_clock_kernel.h>
44 #include "ixgbe_type.h"
45 #include "ixgbe_common.h"
46 #include "ixgbe_dcb.h"
47 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
49 #include "ixgbe_fcoe.h"
50 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
51 #ifdef CONFIG_IXGBE_DCA
52 #include <linux/dca.h>
55 #include <net/busy_poll.h>
57 #ifdef CONFIG_NET_RX_BUSY_POLL
58 #define BP_EXTENDED_STATS
60 /* common prefix used by pr_<> macros */
62 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
64 /* TX/RX descriptor defines */
65 #define IXGBE_DEFAULT_TXD 512
66 #define IXGBE_DEFAULT_TX_WORK 256
67 #define IXGBE_MAX_TXD 4096
68 #define IXGBE_MIN_TXD 64
70 #if (PAGE_SIZE < 8192)
71 #define IXGBE_DEFAULT_RXD 512
73 #define IXGBE_DEFAULT_RXD 128
75 #define IXGBE_MAX_RXD 4096
76 #define IXGBE_MIN_RXD 64
79 #define IXGBE_MIN_FCRTL 0x40
80 #define IXGBE_MAX_FCRTL 0x7FF80
81 #define IXGBE_MIN_FCRTH 0x600
82 #define IXGBE_MAX_FCRTH 0x7FFF0
83 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF
84 #define IXGBE_MIN_FCPAUSE 0
85 #define IXGBE_MAX_FCPAUSE 0xFFFF
87 /* Supported Rx Buffer Sizes */
88 #define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */
89 #define IXGBE_RXBUFFER_2K 2048
90 #define IXGBE_RXBUFFER_3K 3072
91 #define IXGBE_RXBUFFER_4K 4096
92 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
95 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we
96 * reserve 64 more, and skb_shared_info adds an additional 320 bytes more,
97 * this adds up to 448 bytes of extra data.
99 * Since netdev_alloc_skb now allocates a page fragment we can use a value
100 * of 256 and the resultant skb will have a truesize of 960 or less.
102 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
104 /* How many Rx Buffers do we bundle into one write to the hardware ? */
105 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
107 enum ixgbe_tx_flags {
109 IXGBE_TX_FLAGS_HW_VLAN = 0x01,
110 IXGBE_TX_FLAGS_TSO = 0x02,
111 IXGBE_TX_FLAGS_TSTAMP = 0x04,
114 IXGBE_TX_FLAGS_CC = 0x08,
115 IXGBE_TX_FLAGS_IPV4 = 0x10,
116 IXGBE_TX_FLAGS_CSUM = 0x20,
118 /* software defined flags */
119 IXGBE_TX_FLAGS_SW_VLAN = 0x40,
120 IXGBE_TX_FLAGS_FCOE = 0x80,
124 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
125 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
126 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29
127 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16
129 #define IXGBE_MAX_VF_MC_ENTRIES 30
130 #define IXGBE_MAX_VF_FUNCTIONS 64
131 #define IXGBE_MAX_VFTA_ENTRIES 128
132 #define MAX_EMULATION_MAC_ADDRS 16
133 #define IXGBE_MAX_PF_MACVLANS 15
134 #define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset)
135 #define IXGBE_82599_VF_DEVICE_ID 0x10ED
136 #define IXGBE_X540_VF_DEVICE_ID 0x1515
138 struct vf_data_storage {
139 unsigned char vf_mac_addresses[ETH_ALEN];
140 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
141 u16 num_vf_mc_hashes;
142 u16 default_vf_vlan_id;
146 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
160 u8 vf_macvlan[ETH_ALEN];
163 #define IXGBE_MAX_TXD_PWR 14
164 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
166 /* Tx Descriptors needed, worst case */
167 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
168 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
170 /* wrapper around a pointer to a socket buffer,
171 * so a DMA handle can be stored along with the buffer */
172 struct ixgbe_tx_buffer {
173 union ixgbe_adv_tx_desc *next_to_watch;
174 unsigned long time_stamp;
176 unsigned int bytecount;
177 unsigned short gso_segs;
179 DEFINE_DMA_UNMAP_ADDR(dma);
180 DEFINE_DMA_UNMAP_LEN(len);
184 struct ixgbe_rx_buffer {
188 unsigned int page_offset;
191 struct ixgbe_queue_stats {
194 #ifdef BP_EXTENDED_STATS
198 #endif /* BP_EXTENDED_STATS */
201 struct ixgbe_tx_queue_stats {
207 struct ixgbe_rx_queue_stats {
211 u64 alloc_rx_page_failed;
212 u64 alloc_rx_buff_failed;
216 enum ixgbe_ring_state_t {
217 __IXGBE_TX_FDIR_INIT_DONE,
218 __IXGBE_TX_XPS_INIT_DONE,
219 __IXGBE_TX_DETECT_HANG,
220 __IXGBE_HANG_CHECK_ARMED,
221 __IXGBE_RX_RSC_ENABLED,
222 __IXGBE_RX_CSUM_UDP_ZERO_ERR,
226 #define check_for_tx_hang(ring) \
227 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
228 #define set_check_for_tx_hang(ring) \
229 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
230 #define clear_check_for_tx_hang(ring) \
231 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
232 #define ring_is_rsc_enabled(ring) \
233 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
234 #define set_ring_rsc_enabled(ring) \
235 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
236 #define clear_ring_rsc_enabled(ring) \
237 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
239 struct ixgbe_ring *next; /* pointer to next ring in q_vector */
240 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */
241 struct net_device *netdev; /* netdev ring belongs to */
242 struct device *dev; /* device for DMA mapping */
243 void *desc; /* descriptor ring memory */
245 struct ixgbe_tx_buffer *tx_buffer_info;
246 struct ixgbe_rx_buffer *rx_buffer_info;
248 unsigned long last_rx_timestamp;
251 dma_addr_t dma; /* phys. address of descriptor ring */
252 unsigned int size; /* length in bytes */
254 u16 count; /* amount of descriptors */
256 u8 queue_index; /* needed for multiqueue queue management */
257 u8 reg_idx; /* holds the special value that gets
258 * the hardware register offset
259 * associated with this ring, which is
260 * different for DCB and RSS modes
274 struct ixgbe_queue_stats stats;
275 struct u64_stats_sync syncp;
277 struct ixgbe_tx_queue_stats tx_stats;
278 struct ixgbe_rx_queue_stats rx_stats;
280 } ____cacheline_internodealigned_in_smp;
282 enum ixgbe_ring_f_enum {
284 RING_F_VMDQ, /* SR-IOV uses the same ring feature */
289 #endif /* IXGBE_FCOE */
291 RING_F_ARRAY_SIZE /* must be last in enum set */
294 #define IXGBE_MAX_RSS_INDICES 16
295 #define IXGBE_MAX_VMDQ_INDICES 64
296 #define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */
297 #define IXGBE_MAX_FCOE_INDICES 8
298 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1)
299 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1)
300 struct ixgbe_ring_feature {
301 u16 limit; /* upper limit on feature indices */
302 u16 indices; /* current value of indices */
303 u16 mask; /* Mask used for feature to ring mapping */
304 u16 offset; /* offset to start of feature */
305 } ____cacheline_internodealigned_in_smp;
307 #define IXGBE_82599_VMDQ_8Q_MASK 0x78
308 #define IXGBE_82599_VMDQ_4Q_MASK 0x7C
309 #define IXGBE_82599_VMDQ_2Q_MASK 0x7E
312 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since
313 * this is twice the size of a half page we need to double the page order
314 * for FCoE enabled Rx queues.
316 static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring)
319 if (test_bit(__IXGBE_RX_FCOE, &ring->state))
320 return (PAGE_SIZE < 8192) ? IXGBE_RXBUFFER_4K :
323 return IXGBE_RXBUFFER_2K;
326 static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring)
329 if (test_bit(__IXGBE_RX_FCOE, &ring->state))
330 return (PAGE_SIZE < 8192) ? 1 : 0;
334 #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring))
336 struct ixgbe_ring_container {
337 struct ixgbe_ring *ring; /* pointer to linked list of rings */
338 unsigned int total_bytes; /* total bytes processed this int */
339 unsigned int total_packets; /* total packets processed this int */
340 u16 work_limit; /* total work allowed per interrupt */
341 u8 count; /* total number of rings in vector */
342 u8 itr; /* current ITR setting for ring */
345 /* iterator for handling rings in ring container */
346 #define ixgbe_for_each_ring(pos, head) \
347 for (pos = (head).ring; pos != NULL; pos = pos->next)
349 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
351 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
353 /* MAX_Q_VECTORS of these are allocated,
354 * but we only use one per queue-specific vector.
356 struct ixgbe_q_vector {
357 struct ixgbe_adapter *adapter;
358 #ifdef CONFIG_IXGBE_DCA
359 int cpu; /* CPU for DCA */
361 u16 v_idx; /* index of q_vector within array, also used for
362 * finding the bit in EICR and friends that
363 * represents the vector for this ring */
364 u16 itr; /* Interrupt throttle rate written to EITR */
365 struct ixgbe_ring_container rx, tx;
367 struct napi_struct napi;
368 cpumask_t affinity_mask;
370 struct rcu_head rcu; /* to avoid race with update stats on free */
371 char name[IFNAMSIZ + 9];
373 #ifdef CONFIG_NET_RX_BUSY_POLL
375 #define IXGBE_QV_STATE_IDLE 0
376 #define IXGBE_QV_STATE_NAPI 1 /* NAPI owns this QV */
377 #define IXGBE_QV_STATE_POLL 2 /* poll owns this QV */
378 #define IXGBE_QV_STATE_DISABLED 4 /* QV is disabled */
379 #define IXGBE_QV_OWNED (IXGBE_QV_STATE_NAPI | IXGBE_QV_STATE_POLL)
380 #define IXGBE_QV_LOCKED (IXGBE_QV_OWNED | IXGBE_QV_STATE_DISABLED)
381 #define IXGBE_QV_STATE_NAPI_YIELD 8 /* NAPI yielded this QV */
382 #define IXGBE_QV_STATE_POLL_YIELD 16 /* poll yielded this QV */
383 #define IXGBE_QV_YIELD (IXGBE_QV_STATE_NAPI_YIELD | IXGBE_QV_STATE_POLL_YIELD)
384 #define IXGBE_QV_USER_PEND (IXGBE_QV_STATE_POLL | IXGBE_QV_STATE_POLL_YIELD)
386 #endif /* CONFIG_NET_RX_BUSY_POLL */
388 /* for dynamic allocation of rings associated with this q_vector */
389 struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp;
391 #ifdef CONFIG_NET_RX_BUSY_POLL
392 static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector)
395 spin_lock_init(&q_vector->lock);
396 q_vector->state = IXGBE_QV_STATE_IDLE;
399 /* called from the device poll routine to get ownership of a q_vector */
400 static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector)
403 spin_lock_bh(&q_vector->lock);
404 if (q_vector->state & IXGBE_QV_LOCKED) {
405 WARN_ON(q_vector->state & IXGBE_QV_STATE_NAPI);
406 q_vector->state |= IXGBE_QV_STATE_NAPI_YIELD;
408 #ifdef BP_EXTENDED_STATS
409 q_vector->tx.ring->stats.yields++;
412 /* we don't care if someone yielded */
413 q_vector->state = IXGBE_QV_STATE_NAPI;
414 spin_unlock_bh(&q_vector->lock);
418 /* returns true is someone tried to get the qv while napi had it */
419 static inline bool ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector)
422 spin_lock_bh(&q_vector->lock);
423 WARN_ON(q_vector->state & (IXGBE_QV_STATE_POLL |
424 IXGBE_QV_STATE_NAPI_YIELD));
426 if (q_vector->state & IXGBE_QV_STATE_POLL_YIELD)
428 /* will reset state to idle, unless QV is disabled */
429 q_vector->state &= IXGBE_QV_STATE_DISABLED;
430 spin_unlock_bh(&q_vector->lock);
434 /* called from ixgbe_low_latency_poll() */
435 static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector)
438 spin_lock_bh(&q_vector->lock);
439 if ((q_vector->state & IXGBE_QV_LOCKED)) {
440 q_vector->state |= IXGBE_QV_STATE_POLL_YIELD;
442 #ifdef BP_EXTENDED_STATS
443 q_vector->rx.ring->stats.yields++;
446 /* preserve yield marks */
447 q_vector->state |= IXGBE_QV_STATE_POLL;
448 spin_unlock_bh(&q_vector->lock);
452 /* returns true if someone tried to get the qv while it was locked */
453 static inline bool ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector)
456 spin_lock_bh(&q_vector->lock);
457 WARN_ON(q_vector->state & (IXGBE_QV_STATE_NAPI));
459 if (q_vector->state & IXGBE_QV_STATE_POLL_YIELD)
461 /* will reset state to idle, unless QV is disabled */
462 q_vector->state &= IXGBE_QV_STATE_DISABLED;
463 spin_unlock_bh(&q_vector->lock);
467 /* true if a socket is polling, even if it did not get the lock */
468 static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector)
470 WARN_ON(!(q_vector->state & IXGBE_QV_OWNED));
471 return q_vector->state & IXGBE_QV_USER_PEND;
474 /* false if QV is currently owned */
475 static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector)
478 spin_lock_bh(&q_vector->lock);
479 if (q_vector->state & IXGBE_QV_OWNED)
481 q_vector->state |= IXGBE_QV_STATE_DISABLED;
482 spin_unlock_bh(&q_vector->lock);
487 #else /* CONFIG_NET_RX_BUSY_POLL */
488 static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector)
492 static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector)
497 static inline bool ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector)
502 static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector)
507 static inline bool ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector)
512 static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector)
517 static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector)
522 #endif /* CONFIG_NET_RX_BUSY_POLL */
524 #ifdef CONFIG_IXGBE_HWMON
526 #define IXGBE_HWMON_TYPE_LOC 0
527 #define IXGBE_HWMON_TYPE_TEMP 1
528 #define IXGBE_HWMON_TYPE_CAUTION 2
529 #define IXGBE_HWMON_TYPE_MAX 3
532 struct device_attribute dev_attr;
534 struct ixgbe_thermal_diode_data *sensor;
539 struct device *device;
540 struct hwmon_attr *hwmon_list;
541 unsigned int n_hwmon;
543 #endif /* CONFIG_IXGBE_HWMON */
546 * microsecond values for various ITR rates shifted by 2 to fit itr register
547 * with the first 3 bits reserved 0
549 #define IXGBE_MIN_RSC_ITR 24
550 #define IXGBE_100K_ITR 40
551 #define IXGBE_20K_ITR 200
552 #define IXGBE_10K_ITR 400
553 #define IXGBE_8K_ITR 500
555 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */
556 static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
557 const u32 stat_err_bits)
559 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
562 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
564 u16 ntc = ring->next_to_clean;
565 u16 ntu = ring->next_to_use;
567 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
570 #define IXGBE_RX_DESC(R, i) \
571 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
572 #define IXGBE_TX_DESC(R, i) \
573 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
574 #define IXGBE_TX_CTXTDESC(R, i) \
575 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
577 #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */
579 /* Use 3K as the baby jumbo frame size for FCoE */
580 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
581 #endif /* IXGBE_FCOE */
583 #define OTHER_VECTOR 1
584 #define NON_Q_VECTORS (OTHER_VECTOR)
586 #define MAX_MSIX_VECTORS_82599 64
587 #define MAX_Q_VECTORS_82599 64
588 #define MAX_MSIX_VECTORS_82598 18
589 #define MAX_Q_VECTORS_82598 16
591 #define MAX_Q_VECTORS MAX_Q_VECTORS_82599
592 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
594 #define MIN_MSIX_Q_VECTORS 1
595 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
597 /* default to trying for four seconds */
598 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
600 /* board specific private data structure */
601 struct ixgbe_adapter {
602 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
603 /* OS defined structs */
604 struct net_device *netdev;
605 struct pci_dev *pdev;
609 /* Some features need tri-state capability,
610 * thus the additional *_CAPABLE flags.
613 #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 0)
614 #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 1)
615 #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 2)
616 #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 3)
617 #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 4)
618 #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 5)
619 #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 6)
620 #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 7)
621 #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 8)
622 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 9)
623 #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 10)
624 #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 11)
625 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 12)
626 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 13)
627 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 14)
628 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 15)
629 #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 16)
630 #define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 17)
631 #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 18)
632 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 19)
633 #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 20)
634 #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 21)
635 #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 22)
636 #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 23)
639 #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1 << 0)
640 #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
641 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
642 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3)
643 #define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4)
644 #define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5)
645 #define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6)
646 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7)
647 #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8)
648 #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9)
649 #define IXGBE_FLAG2_PTP_PPS_ENABLED (u32)(1 << 10)
650 #define IXGBE_FLAG2_BRIDGE_MODE_VEB (u32)(1 << 11)
652 /* Tx fast path data */
657 /* Rx fast path data */
662 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
666 u32 tx_timeout_count;
669 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES];
670 int num_rx_pools; /* == num_rx_queues in 82598 */
671 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
672 u64 hw_csum_rx_error;
673 u64 hw_rx_no_dma_resources;
677 u32 alloc_rx_page_failed;
678 u32 alloc_rx_buff_failed;
680 struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS];
683 struct ieee_pfc *ixgbe_ieee_pfc;
684 struct ieee_ets *ixgbe_ieee_ets;
685 struct ixgbe_dcb_config dcb_cfg;
686 struct ixgbe_dcb_config temp_dcb_cfg;
689 enum ixgbe_fc_mode last_lfc_mode;
691 int num_q_vectors; /* current number of q_vectors for device */
692 int max_q_vectors; /* true count of q_vectors for device */
693 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
694 struct msix_entry *msix_entries;
697 struct ixgbe_ring test_tx_ring;
698 struct ixgbe_ring test_rx_ring;
700 /* structs defined in ixgbe_hw.h */
703 struct ixgbe_hw_stats stats;
706 unsigned int tx_ring_count;
707 unsigned int rx_ring_count;
711 unsigned long link_check_timeout;
713 struct timer_list service_timer;
714 struct work_struct service_task;
716 struct hlist_head fdir_filter_list;
717 unsigned long fdir_overflow; /* number of times ATR was backed off */
718 union ixgbe_atr_input fdir_mask;
719 int fdir_filter_count;
722 spinlock_t fdir_perfect_lock;
725 struct ixgbe_fcoe fcoe;
726 #endif /* IXGBE_FCOE */
738 struct ptp_clock *ptp_clock;
739 struct ptp_clock_info ptp_caps;
740 struct work_struct ptp_tx_work;
741 struct sk_buff *ptp_tx_skb;
742 unsigned long ptp_tx_start;
743 unsigned long last_overflow_check;
744 unsigned long last_rx_ptp_check;
745 spinlock_t tmreg_lock;
746 struct cyclecounter cc;
747 struct timecounter tc;
751 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
752 unsigned int num_vfs;
753 struct vf_data_storage *vfinfo;
754 int vf_rate_link_speed;
755 struct vf_macvlans vf_mvs;
756 struct vf_macvlans *mv_list;
758 u32 timer_event_accumulator;
760 struct kobject *info_kobj;
761 #ifdef CONFIG_IXGBE_HWMON
762 struct hwmon_buff ixgbe_hwmon_buff;
763 #endif /* CONFIG_IXGBE_HWMON */
764 #ifdef CONFIG_DEBUG_FS
765 struct dentry *ixgbe_dbg_adapter;
766 #endif /*CONFIG_DEBUG_FS*/
771 struct ixgbe_fdir_filter {
772 struct hlist_node fdir_node;
773 union ixgbe_atr_input filter;
782 __IXGBE_SERVICE_SCHED,
788 union { /* Union defining head/tail partner */
789 struct sk_buff *head;
790 struct sk_buff *tail;
796 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb)
804 extern struct ixgbe_info ixgbe_82598_info;
805 extern struct ixgbe_info ixgbe_82599_info;
806 extern struct ixgbe_info ixgbe_X540_info;
807 #ifdef CONFIG_IXGBE_DCB
808 extern const struct dcbnl_rtnl_ops dcbnl_ops;
811 extern char ixgbe_driver_name[];
812 extern const char ixgbe_driver_version[];
814 extern char ixgbe_default_device_descr[];
815 #endif /* IXGBE_FCOE */
817 void ixgbe_up(struct ixgbe_adapter *adapter);
818 void ixgbe_down(struct ixgbe_adapter *adapter);
819 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
820 void ixgbe_reset(struct ixgbe_adapter *adapter);
821 void ixgbe_set_ethtool_ops(struct net_device *netdev);
822 int ixgbe_setup_rx_resources(struct ixgbe_ring *);
823 int ixgbe_setup_tx_resources(struct ixgbe_ring *);
824 void ixgbe_free_rx_resources(struct ixgbe_ring *);
825 void ixgbe_free_tx_resources(struct ixgbe_ring *);
826 void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *);
827 void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *);
828 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_ring *);
829 void ixgbe_update_stats(struct ixgbe_adapter *adapter);
830 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
831 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
833 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
834 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *,
835 struct ixgbe_ring *);
836 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
837 struct ixgbe_tx_buffer *);
838 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
839 void ixgbe_write_eitr(struct ixgbe_q_vector *);
840 int ixgbe_poll(struct napi_struct *napi, int budget);
841 int ethtool_ioctl(struct ifreq *ifr);
842 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
843 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
844 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
845 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
846 union ixgbe_atr_hash_dword input,
847 union ixgbe_atr_hash_dword common,
849 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
850 union ixgbe_atr_input *input_mask);
851 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
852 union ixgbe_atr_input *input,
853 u16 soft_id, u8 queue);
854 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
855 union ixgbe_atr_input *input,
857 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
858 union ixgbe_atr_input *mask);
859 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
860 void ixgbe_set_rx_mode(struct net_device *netdev);
861 #ifdef CONFIG_IXGBE_DCB
862 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter);
864 int ixgbe_setup_tc(struct net_device *dev, u8 tc);
865 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
866 void ixgbe_do_reset(struct net_device *netdev);
867 #ifdef CONFIG_IXGBE_HWMON
868 void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter);
869 int ixgbe_sysfs_init(struct ixgbe_adapter *adapter);
870 #endif /* CONFIG_IXGBE_HWMON */
872 void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
873 int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first,
875 int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
876 union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb);
877 int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
878 struct scatterlist *sgl, unsigned int sgc);
879 int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
880 struct scatterlist *sgl, unsigned int sgc);
881 int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
882 int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
883 void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
884 int ixgbe_fcoe_enable(struct net_device *netdev);
885 int ixgbe_fcoe_disable(struct net_device *netdev);
886 #ifdef CONFIG_IXGBE_DCB
887 u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
888 u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
889 #endif /* CONFIG_IXGBE_DCB */
890 int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
891 int ixgbe_fcoe_get_hbainfo(struct net_device *netdev,
892 struct netdev_fcoe_hbainfo *info);
893 u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter);
894 #endif /* IXGBE_FCOE */
895 #ifdef CONFIG_DEBUG_FS
896 void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter);
897 void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter);
898 void ixgbe_dbg_init(void);
899 void ixgbe_dbg_exit(void);
901 static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {}
902 static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {}
903 static inline void ixgbe_dbg_init(void) {}
904 static inline void ixgbe_dbg_exit(void) {}
905 #endif /* CONFIG_DEBUG_FS */
906 static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring)
908 return netdev_get_tx_queue(ring->netdev, ring->queue_index);
911 void ixgbe_ptp_init(struct ixgbe_adapter *adapter);
912 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter);
913 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter);
914 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter);
915 void __ixgbe_ptp_rx_hwtstamp(struct ixgbe_q_vector *q_vector,
916 struct sk_buff *skb);
917 static inline void ixgbe_ptp_rx_hwtstamp(struct ixgbe_ring *rx_ring,
918 union ixgbe_adv_rx_desc *rx_desc,
921 if (unlikely(!ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
924 __ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector, skb);
927 * Update the last_rx_timestamp timer in order to enable watchdog check
928 * for error case of latched timestamp on a dropped packet.
930 rx_ring->last_rx_timestamp = jiffies;
933 int ixgbe_ptp_hwtstamp_ioctl(struct ixgbe_adapter *adapter, struct ifreq *ifr,
935 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter);
936 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter);
937 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr);
938 #ifdef CONFIG_PCI_IOV
939 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter);
942 #endif /* _IXGBE_H_ */