1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019 Intel Corporation */
6 #include <linux/module.h>
7 #include <linux/device.h>
9 #include <linux/ptp_classify.h>
10 #include <linux/clocksource.h>
11 #include <linux/ktime.h>
12 #include <linux/delay.h>
13 #include <linux/iopoll.h>
15 #define INCVALUE_MASK 0x7fffffff
16 #define ISGN 0x80000000
18 #define IGC_PTP_TX_TIMEOUT (HZ * 15)
20 #define IGC_PTM_STAT_SLEEP 2
21 #define IGC_PTM_STAT_TIMEOUT 100
23 /* SYSTIM read access for I225 */
24 void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts)
26 struct igc_hw *hw = &adapter->hw;
29 /* The timestamp is latched when SYSTIML is read. */
30 nsec = rd32(IGC_SYSTIML);
31 sec = rd32(IGC_SYSTIMH);
37 static void igc_ptp_write_i225(struct igc_adapter *adapter,
38 const struct timespec64 *ts)
40 struct igc_hw *hw = &adapter->hw;
42 wr32(IGC_SYSTIML, ts->tv_nsec);
43 wr32(IGC_SYSTIMH, ts->tv_sec);
46 static int igc_ptp_adjfine_i225(struct ptp_clock_info *ptp, long scaled_ppm)
48 struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
50 struct igc_hw *hw = &igc->hw;
57 scaled_ppm = -scaled_ppm;
61 rate = div_u64(rate, 78125);
63 inca = rate & INCVALUE_MASK;
67 wr32(IGC_TIMINCA, inca);
72 static int igc_ptp_adjtime_i225(struct ptp_clock_info *ptp, s64 delta)
74 struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
76 struct timespec64 now, then = ns_to_timespec64(delta);
79 spin_lock_irqsave(&igc->tmreg_lock, flags);
81 igc_ptp_read(igc, &now);
82 now = timespec64_add(now, then);
83 igc_ptp_write_i225(igc, (const struct timespec64 *)&now);
85 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
90 static int igc_ptp_gettimex64_i225(struct ptp_clock_info *ptp,
91 struct timespec64 *ts,
92 struct ptp_system_timestamp *sts)
94 struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
96 struct igc_hw *hw = &igc->hw;
99 spin_lock_irqsave(&igc->tmreg_lock, flags);
101 ptp_read_system_prets(sts);
102 ts->tv_nsec = rd32(IGC_SYSTIML);
103 ts->tv_sec = rd32(IGC_SYSTIMH);
104 ptp_read_system_postts(sts);
106 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
111 static int igc_ptp_settime_i225(struct ptp_clock_info *ptp,
112 const struct timespec64 *ts)
114 struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
118 spin_lock_irqsave(&igc->tmreg_lock, flags);
120 igc_ptp_write_i225(igc, ts);
122 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
127 static void igc_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext)
129 u32 *ptr = pin < 2 ? ctrl : ctrl_ext;
130 static const u32 mask[IGC_N_SDP] = {
133 IGC_CTRL_EXT_SDP2_DIR,
134 IGC_CTRL_EXT_SDP3_DIR,
143 static void igc_pin_perout(struct igc_adapter *igc, int chan, int pin, int freq)
145 static const u32 igc_aux0_sel_sdp[IGC_N_SDP] = {
146 IGC_AUX0_SEL_SDP0, IGC_AUX0_SEL_SDP1, IGC_AUX0_SEL_SDP2, IGC_AUX0_SEL_SDP3,
148 static const u32 igc_aux1_sel_sdp[IGC_N_SDP] = {
149 IGC_AUX1_SEL_SDP0, IGC_AUX1_SEL_SDP1, IGC_AUX1_SEL_SDP2, IGC_AUX1_SEL_SDP3,
151 static const u32 igc_ts_sdp_en[IGC_N_SDP] = {
152 IGC_TS_SDP0_EN, IGC_TS_SDP1_EN, IGC_TS_SDP2_EN, IGC_TS_SDP3_EN,
154 static const u32 igc_ts_sdp_sel_tt0[IGC_N_SDP] = {
155 IGC_TS_SDP0_SEL_TT0, IGC_TS_SDP1_SEL_TT0,
156 IGC_TS_SDP2_SEL_TT0, IGC_TS_SDP3_SEL_TT0,
158 static const u32 igc_ts_sdp_sel_tt1[IGC_N_SDP] = {
159 IGC_TS_SDP0_SEL_TT1, IGC_TS_SDP1_SEL_TT1,
160 IGC_TS_SDP2_SEL_TT1, IGC_TS_SDP3_SEL_TT1,
162 static const u32 igc_ts_sdp_sel_fc0[IGC_N_SDP] = {
163 IGC_TS_SDP0_SEL_FC0, IGC_TS_SDP1_SEL_FC0,
164 IGC_TS_SDP2_SEL_FC0, IGC_TS_SDP3_SEL_FC0,
166 static const u32 igc_ts_sdp_sel_fc1[IGC_N_SDP] = {
167 IGC_TS_SDP0_SEL_FC1, IGC_TS_SDP1_SEL_FC1,
168 IGC_TS_SDP2_SEL_FC1, IGC_TS_SDP3_SEL_FC1,
170 static const u32 igc_ts_sdp_sel_clr[IGC_N_SDP] = {
171 IGC_TS_SDP0_SEL_FC1, IGC_TS_SDP1_SEL_FC1,
172 IGC_TS_SDP2_SEL_FC1, IGC_TS_SDP3_SEL_FC1,
174 struct igc_hw *hw = &igc->hw;
175 u32 ctrl, ctrl_ext, tssdp = 0;
177 ctrl = rd32(IGC_CTRL);
178 ctrl_ext = rd32(IGC_CTRL_EXT);
179 tssdp = rd32(IGC_TSSDP);
181 igc_pin_direction(pin, 0, &ctrl, &ctrl_ext);
183 /* Make sure this pin is not enabled as an input. */
184 if ((tssdp & IGC_AUX0_SEL_SDP3) == igc_aux0_sel_sdp[pin])
185 tssdp &= ~IGC_AUX0_TS_SDP_EN;
187 if ((tssdp & IGC_AUX1_SEL_SDP3) == igc_aux1_sel_sdp[pin])
188 tssdp &= ~IGC_AUX1_TS_SDP_EN;
190 tssdp &= ~igc_ts_sdp_sel_clr[pin];
193 tssdp |= igc_ts_sdp_sel_fc1[pin];
195 tssdp |= igc_ts_sdp_sel_fc0[pin];
198 tssdp |= igc_ts_sdp_sel_tt1[pin];
200 tssdp |= igc_ts_sdp_sel_tt0[pin];
202 tssdp |= igc_ts_sdp_en[pin];
204 wr32(IGC_TSSDP, tssdp);
205 wr32(IGC_CTRL, ctrl);
206 wr32(IGC_CTRL_EXT, ctrl_ext);
209 static void igc_pin_extts(struct igc_adapter *igc, int chan, int pin)
211 static const u32 igc_aux0_sel_sdp[IGC_N_SDP] = {
212 IGC_AUX0_SEL_SDP0, IGC_AUX0_SEL_SDP1, IGC_AUX0_SEL_SDP2, IGC_AUX0_SEL_SDP3,
214 static const u32 igc_aux1_sel_sdp[IGC_N_SDP] = {
215 IGC_AUX1_SEL_SDP0, IGC_AUX1_SEL_SDP1, IGC_AUX1_SEL_SDP2, IGC_AUX1_SEL_SDP3,
217 static const u32 igc_ts_sdp_en[IGC_N_SDP] = {
218 IGC_TS_SDP0_EN, IGC_TS_SDP1_EN, IGC_TS_SDP2_EN, IGC_TS_SDP3_EN,
220 struct igc_hw *hw = &igc->hw;
221 u32 ctrl, ctrl_ext, tssdp = 0;
223 ctrl = rd32(IGC_CTRL);
224 ctrl_ext = rd32(IGC_CTRL_EXT);
225 tssdp = rd32(IGC_TSSDP);
227 igc_pin_direction(pin, 1, &ctrl, &ctrl_ext);
229 /* Make sure this pin is not enabled as an output. */
230 tssdp &= ~igc_ts_sdp_en[pin];
233 tssdp &= ~IGC_AUX1_SEL_SDP3;
234 tssdp |= igc_aux1_sel_sdp[pin] | IGC_AUX1_TS_SDP_EN;
236 tssdp &= ~IGC_AUX0_SEL_SDP3;
237 tssdp |= igc_aux0_sel_sdp[pin] | IGC_AUX0_TS_SDP_EN;
240 wr32(IGC_TSSDP, tssdp);
241 wr32(IGC_CTRL, ctrl);
242 wr32(IGC_CTRL_EXT, ctrl_ext);
245 static int igc_ptp_feature_enable_i225(struct ptp_clock_info *ptp,
246 struct ptp_clock_request *rq, int on)
248 struct igc_adapter *igc =
249 container_of(ptp, struct igc_adapter, ptp_caps);
250 struct igc_hw *hw = &igc->hw;
252 struct timespec64 ts;
253 int use_freq = 0, pin = -1;
254 u32 tsim, tsauxc, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout;
258 case PTP_CLK_REQ_EXTTS:
259 /* Reject requests with unsupported flags */
260 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
266 /* Reject requests failing to enable both edges. */
267 if ((rq->extts.flags & PTP_STRICT_FLAGS) &&
268 (rq->extts.flags & PTP_ENABLE_FEATURE) &&
269 (rq->extts.flags & PTP_EXTTS_EDGES) != PTP_EXTTS_EDGES)
273 pin = ptp_find_pin(igc->ptp_clock, PTP_PF_EXTTS,
278 if (rq->extts.index == 1) {
279 tsauxc_mask = IGC_TSAUXC_EN_TS1;
280 tsim_mask = IGC_TSICR_AUTT1;
282 tsauxc_mask = IGC_TSAUXC_EN_TS0;
283 tsim_mask = IGC_TSICR_AUTT0;
285 spin_lock_irqsave(&igc->tmreg_lock, flags);
286 tsauxc = rd32(IGC_TSAUXC);
287 tsim = rd32(IGC_TSIM);
289 igc_pin_extts(igc, rq->extts.index, pin);
290 tsauxc |= tsauxc_mask;
293 tsauxc &= ~tsauxc_mask;
296 wr32(IGC_TSAUXC, tsauxc);
297 wr32(IGC_TSIM, tsim);
298 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
301 case PTP_CLK_REQ_PEROUT:
302 /* Reject requests with unsupported flags */
303 if (rq->perout.flags)
307 pin = ptp_find_pin(igc->ptp_clock, PTP_PF_PEROUT,
312 ts.tv_sec = rq->perout.period.sec;
313 ts.tv_nsec = rq->perout.period.nsec;
314 ns = timespec64_to_ns(&ts);
316 if (on && (ns <= 70000000LL || ns == 125000000LL ||
317 ns == 250000000LL || ns == 500000000LL)) {
322 ts = ns_to_timespec64(ns);
323 if (rq->perout.index == 1) {
325 tsauxc_mask = IGC_TSAUXC_EN_CLK1;
328 tsauxc_mask = IGC_TSAUXC_EN_TT1;
329 tsim_mask = IGC_TSICR_TT1;
331 trgttiml = IGC_TRGTTIML1;
332 trgttimh = IGC_TRGTTIMH1;
333 freqout = IGC_FREQOUT1;
336 tsauxc_mask = IGC_TSAUXC_EN_CLK0;
339 tsauxc_mask = IGC_TSAUXC_EN_TT0;
340 tsim_mask = IGC_TSICR_TT0;
342 trgttiml = IGC_TRGTTIML0;
343 trgttimh = IGC_TRGTTIMH0;
344 freqout = IGC_FREQOUT0;
346 spin_lock_irqsave(&igc->tmreg_lock, flags);
347 tsauxc = rd32(IGC_TSAUXC);
348 tsim = rd32(IGC_TSIM);
349 if (rq->perout.index == 1) {
350 tsauxc &= ~(IGC_TSAUXC_EN_TT1 | IGC_TSAUXC_EN_CLK1);
351 tsim &= ~IGC_TSICR_TT1;
353 tsauxc &= ~(IGC_TSAUXC_EN_TT0 | IGC_TSAUXC_EN_CLK0);
354 tsim &= ~IGC_TSICR_TT0;
357 int i = rq->perout.index;
359 igc_pin_perout(igc, i, pin, use_freq);
360 igc->perout[i].start.tv_sec = rq->perout.start.sec;
361 igc->perout[i].start.tv_nsec = rq->perout.start.nsec;
362 igc->perout[i].period.tv_sec = ts.tv_sec;
363 igc->perout[i].period.tv_nsec = ts.tv_nsec;
364 wr32(trgttimh, rq->perout.start.sec);
365 /* For now, always select timer 0 as source. */
366 wr32(trgttiml, rq->perout.start.nsec | IGC_TT_IO_TIMER_SEL_SYSTIM0);
369 tsauxc |= tsauxc_mask;
372 wr32(IGC_TSAUXC, tsauxc);
373 wr32(IGC_TSIM, tsim);
374 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
377 case PTP_CLK_REQ_PPS:
378 spin_lock_irqsave(&igc->tmreg_lock, flags);
379 tsim = rd32(IGC_TSIM);
381 tsim |= IGC_TSICR_SYS_WRAP;
383 tsim &= ~IGC_TSICR_SYS_WRAP;
384 igc->pps_sys_wrap_on = on;
385 wr32(IGC_TSIM, tsim);
386 spin_unlock_irqrestore(&igc->tmreg_lock, flags);
396 static int igc_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
397 enum ptp_pin_function func, unsigned int chan)
411 * igc_ptp_systim_to_hwtstamp - convert system time value to HW timestamp
412 * @adapter: board private structure
413 * @hwtstamps: timestamp structure to update
414 * @systim: unsigned 64bit system time value
416 * We need to convert the system time value stored in the RX/TXSTMP registers
417 * into a hwtstamp which can be used by the upper level timestamping functions.
419 static void igc_ptp_systim_to_hwtstamp(struct igc_adapter *adapter,
420 struct skb_shared_hwtstamps *hwtstamps,
423 switch (adapter->hw.mac.type) {
425 memset(hwtstamps, 0, sizeof(*hwtstamps));
426 /* Upper 32 bits contain s, lower 32 bits contain ns. */
427 hwtstamps->hwtstamp = ktime_set(systim >> 32,
428 systim & 0xFFFFFFFF);
436 * igc_ptp_rx_pktstamp - Retrieve timestamp from Rx packet buffer
437 * @adapter: Pointer to adapter the packet buffer belongs to
438 * @buf: Pointer to packet buffer
440 * This function retrieves the timestamp saved in the beginning of packet
441 * buffer. While two timestamps are available, one in timer0 reference and the
442 * other in timer1 reference, this function considers only the timestamp in
445 * Returns timestamp value.
447 ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf)
453 /* Timestamps are saved in little endian at the beginning of the packet
454 * buffer following the layout:
456 * DWORD: | 0 | 1 | 2 | 3 |
457 * Field: | Timer1 SYSTIML | Timer1 SYSTIMH | Timer0 SYSTIML | Timer0 SYSTIMH |
459 * SYSTIML holds the nanoseconds part while SYSTIMH holds the seconds
460 * part of the timestamp.
462 nsecs = le32_to_cpu(buf[2]);
463 secs = le32_to_cpu(buf[3]);
465 timestamp = ktime_set(secs, nsecs);
467 /* Adjust timestamp for the RX latency based on link speed */
468 switch (adapter->link_speed) {
470 adjust = IGC_I225_RX_LATENCY_10;
473 adjust = IGC_I225_RX_LATENCY_100;
476 adjust = IGC_I225_RX_LATENCY_1000;
479 adjust = IGC_I225_RX_LATENCY_2500;
483 netdev_warn_once(adapter->netdev, "Imprecise timestamp\n");
487 return ktime_sub_ns(timestamp, adjust);
490 static void igc_ptp_disable_rx_timestamp(struct igc_adapter *adapter)
492 struct igc_hw *hw = &adapter->hw;
496 wr32(IGC_TSYNCRXCTL, 0);
498 for (i = 0; i < adapter->num_rx_queues; i++) {
499 val = rd32(IGC_SRRCTL(i));
500 val &= ~IGC_SRRCTL_TIMESTAMP;
501 wr32(IGC_SRRCTL(i), val);
504 val = rd32(IGC_RXPBS);
505 val &= ~IGC_RXPBS_CFG_TS_EN;
506 wr32(IGC_RXPBS, val);
509 static void igc_ptp_enable_rx_timestamp(struct igc_adapter *adapter)
511 struct igc_hw *hw = &adapter->hw;
515 val = rd32(IGC_RXPBS);
516 val |= IGC_RXPBS_CFG_TS_EN;
517 wr32(IGC_RXPBS, val);
519 for (i = 0; i < adapter->num_rx_queues; i++) {
520 val = rd32(IGC_SRRCTL(i));
521 /* FIXME: For now, only support retrieving RX timestamps from
524 val |= IGC_SRRCTL_TIMER1SEL(0) | IGC_SRRCTL_TIMER0SEL(0) |
525 IGC_SRRCTL_TIMESTAMP;
526 wr32(IGC_SRRCTL(i), val);
529 val = IGC_TSYNCRXCTL_ENABLED | IGC_TSYNCRXCTL_TYPE_ALL |
530 IGC_TSYNCRXCTL_RXSYNSIG;
531 wr32(IGC_TSYNCRXCTL, val);
534 static void igc_ptp_disable_tx_timestamp(struct igc_adapter *adapter)
536 struct igc_hw *hw = &adapter->hw;
538 wr32(IGC_TSYNCTXCTL, 0);
541 static void igc_ptp_enable_tx_timestamp(struct igc_adapter *adapter)
543 struct igc_hw *hw = &adapter->hw;
545 wr32(IGC_TSYNCTXCTL, IGC_TSYNCTXCTL_ENABLED | IGC_TSYNCTXCTL_TXSYNSIG);
547 /* Read TXSTMP registers to discard any timestamp previously stored. */
553 * igc_ptp_set_timestamp_mode - setup hardware for timestamping
554 * @adapter: networking device structure
555 * @config: hwtstamp configuration
557 * Return: 0 in case of success, negative errno code otherwise.
559 static int igc_ptp_set_timestamp_mode(struct igc_adapter *adapter,
560 struct hwtstamp_config *config)
562 switch (config->tx_type) {
563 case HWTSTAMP_TX_OFF:
564 igc_ptp_disable_tx_timestamp(adapter);
567 igc_ptp_enable_tx_timestamp(adapter);
573 switch (config->rx_filter) {
574 case HWTSTAMP_FILTER_NONE:
575 igc_ptp_disable_rx_timestamp(adapter);
577 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
578 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
579 case HWTSTAMP_FILTER_PTP_V2_EVENT:
580 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
581 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
582 case HWTSTAMP_FILTER_PTP_V2_SYNC:
583 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
584 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
585 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
586 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
587 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
588 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
589 case HWTSTAMP_FILTER_NTP_ALL:
590 case HWTSTAMP_FILTER_ALL:
591 igc_ptp_enable_rx_timestamp(adapter);
592 config->rx_filter = HWTSTAMP_FILTER_ALL;
601 static void igc_ptp_tx_timeout(struct igc_adapter *adapter)
603 struct igc_hw *hw = &adapter->hw;
605 dev_kfree_skb_any(adapter->ptp_tx_skb);
606 adapter->ptp_tx_skb = NULL;
607 adapter->tx_hwtstamp_timeouts++;
608 clear_bit_unlock(__IGC_PTP_TX_IN_PROGRESS, &adapter->state);
609 /* Clear the tx valid bit in TSYNCTXCTL register to enable interrupt. */
611 netdev_warn(adapter->netdev, "Tx timestamp timeout\n");
614 void igc_ptp_tx_hang(struct igc_adapter *adapter)
616 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
619 if (!test_bit(__IGC_PTP_TX_IN_PROGRESS, &adapter->state))
622 /* If we haven't received a timestamp within the timeout, it is
623 * reasonable to assume that it will never occur, so we can unlock the
624 * timestamp bit when this occurs.
627 cancel_work_sync(&adapter->ptp_tx_work);
628 igc_ptp_tx_timeout(adapter);
633 * igc_ptp_tx_hwtstamp - utility function which checks for TX time stamp
634 * @adapter: Board private structure
636 * If we were asked to do hardware stamping and such a time stamp is
637 * available, then it must have been for this skb here because we only
638 * allow only one such packet into the queue.
640 static void igc_ptp_tx_hwtstamp(struct igc_adapter *adapter)
642 struct sk_buff *skb = adapter->ptp_tx_skb;
643 struct skb_shared_hwtstamps shhwtstamps;
644 struct igc_hw *hw = &adapter->hw;
648 if (WARN_ON_ONCE(!skb))
651 regval = rd32(IGC_TXSTMPL);
652 regval |= (u64)rd32(IGC_TXSTMPH) << 32;
653 igc_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
655 switch (adapter->link_speed) {
657 adjust = IGC_I225_TX_LATENCY_10;
660 adjust = IGC_I225_TX_LATENCY_100;
663 adjust = IGC_I225_TX_LATENCY_1000;
666 adjust = IGC_I225_TX_LATENCY_2500;
670 shhwtstamps.hwtstamp =
671 ktime_add_ns(shhwtstamps.hwtstamp, adjust);
673 /* Clear the lock early before calling skb_tstamp_tx so that
674 * applications are not woken up before the lock bit is clear. We use
675 * a copy of the skb pointer to ensure other threads can't change it
676 * while we're notifying the stack.
678 adapter->ptp_tx_skb = NULL;
679 clear_bit_unlock(__IGC_PTP_TX_IN_PROGRESS, &adapter->state);
681 /* Notify the stack and free the skb after we've unlocked */
682 skb_tstamp_tx(skb, &shhwtstamps);
683 dev_kfree_skb_any(skb);
688 * @work: pointer to work struct
690 * This work function polls the TSYNCTXCTL valid bit to determine when a
691 * timestamp has been taken for the current stored skb.
693 static void igc_ptp_tx_work(struct work_struct *work)
695 struct igc_adapter *adapter = container_of(work, struct igc_adapter,
697 struct igc_hw *hw = &adapter->hw;
700 if (!test_bit(__IGC_PTP_TX_IN_PROGRESS, &adapter->state))
703 tsynctxctl = rd32(IGC_TSYNCTXCTL);
704 if (WARN_ON_ONCE(!(tsynctxctl & IGC_TSYNCTXCTL_TXTT_0)))
707 igc_ptp_tx_hwtstamp(adapter);
711 * igc_ptp_set_ts_config - set hardware time stamping config
712 * @netdev: network interface device structure
713 * @ifr: interface request data
716 int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr)
718 struct igc_adapter *adapter = netdev_priv(netdev);
719 struct hwtstamp_config config;
722 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
725 err = igc_ptp_set_timestamp_mode(adapter, &config);
729 /* save these settings for future reference */
730 memcpy(&adapter->tstamp_config, &config,
731 sizeof(adapter->tstamp_config));
733 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
738 * igc_ptp_get_ts_config - get hardware time stamping config
739 * @netdev: network interface device structure
740 * @ifr: interface request data
742 * Get the hwtstamp_config settings to return to the user. Rather than attempt
743 * to deconstruct the settings from the registers, just return a shadow copy
744 * of the last known settings.
746 int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr)
748 struct igc_adapter *adapter = netdev_priv(netdev);
749 struct hwtstamp_config *config = &adapter->tstamp_config;
751 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
755 /* The two conditions below must be met for cross timestamping via
758 * 1. We have an way to convert the timestamps in the PTM messages
759 * to something related to the system clocks (right now, only
760 * X86 systems with support for the Always Running Timer allow that);
762 * 2. We have PTM enabled in the path from the device to the PCIe root port.
764 static bool igc_is_crosststamp_supported(struct igc_adapter *adapter)
766 if (!IS_ENABLED(CONFIG_X86_TSC))
769 /* FIXME: it was noticed that enabling support for PCIe PTM in
770 * some i225-V models could cause lockups when bringing the
771 * interface up/down. There should be no downsides to
772 * disabling crosstimestamping support for i225-V, as it
773 * doesn't have any PTP support. That way we gain some time
774 * while root causing the issue.
776 if (adapter->pdev->device == IGC_DEV_ID_I225_V)
779 return pcie_ptm_enabled(adapter->pdev);
782 static struct system_counterval_t igc_device_tstamp_to_system(u64 tstamp)
784 #if IS_ENABLED(CONFIG_X86_TSC) && !defined(CONFIG_UML)
785 return convert_art_ns_to_tsc(tstamp);
787 return (struct system_counterval_t) { };
791 static void igc_ptm_log_error(struct igc_adapter *adapter, u32 ptm_stat)
793 struct net_device *netdev = adapter->netdev;
796 case IGC_PTM_STAT_RET_ERR:
797 netdev_err(netdev, "PTM Error: Root port timeout\n");
799 case IGC_PTM_STAT_BAD_PTM_RES:
800 netdev_err(netdev, "PTM Error: Bad response, PTM Response Data expected\n");
802 case IGC_PTM_STAT_T4M1_OVFL:
803 netdev_err(netdev, "PTM Error: T4 minus T1 overflow\n");
805 case IGC_PTM_STAT_ADJUST_1ST:
806 netdev_err(netdev, "PTM Error: 1588 timer adjusted during first PTM cycle\n");
808 case IGC_PTM_STAT_ADJUST_CYC:
809 netdev_err(netdev, "PTM Error: 1588 timer adjusted during non-first PTM cycle\n");
812 netdev_err(netdev, "PTM Error: Unknown error (%#x)\n", ptm_stat);
817 static int igc_phc_get_syncdevicetime(ktime_t *device,
818 struct system_counterval_t *system,
821 u32 stat, t2_curr_h, t2_curr_l, ctrl;
822 struct igc_adapter *adapter = ctx;
823 struct igc_hw *hw = &adapter->hw;
824 int err, count = 100;
827 /* Get a snapshot of system clocks to use as historic value. */
828 ktime_get_snapshot(&adapter->snapshot);
831 /* Doing this in a loop because in the event of a
832 * badly timed (ha!) system clock adjustment, we may
833 * get PTM errors from the PCI root, but these errors
834 * are transitory. Repeating the process returns valid
838 /* To "manually" start the PTM cycle we need to clear and
839 * then set again the TRIG bit.
841 ctrl = rd32(IGC_PTM_CTRL);
842 ctrl &= ~IGC_PTM_CTRL_TRIG;
843 wr32(IGC_PTM_CTRL, ctrl);
844 ctrl |= IGC_PTM_CTRL_TRIG;
845 wr32(IGC_PTM_CTRL, ctrl);
847 /* The cycle only starts "for real" when software notifies
848 * that it has read the registers, this is done by setting
851 wr32(IGC_PTM_STAT, IGC_PTM_STAT_VALID);
853 err = readx_poll_timeout(rd32, IGC_PTM_STAT, stat,
854 stat, IGC_PTM_STAT_SLEEP,
855 IGC_PTM_STAT_TIMEOUT);
857 netdev_err(adapter->netdev, "Timeout reading IGC_PTM_STAT register\n");
861 if ((stat & IGC_PTM_STAT_VALID) == IGC_PTM_STAT_VALID)
864 if (stat & ~IGC_PTM_STAT_VALID) {
865 /* An error occurred, log it. */
866 igc_ptm_log_error(adapter, stat);
867 /* The STAT register is write-1-to-clear (W1C),
868 * so write the previous error status to clear it.
870 wr32(IGC_PTM_STAT, stat);
876 netdev_err(adapter->netdev, "Exceeded number of tries for PTM cycle\n");
880 t1 = ktime_set(rd32(IGC_PTM_T1_TIM0_H), rd32(IGC_PTM_T1_TIM0_L));
882 t2_curr_l = rd32(IGC_PTM_CURR_T2_L);
883 t2_curr_h = rd32(IGC_PTM_CURR_T2_H);
885 /* FIXME: When the register that tells the endianness of the
886 * PTM registers are implemented, check them here and add the
887 * appropriate conversion.
889 t2_curr_h = swab32(t2_curr_h);
891 t2_curr = ((s64)t2_curr_h << 32 | t2_curr_l);
894 *system = igc_device_tstamp_to_system(t2_curr);
899 static int igc_ptp_getcrosststamp(struct ptp_clock_info *ptp,
900 struct system_device_crosststamp *cts)
902 struct igc_adapter *adapter = container_of(ptp, struct igc_adapter,
905 return get_device_system_crosststamp(igc_phc_get_syncdevicetime,
906 adapter, &adapter->snapshot, cts);
910 * igc_ptp_init - Initialize PTP functionality
911 * @adapter: Board private structure
913 * This function is called at device probe to initialize the PTP
916 void igc_ptp_init(struct igc_adapter *adapter)
918 struct net_device *netdev = adapter->netdev;
919 struct igc_hw *hw = &adapter->hw;
922 switch (hw->mac.type) {
924 for (i = 0; i < IGC_N_SDP; i++) {
925 struct ptp_pin_desc *ppd = &adapter->sdp_config[i];
927 snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i);
929 ppd->func = PTP_PF_NONE;
931 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
932 adapter->ptp_caps.owner = THIS_MODULE;
933 adapter->ptp_caps.max_adj = 62499999;
934 adapter->ptp_caps.adjfine = igc_ptp_adjfine_i225;
935 adapter->ptp_caps.adjtime = igc_ptp_adjtime_i225;
936 adapter->ptp_caps.gettimex64 = igc_ptp_gettimex64_i225;
937 adapter->ptp_caps.settime64 = igc_ptp_settime_i225;
938 adapter->ptp_caps.enable = igc_ptp_feature_enable_i225;
939 adapter->ptp_caps.pps = 1;
940 adapter->ptp_caps.pin_config = adapter->sdp_config;
941 adapter->ptp_caps.n_ext_ts = IGC_N_EXTTS;
942 adapter->ptp_caps.n_per_out = IGC_N_PEROUT;
943 adapter->ptp_caps.n_pins = IGC_N_SDP;
944 adapter->ptp_caps.verify = igc_ptp_verify_pin;
946 if (!igc_is_crosststamp_supported(adapter))
949 adapter->ptp_caps.getcrosststamp = igc_ptp_getcrosststamp;
952 adapter->ptp_clock = NULL;
956 spin_lock_init(&adapter->tmreg_lock);
957 INIT_WORK(&adapter->ptp_tx_work, igc_ptp_tx_work);
959 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
960 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
962 adapter->prev_ptp_time = ktime_to_timespec64(ktime_get_real());
963 adapter->ptp_reset_start = ktime_get();
965 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
966 &adapter->pdev->dev);
967 if (IS_ERR(adapter->ptp_clock)) {
968 adapter->ptp_clock = NULL;
969 netdev_err(netdev, "ptp_clock_register failed\n");
970 } else if (adapter->ptp_clock) {
971 netdev_info(netdev, "PHC added\n");
972 adapter->ptp_flags |= IGC_PTP_ENABLED;
976 static void igc_ptp_time_save(struct igc_adapter *adapter)
978 igc_ptp_read(adapter, &adapter->prev_ptp_time);
979 adapter->ptp_reset_start = ktime_get();
982 static void igc_ptp_time_restore(struct igc_adapter *adapter)
984 struct timespec64 ts = adapter->prev_ptp_time;
987 delta = ktime_sub(ktime_get(), adapter->ptp_reset_start);
989 timespec64_add_ns(&ts, ktime_to_ns(delta));
991 igc_ptp_write_i225(adapter, &ts);
994 static void igc_ptm_stop(struct igc_adapter *adapter)
996 struct igc_hw *hw = &adapter->hw;
999 ctrl = rd32(IGC_PTM_CTRL);
1000 ctrl &= ~IGC_PTM_CTRL_EN;
1002 wr32(IGC_PTM_CTRL, ctrl);
1006 * igc_ptp_suspend - Disable PTP work items and prepare for suspend
1007 * @adapter: Board private structure
1009 * This function stops the overflow check work and PTP Tx timestamp work, and
1010 * will prepare the device for OS suspend.
1012 void igc_ptp_suspend(struct igc_adapter *adapter)
1014 if (!(adapter->ptp_flags & IGC_PTP_ENABLED))
1017 cancel_work_sync(&adapter->ptp_tx_work);
1018 dev_kfree_skb_any(adapter->ptp_tx_skb);
1019 adapter->ptp_tx_skb = NULL;
1020 clear_bit_unlock(__IGC_PTP_TX_IN_PROGRESS, &adapter->state);
1022 if (pci_device_is_present(adapter->pdev)) {
1023 igc_ptp_time_save(adapter);
1024 igc_ptm_stop(adapter);
1029 * igc_ptp_stop - Disable PTP device and stop the overflow check.
1030 * @adapter: Board private structure.
1032 * This function stops the PTP support and cancels the delayed work.
1034 void igc_ptp_stop(struct igc_adapter *adapter)
1036 igc_ptp_suspend(adapter);
1038 if (adapter->ptp_clock) {
1039 ptp_clock_unregister(adapter->ptp_clock);
1040 netdev_info(adapter->netdev, "PHC removed\n");
1041 adapter->ptp_flags &= ~IGC_PTP_ENABLED;
1046 * igc_ptp_reset - Re-enable the adapter for PTP following a reset.
1047 * @adapter: Board private structure.
1049 * This function handles the reset work required to re-enable the PTP device.
1051 void igc_ptp_reset(struct igc_adapter *adapter)
1053 struct igc_hw *hw = &adapter->hw;
1054 u32 cycle_ctrl, ctrl;
1055 unsigned long flags;
1058 /* reset the tstamp_config */
1059 igc_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1061 spin_lock_irqsave(&adapter->tmreg_lock, flags);
1063 switch (adapter->hw.mac.type) {
1065 timadj = rd32(IGC_TIMADJ);
1066 timadj |= IGC_TIMADJ_ADJUST_METH;
1067 wr32(IGC_TIMADJ, timadj);
1069 wr32(IGC_TSAUXC, 0x0);
1070 wr32(IGC_TSSDP, 0x0);
1072 IGC_TSICR_INTERRUPTS |
1073 (adapter->pps_sys_wrap_on ? IGC_TSICR_SYS_WRAP : 0));
1074 wr32(IGC_IMS, IGC_IMS_TS);
1076 if (!igc_is_crosststamp_supported(adapter))
1079 wr32(IGC_PCIE_DIG_DELAY, IGC_PCIE_DIG_DELAY_DEFAULT);
1080 wr32(IGC_PCIE_PHY_DELAY, IGC_PCIE_PHY_DELAY_DEFAULT);
1082 cycle_ctrl = IGC_PTM_CYCLE_CTRL_CYC_TIME(IGC_PTM_CYC_TIME_DEFAULT);
1084 wr32(IGC_PTM_CYCLE_CTRL, cycle_ctrl);
1086 ctrl = IGC_PTM_CTRL_EN |
1087 IGC_PTM_CTRL_START_NOW |
1088 IGC_PTM_CTRL_SHRT_CYC(IGC_PTM_SHORT_CYC_DEFAULT) |
1089 IGC_PTM_CTRL_PTM_TO(IGC_PTM_TIMEOUT_DEFAULT) |
1092 wr32(IGC_PTM_CTRL, ctrl);
1094 /* Force the first cycle to run. */
1095 wr32(IGC_PTM_STAT, IGC_PTM_STAT_VALID);
1099 /* No work to do. */
1103 /* Re-initialize the timer. */
1104 if (hw->mac.type == igc_i225) {
1105 igc_ptp_time_restore(adapter);
1107 timecounter_init(&adapter->tc, &adapter->cc,
1108 ktime_to_ns(ktime_get_real()));
1111 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);