1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Intel Corporation. */
7 #define ICE_BYTES_PER_WORD 2
8 #define ICE_BYTES_PER_DWORD 4
10 #include "ice_status.h"
11 #include "ice_hw_autogen.h"
12 #include "ice_osdep.h"
13 #include "ice_controlq.h"
14 #include "ice_lan_tx_rx.h"
15 #include "ice_flex_type.h"
16 #include "ice_protocol_type.h"
18 static inline bool ice_is_tc_ena(unsigned long bitmap, u8 tc)
20 return test_bit(tc, &bitmap);
23 static inline u64 round_up_64bit(u64 a, u32 b)
25 return div64_long(((a) + (b) / 2), (b));
28 static inline u32 ice_round_to_num(u32 N, u32 R)
30 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
31 ((((N) + (R) - 1) / (R)) * (R)));
34 /* Driver always calls main vsi_handle first */
35 #define ICE_MAIN_VSI_HANDLE 0
37 /* debug masks - set these bits in hw->debug_mask to control output */
38 #define ICE_DBG_INIT BIT_ULL(1)
39 #define ICE_DBG_FW_LOG BIT_ULL(3)
40 #define ICE_DBG_LINK BIT_ULL(4)
41 #define ICE_DBG_PHY BIT_ULL(5)
42 #define ICE_DBG_QCTX BIT_ULL(6)
43 #define ICE_DBG_NVM BIT_ULL(7)
44 #define ICE_DBG_LAN BIT_ULL(8)
45 #define ICE_DBG_FLOW BIT_ULL(9)
46 #define ICE_DBG_SW BIT_ULL(13)
47 #define ICE_DBG_SCHED BIT_ULL(14)
48 #define ICE_DBG_PKG BIT_ULL(16)
49 #define ICE_DBG_RES BIT_ULL(17)
50 #define ICE_DBG_AQ_MSG BIT_ULL(24)
51 #define ICE_DBG_AQ_DESC BIT_ULL(25)
52 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
53 #define ICE_DBG_AQ_CMD BIT_ULL(27)
54 #define ICE_DBG_USER BIT_ULL(31)
59 ICE_CHANGE_LOCK_RES_ID,
60 ICE_GLOBAL_CFG_LOCK_RES_ID
63 /* FW update timeout definitions are in milliseconds */
64 #define ICE_NVM_TIMEOUT 180000
65 #define ICE_CHANGE_LOCK_TIMEOUT 1000
66 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000
68 enum ice_aq_res_access_type {
73 struct ice_driver_ver {
97 enum ice_set_fc_aq_failures {
98 ICE_SET_FC_AQ_FAIL_NONE = 0,
99 ICE_SET_FC_AQ_FAIL_GET,
100 ICE_SET_FC_AQ_FAIL_SET,
101 ICE_SET_FC_AQ_FAIL_UPDATE
104 /* Various MAC types */
111 enum ice_media_type {
112 ICE_MEDIA_UNKNOWN = 0,
125 struct ice_link_status {
126 /* Refer to ice_aq_phy_type for bits definition */
129 u8 topo_media_conflict;
133 u8 lse_ena; /* Link Status Event notification */
139 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
140 * ice_aqc_get_phy_caps structure
142 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
145 /* Different reset sources for which a disable queue AQ call has to be made in
146 * order to clean the Tx scheduler as a part of the reset
148 enum ice_disq_rst_src {
154 /* PHY info such as phy_type, etc... */
155 struct ice_phy_info {
156 struct ice_link_status link_info;
157 struct ice_link_status link_info_old;
160 enum ice_media_type media_type;
164 /* Common HW capabilities for SW use */
165 struct ice_hw_common_caps {
167 /* DCB capabilities */
168 u32 active_tc_bitmap;
172 u16 num_rxq; /* Number/Total Rx queues */
173 u16 rxq_first_id; /* First queue ID for Rx queues */
174 u16 num_txq; /* Number/Total Tx queues */
175 u16 txq_first_id; /* First queue ID for Tx queues */
178 u16 num_msix_vectors;
179 u16 msix_vector_first_id;
181 /* Max MTU for function or device */
184 /* Virtualization support */
185 u8 sr_iov_1_1; /* SR-IOV enabled */
187 /* RSS related capabilities */
188 u16 rss_table_size; /* 512 for PFs and 64 for VFs */
189 u8 rss_table_entry_width; /* RSS Entry width in bits */
194 /* Function specific capabilities */
195 struct ice_hw_func_caps {
196 struct ice_hw_common_caps common_cap;
197 u32 num_allocd_vfs; /* Number of allocated VFs */
198 u32 vf_base_id; /* Logical ID of the first VF */
202 /* Device wide capabilities */
203 struct ice_hw_dev_caps {
204 struct ice_hw_common_caps common_cap;
205 u32 num_vfs_exposed; /* Total number of VFs exposed */
206 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
211 struct ice_mac_info {
212 u8 lan_addr[ETH_ALEN];
213 u8 perm_addr[ETH_ALEN];
216 /* Reset types used to determine which kind of reset was requested. These
217 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
218 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
219 * because its reset source is different than the other types listed.
231 struct ice_bus_info {
236 /* Flow control (FC) parameters */
238 enum ice_fc_mode current_mode; /* FC mode in effect */
239 enum ice_fc_mode req_mode; /* FC mode requested by caller */
242 /* Option ROM version information */
243 struct ice_orom_info {
244 u8 major; /* Major version of OROM */
245 u8 patch; /* Patch version of OROM */
246 u16 build; /* Build version of OROM */
249 /* NVM Information */
250 struct ice_nvm_info {
251 struct ice_orom_info orom; /* Option ROM version info */
252 u32 eetrack; /* NVM data version */
253 u16 sr_words; /* Shadow RAM size in words */
254 u32 flash_size; /* Size of available flash in bytes */
255 u8 major_ver; /* major version of NVM package */
256 u8 minor_ver; /* minor version of dev starter */
257 u8 blank_nvm_mode; /* is NVM empty (no FW present) */
260 #define ICE_NVM_VER_LEN 32
262 /* netlist version information */
263 struct ice_netlist_ver_info {
264 u32 major; /* major high/low */
265 u32 minor; /* minor high/low */
266 u32 type; /* type high/low */
267 u32 rev; /* revision high/low */
268 u32 hash; /* SHA-1 hash word */
269 u16 cust_ver; /* customer version */
272 /* Max number of port to queue branches w.r.t topology */
273 #define ICE_MAX_TRAFFIC_CLASS 8
274 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
276 #define ice_for_each_traffic_class(_i) \
277 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
279 #define ICE_INVAL_TEID 0xFFFFFFFF
281 struct ice_sched_node {
282 struct ice_sched_node *parent;
283 struct ice_sched_node *sibling; /* next sibling in the same layer */
284 struct ice_sched_node **children;
285 struct ice_aqc_txsched_elem_data info;
286 u32 agg_id; /* aggregator group ID */
288 u8 in_use; /* suspended or in use */
289 u8 tx_sched_layer; /* Logical Layer (1-9) */
293 #define ICE_SCHED_NODE_OWNER_LAN 0
296 /* Access Macros for Tx Sched Elements data */
297 #define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid)
299 /* The aggregator type determines if identifier is for a VSI group,
300 * aggregator group, aggregator of queues, or queue group.
303 ICE_AGG_TYPE_UNKNOWN = 0,
305 ICE_AGG_TYPE_AGG, /* aggregator */
310 /* Rate limit types */
313 ICE_MIN_BW, /* for CIR profile */
314 ICE_MAX_BW, /* for EIR profile */
315 ICE_SHARED_BW /* for shared profile */
318 #define ICE_SCHED_MIN_BW 500 /* in Kbps */
319 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
320 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
321 #define ICE_SCHED_DFLT_RL_PROF_ID 0
322 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
323 #define ICE_SCHED_DFLT_BW_WT 1
324 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF
325 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
327 /* Data structure for saving BW information */
335 ICE_BW_TYPE_CNT /* This must be last */
343 struct ice_bw_type_info {
344 DECLARE_BITMAP(bw_t_bitmap, ICE_BW_TYPE_CNT);
346 struct ice_bw cir_bw;
347 struct ice_bw eir_bw;
351 /* VSI queue context structure for given TC */
355 /* bw_t_info saves queue BW information */
356 struct ice_bw_type_info bw_t_info;
359 /* VSI type list entry to locate corresponding VSI/aggregator nodes */
360 struct ice_sched_vsi_info {
361 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
362 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
363 struct list_head list_entry;
364 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
367 /* driver defines the policy */
368 struct ice_sched_tx_policy {
370 u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS];
374 /* CEE or IEEE 802.1Qaz ETS Configuration data */
375 struct ice_dcb_ets_cfg {
379 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
380 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
381 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
384 /* CEE or IEEE 802.1Qaz PFC Configuration data */
385 struct ice_dcb_pfc_cfg {
392 /* CEE or IEEE 802.1Qaz Application Priority data */
393 struct ice_dcb_app_priority_table {
399 #define ICE_MAX_USER_PRIORITY 8
400 #define ICE_DCBX_MAX_APPS 32
401 #define ICE_LLDPDU_SIZE 1500
402 #define ICE_TLV_STATUS_OPER 0x1
403 #define ICE_TLV_STATUS_SYNC 0x2
404 #define ICE_TLV_STATUS_ERR 0x4
405 #define ICE_APP_PROT_ID_FCOE 0x8906
406 #define ICE_APP_PROT_ID_ISCSI 0x0cbc
407 #define ICE_APP_PROT_ID_FIP 0x8914
408 #define ICE_APP_SEL_ETHTYPE 0x1
409 #define ICE_APP_SEL_TCPIP 0x2
410 #define ICE_CEE_APP_SEL_ETHTYPE 0x0
411 #define ICE_CEE_APP_SEL_TCPIP 0x1
413 struct ice_dcbx_cfg {
415 u32 tlv_status; /* CEE mode TLV status */
416 struct ice_dcb_ets_cfg etscfg;
417 struct ice_dcb_ets_cfg etsrec;
418 struct ice_dcb_pfc_cfg pfc;
419 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
421 #define ICE_DCBX_MODE_CEE 0x1
422 #define ICE_DCBX_MODE_IEEE 0x2
424 #define ICE_DCBX_APPS_NON_WILLING 0x1
427 struct ice_port_info {
428 struct ice_sched_node *root; /* Root Node per Port */
429 struct ice_hw *hw; /* back pointer to HW instance */
430 u32 last_node_teid; /* scheduler last node info */
431 u16 sw_id; /* Initial switch ID belongs to port */
434 #define ICE_SCHED_PORT_STATE_INIT 0x0
435 #define ICE_SCHED_PORT_STATE_READY 0x1
437 #define ICE_LPORT_MASK 0xff
438 u16 dflt_tx_vsi_rule_id;
440 u16 dflt_rx_vsi_rule_id;
442 struct ice_fc_info fc;
443 struct ice_mac_info mac;
444 struct ice_phy_info phy;
445 struct mutex sched_lock; /* protect access to TXSched tree */
446 struct ice_sched_node *
447 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
448 /* List contain profile ID(s) and other params per layer */
449 struct list_head rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
450 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
452 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
453 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
454 /* LLDP/DCBX Status */
455 u8 dcbx_status:3; /* see ICE_DCBX_STATUS_DIS */
460 struct ice_switch_info {
461 struct list_head vsi_list_map_head;
462 struct ice_sw_recipe *recp_list;
465 /* FW logging configuration */
466 struct ice_fw_log_evnt {
467 u8 cfg : 4; /* New event enables to configure */
468 u8 cur : 4; /* Current/active event enables */
471 struct ice_fw_log_cfg {
472 u8 cq_en : 1; /* FW logging is enabled via the control queue */
473 u8 uart_en : 1; /* FW logging is enabled via UART for all PFs */
474 u8 actv_evnts; /* Cumulation of currently enabled log events */
476 #define ICE_FW_LOG_EVNT_INFO (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S)
477 #define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S)
478 #define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S)
479 #define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S)
480 struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX];
483 /* Port hardware description */
487 struct ice_aqc_layer_props *layer_info;
488 struct ice_port_info *port_info;
489 u64 debug_mask; /* bitmap for debug mask */
490 enum ice_mac_type mac_type;
495 u16 subsystem_device_id;
496 u16 subsystem_vendor_id;
499 u8 pf_id; /* device profile info */
501 u16 max_burst_size; /* driver sets this value */
503 /* Tx Scheduler values */
504 u16 num_tx_sched_layers;
505 u16 num_tx_sched_phys_layers;
508 u8 sw_entry_point_layer;
509 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
510 struct list_head agg_list; /* lists all aggregator */
512 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
513 u8 evb_veb; /* true for VEB, false for VEPA */
514 u8 reset_ongoing; /* true if HW is in reset, false otherwise */
515 struct ice_bus_info bus;
516 struct ice_nvm_info nvm;
517 struct ice_hw_dev_caps dev_caps; /* device capabilities */
518 struct ice_hw_func_caps func_caps; /* function capabilities */
519 struct ice_netlist_ver_info netlist_ver; /* netlist version info */
521 struct ice_switch_info *switch_info; /* switch filter lists */
523 /* Control Queue info */
524 struct ice_ctl_q_info adminq;
525 struct ice_ctl_q_info mailboxq;
527 u8 api_branch; /* API branch version */
528 u8 api_maj_ver; /* API major version */
529 u8 api_min_ver; /* API minor version */
530 u8 api_patch; /* API patch version */
531 u8 fw_branch; /* firmware branch version */
532 u8 fw_maj_ver; /* firmware major version */
533 u8 fw_min_ver; /* firmware minor version */
534 u8 fw_patch; /* firmware patch version */
535 u32 fw_build; /* firmware build number */
537 struct ice_fw_log_cfg fw_log;
539 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
540 * register. Used for determining the ITR/INTRL granularity during
543 #define ICE_MAX_AGG_BW_200G 0x0
544 #define ICE_MAX_AGG_BW_100G 0X1
545 #define ICE_MAX_AGG_BW_50G 0x2
546 #define ICE_MAX_AGG_BW_25G 0x3
547 /* ITR granularity for different speeds */
548 #define ICE_ITR_GRAN_ABOVE_25 2
549 #define ICE_ITR_GRAN_MAX_25 4
550 /* ITR granularity in 1 us */
552 /* INTRL granularity for different speeds */
553 #define ICE_INTRL_GRAN_ABOVE_25 4
554 #define ICE_INTRL_GRAN_MAX_25 8
555 /* INTRL granularity in 1 us */
558 u8 ucast_shared; /* true if VSIs can share unicast addr */
560 /* Active package version (currently active) */
561 struct ice_pkg_ver active_pkg_ver;
562 u8 active_pkg_name[ICE_PKG_NAME_SIZE];
563 u8 active_pkg_in_nvm;
565 enum ice_aq_err pkg_dwnld_status;
567 /* Driver's package ver - (from the Metadata seg) */
568 struct ice_pkg_ver pkg_ver;
569 u8 pkg_name[ICE_PKG_NAME_SIZE];
571 /* Driver's Ice package version (from the Ice seg) */
572 struct ice_pkg_ver ice_pkg_ver;
573 u8 ice_pkg_name[ICE_PKG_NAME_SIZE];
575 /* Pointer to the ice segment */
578 /* Pointer to allocated copy of pkg memory */
582 /* HW block tables */
583 struct ice_blk_info blk[ICE_BLK_COUNT];
584 struct mutex fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
585 struct list_head fl_profs[ICE_BLK_COUNT];
586 struct mutex rss_locks; /* protect RSS configuration */
587 struct list_head rss_list_head;
590 /* Statistics collected by each port, VSI, VEB, and S-channel */
591 struct ice_eth_stats {
592 u64 rx_bytes; /* gorc */
593 u64 rx_unicast; /* uprc */
594 u64 rx_multicast; /* mprc */
595 u64 rx_broadcast; /* bprc */
596 u64 rx_discards; /* rdpc */
597 u64 rx_unknown_protocol; /* rupp */
598 u64 tx_bytes; /* gotc */
599 u64 tx_unicast; /* uptc */
600 u64 tx_multicast; /* mptc */
601 u64 tx_broadcast; /* bptc */
602 u64 tx_discards; /* tdpc */
603 u64 tx_errors; /* tepc */
606 /* Statistics collected by the MAC */
607 struct ice_hw_port_stats {
608 /* eth stats collected by the port */
609 struct ice_eth_stats eth;
610 /* additional port specific stats */
611 u64 tx_dropped_link_down; /* tdold */
612 u64 crc_errors; /* crcerrs */
613 u64 illegal_bytes; /* illerrc */
614 u64 error_bytes; /* errbc */
615 u64 mac_local_faults; /* mlfc */
616 u64 mac_remote_faults; /* mrfc */
617 u64 rx_len_errors; /* rlec */
618 u64 link_xon_rx; /* lxonrxc */
619 u64 link_xoff_rx; /* lxoffrxc */
620 u64 link_xon_tx; /* lxontxc */
621 u64 link_xoff_tx; /* lxofftxc */
622 u64 priority_xon_rx[8]; /* pxonrxc[8] */
623 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
624 u64 priority_xon_tx[8]; /* pxontxc[8] */
625 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
626 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
627 u64 rx_size_64; /* prc64 */
628 u64 rx_size_127; /* prc127 */
629 u64 rx_size_255; /* prc255 */
630 u64 rx_size_511; /* prc511 */
631 u64 rx_size_1023; /* prc1023 */
632 u64 rx_size_1522; /* prc1522 */
633 u64 rx_size_big; /* prc9522 */
634 u64 rx_undersize; /* ruc */
635 u64 rx_fragments; /* rfc */
636 u64 rx_oversize; /* roc */
637 u64 rx_jabber; /* rjc */
638 u64 tx_size_64; /* ptc64 */
639 u64 tx_size_127; /* ptc127 */
640 u64 tx_size_255; /* ptc255 */
641 u64 tx_size_511; /* ptc511 */
642 u64 tx_size_1023; /* ptc1023 */
643 u64 tx_size_1522; /* ptc1522 */
644 u64 tx_size_big; /* ptc9522 */
647 /* Checksum and Shadow RAM pointers */
648 #define ICE_SR_BOOT_CFG_PTR 0x132
649 #define ICE_NVM_OROM_VER_OFF 0x02
650 #define ICE_SR_PBA_BLOCK_PTR 0x16
651 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
652 #define ICE_SR_NVM_EETRACK_LO 0x2D
653 #define ICE_SR_NVM_EETRACK_HI 0x2E
654 #define ICE_NVM_VER_LO_SHIFT 0
655 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
656 #define ICE_NVM_VER_HI_SHIFT 12
657 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
658 #define ICE_OROM_VER_PATCH_SHIFT 0
659 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT)
660 #define ICE_OROM_VER_BUILD_SHIFT 8
661 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT)
662 #define ICE_OROM_VER_SHIFT 24
663 #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT)
664 #define ICE_SR_PFA_PTR 0x40
665 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
666 #define ICE_SR_WORDS_IN_1KB 512
668 /* Hash redirection LUT for VSI - maximum array size */
669 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4)
671 #endif /* _ICE_TYPE_H_ */