1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018, Intel Corporation. */
4 #include "ice_common.h"
6 #include "ice_adminq_cmd.h"
9 #define ICE_PF_RESET_WAIT_COUNT 300
11 static const char * const ice_link_mode_str_low[] = {
28 [16] = "10GBASE_KR_CR1",
29 [17] = "10G_SFI_AOC_ACC",
33 [21] = "25GBASE_CR_S",
38 [26] = "25GBASE_KR_S",
40 [28] = "25G_AUI_AOC_ACC",
46 [34] = "40G_XLAUI_AOC_ACC",
52 [40] = "50G_LAUI2_AOC_ACC",
54 [42] = "50G_AUI2_AOC_ACC",
60 [48] = "50GBASE_KR_PAM4",
61 [49] = "50G_AUI1_AOC_ACC",
63 [51] = "100GBASE_CR4",
64 [52] = "100GBASE_SR4",
65 [53] = "100GBASE_LR4",
66 [54] = "100GBASE_KR4",
67 [55] = "100G_CAUI4_AOC_ACC",
69 [57] = "100G_AUI4_AOC_ACC",
71 [59] = "100GBASE_CR_PAM4",
72 [60] = "100GBASE_KR_PAM4",
73 [61] = "100GBASE_CP2",
74 [62] = "100GBASE_SR2",
78 static const char * const ice_link_mode_str_high[] = {
79 [0] = "100GBASE_KR2_PAM4",
80 [1] = "100G_CAUI2_AOC_ACC",
82 [3] = "100G_AUI2_AOC_ACC",
87 * ice_dump_phy_type - helper function to dump phy_type
88 * @hw: pointer to the HW structure
89 * @low: 64 bit value for phy_type_low
90 * @high: 64 bit value for phy_type_high
91 * @prefix: prefix string to differentiate multiple dumps
94 ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix)
96 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, low);
98 for (u32 i = 0; i < BITS_PER_TYPE(typeof(low)); i++) {
100 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n",
101 prefix, i, ice_link_mode_str_low[i]);
104 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, high);
106 for (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) {
107 if (high & BIT_ULL(i))
108 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n",
109 prefix, i, ice_link_mode_str_high[i]);
114 * ice_set_mac_type - Sets MAC type
115 * @hw: pointer to the HW structure
117 * This function sets the MAC type of the adapter based on the
118 * vendor ID and device ID stored in the HW structure.
120 static int ice_set_mac_type(struct ice_hw *hw)
122 if (hw->vendor_id != PCI_VENDOR_ID_INTEL)
125 switch (hw->device_id) {
126 case ICE_DEV_ID_E810C_BACKPLANE:
127 case ICE_DEV_ID_E810C_QSFP:
128 case ICE_DEV_ID_E810C_SFP:
129 case ICE_DEV_ID_E810_XXV_BACKPLANE:
130 case ICE_DEV_ID_E810_XXV_QSFP:
131 case ICE_DEV_ID_E810_XXV_SFP:
132 hw->mac_type = ICE_MAC_E810;
134 case ICE_DEV_ID_E823C_10G_BASE_T:
135 case ICE_DEV_ID_E823C_BACKPLANE:
136 case ICE_DEV_ID_E823C_QSFP:
137 case ICE_DEV_ID_E823C_SFP:
138 case ICE_DEV_ID_E823C_SGMII:
139 case ICE_DEV_ID_E822C_10G_BASE_T:
140 case ICE_DEV_ID_E822C_BACKPLANE:
141 case ICE_DEV_ID_E822C_QSFP:
142 case ICE_DEV_ID_E822C_SFP:
143 case ICE_DEV_ID_E822C_SGMII:
144 case ICE_DEV_ID_E822L_10G_BASE_T:
145 case ICE_DEV_ID_E822L_BACKPLANE:
146 case ICE_DEV_ID_E822L_SFP:
147 case ICE_DEV_ID_E822L_SGMII:
148 case ICE_DEV_ID_E823L_10G_BASE_T:
149 case ICE_DEV_ID_E823L_1GBE:
150 case ICE_DEV_ID_E823L_BACKPLANE:
151 case ICE_DEV_ID_E823L_QSFP:
152 case ICE_DEV_ID_E823L_SFP:
153 hw->mac_type = ICE_MAC_GENERIC;
156 hw->mac_type = ICE_MAC_UNKNOWN;
160 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type);
166 * @hw: pointer to the hardware structure
168 * returns true if the device is E810 based, false if not.
170 bool ice_is_e810(struct ice_hw *hw)
172 return hw->mac_type == ICE_MAC_E810;
177 * @hw: pointer to the hardware structure
179 * returns true if the device is E810T based, false if not.
181 bool ice_is_e810t(struct ice_hw *hw)
183 switch (hw->device_id) {
184 case ICE_DEV_ID_E810C_SFP:
185 switch (hw->subsystem_device_id) {
186 case ICE_SUBDEV_ID_E810T:
187 case ICE_SUBDEV_ID_E810T2:
188 case ICE_SUBDEV_ID_E810T3:
189 case ICE_SUBDEV_ID_E810T4:
190 case ICE_SUBDEV_ID_E810T6:
191 case ICE_SUBDEV_ID_E810T7:
195 case ICE_DEV_ID_E810C_QSFP:
196 switch (hw->subsystem_device_id) {
197 case ICE_SUBDEV_ID_E810T2:
198 case ICE_SUBDEV_ID_E810T3:
199 case ICE_SUBDEV_ID_E810T5:
212 * @hw: pointer to the hardware structure
214 * returns true if the device is E823-L or E823-C based, false if not.
216 bool ice_is_e823(struct ice_hw *hw)
218 switch (hw->device_id) {
219 case ICE_DEV_ID_E823L_BACKPLANE:
220 case ICE_DEV_ID_E823L_SFP:
221 case ICE_DEV_ID_E823L_10G_BASE_T:
222 case ICE_DEV_ID_E823L_1GBE:
223 case ICE_DEV_ID_E823L_QSFP:
224 case ICE_DEV_ID_E823C_BACKPLANE:
225 case ICE_DEV_ID_E823C_QSFP:
226 case ICE_DEV_ID_E823C_SFP:
227 case ICE_DEV_ID_E823C_10G_BASE_T:
228 case ICE_DEV_ID_E823C_SGMII:
236 * ice_clear_pf_cfg - Clear PF configuration
237 * @hw: pointer to the hardware structure
239 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
240 * configuration, flow director filters, etc.).
242 int ice_clear_pf_cfg(struct ice_hw *hw)
244 struct ice_aq_desc desc;
246 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
248 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
252 * ice_aq_manage_mac_read - manage MAC address read command
253 * @hw: pointer to the HW struct
254 * @buf: a virtual buffer to hold the manage MAC read response
255 * @buf_size: Size of the virtual buffer
256 * @cd: pointer to command details structure or NULL
258 * This function is used to return per PF station MAC address (0x0107).
259 * NOTE: Upon successful completion of this command, MAC address information
260 * is returned in user specified buffer. Please interpret user specified
261 * buffer as "manage_mac_read" response.
262 * Response such as various MAC addresses are stored in HW struct (port.mac)
263 * ice_discover_dev_caps is expected to be called before this function is
267 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
268 struct ice_sq_cd *cd)
270 struct ice_aqc_manage_mac_read_resp *resp;
271 struct ice_aqc_manage_mac_read *cmd;
272 struct ice_aq_desc desc;
277 cmd = &desc.params.mac_read;
279 if (buf_size < sizeof(*resp))
282 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
284 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
289 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
291 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
292 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
296 /* A single port can report up to two (LAN and WoL) addresses */
297 for (i = 0; i < cmd->num_addr; i++)
298 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
299 ether_addr_copy(hw->port_info->mac.lan_addr,
301 ether_addr_copy(hw->port_info->mac.perm_addr,
310 * ice_aq_get_phy_caps - returns PHY capabilities
311 * @pi: port information structure
312 * @qual_mods: report qualified modules
313 * @report_mode: report mode capabilities
314 * @pcaps: structure for PHY capabilities to be filled
315 * @cd: pointer to command details structure or NULL
317 * Returns the various PHY capabilities supported on the Port (0x0600)
320 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
321 struct ice_aqc_get_phy_caps_data *pcaps,
322 struct ice_sq_cd *cd)
324 struct ice_aqc_get_phy_caps *cmd;
325 u16 pcaps_size = sizeof(*pcaps);
326 struct ice_aq_desc desc;
331 cmd = &desc.params.get_phy;
333 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
337 if (report_mode == ICE_AQC_REPORT_DFLT_CFG &&
338 !ice_fw_supports_report_dflt_cfg(hw))
341 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
344 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM);
346 cmd->param0 |= cpu_to_le16(report_mode);
347 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd);
349 ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n");
351 switch (report_mode) {
352 case ICE_AQC_REPORT_TOPO_CAP_MEDIA:
353 prefix = "phy_caps_media";
355 case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA:
356 prefix = "phy_caps_no_media";
358 case ICE_AQC_REPORT_ACTIVE_CFG:
359 prefix = "phy_caps_active";
361 case ICE_AQC_REPORT_DFLT_CFG:
362 prefix = "phy_caps_default";
365 prefix = "phy_caps_invalid";
368 ice_dump_phy_type(hw, le64_to_cpu(pcaps->phy_type_low),
369 le64_to_cpu(pcaps->phy_type_high), prefix);
371 ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n",
372 prefix, report_mode);
373 ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps);
374 ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix,
375 pcaps->low_power_ctrl_an);
376 ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix,
378 ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix,
380 ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix,
381 pcaps->link_fec_options);
382 ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n",
383 prefix, pcaps->module_compliance_enforcement);
384 ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n",
385 prefix, pcaps->extended_compliance_code);
386 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix,
387 pcaps->module_type[0]);
388 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix,
389 pcaps->module_type[1]);
390 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix,
391 pcaps->module_type[2]);
393 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) {
394 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low);
395 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high);
396 memcpy(pi->phy.link_info.module_type, &pcaps->module_type,
397 sizeof(pi->phy.link_info.module_type));
404 * ice_aq_get_link_topo_handle - get link topology node return status
405 * @pi: port information structure
406 * @node_type: requested node type
407 * @cd: pointer to command details structure or NULL
409 * Get link topology node return status for specified node type (0x06E0)
411 * Node type cage can be used to determine if cage is present. If AQC
412 * returns error (ENOENT), then no cage present. If no cage present, then
413 * connection type is backplane or BASE-T.
416 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type,
417 struct ice_sq_cd *cd)
419 struct ice_aqc_get_link_topo *cmd;
420 struct ice_aq_desc desc;
422 cmd = &desc.params.get_link_topo;
424 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
426 cmd->addr.topo_params.node_type_ctx =
427 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<
428 ICE_AQC_LINK_TOPO_NODE_CTX_S);
431 cmd->addr.topo_params.node_type_ctx |=
432 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type);
434 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
438 * ice_is_media_cage_present
439 * @pi: port information structure
441 * Returns true if media cage is present, else false. If no cage, then
442 * media type is backplane or BASE-T.
444 static bool ice_is_media_cage_present(struct ice_port_info *pi)
446 /* Node type cage can be used to determine if cage is present. If AQC
447 * returns error (ENOENT), then no cage present. If no cage present then
448 * connection type is backplane or BASE-T.
450 return !ice_aq_get_link_topo_handle(pi,
451 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE,
456 * ice_get_media_type - Gets media type
457 * @pi: port information structure
459 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
461 struct ice_link_status *hw_link_info;
464 return ICE_MEDIA_UNKNOWN;
466 hw_link_info = &pi->phy.link_info;
467 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
468 /* If more than one media type is selected, report unknown */
469 return ICE_MEDIA_UNKNOWN;
471 if (hw_link_info->phy_type_low) {
472 /* 1G SGMII is a special case where some DA cable PHYs
473 * may show this as an option when it really shouldn't
474 * be since SGMII is meant to be between a MAC and a PHY
475 * in a backplane. Try to detect this case and handle it
477 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII &&
478 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==
479 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE ||
480 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==
481 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE))
484 switch (hw_link_info->phy_type_low) {
485 case ICE_PHY_TYPE_LOW_1000BASE_SX:
486 case ICE_PHY_TYPE_LOW_1000BASE_LX:
487 case ICE_PHY_TYPE_LOW_10GBASE_SR:
488 case ICE_PHY_TYPE_LOW_10GBASE_LR:
489 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
490 case ICE_PHY_TYPE_LOW_25GBASE_SR:
491 case ICE_PHY_TYPE_LOW_25GBASE_LR:
492 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
493 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
494 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
495 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
496 case ICE_PHY_TYPE_LOW_50GBASE_SR:
497 case ICE_PHY_TYPE_LOW_50GBASE_FR:
498 case ICE_PHY_TYPE_LOW_50GBASE_LR:
499 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
500 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
501 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
502 case ICE_PHY_TYPE_LOW_100GBASE_DR:
503 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
504 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
505 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
506 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
507 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
508 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
509 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
510 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
511 return ICE_MEDIA_FIBER;
512 case ICE_PHY_TYPE_LOW_100BASE_TX:
513 case ICE_PHY_TYPE_LOW_1000BASE_T:
514 case ICE_PHY_TYPE_LOW_2500BASE_T:
515 case ICE_PHY_TYPE_LOW_5GBASE_T:
516 case ICE_PHY_TYPE_LOW_10GBASE_T:
517 case ICE_PHY_TYPE_LOW_25GBASE_T:
518 return ICE_MEDIA_BASET;
519 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
520 case ICE_PHY_TYPE_LOW_25GBASE_CR:
521 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
522 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
523 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
524 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
525 case ICE_PHY_TYPE_LOW_50GBASE_CP:
526 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
527 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
528 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
530 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
531 case ICE_PHY_TYPE_LOW_40G_XLAUI:
532 case ICE_PHY_TYPE_LOW_50G_LAUI2:
533 case ICE_PHY_TYPE_LOW_50G_AUI2:
534 case ICE_PHY_TYPE_LOW_50G_AUI1:
535 case ICE_PHY_TYPE_LOW_100G_AUI4:
536 case ICE_PHY_TYPE_LOW_100G_CAUI4:
537 if (ice_is_media_cage_present(pi))
540 case ICE_PHY_TYPE_LOW_1000BASE_KX:
541 case ICE_PHY_TYPE_LOW_2500BASE_KX:
542 case ICE_PHY_TYPE_LOW_2500BASE_X:
543 case ICE_PHY_TYPE_LOW_5GBASE_KR:
544 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
545 case ICE_PHY_TYPE_LOW_25GBASE_KR:
546 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
547 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
548 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
549 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
550 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
551 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
552 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
553 return ICE_MEDIA_BACKPLANE;
556 switch (hw_link_info->phy_type_high) {
557 case ICE_PHY_TYPE_HIGH_100G_AUI2:
558 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
559 if (ice_is_media_cage_present(pi))
562 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
563 return ICE_MEDIA_BACKPLANE;
564 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
565 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
566 return ICE_MEDIA_FIBER;
569 return ICE_MEDIA_UNKNOWN;
573 * ice_aq_get_link_info
574 * @pi: port information structure
575 * @ena_lse: enable/disable LinkStatusEvent reporting
576 * @link: pointer to link status structure - optional
577 * @cd: pointer to command details structure or NULL
579 * Get Link Status (0x607). Returns the link status of the adapter.
582 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
583 struct ice_link_status *link, struct ice_sq_cd *cd)
585 struct ice_aqc_get_link_status_data link_data = { 0 };
586 struct ice_aqc_get_link_status *resp;
587 struct ice_link_status *li_old, *li;
588 enum ice_media_type *hw_media_type;
589 struct ice_fc_info *hw_fc_info;
590 bool tx_pause, rx_pause;
591 struct ice_aq_desc desc;
599 li_old = &pi->phy.link_info_old;
600 hw_media_type = &pi->phy.media_type;
601 li = &pi->phy.link_info;
602 hw_fc_info = &pi->fc;
604 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
605 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
606 resp = &desc.params.get_link_status;
607 resp->cmd_flags = cpu_to_le16(cmd_flags);
608 resp->lport_num = pi->lport;
610 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);
615 /* save off old link status information */
618 /* update current link status information */
619 li->link_speed = le16_to_cpu(link_data.link_speed);
620 li->phy_type_low = le64_to_cpu(link_data.phy_type_low);
621 li->phy_type_high = le64_to_cpu(link_data.phy_type_high);
622 *hw_media_type = ice_get_media_type(pi);
623 li->link_info = link_data.link_info;
624 li->link_cfg_err = link_data.link_cfg_err;
625 li->an_info = link_data.an_info;
626 li->ext_info = link_data.ext_info;
627 li->max_frame_size = le16_to_cpu(link_data.max_frame_size);
628 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
629 li->topo_media_conflict = link_data.topo_media_conflict;
630 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
631 ICE_AQ_CFG_PACING_TYPE_M);
634 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
635 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
636 if (tx_pause && rx_pause)
637 hw_fc_info->current_mode = ICE_FC_FULL;
639 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
641 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
643 hw_fc_info->current_mode = ICE_FC_NONE;
645 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED));
647 ice_debug(hw, ICE_DBG_LINK, "get link info\n");
648 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed);
649 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
650 (unsigned long long)li->phy_type_low);
651 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
652 (unsigned long long)li->phy_type_high);
653 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type);
654 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info);
655 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err);
656 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info);
657 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info);
658 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info);
659 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena);
660 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n",
662 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing);
664 /* save link status information */
668 /* flag cleared so calling functions don't call AQ again */
669 pi->phy.get_link_info = false;
675 * ice_fill_tx_timer_and_fc_thresh
676 * @hw: pointer to the HW struct
677 * @cmd: pointer to MAC cfg structure
679 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command
683 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,
684 struct ice_aqc_set_mac_cfg *cmd)
686 u16 fc_thres_val, tx_timer_val;
689 /* We read back the transmit timer and FC threshold value of
690 * LFC. Thus, we will use index =
691 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
693 * Also, because we are operating on transmit timer and FC
694 * threshold of LFC, we don't turn on any bit in tx_tmr_priority
696 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
698 /* Retrieve the transmit timer */
699 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
701 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
702 cmd->tx_tmr_value = cpu_to_le16(tx_timer_val);
704 /* Retrieve the FC threshold */
705 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
706 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M;
708 cmd->fc_refresh_threshold = cpu_to_le16(fc_thres_val);
713 * @hw: pointer to the HW struct
714 * @max_frame_size: Maximum Frame Size to be supported
715 * @cd: pointer to command details structure or NULL
717 * Set MAC configuration (0x0603)
720 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
722 struct ice_aqc_set_mac_cfg *cmd;
723 struct ice_aq_desc desc;
725 cmd = &desc.params.set_mac_cfg;
727 if (max_frame_size == 0)
730 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
732 cmd->max_frame_size = cpu_to_le16(max_frame_size);
734 ice_fill_tx_timer_and_fc_thresh(hw, cmd);
736 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
740 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
741 * @hw: pointer to the HW struct
743 static int ice_init_fltr_mgmt_struct(struct ice_hw *hw)
745 struct ice_switch_info *sw;
748 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw),
749 sizeof(*hw->switch_info), GFP_KERNEL);
750 sw = hw->switch_info;
755 INIT_LIST_HEAD(&sw->vsi_list_map_head);
756 sw->prof_res_bm_init = 0;
758 status = ice_init_def_sw_recp(hw);
760 devm_kfree(ice_hw_to_dev(hw), hw->switch_info);
767 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
768 * @hw: pointer to the HW struct
770 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
772 struct ice_switch_info *sw = hw->switch_info;
773 struct ice_vsi_list_map_info *v_pos_map;
774 struct ice_vsi_list_map_info *v_tmp_map;
775 struct ice_sw_recipe *recps;
778 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
780 list_del(&v_pos_map->list_entry);
781 devm_kfree(ice_hw_to_dev(hw), v_pos_map);
783 recps = sw->recp_list;
784 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
785 struct ice_recp_grp_entry *rg_entry, *tmprg_entry;
787 recps[i].root_rid = i;
788 list_for_each_entry_safe(rg_entry, tmprg_entry,
789 &recps[i].rg_list, l_entry) {
790 list_del(&rg_entry->l_entry);
791 devm_kfree(ice_hw_to_dev(hw), rg_entry);
794 if (recps[i].adv_rule) {
795 struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
796 struct ice_adv_fltr_mgmt_list_entry *lst_itr;
798 mutex_destroy(&recps[i].filt_rule_lock);
799 list_for_each_entry_safe(lst_itr, tmp_entry,
800 &recps[i].filt_rules,
802 list_del(&lst_itr->list_entry);
803 devm_kfree(ice_hw_to_dev(hw), lst_itr->lkups);
804 devm_kfree(ice_hw_to_dev(hw), lst_itr);
807 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
809 mutex_destroy(&recps[i].filt_rule_lock);
810 list_for_each_entry_safe(lst_itr, tmp_entry,
811 &recps[i].filt_rules,
813 list_del(&lst_itr->list_entry);
814 devm_kfree(ice_hw_to_dev(hw), lst_itr);
817 devm_kfree(ice_hw_to_dev(hw), recps[i].root_buf);
819 ice_rm_all_sw_replay_rule_info(hw);
820 devm_kfree(ice_hw_to_dev(hw), sw->recp_list);
821 devm_kfree(ice_hw_to_dev(hw), sw);
825 * ice_get_fw_log_cfg - get FW logging configuration
826 * @hw: pointer to the HW struct
828 static int ice_get_fw_log_cfg(struct ice_hw *hw)
830 struct ice_aq_desc desc;
835 size = sizeof(*config) * ICE_AQC_FW_LOG_ID_MAX;
836 config = kzalloc(size, GFP_KERNEL);
840 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging_info);
842 status = ice_aq_send_cmd(hw, &desc, config, size, NULL);
846 /* Save FW logging information into the HW structure */
847 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
850 v = le16_to_cpu(config[i]);
851 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;
852 flgs = (v & ICE_AQC_FW_LOG_EN_M) >> ICE_AQC_FW_LOG_EN_S;
854 if (m < ICE_AQC_FW_LOG_ID_MAX)
855 hw->fw_log.evnts[m].cur = flgs;
865 * ice_cfg_fw_log - configure FW logging
866 * @hw: pointer to the HW struct
867 * @enable: enable certain FW logging events if true, disable all if false
869 * This function enables/disables the FW logging via Rx CQ events and a UART
870 * port based on predetermined configurations. FW logging via the Rx CQ can be
871 * enabled/disabled for individual PF's. However, FW logging via the UART can
872 * only be enabled/disabled for all PFs on the same device.
874 * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in
875 * hw->fw_log need to be set accordingly, e.g. based on user-provided input,
876 * before initializing the device.
878 * When re/configuring FW logging, callers need to update the "cfg" elements of
879 * the hw->fw_log.evnts array with the desired logging event configurations for
880 * modules of interest. When disabling FW logging completely, the callers can
881 * just pass false in the "enable" parameter. On completion, the function will
882 * update the "cur" element of the hw->fw_log.evnts array with the resulting
883 * logging event configurations of the modules that are being re/configured. FW
884 * logging modules that are not part of a reconfiguration operation retain their
887 * Before resetting the device, it is recommended that the driver disables FW
888 * logging before shutting down the control queue. When disabling FW logging
889 * ("enable" = false), the latest configurations of FW logging events stored in
890 * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after
893 * When enabling FW logging to emit log messages via the Rx CQ during the
894 * device's initialization phase, a mechanism alternative to interrupt handlers
895 * needs to be used to extract FW log messages from the Rx CQ periodically and
896 * to prevent the Rx CQ from being full and stalling other types of control
897 * messages from FW to SW. Interrupts are typically disabled during the device's
898 * initialization phase.
900 static int ice_cfg_fw_log(struct ice_hw *hw, bool enable)
902 struct ice_aqc_fw_logging *cmd;
903 u16 i, chgs = 0, len = 0;
904 struct ice_aq_desc desc;
910 if (!hw->fw_log.cq_en && !hw->fw_log.uart_en)
913 /* Disable FW logging only when the control queue is still responsive */
915 (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq)))
918 /* Get current FW log settings */
919 status = ice_get_fw_log_cfg(hw);
923 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging);
924 cmd = &desc.params.fw_logging;
926 /* Indicate which controls are valid */
927 if (hw->fw_log.cq_en)
928 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID;
930 if (hw->fw_log.uart_en)
931 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID;
934 /* Fill in an array of entries with FW logging modules and
935 * logging events being reconfigured.
937 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
940 /* Keep track of enabled event types */
941 actv_evnts |= hw->fw_log.evnts[i].cfg;
943 if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur)
947 data = devm_kcalloc(ice_hw_to_dev(hw),
948 ICE_AQC_FW_LOG_ID_MAX,
955 val = i << ICE_AQC_FW_LOG_ID_S;
956 val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S;
957 data[chgs++] = cpu_to_le16(val);
960 /* Only enable FW logging if at least one module is specified.
961 * If FW logging is currently enabled but all modules are not
962 * enabled to emit log messages, disable FW logging altogether.
965 /* Leave if there is effectively no change */
969 if (hw->fw_log.cq_en)
970 cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN;
972 if (hw->fw_log.uart_en)
973 cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN;
976 len = sizeof(*data) * chgs;
977 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
981 status = ice_aq_send_cmd(hw, &desc, buf, len, NULL);
983 /* Update the current configuration to reflect events enabled.
984 * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW
985 * logging mode is enabled for the device. They do not reflect
986 * actual modules being enabled to emit log messages. So, their
987 * values remain unchanged even when all modules are disabled.
989 u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX;
991 hw->fw_log.actv_evnts = actv_evnts;
992 for (i = 0; i < cnt; i++) {
996 /* When disabling all FW logging events as part
997 * of device's de-initialization, the original
998 * configurations are retained, and can be used
999 * to reconfigure FW logging later if the device
1000 * is re-initialized.
1002 hw->fw_log.evnts[i].cur = 0;
1006 v = le16_to_cpu(data[i]);
1007 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;
1008 hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg;
1013 devm_kfree(ice_hw_to_dev(hw), data);
1020 * @hw: pointer to the HW struct
1021 * @desc: pointer to the AQ message descriptor
1022 * @buf: pointer to the buffer accompanying the AQ message
1024 * Formats a FW Log message and outputs it via the standard driver logs.
1026 void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf)
1028 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg Start ]\n");
1029 ice_debug_array(hw, ICE_DBG_FW_LOG, 16, 1, (u8 *)buf,
1030 le16_to_cpu(desc->datalen));
1031 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg End ]\n");
1035 * ice_get_itr_intrl_gran
1036 * @hw: pointer to the HW struct
1038 * Determines the ITR/INTRL granularities based on the maximum aggregate
1039 * bandwidth according to the device's configuration during power-on.
1041 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
1043 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
1044 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
1045 GL_PWR_MODE_CTL_CAR_MAX_BW_S;
1047 switch (max_agg_bw) {
1048 case ICE_MAX_AGG_BW_200G:
1049 case ICE_MAX_AGG_BW_100G:
1050 case ICE_MAX_AGG_BW_50G:
1051 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
1052 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
1054 case ICE_MAX_AGG_BW_25G:
1055 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
1056 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
1062 * ice_init_hw - main hardware initialization routine
1063 * @hw: pointer to the hardware structure
1065 int ice_init_hw(struct ice_hw *hw)
1067 struct ice_aqc_get_phy_caps_data *pcaps;
1072 /* Set MAC type based on DeviceID */
1073 status = ice_set_mac_type(hw);
1077 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
1078 PF_FUNC_RID_FUNC_NUM_M) >>
1079 PF_FUNC_RID_FUNC_NUM_S;
1081 status = ice_reset(hw, ICE_RESET_PFR);
1085 ice_get_itr_intrl_gran(hw);
1087 status = ice_create_all_ctrlq(hw);
1089 goto err_unroll_cqinit;
1091 /* Enable FW logging. Not fatal if this fails. */
1092 status = ice_cfg_fw_log(hw, true);
1094 ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n");
1096 status = ice_clear_pf_cfg(hw);
1098 goto err_unroll_cqinit;
1100 /* Set bit to enable Flow Director filters */
1101 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
1102 INIT_LIST_HEAD(&hw->fdir_list_head);
1104 ice_clear_pxe_mode(hw);
1106 status = ice_init_nvm(hw);
1108 goto err_unroll_cqinit;
1110 status = ice_get_caps(hw);
1112 goto err_unroll_cqinit;
1115 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw),
1116 sizeof(*hw->port_info),
1118 if (!hw->port_info) {
1120 goto err_unroll_cqinit;
1123 /* set the back pointer to HW */
1124 hw->port_info->hw = hw;
1126 /* Initialize port_info struct with switch configuration data */
1127 status = ice_get_initial_sw_cfg(hw);
1129 goto err_unroll_alloc;
1133 /* init xarray for identifying scheduling nodes uniquely */
1134 xa_init_flags(&hw->port_info->sched_node_ids, XA_FLAGS_ALLOC);
1136 /* Query the allocated resources for Tx scheduler */
1137 status = ice_sched_query_res_alloc(hw);
1139 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n");
1140 goto err_unroll_alloc;
1142 ice_sched_get_psm_clk_freq(hw);
1144 /* Initialize port_info struct with scheduler data */
1145 status = ice_sched_init_port(hw->port_info);
1147 goto err_unroll_sched;
1149 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL);
1152 goto err_unroll_sched;
1155 /* Initialize port_info struct with PHY capabilities */
1156 status = ice_aq_get_phy_caps(hw->port_info, false,
1157 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps,
1159 devm_kfree(ice_hw_to_dev(hw), pcaps);
1161 dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n",
1164 /* Initialize port_info struct with link information */
1165 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
1167 goto err_unroll_sched;
1169 /* need a valid SW entry point to build a Tx tree */
1170 if (!hw->sw_entry_point_layer) {
1171 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
1173 goto err_unroll_sched;
1175 INIT_LIST_HEAD(&hw->agg_list);
1176 /* Initialize max burst size */
1177 if (!hw->max_burst_size)
1178 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
1180 status = ice_init_fltr_mgmt_struct(hw);
1182 goto err_unroll_sched;
1184 /* Get MAC information */
1185 /* A single port can report up to two (LAN and WoL) addresses */
1186 mac_buf = devm_kcalloc(ice_hw_to_dev(hw), 2,
1187 sizeof(struct ice_aqc_manage_mac_read_resp),
1189 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
1193 goto err_unroll_fltr_mgmt_struct;
1196 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
1197 devm_kfree(ice_hw_to_dev(hw), mac_buf);
1200 goto err_unroll_fltr_mgmt_struct;
1201 /* enable jumbo frame support at MAC level */
1202 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL);
1204 goto err_unroll_fltr_mgmt_struct;
1205 /* Obtain counter base index which would be used by flow director */
1206 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
1208 goto err_unroll_fltr_mgmt_struct;
1209 status = ice_init_hw_tbls(hw);
1211 goto err_unroll_fltr_mgmt_struct;
1212 mutex_init(&hw->tnl_lock);
1215 err_unroll_fltr_mgmt_struct:
1216 ice_cleanup_fltr_mgmt_struct(hw);
1218 ice_sched_cleanup_all(hw);
1220 devm_kfree(ice_hw_to_dev(hw), hw->port_info);
1222 ice_destroy_all_ctrlq(hw);
1227 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
1228 * @hw: pointer to the hardware structure
1230 * This should be called only during nominal operation, not as a result of
1231 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
1232 * applicable initializations if it fails for any reason.
1234 void ice_deinit_hw(struct ice_hw *hw)
1236 ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
1237 ice_cleanup_fltr_mgmt_struct(hw);
1239 ice_sched_cleanup_all(hw);
1240 ice_sched_clear_agg(hw);
1242 ice_free_hw_tbls(hw);
1243 mutex_destroy(&hw->tnl_lock);
1245 /* Attempt to disable FW logging before shutting down control queues */
1246 ice_cfg_fw_log(hw, false);
1247 ice_destroy_all_ctrlq(hw);
1249 /* Clear VSI contexts if not already cleared */
1250 ice_clear_all_vsi_ctx(hw);
1254 * ice_check_reset - Check to see if a global reset is complete
1255 * @hw: pointer to the hardware structure
1257 int ice_check_reset(struct ice_hw *hw)
1259 u32 cnt, reg = 0, grst_timeout, uld_mask;
1261 /* Poll for Device Active state in case a recent CORER, GLOBR,
1262 * or EMPR has occurred. The grst delay value is in 100ms units.
1263 * Add 1sec for outstanding AQ commands that can take a long time.
1265 grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
1266 GLGEN_RSTCTL_GRSTDEL_S) + 10;
1268 for (cnt = 0; cnt < grst_timeout; cnt++) {
1270 reg = rd32(hw, GLGEN_RSTAT);
1271 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
1275 if (cnt == grst_timeout) {
1276 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n");
1280 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\
1281 GLNVM_ULD_PCIER_DONE_1_M |\
1282 GLNVM_ULD_CORER_DONE_M |\
1283 GLNVM_ULD_GLOBR_DONE_M |\
1284 GLNVM_ULD_POR_DONE_M |\
1285 GLNVM_ULD_POR_DONE_1_M |\
1286 GLNVM_ULD_PCIER_DONE_2_M)
1288 uld_mask = ICE_RESET_DONE_MASK | (hw->func_caps.common_cap.rdma ?
1289 GLNVM_ULD_PE_DONE_M : 0);
1291 /* Device is Active; check Global Reset processes are done */
1292 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
1293 reg = rd32(hw, GLNVM_ULD) & uld_mask;
1294 if (reg == uld_mask) {
1295 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt);
1301 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1302 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
1311 * ice_pf_reset - Reset the PF
1312 * @hw: pointer to the hardware structure
1314 * If a global reset has been triggered, this function checks
1315 * for its completion and then issues the PF reset
1317 static int ice_pf_reset(struct ice_hw *hw)
1321 /* If at function entry a global reset was already in progress, i.e.
1322 * state is not 'device active' or any of the reset done bits are not
1323 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
1324 * global reset is done.
1326 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
1327 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
1328 /* poll on global reset currently in progress until done */
1329 if (ice_check_reset(hw))
1336 reg = rd32(hw, PFGEN_CTRL);
1338 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
1340 /* Wait for the PFR to complete. The wait time is the global config lock
1341 * timeout plus the PFR timeout which will account for a possible reset
1342 * that is occurring during a download package operation.
1344 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT +
1345 ICE_PF_RESET_WAIT_COUNT; cnt++) {
1346 reg = rd32(hw, PFGEN_CTRL);
1347 if (!(reg & PFGEN_CTRL_PFSWR_M))
1353 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1354 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n");
1362 * ice_reset - Perform different types of reset
1363 * @hw: pointer to the hardware structure
1364 * @req: reset request
1366 * This function triggers a reset as specified by the req parameter.
1369 * If anything other than a PF reset is triggered, PXE mode is restored.
1370 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
1371 * interface has been restored in the rebuild flow.
1373 int ice_reset(struct ice_hw *hw, enum ice_reset_req req)
1379 return ice_pf_reset(hw);
1380 case ICE_RESET_CORER:
1381 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
1382 val = GLGEN_RTRIG_CORER_M;
1384 case ICE_RESET_GLOBR:
1385 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
1386 val = GLGEN_RTRIG_GLOBR_M;
1392 val |= rd32(hw, GLGEN_RTRIG);
1393 wr32(hw, GLGEN_RTRIG, val);
1396 /* wait for the FW to be ready */
1397 return ice_check_reset(hw);
1401 * ice_copy_rxq_ctx_to_hw
1402 * @hw: pointer to the hardware structure
1403 * @ice_rxq_ctx: pointer to the rxq context
1404 * @rxq_index: the index of the Rx queue
1406 * Copies rxq context from dense structure to HW register space
1409 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
1416 if (rxq_index > QRX_CTRL_MAX_INDEX)
1419 /* Copy each dword separately to HW */
1420 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1421 wr32(hw, QRX_CONTEXT(i, rxq_index),
1422 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1424 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1425 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1431 /* LAN Rx Queue Context */
1432 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1433 /* Field Width LSB */
1434 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1435 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1436 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1437 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1438 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1439 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1440 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1441 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1442 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1443 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1444 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1445 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1446 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1447 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1448 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1449 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1450 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1451 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1452 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1453 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201),
1459 * @hw: pointer to the hardware structure
1460 * @rlan_ctx: pointer to the rxq context
1461 * @rxq_index: the index of the Rx queue
1463 * Converts rxq context from sparse to dense structure and then writes
1464 * it to HW register space and enables the hardware to prefetch descriptors
1465 * instead of only fetching them on demand
1468 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1471 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1476 rlan_ctx->prefena = 1;
1478 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1479 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1482 /* LAN Tx Queue Context */
1483 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1484 /* Field Width LSB */
1485 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1486 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1487 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1488 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1489 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1490 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1491 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1492 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1493 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91),
1494 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1495 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1496 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1497 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1498 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1499 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1500 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1501 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1502 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1503 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1504 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1505 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1506 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1507 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1508 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1509 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1510 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1511 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1512 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171),
1516 /* Sideband Queue command wrappers */
1519 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue
1520 * @hw: pointer to the HW struct
1521 * @desc: descriptor describing the command
1522 * @buf: buffer to use for indirect commands (NULL for direct commands)
1523 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1524 * @cd: pointer to command details structure
1527 ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc,
1528 void *buf, u16 buf_size, struct ice_sq_cd *cd)
1530 return ice_sq_send_cmd(hw, ice_get_sbq(hw),
1531 (struct ice_aq_desc *)desc, buf, buf_size, cd);
1535 * ice_sbq_rw_reg - Fill Sideband Queue command
1536 * @hw: pointer to the HW struct
1537 * @in: message info to be filled in descriptor
1539 int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in)
1541 struct ice_sbq_cmd_desc desc = {0};
1542 struct ice_sbq_msg_req msg = {0};
1546 msg_len = sizeof(msg);
1548 msg.dest_dev = in->dest_dev;
1549 msg.opcode = in->opcode;
1550 msg.flags = ICE_SBQ_MSG_FLAGS;
1551 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE;
1552 msg.msg_addr_low = cpu_to_le16(in->msg_addr_low);
1553 msg.msg_addr_high = cpu_to_le32(in->msg_addr_high);
1556 msg.data = cpu_to_le32(in->data);
1558 /* data read comes back in completion, so shorten the struct by
1561 msg_len -= sizeof(msg.data);
1563 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD);
1564 desc.opcode = cpu_to_le16(ice_sbq_opc_neigh_dev_req);
1565 desc.param0.cmd_len = cpu_to_le16(msg_len);
1566 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL);
1567 if (!status && !in->opcode)
1568 in->data = le32_to_cpu
1569 (((struct ice_sbq_msg_cmpl *)&msg)->data);
1573 /* FW Admin Queue command wrappers */
1575 /* Software lock/mutex that is meant to be held while the Global Config Lock
1576 * in firmware is acquired by the software to prevent most (but not all) types
1577 * of AQ commands from being sent to FW
1579 DEFINE_MUTEX(ice_global_cfg_lock_sw);
1582 * ice_should_retry_sq_send_cmd
1583 * @opcode: AQ opcode
1585 * Decide if we should retry the send command routine for the ATQ, depending
1588 static bool ice_should_retry_sq_send_cmd(u16 opcode)
1591 case ice_aqc_opc_get_link_topo:
1592 case ice_aqc_opc_lldp_stop:
1593 case ice_aqc_opc_lldp_start:
1594 case ice_aqc_opc_lldp_filter_ctrl:
1602 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ)
1603 * @hw: pointer to the HW struct
1604 * @cq: pointer to the specific Control queue
1605 * @desc: prefilled descriptor describing the command
1606 * @buf: buffer to use for indirect commands (or NULL for direct commands)
1607 * @buf_size: size of buffer for indirect commands (or 0 for direct commands)
1608 * @cd: pointer to command details structure
1610 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin
1611 * Queue if the EBUSY AQ error is returned.
1614 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq,
1615 struct ice_aq_desc *desc, void *buf, u16 buf_size,
1616 struct ice_sq_cd *cd)
1618 struct ice_aq_desc desc_cpy;
1619 bool is_cmd_for_retry;
1624 opcode = le16_to_cpu(desc->opcode);
1625 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode);
1626 memset(&desc_cpy, 0, sizeof(desc_cpy));
1628 if (is_cmd_for_retry) {
1629 /* All retryable cmds are direct, without buf. */
1632 memcpy(&desc_cpy, desc, sizeof(desc_cpy));
1636 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd);
1638 if (!is_cmd_for_retry || !status ||
1639 hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY)
1642 memcpy(desc, &desc_cpy, sizeof(desc_cpy));
1644 msleep(ICE_SQ_SEND_DELAY_TIME_MS);
1646 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE);
1652 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1653 * @hw: pointer to the HW struct
1654 * @desc: descriptor describing the command
1655 * @buf: buffer to use for indirect commands (NULL for direct commands)
1656 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1657 * @cd: pointer to command details structure
1659 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1662 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1663 u16 buf_size, struct ice_sq_cd *cd)
1665 struct ice_aqc_req_res *cmd = &desc->params.res_owner;
1666 bool lock_acquired = false;
1669 /* When a package download is in process (i.e. when the firmware's
1670 * Global Configuration Lock resource is held), only the Download
1671 * Package, Get Version, Get Package Info List, Upload Section,
1672 * Update Package, Set Port Parameters, Get/Set VLAN Mode Parameters,
1673 * Add Recipe, Set Recipes to Profile Association, Get Recipe, and Get
1674 * Recipes to Profile Association, and Release Resource (with resource
1675 * ID set to Global Config Lock) AdminQ commands are allowed; all others
1676 * must block until the package download completes and the Global Config
1677 * Lock is released. See also ice_acquire_global_cfg_lock().
1679 switch (le16_to_cpu(desc->opcode)) {
1680 case ice_aqc_opc_download_pkg:
1681 case ice_aqc_opc_get_pkg_info_list:
1682 case ice_aqc_opc_get_ver:
1683 case ice_aqc_opc_upload_section:
1684 case ice_aqc_opc_update_pkg:
1685 case ice_aqc_opc_set_port_params:
1686 case ice_aqc_opc_get_vlan_mode_parameters:
1687 case ice_aqc_opc_set_vlan_mode_parameters:
1688 case ice_aqc_opc_add_recipe:
1689 case ice_aqc_opc_recipe_to_profile:
1690 case ice_aqc_opc_get_recipe:
1691 case ice_aqc_opc_get_recipe_to_profile:
1693 case ice_aqc_opc_release_res:
1694 if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK)
1698 mutex_lock(&ice_global_cfg_lock_sw);
1699 lock_acquired = true;
1703 status = ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd);
1705 mutex_unlock(&ice_global_cfg_lock_sw);
1712 * @hw: pointer to the HW struct
1713 * @cd: pointer to command details structure or NULL
1715 * Get the firmware version (0x0001) from the admin queue commands
1717 int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1719 struct ice_aqc_get_ver *resp;
1720 struct ice_aq_desc desc;
1723 resp = &desc.params.get_ver;
1725 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1727 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1730 hw->fw_branch = resp->fw_branch;
1731 hw->fw_maj_ver = resp->fw_major;
1732 hw->fw_min_ver = resp->fw_minor;
1733 hw->fw_patch = resp->fw_patch;
1734 hw->fw_build = le32_to_cpu(resp->fw_build);
1735 hw->api_branch = resp->api_branch;
1736 hw->api_maj_ver = resp->api_major;
1737 hw->api_min_ver = resp->api_minor;
1738 hw->api_patch = resp->api_patch;
1745 * ice_aq_send_driver_ver
1746 * @hw: pointer to the HW struct
1747 * @dv: driver's major, minor version
1748 * @cd: pointer to command details structure or NULL
1750 * Send the driver version (0x0002) to the firmware
1753 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1754 struct ice_sq_cd *cd)
1756 struct ice_aqc_driver_ver *cmd;
1757 struct ice_aq_desc desc;
1760 cmd = &desc.params.driver_ver;
1765 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver);
1767 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
1768 cmd->major_ver = dv->major_ver;
1769 cmd->minor_ver = dv->minor_ver;
1770 cmd->build_ver = dv->build_ver;
1771 cmd->subbuild_ver = dv->subbuild_ver;
1774 while (len < sizeof(dv->driver_string) &&
1775 isascii(dv->driver_string[len]) && dv->driver_string[len])
1778 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd);
1783 * @hw: pointer to the HW struct
1784 * @unloading: is the driver unloading itself
1786 * Tell the Firmware that we're shutting down the AdminQ and whether
1787 * or not the driver is unloading as well (0x0003).
1789 int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1791 struct ice_aqc_q_shutdown *cmd;
1792 struct ice_aq_desc desc;
1794 cmd = &desc.params.q_shutdown;
1796 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1799 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING;
1801 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1806 * @hw: pointer to the HW struct
1808 * @access: access type
1809 * @sdp_number: resource number
1810 * @timeout: the maximum time in ms that the driver may hold the resource
1811 * @cd: pointer to command details structure or NULL
1813 * Requests common resource using the admin queue commands (0x0008).
1814 * When attempting to acquire the Global Config Lock, the driver can
1815 * learn of three states:
1816 * 1) 0 - acquired lock, and can perform download package
1817 * 2) -EIO - did not get lock, driver should fail to load
1818 * 3) -EALREADY - did not get lock, but another driver has
1819 * successfully downloaded the package; the driver does
1820 * not have to download the package and can continue
1823 * Note that if the caller is in an acquire lock, perform action, release lock
1824 * phase of operation, it is possible that the FW may detect a timeout and issue
1825 * a CORER. In this case, the driver will receive a CORER interrupt and will
1826 * have to determine its cause. The calling thread that is handling this flow
1827 * will likely get an error propagated back to it indicating the Download
1828 * Package, Update Package or the Release Resource AQ commands timed out.
1831 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1832 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1833 struct ice_sq_cd *cd)
1835 struct ice_aqc_req_res *cmd_resp;
1836 struct ice_aq_desc desc;
1839 cmd_resp = &desc.params.res_owner;
1841 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1843 cmd_resp->res_id = cpu_to_le16(res);
1844 cmd_resp->access_type = cpu_to_le16(access);
1845 cmd_resp->res_number = cpu_to_le32(sdp_number);
1846 cmd_resp->timeout = cpu_to_le32(*timeout);
1849 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1851 /* The completion specifies the maximum time in ms that the driver
1852 * may hold the resource in the Timeout field.
1855 /* Global config lock response utilizes an additional status field.
1857 * If the Global config lock resource is held by some other driver, the
1858 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1859 * and the timeout field indicates the maximum time the current owner
1860 * of the resource has to free it.
1862 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1863 if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1864 *timeout = le32_to_cpu(cmd_resp->timeout);
1866 } else if (le16_to_cpu(cmd_resp->status) ==
1867 ICE_AQ_RES_GLBL_IN_PROG) {
1868 *timeout = le32_to_cpu(cmd_resp->timeout);
1870 } else if (le16_to_cpu(cmd_resp->status) ==
1871 ICE_AQ_RES_GLBL_DONE) {
1875 /* invalid FW response, force a timeout immediately */
1880 /* If the resource is held by some other driver, the command completes
1881 * with a busy return value and the timeout field indicates the maximum
1882 * time the current owner of the resource has to free it.
1884 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1885 *timeout = le32_to_cpu(cmd_resp->timeout);
1891 * ice_aq_release_res
1892 * @hw: pointer to the HW struct
1894 * @sdp_number: resource number
1895 * @cd: pointer to command details structure or NULL
1897 * release common resource using the admin queue commands (0x0009)
1900 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1901 struct ice_sq_cd *cd)
1903 struct ice_aqc_req_res *cmd;
1904 struct ice_aq_desc desc;
1906 cmd = &desc.params.res_owner;
1908 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1910 cmd->res_id = cpu_to_le16(res);
1911 cmd->res_number = cpu_to_le32(sdp_number);
1913 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1918 * @hw: pointer to the HW structure
1920 * @access: access type (read or write)
1921 * @timeout: timeout in milliseconds
1923 * This function will attempt to acquire the ownership of a resource.
1926 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1927 enum ice_aq_res_access_type access, u32 timeout)
1929 #define ICE_RES_POLLING_DELAY_MS 10
1930 u32 delay = ICE_RES_POLLING_DELAY_MS;
1931 u32 time_left = timeout;
1934 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1936 /* A return code of -EALREADY means that another driver has
1937 * previously acquired the resource and performed any necessary updates;
1938 * in this case the caller does not obtain the resource and has no
1939 * further work to do.
1941 if (status == -EALREADY)
1942 goto ice_acquire_res_exit;
1945 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access);
1947 /* If necessary, poll until the current lock owner timeouts */
1948 timeout = time_left;
1949 while (status && timeout && time_left) {
1951 timeout = (timeout > delay) ? timeout - delay : 0;
1952 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1954 if (status == -EALREADY)
1955 /* lock free, but no work to do */
1962 if (status && status != -EALREADY)
1963 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1965 ice_acquire_res_exit:
1966 if (status == -EALREADY) {
1967 if (access == ICE_RES_WRITE)
1968 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n");
1970 ice_debug(hw, ICE_DBG_RES, "Warning: -EALREADY not expected\n");
1977 * @hw: pointer to the HW structure
1980 * This function will release a resource using the proper Admin Command.
1982 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1984 unsigned long timeout;
1987 /* there are some rare cases when trying to release the resource
1988 * results in an admin queue timeout, so handle them correctly
1990 timeout = jiffies + 10 * ICE_CTL_Q_SQ_CMD_TIMEOUT;
1992 status = ice_aq_release_res(hw, res, 0, NULL);
1995 usleep_range(1000, 2000);
1996 } while (time_before(jiffies, timeout));
2000 * ice_aq_alloc_free_res - command to allocate/free resources
2001 * @hw: pointer to the HW struct
2002 * @num_entries: number of resource entries in buffer
2003 * @buf: Indirect buffer to hold data parameters and response
2004 * @buf_size: size of buffer for indirect commands
2005 * @opc: pass in the command opcode
2006 * @cd: pointer to command details structure or NULL
2008 * Helper function to allocate/free resources using the admin queue commands
2011 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
2012 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
2013 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
2015 struct ice_aqc_alloc_free_res_cmd *cmd;
2016 struct ice_aq_desc desc;
2018 cmd = &desc.params.sw_res_ctrl;
2023 if (buf_size < flex_array_size(buf, elem, num_entries))
2026 ice_fill_dflt_direct_cmd_desc(&desc, opc);
2028 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
2030 cmd->num_entries = cpu_to_le16(num_entries);
2032 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
2036 * ice_alloc_hw_res - allocate resource
2037 * @hw: pointer to the HW struct
2038 * @type: type of resource
2039 * @num: number of resources to allocate
2040 * @btm: allocate from bottom
2041 * @res: pointer to array that will receive the resources
2044 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
2046 struct ice_aqc_alloc_free_res_elem *buf;
2050 buf_len = struct_size(buf, elem, num);
2051 buf = kzalloc(buf_len, GFP_KERNEL);
2055 /* Prepare buffer to allocate resource. */
2056 buf->num_elems = cpu_to_le16(num);
2057 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED |
2058 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX);
2060 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM);
2062 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
2063 ice_aqc_opc_alloc_res, NULL);
2065 goto ice_alloc_res_exit;
2067 memcpy(res, buf->elem, sizeof(*buf->elem) * num);
2075 * ice_free_hw_res - free allocated HW resource
2076 * @hw: pointer to the HW struct
2077 * @type: type of resource to free
2078 * @num: number of resources
2079 * @res: pointer to array that contains the resources to free
2081 int ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
2083 struct ice_aqc_alloc_free_res_elem *buf;
2087 buf_len = struct_size(buf, elem, num);
2088 buf = kzalloc(buf_len, GFP_KERNEL);
2092 /* Prepare buffer to free resource. */
2093 buf->num_elems = cpu_to_le16(num);
2094 buf->res_type = cpu_to_le16(type);
2095 memcpy(buf->elem, res, sizeof(*buf->elem) * num);
2097 status = ice_aq_alloc_free_res(hw, num, buf, buf_len,
2098 ice_aqc_opc_free_res, NULL);
2100 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
2107 * ice_get_num_per_func - determine number of resources per PF
2108 * @hw: pointer to the HW structure
2109 * @max: value to be evenly split between each PF
2111 * Determine the number of valid functions by going through the bitmap returned
2112 * from parsing capabilities and use this to calculate the number of resources
2113 * per PF based on the max value passed in.
2115 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
2119 #define ICE_CAPS_VALID_FUNCS_M 0xFF
2120 funcs = hweight8(hw->dev_caps.common_cap.valid_functions &
2121 ICE_CAPS_VALID_FUNCS_M);
2130 * ice_parse_common_caps - parse common device/function capabilities
2131 * @hw: pointer to the HW struct
2132 * @caps: pointer to common capabilities structure
2133 * @elem: the capability element to parse
2134 * @prefix: message prefix for tracing capabilities
2136 * Given a capability element, extract relevant details into the common
2137 * capability structure.
2139 * Returns: true if the capability matches one of the common capability ids,
2143 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps,
2144 struct ice_aqc_list_caps_elem *elem, const char *prefix)
2146 u32 logical_id = le32_to_cpu(elem->logical_id);
2147 u32 phys_id = le32_to_cpu(elem->phys_id);
2148 u32 number = le32_to_cpu(elem->number);
2149 u16 cap = le16_to_cpu(elem->cap);
2153 case ICE_AQC_CAPS_VALID_FUNCTIONS:
2154 caps->valid_functions = number;
2155 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix,
2156 caps->valid_functions);
2158 case ICE_AQC_CAPS_SRIOV:
2159 caps->sr_iov_1_1 = (number == 1);
2160 ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix,
2163 case ICE_AQC_CAPS_DCB:
2164 caps->dcb = (number == 1);
2165 caps->active_tc_bitmap = logical_id;
2166 caps->maxtc = phys_id;
2167 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb);
2168 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix,
2169 caps->active_tc_bitmap);
2170 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc);
2172 case ICE_AQC_CAPS_RSS:
2173 caps->rss_table_size = number;
2174 caps->rss_table_entry_width = logical_id;
2175 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix,
2176 caps->rss_table_size);
2177 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix,
2178 caps->rss_table_entry_width);
2180 case ICE_AQC_CAPS_RXQS:
2181 caps->num_rxq = number;
2182 caps->rxq_first_id = phys_id;
2183 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix,
2185 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix,
2186 caps->rxq_first_id);
2188 case ICE_AQC_CAPS_TXQS:
2189 caps->num_txq = number;
2190 caps->txq_first_id = phys_id;
2191 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix,
2193 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix,
2194 caps->txq_first_id);
2196 case ICE_AQC_CAPS_MSIX:
2197 caps->num_msix_vectors = number;
2198 caps->msix_vector_first_id = phys_id;
2199 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix,
2200 caps->num_msix_vectors);
2201 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix,
2202 caps->msix_vector_first_id);
2204 case ICE_AQC_CAPS_PENDING_NVM_VER:
2205 caps->nvm_update_pending_nvm = true;
2206 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix);
2208 case ICE_AQC_CAPS_PENDING_OROM_VER:
2209 caps->nvm_update_pending_orom = true;
2210 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix);
2212 case ICE_AQC_CAPS_PENDING_NET_VER:
2213 caps->nvm_update_pending_netlist = true;
2214 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix);
2216 case ICE_AQC_CAPS_NVM_MGMT:
2217 caps->nvm_unified_update =
2218 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ?
2220 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix,
2221 caps->nvm_unified_update);
2223 case ICE_AQC_CAPS_RDMA:
2224 caps->rdma = (number == 1);
2225 ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma);
2227 case ICE_AQC_CAPS_MAX_MTU:
2228 caps->max_mtu = number;
2229 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
2230 prefix, caps->max_mtu);
2232 case ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE:
2233 caps->pcie_reset_avoidance = (number > 0);
2234 ice_debug(hw, ICE_DBG_INIT,
2235 "%s: pcie_reset_avoidance = %d\n", prefix,
2236 caps->pcie_reset_avoidance);
2238 case ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT:
2239 caps->reset_restrict_support = (number == 1);
2240 ice_debug(hw, ICE_DBG_INIT,
2241 "%s: reset_restrict_support = %d\n", prefix,
2242 caps->reset_restrict_support);
2245 /* Not one of the recognized common capabilities */
2253 * ice_recalc_port_limited_caps - Recalculate port limited capabilities
2254 * @hw: pointer to the HW structure
2255 * @caps: pointer to capabilities structure to fix
2257 * Re-calculate the capabilities that are dependent on the number of physical
2258 * ports; i.e. some features are not supported or function differently on
2259 * devices with more than 4 ports.
2262 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps)
2264 /* This assumes device capabilities are always scanned before function
2265 * capabilities during the initialization flow.
2267 if (hw->dev_caps.num_funcs > 4) {
2268 /* Max 4 TCs per port */
2270 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n",
2273 ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n");
2277 /* print message only when processing device capabilities
2278 * during initialization.
2280 if (caps == &hw->dev_caps.common_cap)
2281 dev_info(ice_hw_to_dev(hw), "RDMA functionality is not available with the current device configuration.\n");
2286 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps
2287 * @hw: pointer to the HW struct
2288 * @func_p: pointer to function capabilities structure
2289 * @cap: pointer to the capability element to parse
2291 * Extract function capabilities for ICE_AQC_CAPS_VF.
2294 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2295 struct ice_aqc_list_caps_elem *cap)
2297 u32 logical_id = le32_to_cpu(cap->logical_id);
2298 u32 number = le32_to_cpu(cap->number);
2300 func_p->num_allocd_vfs = number;
2301 func_p->vf_base_id = logical_id;
2302 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n",
2303 func_p->num_allocd_vfs);
2304 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n",
2305 func_p->vf_base_id);
2309 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps
2310 * @hw: pointer to the HW struct
2311 * @func_p: pointer to function capabilities structure
2312 * @cap: pointer to the capability element to parse
2314 * Extract function capabilities for ICE_AQC_CAPS_VSI.
2317 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2318 struct ice_aqc_list_caps_elem *cap)
2320 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI);
2321 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n",
2322 le32_to_cpu(cap->number));
2323 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n",
2324 func_p->guar_num_vsi);
2328 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps
2329 * @hw: pointer to the HW struct
2330 * @func_p: pointer to function capabilities structure
2331 * @cap: pointer to the capability element to parse
2333 * Extract function capabilities for ICE_AQC_CAPS_1588.
2336 ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2337 struct ice_aqc_list_caps_elem *cap)
2339 struct ice_ts_func_info *info = &func_p->ts_func_info;
2340 u32 number = le32_to_cpu(cap->number);
2342 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0);
2343 func_p->common_cap.ieee_1588 = info->ena;
2345 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0);
2346 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0);
2347 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0);
2348 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0);
2350 info->clk_freq = (number & ICE_TS_CLK_FREQ_M) >> ICE_TS_CLK_FREQ_S;
2351 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0);
2353 if (info->clk_freq < NUM_ICE_TIME_REF_FREQ) {
2354 info->time_ref = (enum ice_time_ref_freq)info->clk_freq;
2356 /* Unknown clock frequency, so assume a (probably incorrect)
2357 * default to avoid out-of-bounds look ups of frequency
2358 * related information.
2360 ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n",
2362 info->time_ref = ICE_TIME_REF_FREQ_25_000;
2365 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n",
2366 func_p->common_cap.ieee_1588);
2367 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n",
2368 info->src_tmr_owned);
2369 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n",
2371 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n",
2372 info->tmr_index_owned);
2373 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n",
2374 info->tmr_index_assoc);
2375 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n",
2377 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n",
2382 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps
2383 * @hw: pointer to the HW struct
2384 * @func_p: pointer to function capabilities structure
2386 * Extract function capabilities for ICE_AQC_CAPS_FD.
2389 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p)
2393 reg_val = rd32(hw, GLQF_FD_SIZE);
2394 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
2395 GLQF_FD_SIZE_FD_GSIZE_S;
2396 func_p->fd_fltr_guar =
2397 ice_get_num_per_func(hw, val);
2398 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
2399 GLQF_FD_SIZE_FD_BSIZE_S;
2400 func_p->fd_fltr_best_effort = val;
2402 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n",
2403 func_p->fd_fltr_guar);
2404 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n",
2405 func_p->fd_fltr_best_effort);
2409 * ice_parse_func_caps - Parse function capabilities
2410 * @hw: pointer to the HW struct
2411 * @func_p: pointer to function capabilities structure
2412 * @buf: buffer containing the function capability records
2413 * @cap_count: the number of capabilities
2415 * Helper function to parse function (0x000A) capabilities list. For
2416 * capabilities shared between device and function, this relies on
2417 * ice_parse_common_caps.
2419 * Loop through the list of provided capabilities and extract the relevant
2420 * data into the function capabilities structured.
2423 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2424 void *buf, u32 cap_count)
2426 struct ice_aqc_list_caps_elem *cap_resp;
2431 memset(func_p, 0, sizeof(*func_p));
2433 for (i = 0; i < cap_count; i++) {
2434 u16 cap = le16_to_cpu(cap_resp[i].cap);
2437 found = ice_parse_common_caps(hw, &func_p->common_cap,
2438 &cap_resp[i], "func caps");
2441 case ICE_AQC_CAPS_VF:
2442 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]);
2444 case ICE_AQC_CAPS_VSI:
2445 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]);
2447 case ICE_AQC_CAPS_1588:
2448 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]);
2450 case ICE_AQC_CAPS_FD:
2451 ice_parse_fdir_func_caps(hw, func_p);
2454 /* Don't list common capabilities as unknown */
2456 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n",
2462 ice_recalc_port_limited_caps(hw, &func_p->common_cap);
2466 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps
2467 * @hw: pointer to the HW struct
2468 * @dev_p: pointer to device capabilities structure
2469 * @cap: capability element to parse
2471 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities.
2474 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2475 struct ice_aqc_list_caps_elem *cap)
2477 u32 number = le32_to_cpu(cap->number);
2479 dev_p->num_funcs = hweight32(number);
2480 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n",
2485 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps
2486 * @hw: pointer to the HW struct
2487 * @dev_p: pointer to device capabilities structure
2488 * @cap: capability element to parse
2490 * Parse ICE_AQC_CAPS_VF for device capabilities.
2493 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2494 struct ice_aqc_list_caps_elem *cap)
2496 u32 number = le32_to_cpu(cap->number);
2498 dev_p->num_vfs_exposed = number;
2499 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n",
2500 dev_p->num_vfs_exposed);
2504 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps
2505 * @hw: pointer to the HW struct
2506 * @dev_p: pointer to device capabilities structure
2507 * @cap: capability element to parse
2509 * Parse ICE_AQC_CAPS_VSI for device capabilities.
2512 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2513 struct ice_aqc_list_caps_elem *cap)
2515 u32 number = le32_to_cpu(cap->number);
2517 dev_p->num_vsi_allocd_to_host = number;
2518 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n",
2519 dev_p->num_vsi_allocd_to_host);
2523 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps
2524 * @hw: pointer to the HW struct
2525 * @dev_p: pointer to device capabilities structure
2526 * @cap: capability element to parse
2528 * Parse ICE_AQC_CAPS_1588 for device capabilities.
2531 ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2532 struct ice_aqc_list_caps_elem *cap)
2534 struct ice_ts_dev_info *info = &dev_p->ts_dev_info;
2535 u32 logical_id = le32_to_cpu(cap->logical_id);
2536 u32 phys_id = le32_to_cpu(cap->phys_id);
2537 u32 number = le32_to_cpu(cap->number);
2539 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0);
2540 dev_p->common_cap.ieee_1588 = info->ena;
2542 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M;
2543 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0);
2544 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0);
2546 info->tmr1_owner = (number & ICE_TS_TMR1_OWNR_M) >> ICE_TS_TMR1_OWNR_S;
2547 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0);
2548 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0);
2550 info->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0);
2552 info->ena_ports = logical_id;
2553 info->tmr_own_map = phys_id;
2555 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n",
2556 dev_p->common_cap.ieee_1588);
2557 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n",
2559 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n",
2561 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n",
2563 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n",
2565 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n",
2567 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n",
2569 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_read = %u\n",
2571 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n",
2573 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n",
2578 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps
2579 * @hw: pointer to the HW struct
2580 * @dev_p: pointer to device capabilities structure
2581 * @cap: capability element to parse
2583 * Parse ICE_AQC_CAPS_FD for device capabilities.
2586 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2587 struct ice_aqc_list_caps_elem *cap)
2589 u32 number = le32_to_cpu(cap->number);
2591 dev_p->num_flow_director_fltr = number;
2592 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n",
2593 dev_p->num_flow_director_fltr);
2597 * ice_parse_dev_caps - Parse device capabilities
2598 * @hw: pointer to the HW struct
2599 * @dev_p: pointer to device capabilities structure
2600 * @buf: buffer containing the device capability records
2601 * @cap_count: the number of capabilities
2603 * Helper device to parse device (0x000B) capabilities list. For
2604 * capabilities shared between device and function, this relies on
2605 * ice_parse_common_caps.
2607 * Loop through the list of provided capabilities and extract the relevant
2608 * data into the device capabilities structured.
2611 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2612 void *buf, u32 cap_count)
2614 struct ice_aqc_list_caps_elem *cap_resp;
2619 memset(dev_p, 0, sizeof(*dev_p));
2621 for (i = 0; i < cap_count; i++) {
2622 u16 cap = le16_to_cpu(cap_resp[i].cap);
2625 found = ice_parse_common_caps(hw, &dev_p->common_cap,
2626 &cap_resp[i], "dev caps");
2629 case ICE_AQC_CAPS_VALID_FUNCTIONS:
2630 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]);
2632 case ICE_AQC_CAPS_VF:
2633 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]);
2635 case ICE_AQC_CAPS_VSI:
2636 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]);
2638 case ICE_AQC_CAPS_1588:
2639 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]);
2641 case ICE_AQC_CAPS_FD:
2642 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]);
2645 /* Don't list common capabilities as unknown */
2647 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n",
2653 ice_recalc_port_limited_caps(hw, &dev_p->common_cap);
2657 * ice_aq_list_caps - query function/device capabilities
2658 * @hw: pointer to the HW struct
2659 * @buf: a buffer to hold the capabilities
2660 * @buf_size: size of the buffer
2661 * @cap_count: if not NULL, set to the number of capabilities reported
2662 * @opc: capabilities type to discover, device or function
2663 * @cd: pointer to command details structure or NULL
2665 * Get the function (0x000A) or device (0x000B) capabilities description from
2666 * firmware and store it in the buffer.
2668 * If the cap_count pointer is not NULL, then it is set to the number of
2669 * capabilities firmware will report. Note that if the buffer size is too
2670 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The
2671 * cap_count will still be updated in this case. It is recommended that the
2672 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that
2673 * firmware could return) to avoid this.
2676 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
2677 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
2679 struct ice_aqc_list_caps *cmd;
2680 struct ice_aq_desc desc;
2683 cmd = &desc.params.get_cap;
2685 if (opc != ice_aqc_opc_list_func_caps &&
2686 opc != ice_aqc_opc_list_dev_caps)
2689 ice_fill_dflt_direct_cmd_desc(&desc, opc);
2690 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
2693 *cap_count = le32_to_cpu(cmd->count);
2699 * ice_discover_dev_caps - Read and extract device capabilities
2700 * @hw: pointer to the hardware structure
2701 * @dev_caps: pointer to device capabilities structure
2703 * Read the device capabilities and extract them into the dev_caps structure
2707 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps)
2713 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL);
2717 /* Although the driver doesn't know the number of capabilities the
2718 * device will return, we can simply send a 4KB buffer, the maximum
2719 * possible size that firmware can return.
2721 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem);
2723 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count,
2724 ice_aqc_opc_list_dev_caps, NULL);
2726 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count);
2733 * ice_discover_func_caps - Read and extract function capabilities
2734 * @hw: pointer to the hardware structure
2735 * @func_caps: pointer to function capabilities structure
2737 * Read the function capabilities and extract them into the func_caps structure
2741 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps)
2747 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL);
2751 /* Although the driver doesn't know the number of capabilities the
2752 * device will return, we can simply send a 4KB buffer, the maximum
2753 * possible size that firmware can return.
2755 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem);
2757 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count,
2758 ice_aqc_opc_list_func_caps, NULL);
2760 ice_parse_func_caps(hw, func_caps, cbuf, cap_count);
2767 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode
2768 * @hw: pointer to the hardware structure
2770 void ice_set_safe_mode_caps(struct ice_hw *hw)
2772 struct ice_hw_func_caps *func_caps = &hw->func_caps;
2773 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps;
2774 struct ice_hw_common_caps cached_caps;
2777 /* cache some func_caps values that should be restored after memset */
2778 cached_caps = func_caps->common_cap;
2780 /* unset func capabilities */
2781 memset(func_caps, 0, sizeof(*func_caps));
2783 #define ICE_RESTORE_FUNC_CAP(name) \
2784 func_caps->common_cap.name = cached_caps.name
2786 /* restore cached values */
2787 ICE_RESTORE_FUNC_CAP(valid_functions);
2788 ICE_RESTORE_FUNC_CAP(txq_first_id);
2789 ICE_RESTORE_FUNC_CAP(rxq_first_id);
2790 ICE_RESTORE_FUNC_CAP(msix_vector_first_id);
2791 ICE_RESTORE_FUNC_CAP(max_mtu);
2792 ICE_RESTORE_FUNC_CAP(nvm_unified_update);
2793 ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm);
2794 ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom);
2795 ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist);
2797 /* one Tx and one Rx queue in safe mode */
2798 func_caps->common_cap.num_rxq = 1;
2799 func_caps->common_cap.num_txq = 1;
2801 /* two MSIX vectors, one for traffic and one for misc causes */
2802 func_caps->common_cap.num_msix_vectors = 2;
2803 func_caps->guar_num_vsi = 1;
2805 /* cache some dev_caps values that should be restored after memset */
2806 cached_caps = dev_caps->common_cap;
2807 num_funcs = dev_caps->num_funcs;
2809 /* unset dev capabilities */
2810 memset(dev_caps, 0, sizeof(*dev_caps));
2812 #define ICE_RESTORE_DEV_CAP(name) \
2813 dev_caps->common_cap.name = cached_caps.name
2815 /* restore cached values */
2816 ICE_RESTORE_DEV_CAP(valid_functions);
2817 ICE_RESTORE_DEV_CAP(txq_first_id);
2818 ICE_RESTORE_DEV_CAP(rxq_first_id);
2819 ICE_RESTORE_DEV_CAP(msix_vector_first_id);
2820 ICE_RESTORE_DEV_CAP(max_mtu);
2821 ICE_RESTORE_DEV_CAP(nvm_unified_update);
2822 ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm);
2823 ICE_RESTORE_DEV_CAP(nvm_update_pending_orom);
2824 ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist);
2825 dev_caps->num_funcs = num_funcs;
2827 /* one Tx and one Rx queue per function in safe mode */
2828 dev_caps->common_cap.num_rxq = num_funcs;
2829 dev_caps->common_cap.num_txq = num_funcs;
2831 /* two MSIX vectors per function */
2832 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs;
2836 * ice_get_caps - get info about the HW
2837 * @hw: pointer to the hardware structure
2839 int ice_get_caps(struct ice_hw *hw)
2843 status = ice_discover_dev_caps(hw, &hw->dev_caps);
2847 return ice_discover_func_caps(hw, &hw->func_caps);
2851 * ice_aq_manage_mac_write - manage MAC address write command
2852 * @hw: pointer to the HW struct
2853 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
2854 * @flags: flags to control write behavior
2855 * @cd: pointer to command details structure or NULL
2857 * This function is used to write MAC address to the NVM (0x0108).
2860 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
2861 struct ice_sq_cd *cd)
2863 struct ice_aqc_manage_mac_write *cmd;
2864 struct ice_aq_desc desc;
2866 cmd = &desc.params.mac_write;
2867 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
2870 ether_addr_copy(cmd->mac_addr, mac_addr);
2872 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2876 * ice_aq_clear_pxe_mode
2877 * @hw: pointer to the HW struct
2879 * Tell the firmware that the driver is taking over from PXE (0x0110).
2881 static int ice_aq_clear_pxe_mode(struct ice_hw *hw)
2883 struct ice_aq_desc desc;
2885 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
2886 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
2888 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
2892 * ice_clear_pxe_mode - clear pxe operations mode
2893 * @hw: pointer to the HW struct
2895 * Make sure all PXE mode settings are cleared, including things
2896 * like descriptor fetch/write-back mode.
2898 void ice_clear_pxe_mode(struct ice_hw *hw)
2900 if (ice_check_sq_alive(hw, &hw->adminq))
2901 ice_aq_clear_pxe_mode(hw);
2905 * ice_aq_set_port_params - set physical port parameters.
2906 * @pi: pointer to the port info struct
2907 * @double_vlan: if set double VLAN is enabled
2908 * @cd: pointer to command details structure or NULL
2910 * Set Physical port parameters (0x0203)
2913 ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan,
2914 struct ice_sq_cd *cd)
2917 struct ice_aqc_set_port_params *cmd;
2918 struct ice_hw *hw = pi->hw;
2919 struct ice_aq_desc desc;
2922 cmd = &desc.params.set_port_params;
2924 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params);
2926 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA;
2927 cmd->cmd_flags = cpu_to_le16(cmd_flags);
2929 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2933 * ice_is_100m_speed_supported
2934 * @hw: pointer to the HW struct
2936 * returns true if 100M speeds are supported by the device,
2939 bool ice_is_100m_speed_supported(struct ice_hw *hw)
2941 switch (hw->device_id) {
2942 case ICE_DEV_ID_E822C_SGMII:
2943 case ICE_DEV_ID_E822L_SGMII:
2944 case ICE_DEV_ID_E823L_1GBE:
2945 case ICE_DEV_ID_E823C_SGMII:
2953 * ice_get_link_speed_based_on_phy_type - returns link speed
2954 * @phy_type_low: lower part of phy_type
2955 * @phy_type_high: higher part of phy_type
2957 * This helper function will convert an entry in PHY type structure
2958 * [phy_type_low, phy_type_high] to its corresponding link speed.
2959 * Note: In the structure of [phy_type_low, phy_type_high], there should
2960 * be one bit set, as this function will convert one PHY type to its
2962 * If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned
2963 * If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned
2966 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
2968 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2969 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2971 switch (phy_type_low) {
2972 case ICE_PHY_TYPE_LOW_100BASE_TX:
2973 case ICE_PHY_TYPE_LOW_100M_SGMII:
2974 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
2976 case ICE_PHY_TYPE_LOW_1000BASE_T:
2977 case ICE_PHY_TYPE_LOW_1000BASE_SX:
2978 case ICE_PHY_TYPE_LOW_1000BASE_LX:
2979 case ICE_PHY_TYPE_LOW_1000BASE_KX:
2980 case ICE_PHY_TYPE_LOW_1G_SGMII:
2981 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
2983 case ICE_PHY_TYPE_LOW_2500BASE_T:
2984 case ICE_PHY_TYPE_LOW_2500BASE_X:
2985 case ICE_PHY_TYPE_LOW_2500BASE_KX:
2986 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
2988 case ICE_PHY_TYPE_LOW_5GBASE_T:
2989 case ICE_PHY_TYPE_LOW_5GBASE_KR:
2990 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
2992 case ICE_PHY_TYPE_LOW_10GBASE_T:
2993 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
2994 case ICE_PHY_TYPE_LOW_10GBASE_SR:
2995 case ICE_PHY_TYPE_LOW_10GBASE_LR:
2996 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
2997 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
2998 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
2999 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
3001 case ICE_PHY_TYPE_LOW_25GBASE_T:
3002 case ICE_PHY_TYPE_LOW_25GBASE_CR:
3003 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
3004 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
3005 case ICE_PHY_TYPE_LOW_25GBASE_SR:
3006 case ICE_PHY_TYPE_LOW_25GBASE_LR:
3007 case ICE_PHY_TYPE_LOW_25GBASE_KR:
3008 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
3009 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
3010 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
3011 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
3012 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
3014 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
3015 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
3016 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
3017 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
3018 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
3019 case ICE_PHY_TYPE_LOW_40G_XLAUI:
3020 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
3022 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
3023 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
3024 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
3025 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
3026 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
3027 case ICE_PHY_TYPE_LOW_50G_LAUI2:
3028 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
3029 case ICE_PHY_TYPE_LOW_50G_AUI2:
3030 case ICE_PHY_TYPE_LOW_50GBASE_CP:
3031 case ICE_PHY_TYPE_LOW_50GBASE_SR:
3032 case ICE_PHY_TYPE_LOW_50GBASE_FR:
3033 case ICE_PHY_TYPE_LOW_50GBASE_LR:
3034 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
3035 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
3036 case ICE_PHY_TYPE_LOW_50G_AUI1:
3037 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
3039 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
3040 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
3041 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
3042 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
3043 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
3044 case ICE_PHY_TYPE_LOW_100G_CAUI4:
3045 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
3046 case ICE_PHY_TYPE_LOW_100G_AUI4:
3047 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
3048 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
3049 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
3050 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
3051 case ICE_PHY_TYPE_LOW_100GBASE_DR:
3052 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
3055 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
3059 switch (phy_type_high) {
3060 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
3061 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
3062 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
3063 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
3064 case ICE_PHY_TYPE_HIGH_100G_AUI2:
3065 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
3068 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
3072 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
3073 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
3074 return ICE_AQ_LINK_SPEED_UNKNOWN;
3075 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
3076 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
3077 return ICE_AQ_LINK_SPEED_UNKNOWN;
3078 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
3079 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
3080 return speed_phy_type_low;
3082 return speed_phy_type_high;
3086 * ice_update_phy_type
3087 * @phy_type_low: pointer to the lower part of phy_type
3088 * @phy_type_high: pointer to the higher part of phy_type
3089 * @link_speeds_bitmap: targeted link speeds bitmap
3091 * Note: For the link_speeds_bitmap structure, you can check it at
3092 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
3093 * link_speeds_bitmap include multiple speeds.
3095 * Each entry in this [phy_type_low, phy_type_high] structure will
3096 * present a certain link speed. This helper function will turn on bits
3097 * in [phy_type_low, phy_type_high] structure based on the value of
3098 * link_speeds_bitmap input parameter.
3101 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
3102 u16 link_speeds_bitmap)
3109 /* We first check with low part of phy_type */
3110 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
3111 pt_low = BIT_ULL(index);
3112 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
3114 if (link_speeds_bitmap & speed)
3115 *phy_type_low |= BIT_ULL(index);
3118 /* We then check with high part of phy_type */
3119 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
3120 pt_high = BIT_ULL(index);
3121 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
3123 if (link_speeds_bitmap & speed)
3124 *phy_type_high |= BIT_ULL(index);
3129 * ice_aq_set_phy_cfg
3130 * @hw: pointer to the HW struct
3131 * @pi: port info structure of the interested logical port
3132 * @cfg: structure with PHY configuration data to be set
3133 * @cd: pointer to command details structure or NULL
3135 * Set the various PHY configuration parameters supported on the Port.
3136 * One or more of the Set PHY config parameters may be ignored in an MFP
3137 * mode as the PF may not have the privilege to set some of the PHY Config
3138 * parameters. This status will be indicated by the command response (0x0601).
3141 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
3142 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
3144 struct ice_aq_desc desc;
3150 /* Ensure that only valid bits of cfg->caps can be turned on. */
3151 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
3152 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
3155 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
3158 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
3159 desc.params.set_phy.lport_num = pi->lport;
3160 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
3162 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n");
3163 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
3164 (unsigned long long)le64_to_cpu(cfg->phy_type_low));
3165 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
3166 (unsigned long long)le64_to_cpu(cfg->phy_type_high));
3167 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps);
3168 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n",
3169 cfg->low_power_ctrl_an);
3170 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap);
3171 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value);
3172 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n",
3175 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
3176 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE)
3180 pi->phy.curr_user_phy_cfg = *cfg;
3186 * ice_update_link_info - update status of the HW network link
3187 * @pi: port info structure of the interested logical port
3189 int ice_update_link_info(struct ice_port_info *pi)
3191 struct ice_link_status *li;
3197 li = &pi->phy.link_info;
3199 status = ice_aq_get_link_info(pi, true, NULL, NULL);
3203 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) {
3204 struct ice_aqc_get_phy_caps_data *pcaps;
3208 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps),
3213 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA,
3216 devm_kfree(ice_hw_to_dev(hw), pcaps);
3223 * ice_cache_phy_user_req
3224 * @pi: port information structure
3225 * @cache_data: PHY logging data
3226 * @cache_mode: PHY logging mode
3228 * Log the user request on (FC, FEC, SPEED) for later use.
3231 ice_cache_phy_user_req(struct ice_port_info *pi,
3232 struct ice_phy_cache_mode_data cache_data,
3233 enum ice_phy_cache_mode cache_mode)
3238 switch (cache_mode) {
3240 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;
3242 case ICE_SPEED_MODE:
3243 pi->phy.curr_user_speed_req =
3244 cache_data.data.curr_user_speed_req;
3247 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;
3255 * ice_caps_to_fc_mode
3256 * @caps: PHY capabilities
3258 * Convert PHY FC capabilities to ice FC mode
3260 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps)
3262 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&
3263 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
3266 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)
3267 return ICE_FC_TX_PAUSE;
3269 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
3270 return ICE_FC_RX_PAUSE;
3276 * ice_caps_to_fec_mode
3277 * @caps: PHY capabilities
3278 * @fec_options: Link FEC options
3280 * Convert PHY FEC capabilities to ice FEC mode
3282 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options)
3284 if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
3285 return ICE_FEC_AUTO;
3287 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
3288 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
3289 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |
3290 ICE_AQC_PHY_FEC_25G_KR_REQ))
3291 return ICE_FEC_BASER;
3293 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
3294 ICE_AQC_PHY_FEC_25G_RS_544_REQ |
3295 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))
3298 return ICE_FEC_NONE;
3302 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode
3303 * @pi: port information structure
3304 * @cfg: PHY configuration data to set FC mode
3305 * @req_mode: FC mode to configure
3308 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
3309 enum ice_fc_mode req_mode)
3311 struct ice_phy_cache_mode_data cache_data;
3312 u8 pause_mask = 0x0;
3319 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
3320 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
3322 case ICE_FC_RX_PAUSE:
3323 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
3325 case ICE_FC_TX_PAUSE:
3326 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
3332 /* clear the old pause settings */
3333 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
3334 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
3336 /* set the new capabilities */
3337 cfg->caps |= pause_mask;
3339 /* Cache user FC request */
3340 cache_data.data.curr_user_fc_req = req_mode;
3341 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE);
3348 * @pi: port information structure
3349 * @aq_failures: pointer to status code, specific to ice_set_fc routine
3350 * @ena_auto_link_update: enable automatic link update
3352 * Set the requested flow control mode.
3355 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
3357 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3358 struct ice_aqc_get_phy_caps_data *pcaps;
3362 if (!pi || !aq_failures)
3368 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL);
3372 /* Get the current PHY config */
3373 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG,
3376 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
3380 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg);
3382 /* Configure the set PHY data */
3383 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode);
3387 /* If the capabilities have changed, then set the new config */
3388 if (cfg.caps != pcaps->caps) {
3389 int retry_count, retry_max = 10;
3391 /* Auto restart link so settings take effect */
3392 if (ena_auto_link_update)
3393 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3395 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3397 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
3401 /* Update the link info
3402 * It sometimes takes a really long time for link to
3403 * come back from the atomic reset. Thus, we wait a
3406 for (retry_count = 0; retry_count < retry_max; retry_count++) {
3407 status = ice_update_link_info(pi);
3416 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
3420 devm_kfree(ice_hw_to_dev(hw), pcaps);
3425 * ice_phy_caps_equals_cfg
3426 * @phy_caps: PHY capabilities
3427 * @phy_cfg: PHY configuration
3429 * Helper function to determine if PHY capabilities matches PHY
3433 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
3434 struct ice_aqc_set_phy_cfg_data *phy_cfg)
3436 u8 caps_mask, cfg_mask;
3438 if (!phy_caps || !phy_cfg)
3441 /* These bits are not common between capabilities and configuration.
3442 * Do not use them to determine equality.
3444 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE |
3445 ICE_AQC_GET_PHY_EN_MOD_QUAL);
3446 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3448 if (phy_caps->phy_type_low != phy_cfg->phy_type_low ||
3449 phy_caps->phy_type_high != phy_cfg->phy_type_high ||
3450 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||
3451 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an ||
3452 phy_caps->eee_cap != phy_cfg->eee_cap ||
3453 phy_caps->eeer_value != phy_cfg->eeer_value ||
3454 phy_caps->link_fec_options != phy_cfg->link_fec_opt)
3461 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
3462 * @pi: port information structure
3463 * @caps: PHY ability structure to copy date from
3464 * @cfg: PHY configuration structure to copy data to
3466 * Helper function to copy AQC PHY get ability data to PHY set configuration
3470 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
3471 struct ice_aqc_get_phy_caps_data *caps,
3472 struct ice_aqc_set_phy_cfg_data *cfg)
3474 if (!pi || !caps || !cfg)
3477 memset(cfg, 0, sizeof(*cfg));
3478 cfg->phy_type_low = caps->phy_type_low;
3479 cfg->phy_type_high = caps->phy_type_high;
3480 cfg->caps = caps->caps;
3481 cfg->low_power_ctrl_an = caps->low_power_ctrl_an;
3482 cfg->eee_cap = caps->eee_cap;
3483 cfg->eeer_value = caps->eeer_value;
3484 cfg->link_fec_opt = caps->link_fec_options;
3485 cfg->module_compliance_enforcement =
3486 caps->module_compliance_enforcement;
3490 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
3491 * @pi: port information structure
3492 * @cfg: PHY configuration data to set FEC mode
3493 * @fec: FEC mode to configure
3496 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
3497 enum ice_fec_mode fec)
3499 struct ice_aqc_get_phy_caps_data *pcaps;
3508 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL);
3512 status = ice_aq_get_phy_caps(pi, false,
3513 (ice_fw_supports_report_dflt_cfg(hw) ?
3514 ICE_AQC_REPORT_DFLT_CFG :
3515 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL);
3519 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC;
3520 cfg->link_fec_opt = pcaps->link_fec_options;
3524 /* Clear RS bits, and AND BASE-R ability
3525 * bits and OR request bits.
3527 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
3528 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
3529 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
3530 ICE_AQC_PHY_FEC_25G_KR_REQ;
3533 /* Clear BASE-R bits, and AND RS ability
3534 * bits and OR request bits.
3536 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
3537 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
3538 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
3541 /* Clear all FEC option bits. */
3542 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
3545 /* AND auto FEC bit, and all caps bits. */
3546 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
3547 cfg->link_fec_opt |= pcaps->link_fec_options;
3554 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(hw) &&
3555 !ice_fw_supports_report_dflt_cfg(hw)) {
3556 struct ice_link_default_override_tlv tlv = { 0 };
3558 status = ice_get_link_default_override(&tlv, pi);
3562 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) &&
3563 (tlv.options & ICE_LINK_OVERRIDE_EN))
3564 cfg->link_fec_opt = tlv.fec_options;
3574 * ice_get_link_status - get status of the HW network link
3575 * @pi: port information structure
3576 * @link_up: pointer to bool (true/false = linkup/linkdown)
3578 * Variable link_up is true if link is up, false if link is down.
3579 * The variable link_up is invalid if status is non zero. As a
3580 * result of this call, link status reporting becomes enabled
3582 int ice_get_link_status(struct ice_port_info *pi, bool *link_up)
3584 struct ice_phy_info *phy_info;
3587 if (!pi || !link_up)
3590 phy_info = &pi->phy;
3592 if (phy_info->get_link_info) {
3593 status = ice_update_link_info(pi);
3596 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n",
3600 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
3606 * ice_aq_set_link_restart_an
3607 * @pi: pointer to the port information structure
3608 * @ena_link: if true: enable link, if false: disable link
3609 * @cd: pointer to command details structure or NULL
3611 * Sets up the link and restarts the Auto-Negotiation over the link.
3614 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
3615 struct ice_sq_cd *cd)
3617 struct ice_aqc_restart_an *cmd;
3618 struct ice_aq_desc desc;
3620 cmd = &desc.params.restart_an;
3622 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
3624 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
3625 cmd->lport_num = pi->lport;
3627 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
3629 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
3631 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
3635 * ice_aq_set_event_mask
3636 * @hw: pointer to the HW struct
3637 * @port_num: port number of the physical function
3638 * @mask: event mask to be set
3639 * @cd: pointer to command details structure or NULL
3641 * Set event mask (0x0613)
3644 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
3645 struct ice_sq_cd *cd)
3647 struct ice_aqc_set_event_mask *cmd;
3648 struct ice_aq_desc desc;
3650 cmd = &desc.params.set_event_mask;
3652 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
3654 cmd->lport_num = port_num;
3656 cmd->event_mask = cpu_to_le16(mask);
3657 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3661 * ice_aq_set_mac_loopback
3662 * @hw: pointer to the HW struct
3663 * @ena_lpbk: Enable or Disable loopback
3664 * @cd: pointer to command details structure or NULL
3666 * Enable/disable loopback on a given port
3669 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
3671 struct ice_aqc_set_mac_lb *cmd;
3672 struct ice_aq_desc desc;
3674 cmd = &desc.params.set_mac_lb;
3676 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
3678 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
3680 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3684 * ice_aq_set_port_id_led
3685 * @pi: pointer to the port information
3686 * @is_orig_mode: is this LED set to original mode (by the net-list)
3687 * @cd: pointer to command details structure or NULL
3689 * Set LED value for the given port (0x06e9)
3692 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
3693 struct ice_sq_cd *cd)
3695 struct ice_aqc_set_port_id_led *cmd;
3696 struct ice_hw *hw = pi->hw;
3697 struct ice_aq_desc desc;
3699 cmd = &desc.params.set_port_id_led;
3701 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
3704 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
3706 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
3708 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3712 * ice_aq_get_port_options
3713 * @hw: pointer to the HW struct
3714 * @options: buffer for the resultant port options
3715 * @option_count: input - size of the buffer in port options structures,
3716 * output - number of returned port options
3717 * @lport: logical port to call the command with (optional)
3718 * @lport_valid: when false, FW uses port owned by the PF instead of lport,
3719 * when PF owns more than 1 port it must be true
3720 * @active_option_idx: index of active port option in returned buffer
3721 * @active_option_valid: active option in returned buffer is valid
3722 * @pending_option_idx: index of pending port option in returned buffer
3723 * @pending_option_valid: pending option in returned buffer is valid
3725 * Calls Get Port Options AQC (0x06ea) and verifies result.
3728 ice_aq_get_port_options(struct ice_hw *hw,
3729 struct ice_aqc_get_port_options_elem *options,
3730 u8 *option_count, u8 lport, bool lport_valid,
3731 u8 *active_option_idx, bool *active_option_valid,
3732 u8 *pending_option_idx, bool *pending_option_valid)
3734 struct ice_aqc_get_port_options *cmd;
3735 struct ice_aq_desc desc;
3739 /* options buffer shall be able to hold max returned options */
3740 if (*option_count < ICE_AQC_PORT_OPT_COUNT_M)
3743 cmd = &desc.params.get_port_options;
3744 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_port_options);
3747 cmd->lport_num = lport;
3748 cmd->lport_num_valid = lport_valid;
3750 status = ice_aq_send_cmd(hw, &desc, options,
3751 *option_count * sizeof(*options), NULL);
3755 /* verify direct FW response & set output parameters */
3756 *option_count = FIELD_GET(ICE_AQC_PORT_OPT_COUNT_M,
3757 cmd->port_options_count);
3758 ice_debug(hw, ICE_DBG_PHY, "options: %x\n", *option_count);
3759 *active_option_valid = FIELD_GET(ICE_AQC_PORT_OPT_VALID,
3761 if (*active_option_valid) {
3762 *active_option_idx = FIELD_GET(ICE_AQC_PORT_OPT_ACTIVE_M,
3764 if (*active_option_idx > (*option_count - 1))
3766 ice_debug(hw, ICE_DBG_PHY, "active idx: %x\n",
3767 *active_option_idx);
3770 *pending_option_valid = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_VALID,
3771 cmd->pending_port_option_status);
3772 if (*pending_option_valid) {
3773 *pending_option_idx = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_IDX_M,
3774 cmd->pending_port_option_status);
3775 if (*pending_option_idx > (*option_count - 1))
3777 ice_debug(hw, ICE_DBG_PHY, "pending idx: %x\n",
3778 *pending_option_idx);
3781 /* mask output options fields */
3782 for (i = 0; i < *option_count; i++) {
3783 options[i].pmd = FIELD_GET(ICE_AQC_PORT_OPT_PMD_COUNT_M,
3785 options[i].max_lane_speed = FIELD_GET(ICE_AQC_PORT_OPT_MAX_LANE_M,
3786 options[i].max_lane_speed);
3787 ice_debug(hw, ICE_DBG_PHY, "pmds: %x max speed: %x\n",
3788 options[i].pmd, options[i].max_lane_speed);
3795 * ice_aq_set_port_option
3796 * @hw: pointer to the HW struct
3797 * @lport: logical port to call the command with
3798 * @lport_valid: when false, FW uses port owned by the PF instead of lport,
3799 * when PF owns more than 1 port it must be true
3800 * @new_option: new port option to be written
3802 * Calls Set Port Options AQC (0x06eb).
3805 ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid,
3808 struct ice_aqc_set_port_option *cmd;
3809 struct ice_aq_desc desc;
3811 if (new_option > ICE_AQC_PORT_OPT_COUNT_M)
3814 cmd = &desc.params.set_port_option;
3815 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_option);
3818 cmd->lport_num = lport;
3820 cmd->lport_num_valid = lport_valid;
3821 cmd->selected_port_option = new_option;
3823 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
3828 * @hw: pointer to the HW struct
3829 * @lport: bits [7:0] = logical port, bit [8] = logical port valid
3830 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default)
3831 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding.
3833 * @set_page: set or ignore the page
3834 * @data: pointer to data buffer to be read/written to the I2C device.
3835 * @length: 1-16 for read, 1 for write.
3836 * @write: 0 read, 1 for write.
3837 * @cd: pointer to command details structure or NULL
3839 * Read/Write SFF EEPROM (0x06EE)
3842 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
3843 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
3844 bool write, struct ice_sq_cd *cd)
3846 struct ice_aqc_sff_eeprom *cmd;
3847 struct ice_aq_desc desc;
3850 if (!data || (mem_addr & 0xff00))
3853 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom);
3854 cmd = &desc.params.read_write_sff_param;
3855 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD);
3856 cmd->lport_num = (u8)(lport & 0xff);
3857 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01);
3858 cmd->i2c_bus_addr = cpu_to_le16(((bus_addr >> 1) &
3859 ICE_AQC_SFF_I2CBUS_7BIT_M) |
3861 ICE_AQC_SFF_SET_EEPROM_PAGE_S) &
3862 ICE_AQC_SFF_SET_EEPROM_PAGE_M));
3863 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff);
3864 cmd->eeprom_page = cpu_to_le16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S);
3866 cmd->i2c_bus_addr |= cpu_to_le16(ICE_AQC_SFF_IS_WRITE);
3868 status = ice_aq_send_cmd(hw, &desc, data, length, cd);
3873 * __ice_aq_get_set_rss_lut
3874 * @hw: pointer to the hardware structure
3875 * @params: RSS LUT parameters
3876 * @set: set true to set the table, false to get the table
3878 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
3881 __ice_aq_get_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *params, bool set)
3883 u16 flags = 0, vsi_id, lut_type, lut_size, glob_lut_idx, vsi_handle;
3884 struct ice_aqc_get_set_rss_lut *cmd_resp;
3885 struct ice_aq_desc desc;
3892 vsi_handle = params->vsi_handle;
3895 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3898 lut_size = params->lut_size;
3899 lut_type = params->lut_type;
3900 glob_lut_idx = params->global_lut_id;
3901 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle);
3903 cmd_resp = &desc.params.get_set_rss_lut;
3906 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
3907 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
3909 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
3912 cmd_resp->vsi_id = cpu_to_le16(((vsi_id <<
3913 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
3914 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
3915 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
3918 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
3919 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
3920 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
3921 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
3922 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
3926 goto ice_aq_get_set_rss_lut_exit;
3929 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
3930 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
3931 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
3934 goto ice_aq_get_set_rss_lut_send;
3935 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3937 goto ice_aq_get_set_rss_lut_send;
3939 goto ice_aq_get_set_rss_lut_send;
3942 /* LUT size is only valid for Global and PF table types */
3944 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
3946 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
3947 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
3948 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3949 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3951 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
3952 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3953 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
3954 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3955 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3961 goto ice_aq_get_set_rss_lut_exit;
3964 ice_aq_get_set_rss_lut_send:
3965 cmd_resp->flags = cpu_to_le16(flags);
3966 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
3968 ice_aq_get_set_rss_lut_exit:
3973 * ice_aq_get_rss_lut
3974 * @hw: pointer to the hardware structure
3975 * @get_params: RSS LUT parameters used to specify which RSS LUT to get
3977 * get the RSS lookup table, PF or VSI type
3980 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params)
3982 return __ice_aq_get_set_rss_lut(hw, get_params, false);
3986 * ice_aq_set_rss_lut
3987 * @hw: pointer to the hardware structure
3988 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT
3990 * set the RSS lookup table, PF or VSI type
3993 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params)
3995 return __ice_aq_get_set_rss_lut(hw, set_params, true);
3999 * __ice_aq_get_set_rss_key
4000 * @hw: pointer to the HW struct
4001 * @vsi_id: VSI FW index
4002 * @key: pointer to key info struct
4003 * @set: set true to set the key, false to get the key
4005 * get (0x0B04) or set (0x0B02) the RSS key per VSI
4008 __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
4009 struct ice_aqc_get_set_rss_keys *key, bool set)
4011 struct ice_aqc_get_set_rss_key *cmd_resp;
4012 u16 key_size = sizeof(*key);
4013 struct ice_aq_desc desc;
4015 cmd_resp = &desc.params.get_set_rss_key;
4018 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
4019 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
4021 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
4024 cmd_resp->vsi_id = cpu_to_le16(((vsi_id <<
4025 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
4026 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
4027 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
4029 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
4033 * ice_aq_get_rss_key
4034 * @hw: pointer to the HW struct
4035 * @vsi_handle: software VSI handle
4036 * @key: pointer to key info struct
4038 * get the RSS key per VSI
4041 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
4042 struct ice_aqc_get_set_rss_keys *key)
4044 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
4047 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
4052 * ice_aq_set_rss_key
4053 * @hw: pointer to the HW struct
4054 * @vsi_handle: software VSI handle
4055 * @keys: pointer to key info struct
4057 * set the RSS key per VSI
4060 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
4061 struct ice_aqc_get_set_rss_keys *keys)
4063 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
4066 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
4071 * ice_aq_add_lan_txq
4072 * @hw: pointer to the hardware structure
4073 * @num_qgrps: Number of added queue groups
4074 * @qg_list: list of queue groups to be added
4075 * @buf_size: size of buffer for indirect command
4076 * @cd: pointer to command details structure or NULL
4078 * Add Tx LAN queue (0x0C30)
4081 * Prior to calling add Tx LAN queue:
4082 * Initialize the following as part of the Tx queue context:
4083 * Completion queue ID if the queue uses Completion queue, Quanta profile,
4084 * Cache profile and Packet shaper profile.
4086 * After add Tx LAN queue AQ command is completed:
4087 * Interrupts should be associated with specific queues,
4088 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
4092 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
4093 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
4094 struct ice_sq_cd *cd)
4096 struct ice_aqc_add_tx_qgrp *list;
4097 struct ice_aqc_add_txqs *cmd;
4098 struct ice_aq_desc desc;
4099 u16 i, sum_size = 0;
4101 cmd = &desc.params.add_txqs;
4103 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
4108 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
4111 for (i = 0, list = qg_list; i < num_qgrps; i++) {
4112 sum_size += struct_size(list, txqs, list->num_txqs);
4113 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs +
4117 if (buf_size != sum_size)
4120 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
4122 cmd->num_qgrps = num_qgrps;
4124 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
4128 * ice_aq_dis_lan_txq
4129 * @hw: pointer to the hardware structure
4130 * @num_qgrps: number of groups in the list
4131 * @qg_list: the list of groups to disable
4132 * @buf_size: the total size of the qg_list buffer in bytes
4133 * @rst_src: if called due to reset, specifies the reset source
4134 * @vmvf_num: the relative VM or VF number that is undergoing the reset
4135 * @cd: pointer to command details structure or NULL
4137 * Disable LAN Tx queue (0x0C31)
4140 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
4141 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
4142 enum ice_disq_rst_src rst_src, u16 vmvf_num,
4143 struct ice_sq_cd *cd)
4145 struct ice_aqc_dis_txq_item *item;
4146 struct ice_aqc_dis_txqs *cmd;
4147 struct ice_aq_desc desc;
4151 cmd = &desc.params.dis_txqs;
4152 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
4154 /* qg_list can be NULL only in VM/VF reset flow */
4155 if (!qg_list && !rst_src)
4158 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
4161 cmd->num_entries = num_qgrps;
4163 cmd->vmvf_and_timeout = cpu_to_le16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
4164 ICE_AQC_Q_DIS_TIMEOUT_M);
4168 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
4169 cmd->vmvf_and_timeout |=
4170 cpu_to_le16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
4173 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET;
4174 /* In this case, FW expects vmvf_num to be absolute VF ID */
4175 cmd->vmvf_and_timeout |=
4176 cpu_to_le16((vmvf_num + hw->func_caps.vf_base_id) &
4177 ICE_AQC_Q_DIS_VMVF_NUM_M);
4184 /* flush pipe on time out */
4185 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
4186 /* If no queue group info, we are in a reset flow. Issue the AQ */
4190 /* set RD bit to indicate that command buffer is provided by the driver
4191 * and it needs to be read by the firmware
4193 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
4195 for (i = 0, item = qg_list; i < num_qgrps; i++) {
4196 u16 item_size = struct_size(item, q_id, item->num_qs);
4198 /* If the num of queues is even, add 2 bytes of padding */
4199 if ((item->num_qs % 2) == 0)
4204 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size);
4211 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
4214 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
4215 vmvf_num, hw->adminq.sq_last_status);
4217 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
4218 le16_to_cpu(qg_list[0].q_id[0]),
4219 hw->adminq.sq_last_status);
4225 * ice_aq_add_rdma_qsets
4226 * @hw: pointer to the hardware structure
4227 * @num_qset_grps: Number of RDMA Qset groups
4228 * @qset_list: list of Qset groups to be added
4229 * @buf_size: size of buffer for indirect command
4230 * @cd: pointer to command details structure or NULL
4232 * Add Tx RDMA Qsets (0x0C33)
4235 ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps,
4236 struct ice_aqc_add_rdma_qset_data *qset_list,
4237 u16 buf_size, struct ice_sq_cd *cd)
4239 struct ice_aqc_add_rdma_qset_data *list;
4240 struct ice_aqc_add_rdma_qset *cmd;
4241 struct ice_aq_desc desc;
4242 u16 i, sum_size = 0;
4244 cmd = &desc.params.add_rdma_qset;
4246 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_rdma_qset);
4248 if (num_qset_grps > ICE_LAN_TXQ_MAX_QGRPS)
4251 for (i = 0, list = qset_list; i < num_qset_grps; i++) {
4252 u16 num_qsets = le16_to_cpu(list->num_qsets);
4254 sum_size += struct_size(list, rdma_qsets, num_qsets);
4255 list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets +
4259 if (buf_size != sum_size)
4262 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
4264 cmd->num_qset_grps = num_qset_grps;
4266 return ice_aq_send_cmd(hw, &desc, qset_list, buf_size, cd);
4269 /* End of FW Admin Queue command wrappers */
4272 * ice_write_byte - write a byte to a packed context structure
4273 * @src_ctx: the context structure to read from
4274 * @dest_ctx: the context to be written to
4275 * @ce_info: a description of the struct to be filled
4278 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
4280 u8 src_byte, dest_byte, mask;
4284 /* copy from the next struct field */
4285 from = src_ctx + ce_info->offset;
4287 /* prepare the bits and mask */
4288 shift_width = ce_info->lsb % 8;
4289 mask = (u8)(BIT(ce_info->width) - 1);
4294 /* shift to correct alignment */
4295 mask <<= shift_width;
4296 src_byte <<= shift_width;
4298 /* get the current bits from the target bit string */
4299 dest = dest_ctx + (ce_info->lsb / 8);
4301 memcpy(&dest_byte, dest, sizeof(dest_byte));
4303 dest_byte &= ~mask; /* get the bits not changing */
4304 dest_byte |= src_byte; /* add in the new bits */
4306 /* put it all back */
4307 memcpy(dest, &dest_byte, sizeof(dest_byte));
4311 * ice_write_word - write a word to a packed context structure
4312 * @src_ctx: the context structure to read from
4313 * @dest_ctx: the context to be written to
4314 * @ce_info: a description of the struct to be filled
4317 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
4324 /* copy from the next struct field */
4325 from = src_ctx + ce_info->offset;
4327 /* prepare the bits and mask */
4328 shift_width = ce_info->lsb % 8;
4329 mask = BIT(ce_info->width) - 1;
4331 /* don't swizzle the bits until after the mask because the mask bits
4332 * will be in a different bit position on big endian machines
4334 src_word = *(u16 *)from;
4337 /* shift to correct alignment */
4338 mask <<= shift_width;
4339 src_word <<= shift_width;
4341 /* get the current bits from the target bit string */
4342 dest = dest_ctx + (ce_info->lsb / 8);
4344 memcpy(&dest_word, dest, sizeof(dest_word));
4346 dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */
4347 dest_word |= cpu_to_le16(src_word); /* add in the new bits */
4349 /* put it all back */
4350 memcpy(dest, &dest_word, sizeof(dest_word));
4354 * ice_write_dword - write a dword to a packed context structure
4355 * @src_ctx: the context structure to read from
4356 * @dest_ctx: the context to be written to
4357 * @ce_info: a description of the struct to be filled
4360 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
4362 u32 src_dword, mask;
4367 /* copy from the next struct field */
4368 from = src_ctx + ce_info->offset;
4370 /* prepare the bits and mask */
4371 shift_width = ce_info->lsb % 8;
4373 /* if the field width is exactly 32 on an x86 machine, then the shift
4374 * operation will not work because the SHL instructions count is masked
4375 * to 5 bits so the shift will do nothing
4377 if (ce_info->width < 32)
4378 mask = BIT(ce_info->width) - 1;
4382 /* don't swizzle the bits until after the mask because the mask bits
4383 * will be in a different bit position on big endian machines
4385 src_dword = *(u32 *)from;
4388 /* shift to correct alignment */
4389 mask <<= shift_width;
4390 src_dword <<= shift_width;
4392 /* get the current bits from the target bit string */
4393 dest = dest_ctx + (ce_info->lsb / 8);
4395 memcpy(&dest_dword, dest, sizeof(dest_dword));
4397 dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */
4398 dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */
4400 /* put it all back */
4401 memcpy(dest, &dest_dword, sizeof(dest_dword));
4405 * ice_write_qword - write a qword to a packed context structure
4406 * @src_ctx: the context structure to read from
4407 * @dest_ctx: the context to be written to
4408 * @ce_info: a description of the struct to be filled
4411 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
4413 u64 src_qword, mask;
4418 /* copy from the next struct field */
4419 from = src_ctx + ce_info->offset;
4421 /* prepare the bits and mask */
4422 shift_width = ce_info->lsb % 8;
4424 /* if the field width is exactly 64 on an x86 machine, then the shift
4425 * operation will not work because the SHL instructions count is masked
4426 * to 6 bits so the shift will do nothing
4428 if (ce_info->width < 64)
4429 mask = BIT_ULL(ce_info->width) - 1;
4433 /* don't swizzle the bits until after the mask because the mask bits
4434 * will be in a different bit position on big endian machines
4436 src_qword = *(u64 *)from;
4439 /* shift to correct alignment */
4440 mask <<= shift_width;
4441 src_qword <<= shift_width;
4443 /* get the current bits from the target bit string */
4444 dest = dest_ctx + (ce_info->lsb / 8);
4446 memcpy(&dest_qword, dest, sizeof(dest_qword));
4448 dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */
4449 dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */
4451 /* put it all back */
4452 memcpy(dest, &dest_qword, sizeof(dest_qword));
4456 * ice_set_ctx - set context bits in packed structure
4457 * @hw: pointer to the hardware structure
4458 * @src_ctx: pointer to a generic non-packed context structure
4459 * @dest_ctx: pointer to memory for the packed structure
4460 * @ce_info: a description of the structure to be transformed
4463 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,
4464 const struct ice_ctx_ele *ce_info)
4468 for (f = 0; ce_info[f].width; f++) {
4469 /* We have to deal with each element of the FW response
4470 * using the correct size so that we are correct regardless
4471 * of the endianness of the machine.
4473 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) {
4474 ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n",
4475 f, ce_info[f].width, ce_info[f].size_of);
4478 switch (ce_info[f].size_of) {
4480 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
4483 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
4486 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
4489 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
4500 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
4501 * @hw: pointer to the HW struct
4502 * @vsi_handle: software VSI handle
4504 * @q_handle: software queue handle
4507 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
4509 struct ice_vsi_ctx *vsi;
4510 struct ice_q_ctx *q_ctx;
4512 vsi = ice_get_vsi_ctx(hw, vsi_handle);
4515 if (q_handle >= vsi->num_lan_q_entries[tc])
4517 if (!vsi->lan_q_ctx[tc])
4519 q_ctx = vsi->lan_q_ctx[tc];
4520 return &q_ctx[q_handle];
4525 * @pi: port information structure
4526 * @vsi_handle: software VSI handle
4528 * @q_handle: software queue handle
4529 * @num_qgrps: Number of added queue groups
4530 * @buf: list of queue groups to be added
4531 * @buf_size: size of buffer for indirect command
4532 * @cd: pointer to command details structure or NULL
4534 * This function adds one LAN queue
4537 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
4538 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
4539 struct ice_sq_cd *cd)
4541 struct ice_aqc_txsched_elem_data node = { 0 };
4542 struct ice_sched_node *parent;
4543 struct ice_q_ctx *q_ctx;
4547 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4550 if (num_qgrps > 1 || buf->num_txqs > 1)
4555 if (!ice_is_vsi_valid(hw, vsi_handle))
4558 mutex_lock(&pi->sched_lock);
4560 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
4562 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
4568 /* find a parent node */
4569 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
4570 ICE_SCHED_NODE_OWNER_LAN);
4576 buf->parent_teid = parent->info.node_teid;
4577 node.parent_teid = parent->info.node_teid;
4578 /* Mark that the values in the "generic" section as valid. The default
4579 * value in the "generic" section is zero. This means that :
4580 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
4581 * - 0 priority among siblings, indicated by Bit 1-3.
4582 * - WFQ, indicated by Bit 4.
4583 * - 0 Adjustment value is used in PSM credit update flow, indicated by
4585 * - Bit 7 is reserved.
4586 * Without setting the generic section as valid in valid_sections, the
4587 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
4589 buf->txqs[0].info.valid_sections =
4590 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR |
4591 ICE_AQC_ELEM_VALID_EIR;
4592 buf->txqs[0].info.generic = 0;
4593 buf->txqs[0].info.cir_bw.bw_profile_idx =
4594 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID);
4595 buf->txqs[0].info.cir_bw.bw_alloc =
4596 cpu_to_le16(ICE_SCHED_DFLT_BW_WT);
4597 buf->txqs[0].info.eir_bw.bw_profile_idx =
4598 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID);
4599 buf->txqs[0].info.eir_bw.bw_alloc =
4600 cpu_to_le16(ICE_SCHED_DFLT_BW_WT);
4602 /* add the LAN queue */
4603 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
4605 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
4606 le16_to_cpu(buf->txqs[0].txq_id),
4607 hw->adminq.sq_last_status);
4611 node.node_teid = buf->txqs[0].q_teid;
4612 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
4613 q_ctx->q_handle = q_handle;
4614 q_ctx->q_teid = le32_to_cpu(node.node_teid);
4616 /* add a leaf node into scheduler tree queue layer */
4617 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node, NULL);
4619 status = ice_sched_replay_q_bw(pi, q_ctx);
4622 mutex_unlock(&pi->sched_lock);
4628 * @pi: port information structure
4629 * @vsi_handle: software VSI handle
4631 * @num_queues: number of queues
4632 * @q_handles: pointer to software queue handle array
4633 * @q_ids: pointer to the q_id array
4634 * @q_teids: pointer to queue node teids
4635 * @rst_src: if called due to reset, specifies the reset source
4636 * @vmvf_num: the relative VM or VF number that is undergoing the reset
4637 * @cd: pointer to command details structure or NULL
4639 * This function removes queues and their corresponding nodes in SW DB
4642 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
4643 u16 *q_handles, u16 *q_ids, u32 *q_teids,
4644 enum ice_disq_rst_src rst_src, u16 vmvf_num,
4645 struct ice_sq_cd *cd)
4647 struct ice_aqc_dis_txq_item *qg_list;
4648 struct ice_q_ctx *q_ctx;
4649 int status = -ENOENT;
4653 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4659 /* if queue is disabled already yet the disable queue command
4660 * has to be sent to complete the VF reset, then call
4661 * ice_aq_dis_lan_txq without any queue information
4664 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src,
4669 buf_size = struct_size(qg_list, q_id, 1);
4670 qg_list = kzalloc(buf_size, GFP_KERNEL);
4674 mutex_lock(&pi->sched_lock);
4676 for (i = 0; i < num_queues; i++) {
4677 struct ice_sched_node *node;
4679 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
4682 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]);
4684 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
4688 if (q_ctx->q_handle != q_handles[i]) {
4689 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
4690 q_ctx->q_handle, q_handles[i]);
4693 qg_list->parent_teid = node->info.parent_teid;
4694 qg_list->num_qs = 1;
4695 qg_list->q_id[0] = cpu_to_le16(q_ids[i]);
4696 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src,
4701 ice_free_sched_node(pi, node);
4702 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
4704 mutex_unlock(&pi->sched_lock);
4710 * ice_cfg_vsi_qs - configure the new/existing VSI queues
4711 * @pi: port information structure
4712 * @vsi_handle: software VSI handle
4713 * @tc_bitmap: TC bitmap
4714 * @maxqs: max queues array per TC
4715 * @owner: LAN or RDMA
4717 * This function adds/updates the VSI queues per TC.
4720 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
4721 u16 *maxqs, u8 owner)
4726 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4729 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
4732 mutex_lock(&pi->sched_lock);
4734 ice_for_each_traffic_class(i) {
4735 /* configuration is possible only if TC node is present */
4736 if (!ice_sched_get_tc_node(pi, i))
4739 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
4740 ice_is_tc_ena(tc_bitmap, i));
4745 mutex_unlock(&pi->sched_lock);
4750 * ice_cfg_vsi_lan - configure VSI LAN queues
4751 * @pi: port information structure
4752 * @vsi_handle: software VSI handle
4753 * @tc_bitmap: TC bitmap
4754 * @max_lanqs: max LAN queues array per TC
4756 * This function adds/updates the VSI LAN queues per TC.
4759 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
4762 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
4763 ICE_SCHED_NODE_OWNER_LAN);
4767 * ice_cfg_vsi_rdma - configure the VSI RDMA queues
4768 * @pi: port information structure
4769 * @vsi_handle: software VSI handle
4770 * @tc_bitmap: TC bitmap
4771 * @max_rdmaqs: max RDMA queues array per TC
4773 * This function adds/updates the VSI RDMA queues per TC.
4776 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
4779 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_rdmaqs,
4780 ICE_SCHED_NODE_OWNER_RDMA);
4784 * ice_ena_vsi_rdma_qset
4785 * @pi: port information structure
4786 * @vsi_handle: software VSI handle
4788 * @rdma_qset: pointer to RDMA Qset
4789 * @num_qsets: number of RDMA Qsets
4790 * @qset_teid: pointer to Qset node TEIDs
4792 * This function adds RDMA Qset
4795 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
4796 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid)
4798 struct ice_aqc_txsched_elem_data node = { 0 };
4799 struct ice_aqc_add_rdma_qset_data *buf;
4800 struct ice_sched_node *parent;
4805 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4809 if (!ice_is_vsi_valid(hw, vsi_handle))
4812 buf_size = struct_size(buf, rdma_qsets, num_qsets);
4813 buf = kzalloc(buf_size, GFP_KERNEL);
4816 mutex_lock(&pi->sched_lock);
4818 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
4819 ICE_SCHED_NODE_OWNER_RDMA);
4822 goto rdma_error_exit;
4824 buf->parent_teid = parent->info.node_teid;
4825 node.parent_teid = parent->info.node_teid;
4827 buf->num_qsets = cpu_to_le16(num_qsets);
4828 for (i = 0; i < num_qsets; i++) {
4829 buf->rdma_qsets[i].tx_qset_id = cpu_to_le16(rdma_qset[i]);
4830 buf->rdma_qsets[i].info.valid_sections =
4831 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR |
4832 ICE_AQC_ELEM_VALID_EIR;
4833 buf->rdma_qsets[i].info.generic = 0;
4834 buf->rdma_qsets[i].info.cir_bw.bw_profile_idx =
4835 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID);
4836 buf->rdma_qsets[i].info.cir_bw.bw_alloc =
4837 cpu_to_le16(ICE_SCHED_DFLT_BW_WT);
4838 buf->rdma_qsets[i].info.eir_bw.bw_profile_idx =
4839 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID);
4840 buf->rdma_qsets[i].info.eir_bw.bw_alloc =
4841 cpu_to_le16(ICE_SCHED_DFLT_BW_WT);
4843 ret = ice_aq_add_rdma_qsets(hw, 1, buf, buf_size, NULL);
4845 ice_debug(hw, ICE_DBG_RDMA, "add RDMA qset failed\n");
4846 goto rdma_error_exit;
4848 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
4849 for (i = 0; i < num_qsets; i++) {
4850 node.node_teid = buf->rdma_qsets[i].qset_teid;
4851 ret = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1,
4855 qset_teid[i] = le32_to_cpu(node.node_teid);
4858 mutex_unlock(&pi->sched_lock);
4864 * ice_dis_vsi_rdma_qset - free RDMA resources
4865 * @pi: port_info struct
4866 * @count: number of RDMA Qsets to free
4867 * @qset_teid: TEID of Qset node
4868 * @q_id: list of queue IDs being disabled
4871 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid,
4874 struct ice_aqc_dis_txq_item *qg_list;
4880 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4885 qg_size = struct_size(qg_list, q_id, 1);
4886 qg_list = kzalloc(qg_size, GFP_KERNEL);
4890 mutex_lock(&pi->sched_lock);
4892 for (i = 0; i < count; i++) {
4893 struct ice_sched_node *node;
4895 node = ice_sched_find_node_by_teid(pi->root, qset_teid[i]);
4899 qg_list->parent_teid = node->info.parent_teid;
4900 qg_list->num_qs = 1;
4902 cpu_to_le16(q_id[i] |
4903 ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET);
4905 status = ice_aq_dis_lan_txq(hw, 1, qg_list, qg_size,
4906 ICE_NO_RESET, 0, NULL);
4910 ice_free_sched_node(pi, node);
4913 mutex_unlock(&pi->sched_lock);
4919 * ice_replay_pre_init - replay pre initialization
4920 * @hw: pointer to the HW struct
4922 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
4924 static int ice_replay_pre_init(struct ice_hw *hw)
4926 struct ice_switch_info *sw = hw->switch_info;
4929 /* Delete old entries from replay filter list head if there is any */
4930 ice_rm_all_sw_replay_rule_info(hw);
4931 /* In start of replay, move entries into replay_rules list, it
4932 * will allow adding rules entries back to filt_rules list,
4933 * which is operational list.
4935 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
4936 list_replace_init(&sw->recp_list[i].filt_rules,
4937 &sw->recp_list[i].filt_replay_rules);
4938 ice_sched_replay_agg_vsi_preinit(hw);
4944 * ice_replay_vsi - replay VSI configuration
4945 * @hw: pointer to the HW struct
4946 * @vsi_handle: driver VSI handle
4948 * Restore all VSI configuration after reset. It is required to call this
4949 * function with main VSI first.
4951 int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
4955 if (!ice_is_vsi_valid(hw, vsi_handle))
4958 /* Replay pre-initialization if there is any */
4959 if (vsi_handle == ICE_MAIN_VSI_HANDLE) {
4960 status = ice_replay_pre_init(hw);
4964 /* Replay per VSI all RSS configurations */
4965 status = ice_replay_rss_cfg(hw, vsi_handle);
4968 /* Replay per VSI all filters */
4969 status = ice_replay_vsi_all_fltr(hw, vsi_handle);
4971 status = ice_replay_vsi_agg(hw, vsi_handle);
4976 * ice_replay_post - post replay configuration cleanup
4977 * @hw: pointer to the HW struct
4979 * Post replay cleanup.
4981 void ice_replay_post(struct ice_hw *hw)
4983 /* Delete old entries from replay filter list head */
4984 ice_rm_all_sw_replay_rule_info(hw);
4985 ice_sched_replay_agg(hw);
4989 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
4990 * @hw: ptr to the hardware info
4991 * @reg: offset of 64 bit HW register to read from
4992 * @prev_stat_loaded: bool to specify if previous stats are loaded
4993 * @prev_stat: ptr to previous loaded stat value
4994 * @cur_stat: ptr to current stat value
4997 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4998 u64 *prev_stat, u64 *cur_stat)
5000 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
5002 /* device stats are not reset at PFR, they likely will not be zeroed
5003 * when the driver starts. Thus, save the value from the first read
5004 * without adding to the statistic value so that we report stats which
5005 * count up from zero.
5007 if (!prev_stat_loaded) {
5008 *prev_stat = new_data;
5012 /* Calculate the difference between the new and old values, and then
5013 * add it to the software stat value.
5015 if (new_data >= *prev_stat)
5016 *cur_stat += new_data - *prev_stat;
5018 /* to manage the potential roll-over */
5019 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
5021 /* Update the previously stored value to prepare for next read */
5022 *prev_stat = new_data;
5026 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
5027 * @hw: ptr to the hardware info
5028 * @reg: offset of HW register to read from
5029 * @prev_stat_loaded: bool to specify if previous stats are loaded
5030 * @prev_stat: ptr to previous loaded stat value
5031 * @cur_stat: ptr to current stat value
5034 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
5035 u64 *prev_stat, u64 *cur_stat)
5039 new_data = rd32(hw, reg);
5041 /* device stats are not reset at PFR, they likely will not be zeroed
5042 * when the driver starts. Thus, save the value from the first read
5043 * without adding to the statistic value so that we report stats which
5044 * count up from zero.
5046 if (!prev_stat_loaded) {
5047 *prev_stat = new_data;
5051 /* Calculate the difference between the new and old values, and then
5052 * add it to the software stat value.
5054 if (new_data >= *prev_stat)
5055 *cur_stat += new_data - *prev_stat;
5057 /* to manage the potential roll-over */
5058 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
5060 /* Update the previously stored value to prepare for next read */
5061 *prev_stat = new_data;
5065 * ice_sched_query_elem - query element information from HW
5066 * @hw: pointer to the HW struct
5067 * @node_teid: node TEID to be queried
5068 * @buf: buffer to element information
5070 * This function queries HW element information
5073 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
5074 struct ice_aqc_txsched_elem_data *buf)
5076 u16 buf_size, num_elem_ret = 0;
5079 buf_size = sizeof(*buf);
5080 memset(buf, 0, buf_size);
5081 buf->node_teid = cpu_to_le32(node_teid);
5082 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
5084 if (status || num_elem_ret != 1)
5085 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
5091 * @hw: pointer to the hw struct
5092 * @topo_addr: topology address for a device to communicate with
5093 * @bus_addr: 7-bit I2C bus address
5094 * @addr: I2C memory address (I2C offset) with up to 16 bits
5095 * @params: I2C parameters: bit [7] - Repeated start,
5096 * bits [6:5] data offset size,
5097 * bit [4] - I2C address type,
5098 * bits [3:0] - data size to read (0-16 bytes)
5099 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device
5100 * @cd: pointer to command details structure or NULL
5105 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
5106 u16 bus_addr, __le16 addr, u8 params, u8 *data,
5107 struct ice_sq_cd *cd)
5109 struct ice_aq_desc desc = { 0 };
5110 struct ice_aqc_i2c *cmd;
5114 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c);
5115 cmd = &desc.params.read_write_i2c;
5120 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params);
5122 cmd->i2c_bus_addr = cpu_to_le16(bus_addr);
5123 cmd->topo_addr = topo_addr;
5124 cmd->i2c_params = params;
5125 cmd->i2c_addr = addr;
5127 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
5129 struct ice_aqc_read_i2c_resp *resp;
5132 resp = &desc.params.read_i2c_resp;
5133 for (i = 0; i < data_size; i++) {
5134 *data = resp->i2c_data[i];
5144 * @hw: pointer to the hw struct
5145 * @topo_addr: topology address for a device to communicate with
5146 * @bus_addr: 7-bit I2C bus address
5147 * @addr: I2C memory address (I2C offset) with up to 16 bits
5148 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes)
5149 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device
5150 * @cd: pointer to command details structure or NULL
5152 * Write I2C (0x06E3)
5155 * * 0 - Successful write to the i2c device
5156 * * -EINVAL - Data size greater than 4 bytes
5160 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
5161 u16 bus_addr, __le16 addr, u8 params, const u8 *data,
5162 struct ice_sq_cd *cd)
5164 struct ice_aq_desc desc = { 0 };
5165 struct ice_aqc_i2c *cmd;
5168 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c);
5169 cmd = &desc.params.read_write_i2c;
5171 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params);
5173 /* data_size limited to 4 */
5177 cmd->i2c_bus_addr = cpu_to_le16(bus_addr);
5178 cmd->topo_addr = topo_addr;
5179 cmd->i2c_params = params;
5180 cmd->i2c_addr = addr;
5182 memcpy(cmd->i2c_data, data, data_size);
5184 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
5188 * ice_aq_set_driver_param - Set driver parameter to share via firmware
5189 * @hw: pointer to the HW struct
5190 * @idx: parameter index to set
5191 * @value: the value to set the parameter to
5192 * @cd: pointer to command details structure or NULL
5194 * Set the value of one of the software defined parameters. All PFs connected
5195 * to this device can read the value using ice_aq_get_driver_param.
5197 * Note that firmware provides no synchronization or locking, and will not
5198 * save the parameter value during a device reset. It is expected that
5199 * a single PF will write the parameter value, while all other PFs will only
5203 ice_aq_set_driver_param(struct ice_hw *hw, enum ice_aqc_driver_params idx,
5204 u32 value, struct ice_sq_cd *cd)
5206 struct ice_aqc_driver_shared_params *cmd;
5207 struct ice_aq_desc desc;
5209 if (idx >= ICE_AQC_DRIVER_PARAM_MAX)
5212 cmd = &desc.params.drv_shared_params;
5214 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_shared_params);
5216 cmd->set_or_get_op = ICE_AQC_DRIVER_PARAM_SET;
5217 cmd->param_indx = idx;
5218 cmd->param_val = cpu_to_le32(value);
5220 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
5224 * ice_aq_get_driver_param - Get driver parameter shared via firmware
5225 * @hw: pointer to the HW struct
5226 * @idx: parameter index to set
5227 * @value: storage to return the shared parameter
5228 * @cd: pointer to command details structure or NULL
5230 * Get the value of one of the software defined parameters.
5232 * Note that firmware provides no synchronization or locking. It is expected
5233 * that only a single PF will write a given parameter.
5236 ice_aq_get_driver_param(struct ice_hw *hw, enum ice_aqc_driver_params idx,
5237 u32 *value, struct ice_sq_cd *cd)
5239 struct ice_aqc_driver_shared_params *cmd;
5240 struct ice_aq_desc desc;
5243 if (idx >= ICE_AQC_DRIVER_PARAM_MAX)
5246 cmd = &desc.params.drv_shared_params;
5248 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_shared_params);
5250 cmd->set_or_get_op = ICE_AQC_DRIVER_PARAM_GET;
5251 cmd->param_indx = idx;
5253 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
5257 *value = le32_to_cpu(cmd->param_val);
5264 * @hw: pointer to the hw struct
5265 * @gpio_ctrl_handle: GPIO controller node handle
5266 * @pin_idx: IO Number of the GPIO that needs to be set
5267 * @value: SW provide IO value to set in the LSB
5268 * @cd: pointer to command details structure or NULL
5270 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology
5273 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value,
5274 struct ice_sq_cd *cd)
5276 struct ice_aqc_gpio *cmd;
5277 struct ice_aq_desc desc;
5279 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio);
5280 cmd = &desc.params.read_write_gpio;
5281 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle);
5282 cmd->gpio_num = pin_idx;
5283 cmd->gpio_val = value ? 1 : 0;
5285 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
5290 * @hw: pointer to the hw struct
5291 * @gpio_ctrl_handle: GPIO controller node handle
5292 * @pin_idx: IO Number of the GPIO that needs to be set
5293 * @value: IO value read
5294 * @cd: pointer to command details structure or NULL
5296 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of
5300 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,
5301 bool *value, struct ice_sq_cd *cd)
5303 struct ice_aqc_gpio *cmd;
5304 struct ice_aq_desc desc;
5307 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio);
5308 cmd = &desc.params.read_write_gpio;
5309 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle);
5310 cmd->gpio_num = pin_idx;
5312 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
5316 *value = !!cmd->gpio_val;
5321 * ice_is_fw_api_min_ver
5322 * @hw: pointer to the hardware structure
5323 * @maj: major version
5324 * @min: minor version
5325 * @patch: patch version
5327 * Checks if the firmware API is minimum version
5329 static bool ice_is_fw_api_min_ver(struct ice_hw *hw, u8 maj, u8 min, u8 patch)
5331 if (hw->api_maj_ver == maj) {
5332 if (hw->api_min_ver > min)
5334 if (hw->api_min_ver == min && hw->api_patch >= patch)
5336 } else if (hw->api_maj_ver > maj) {
5344 * ice_fw_supports_link_override
5345 * @hw: pointer to the hardware structure
5347 * Checks if the firmware supports link override
5349 bool ice_fw_supports_link_override(struct ice_hw *hw)
5351 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LINK_OVERRIDE_MAJ,
5352 ICE_FW_API_LINK_OVERRIDE_MIN,
5353 ICE_FW_API_LINK_OVERRIDE_PATCH);
5357 * ice_get_link_default_override
5358 * @ldo: pointer to the link default override struct
5359 * @pi: pointer to the port info struct
5361 * Gets the link default override for a port
5364 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
5365 struct ice_port_info *pi)
5367 u16 i, tlv, tlv_len, tlv_start, buf, offset;
5368 struct ice_hw *hw = pi->hw;
5371 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len,
5372 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR);
5374 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n");
5378 /* Each port has its own config; calculate for our port */
5379 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS +
5380 ICE_SR_PFA_LINK_OVERRIDE_OFFSET;
5382 /* link options first */
5383 status = ice_read_sr_word(hw, tlv_start, &buf);
5385 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
5388 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M;
5389 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >>
5390 ICE_LINK_OVERRIDE_PHY_CFG_S;
5392 /* link PHY config */
5393 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET;
5394 status = ice_read_sr_word(hw, offset, &buf);
5396 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n");
5399 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M;
5402 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET;
5403 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
5404 status = ice_read_sr_word(hw, (offset + i), &buf);
5406 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
5409 /* shift 16 bits at a time to fill 64 bits */
5410 ldo->phy_type_low |= ((u64)buf << (i * 16));
5413 /* PHY types high */
5414 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET +
5415 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS;
5416 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
5417 status = ice_read_sr_word(hw, (offset + i), &buf);
5419 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
5422 /* shift 16 bits at a time to fill 64 bits */
5423 ldo->phy_type_high |= ((u64)buf << (i * 16));
5430 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled
5431 * @caps: get PHY capability data
5433 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps)
5435 if (caps->caps & ICE_AQC_PHY_AN_MODE ||
5436 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 |
5437 ICE_AQC_PHY_AN_EN_CLAUSE73 |
5438 ICE_AQC_PHY_AN_EN_CLAUSE37))
5445 * ice_aq_set_lldp_mib - Set the LLDP MIB
5446 * @hw: pointer to the HW struct
5447 * @mib_type: Local, Remote or both Local and Remote MIBs
5448 * @buf: pointer to the caller-supplied buffer to store the MIB block
5449 * @buf_size: size of the buffer (in bytes)
5450 * @cd: pointer to command details structure or NULL
5452 * Set the LLDP MIB. (0x0A08)
5455 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
5456 struct ice_sq_cd *cd)
5458 struct ice_aqc_lldp_set_local_mib *cmd;
5459 struct ice_aq_desc desc;
5461 cmd = &desc.params.lldp_set_mib;
5463 if (buf_size == 0 || !buf)
5466 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib);
5468 desc.flags |= cpu_to_le16((u16)ICE_AQ_FLAG_RD);
5469 desc.datalen = cpu_to_le16(buf_size);
5471 cmd->type = mib_type;
5472 cmd->length = cpu_to_le16(buf_size);
5474 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
5478 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl
5479 * @hw: pointer to HW struct
5481 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw)
5483 if (hw->mac_type != ICE_MAC_E810)
5486 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LLDP_FLTR_MAJ,
5487 ICE_FW_API_LLDP_FLTR_MIN,
5488 ICE_FW_API_LLDP_FLTR_PATCH);
5492 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter
5493 * @hw: pointer to HW struct
5494 * @vsi_num: absolute HW index for VSI
5495 * @add: boolean for if adding or removing a filter
5498 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add)
5500 struct ice_aqc_lldp_filter_ctrl *cmd;
5501 struct ice_aq_desc desc;
5503 cmd = &desc.params.lldp_filter_ctrl;
5505 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl);
5508 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD;
5510 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE;
5512 cmd->vsi_num = cpu_to_le16(vsi_num);
5514 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5518 * ice_lldp_execute_pending_mib - execute LLDP pending MIB request
5519 * @hw: pointer to HW struct
5521 int ice_lldp_execute_pending_mib(struct ice_hw *hw)
5523 struct ice_aq_desc desc;
5525 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_execute_pending_mib);
5527 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5531 * ice_fw_supports_report_dflt_cfg
5532 * @hw: pointer to the hardware structure
5534 * Checks if the firmware supports report default configuration
5536 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw)
5538 return ice_is_fw_api_min_ver(hw, ICE_FW_API_REPORT_DFLT_CFG_MAJ,
5539 ICE_FW_API_REPORT_DFLT_CFG_MIN,
5540 ICE_FW_API_REPORT_DFLT_CFG_PATCH);
5543 /* each of the indexes into the following array match the speed of a return
5544 * value from the list of AQ returned speeds like the range:
5545 * ICE_AQ_LINK_SPEED_10MB .. ICE_AQ_LINK_SPEED_100GB excluding
5546 * ICE_AQ_LINK_SPEED_UNKNOWN which is BIT(15) and maps to BIT(14) in this
5547 * array. The array is defined as 15 elements long because the link_speed
5548 * returned by the firmware is a 16 bit * value, but is indexed
5549 * by [fls(speed) - 1]
5551 static const u32 ice_aq_to_link_speed[] = {
5552 SPEED_10, /* BIT(0) */
5562 SPEED_100000, /* BIT(10) */
5566 * ice_get_link_speed - get integer speed from table
5567 * @index: array index from fls(aq speed) - 1
5569 * Returns: u32 value containing integer speed
5571 u32 ice_get_link_speed(u16 index)
5573 if (index >= ARRAY_SIZE(ice_aq_to_link_speed))
5576 return ice_aq_to_link_speed[index];