1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Intel Corporation. */
4 #ifndef _ICE_ADMINQ_CMD_H_
5 #define _ICE_ADMINQ_CMD_H_
7 /* This header file defines the Admin Queue commands, error codes and
8 * descriptor format. It is shared between Firmware and Software.
11 #define ICE_MAX_VSI 768
12 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9
13 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728
15 struct ice_aqc_generic {
22 /* Get version (direct 0x0001) */
23 struct ice_aqc_get_ver {
36 /* Send driver version (indirect 0x0002) */
37 struct ice_aqc_driver_ver {
47 /* Queue Shutdown (direct 0x0003) */
48 struct ice_aqc_q_shutdown {
50 #define ICE_AQC_DRIVER_UNLOADING BIT(0)
54 /* Request resource ownership (direct 0x0008)
55 * Release resource ownership (direct 0x0009)
57 struct ice_aqc_req_res {
59 #define ICE_AQC_RES_ID_NVM 1
60 #define ICE_AQC_RES_ID_SDP 2
61 #define ICE_AQC_RES_ID_CHNG_LOCK 3
62 #define ICE_AQC_RES_ID_GLBL_LOCK 4
64 #define ICE_AQC_RES_ACCESS_READ 1
65 #define ICE_AQC_RES_ACCESS_WRITE 2
67 /* Upon successful completion, FW writes this value and driver is
68 * expected to release resource before timeout. This value is provided
72 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000
73 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000
74 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000
75 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000
76 /* For SDP: pin ID of the SDP */
78 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */
80 #define ICE_AQ_RES_GLBL_SUCCESS 0
81 #define ICE_AQ_RES_GLBL_IN_PROG 1
82 #define ICE_AQ_RES_GLBL_DONE 2
86 /* Get function capabilities (indirect 0x000A)
87 * Get device capabilities (indirect 0x000B)
89 struct ice_aqc_list_caps {
98 /* Device/Function buffer entry, repeated per reported capability */
99 struct ice_aqc_list_caps_elem {
101 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005
102 #define ICE_AQC_CAPS_SRIOV 0x0012
103 #define ICE_AQC_CAPS_VF 0x0013
104 #define ICE_AQC_CAPS_VSI 0x0017
105 #define ICE_AQC_CAPS_DCB 0x0018
106 #define ICE_AQC_CAPS_RSS 0x0040
107 #define ICE_AQC_CAPS_RXQS 0x0041
108 #define ICE_AQC_CAPS_TXQS 0x0042
109 #define ICE_AQC_CAPS_MSIX 0x0043
110 #define ICE_AQC_CAPS_FD 0x0045
111 #define ICE_AQC_CAPS_1588 0x0046
112 #define ICE_AQC_CAPS_MAX_MTU 0x0047
113 #define ICE_AQC_CAPS_NVM_VER 0x0048
114 #define ICE_AQC_CAPS_PENDING_NVM_VER 0x0049
115 #define ICE_AQC_CAPS_OROM_VER 0x004A
116 #define ICE_AQC_CAPS_PENDING_OROM_VER 0x004B
117 #define ICE_AQC_CAPS_NET_VER 0x004C
118 #define ICE_AQC_CAPS_PENDING_NET_VER 0x004D
119 #define ICE_AQC_CAPS_RDMA 0x0051
120 #define ICE_AQC_CAPS_NVM_MGMT 0x0080
124 /* Number of resources described by this capability */
126 /* Only meaningful for some types of resources */
128 /* Only meaningful for some types of resources */
134 /* Manage MAC address, read command - indirect (0x0107)
135 * This struct is also used for the response
137 struct ice_aqc_manage_mac_read {
138 __le16 flags; /* Zeroed by device driver */
139 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4)
140 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5)
141 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6)
142 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7)
143 #define ICE_AQC_MAN_MAC_READ_S 4
144 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S)
146 u8 num_addr; /* Used in response */
152 /* Response buffer format for manage MAC read command */
153 struct ice_aqc_manage_mac_read_resp {
156 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0
157 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1
158 u8 mac_addr[ETH_ALEN];
161 /* Manage MAC address, write command - direct (0x0108) */
162 struct ice_aqc_manage_mac_write {
165 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0)
166 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1)
167 #define ICE_AQC_MAN_MAC_WR_S 6
168 #define ICE_AQC_MAN_MAC_WR_M ICE_M(3, ICE_AQC_MAN_MAC_WR_S)
169 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0
170 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S)
171 /* byte stream in network order */
172 u8 mac_addr[ETH_ALEN];
177 /* Clear PXE Command and response (direct 0x0110) */
178 struct ice_aqc_clear_pxe {
180 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2
184 /* Get switch configuration (0x0200) */
185 struct ice_aqc_get_sw_cfg {
186 /* Reserved for command and copy of request flags for response */
188 /* First desc in case of command and next_elem in case of response
189 * In case of response, if it is not zero, means all the configuration
190 * was not returned and new command shall be sent with this value in
191 * the 'first desc' field
194 /* Reserved for command, only used for response */
201 /* Each entry in the response buffer is of the following type: */
202 struct ice_aqc_get_sw_cfg_resp_elem {
203 /* VSI/Port Number */
205 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0
206 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \
207 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)
208 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14
209 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)
210 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0
211 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1
212 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2
214 /* SWID VSI/Port belongs to */
217 /* Bit 14..0 : PF/VF number VSI belongs to
218 * Bit 15 : VF indication bit
221 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0
222 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \
223 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)
224 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15)
227 /* These resource type defines are used for all switch resource
228 * commands where a resource type is required, such as:
229 * Get Resource Allocation command (indirect 0x0204)
230 * Allocate Resources command (indirect 0x0208)
231 * Free Resources command (indirect 0x0209)
232 * Get Allocated Resource Descriptors Command (indirect 0x020A)
234 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03
235 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04
236 #define ICE_AQC_RES_TYPE_RECIPE 0x05
237 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21
238 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22
239 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23
240 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58
241 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59
242 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60
243 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61
245 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7)
246 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12)
247 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13)
249 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00
251 #define ICE_AQC_RES_TYPE_S 0
252 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S)
254 /* Allocate Resources command (indirect 0x0208)
255 * Free Resources command (indirect 0x0209)
257 struct ice_aqc_alloc_free_res_cmd {
258 __le16 num_entries; /* Number of Resource entries */
264 /* Resource descriptor */
265 struct ice_aqc_res_elem {
272 /* Buffer for Allocate/Free Resources commands */
273 struct ice_aqc_alloc_free_res_elem {
274 __le16 res_type; /* Types defined above cmd 0x0204 */
275 #define ICE_AQC_RES_TYPE_SHARED_S 7
276 #define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S)
277 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8
278 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \
279 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)
281 struct ice_aqc_res_elem elem[];
284 /* Add VSI (indirect 0x0210)
285 * Update VSI (indirect 0x0211)
286 * Get VSI (indirect 0x0212)
287 * Free VSI (indirect 0x0213)
289 struct ice_aqc_add_get_update_free_vsi {
291 #define ICE_AQ_VSI_NUM_S 0
292 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S)
293 #define ICE_AQ_VSI_IS_VALID BIT(15)
295 #define ICE_AQ_VSI_KEEP_ALLOC 0x1
299 #define ICE_AQ_VSI_TYPE_S 0
300 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S)
301 #define ICE_AQ_VSI_TYPE_VF 0x0
302 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1
303 #define ICE_AQ_VSI_TYPE_PF 0x2
304 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3
309 /* Response descriptor for:
310 * Add VSI (indirect 0x0210)
311 * Update VSI (indirect 0x0211)
312 * Free VSI (indirect 0x0213)
314 struct ice_aqc_add_update_free_vsi_resp {
323 struct ice_aqc_vsi_props {
324 __le16 valid_sections;
325 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0)
326 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1)
327 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2)
328 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3)
329 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4)
330 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5)
331 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6)
332 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7)
333 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8)
334 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11)
335 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12)
339 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5)
340 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6)
341 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7)
343 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0
344 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \
345 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
346 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0)
347 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4)
349 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0
350 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)
351 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5)
352 /* security section */
354 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0)
355 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2)
356 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4
357 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)
358 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0)
361 __le16 pvid; /* VLANS include priority bits */
362 u8 pvlan_reserved[2];
364 #define ICE_AQ_VSI_VLAN_MODE_S 0
365 #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S)
366 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1
367 #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2
368 #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3
369 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2)
370 #define ICE_AQ_VSI_VLAN_EMOD_S 3
371 #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
372 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S)
373 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S)
374 #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S)
375 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
376 u8 pvlan_reserved2[3];
377 /* ingress egress up sections */
378 __le32 ingress_table; /* bitmap, 3 bits per up */
379 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0
380 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)
381 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3
382 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)
383 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6
384 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)
385 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9
386 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)
387 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12
388 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)
389 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15
390 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)
391 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18
392 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)
393 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21
394 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)
395 __le32 egress_table; /* same defines as for ingress table */
396 /* outer tags section */
399 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0
400 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S)
401 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0
402 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1
403 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2
404 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2
405 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)
406 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0
407 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1
408 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2
409 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3
410 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4)
411 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6)
412 u8 outer_tag_reserved;
413 /* queue mapping section */
414 __le16 mapping_flags;
415 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0
416 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0)
417 __le16 q_mapping[16];
418 #define ICE_AQ_VSI_Q_S 0
419 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S)
420 __le16 tc_mapping[8];
421 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0
422 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)
423 #define ICE_AQ_VSI_TC_Q_NUM_S 11
424 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S)
425 /* queueing option section */
427 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0
428 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)
429 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0
430 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2
431 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3
432 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2
433 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)
434 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6
435 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
436 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
437 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
438 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
439 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
441 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0
442 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)
443 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7)
445 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0)
446 u8 q_opt_reserved[3];
447 /* outer up section */
448 __le32 outer_up_table; /* same structure and defines as ingress tbl */
450 __le16 sect_10_reserved;
451 /* flow director section */
453 #define ICE_AQ_VSI_FD_ENABLE BIT(0)
454 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1)
455 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3)
456 __le16 max_fd_fltr_dedicated;
457 __le16 max_fd_fltr_shared;
459 #define ICE_AQ_VSI_FD_DEF_Q_S 0
460 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)
461 #define ICE_AQ_VSI_FD_DEF_GRP_S 12
462 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)
463 __le16 fd_report_opt;
464 #define ICE_AQ_VSI_FD_REPORT_Q_S 0
465 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)
466 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12
467 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)
468 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15)
471 #define ICE_AQ_VSI_PASID_ID_S 0
472 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S)
473 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31)
477 #define ICE_MAX_NUM_RECIPES 64
479 /* Add/Get Recipe (indirect 0x0290/0x0292) */
480 struct ice_aqc_add_get_recipe {
481 __le16 num_sub_recipes; /* Input in Add cmd, Output in Get cmd */
482 __le16 return_index; /* Input, used for Get cmd only */
488 struct ice_aqc_recipe_content {
490 #define ICE_AQ_RECIPE_ID_IS_ROOT BIT(7)
491 #define ICE_AQ_SW_ID_LKUP_IDX 0
493 #define ICE_AQ_RECIPE_LKUP_IGNORE BIT(7)
494 #define ICE_AQ_SW_ID_LKUP_MASK 0x00FF
497 #define ICE_AQ_RECIPE_RESULT_DATA_S 0
498 #define ICE_AQ_RECIPE_RESULT_DATA_M (0x3F << ICE_AQ_RECIPE_RESULT_DATA_S)
499 #define ICE_AQ_RECIPE_RESULT_EN BIT(7)
501 u8 act_ctrl_join_priority;
502 u8 act_ctrl_fwd_priority;
504 #define ICE_AQ_RECIPE_ACT_INV_ACT BIT(2)
509 struct ice_aqc_recipe_data_elem {
515 struct ice_aqc_recipe_content content;
519 /* Set/Get Recipes to Profile Association (direct 0x0291/0x0293) */
520 struct ice_aqc_recipe_to_profile {
523 DECLARE_BITMAP(recipe_assoc, ICE_MAX_NUM_RECIPES);
526 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)
528 struct ice_aqc_sw_rules {
529 /* ops: add switch rules, referring the number of rules.
530 * ops: update switch rules, referring the number of filters
531 * ops: remove switch rules, referring the entry index.
532 * ops: get switch rules, referring to the number of filters.
534 __le16 num_rules_fltr_entry_index;
540 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry
541 * This structures describes the lookup rules and associated actions. "index"
542 * is returned as part of a response to a successful Add command, and can be
543 * used to identify the rule for Update/Get/Remove commands.
545 struct ice_sw_rule_lkup_rx_tx {
547 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10
548 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */
552 /* Bit 0:1 - Action type */
553 #define ICE_SINGLE_ACT_TYPE_S 0x00
554 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S)
556 /* Bit 2 - Loop back enable
559 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2)
560 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3)
562 /* Action type = 0 - Forward to VSI or VSI list */
563 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0
565 #define ICE_SINGLE_ACT_VSI_ID_S 4
566 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S)
567 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4
568 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)
569 /* This bit needs to be set if action is forward to VSI list */
570 #define ICE_SINGLE_ACT_VSI_LIST BIT(14)
571 #define ICE_SINGLE_ACT_VALID_BIT BIT(17)
572 #define ICE_SINGLE_ACT_DROP BIT(18)
574 /* Action type = 1 - Forward to Queue of Queue group */
575 #define ICE_SINGLE_ACT_TO_Q 0x1
576 #define ICE_SINGLE_ACT_Q_INDEX_S 4
577 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)
578 #define ICE_SINGLE_ACT_Q_REGION_S 15
579 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S)
580 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18)
582 /* Action type = 2 - Prune */
583 #define ICE_SINGLE_ACT_PRUNE 0x2
584 #define ICE_SINGLE_ACT_EGRESS BIT(15)
585 #define ICE_SINGLE_ACT_INGRESS BIT(16)
586 #define ICE_SINGLE_ACT_PRUNET BIT(17)
587 /* Bit 18 should be set to 0 for this action */
589 /* Action type = 2 - Pointer */
590 #define ICE_SINGLE_ACT_PTR 0x2
591 #define ICE_SINGLE_ACT_PTR_VAL_S 4
592 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
593 /* Bit 18 should be set to 1 */
594 #define ICE_SINGLE_ACT_PTR_BIT BIT(18)
596 /* Action type = 3 - Other actions. Last two bits
597 * are other action identifier
599 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3
600 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17
601 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \
602 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)
604 /* Bit 17:18 - Defines other actions */
605 /* Other action = 0 - Mirror VSI */
606 #define ICE_SINGLE_OTHER_ACT_MIRROR 0
607 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4
608 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \
609 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)
611 /* Other action = 3 - Set Stat count */
612 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3
613 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4
614 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \
615 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)
617 __le16 index; /* The index of the rule in the lookup table */
618 /* Length and values of the header to be matched per recipe or
625 /* Add/Update/Remove large action command/response entry
626 * "index" is returned as part of a response to a successful Add command, and
627 * can be used to identify the action for Update/Get/Remove commands.
629 struct ice_sw_rule_lg_act {
630 __le16 index; /* Index in large action table */
632 /* Max number of large actions */
633 #define ICE_MAX_LG_ACT 4
634 /* Bit 0:1 - Action type */
635 #define ICE_LG_ACT_TYPE_S 0
636 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S)
638 /* Action type = 0 - Forward to VSI or VSI list */
639 #define ICE_LG_ACT_VSI_FORWARDING 0
640 #define ICE_LG_ACT_VSI_ID_S 3
641 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S)
642 #define ICE_LG_ACT_VSI_LIST_ID_S 3
643 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)
644 /* This bit needs to be set if action is forward to VSI list */
645 #define ICE_LG_ACT_VSI_LIST BIT(13)
647 #define ICE_LG_ACT_VALID_BIT BIT(16)
649 /* Action type = 1 - Forward to Queue of Queue group */
650 #define ICE_LG_ACT_TO_Q 0x1
651 #define ICE_LG_ACT_Q_INDEX_S 3
652 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S)
653 #define ICE_LG_ACT_Q_REGION_S 14
654 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S)
655 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17)
657 /* Action type = 2 - Prune */
658 #define ICE_LG_ACT_PRUNE 0x2
659 #define ICE_LG_ACT_EGRESS BIT(14)
660 #define ICE_LG_ACT_INGRESS BIT(15)
661 #define ICE_LG_ACT_PRUNET BIT(16)
663 /* Action type = 3 - Mirror VSI */
664 #define ICE_LG_OTHER_ACT_MIRROR 0x3
665 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3
666 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)
668 /* Action type = 5 - Generic Value */
669 #define ICE_LG_ACT_GENERIC 0x5
670 #define ICE_LG_ACT_GENERIC_VALUE_S 3
671 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)
672 #define ICE_LG_ACT_GENERIC_OFFSET_S 19
673 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)
674 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22
675 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)
676 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7
678 /* Action = 7 - Set Stat count */
679 #define ICE_LG_ACT_STAT_COUNT 0x7
680 #define ICE_LG_ACT_STAT_COUNT_S 3
681 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S)
682 __le32 act[]; /* array of size for actions */
685 /* Add/Update/Remove VSI list command/response entry
686 * "index" is returned as part of a response to a successful Add command, and
687 * can be used to identify the VSI list for Update/Get/Remove commands.
689 struct ice_sw_rule_vsi_list {
690 __le16 index; /* Index of VSI/Prune list */
692 __le16 vsi[]; /* Array of number_vsi VSI numbers */
695 /* Query VSI list command/response entry */
696 struct ice_sw_rule_vsi_list_query {
698 DECLARE_BITMAP(vsi_list, ICE_MAX_VSI);
701 /* Add switch rule response:
702 * Content of return buffer is same as the input buffer. The status field and
703 * LUT index are updated as part of the response
705 struct ice_aqc_sw_rules_elem {
706 __le16 type; /* Switch rule type, one of T_... */
707 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0
708 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1
709 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2
710 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3
711 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4
712 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5
713 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6
716 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx;
717 struct ice_sw_rule_lg_act lg_act;
718 struct ice_sw_rule_vsi_list vsi_list;
719 struct ice_sw_rule_vsi_list_query vsi_list_query;
723 /* Query PFC Mode (direct 0x0302)
724 * Set PFC Mode (direct 0x0303)
726 struct ice_aqc_set_query_pfc_mode {
728 /* For Query Command response, reserved in all other cases */
729 #define ICE_AQC_PFC_VLAN_BASED_PFC 1
730 #define ICE_AQC_PFC_DSCP_BASED_PFC 2
733 /* Get Default Topology (indirect 0x0400) */
734 struct ice_aqc_get_topo {
743 /* Update TSE (indirect 0x0403)
744 * Get TSE (indirect 0x0404)
745 * Add TSE (indirect 0x0401)
746 * Delete TSE (indirect 0x040F)
747 * Move TSE (indirect 0x0408)
748 * Suspend Nodes (indirect 0x0409)
749 * Resume Nodes (indirect 0x040A)
751 struct ice_aqc_sched_elem_cmd {
752 __le16 num_elem_req; /* Used by commands */
753 __le16 num_elem_resp; /* Used by responses */
759 struct ice_aqc_txsched_move_grp_info_hdr {
760 __le32 src_parent_teid;
761 __le32 dest_parent_teid;
766 struct ice_aqc_move_elem {
767 struct ice_aqc_txsched_move_grp_info_hdr hdr;
771 struct ice_aqc_elem_info_bw {
772 __le16 bw_profile_idx;
776 struct ice_aqc_txsched_elem {
777 u8 elem_type; /* Special field, reserved for some aq calls */
778 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0
779 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1
780 #define ICE_AQC_ELEM_TYPE_TC 0x2
781 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3
782 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4
783 #define ICE_AQC_ELEM_TYPE_LEAF 0x5
784 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6
786 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0)
787 #define ICE_AQC_ELEM_VALID_CIR BIT(1)
788 #define ICE_AQC_ELEM_VALID_EIR BIT(2)
789 #define ICE_AQC_ELEM_VALID_SHARED BIT(3)
791 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1
792 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1
793 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S)
794 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4
795 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S)
796 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5
797 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \
798 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)
799 u8 flags; /* Special field, reserved for some aq calls */
800 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1
801 struct ice_aqc_elem_info_bw cir_bw;
802 struct ice_aqc_elem_info_bw eir_bw;
807 struct ice_aqc_txsched_elem_data {
810 struct ice_aqc_txsched_elem data;
813 struct ice_aqc_txsched_topo_grp_info_hdr {
819 struct ice_aqc_add_elem {
820 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
821 struct ice_aqc_txsched_elem_data generic[];
824 struct ice_aqc_get_topo_elem {
825 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
826 struct ice_aqc_txsched_elem_data
827 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM];
830 struct ice_aqc_delete_elem {
831 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
835 /* Query Port ETS (indirect 0x040E)
837 * This indirect command is used to query port TC node configuration.
839 struct ice_aqc_query_port_ets {
846 struct ice_aqc_port_ets_elem {
849 /* 3 bits for UP per TC 0-7, 4th byte reserved */
852 __le32 port_eir_prof_id;
853 __le32 port_cir_prof_id;
854 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */
856 #define ICE_TC_NODE_PRIO_S 0x4
858 __le32 tc_node_teid[8]; /* Used for response, reserved in command */
861 /* Rate limiting profile for
862 * Add RL profile (indirect 0x0410)
863 * Query RL profile (indirect 0x0411)
864 * Remove RL profile (indirect 0x0415)
865 * These indirect commands acts on single or multiple
866 * RL profiles with specified data.
868 struct ice_aqc_rl_profile {
870 __le16 num_processed; /* Only for response. Reserved in Command. */
876 struct ice_aqc_rl_profile_elem {
879 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0
880 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S)
881 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0
882 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1
883 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2
884 /* The following flag is used for Query RL Profile Data */
885 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7
886 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S)
889 __le16 max_burst_size;
895 /* Query Scheduler Resource Allocation (indirect 0x0412)
896 * This indirect command retrieves the scheduler resources allocated by
897 * EMP Firmware to the given PF.
899 struct ice_aqc_query_txsched_res {
905 struct ice_aqc_generic_sched_props {
907 __le16 logical_levels;
908 u8 flattening_bitmap;
916 struct ice_aqc_layer_props {
919 __le16 max_device_nodes;
922 __le16 max_sibl_grp_sz;
923 __le16 max_cir_rl_profiles;
924 __le16 max_eir_rl_profiles;
925 __le16 max_srl_profiles;
929 struct ice_aqc_query_txsched_res_resp {
930 struct ice_aqc_generic_sched_props sched_props;
931 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];
934 /* Get PHY capabilities (indirect 0x0600) */
935 struct ice_aqc_get_phy_caps {
939 /* 18.0 - Report qualified modules */
940 #define ICE_AQC_GET_PHY_RQM BIT(0)
941 /* 18.1 - 18.3 : Report mode
942 * 000b - Report NVM capabilities
943 * 001b - Report topology capabilities
944 * 010b - Report SW configured
945 * 100b - Report default capabilities
947 #define ICE_AQC_REPORT_MODE_S 1
948 #define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S)
949 #define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0
950 #define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1)
951 #define ICE_AQC_REPORT_ACTIVE_CFG BIT(2)
952 #define ICE_AQC_REPORT_DFLT_CFG BIT(3)
958 /* This is #define of PHY type (Extended):
959 * The first set of defines is for phy_type_low.
961 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
962 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
963 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
964 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3)
965 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4)
966 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5)
967 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
968 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
969 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
970 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9)
971 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)
972 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)
973 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)
974 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13)
975 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14)
976 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15)
977 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16)
978 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17)
979 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18)
980 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19)
981 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20)
982 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21)
983 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22)
984 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23)
985 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24)
986 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25)
987 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26)
988 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27)
989 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28)
990 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29)
991 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30)
992 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31)
993 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32)
994 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33)
995 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34)
996 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35)
997 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36)
998 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37)
999 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38)
1000 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39)
1001 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40)
1002 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41)
1003 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42)
1004 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43)
1005 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44)
1006 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45)
1007 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46)
1008 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47)
1009 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48)
1010 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49)
1011 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50)
1012 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51)
1013 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52)
1014 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53)
1015 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54)
1016 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55)
1017 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56)
1018 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57)
1019 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58)
1020 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59)
1021 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60)
1022 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61)
1023 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62)
1024 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63)
1025 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63
1026 /* The second set of defines is for phy_type_high. */
1027 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0)
1028 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1)
1029 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
1030 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3)
1031 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4)
1032 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 5
1034 struct ice_aqc_get_phy_caps_data {
1035 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1036 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1038 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0)
1039 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1)
1040 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2)
1041 #define ICE_AQC_PHY_EN_LINK BIT(3)
1042 #define ICE_AQC_PHY_AN_MODE BIT(4)
1043 #define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5)
1044 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7)
1045 #define ICE_AQC_PHY_CAPS_MASK ICE_M(0xff, 0)
1046 u8 low_power_ctrl_an;
1047 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0)
1048 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1)
1049 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2)
1050 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3)
1052 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0)
1053 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1)
1054 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2)
1055 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3)
1056 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4)
1057 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5)
1058 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6)
1060 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */
1062 u8 link_fec_options;
1063 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0)
1064 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1)
1065 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2)
1066 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3)
1067 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4)
1068 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6)
1069 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7)
1070 #define ICE_AQC_PHY_FEC_MASK ICE_M(0xdf, 0)
1071 u8 module_compliance_enforcement;
1072 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0)
1073 u8 extended_compliance_code;
1074 #define ICE_MODULE_TYPE_TOTAL_BYTE 3
1075 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
1076 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0
1077 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80
1078 #define ICE_AQC_MOD_TYPE_IDENT 1
1079 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0)
1080 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1)
1081 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4)
1082 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5)
1083 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6)
1084 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7)
1085 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0
1086 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86
1087 u8 qualified_module_count;
1088 u8 rsvd2[7]; /* Bytes 47:41 reserved */
1089 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16
1096 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];
1099 /* Set PHY capabilities (direct 0x0601)
1100 * NOTE: This command must be followed by setup link and restart auto-neg
1102 struct ice_aqc_set_phy_cfg {
1109 /* Set PHY config command data structure */
1110 struct ice_aqc_set_phy_cfg_data {
1111 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1112 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1114 #define ICE_AQ_PHY_ENA_VALID_MASK ICE_M(0xef, 0)
1115 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0)
1116 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1)
1117 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2)
1118 #define ICE_AQ_PHY_ENA_LINK BIT(3)
1119 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5)
1120 #define ICE_AQ_PHY_ENA_LESM BIT(6)
1121 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7)
1122 u8 low_power_ctrl_an;
1123 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */
1125 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */
1126 u8 module_compliance_enforcement;
1129 /* Set MAC Config command data structure (direct 0x0603) */
1130 struct ice_aqc_set_mac_cfg {
1131 __le16 max_frame_size;
1133 #define ICE_AQ_SET_MAC_PACE_S 3
1134 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S)
1135 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7)
1136 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0
1137 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M
1139 __le16 tx_tmr_value;
1140 __le16 fc_refresh_threshold;
1142 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0)
1143 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0
1144 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0)
1148 /* Restart AN command data structure (direct 0x0605)
1149 * Also used for response, with only the lport_num field present.
1151 struct ice_aqc_restart_an {
1155 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1)
1156 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2)
1160 /* Get link status (indirect 0x0607), also used for Link Status Event */
1161 struct ice_aqc_get_link_status {
1165 #define ICE_AQ_LSE_M 0x3
1166 #define ICE_AQ_LSE_NOP 0x0
1167 #define ICE_AQ_LSE_DIS 0x2
1168 #define ICE_AQ_LSE_ENA 0x3
1169 /* only response uses this flag */
1170 #define ICE_AQ_LSE_IS_ENABLED 0x1
1176 /* Get link status response data structure, also used for Link Status Event */
1177 struct ice_aqc_get_link_status_data {
1178 u8 topo_media_conflict;
1179 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0)
1180 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1)
1181 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2)
1182 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4)
1183 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5)
1184 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6)
1185 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7)
1187 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5)
1188 #define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT BIT(7)
1190 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */
1191 #define ICE_AQ_LINK_FAULT BIT(1)
1192 #define ICE_AQ_LINK_FAULT_TX BIT(2)
1193 #define ICE_AQ_LINK_FAULT_RX BIT(3)
1194 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4)
1195 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */
1196 #define ICE_AQ_MEDIA_AVAILABLE BIT(6)
1197 #define ICE_AQ_SIGNAL_DETECT BIT(7)
1199 #define ICE_AQ_AN_COMPLETED BIT(0)
1200 #define ICE_AQ_LP_AN_ABILITY BIT(1)
1201 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */
1202 #define ICE_AQ_FEC_EN BIT(3)
1203 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */
1204 #define ICE_AQ_LINK_PAUSE_TX BIT(5)
1205 #define ICE_AQ_LINK_PAUSE_RX BIT(6)
1206 #define ICE_AQ_QUALIFIED_MODULE BIT(7)
1208 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0)
1209 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */
1210 /* Port Tx Suspended */
1211 #define ICE_AQ_LINK_TX_S 2
1212 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S)
1213 #define ICE_AQ_LINK_TX_ACTIVE 0
1214 #define ICE_AQ_LINK_TX_DRAINED 1
1215 #define ICE_AQ_LINK_TX_FLUSHED 3
1217 __le16 max_frame_size;
1219 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0)
1220 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1)
1221 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2)
1222 #define ICE_AQ_FEC_MASK ICE_M(0x7, 0)
1224 #define ICE_AQ_CFG_PACING_S 3
1225 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S)
1226 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7)
1227 #define ICE_AQ_CFG_PACING_TYPE_AVG 0
1228 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M
1229 /* External Device Power Ability */
1231 #define ICE_AQ_PWR_CLASS_M 0x3F
1232 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0
1233 #define ICE_AQ_LINK_PWR_BASET_HIGH 1
1234 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0
1235 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1
1236 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
1237 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
1239 #define ICE_AQ_LINK_SPEED_M 0x7FF
1240 #define ICE_AQ_LINK_SPEED_10MB BIT(0)
1241 #define ICE_AQ_LINK_SPEED_100MB BIT(1)
1242 #define ICE_AQ_LINK_SPEED_1000MB BIT(2)
1243 #define ICE_AQ_LINK_SPEED_2500MB BIT(3)
1244 #define ICE_AQ_LINK_SPEED_5GB BIT(4)
1245 #define ICE_AQ_LINK_SPEED_10GB BIT(5)
1246 #define ICE_AQ_LINK_SPEED_20GB BIT(6)
1247 #define ICE_AQ_LINK_SPEED_25GB BIT(7)
1248 #define ICE_AQ_LINK_SPEED_40GB BIT(8)
1249 #define ICE_AQ_LINK_SPEED_50GB BIT(9)
1250 #define ICE_AQ_LINK_SPEED_100GB BIT(10)
1251 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15)
1252 __le32 reserved3; /* Aligns next field to 8-byte boundary */
1253 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1254 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1257 /* Set event mask command (direct 0x0613) */
1258 struct ice_aqc_set_event_mask {
1262 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1)
1263 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2)
1264 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3)
1265 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4)
1266 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5)
1267 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6)
1268 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7)
1269 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)
1270 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9)
1274 /* Set MAC Loopback command (direct 0x0620) */
1275 struct ice_aqc_set_mac_lb {
1277 #define ICE_AQ_MAC_LB_EN BIT(0)
1278 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1)
1282 struct ice_aqc_link_topo_params {
1285 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0)
1287 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0
1288 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S)
1289 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0
1290 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1
1291 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2
1292 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3
1293 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4
1294 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5
1295 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6
1296 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7
1297 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8
1298 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4
1299 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \
1300 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S)
1301 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0
1302 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1
1303 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2
1304 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3
1305 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4
1306 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5
1310 struct ice_aqc_link_topo_addr {
1311 struct ice_aqc_link_topo_params topo_params;
1313 #define ICE_AQC_LINK_TOPO_HANDLE_S 0
1314 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S)
1315 /* Used to decode the handle field */
1316 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9)
1317 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9)
1318 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0
1319 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0
1320 /* In case of a Mezzanine type */
1321 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \
1322 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1323 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6
1324 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S)
1325 /* In case of a LOM type */
1326 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \
1327 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1330 /* Get Link Topology Handle (direct, 0x06E0) */
1331 struct ice_aqc_get_link_topo {
1332 struct ice_aqc_link_topo_addr addr;
1334 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575 0x21
1338 /* Set Port Identification LED (direct, 0x06E9) */
1339 struct ice_aqc_set_port_id_led {
1343 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0)
1344 #define ICE_AQC_PORT_IDENT_LED_ORIG 0
1348 /* Set/Get GPIO (direct, 0x06EC/0x06ED) */
1349 struct ice_aqc_gpio {
1350 __le16 gpio_ctrl_handle;
1351 #define ICE_AQC_GPIO_HANDLE_S 0
1352 #define ICE_AQC_GPIO_HANDLE_M (0x3FF << ICE_AQC_GPIO_HANDLE_S)
1358 /* Read/Write SFF EEPROM command (indirect 0x06EE) */
1359 struct ice_aqc_sff_eeprom {
1362 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0)
1363 __le16 i2c_bus_addr;
1364 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F
1365 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF
1366 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10)
1367 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0
1368 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M
1369 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11
1370 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S)
1371 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0
1372 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1
1373 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2
1374 #define ICE_AQC_SFF_IS_WRITE BIT(15)
1375 __le16 i2c_mem_addr;
1377 #define ICE_AQC_SFF_EEPROM_BANK_S 0
1378 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S)
1379 #define ICE_AQC_SFF_EEPROM_PAGE_S 8
1380 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S)
1385 /* NVM Read command (indirect 0x0701)
1386 * NVM Erase commands (direct 0x0702)
1387 * NVM Update commands (indirect 0x0703)
1389 struct ice_aqc_nvm {
1390 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF
1394 #define ICE_AQC_NVM_LAST_CMD BIT(0)
1395 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */
1396 #define ICE_AQC_NVM_PRESERVATION_S 1
1397 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S)
1398 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S)
1399 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1)
1400 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S)
1401 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S)
1402 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */
1403 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4)
1404 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5)
1405 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6)
1406 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */
1407 #define ICE_AQC_NVM_ACTIV_SEL_MASK ICE_M(0x7, 3)
1408 #define ICE_AQC_NVM_FLASH_ONLY BIT(7)
1409 __le16 module_typeid;
1411 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF
1416 #define ICE_AQC_NVM_START_POINT 0
1418 /* NVM Checksum Command (direct, 0x0706) */
1419 struct ice_aqc_nvm_checksum {
1421 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0)
1422 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1)
1424 __le16 checksum; /* Used only by response */
1425 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA
1429 /* Used for NVM Set Package Data command - 0x070A */
1430 struct ice_aqc_nvm_pkg_data {
1433 #define ICE_AQC_NVM_PKG_DELETE BIT(0) /* used for command call */
1434 #define ICE_AQC_NVM_PKG_SKIPPED BIT(0) /* used for command response */
1441 /* Used for Pass Component Table command - 0x070B */
1442 struct ice_aqc_nvm_pass_comp_tbl {
1443 u8 component_response; /* Response only */
1444 #define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED 0x0
1445 #define ICE_AQ_NVM_PASS_COMP_CAN_MAY_BE_UPDATEABLE 0x1
1446 #define ICE_AQ_NVM_PASS_COMP_CAN_NOT_BE_UPDATED 0x2
1447 u8 component_response_code; /* Response only */
1448 #define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED_CODE 0x0
1449 #define ICE_AQ_NVM_PASS_COMP_STAMP_IDENTICAL_CODE 0x1
1450 #define ICE_AQ_NVM_PASS_COMP_STAMP_LOWER 0x2
1451 #define ICE_AQ_NVM_PASS_COMP_INVALID_STAMP_CODE 0x3
1452 #define ICE_AQ_NVM_PASS_COMP_CONFLICT_CODE 0x4
1453 #define ICE_AQ_NVM_PASS_COMP_PRE_REQ_NOT_MET_CODE 0x5
1454 #define ICE_AQ_NVM_PASS_COMP_NOT_SUPPORTED_CODE 0x6
1455 #define ICE_AQ_NVM_PASS_COMP_CANNOT_DOWNGRADE_CODE 0x7
1456 #define ICE_AQ_NVM_PASS_COMP_INCOMPLETE_IMAGE_CODE 0x8
1457 #define ICE_AQ_NVM_PASS_COMP_VER_STR_IDENTICAL_CODE 0xA
1458 #define ICE_AQ_NVM_PASS_COMP_VER_STR_LOWER_CODE 0xB
1461 #define ICE_AQ_NVM_PASS_COMP_TBL_START 0x1
1462 #define ICE_AQ_NVM_PASS_COMP_TBL_MIDDLE 0x2
1463 #define ICE_AQ_NVM_PASS_COMP_TBL_END 0x4
1464 #define ICE_AQ_NVM_PASS_COMP_TBL_START_AND_END 0x5
1470 struct ice_aqc_nvm_comp_tbl {
1472 #define NVM_COMP_CLASS_ALL_FW 0x000A
1475 #define NVM_COMP_ID_OROM 0x5
1476 #define NVM_COMP_ID_NVM 0x6
1477 #define NVM_COMP_ID_NETLIST 0x8
1480 #define FWU_COMP_CLASS_IDX_NOT_USE 0x0
1482 __le32 comp_cmp_stamp;
1484 #define NVM_CVS_TYPE_ASCII 0x1
1487 u8 cvs[]; /* Component Version String */
1490 /* Send to PF command (indirect 0x0801) ID is only used by PF
1492 * Send to VF command (indirect 0x0802) ID is only used by PF
1495 struct ice_aqc_pf_vf_msg {
1502 /* Get LLDP MIB (indirect 0x0A00)
1503 * Note: This is also used by the LLDP MIB Change Event (0x0A01)
1504 * as the format is the same.
1506 struct ice_aqc_lldp_get_mib {
1508 #define ICE_AQ_LLDP_MIB_TYPE_S 0
1509 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S)
1510 #define ICE_AQ_LLDP_MIB_LOCAL 0
1511 #define ICE_AQ_LLDP_MIB_REMOTE 1
1512 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2
1513 #define ICE_AQ_LLDP_BRID_TYPE_S 2
1514 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S)
1515 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0
1516 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1
1517 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */
1518 #define ICE_AQ_LLDP_TX_S 0x4
1519 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S)
1520 #define ICE_AQ_LLDP_TX_ACTIVE 0
1521 #define ICE_AQ_LLDP_TX_SUSPENDED 1
1522 #define ICE_AQ_LLDP_TX_FLUSHED 3
1523 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00)
1524 * and in the LLDP MIB Change Event (0x0A01). They are valid for the
1525 * Get LLDP MIB (0x0A00) response only.
1535 /* Configure LLDP MIB Change Event (direct 0x0A01) */
1536 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */
1537 struct ice_aqc_lldp_set_mib_change {
1539 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
1540 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1
1544 /* Stop LLDP (direct 0x0A05) */
1545 struct ice_aqc_lldp_stop {
1547 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0)
1548 #define ICE_AQ_LLDP_AGENT_STOP 0x0
1549 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK
1550 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1)
1554 /* Start LLDP (direct 0x0A06) */
1555 struct ice_aqc_lldp_start {
1557 #define ICE_AQ_LLDP_AGENT_START BIT(0)
1558 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1)
1562 /* Get CEE DCBX Oper Config (0x0A07)
1563 * The command uses the generic descriptor struct and
1564 * returns the struct below as an indirect response.
1566 struct ice_aqc_get_cee_dcb_cfg_resp {
1571 __le16 oper_app_prio;
1572 #define ICE_AQC_CEE_APP_FCOE_S 0
1573 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S)
1574 #define ICE_AQC_CEE_APP_ISCSI_S 3
1575 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S)
1576 #define ICE_AQC_CEE_APP_FIP_S 8
1577 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S)
1579 #define ICE_AQC_CEE_PG_STATUS_S 0
1580 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S)
1581 #define ICE_AQC_CEE_PFC_STATUS_S 3
1582 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S)
1583 #define ICE_AQC_CEE_FCOE_STATUS_S 8
1584 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S)
1585 #define ICE_AQC_CEE_ISCSI_STATUS_S 11
1586 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S)
1587 #define ICE_AQC_CEE_FIP_STATUS_S 16
1588 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S)
1592 /* Set Local LLDP MIB (indirect 0x0A08)
1593 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX
1595 struct ice_aqc_lldp_set_local_mib {
1597 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0)
1598 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0
1599 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1)
1600 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0
1601 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M
1609 /* Stop/Start LLDP Agent (direct 0x0A09)
1610 * Used for stopping/starting specific LLDP agent. e.g. DCBX.
1611 * The same structure is used for the response, with the command field
1612 * being used as the status field.
1614 struct ice_aqc_lldp_stop_start_specific_agent {
1616 #define ICE_AQC_START_STOP_AGENT_M BIT(0)
1617 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0
1618 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M
1622 /* LLDP Filter Control (direct 0x0A0A) */
1623 struct ice_aqc_lldp_filter_ctrl {
1625 #define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0
1626 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1
1632 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */
1633 struct ice_aqc_get_set_rss_key {
1634 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15)
1635 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0
1636 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S)
1643 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28
1644 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC
1645 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \
1646 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \
1647 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE)
1649 struct ice_aqc_get_set_rss_keys {
1650 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];
1651 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];
1654 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */
1655 struct ice_aqc_get_set_rss_lut {
1656 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15)
1657 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0
1658 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S)
1660 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0
1661 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \
1662 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S)
1664 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0
1665 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1
1666 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2
1668 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2
1669 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \
1670 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S)
1672 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128
1673 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0
1674 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512
1675 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1
1676 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048
1677 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2
1679 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4
1680 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \
1681 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S)
1689 /* Sideband Control Interface Commands */
1690 /* Neighbor Device Request (indirect 0x0C00); also used for the response. */
1691 struct ice_aqc_neigh_dev_req {
1698 /* Add Tx LAN Queues (indirect 0x0C30) */
1699 struct ice_aqc_add_txqs {
1707 /* This is the descriptor of each queue entry for the Add Tx LAN Queues
1708 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.
1710 struct ice_aqc_add_txqs_perq {
1716 struct ice_aqc_txsched_elem info;
1719 /* The format of the command buffer for Add Tx LAN Queues (0x0C30)
1720 * is an array of the following structs. Please note that the length of
1721 * each struct ice_aqc_add_tx_qgrp is variable due
1722 * to the variable number of queues in each group!
1724 struct ice_aqc_add_tx_qgrp {
1728 struct ice_aqc_add_txqs_perq txqs[];
1731 /* Disable Tx LAN Queues (indirect 0x0C31) */
1732 struct ice_aqc_dis_txqs {
1734 #define ICE_AQC_Q_DIS_CMD_S 0
1735 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S)
1736 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S)
1737 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S)
1738 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S)
1739 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S)
1740 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2)
1741 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3)
1743 __le16 vmvf_and_timeout;
1744 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0
1745 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)
1746 #define ICE_AQC_Q_DIS_TIMEOUT_S 10
1747 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)
1748 __le32 blocked_cgds;
1753 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31)
1754 * contains the following structures, arrayed one after the
1756 * Note: Since the q_id is 16 bits wide, if the
1757 * number of queues is even, then 2 bytes of alignment MUST be
1758 * added before the start of the next group, to allow correct
1759 * alignment of the parent_teid field.
1761 struct ice_aqc_dis_txq_item {
1765 /* The length of the q_id array varies according to num_qs */
1766 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15
1767 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \
1768 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1769 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \
1770 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1774 /* Add Tx RDMA Queue Set (indirect 0x0C33) */
1775 struct ice_aqc_add_rdma_qset {
1782 /* This is the descriptor of each Qset entry for the Add Tx RDMA Queue Set
1783 * command (0x0C33). Only used within struct ice_aqc_add_rdma_qset.
1785 struct ice_aqc_add_tx_rdma_qset_entry {
1789 struct ice_aqc_txsched_elem info;
1792 /* The format of the command buffer for Add Tx RDMA Queue Set(0x0C33)
1793 * is an array of the following structs. Please note that the length of
1794 * each struct ice_aqc_add_rdma_qset is variable due to the variable
1795 * number of queues in each group!
1797 struct ice_aqc_add_rdma_qset_data {
1801 struct ice_aqc_add_tx_rdma_qset_entry rdma_qsets[];
1804 /* Configure Firmware Logging Command (indirect 0xFF09)
1805 * Logging Information Read Response (indirect 0xFF10)
1806 * Note: The 0xFF10 command has no input parameters.
1808 struct ice_aqc_fw_logging {
1810 #define ICE_AQC_FW_LOG_AQ_EN BIT(0)
1811 #define ICE_AQC_FW_LOG_UART_EN BIT(1)
1813 u8 log_ctrl_valid; /* Not used by 0xFF10 Response */
1814 #define ICE_AQC_FW_LOG_AQ_VALID BIT(0)
1815 #define ICE_AQC_FW_LOG_UART_VALID BIT(1)
1821 enum ice_aqc_fw_logging_mod {
1822 ICE_AQC_FW_LOG_ID_GENERAL = 0,
1823 ICE_AQC_FW_LOG_ID_CTRL,
1824 ICE_AQC_FW_LOG_ID_LINK,
1825 ICE_AQC_FW_LOG_ID_LINK_TOPO,
1826 ICE_AQC_FW_LOG_ID_DNL,
1827 ICE_AQC_FW_LOG_ID_I2C,
1828 ICE_AQC_FW_LOG_ID_SDP,
1829 ICE_AQC_FW_LOG_ID_MDIO,
1830 ICE_AQC_FW_LOG_ID_ADMINQ,
1831 ICE_AQC_FW_LOG_ID_HDMA,
1832 ICE_AQC_FW_LOG_ID_LLDP,
1833 ICE_AQC_FW_LOG_ID_DCBX,
1834 ICE_AQC_FW_LOG_ID_DCB,
1835 ICE_AQC_FW_LOG_ID_NETPROXY,
1836 ICE_AQC_FW_LOG_ID_NVM,
1837 ICE_AQC_FW_LOG_ID_AUTH,
1838 ICE_AQC_FW_LOG_ID_VPD,
1839 ICE_AQC_FW_LOG_ID_IOSF,
1840 ICE_AQC_FW_LOG_ID_PARSER,
1841 ICE_AQC_FW_LOG_ID_SW,
1842 ICE_AQC_FW_LOG_ID_SCHEDULER,
1843 ICE_AQC_FW_LOG_ID_TXQ,
1844 ICE_AQC_FW_LOG_ID_RSVD,
1845 ICE_AQC_FW_LOG_ID_POST,
1846 ICE_AQC_FW_LOG_ID_WATCHDOG,
1847 ICE_AQC_FW_LOG_ID_TASK_DISPATCH,
1848 ICE_AQC_FW_LOG_ID_MNG,
1849 ICE_AQC_FW_LOG_ID_MAX,
1852 /* Defines for both above FW logging command/response buffers */
1853 #define ICE_AQC_FW_LOG_ID_S 0
1854 #define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S)
1856 #define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */
1857 #define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */
1859 #define ICE_AQC_FW_LOG_EN_S 12
1860 #define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S)
1861 #define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */
1862 #define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */
1863 #define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */
1864 #define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */
1866 /* Get/Clear FW Log (indirect 0xFF11) */
1867 struct ice_aqc_get_clear_fw_log {
1869 #define ICE_AQC_FW_LOG_CLEAR BIT(0)
1870 #define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1)
1876 /* Download Package (indirect 0x0C40) */
1877 /* Also used for Update Package (indirect 0x0C42) */
1878 struct ice_aqc_download_pkg {
1880 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01
1887 struct ice_aqc_download_pkg_resp {
1888 __le32 error_offset;
1894 /* Get Package Info List (indirect 0x0C43) */
1895 struct ice_aqc_get_pkg_info_list {
1902 /* Version format for packages */
1903 struct ice_pkg_ver {
1910 #define ICE_PKG_NAME_SIZE 32
1911 #define ICE_SEG_ID_SIZE 28
1912 #define ICE_SEG_NAME_SIZE 28
1914 struct ice_aqc_get_pkg_info {
1915 struct ice_pkg_ver ver;
1916 char name[ICE_SEG_NAME_SIZE];
1920 u8 is_active_at_boot;
1924 /* Get Package Info List response buffer format (0x0C43) */
1925 struct ice_aqc_get_pkg_info_resp {
1927 struct ice_aqc_get_pkg_info pkg_info[];
1930 /* Driver Shared Parameters (direct, 0x0C90) */
1931 struct ice_aqc_driver_shared_params {
1933 #define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0)
1934 #define ICE_AQC_DRIVER_PARAM_SET 0
1935 #define ICE_AQC_DRIVER_PARAM_GET 1
1937 #define ICE_AQC_DRIVER_PARAM_MAX_IDX 15
1944 enum ice_aqc_driver_params {
1945 /* OS clock index for PTP timer Domain 0 */
1946 ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR0 = 0,
1947 /* OS clock index for PTP timer Domain 1 */
1948 ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR1,
1950 /* Add new parameters above */
1951 ICE_AQC_DRIVER_PARAM_MAX = 16,
1954 /* Lan Queue Overflow Event (direct, 0x1001) */
1955 struct ice_aqc_event_lan_overflow {
1956 __le32 prtdcb_ruptq;
1962 * struct ice_aq_desc - Admin Queue (AQ) descriptor
1963 * @flags: ICE_AQ_FLAG_* flags
1964 * @opcode: AQ command opcode
1965 * @datalen: length in bytes of indirect/external data buffer
1966 * @retval: return value from firmware
1967 * @cookie_high: opaque data high-half
1968 * @cookie_low: opaque data low-half
1969 * @params: command-specific parameters
1971 * Descriptor format for commands the driver posts on the Admin Transmit Queue
1972 * (ATQ). The firmware writes back onto the command descriptor and returns
1973 * the result of the command. Asynchronous events that are not an immediate
1974 * result of the command are written to the Admin Receive Queue (ARQ) using
1975 * the same descriptor format. Descriptors are in little-endian notation with
1978 struct ice_aq_desc {
1987 struct ice_aqc_generic generic;
1988 struct ice_aqc_get_ver get_ver;
1989 struct ice_aqc_driver_ver driver_ver;
1990 struct ice_aqc_q_shutdown q_shutdown;
1991 struct ice_aqc_req_res res_owner;
1992 struct ice_aqc_manage_mac_read mac_read;
1993 struct ice_aqc_manage_mac_write mac_write;
1994 struct ice_aqc_clear_pxe clear_pxe;
1995 struct ice_aqc_list_caps get_cap;
1996 struct ice_aqc_get_phy_caps get_phy;
1997 struct ice_aqc_set_phy_cfg set_phy;
1998 struct ice_aqc_restart_an restart_an;
1999 struct ice_aqc_gpio read_write_gpio;
2000 struct ice_aqc_sff_eeprom read_write_sff_param;
2001 struct ice_aqc_set_port_id_led set_port_id_led;
2002 struct ice_aqc_get_sw_cfg get_sw_conf;
2003 struct ice_aqc_sw_rules sw_rules;
2004 struct ice_aqc_add_get_recipe add_get_recipe;
2005 struct ice_aqc_recipe_to_profile recipe_to_profile;
2006 struct ice_aqc_get_topo get_topo;
2007 struct ice_aqc_sched_elem_cmd sched_elem_cmd;
2008 struct ice_aqc_query_txsched_res query_sched_res;
2009 struct ice_aqc_query_port_ets port_ets;
2010 struct ice_aqc_rl_profile rl_profile;
2011 struct ice_aqc_nvm nvm;
2012 struct ice_aqc_nvm_checksum nvm_checksum;
2013 struct ice_aqc_nvm_pkg_data pkg_data;
2014 struct ice_aqc_nvm_pass_comp_tbl pass_comp_tbl;
2015 struct ice_aqc_pf_vf_msg virt;
2016 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode;
2017 struct ice_aqc_lldp_get_mib lldp_get_mib;
2018 struct ice_aqc_lldp_set_mib_change lldp_set_event;
2019 struct ice_aqc_lldp_stop lldp_stop;
2020 struct ice_aqc_lldp_start lldp_start;
2021 struct ice_aqc_lldp_set_local_mib lldp_set_mib;
2022 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl;
2023 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl;
2024 struct ice_aqc_get_set_rss_lut get_set_rss_lut;
2025 struct ice_aqc_get_set_rss_key get_set_rss_key;
2026 struct ice_aqc_neigh_dev_req neigh_dev;
2027 struct ice_aqc_add_txqs add_txqs;
2028 struct ice_aqc_dis_txqs dis_txqs;
2029 struct ice_aqc_add_rdma_qset add_rdma_qset;
2030 struct ice_aqc_add_get_update_free_vsi vsi_cmd;
2031 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
2032 struct ice_aqc_fw_logging fw_logging;
2033 struct ice_aqc_get_clear_fw_log get_clear_fw_log;
2034 struct ice_aqc_download_pkg download_pkg;
2035 struct ice_aqc_driver_shared_params drv_shared_params;
2036 struct ice_aqc_set_mac_lb set_mac_lb;
2037 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
2038 struct ice_aqc_set_mac_cfg set_mac_cfg;
2039 struct ice_aqc_set_event_mask set_event_mask;
2040 struct ice_aqc_get_link_status get_link_status;
2041 struct ice_aqc_event_lan_overflow lan_overflow;
2042 struct ice_aqc_get_link_topo get_link_topo;
2046 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
2047 #define ICE_AQ_LG_BUF 512
2049 #define ICE_AQ_FLAG_ERR_S 2
2050 #define ICE_AQ_FLAG_LB_S 9
2051 #define ICE_AQ_FLAG_RD_S 10
2052 #define ICE_AQ_FLAG_BUF_S 12
2053 #define ICE_AQ_FLAG_SI_S 13
2055 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */
2056 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */
2057 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */
2058 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */
2059 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */
2063 ICE_AQ_RC_OK = 0, /* Success */
2064 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */
2065 ICE_AQ_RC_ENOENT = 2, /* No such element */
2066 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */
2067 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */
2068 ICE_AQ_RC_EEXIST = 13, /* Object already exists */
2069 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */
2070 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */
2071 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */
2072 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
2073 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */
2074 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */
2075 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */
2076 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */
2077 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */
2080 /* Admin Queue command opcodes */
2081 enum ice_adminq_opc {
2083 ice_aqc_opc_get_ver = 0x0001,
2084 ice_aqc_opc_driver_ver = 0x0002,
2085 ice_aqc_opc_q_shutdown = 0x0003,
2087 /* resource ownership */
2088 ice_aqc_opc_req_res = 0x0008,
2089 ice_aqc_opc_release_res = 0x0009,
2091 /* device/function capabilities */
2092 ice_aqc_opc_list_func_caps = 0x000A,
2093 ice_aqc_opc_list_dev_caps = 0x000B,
2095 /* manage MAC address */
2096 ice_aqc_opc_manage_mac_read = 0x0107,
2097 ice_aqc_opc_manage_mac_write = 0x0108,
2100 ice_aqc_opc_clear_pxe_mode = 0x0110,
2102 /* internal switch commands */
2103 ice_aqc_opc_get_sw_cfg = 0x0200,
2105 /* Alloc/Free/Get Resources */
2106 ice_aqc_opc_alloc_res = 0x0208,
2107 ice_aqc_opc_free_res = 0x0209,
2110 ice_aqc_opc_add_vsi = 0x0210,
2111 ice_aqc_opc_update_vsi = 0x0211,
2112 ice_aqc_opc_free_vsi = 0x0213,
2114 /* recipe commands */
2115 ice_aqc_opc_add_recipe = 0x0290,
2116 ice_aqc_opc_recipe_to_profile = 0x0291,
2117 ice_aqc_opc_get_recipe = 0x0292,
2118 ice_aqc_opc_get_recipe_to_profile = 0x0293,
2120 /* switch rules population commands */
2121 ice_aqc_opc_add_sw_rules = 0x02A0,
2122 ice_aqc_opc_update_sw_rules = 0x02A1,
2123 ice_aqc_opc_remove_sw_rules = 0x02A2,
2125 ice_aqc_opc_clear_pf_cfg = 0x02A4,
2128 ice_aqc_opc_query_pfc_mode = 0x0302,
2129 ice_aqc_opc_set_pfc_mode = 0x0303,
2131 /* transmit scheduler commands */
2132 ice_aqc_opc_get_dflt_topo = 0x0400,
2133 ice_aqc_opc_add_sched_elems = 0x0401,
2134 ice_aqc_opc_cfg_sched_elems = 0x0403,
2135 ice_aqc_opc_get_sched_elems = 0x0404,
2136 ice_aqc_opc_move_sched_elems = 0x0408,
2137 ice_aqc_opc_suspend_sched_elems = 0x0409,
2138 ice_aqc_opc_resume_sched_elems = 0x040A,
2139 ice_aqc_opc_query_port_ets = 0x040E,
2140 ice_aqc_opc_delete_sched_elems = 0x040F,
2141 ice_aqc_opc_add_rl_profiles = 0x0410,
2142 ice_aqc_opc_query_sched_res = 0x0412,
2143 ice_aqc_opc_remove_rl_profiles = 0x0415,
2146 ice_aqc_opc_get_phy_caps = 0x0600,
2147 ice_aqc_opc_set_phy_cfg = 0x0601,
2148 ice_aqc_opc_set_mac_cfg = 0x0603,
2149 ice_aqc_opc_restart_an = 0x0605,
2150 ice_aqc_opc_get_link_status = 0x0607,
2151 ice_aqc_opc_set_event_mask = 0x0613,
2152 ice_aqc_opc_set_mac_lb = 0x0620,
2153 ice_aqc_opc_get_link_topo = 0x06E0,
2154 ice_aqc_opc_set_port_id_led = 0x06E9,
2155 ice_aqc_opc_set_gpio = 0x06EC,
2156 ice_aqc_opc_get_gpio = 0x06ED,
2157 ice_aqc_opc_sff_eeprom = 0x06EE,
2160 ice_aqc_opc_nvm_read = 0x0701,
2161 ice_aqc_opc_nvm_erase = 0x0702,
2162 ice_aqc_opc_nvm_write = 0x0703,
2163 ice_aqc_opc_nvm_checksum = 0x0706,
2164 ice_aqc_opc_nvm_write_activate = 0x0707,
2165 ice_aqc_opc_nvm_update_empr = 0x0709,
2166 ice_aqc_opc_nvm_pkg_data = 0x070A,
2167 ice_aqc_opc_nvm_pass_component_tbl = 0x070B,
2169 /* PF/VF mailbox commands */
2170 ice_mbx_opc_send_msg_to_pf = 0x0801,
2171 ice_mbx_opc_send_msg_to_vf = 0x0802,
2173 ice_aqc_opc_lldp_get_mib = 0x0A00,
2174 ice_aqc_opc_lldp_set_mib_change = 0x0A01,
2175 ice_aqc_opc_lldp_stop = 0x0A05,
2176 ice_aqc_opc_lldp_start = 0x0A06,
2177 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07,
2178 ice_aqc_opc_lldp_set_local_mib = 0x0A08,
2179 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09,
2180 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A,
2183 ice_aqc_opc_set_rss_key = 0x0B02,
2184 ice_aqc_opc_set_rss_lut = 0x0B03,
2185 ice_aqc_opc_get_rss_key = 0x0B04,
2186 ice_aqc_opc_get_rss_lut = 0x0B05,
2188 /* Sideband Control Interface commands */
2189 ice_aqc_opc_neighbour_device_request = 0x0C00,
2191 /* Tx queue handling commands/events */
2192 ice_aqc_opc_add_txqs = 0x0C30,
2193 ice_aqc_opc_dis_txqs = 0x0C31,
2194 ice_aqc_opc_add_rdma_qset = 0x0C33,
2196 /* package commands */
2197 ice_aqc_opc_download_pkg = 0x0C40,
2198 ice_aqc_opc_update_pkg = 0x0C42,
2199 ice_aqc_opc_get_pkg_info_list = 0x0C43,
2201 ice_aqc_opc_driver_shared_params = 0x0C90,
2203 /* Standalone Commands/Events */
2204 ice_aqc_opc_event_lan_overflow = 0x1001,
2206 /* debug commands */
2207 ice_aqc_opc_fw_logging = 0xFF09,
2208 ice_aqc_opc_fw_logging_info = 0xFF10,
2211 #endif /* _ICE_ADMINQ_CMD_H_ */