1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
4 #include "iavf_status.h"
6 #include "iavf_register.h"
7 #include "iavf_adminq.h"
8 #include "iavf_prototype.h"
11 * iavf_adminq_init_regs - Initialize AdminQ registers
12 * @hw: pointer to the hardware structure
14 * This assumes the alloc_asq and alloc_arq functions have already been called
16 static void iavf_adminq_init_regs(struct iavf_hw *hw)
18 /* set head and tail registers in our local struct */
19 hw->aq.asq.tail = IAVF_VF_ATQT1;
20 hw->aq.asq.head = IAVF_VF_ATQH1;
21 hw->aq.asq.len = IAVF_VF_ATQLEN1;
22 hw->aq.asq.bal = IAVF_VF_ATQBAL1;
23 hw->aq.asq.bah = IAVF_VF_ATQBAH1;
24 hw->aq.arq.tail = IAVF_VF_ARQT1;
25 hw->aq.arq.head = IAVF_VF_ARQH1;
26 hw->aq.arq.len = IAVF_VF_ARQLEN1;
27 hw->aq.arq.bal = IAVF_VF_ARQBAL1;
28 hw->aq.arq.bah = IAVF_VF_ARQBAH1;
32 * iavf_alloc_adminq_asq_ring - Allocate Admin Queue send rings
33 * @hw: pointer to the hardware structure
35 static enum iavf_status iavf_alloc_adminq_asq_ring(struct iavf_hw *hw)
37 enum iavf_status ret_code;
39 ret_code = iavf_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,
41 (hw->aq.num_asq_entries *
42 sizeof(struct iavf_aq_desc)),
43 IAVF_ADMINQ_DESC_ALIGNMENT);
47 ret_code = iavf_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf,
48 (hw->aq.num_asq_entries *
49 sizeof(struct iavf_asq_cmd_details)));
51 iavf_free_dma_mem(hw, &hw->aq.asq.desc_buf);
59 * iavf_alloc_adminq_arq_ring - Allocate Admin Queue receive rings
60 * @hw: pointer to the hardware structure
62 static enum iavf_status iavf_alloc_adminq_arq_ring(struct iavf_hw *hw)
64 enum iavf_status ret_code;
66 ret_code = iavf_allocate_dma_mem(hw, &hw->aq.arq.desc_buf,
68 (hw->aq.num_arq_entries *
69 sizeof(struct iavf_aq_desc)),
70 IAVF_ADMINQ_DESC_ALIGNMENT);
76 * iavf_free_adminq_asq - Free Admin Queue send rings
77 * @hw: pointer to the hardware structure
79 * This assumes the posted send buffers have already been cleaned
82 static void iavf_free_adminq_asq(struct iavf_hw *hw)
84 iavf_free_dma_mem(hw, &hw->aq.asq.desc_buf);
88 * iavf_free_adminq_arq - Free Admin Queue receive rings
89 * @hw: pointer to the hardware structure
91 * This assumes the posted receive buffers have already been cleaned
94 static void iavf_free_adminq_arq(struct iavf_hw *hw)
96 iavf_free_dma_mem(hw, &hw->aq.arq.desc_buf);
100 * iavf_alloc_arq_bufs - Allocate pre-posted buffers for the receive queue
101 * @hw: pointer to the hardware structure
103 static enum iavf_status iavf_alloc_arq_bufs(struct iavf_hw *hw)
105 struct iavf_aq_desc *desc;
106 struct iavf_dma_mem *bi;
107 enum iavf_status ret_code;
110 /* We'll be allocating the buffer info memory first, then we can
111 * allocate the mapped buffers for the event processing
114 /* buffer_info structures do not need alignment */
115 ret_code = iavf_allocate_virt_mem(hw, &hw->aq.arq.dma_head,
116 (hw->aq.num_arq_entries *
117 sizeof(struct iavf_dma_mem)));
120 hw->aq.arq.r.arq_bi = (struct iavf_dma_mem *)hw->aq.arq.dma_head.va;
122 /* allocate the mapped buffers */
123 for (i = 0; i < hw->aq.num_arq_entries; i++) {
124 bi = &hw->aq.arq.r.arq_bi[i];
125 ret_code = iavf_allocate_dma_mem(hw, bi,
128 IAVF_ADMINQ_DESC_ALIGNMENT);
130 goto unwind_alloc_arq_bufs;
132 /* now configure the descriptors for use */
133 desc = IAVF_ADMINQ_DESC(hw->aq.arq, i);
135 desc->flags = cpu_to_le16(IAVF_AQ_FLAG_BUF);
136 if (hw->aq.arq_buf_size > IAVF_AQ_LARGE_BUF)
137 desc->flags |= cpu_to_le16(IAVF_AQ_FLAG_LB);
139 /* This is in accordance with Admin queue design, there is no
140 * register for buffer size configuration
142 desc->datalen = cpu_to_le16((u16)bi->size);
144 desc->cookie_high = 0;
145 desc->cookie_low = 0;
146 desc->params.external.addr_high =
147 cpu_to_le32(upper_32_bits(bi->pa));
148 desc->params.external.addr_low =
149 cpu_to_le32(lower_32_bits(bi->pa));
150 desc->params.external.param0 = 0;
151 desc->params.external.param1 = 0;
157 unwind_alloc_arq_bufs:
158 /* don't try to free the one that failed... */
161 iavf_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
162 iavf_free_virt_mem(hw, &hw->aq.arq.dma_head);
168 * iavf_alloc_asq_bufs - Allocate empty buffer structs for the send queue
169 * @hw: pointer to the hardware structure
171 static enum iavf_status iavf_alloc_asq_bufs(struct iavf_hw *hw)
173 struct iavf_dma_mem *bi;
174 enum iavf_status ret_code;
177 /* No mapped memory needed yet, just the buffer info structures */
178 ret_code = iavf_allocate_virt_mem(hw, &hw->aq.asq.dma_head,
179 (hw->aq.num_asq_entries *
180 sizeof(struct iavf_dma_mem)));
183 hw->aq.asq.r.asq_bi = (struct iavf_dma_mem *)hw->aq.asq.dma_head.va;
185 /* allocate the mapped buffers */
186 for (i = 0; i < hw->aq.num_asq_entries; i++) {
187 bi = &hw->aq.asq.r.asq_bi[i];
188 ret_code = iavf_allocate_dma_mem(hw, bi,
191 IAVF_ADMINQ_DESC_ALIGNMENT);
193 goto unwind_alloc_asq_bufs;
198 unwind_alloc_asq_bufs:
199 /* don't try to free the one that failed... */
202 iavf_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
203 iavf_free_virt_mem(hw, &hw->aq.asq.dma_head);
209 * iavf_free_arq_bufs - Free receive queue buffer info elements
210 * @hw: pointer to the hardware structure
212 static void iavf_free_arq_bufs(struct iavf_hw *hw)
216 /* free descriptors */
217 for (i = 0; i < hw->aq.num_arq_entries; i++)
218 iavf_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
220 /* free the descriptor memory */
221 iavf_free_dma_mem(hw, &hw->aq.arq.desc_buf);
223 /* free the dma header */
224 iavf_free_virt_mem(hw, &hw->aq.arq.dma_head);
228 * iavf_free_asq_bufs - Free send queue buffer info elements
229 * @hw: pointer to the hardware structure
231 static void iavf_free_asq_bufs(struct iavf_hw *hw)
235 /* only unmap if the address is non-NULL */
236 for (i = 0; i < hw->aq.num_asq_entries; i++)
237 if (hw->aq.asq.r.asq_bi[i].pa)
238 iavf_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
240 /* free the buffer info list */
241 iavf_free_virt_mem(hw, &hw->aq.asq.cmd_buf);
243 /* free the descriptor memory */
244 iavf_free_dma_mem(hw, &hw->aq.asq.desc_buf);
246 /* free the dma header */
247 iavf_free_virt_mem(hw, &hw->aq.asq.dma_head);
251 * iavf_config_asq_regs - configure ASQ registers
252 * @hw: pointer to the hardware structure
254 * Configure base address and length registers for the transmit queue
256 static enum iavf_status iavf_config_asq_regs(struct iavf_hw *hw)
258 enum iavf_status ret_code = 0;
261 /* Clear Head and Tail */
262 wr32(hw, hw->aq.asq.head, 0);
263 wr32(hw, hw->aq.asq.tail, 0);
265 /* set starting point */
266 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
267 IAVF_VF_ATQLEN1_ATQENABLE_MASK));
268 wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa));
269 wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa));
271 /* Check one register to verify that config was applied */
272 reg = rd32(hw, hw->aq.asq.bal);
273 if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa))
274 ret_code = IAVF_ERR_ADMIN_QUEUE_ERROR;
280 * iavf_config_arq_regs - ARQ register configuration
281 * @hw: pointer to the hardware structure
283 * Configure base address and length registers for the receive (event queue)
285 static enum iavf_status iavf_config_arq_regs(struct iavf_hw *hw)
287 enum iavf_status ret_code = 0;
290 /* Clear Head and Tail */
291 wr32(hw, hw->aq.arq.head, 0);
292 wr32(hw, hw->aq.arq.tail, 0);
294 /* set starting point */
295 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
296 IAVF_VF_ARQLEN1_ARQENABLE_MASK));
297 wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa));
298 wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa));
300 /* Update tail in the HW to post pre-allocated buffers */
301 wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);
303 /* Check one register to verify that config was applied */
304 reg = rd32(hw, hw->aq.arq.bal);
305 if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa))
306 ret_code = IAVF_ERR_ADMIN_QUEUE_ERROR;
312 * iavf_init_asq - main initialization routine for ASQ
313 * @hw: pointer to the hardware structure
315 * This is the main initialization routine for the Admin Send Queue
316 * Prior to calling this function, drivers *MUST* set the following fields
317 * in the hw->aq structure:
318 * - hw->aq.num_asq_entries
319 * - hw->aq.arq_buf_size
321 * Do *NOT* hold the lock when calling this as the memory allocation routines
322 * called are not going to be atomic context safe
324 static enum iavf_status iavf_init_asq(struct iavf_hw *hw)
326 enum iavf_status ret_code = 0;
328 if (hw->aq.asq.count > 0) {
329 /* queue already initialized */
330 ret_code = IAVF_ERR_NOT_READY;
331 goto init_adminq_exit;
334 /* verify input for valid configuration */
335 if ((hw->aq.num_asq_entries == 0) ||
336 (hw->aq.asq_buf_size == 0)) {
337 ret_code = IAVF_ERR_CONFIG;
338 goto init_adminq_exit;
341 hw->aq.asq.next_to_use = 0;
342 hw->aq.asq.next_to_clean = 0;
344 /* allocate the ring memory */
345 ret_code = iavf_alloc_adminq_asq_ring(hw);
347 goto init_adminq_exit;
349 /* allocate buffers in the rings */
350 ret_code = iavf_alloc_asq_bufs(hw);
352 goto init_adminq_free_rings;
354 /* initialize base registers */
355 ret_code = iavf_config_asq_regs(hw);
357 goto init_adminq_free_rings;
360 hw->aq.asq.count = hw->aq.num_asq_entries;
361 goto init_adminq_exit;
363 init_adminq_free_rings:
364 iavf_free_adminq_asq(hw);
371 * iavf_init_arq - initialize ARQ
372 * @hw: pointer to the hardware structure
374 * The main initialization routine for the Admin Receive (Event) Queue.
375 * Prior to calling this function, drivers *MUST* set the following fields
376 * in the hw->aq structure:
377 * - hw->aq.num_asq_entries
378 * - hw->aq.arq_buf_size
380 * Do *NOT* hold the lock when calling this as the memory allocation routines
381 * called are not going to be atomic context safe
383 static enum iavf_status iavf_init_arq(struct iavf_hw *hw)
385 enum iavf_status ret_code = 0;
387 if (hw->aq.arq.count > 0) {
388 /* queue already initialized */
389 ret_code = IAVF_ERR_NOT_READY;
390 goto init_adminq_exit;
393 /* verify input for valid configuration */
394 if ((hw->aq.num_arq_entries == 0) ||
395 (hw->aq.arq_buf_size == 0)) {
396 ret_code = IAVF_ERR_CONFIG;
397 goto init_adminq_exit;
400 hw->aq.arq.next_to_use = 0;
401 hw->aq.arq.next_to_clean = 0;
403 /* allocate the ring memory */
404 ret_code = iavf_alloc_adminq_arq_ring(hw);
406 goto init_adminq_exit;
408 /* allocate buffers in the rings */
409 ret_code = iavf_alloc_arq_bufs(hw);
411 goto init_adminq_free_rings;
413 /* initialize base registers */
414 ret_code = iavf_config_arq_regs(hw);
416 goto init_adminq_free_rings;
419 hw->aq.arq.count = hw->aq.num_arq_entries;
420 goto init_adminq_exit;
422 init_adminq_free_rings:
423 iavf_free_adminq_arq(hw);
430 * iavf_shutdown_asq - shutdown the ASQ
431 * @hw: pointer to the hardware structure
433 * The main shutdown routine for the Admin Send Queue
435 static enum iavf_status iavf_shutdown_asq(struct iavf_hw *hw)
437 enum iavf_status ret_code = 0;
439 mutex_lock(&hw->aq.asq_mutex);
441 if (hw->aq.asq.count == 0) {
442 ret_code = IAVF_ERR_NOT_READY;
443 goto shutdown_asq_out;
446 /* Stop firmware AdminQ processing */
447 wr32(hw, hw->aq.asq.head, 0);
448 wr32(hw, hw->aq.asq.tail, 0);
449 wr32(hw, hw->aq.asq.len, 0);
450 wr32(hw, hw->aq.asq.bal, 0);
451 wr32(hw, hw->aq.asq.bah, 0);
453 hw->aq.asq.count = 0; /* to indicate uninitialized queue */
455 /* free ring buffers */
456 iavf_free_asq_bufs(hw);
459 mutex_unlock(&hw->aq.asq_mutex);
464 * iavf_shutdown_arq - shutdown ARQ
465 * @hw: pointer to the hardware structure
467 * The main shutdown routine for the Admin Receive Queue
469 static enum iavf_status iavf_shutdown_arq(struct iavf_hw *hw)
471 enum iavf_status ret_code = 0;
473 mutex_lock(&hw->aq.arq_mutex);
475 if (hw->aq.arq.count == 0) {
476 ret_code = IAVF_ERR_NOT_READY;
477 goto shutdown_arq_out;
480 /* Stop firmware AdminQ processing */
481 wr32(hw, hw->aq.arq.head, 0);
482 wr32(hw, hw->aq.arq.tail, 0);
483 wr32(hw, hw->aq.arq.len, 0);
484 wr32(hw, hw->aq.arq.bal, 0);
485 wr32(hw, hw->aq.arq.bah, 0);
487 hw->aq.arq.count = 0; /* to indicate uninitialized queue */
489 /* free ring buffers */
490 iavf_free_arq_bufs(hw);
493 mutex_unlock(&hw->aq.arq_mutex);
498 * iavf_init_adminq - main initialization routine for Admin Queue
499 * @hw: pointer to the hardware structure
501 * Prior to calling this function, drivers *MUST* set the following fields
502 * in the hw->aq structure:
503 * - hw->aq.num_asq_entries
504 * - hw->aq.num_arq_entries
505 * - hw->aq.arq_buf_size
506 * - hw->aq.asq_buf_size
508 enum iavf_status iavf_init_adminq(struct iavf_hw *hw)
510 enum iavf_status ret_code;
512 /* verify input for valid configuration */
513 if ((hw->aq.num_arq_entries == 0) ||
514 (hw->aq.num_asq_entries == 0) ||
515 (hw->aq.arq_buf_size == 0) ||
516 (hw->aq.asq_buf_size == 0)) {
517 ret_code = IAVF_ERR_CONFIG;
518 goto init_adminq_exit;
521 /* Set up register offsets */
522 iavf_adminq_init_regs(hw);
524 /* setup ASQ command write back timeout */
525 hw->aq.asq_cmd_timeout = IAVF_ASQ_CMD_TIMEOUT;
527 /* allocate the ASQ */
528 ret_code = iavf_init_asq(hw);
530 goto init_adminq_destroy_locks;
532 /* allocate the ARQ */
533 ret_code = iavf_init_arq(hw);
535 goto init_adminq_free_asq;
538 goto init_adminq_exit;
540 init_adminq_free_asq:
541 iavf_shutdown_asq(hw);
542 init_adminq_destroy_locks:
549 * iavf_shutdown_adminq - shutdown routine for the Admin Queue
550 * @hw: pointer to the hardware structure
552 enum iavf_status iavf_shutdown_adminq(struct iavf_hw *hw)
554 if (iavf_check_asq_alive(hw))
555 iavf_aq_queue_shutdown(hw, true);
557 iavf_shutdown_asq(hw);
558 iavf_shutdown_arq(hw);
564 * iavf_clean_asq - cleans Admin send queue
565 * @hw: pointer to the hardware structure
567 * returns the number of free desc
569 static u16 iavf_clean_asq(struct iavf_hw *hw)
571 struct iavf_adminq_ring *asq = &hw->aq.asq;
572 struct iavf_asq_cmd_details *details;
573 u16 ntc = asq->next_to_clean;
574 struct iavf_aq_desc desc_cb;
575 struct iavf_aq_desc *desc;
577 desc = IAVF_ADMINQ_DESC(*asq, ntc);
578 details = IAVF_ADMINQ_DETAILS(*asq, ntc);
579 while (rd32(hw, hw->aq.asq.head) != ntc) {
580 iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,
581 "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head));
583 if (details->callback) {
584 IAVF_ADMINQ_CALLBACK cb_func =
585 (IAVF_ADMINQ_CALLBACK)details->callback;
587 cb_func(hw, &desc_cb);
589 memset((void *)desc, 0, sizeof(struct iavf_aq_desc));
590 memset((void *)details, 0,
591 sizeof(struct iavf_asq_cmd_details));
593 if (ntc == asq->count)
595 desc = IAVF_ADMINQ_DESC(*asq, ntc);
596 details = IAVF_ADMINQ_DETAILS(*asq, ntc);
599 asq->next_to_clean = ntc;
601 return IAVF_DESC_UNUSED(asq);
605 * iavf_asq_done - check if FW has processed the Admin Send Queue
606 * @hw: pointer to the hw struct
608 * Returns true if the firmware has processed all descriptors on the
609 * admin send queue. Returns false if there are still requests pending.
611 bool iavf_asq_done(struct iavf_hw *hw)
613 /* AQ designers suggest use of head for better
614 * timing reliability than DD bit
616 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use;
620 * iavf_asq_send_command - send command to Admin Queue
621 * @hw: pointer to the hw struct
622 * @desc: prefilled descriptor describing the command (non DMA mem)
623 * @buff: buffer to use for indirect commands
624 * @buff_size: size of buffer for indirect commands
625 * @cmd_details: pointer to command details structure
627 * This is the main send command driver routine for the Admin Queue send
628 * queue. It runs the queue, cleans the queue, etc
630 enum iavf_status iavf_asq_send_command(struct iavf_hw *hw,
631 struct iavf_aq_desc *desc,
632 void *buff, /* can be NULL */
634 struct iavf_asq_cmd_details *cmd_details)
636 struct iavf_dma_mem *dma_buff = NULL;
637 struct iavf_asq_cmd_details *details;
638 struct iavf_aq_desc *desc_on_ring;
639 bool cmd_completed = false;
640 enum iavf_status status = 0;
644 mutex_lock(&hw->aq.asq_mutex);
646 if (hw->aq.asq.count == 0) {
647 iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,
648 "AQTX: Admin queue not initialized.\n");
649 status = IAVF_ERR_QUEUE_EMPTY;
650 goto asq_send_command_error;
653 hw->aq.asq_last_status = IAVF_AQ_RC_OK;
655 val = rd32(hw, hw->aq.asq.head);
656 if (val >= hw->aq.num_asq_entries) {
657 iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,
658 "AQTX: head overrun at %d\n", val);
659 status = IAVF_ERR_QUEUE_EMPTY;
660 goto asq_send_command_error;
663 details = IAVF_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);
665 *details = *cmd_details;
667 /* If the cmd_details are defined copy the cookie. The
668 * cpu_to_le32 is not needed here because the data is ignored
669 * by the FW, only used by the driver
671 if (details->cookie) {
673 cpu_to_le32(upper_32_bits(details->cookie));
675 cpu_to_le32(lower_32_bits(details->cookie));
678 memset(details, 0, sizeof(struct iavf_asq_cmd_details));
681 /* clear requested flags and then set additional flags if defined */
682 desc->flags &= ~cpu_to_le16(details->flags_dis);
683 desc->flags |= cpu_to_le16(details->flags_ena);
685 if (buff_size > hw->aq.asq_buf_size) {
687 IAVF_DEBUG_AQ_MESSAGE,
688 "AQTX: Invalid buffer size: %d.\n",
690 status = IAVF_ERR_INVALID_SIZE;
691 goto asq_send_command_error;
694 if (details->postpone && !details->async) {
696 IAVF_DEBUG_AQ_MESSAGE,
697 "AQTX: Async flag not set along with postpone flag");
698 status = IAVF_ERR_PARAM;
699 goto asq_send_command_error;
702 /* call clean and check queue available function to reclaim the
703 * descriptors that were processed by FW, the function returns the
704 * number of desc available
706 /* the clean function called here could be called in a separate thread
707 * in case of asynchronous completions
709 if (iavf_clean_asq(hw) == 0) {
711 IAVF_DEBUG_AQ_MESSAGE,
712 "AQTX: Error queue is full.\n");
713 status = IAVF_ERR_ADMIN_QUEUE_FULL;
714 goto asq_send_command_error;
717 /* initialize the temp desc pointer with the right desc */
718 desc_on_ring = IAVF_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use);
720 /* if the desc is available copy the temp desc to the right place */
721 *desc_on_ring = *desc;
723 /* if buff is not NULL assume indirect command */
725 dma_buff = &hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use];
726 /* copy the user buff into the respective DMA buff */
727 memcpy(dma_buff->va, buff, buff_size);
728 desc_on_ring->datalen = cpu_to_le16(buff_size);
730 /* Update the address values in the desc with the pa value
731 * for respective buffer
733 desc_on_ring->params.external.addr_high =
734 cpu_to_le32(upper_32_bits(dma_buff->pa));
735 desc_on_ring->params.external.addr_low =
736 cpu_to_le32(lower_32_bits(dma_buff->pa));
740 iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE, "AQTX: desc and buffer:\n");
741 iavf_debug_aq(hw, IAVF_DEBUG_AQ_COMMAND, (void *)desc_on_ring,
743 (hw->aq.asq.next_to_use)++;
744 if (hw->aq.asq.next_to_use == hw->aq.asq.count)
745 hw->aq.asq.next_to_use = 0;
746 if (!details->postpone)
747 wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use);
749 /* if cmd_details are not defined or async flag is not set,
750 * we need to wait for desc write back
752 if (!details->async && !details->postpone) {
756 /* AQ designers suggest use of head for better
757 * timing reliability than DD bit
759 if (iavf_asq_done(hw))
763 } while (total_delay < hw->aq.asq_cmd_timeout);
766 /* if ready, copy the desc back to temp */
767 if (iavf_asq_done(hw)) {
768 *desc = *desc_on_ring;
770 memcpy(buff, dma_buff->va, buff_size);
771 retval = le16_to_cpu(desc->retval);
774 IAVF_DEBUG_AQ_MESSAGE,
775 "AQTX: Command completed with error 0x%X.\n",
778 /* strip off FW internal code */
781 cmd_completed = true;
782 if ((enum iavf_admin_queue_err)retval == IAVF_AQ_RC_OK)
784 else if ((enum iavf_admin_queue_err)retval == IAVF_AQ_RC_EBUSY)
785 status = IAVF_ERR_NOT_READY;
787 status = IAVF_ERR_ADMIN_QUEUE_ERROR;
788 hw->aq.asq_last_status = (enum iavf_admin_queue_err)retval;
791 iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,
792 "AQTX: desc and buffer writeback:\n");
793 iavf_debug_aq(hw, IAVF_DEBUG_AQ_COMMAND, (void *)desc, buff, buff_size);
795 /* save writeback aq if requested */
796 if (details->wb_desc)
797 *details->wb_desc = *desc_on_ring;
799 /* update the error if time out occurred */
800 if ((!cmd_completed) &&
801 (!details->async && !details->postpone)) {
802 if (rd32(hw, hw->aq.asq.len) & IAVF_VF_ATQLEN1_ATQCRIT_MASK) {
803 iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,
804 "AQTX: AQ Critical error.\n");
805 status = IAVF_ERR_ADMIN_QUEUE_CRITICAL_ERROR;
807 iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,
808 "AQTX: Writeback timeout.\n");
809 status = IAVF_ERR_ADMIN_QUEUE_TIMEOUT;
813 asq_send_command_error:
814 mutex_unlock(&hw->aq.asq_mutex);
819 * iavf_fill_default_direct_cmd_desc - AQ descriptor helper function
820 * @desc: pointer to the temp descriptor (non DMA mem)
821 * @opcode: the opcode can be used to decide which flags to turn off or on
823 * Fill the desc with default values
825 void iavf_fill_default_direct_cmd_desc(struct iavf_aq_desc *desc, u16 opcode)
827 /* zero out the desc */
828 memset((void *)desc, 0, sizeof(struct iavf_aq_desc));
829 desc->opcode = cpu_to_le16(opcode);
830 desc->flags = cpu_to_le16(IAVF_AQ_FLAG_SI);
834 * iavf_clean_arq_element
835 * @hw: pointer to the hw struct
836 * @e: event info from the receive descriptor, includes any buffers
837 * @pending: number of events that could be left to process
839 * This function cleans one Admin Receive Queue element and returns
840 * the contents through e. It can also return how many events are
841 * left to process through 'pending'
843 enum iavf_status iavf_clean_arq_element(struct iavf_hw *hw,
844 struct iavf_arq_event_info *e,
847 u16 ntc = hw->aq.arq.next_to_clean;
848 struct iavf_aq_desc *desc;
849 enum iavf_status ret_code = 0;
850 struct iavf_dma_mem *bi;
856 /* pre-clean the event info */
857 memset(&e->desc, 0, sizeof(e->desc));
859 /* take the lock before we start messing with the ring */
860 mutex_lock(&hw->aq.arq_mutex);
862 if (hw->aq.arq.count == 0) {
863 iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,
864 "AQRX: Admin queue not initialized.\n");
865 ret_code = IAVF_ERR_QUEUE_EMPTY;
866 goto clean_arq_element_err;
869 /* set next_to_use to head */
870 ntu = rd32(hw, hw->aq.arq.head) & IAVF_VF_ARQH1_ARQH_MASK;
872 /* nothing to do - shouldn't need to update ring's values */
873 ret_code = IAVF_ERR_ADMIN_QUEUE_NO_WORK;
874 goto clean_arq_element_out;
877 /* now clean the next descriptor */
878 desc = IAVF_ADMINQ_DESC(hw->aq.arq, ntc);
881 hw->aq.arq_last_status =
882 (enum iavf_admin_queue_err)le16_to_cpu(desc->retval);
883 flags = le16_to_cpu(desc->flags);
884 if (flags & IAVF_AQ_FLAG_ERR) {
885 ret_code = IAVF_ERR_ADMIN_QUEUE_ERROR;
887 IAVF_DEBUG_AQ_MESSAGE,
888 "AQRX: Event received with error 0x%X.\n",
889 hw->aq.arq_last_status);
893 datalen = le16_to_cpu(desc->datalen);
894 e->msg_len = min(datalen, e->buf_len);
895 if (e->msg_buf && (e->msg_len != 0))
896 memcpy(e->msg_buf, hw->aq.arq.r.arq_bi[desc_idx].va,
899 iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE, "AQRX: desc and buffer:\n");
900 iavf_debug_aq(hw, IAVF_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf,
901 hw->aq.arq_buf_size);
903 /* Restore the original datalen and buffer address in the desc,
904 * FW updates datalen to indicate the event message
907 bi = &hw->aq.arq.r.arq_bi[ntc];
908 memset((void *)desc, 0, sizeof(struct iavf_aq_desc));
910 desc->flags = cpu_to_le16(IAVF_AQ_FLAG_BUF);
911 if (hw->aq.arq_buf_size > IAVF_AQ_LARGE_BUF)
912 desc->flags |= cpu_to_le16(IAVF_AQ_FLAG_LB);
913 desc->datalen = cpu_to_le16((u16)bi->size);
914 desc->params.external.addr_high = cpu_to_le32(upper_32_bits(bi->pa));
915 desc->params.external.addr_low = cpu_to_le32(lower_32_bits(bi->pa));
917 /* set tail = the last cleaned desc index. */
918 wr32(hw, hw->aq.arq.tail, ntc);
919 /* ntc is updated to tail + 1 */
921 if (ntc == hw->aq.num_arq_entries)
923 hw->aq.arq.next_to_clean = ntc;
924 hw->aq.arq.next_to_use = ntu;
926 clean_arq_element_out:
927 /* Set pending if needed, unlock and return */
929 *pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc);
931 clean_arq_element_err:
932 mutex_unlock(&hw->aq.arq_mutex);