drivers/net/ethernet/intel/i40e/i40e_common.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
   3
   4 #include "i40e_type.h"
   5 #include "i40e_adminq.h"
   6 #include "i40e_prototype.h"
   7 #include <linux/avf/virtchnl.h>
   8
   9 /**
  10  * i40e_set_mac_type - Sets MAC type
  11  * @hw: pointer to the HW structure
  12  *
  13  * This function sets the mac type of the adapter based on the
  14  * vendor ID and device ID stored in the hw structure.
  15  **/
  16 static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
  17 {
  18         i40e_status status = 0;
  19
  20         if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
  21                 switch (hw->device_id) {
  22                 case I40E_DEV_ID_SFP_XL710:
  23                 case I40E_DEV_ID_QEMU:
  24                 case I40E_DEV_ID_KX_B:
  25                 case I40E_DEV_ID_KX_C:
  26                 case I40E_DEV_ID_QSFP_A:
  27                 case I40E_DEV_ID_QSFP_B:
  28                 case I40E_DEV_ID_QSFP_C:
  29                 case I40E_DEV_ID_10G_BASE_T:
  30                 case I40E_DEV_ID_10G_BASE_T4:
  31                 case I40E_DEV_ID_20G_KR2:
  32                 case I40E_DEV_ID_20G_KR2_A:
  33                 case I40E_DEV_ID_25G_B:
  34                 case I40E_DEV_ID_25G_SFP28:
  35                         hw->mac.type = I40E_MAC_XL710;
  36                         break;
  37                 case I40E_DEV_ID_KX_X722:
  38                 case I40E_DEV_ID_QSFP_X722:
  39                 case I40E_DEV_ID_SFP_X722:
  40                 case I40E_DEV_ID_1G_BASE_T_X722:
  41                 case I40E_DEV_ID_10G_BASE_T_X722:
  42                 case I40E_DEV_ID_SFP_I_X722:
  43                         hw->mac.type = I40E_MAC_X722;
  44                         break;
  45                 default:
  46                         hw->mac.type = I40E_MAC_GENERIC;
  47                         break;
  48                 }
  49         } else {
  50                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
  51         }
  52
  53         hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
  54                   hw->mac.type, status);
  55         return status;
  56 }
  57
  58 /**
  59  * i40e_aq_str - convert AQ err code to a string
  60  * @hw: pointer to the HW structure
  61  * @aq_err: the AQ error code to convert
  62  **/
  63 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
  64 {
  65         switch (aq_err) {
  66         case I40E_AQ_RC_OK:
  67                 return "OK";
  68         case I40E_AQ_RC_EPERM:
  69                 return "I40E_AQ_RC_EPERM";
  70         case I40E_AQ_RC_ENOENT:
  71                 return "I40E_AQ_RC_ENOENT";
  72         case I40E_AQ_RC_ESRCH:
  73                 return "I40E_AQ_RC_ESRCH";
  74         case I40E_AQ_RC_EINTR:
  75                 return "I40E_AQ_RC_EINTR";
  76         case I40E_AQ_RC_EIO:
  77                 return "I40E_AQ_RC_EIO";
  78         case I40E_AQ_RC_ENXIO:
  79                 return "I40E_AQ_RC_ENXIO";
  80         case I40E_AQ_RC_E2BIG:
  81                 return "I40E_AQ_RC_E2BIG";
  82         case I40E_AQ_RC_EAGAIN:
  83                 return "I40E_AQ_RC_EAGAIN";
  84         case I40E_AQ_RC_ENOMEM:
  85                 return "I40E_AQ_RC_ENOMEM";
  86         case I40E_AQ_RC_EACCES:
  87                 return "I40E_AQ_RC_EACCES";
  88         case I40E_AQ_RC_EFAULT:
  89                 return "I40E_AQ_RC_EFAULT";
  90         case I40E_AQ_RC_EBUSY:
  91                 return "I40E_AQ_RC_EBUSY";
  92         case I40E_AQ_RC_EEXIST:
  93                 return "I40E_AQ_RC_EEXIST";
  94         case I40E_AQ_RC_EINVAL:
  95                 return "I40E_AQ_RC_EINVAL";
  96         case I40E_AQ_RC_ENOTTY:
  97                 return "I40E_AQ_RC_ENOTTY";
  98         case I40E_AQ_RC_ENOSPC:
  99                 return "I40E_AQ_RC_ENOSPC";
 100         case I40E_AQ_RC_ENOSYS:
 101                 return "I40E_AQ_RC_ENOSYS";
 102         case I40E_AQ_RC_ERANGE:
 103                 return "I40E_AQ_RC_ERANGE";
 104         case I40E_AQ_RC_EFLUSHED:
 105                 return "I40E_AQ_RC_EFLUSHED";
 106         case I40E_AQ_RC_BAD_ADDR:
 107                 return "I40E_AQ_RC_BAD_ADDR";
 108         case I40E_AQ_RC_EMODE:
 109                 return "I40E_AQ_RC_EMODE";
 110         case I40E_AQ_RC_EFBIG:
 111                 return "I40E_AQ_RC_EFBIG";
 112         }
 113
 114         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 115         return hw->err_str;
 116 }
 117
 118 /**
 119  * i40e_stat_str - convert status err code to a string
 120  * @hw: pointer to the HW structure
 121  * @stat_err: the status error code to convert
 122  **/
 123 const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err)
 124 {
 125         switch (stat_err) {
 126         case 0:
 127                 return "OK";
 128         case I40E_ERR_NVM:
 129                 return "I40E_ERR_NVM";
 130         case I40E_ERR_NVM_CHECKSUM:
 131                 return "I40E_ERR_NVM_CHECKSUM";
 132         case I40E_ERR_PHY:
 133                 return "I40E_ERR_PHY";
 134         case I40E_ERR_CONFIG:
 135                 return "I40E_ERR_CONFIG";
 136         case I40E_ERR_PARAM:
 137                 return "I40E_ERR_PARAM";
 138         case I40E_ERR_MAC_TYPE:
 139                 return "I40E_ERR_MAC_TYPE";
 140         case I40E_ERR_UNKNOWN_PHY:
 141                 return "I40E_ERR_UNKNOWN_PHY";
 142         case I40E_ERR_LINK_SETUP:
 143                 return "I40E_ERR_LINK_SETUP";
 144         case I40E_ERR_ADAPTER_STOPPED:
 145                 return "I40E_ERR_ADAPTER_STOPPED";
 146         case I40E_ERR_INVALID_MAC_ADDR:
 147                 return "I40E_ERR_INVALID_MAC_ADDR";
 148         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 149                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 150         case I40E_ERR_MASTER_REQUESTS_PENDING:
 151                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 152         case I40E_ERR_INVALID_LINK_SETTINGS:
 153                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 154         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 155                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 156         case I40E_ERR_RESET_FAILED:
 157                 return "I40E_ERR_RESET_FAILED";
 158         case I40E_ERR_SWFW_SYNC:
 159                 return "I40E_ERR_SWFW_SYNC";
 160         case I40E_ERR_NO_AVAILABLE_VSI:
 161                 return "I40E_ERR_NO_AVAILABLE_VSI";
 162         case I40E_ERR_NO_MEMORY:
 163                 return "I40E_ERR_NO_MEMORY";
 164         case I40E_ERR_BAD_PTR:
 165                 return "I40E_ERR_BAD_PTR";
 166         case I40E_ERR_RING_FULL:
 167                 return "I40E_ERR_RING_FULL";
 168         case I40E_ERR_INVALID_PD_ID:
 169                 return "I40E_ERR_INVALID_PD_ID";
 170         case I40E_ERR_INVALID_QP_ID:
 171                 return "I40E_ERR_INVALID_QP_ID";
 172         case I40E_ERR_INVALID_CQ_ID:
 173                 return "I40E_ERR_INVALID_CQ_ID";
 174         case I40E_ERR_INVALID_CEQ_ID:
 175                 return "I40E_ERR_INVALID_CEQ_ID";
 176         case I40E_ERR_INVALID_AEQ_ID:
 177                 return "I40E_ERR_INVALID_AEQ_ID";
 178         case I40E_ERR_INVALID_SIZE:
 179                 return "I40E_ERR_INVALID_SIZE";
 180         case I40E_ERR_INVALID_ARP_INDEX:
 181                 return "I40E_ERR_INVALID_ARP_INDEX";
 182         case I40E_ERR_INVALID_FPM_FUNC_ID:
 183                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 184         case I40E_ERR_QP_INVALID_MSG_SIZE:
 185                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 186         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 187                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 188         case I40E_ERR_INVALID_FRAG_COUNT:
 189                 return "I40E_ERR_INVALID_FRAG_COUNT";
 190         case I40E_ERR_QUEUE_EMPTY:
 191                 return "I40E_ERR_QUEUE_EMPTY";
 192         case I40E_ERR_INVALID_ALIGNMENT:
 193                 return "I40E_ERR_INVALID_ALIGNMENT";
 194         case I40E_ERR_FLUSHED_QUEUE:
 195                 return "I40E_ERR_FLUSHED_QUEUE";
 196         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 197                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 198         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 199                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 200         case I40E_ERR_TIMEOUT:
 201                 return "I40E_ERR_TIMEOUT";
 202         case I40E_ERR_OPCODE_MISMATCH:
 203                 return "I40E_ERR_OPCODE_MISMATCH";
 204         case I40E_ERR_CQP_COMPL_ERROR:
 205                 return "I40E_ERR_CQP_COMPL_ERROR";
 206         case I40E_ERR_INVALID_VF_ID:
 207                 return "I40E_ERR_INVALID_VF_ID";
 208         case I40E_ERR_INVALID_HMCFN_ID:
 209                 return "I40E_ERR_INVALID_HMCFN_ID";
 210         case I40E_ERR_BACKING_PAGE_ERROR:
 211                 return "I40E_ERR_BACKING_PAGE_ERROR";
 212         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 213                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 214         case I40E_ERR_INVALID_PBLE_INDEX:
 215                 return "I40E_ERR_INVALID_PBLE_INDEX";
 216         case I40E_ERR_INVALID_SD_INDEX:
 217                 return "I40E_ERR_INVALID_SD_INDEX";
 218         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 219                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 220         case I40E_ERR_INVALID_SD_TYPE:
 221                 return "I40E_ERR_INVALID_SD_TYPE";
 222         case I40E_ERR_MEMCPY_FAILED:
 223                 return "I40E_ERR_MEMCPY_FAILED";
 224         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 225                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 226         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 227                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 228         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 229                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 230         case I40E_ERR_SRQ_ENABLED:
 231                 return "I40E_ERR_SRQ_ENABLED";
 232         case I40E_ERR_ADMIN_QUEUE_ERROR:
 233                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 234         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 235                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 236         case I40E_ERR_BUF_TOO_SHORT:
 237                 return "I40E_ERR_BUF_TOO_SHORT";
 238         case I40E_ERR_ADMIN_QUEUE_FULL:
 239                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 240         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 241                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 242         case I40E_ERR_BAD_IWARP_CQE:
 243                 return "I40E_ERR_BAD_IWARP_CQE";
 244         case I40E_ERR_NVM_BLANK_MODE:
 245                 return "I40E_ERR_NVM_BLANK_MODE";
 246         case I40E_ERR_NOT_IMPLEMENTED:
 247                 return "I40E_ERR_NOT_IMPLEMENTED";
 248         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 249                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 250         case I40E_ERR_DIAG_TEST_FAILED:
 251                 return "I40E_ERR_DIAG_TEST_FAILED";
 252         case I40E_ERR_NOT_READY:
 253                 return "I40E_ERR_NOT_READY";
 254         case I40E_NOT_SUPPORTED:
 255                 return "I40E_NOT_SUPPORTED";
 256         case I40E_ERR_FIRMWARE_API_VERSION:
 257                 return "I40E_ERR_FIRMWARE_API_VERSION";
 258         case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
 259                 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
 260         }
 261
 262         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 263         return hw->err_str;
 264 }
 265
 266 /**
 267  * i40e_debug_aq
 268  * @hw: debug mask related to admin queue
 269  * @mask: debug mask
 270  * @desc: pointer to admin queue descriptor
 271  * @buffer: pointer to command buffer
 272  * @buf_len: max length of buffer
 273  *
 274  * Dumps debug log about adminq command with descriptor contents.
 275  **/
 276 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 277                    void *buffer, u16 buf_len)
 278 {
 279         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 280         u16 len;
 281         u8 *buf = (u8 *)buffer;
 282
 283         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 284                 return;
 285
 286         len = le16_to_cpu(aq_desc->datalen);
 287
 288         i40e_debug(hw, mask,
 289                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 290                    le16_to_cpu(aq_desc->opcode),
 291                    le16_to_cpu(aq_desc->flags),
 292                    le16_to_cpu(aq_desc->datalen),
 293                    le16_to_cpu(aq_desc->retval));
 294         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 295                    le32_to_cpu(aq_desc->cookie_high),
 296                    le32_to_cpu(aq_desc->cookie_low));
 297         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 298                    le32_to_cpu(aq_desc->params.internal.param0),
 299                    le32_to_cpu(aq_desc->params.internal.param1));
 300         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 301                    le32_to_cpu(aq_desc->params.external.addr_high),
 302                    le32_to_cpu(aq_desc->params.external.addr_low));
 303
 304         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 305                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 306                 if (buf_len < len)
 307                         len = buf_len;
 308                 /* write the full 16-byte chunks */
 309                 if (hw->debug_mask & mask) {
 310                         char prefix[27];
 311
 312                         snprintf(prefix, sizeof(prefix),
 313                                  "i40e %02x:%02x.%x: \t0x",
 314                                  hw->bus.bus_id,
 315                                  hw->bus.device,
 316                                  hw->bus.func);
 317
 318                         print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET,
 319                                        16, 1, buf, len, false);
 320                 }
 321         }
 322 }
 323
 324 /**
 325  * i40e_check_asq_alive
 326  * @hw: pointer to the hw struct
 327  *
 328  * Returns true if Queue is enabled else false.
 329  **/
 330 bool i40e_check_asq_alive(struct i40e_hw *hw)
 331 {
 332         if (hw->aq.asq.len)
 333                 return !!(rd32(hw, hw->aq.asq.len) &
 334                           I40E_PF_ATQLEN_ATQENABLE_MASK);
 335         else
 336                 return false;
 337 }
 338
 339 /**
 340  * i40e_aq_queue_shutdown
 341  * @hw: pointer to the hw struct
 342  * @unloading: is the driver unloading itself
 343  *
 344  * Tell the Firmware that we're shutting down the AdminQ and whether
 345  * or not the driver is unloading as well.
 346  **/
 347 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
 348                                              bool unloading)
 349 {
 350         struct i40e_aq_desc desc;
 351         struct i40e_aqc_queue_shutdown *cmd =
 352                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 353         i40e_status status;
 354
 355         i40e_fill_default_direct_cmd_desc(&desc,
 356                                           i40e_aqc_opc_queue_shutdown);
 357
 358         if (unloading)
 359                 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
 360         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 361
 362         return status;
 363 }
 364
 365 /**
 366  * i40e_aq_get_set_rss_lut
 367  * @hw: pointer to the hardware structure
 368  * @vsi_id: vsi fw index
 369  * @pf_lut: for PF table set true, for VSI table set false
 370  * @lut: pointer to the lut buffer provided by the caller
 371  * @lut_size: size of the lut buffer
 372  * @set: set true to set the table, false to get the table
 373  *
 374  * Internal function to get or set RSS look up table
 375  **/
 376 static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 377                                            u16 vsi_id, bool pf_lut,
 378                                            u8 *lut, u16 lut_size,
 379                                            bool set)
 380 {
 381         i40e_status status;
 382         struct i40e_aq_desc desc;
 383         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 384                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 385
 386         if (set)
 387                 i40e_fill_default_direct_cmd_desc(&desc,
 388                                                   i40e_aqc_opc_set_rss_lut);
 389         else
 390                 i40e_fill_default_direct_cmd_desc(&desc,
 391                                                   i40e_aqc_opc_get_rss_lut);
 392
 393         /* Indirect command */
 394         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
 395         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
 396
 397         cmd_resp->vsi_id =
 398                         cpu_to_le16((u16)((vsi_id <<
 399                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 400                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 401         cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 402
 403         if (pf_lut)
 404                 cmd_resp->flags |= cpu_to_le16((u16)
 405                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 406                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 407                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 408         else
 409                 cmd_resp->flags |= cpu_to_le16((u16)
 410                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 411                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 412                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 413
 414         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 415
 416         return status;
 417 }
 418
 419 /**
 420  * i40e_aq_get_rss_lut
 421  * @hw: pointer to the hardware structure
 422  * @vsi_id: vsi fw index
 423  * @pf_lut: for PF table set true, for VSI table set false
 424  * @lut: pointer to the lut buffer provided by the caller
 425  * @lut_size: size of the lut buffer
 426  *
 427  * get the RSS lookup table, PF or VSI type
 428  **/
 429 i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 430                                 bool pf_lut, u8 *lut, u16 lut_size)
 431 {
 432         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 433                                        false);
 434 }
 435
 436 /**
 437  * i40e_aq_set_rss_lut
 438  * @hw: pointer to the hardware structure
 439  * @vsi_id: vsi fw index
 440  * @pf_lut: for PF table set true, for VSI table set false
 441  * @lut: pointer to the lut buffer provided by the caller
 442  * @lut_size: size of the lut buffer
 443  *
 444  * set the RSS lookup table, PF or VSI type
 445  **/
 446 i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 447                                 bool pf_lut, u8 *lut, u16 lut_size)
 448 {
 449         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 450 }
 451
 452 /**
 453  * i40e_aq_get_set_rss_key
 454  * @hw: pointer to the hw struct
 455  * @vsi_id: vsi fw index
 456  * @key: pointer to key info struct
 457  * @set: set true to set the key, false to get the key
 458  *
 459  * get the RSS key per VSI
 460  **/
 461 static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 462                                       u16 vsi_id,
 463                                       struct i40e_aqc_get_set_rss_key_data *key,
 464                                       bool set)
 465 {
 466         i40e_status status;
 467         struct i40e_aq_desc desc;
 468         struct i40e_aqc_get_set_rss_key *cmd_resp =
 469                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 470         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 471
 472         if (set)
 473                 i40e_fill_default_direct_cmd_desc(&desc,
 474                                                   i40e_aqc_opc_set_rss_key);
 475         else
 476                 i40e_fill_default_direct_cmd_desc(&desc,
 477                                                   i40e_aqc_opc_get_rss_key);
 478
 479         /* Indirect command */
 480         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
 481         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
 482
 483         cmd_resp->vsi_id =
 484                         cpu_to_le16((u16)((vsi_id <<
 485                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 486                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 487         cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 488
 489         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 490
 491         return status;
 492 }
 493
 494 /**
 495  * i40e_aq_get_rss_key
 496  * @hw: pointer to the hw struct
 497  * @vsi_id: vsi fw index
 498  * @key: pointer to key info struct
 499  *
 500  **/
 501 i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw,
 502                                 u16 vsi_id,
 503                                 struct i40e_aqc_get_set_rss_key_data *key)
 504 {
 505         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 506 }
 507
 508 /**
 509  * i40e_aq_set_rss_key
 510  * @hw: pointer to the hw struct
 511  * @vsi_id: vsi fw index
 512  * @key: pointer to key info struct
 513  *
 514  * set the RSS key per VSI
 515  **/
 516 i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,
 517                                 u16 vsi_id,
 518                                 struct i40e_aqc_get_set_rss_key_data *key)
 519 {
 520         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 521 }
 522
 523 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 524  * hardware to a bit-field that can be used by SW to more easily determine the
 525  * packet type.
 526  *
 527  * Macros are used to shorten the table lines and make this table human
 528  * readable.
 529  *
 530  * We store the PTYPE in the top byte of the bit field - this is just so that
 531  * we can check that the table doesn't have a row missing, as the index into
 532  * the table should be the PTYPE.
 533  *
 534  * Typical work flow:
 535  *
 536  * IF NOT i40e_ptype_lookup[ptype].known
 537  * THEN
 538  *      Packet is unknown
 539  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 540  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 541  * ELSE
 542  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 543  * ENDIF
 544  */
 545
 546 /* macro to make the table lines short */
 547 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 548         {       PTYPE, \
 549                 1, \
 550                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 551                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 552                 I40E_RX_PTYPE_##OUTER_FRAG, \
 553                 I40E_RX_PTYPE_TUNNEL_##T, \
 554                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 555                 I40E_RX_PTYPE_##TEF, \
 556                 I40E_RX_PTYPE_INNER_PROT_##I, \
 557                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 558
 559 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 560                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 561
 562 /* shorter macros makes the table fit but are terse */
 563 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 564 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 565 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 566
 567 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 568 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 569         /* L2 Packet types */
 570         I40E_PTT_UNUSED_ENTRY(0),
 571         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 572         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 573         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 574         I40E_PTT_UNUSED_ENTRY(4),
 575         I40E_PTT_UNUSED_ENTRY(5),
 576         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 577         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 578         I40E_PTT_UNUSED_ENTRY(8),
 579         I40E_PTT_UNUSED_ENTRY(9),
 580         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 581         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 582         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 583         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 584         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 585         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 586         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 587         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 588         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 589         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 590         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 591         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 592
 593         /* Non Tunneled IPv4 */
 594         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 595         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 596         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 597         I40E_PTT_UNUSED_ENTRY(25),
 598         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 599         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 600         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 601
 602         /* IPv4 --> IPv4 */
 603         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 604         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 605         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 606         I40E_PTT_UNUSED_ENTRY(32),
 607         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 608         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 609         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 610
 611         /* IPv4 --> IPv6 */
 612         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 613         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 614         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 615         I40E_PTT_UNUSED_ENTRY(39),
 616         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 617         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 618         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 619
 620         /* IPv4 --> GRE/NAT */
 621         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 622
 623         /* IPv4 --> GRE/NAT --> IPv4 */
 624         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 625         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 626         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 627         I40E_PTT_UNUSED_ENTRY(47),
 628         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 629         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 630         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 631
 632         /* IPv4 --> GRE/NAT --> IPv6 */
 633         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 634         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 635         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 636         I40E_PTT_UNUSED_ENTRY(54),
 637         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 638         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 639         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 640
 641         /* IPv4 --> GRE/NAT --> MAC */
 642         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 643
 644         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 645         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 646         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 647         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 648         I40E_PTT_UNUSED_ENTRY(62),
 649         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 650         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 651         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 652
 653         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 654         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 655         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 656         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 657         I40E_PTT_UNUSED_ENTRY(69),
 658         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 659         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 660         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 661
 662         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 663         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 664
 665         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 666         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 667         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 668         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 669         I40E_PTT_UNUSED_ENTRY(77),
 670         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 671         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 672         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 673
 674         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 675         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 676         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 677         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 678         I40E_PTT_UNUSED_ENTRY(84),
 679         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 680         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 681         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 682
 683         /* Non Tunneled IPv6 */
 684         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 685         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 686         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 687         I40E_PTT_UNUSED_ENTRY(91),
 688         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 689         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 690         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 691
 692         /* IPv6 --> IPv4 */
 693         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 694         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 695         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 696         I40E_PTT_UNUSED_ENTRY(98),
 697         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 698         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 699         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 700
 701         /* IPv6 --> IPv6 */
 702         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 703         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 704         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 705         I40E_PTT_UNUSED_ENTRY(105),
 706         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 707         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 708         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 709
 710         /* IPv6 --> GRE/NAT */
 711         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 712
 713         /* IPv6 --> GRE/NAT -> IPv4 */
 714         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 715         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 716         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 717         I40E_PTT_UNUSED_ENTRY(113),
 718         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 719         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 720         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 721
 722         /* IPv6 --> GRE/NAT -> IPv6 */
 723         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 724         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 725         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 726         I40E_PTT_UNUSED_ENTRY(120),
 727         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 728         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 729         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 730
 731         /* IPv6 --> GRE/NAT -> MAC */
 732         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 733
 734         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 735         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 736         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 737         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 738         I40E_PTT_UNUSED_ENTRY(128),
 739         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 740         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 741         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 742
 743         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 744         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 745         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 746         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 747         I40E_PTT_UNUSED_ENTRY(135),
 748         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 749         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 750         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 751
 752         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 753         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 754
 755         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 756         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 757         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 758         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 759         I40E_PTT_UNUSED_ENTRY(143),
 760         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 761         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 762         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 763
 764         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 765         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 766         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 767         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 768         I40E_PTT_UNUSED_ENTRY(150),
 769         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 770         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 771         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 772
 773         /* unused entries */
 774         I40E_PTT_UNUSED_ENTRY(154),
 775         I40E_PTT_UNUSED_ENTRY(155),
 776         I40E_PTT_UNUSED_ENTRY(156),
 777         I40E_PTT_UNUSED_ENTRY(157),
 778         I40E_PTT_UNUSED_ENTRY(158),
 779         I40E_PTT_UNUSED_ENTRY(159),
 780
 781         I40E_PTT_UNUSED_ENTRY(160),
 782         I40E_PTT_UNUSED_ENTRY(161),
 783         I40E_PTT_UNUSED_ENTRY(162),
 784         I40E_PTT_UNUSED_ENTRY(163),
 785         I40E_PTT_UNUSED_ENTRY(164),
 786         I40E_PTT_UNUSED_ENTRY(165),
 787         I40E_PTT_UNUSED_ENTRY(166),
 788         I40E_PTT_UNUSED_ENTRY(167),
 789         I40E_PTT_UNUSED_ENTRY(168),
 790         I40E_PTT_UNUSED_ENTRY(169),
 791
 792         I40E_PTT_UNUSED_ENTRY(170),
 793         I40E_PTT_UNUSED_ENTRY(171),
 794         I40E_PTT_UNUSED_ENTRY(172),
 795         I40E_PTT_UNUSED_ENTRY(173),
 796         I40E_PTT_UNUSED_ENTRY(174),
 797         I40E_PTT_UNUSED_ENTRY(175),
 798         I40E_PTT_UNUSED_ENTRY(176),
 799         I40E_PTT_UNUSED_ENTRY(177),
 800         I40E_PTT_UNUSED_ENTRY(178),
 801         I40E_PTT_UNUSED_ENTRY(179),
 802
 803         I40E_PTT_UNUSED_ENTRY(180),
 804         I40E_PTT_UNUSED_ENTRY(181),
 805         I40E_PTT_UNUSED_ENTRY(182),
 806         I40E_PTT_UNUSED_ENTRY(183),
 807         I40E_PTT_UNUSED_ENTRY(184),
 808         I40E_PTT_UNUSED_ENTRY(185),
 809         I40E_PTT_UNUSED_ENTRY(186),
 810         I40E_PTT_UNUSED_ENTRY(187),
 811         I40E_PTT_UNUSED_ENTRY(188),
 812         I40E_PTT_UNUSED_ENTRY(189),
 813
 814         I40E_PTT_UNUSED_ENTRY(190),
 815         I40E_PTT_UNUSED_ENTRY(191),
 816         I40E_PTT_UNUSED_ENTRY(192),
 817         I40E_PTT_UNUSED_ENTRY(193),
 818         I40E_PTT_UNUSED_ENTRY(194),
 819         I40E_PTT_UNUSED_ENTRY(195),
 820         I40E_PTT_UNUSED_ENTRY(196),
 821         I40E_PTT_UNUSED_ENTRY(197),
 822         I40E_PTT_UNUSED_ENTRY(198),
 823         I40E_PTT_UNUSED_ENTRY(199),
 824
 825         I40E_PTT_UNUSED_ENTRY(200),
 826         I40E_PTT_UNUSED_ENTRY(201),
 827         I40E_PTT_UNUSED_ENTRY(202),
 828         I40E_PTT_UNUSED_ENTRY(203),
 829         I40E_PTT_UNUSED_ENTRY(204),
 830         I40E_PTT_UNUSED_ENTRY(205),
 831         I40E_PTT_UNUSED_ENTRY(206),
 832         I40E_PTT_UNUSED_ENTRY(207),
 833         I40E_PTT_UNUSED_ENTRY(208),
 834         I40E_PTT_UNUSED_ENTRY(209),
 835
 836         I40E_PTT_UNUSED_ENTRY(210),
 837         I40E_PTT_UNUSED_ENTRY(211),
 838         I40E_PTT_UNUSED_ENTRY(212),
 839         I40E_PTT_UNUSED_ENTRY(213),
 840         I40E_PTT_UNUSED_ENTRY(214),
 841         I40E_PTT_UNUSED_ENTRY(215),
 842         I40E_PTT_UNUSED_ENTRY(216),
 843         I40E_PTT_UNUSED_ENTRY(217),
 844         I40E_PTT_UNUSED_ENTRY(218),
 845         I40E_PTT_UNUSED_ENTRY(219),
 846
 847         I40E_PTT_UNUSED_ENTRY(220),
 848         I40E_PTT_UNUSED_ENTRY(221),
 849         I40E_PTT_UNUSED_ENTRY(222),
 850         I40E_PTT_UNUSED_ENTRY(223),
 851         I40E_PTT_UNUSED_ENTRY(224),
 852         I40E_PTT_UNUSED_ENTRY(225),
 853         I40E_PTT_UNUSED_ENTRY(226),
 854         I40E_PTT_UNUSED_ENTRY(227),
 855         I40E_PTT_UNUSED_ENTRY(228),
 856         I40E_PTT_UNUSED_ENTRY(229),
 857
 858         I40E_PTT_UNUSED_ENTRY(230),
 859         I40E_PTT_UNUSED_ENTRY(231),
 860         I40E_PTT_UNUSED_ENTRY(232),
 861         I40E_PTT_UNUSED_ENTRY(233),
 862         I40E_PTT_UNUSED_ENTRY(234),
 863         I40E_PTT_UNUSED_ENTRY(235),
 864         I40E_PTT_UNUSED_ENTRY(236),
 865         I40E_PTT_UNUSED_ENTRY(237),
 866         I40E_PTT_UNUSED_ENTRY(238),
 867         I40E_PTT_UNUSED_ENTRY(239),
 868
 869         I40E_PTT_UNUSED_ENTRY(240),
 870         I40E_PTT_UNUSED_ENTRY(241),
 871         I40E_PTT_UNUSED_ENTRY(242),
 872         I40E_PTT_UNUSED_ENTRY(243),
 873         I40E_PTT_UNUSED_ENTRY(244),
 874         I40E_PTT_UNUSED_ENTRY(245),
 875         I40E_PTT_UNUSED_ENTRY(246),
 876         I40E_PTT_UNUSED_ENTRY(247),
 877         I40E_PTT_UNUSED_ENTRY(248),
 878         I40E_PTT_UNUSED_ENTRY(249),
 879
 880         I40E_PTT_UNUSED_ENTRY(250),
 881         I40E_PTT_UNUSED_ENTRY(251),
 882         I40E_PTT_UNUSED_ENTRY(252),
 883         I40E_PTT_UNUSED_ENTRY(253),
 884         I40E_PTT_UNUSED_ENTRY(254),
 885         I40E_PTT_UNUSED_ENTRY(255)
 886 };
 887
 888 /**
 889  * i40e_init_shared_code - Initialize the shared code
 890  * @hw: pointer to hardware structure
 891  *
 892  * This assigns the MAC type and PHY code and inits the NVM.
 893  * Does not touch the hardware. This function must be called prior to any
 894  * other function in the shared code. The i40e_hw structure should be
 895  * memset to 0 prior to calling this function.  The following fields in
 896  * hw structure should be filled in prior to calling this function:
 897  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
 898  * subsystem_vendor_id, and revision_id
 899  **/
 900 i40e_status i40e_init_shared_code(struct i40e_hw *hw)
 901 {
 902         i40e_status status = 0;
 903         u32 port, ari, func_rid;
 904
 905         i40e_set_mac_type(hw);
 906
 907         switch (hw->mac.type) {
 908         case I40E_MAC_XL710:
 909         case I40E_MAC_X722:
 910                 break;
 911         default:
 912                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
 913         }
 914
 915         hw->phy.get_link_info = true;
 916
 917         /* Determine port number and PF number*/
 918         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
 919                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
 920         hw->port = (u8)port;
 921         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
 922                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
 923         func_rid = rd32(hw, I40E_PF_FUNC_RID);
 924         if (ari)
 925                 hw->pf_id = (u8)(func_rid & 0xff);
 926         else
 927                 hw->pf_id = (u8)(func_rid & 0x7);
 928
 929         if (hw->mac.type == I40E_MAC_X722)
 930                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
 931                              I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
 932
 933         status = i40e_init_nvm(hw);
 934         return status;
 935 }
 936
 937 /**
 938  * i40e_aq_mac_address_read - Retrieve the MAC addresses
 939  * @hw: pointer to the hw struct
 940  * @flags: a return indicator of what addresses were added to the addr store
 941  * @addrs: the requestor's mac addr store
 942  * @cmd_details: pointer to command details structure or NULL
 943  **/
 944 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
 945                                    u16 *flags,
 946                                    struct i40e_aqc_mac_address_read_data *addrs,
 947                                    struct i40e_asq_cmd_details *cmd_details)
 948 {
 949         struct i40e_aq_desc desc;
 950         struct i40e_aqc_mac_address_read *cmd_data =
 951                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
 952         i40e_status status;
 953
 954         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
 955         desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
 956
 957         status = i40e_asq_send_command(hw, &desc, addrs,
 958                                        sizeof(*addrs), cmd_details);
 959         *flags = le16_to_cpu(cmd_data->command_flags);
 960
 961         return status;
 962 }
 963
 964 /**
 965  * i40e_aq_mac_address_write - Change the MAC addresses
 966  * @hw: pointer to the hw struct
 967  * @flags: indicates which MAC to be written
 968  * @mac_addr: address to write
 969  * @cmd_details: pointer to command details structure or NULL
 970  **/
 971 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
 972                                     u16 flags, u8 *mac_addr,
 973                                     struct i40e_asq_cmd_details *cmd_details)
 974 {
 975         struct i40e_aq_desc desc;
 976         struct i40e_aqc_mac_address_write *cmd_data =
 977                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
 978         i40e_status status;
 979
 980         i40e_fill_default_direct_cmd_desc(&desc,
 981                                           i40e_aqc_opc_mac_address_write);
 982         cmd_data->command_flags = cpu_to_le16(flags);
 983         cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
 984         cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
 985                                         ((u32)mac_addr[3] << 16) |
 986                                         ((u32)mac_addr[4] << 8) |
 987                                         mac_addr[5]);
 988
 989         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
 990
 991         return status;
 992 }
 993
 994 /**
 995  * i40e_get_mac_addr - get MAC address
 996  * @hw: pointer to the HW structure
 997  * @mac_addr: pointer to MAC address
 998  *
 999  * Reads the adapter's MAC address from register
1000  **/
1001 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1002 {
1003         struct i40e_aqc_mac_address_read_data addrs;
1004         i40e_status status;
1005         u16 flags = 0;
1006
1007         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1008
1009         if (flags & I40E_AQC_LAN_ADDR_VALID)
1010                 ether_addr_copy(mac_addr, addrs.pf_lan_mac);
1011
1012         return status;
1013 }
1014
1015 /**
1016  * i40e_get_port_mac_addr - get Port MAC address
1017  * @hw: pointer to the HW structure
1018  * @mac_addr: pointer to Port MAC address
1019  *
1020  * Reads the adapter's Port MAC address
1021  **/
1022 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1023 {
1024         struct i40e_aqc_mac_address_read_data addrs;
1025         i40e_status status;
1026         u16 flags = 0;
1027
1028         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1029         if (status)
1030                 return status;
1031
1032         if (flags & I40E_AQC_PORT_ADDR_VALID)
1033                 ether_addr_copy(mac_addr, addrs.port_mac);
1034         else
1035                 status = I40E_ERR_INVALID_MAC_ADDR;
1036
1037         return status;
1038 }
1039
1040 /**
1041  * i40e_pre_tx_queue_cfg - pre tx queue configure
1042  * @hw: pointer to the HW structure
1043  * @queue: target PF queue index
1044  * @enable: state change request
1045  *
1046  * Handles hw requirement to indicate intention to enable
1047  * or disable target queue.
1048  **/
1049 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1050 {
1051         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1052         u32 reg_block = 0;
1053         u32 reg_val;
1054
1055         if (abs_queue_idx >= 128) {
1056                 reg_block = abs_queue_idx / 128;
1057                 abs_queue_idx %= 128;
1058         }
1059
1060         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1061         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1062         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1063
1064         if (enable)
1065                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1066         else
1067                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1068
1069         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1070 }
1071
1072 /**
1073  *  i40e_read_pba_string - Reads part number string from EEPROM
1074  *  @hw: pointer to hardware structure
1075  *  @pba_num: stores the part number string from the EEPROM
1076  *  @pba_num_size: part number string buffer length
1077  *
1078  *  Reads the part number string from the EEPROM.
1079  **/
1080 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1081                                  u32 pba_num_size)
1082 {
1083         i40e_status status = 0;
1084         u16 pba_word = 0;
1085         u16 pba_size = 0;
1086         u16 pba_ptr = 0;
1087         u16 i = 0;
1088
1089         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1090         if (status || (pba_word != 0xFAFA)) {
1091                 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
1092                 return status;
1093         }
1094
1095         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1096         if (status) {
1097                 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
1098                 return status;
1099         }
1100
1101         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1102         if (status) {
1103                 hw_dbg(hw, "Failed to read PBA Block size.\n");
1104                 return status;
1105         }
1106
1107         /* Subtract one to get PBA word count (PBA Size word is included in
1108          * total size)
1109          */
1110         pba_size--;
1111         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1112                 hw_dbg(hw, "Buffer to small for PBA data.\n");
1113                 return I40E_ERR_PARAM;
1114         }
1115
1116         for (i = 0; i < pba_size; i++) {
1117                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1118                 if (status) {
1119                         hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
1120                         return status;
1121                 }
1122
1123                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1124                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1125         }
1126         pba_num[(pba_size * 2)] = '\0';
1127
1128         return status;
1129 }
1130
1131 /**
1132  * i40e_get_media_type - Gets media type
1133  * @hw: pointer to the hardware structure
1134  **/
1135 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1136 {
1137         enum i40e_media_type media;
1138
1139         switch (hw->phy.link_info.phy_type) {
1140         case I40E_PHY_TYPE_10GBASE_SR:
1141         case I40E_PHY_TYPE_10GBASE_LR:
1142         case I40E_PHY_TYPE_1000BASE_SX:
1143         case I40E_PHY_TYPE_1000BASE_LX:
1144         case I40E_PHY_TYPE_40GBASE_SR4:
1145         case I40E_PHY_TYPE_40GBASE_LR4:
1146         case I40E_PHY_TYPE_25GBASE_LR:
1147         case I40E_PHY_TYPE_25GBASE_SR:
1148                 media = I40E_MEDIA_TYPE_FIBER;
1149                 break;
1150         case I40E_PHY_TYPE_100BASE_TX:
1151         case I40E_PHY_TYPE_1000BASE_T:
1152         case I40E_PHY_TYPE_10GBASE_T:
1153                 media = I40E_MEDIA_TYPE_BASET;
1154                 break;
1155         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1156         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1157         case I40E_PHY_TYPE_10GBASE_CR1:
1158         case I40E_PHY_TYPE_40GBASE_CR4:
1159         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1160         case I40E_PHY_TYPE_40GBASE_AOC:
1161         case I40E_PHY_TYPE_10GBASE_AOC:
1162         case I40E_PHY_TYPE_25GBASE_CR:
1163         case I40E_PHY_TYPE_25GBASE_AOC:
1164         case I40E_PHY_TYPE_25GBASE_ACC:
1165                 media = I40E_MEDIA_TYPE_DA;
1166                 break;
1167         case I40E_PHY_TYPE_1000BASE_KX:
1168         case I40E_PHY_TYPE_10GBASE_KX4:
1169         case I40E_PHY_TYPE_10GBASE_KR:
1170         case I40E_PHY_TYPE_40GBASE_KR4:
1171         case I40E_PHY_TYPE_20GBASE_KR2:
1172         case I40E_PHY_TYPE_25GBASE_KR:
1173                 media = I40E_MEDIA_TYPE_BACKPLANE;
1174                 break;
1175         case I40E_PHY_TYPE_SGMII:
1176         case I40E_PHY_TYPE_XAUI:
1177         case I40E_PHY_TYPE_XFI:
1178         case I40E_PHY_TYPE_XLAUI:
1179         case I40E_PHY_TYPE_XLPPI:
1180         default:
1181                 media = I40E_MEDIA_TYPE_UNKNOWN;
1182                 break;
1183         }
1184
1185         return media;
1186 }
1187
1188 /**
1189  * i40e_poll_globr - Poll for Global Reset completion
1190  * @hw: pointer to the hardware structure
1191  * @retry_limit: how many times to retry before failure
1192  **/
1193 static i40e_status i40e_poll_globr(struct i40e_hw *hw,
1194                                    u32 retry_limit)
1195 {
1196         u32 cnt, reg = 0;
1197
1198         for (cnt = 0; cnt < retry_limit; cnt++) {
1199                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1200                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1201                         return 0;
1202                 msleep(100);
1203         }
1204
1205         hw_dbg(hw, "Global reset failed.\n");
1206         hw_dbg(hw, "I40E_GLGEN_RSTAT = 0x%x\n", reg);
1207
1208         return I40E_ERR_RESET_FAILED;
1209 }
1210
1211 #define I40E_PF_RESET_WAIT_COUNT_A0     200
1212 #define I40E_PF_RESET_WAIT_COUNT        200
1213 /**
1214  * i40e_pf_reset - Reset the PF
1215  * @hw: pointer to the hardware structure
1216  *
1217  * Assuming someone else has triggered a global reset,
1218  * assure the global reset is complete and then reset the PF
1219  **/
1220 i40e_status i40e_pf_reset(struct i40e_hw *hw)
1221 {
1222         u32 cnt = 0;
1223         u32 cnt1 = 0;
1224         u32 reg = 0;
1225         u32 grst_del;
1226
1227         /* Poll for Global Reset steady state in case of recent GRST.
1228          * The grst delay value is in 100ms units, and we'll wait a
1229          * couple counts longer to be sure we don't just miss the end.
1230          */
1231         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1232                     I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1233                     I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1234
1235         /* It can take upto 15 secs for GRST steady state.
1236          * Bump it to 16 secs max to be safe.
1237          */
1238         grst_del = grst_del * 20;
1239
1240         for (cnt = 0; cnt < grst_del; cnt++) {
1241                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1242                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1243                         break;
1244                 msleep(100);
1245         }
1246         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1247                 hw_dbg(hw, "Global reset polling failed to complete.\n");
1248                 return I40E_ERR_RESET_FAILED;
1249         }
1250
1251         /* Now Wait for the FW to be ready */
1252         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1253                 reg = rd32(hw, I40E_GLNVM_ULD);
1254                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1255                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1256                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1257                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1258                         hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
1259                         break;
1260                 }
1261                 usleep_range(10000, 20000);
1262         }
1263         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1264                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1265                 hw_dbg(hw, "wait for FW Reset complete timedout\n");
1266                 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
1267                 return I40E_ERR_RESET_FAILED;
1268         }
1269
1270         /* If there was a Global Reset in progress when we got here,
1271          * we don't need to do the PF Reset
1272          */
1273         if (!cnt) {
1274                 u32 reg2 = 0;
1275                 if (hw->revision_id == 0)
1276                         cnt = I40E_PF_RESET_WAIT_COUNT_A0;
1277                 else
1278                         cnt = I40E_PF_RESET_WAIT_COUNT;
1279                 reg = rd32(hw, I40E_PFGEN_CTRL);
1280                 wr32(hw, I40E_PFGEN_CTRL,
1281                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1282                 for (; cnt; cnt--) {
1283                         reg = rd32(hw, I40E_PFGEN_CTRL);
1284                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1285                                 break;
1286                         reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1287                         if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
1288                                 break;
1289                         usleep_range(1000, 2000);
1290                 }
1291                 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1292                         if (i40e_poll_globr(hw, grst_del))
1293                                 return I40E_ERR_RESET_FAILED;
1294                 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1295                         hw_dbg(hw, "PF reset polling failed to complete.\n");
1296                         return I40E_ERR_RESET_FAILED;
1297                 }
1298         }
1299
1300         i40e_clear_pxe_mode(hw);
1301
1302         return 0;
1303 }
1304
1305 /**
1306  * i40e_clear_hw - clear out any left over hw state
1307  * @hw: pointer to the hw struct
1308  *
1309  * Clear queues and interrupts, typically called at init time,
1310  * but after the capabilities have been found so we know how many
1311  * queues and msix vectors have been allocated.
1312  **/
1313 void i40e_clear_hw(struct i40e_hw *hw)
1314 {
1315         u32 num_queues, base_queue;
1316         u32 num_pf_int;
1317         u32 num_vf_int;
1318         u32 num_vfs;
1319         u32 i, j;
1320         u32 val;
1321         u32 eol = 0x7ff;
1322
1323         /* get number of interrupts, queues, and VFs */
1324         val = rd32(hw, I40E_GLPCI_CNF2);
1325         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1326                      I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1327         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1328                      I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1329
1330         val = rd32(hw, I40E_PFLAN_QALLOC);
1331         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1332                      I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1333         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1334             I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1335         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1336                 num_queues = (j - base_queue) + 1;
1337         else
1338                 num_queues = 0;
1339
1340         val = rd32(hw, I40E_PF_VT_PFALLOC);
1341         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1342             I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1343         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1344             I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1345         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1346                 num_vfs = (j - i) + 1;
1347         else
1348                 num_vfs = 0;
1349
1350         /* stop all the interrupts */
1351         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1352         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1353         for (i = 0; i < num_pf_int - 2; i++)
1354                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1355
1356         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1357         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1358         wr32(hw, I40E_PFINT_LNKLST0, val);
1359         for (i = 0; i < num_pf_int - 2; i++)
1360                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1361         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1362         for (i = 0; i < num_vfs; i++)
1363                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1364         for (i = 0; i < num_vf_int - 2; i++)
1365                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1366
1367         /* warn the HW of the coming Tx disables */
1368         for (i = 0; i < num_queues; i++) {
1369                 u32 abs_queue_idx = base_queue + i;
1370                 u32 reg_block = 0;
1371
1372                 if (abs_queue_idx >= 128) {
1373                         reg_block = abs_queue_idx / 128;
1374                         abs_queue_idx %= 128;
1375                 }
1376
1377                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1378                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1379                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1380                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1381
1382                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1383         }
1384         udelay(400);
1385
1386         /* stop all the queues */
1387         for (i = 0; i < num_queues; i++) {
1388                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1389                 wr32(hw, I40E_QTX_ENA(i), 0);
1390                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1391                 wr32(hw, I40E_QRX_ENA(i), 0);
1392         }
1393
1394         /* short wait for all queue disables to settle */
1395         udelay(50);
1396 }
1397
1398 /**
1399  * i40e_clear_pxe_mode - clear pxe operations mode
1400  * @hw: pointer to the hw struct
1401  *
1402  * Make sure all PXE mode settings are cleared, including things
1403  * like descriptor fetch/write-back mode.
1404  **/
1405 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1406 {
1407         u32 reg;
1408
1409         if (i40e_check_asq_alive(hw))
1410                 i40e_aq_clear_pxe_mode(hw, NULL);
1411
1412         /* Clear single descriptor fetch/write-back mode */
1413         reg = rd32(hw, I40E_GLLAN_RCTL_0);
1414
1415         if (hw->revision_id == 0) {
1416                 /* As a work around clear PXE_MODE instead of setting it */
1417                 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1418         } else {
1419                 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1420         }
1421 }
1422
1423 /**
1424  * i40e_led_is_mine - helper to find matching led
1425  * @hw: pointer to the hw struct
1426  * @idx: index into GPIO registers
1427  *
1428  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1429  */
1430 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1431 {
1432         u32 gpio_val = 0;
1433         u32 port;
1434
1435         if (!hw->func_caps.led[idx])
1436                 return 0;
1437
1438         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1439         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1440                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1441
1442         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1443          * if it is not our port then ignore
1444          */
1445         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1446             (port != hw->port))
1447                 return 0;
1448
1449         return gpio_val;
1450 }
1451
1452 #define I40E_COMBINED_ACTIVITY 0xA
1453 #define I40E_FILTER_ACTIVITY 0xE
1454 #define I40E_LINK_ACTIVITY 0xC
1455 #define I40E_MAC_ACTIVITY 0xD
1456 #define I40E_LED0 22
1457
1458 /**
1459  * i40e_led_get - return current on/off mode
1460  * @hw: pointer to the hw struct
1461  *
1462  * The value returned is the 'mode' field as defined in the
1463  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1464  * values are variations of possible behaviors relating to
1465  * blink, link, and wire.
1466  **/
1467 u32 i40e_led_get(struct i40e_hw *hw)
1468 {
1469         u32 current_mode = 0;
1470         u32 mode = 0;
1471         int i;
1472
1473         /* as per the documentation GPIO 22-29 are the LED
1474          * GPIO pins named LED0..LED7
1475          */
1476         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1477                 u32 gpio_val = i40e_led_is_mine(hw, i);
1478
1479                 if (!gpio_val)
1480                         continue;
1481
1482                 /* ignore gpio LED src mode entries related to the activity
1483                  * LEDs
1484                  */
1485                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1486                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1487                 switch (current_mode) {
1488                 case I40E_COMBINED_ACTIVITY:
1489                 case I40E_FILTER_ACTIVITY:
1490                 case I40E_MAC_ACTIVITY:
1491                 case I40E_LINK_ACTIVITY:
1492                         continue;
1493                 default:
1494                         break;
1495                 }
1496
1497                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1498                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1499                 break;
1500         }
1501
1502         return mode;
1503 }
1504
1505 /**
1506  * i40e_led_set - set new on/off mode
1507  * @hw: pointer to the hw struct
1508  * @mode: 0=off, 0xf=on (else see manual for mode details)
1509  * @blink: true if the LED should blink when on, false if steady
1510  *
1511  * if this function is used to turn on the blink it should
1512  * be used to disable the blink when restoring the original state.
1513  **/
1514 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1515 {
1516         u32 current_mode = 0;
1517         int i;
1518
1519         if (mode & 0xfffffff0)
1520                 hw_dbg(hw, "invalid mode passed in %X\n", mode);
1521
1522         /* as per the documentation GPIO 22-29 are the LED
1523          * GPIO pins named LED0..LED7
1524          */
1525         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1526                 u32 gpio_val = i40e_led_is_mine(hw, i);
1527
1528                 if (!gpio_val)
1529                         continue;
1530
1531                 /* ignore gpio LED src mode entries related to the activity
1532                  * LEDs
1533                  */
1534                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1535                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1536                 switch (current_mode) {
1537                 case I40E_COMBINED_ACTIVITY:
1538                 case I40E_FILTER_ACTIVITY:
1539                 case I40E_MAC_ACTIVITY:
1540                 case I40E_LINK_ACTIVITY:
1541                         continue;
1542                 default:
1543                         break;
1544                 }
1545
1546                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1547                 /* this & is a bit of paranoia, but serves as a range check */
1548                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1549                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1550
1551                 if (blink)
1552                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1553                 else
1554                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1555
1556                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1557                 break;
1558         }
1559 }
1560
1561 /* Admin command wrappers */
1562
1563 /**
1564  * i40e_aq_get_phy_capabilities
1565  * @hw: pointer to the hw struct
1566  * @abilities: structure for PHY capabilities to be filled
1567  * @qualified_modules: report Qualified Modules
1568  * @report_init: report init capabilities (active are default)
1569  * @cmd_details: pointer to command details structure or NULL
1570  *
1571  * Returns the various PHY abilities supported on the Port.
1572  **/
1573 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1574                         bool qualified_modules, bool report_init,
1575                         struct i40e_aq_get_phy_abilities_resp *abilities,
1576                         struct i40e_asq_cmd_details *cmd_details)
1577 {
1578         struct i40e_aq_desc desc;
1579         i40e_status status;
1580         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1581         u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1582
1583         if (!abilities)
1584                 return I40E_ERR_PARAM;
1585
1586         do {
1587                 i40e_fill_default_direct_cmd_desc(&desc,
1588                                                i40e_aqc_opc_get_phy_abilities);
1589
1590                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1591                 if (abilities_size > I40E_AQ_LARGE_BUF)
1592                         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1593
1594                 if (qualified_modules)
1595                         desc.params.external.param0 |=
1596                         cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1597
1598                 if (report_init)
1599                         desc.params.external.param0 |=
1600                         cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1601
1602                 status = i40e_asq_send_command(hw, &desc, abilities,
1603                                                abilities_size, cmd_details);
1604
1605                 if (status)
1606                         break;
1607
1608                 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) {
1609                         status = I40E_ERR_UNKNOWN_PHY;
1610                         break;
1611                 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) {
1612                         usleep_range(1000, 2000);
1613                         total_delay++;
1614                         status = I40E_ERR_TIMEOUT;
1615                 }
1616         } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) &&
1617                  (total_delay < max_delay));
1618
1619         if (status)
1620                 return status;
1621
1622         if (report_init) {
1623                 if (hw->mac.type ==  I40E_MAC_XL710 &&
1624                     hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1625                     hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1626                         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1627                 } else {
1628                         hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
1629                         hw->phy.phy_types |=
1630                                         ((u64)abilities->phy_type_ext << 32);
1631                 }
1632         }
1633
1634         return status;
1635 }
1636
1637 /**
1638  * i40e_aq_set_phy_config
1639  * @hw: pointer to the hw struct
1640  * @config: structure with PHY configuration to be set
1641  * @cmd_details: pointer to command details structure or NULL
1642  *
1643  * Set the various PHY configuration parameters
1644  * supported on the Port.One or more of the Set PHY config parameters may be
1645  * ignored in an MFP mode as the PF may not have the privilege to set some
1646  * of the PHY Config parameters. This status will be indicated by the
1647  * command response.
1648  **/
1649 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1650                                 struct i40e_aq_set_phy_config *config,
1651                                 struct i40e_asq_cmd_details *cmd_details)
1652 {
1653         struct i40e_aq_desc desc;
1654         struct i40e_aq_set_phy_config *cmd =
1655                         (struct i40e_aq_set_phy_config *)&desc.params.raw;
1656         enum i40e_status_code status;
1657
1658         if (!config)
1659                 return I40E_ERR_PARAM;
1660
1661         i40e_fill_default_direct_cmd_desc(&desc,
1662                                           i40e_aqc_opc_set_phy_config);
1663
1664         *cmd = *config;
1665
1666         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1667
1668         return status;
1669 }
1670
1671 /**
1672  * i40e_set_fc
1673  * @hw: pointer to the hw struct
1674  * @aq_failures: buffer to return AdminQ failure information
1675  * @atomic_restart: whether to enable atomic link restart
1676  *
1677  * Set the requested flow control mode using set_phy_config.
1678  **/
1679 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1680                                   bool atomic_restart)
1681 {
1682         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1683         struct i40e_aq_get_phy_abilities_resp abilities;
1684         struct i40e_aq_set_phy_config config;
1685         enum i40e_status_code status;
1686         u8 pause_mask = 0x0;
1687
1688         *aq_failures = 0x0;
1689
1690         switch (fc_mode) {
1691         case I40E_FC_FULL:
1692                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1693                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1694                 break;
1695         case I40E_FC_RX_PAUSE:
1696                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1697                 break;
1698         case I40E_FC_TX_PAUSE:
1699                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1700                 break;
1701         default:
1702                 break;
1703         }
1704
1705         /* Get the current phy config */
1706         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1707                                               NULL);
1708         if (status) {
1709                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1710                 return status;
1711         }
1712
1713         memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1714         /* clear the old pause settings */
1715         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1716                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1717         /* set the new abilities */
1718         config.abilities |= pause_mask;
1719         /* If the abilities have changed, then set the new config */
1720         if (config.abilities != abilities.abilities) {
1721                 /* Auto restart link so settings take effect */
1722                 if (atomic_restart)
1723                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1724                 /* Copy over all the old settings */
1725                 config.phy_type = abilities.phy_type;
1726                 config.phy_type_ext = abilities.phy_type_ext;
1727                 config.link_speed = abilities.link_speed;
1728                 config.eee_capability = abilities.eee_capability;
1729                 config.eeer = abilities.eeer_val;
1730                 config.low_power_ctrl = abilities.d3_lpan;
1731                 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1732                                     I40E_AQ_PHY_FEC_CONFIG_MASK;
1733                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1734
1735                 if (status)
1736                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1737         }
1738         /* Update the link info */
1739         status = i40e_update_link_info(hw);
1740         if (status) {
1741                 /* Wait a little bit (on 40G cards it sometimes takes a really
1742                  * long time for link to come back from the atomic reset)
1743                  * and try once more
1744                  */
1745                 msleep(1000);
1746                 status = i40e_update_link_info(hw);
1747         }
1748         if (status)
1749                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1750
1751         return status;
1752 }
1753
1754 /**
1755  * i40e_aq_clear_pxe_mode
1756  * @hw: pointer to the hw struct
1757  * @cmd_details: pointer to command details structure or NULL
1758  *
1759  * Tell the firmware that the driver is taking over from PXE
1760  **/
1761 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1762                                 struct i40e_asq_cmd_details *cmd_details)
1763 {
1764         i40e_status status;
1765         struct i40e_aq_desc desc;
1766         struct i40e_aqc_clear_pxe *cmd =
1767                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1768
1769         i40e_fill_default_direct_cmd_desc(&desc,
1770                                           i40e_aqc_opc_clear_pxe_mode);
1771
1772         cmd->rx_cnt = 0x2;
1773
1774         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1775
1776         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1777
1778         return status;
1779 }
1780
1781 /**
1782  * i40e_aq_set_link_restart_an
1783  * @hw: pointer to the hw struct
1784  * @enable_link: if true: enable link, if false: disable link
1785  * @cmd_details: pointer to command details structure or NULL
1786  *
1787  * Sets up the link and restarts the Auto-Negotiation over the link.
1788  **/
1789 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1790                                         bool enable_link,
1791                                         struct i40e_asq_cmd_details *cmd_details)
1792 {
1793         struct i40e_aq_desc desc;
1794         struct i40e_aqc_set_link_restart_an *cmd =
1795                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1796         i40e_status status;
1797
1798         i40e_fill_default_direct_cmd_desc(&desc,
1799                                           i40e_aqc_opc_set_link_restart_an);
1800
1801         cmd->command = I40E_AQ_PHY_RESTART_AN;
1802         if (enable_link)
1803                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1804         else
1805                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1806
1807         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1808
1809         return status;
1810 }
1811
1812 /**
1813  * i40e_aq_get_link_info
1814  * @hw: pointer to the hw struct
1815  * @enable_lse: enable/disable LinkStatusEvent reporting
1816  * @link: pointer to link status structure - optional
1817  * @cmd_details: pointer to command details structure or NULL
1818  *
1819  * Returns the link status of the adapter.
1820  **/
1821 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1822                                 bool enable_lse, struct i40e_link_status *link,
1823                                 struct i40e_asq_cmd_details *cmd_details)
1824 {
1825         struct i40e_aq_desc desc;
1826         struct i40e_aqc_get_link_status *resp =
1827                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1828         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1829         i40e_status status;
1830         bool tx_pause, rx_pause;
1831         u16 command_flags;
1832
1833         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1834
1835         if (enable_lse)
1836                 command_flags = I40E_AQ_LSE_ENABLE;
1837         else
1838                 command_flags = I40E_AQ_LSE_DISABLE;
1839         resp->command_flags = cpu_to_le16(command_flags);
1840
1841         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1842
1843         if (status)
1844                 goto aq_get_link_info_exit;
1845
1846         /* save off old link status information */
1847         hw->phy.link_info_old = *hw_link_info;
1848
1849         /* update link status */
1850         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1851         hw->phy.media_type = i40e_get_media_type(hw);
1852         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1853         hw_link_info->link_info = resp->link_info;
1854         hw_link_info->an_info = resp->an_info;
1855         hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1856                                                  I40E_AQ_CONFIG_FEC_RS_ENA);
1857         hw_link_info->ext_info = resp->ext_info;
1858         hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
1859         hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1860         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1861
1862         /* update fc info */
1863         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1864         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1865         if (tx_pause & rx_pause)
1866                 hw->fc.current_mode = I40E_FC_FULL;
1867         else if (tx_pause)
1868                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1869         else if (rx_pause)
1870                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1871         else
1872                 hw->fc.current_mode = I40E_FC_NONE;
1873
1874         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1875                 hw_link_info->crc_enable = true;
1876         else
1877                 hw_link_info->crc_enable = false;
1878
1879         if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_IS_ENABLED))
1880                 hw_link_info->lse_enable = true;
1881         else
1882                 hw_link_info->lse_enable = false;
1883
1884         if ((hw->mac.type == I40E_MAC_XL710) &&
1885             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1886              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1887                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1888
1889         if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1890             hw->aq.api_min_ver >= 7) {
1891                 __le32 tmp;
1892
1893                 memcpy(&tmp, resp->link_type, sizeof(tmp));
1894                 hw->phy.phy_types = le32_to_cpu(tmp);
1895                 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
1896         }
1897
1898         /* save link status information */
1899         if (link)
1900                 *link = *hw_link_info;
1901
1902         /* flag cleared so helper functions don't call AQ again */
1903         hw->phy.get_link_info = false;
1904
1905 aq_get_link_info_exit:
1906         return status;
1907 }
1908
1909 /**
1910  * i40e_aq_set_phy_int_mask
1911  * @hw: pointer to the hw struct
1912  * @mask: interrupt mask to be set
1913  * @cmd_details: pointer to command details structure or NULL
1914  *
1915  * Set link interrupt mask.
1916  **/
1917 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1918                                      u16 mask,
1919                                      struct i40e_asq_cmd_details *cmd_details)
1920 {
1921         struct i40e_aq_desc desc;
1922         struct i40e_aqc_set_phy_int_mask *cmd =
1923                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1924         i40e_status status;
1925
1926         i40e_fill_default_direct_cmd_desc(&desc,
1927                                           i40e_aqc_opc_set_phy_int_mask);
1928
1929         cmd->event_mask = cpu_to_le16(mask);
1930
1931         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1932
1933         return status;
1934 }
1935
1936 /**
1937  * i40e_aq_set_phy_debug
1938  * @hw: pointer to the hw struct
1939  * @cmd_flags: debug command flags
1940  * @cmd_details: pointer to command details structure or NULL
1941  *
1942  * Reset the external PHY.
1943  **/
1944 i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1945                                   struct i40e_asq_cmd_details *cmd_details)
1946 {
1947         struct i40e_aq_desc desc;
1948         struct i40e_aqc_set_phy_debug *cmd =
1949                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1950         i40e_status status;
1951
1952         i40e_fill_default_direct_cmd_desc(&desc,
1953                                           i40e_aqc_opc_set_phy_debug);
1954
1955         cmd->command_flags = cmd_flags;
1956
1957         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1958
1959         return status;
1960 }
1961
1962 /**
1963  * i40e_aq_add_vsi
1964  * @hw: pointer to the hw struct
1965  * @vsi_ctx: pointer to a vsi context struct
1966  * @cmd_details: pointer to command details structure or NULL
1967  *
1968  * Add a VSI context to the hardware.
1969 **/
1970 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1971                                 struct i40e_vsi_context *vsi_ctx,
1972                                 struct i40e_asq_cmd_details *cmd_details)
1973 {
1974         struct i40e_aq_desc desc;
1975         struct i40e_aqc_add_get_update_vsi *cmd =
1976                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1977         struct i40e_aqc_add_get_update_vsi_completion *resp =
1978                 (struct i40e_aqc_add_get_update_vsi_completion *)
1979                 &desc.params.raw;
1980         i40e_status status;
1981
1982         i40e_fill_default_direct_cmd_desc(&desc,
1983                                           i40e_aqc_opc_add_vsi);
1984
1985         cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1986         cmd->connection_type = vsi_ctx->connection_type;
1987         cmd->vf_id = vsi_ctx->vf_num;
1988         cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1989
1990         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1991
1992         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1993                                     sizeof(vsi_ctx->info), cmd_details);
1994
1995         if (status)
1996                 goto aq_add_vsi_exit;
1997
1998         vsi_ctx->seid = le16_to_cpu(resp->seid);
1999         vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2000         vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2001         vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2002
2003 aq_add_vsi_exit:
2004         return status;
2005 }
2006
2007 /**
2008  * i40e_aq_set_default_vsi
2009  * @hw: pointer to the hw struct
2010  * @seid: vsi number
2011  * @cmd_details: pointer to command details structure or NULL
2012  **/
2013 i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw,
2014                                     u16 seid,
2015                                     struct i40e_asq_cmd_details *cmd_details)
2016 {
2017         struct i40e_aq_desc desc;
2018         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2019                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2020                 &desc.params.raw;
2021         i40e_status status;
2022
2023         i40e_fill_default_direct_cmd_desc(&desc,
2024                                           i40e_aqc_opc_set_vsi_promiscuous_modes);
2025
2026         cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
2027         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
2028         cmd->seid = cpu_to_le16(seid);
2029
2030         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2031
2032         return status;
2033 }
2034
2035 /**
2036  * i40e_aq_clear_default_vsi
2037  * @hw: pointer to the hw struct
2038  * @seid: vsi number
2039  * @cmd_details: pointer to command details structure or NULL
2040  **/
2041 i40e_status i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2042                                       u16 seid,
2043                                       struct i40e_asq_cmd_details *cmd_details)
2044 {
2045         struct i40e_aq_desc desc;
2046         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2047                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2048                 &desc.params.raw;
2049         i40e_status status;
2050
2051         i40e_fill_default_direct_cmd_desc(&desc,
2052                                           i40e_aqc_opc_set_vsi_promiscuous_modes);
2053
2054         cmd->promiscuous_flags = cpu_to_le16(0);
2055         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
2056         cmd->seid = cpu_to_le16(seid);
2057
2058         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2059
2060         return status;
2061 }
2062
2063 /**
2064  * i40e_aq_set_vsi_unicast_promiscuous
2065  * @hw: pointer to the hw struct
2066  * @seid: vsi number
2067  * @set: set unicast promiscuous enable/disable
2068  * @cmd_details: pointer to command details structure or NULL
2069  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2070  **/
2071 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2072                                 u16 seid, bool set,
2073                                 struct i40e_asq_cmd_details *cmd_details,
2074                                 bool rx_only_promisc)
2075 {
2076         struct i40e_aq_desc desc;
2077         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2078                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2079         i40e_status status;
2080         u16 flags = 0;
2081
2082         i40e_fill_default_direct_cmd_desc(&desc,
2083                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2084
2085         if (set) {
2086                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2087                 if (rx_only_promisc &&
2088                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2089                      (hw->aq.api_maj_ver > 1)))
2090                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2091         }
2092
2093         cmd->promiscuous_flags = cpu_to_le16(flags);
2094
2095         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2096         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2097             (hw->aq.api_maj_ver > 1))
2098                 cmd->valid_flags |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_TX);
2099
2100         cmd->seid = cpu_to_le16(seid);
2101         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2102
2103         return status;
2104 }
2105
2106 /**
2107  * i40e_aq_set_vsi_multicast_promiscuous
2108  * @hw: pointer to the hw struct
2109  * @seid: vsi number
2110  * @set: set multicast promiscuous enable/disable
2111  * @cmd_details: pointer to command details structure or NULL
2112  **/
2113 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2114                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2115 {
2116         struct i40e_aq_desc desc;
2117         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2118                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2119         i40e_status status;
2120         u16 flags = 0;
2121
2122         i40e_fill_default_direct_cmd_desc(&desc,
2123                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2124
2125         if (set)
2126                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2127
2128         cmd->promiscuous_flags = cpu_to_le16(flags);
2129
2130         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2131
2132         cmd->seid = cpu_to_le16(seid);
2133         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2134
2135         return status;
2136 }
2137
2138 /**
2139  * i40e_aq_set_vsi_mc_promisc_on_vlan
2140  * @hw: pointer to the hw struct
2141  * @seid: vsi number
2142  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2143  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2144  * @cmd_details: pointer to command details structure or NULL
2145  **/
2146 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2147                                                          u16 seid, bool enable,
2148                                                          u16 vid,
2149                                 struct i40e_asq_cmd_details *cmd_details)
2150 {
2151         struct i40e_aq_desc desc;
2152         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2153                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2154         enum i40e_status_code status;
2155         u16 flags = 0;
2156
2157         i40e_fill_default_direct_cmd_desc(&desc,
2158                                           i40e_aqc_opc_set_vsi_promiscuous_modes);
2159
2160         if (enable)
2161                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2162
2163         cmd->promiscuous_flags = cpu_to_le16(flags);
2164         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2165         cmd->seid = cpu_to_le16(seid);
2166         cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2167
2168         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2169
2170         return status;
2171 }
2172
2173 /**
2174  * i40e_aq_set_vsi_uc_promisc_on_vlan
2175  * @hw: pointer to the hw struct
2176  * @seid: vsi number
2177  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2178  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2179  * @cmd_details: pointer to command details structure or NULL
2180  **/
2181 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2182                                                          u16 seid, bool enable,
2183                                                          u16 vid,
2184                                 struct i40e_asq_cmd_details *cmd_details)
2185 {
2186         struct i40e_aq_desc desc;
2187         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2188                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2189         enum i40e_status_code status;
2190         u16 flags = 0;
2191
2192         i40e_fill_default_direct_cmd_desc(&desc,
2193                                           i40e_aqc_opc_set_vsi_promiscuous_modes);
2194
2195         if (enable)
2196                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2197
2198         cmd->promiscuous_flags = cpu_to_le16(flags);
2199         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2200         cmd->seid = cpu_to_le16(seid);
2201         cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2202
2203         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2204
2205         return status;
2206 }
2207
2208 /**
2209  * i40e_aq_set_vsi_bc_promisc_on_vlan
2210  * @hw: pointer to the hw struct
2211  * @seid: vsi number
2212  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2213  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2214  * @cmd_details: pointer to command details structure or NULL
2215  **/
2216 i40e_status i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2217                                 u16 seid, bool enable, u16 vid,
2218                                 struct i40e_asq_cmd_details *cmd_details)
2219 {
2220         struct i40e_aq_desc desc;
2221         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2222                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2223         i40e_status status;
2224         u16 flags = 0;
2225
2226         i40e_fill_default_direct_cmd_desc(&desc,
2227                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2228
2229         if (enable)
2230                 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2231
2232         cmd->promiscuous_flags = cpu_to_le16(flags);
2233         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2234         cmd->seid = cpu_to_le16(seid);
2235         cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2236
2237         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2238
2239         return status;
2240 }
2241
2242 /**
2243  * i40e_aq_set_vsi_broadcast
2244  * @hw: pointer to the hw struct
2245  * @seid: vsi number
2246  * @set_filter: true to set filter, false to clear filter
2247  * @cmd_details: pointer to command details structure or NULL
2248  *
2249  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2250  **/
2251 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2252                                 u16 seid, bool set_filter,
2253                                 struct i40e_asq_cmd_details *cmd_details)
2254 {
2255         struct i40e_aq_desc desc;
2256         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2257                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2258         i40e_status status;
2259
2260         i40e_fill_default_direct_cmd_desc(&desc,
2261                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2262
2263         if (set_filter)
2264                 cmd->promiscuous_flags
2265                             |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2266         else
2267                 cmd->promiscuous_flags
2268                             &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2269
2270         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2271         cmd->seid = cpu_to_le16(seid);
2272         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2273
2274         return status;
2275 }
2276
2277 /**
2278  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2279  * @hw: pointer to the hw struct
2280  * @seid: vsi number
2281  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2282  * @cmd_details: pointer to command details structure or NULL
2283  **/
2284 i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2285                                        u16 seid, bool enable,
2286                                        struct i40e_asq_cmd_details *cmd_details)
2287 {
2288         struct i40e_aq_desc desc;
2289         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2290                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2291         i40e_status status;
2292         u16 flags = 0;
2293
2294         i40e_fill_default_direct_cmd_desc(&desc,
2295                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2296         if (enable)
2297                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2298
2299         cmd->promiscuous_flags = cpu_to_le16(flags);
2300         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2301         cmd->seid = cpu_to_le16(seid);
2302
2303         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2304
2305         return status;
2306 }
2307
2308 /**
2309  * i40e_get_vsi_params - get VSI configuration info
2310  * @hw: pointer to the hw struct
2311  * @vsi_ctx: pointer to a vsi context struct
2312  * @cmd_details: pointer to command details structure or NULL
2313  **/
2314 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
2315                                 struct i40e_vsi_context *vsi_ctx,
2316                                 struct i40e_asq_cmd_details *cmd_details)
2317 {
2318         struct i40e_aq_desc desc;
2319         struct i40e_aqc_add_get_update_vsi *cmd =
2320                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2321         struct i40e_aqc_add_get_update_vsi_completion *resp =
2322                 (struct i40e_aqc_add_get_update_vsi_completion *)
2323                 &desc.params.raw;
2324         i40e_status status;
2325
2326         i40e_fill_default_direct_cmd_desc(&desc,
2327                                           i40e_aqc_opc_get_vsi_parameters);
2328
2329         cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2330
2331         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2332
2333         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2334                                     sizeof(vsi_ctx->info), NULL);
2335
2336         if (status)
2337                 goto aq_get_vsi_params_exit;
2338
2339         vsi_ctx->seid = le16_to_cpu(resp->seid);
2340         vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2341         vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2342         vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2343
2344 aq_get_vsi_params_exit:
2345         return status;
2346 }
2347
2348 /**
2349  * i40e_aq_update_vsi_params
2350  * @hw: pointer to the hw struct
2351  * @vsi_ctx: pointer to a vsi context struct
2352  * @cmd_details: pointer to command details structure or NULL
2353  *
2354  * Update a VSI context.
2355  **/
2356 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
2357                                 struct i40e_vsi_context *vsi_ctx,
2358                                 struct i40e_asq_cmd_details *cmd_details)
2359 {
2360         struct i40e_aq_desc desc;
2361         struct i40e_aqc_add_get_update_vsi *cmd =
2362                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2363         struct i40e_aqc_add_get_update_vsi_completion *resp =
2364                 (struct i40e_aqc_add_get_update_vsi_completion *)
2365                 &desc.params.raw;
2366         i40e_status status;
2367
2368         i40e_fill_default_direct_cmd_desc(&desc,
2369                                           i40e_aqc_opc_update_vsi_parameters);
2370         cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2371
2372         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2373
2374         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2375                                     sizeof(vsi_ctx->info), cmd_details);
2376
2377         vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2378         vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2379
2380         return status;
2381 }
2382
2383 /**
2384  * i40e_aq_get_switch_config
2385  * @hw: pointer to the hardware structure
2386  * @buf: pointer to the result buffer
2387  * @buf_size: length of input buffer
2388  * @start_seid: seid to start for the report, 0 == beginning
2389  * @cmd_details: pointer to command details structure or NULL
2390  *
2391  * Fill the buf with switch configuration returned from AdminQ command
2392  **/
2393 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
2394                                 struct i40e_aqc_get_switch_config_resp *buf,
2395                                 u16 buf_size, u16 *start_seid,
2396                                 struct i40e_asq_cmd_details *cmd_details)
2397 {
2398         struct i40e_aq_desc desc;
2399         struct i40e_aqc_switch_seid *scfg =
2400                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2401         i40e_status status;
2402
2403         i40e_fill_default_direct_cmd_desc(&desc,
2404                                           i40e_aqc_opc_get_switch_config);
2405         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2406         if (buf_size > I40E_AQ_LARGE_BUF)
2407                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2408         scfg->seid = cpu_to_le16(*start_seid);
2409
2410         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2411         *start_seid = le16_to_cpu(scfg->seid);
2412
2413         return status;
2414 }
2415
2416 /**
2417  * i40e_aq_set_switch_config
2418  * @hw: pointer to the hardware structure
2419  * @flags: bit flag values to set
2420  * @mode: cloud filter mode
2421  * @valid_flags: which bit flags to set
2422  * @mode: cloud filter mode
2423  * @cmd_details: pointer to command details structure or NULL
2424  *
2425  * Set switch configuration bits
2426  **/
2427 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2428                                                 u16 flags,
2429                                                 u16 valid_flags, u8 mode,
2430                                 struct i40e_asq_cmd_details *cmd_details)
2431 {
2432         struct i40e_aq_desc desc;
2433         struct i40e_aqc_set_switch_config *scfg =
2434                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2435         enum i40e_status_code status;
2436
2437         i40e_fill_default_direct_cmd_desc(&desc,
2438                                           i40e_aqc_opc_set_switch_config);
2439         scfg->flags = cpu_to_le16(flags);
2440         scfg->valid_flags = cpu_to_le16(valid_flags);
2441         scfg->mode = mode;
2442         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2443                 scfg->switch_tag = cpu_to_le16(hw->switch_tag);
2444                 scfg->first_tag = cpu_to_le16(hw->first_tag);
2445                 scfg->second_tag = cpu_to_le16(hw->second_tag);
2446         }
2447         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2448
2449         return status;
2450 }
2451
2452 /**
2453  * i40e_aq_get_firmware_version
2454  * @hw: pointer to the hw struct
2455  * @fw_major_version: firmware major version
2456  * @fw_minor_version: firmware minor version
2457  * @fw_build: firmware build number
2458  * @api_major_version: major queue version
2459  * @api_minor_version: minor queue version
2460  * @cmd_details: pointer to command details structure or NULL
2461  *
2462  * Get the firmware version from the admin queue commands
2463  **/
2464 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
2465                                 u16 *fw_major_version, u16 *fw_minor_version,
2466                                 u32 *fw_build,
2467                                 u16 *api_major_version, u16 *api_minor_version,
2468                                 struct i40e_asq_cmd_details *cmd_details)
2469 {
2470         struct i40e_aq_desc desc;
2471         struct i40e_aqc_get_version *resp =
2472                 (struct i40e_aqc_get_version *)&desc.params.raw;
2473         i40e_status status;
2474
2475         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2476
2477         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2478
2479         if (!status) {
2480                 if (fw_major_version)
2481                         *fw_major_version = le16_to_cpu(resp->fw_major);
2482                 if (fw_minor_version)
2483                         *fw_minor_version = le16_to_cpu(resp->fw_minor);
2484                 if (fw_build)
2485                         *fw_build = le32_to_cpu(resp->fw_build);
2486                 if (api_major_version)
2487                         *api_major_version = le16_to_cpu(resp->api_major);
2488                 if (api_minor_version)
2489                         *api_minor_version = le16_to_cpu(resp->api_minor);
2490         }
2491
2492         return status;
2493 }
2494
2495 /**
2496  * i40e_aq_send_driver_version
2497  * @hw: pointer to the hw struct
2498  * @dv: driver's major, minor version
2499  * @cmd_details: pointer to command details structure or NULL
2500  *
2501  * Send the driver version to the firmware
2502  **/
2503 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
2504                                 struct i40e_driver_version *dv,
2505                                 struct i40e_asq_cmd_details *cmd_details)
2506 {
2507         struct i40e_aq_desc desc;
2508         struct i40e_aqc_driver_version *cmd =
2509                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2510         i40e_status status;
2511         u16 len;
2512
2513         if (dv == NULL)
2514                 return I40E_ERR_PARAM;
2515
2516         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2517
2518         desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2519         cmd->driver_major_ver = dv->major_version;
2520         cmd->driver_minor_ver = dv->minor_version;
2521         cmd->driver_build_ver = dv->build_version;
2522         cmd->driver_subbuild_ver = dv->subbuild_version;
2523
2524         len = 0;
2525         while (len < sizeof(dv->driver_string) &&
2526                (dv->driver_string[len] < 0x80) &&
2527                dv->driver_string[len])
2528                 len++;
2529         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2530                                        len, cmd_details);
2531
2532         return status;
2533 }
2534
2535 /**
2536  * i40e_get_link_status - get status of the HW network link
2537  * @hw: pointer to the hw struct
2538  * @link_up: pointer to bool (true/false = linkup/linkdown)
2539  *
2540  * Variable link_up true if link is up, false if link is down.
2541  * The variable link_up is invalid if returned value of status != 0
2542  *
2543  * Side effect: LinkStatusEvent reporting becomes enabled
2544  **/
2545 i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2546 {
2547         i40e_status status = 0;
2548
2549         if (hw->phy.get_link_info) {
2550                 status = i40e_update_link_info(hw);
2551
2552                 if (status)
2553                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2554                                    status);
2555         }
2556
2557         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2558
2559         return status;
2560 }
2561
2562 /**
2563  * i40e_updatelink_status - update status of the HW network link
2564  * @hw: pointer to the hw struct
2565  **/
2566 i40e_status i40e_update_link_info(struct i40e_hw *hw)
2567 {
2568         struct i40e_aq_get_phy_abilities_resp abilities;
2569         i40e_status status = 0;
2570
2571         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2572         if (status)
2573                 return status;
2574
2575         /* extra checking needed to ensure link info to user is timely */
2576         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2577             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2578              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2579                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2580                                                       &abilities, NULL);
2581                 if (status)
2582                         return status;
2583
2584                 hw->phy.link_info.req_fec_info =
2585                         abilities.fec_cfg_curr_mod_ext_info &
2586                         (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2587
2588                 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2589                        sizeof(hw->phy.link_info.module_type));
2590         }
2591
2592         return status;
2593 }
2594
2595 /**
2596  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2597  * @hw: pointer to the hw struct
2598  * @uplink_seid: the MAC or other gizmo SEID
2599  * @downlink_seid: the VSI SEID
2600  * @enabled_tc: bitmap of TCs to be enabled
2601  * @default_port: true for default port VSI, false for control port
2602  * @veb_seid: pointer to where to put the resulting VEB SEID
2603  * @enable_stats: true to turn on VEB stats
2604  * @cmd_details: pointer to command details structure or NULL
2605  *
2606  * This asks the FW to add a VEB between the uplink and downlink
2607  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2608  **/
2609 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2610                                 u16 downlink_seid, u8 enabled_tc,
2611                                 bool default_port, u16 *veb_seid,
2612                                 bool enable_stats,
2613                                 struct i40e_asq_cmd_details *cmd_details)
2614 {
2615         struct i40e_aq_desc desc;
2616         struct i40e_aqc_add_veb *cmd =
2617                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2618         struct i40e_aqc_add_veb_completion *resp =
2619                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2620         i40e_status status;
2621         u16 veb_flags = 0;
2622
2623         /* SEIDs need to either both be set or both be 0 for floating VEB */
2624         if (!!uplink_seid != !!downlink_seid)
2625                 return I40E_ERR_PARAM;
2626
2627         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2628
2629         cmd->uplink_seid = cpu_to_le16(uplink_seid);
2630         cmd->downlink_seid = cpu_to_le16(downlink_seid);
2631         cmd->enable_tcs = enabled_tc;
2632         if (!uplink_seid)
2633                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2634         if (default_port)
2635                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2636         else
2637                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2638
2639         /* reverse logic here: set the bitflag to disable the stats */
2640         if (!enable_stats)
2641                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2642
2643         cmd->veb_flags = cpu_to_le16(veb_flags);
2644
2645         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2646
2647         if (!status && veb_seid)
2648                 *veb_seid = le16_to_cpu(resp->veb_seid);
2649
2650         return status;
2651 }
2652
2653 /**
2654  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2655  * @hw: pointer to the hw struct
2656  * @veb_seid: the SEID of the VEB to query
2657  * @switch_id: the uplink switch id
2658  * @floating: set to true if the VEB is floating
2659  * @statistic_index: index of the stats counter block for this VEB
2660  * @vebs_used: number of VEB's used by function
2661  * @vebs_free: total VEB's not reserved by any function
2662  * @cmd_details: pointer to command details structure or NULL
2663  *
2664  * This retrieves the parameters for a particular VEB, specified by
2665  * uplink_seid, and returns them to the caller.
2666  **/
2667 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2668                                 u16 veb_seid, u16 *switch_id,
2669                                 bool *floating, u16 *statistic_index,
2670                                 u16 *vebs_used, u16 *vebs_free,
2671                                 struct i40e_asq_cmd_details *cmd_details)
2672 {
2673         struct i40e_aq_desc desc;
2674         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2675                 (struct i40e_aqc_get_veb_parameters_completion *)
2676                 &desc.params.raw;
2677         i40e_status status;
2678
2679         if (veb_seid == 0)
2680                 return I40E_ERR_PARAM;
2681
2682         i40e_fill_default_direct_cmd_desc(&desc,
2683                                           i40e_aqc_opc_get_veb_parameters);
2684         cmd_resp->seid = cpu_to_le16(veb_seid);
2685
2686         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2687         if (status)
2688                 goto get_veb_exit;
2689
2690         if (switch_id)
2691                 *switch_id = le16_to_cpu(cmd_resp->switch_id);
2692         if (statistic_index)
2693                 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
2694         if (vebs_used)
2695                 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
2696         if (vebs_free)
2697                 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
2698         if (floating) {
2699                 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
2700
2701                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2702                         *floating = true;
2703                 else
2704                         *floating = false;
2705         }
2706
2707 get_veb_exit:
2708         return status;
2709 }
2710
2711 /**
2712  * i40e_aq_add_macvlan
2713  * @hw: pointer to the hw struct
2714  * @seid: VSI for the mac address
2715  * @mv_list: list of macvlans to be added
2716  * @count: length of the list
2717  * @cmd_details: pointer to command details structure or NULL
2718  *
2719  * Add MAC/VLAN addresses to the HW filtering
2720  **/
2721 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2722                         struct i40e_aqc_add_macvlan_element_data *mv_list,
2723                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2724 {
2725         struct i40e_aq_desc desc;
2726         struct i40e_aqc_macvlan *cmd =
2727                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2728         i40e_status status;
2729         u16 buf_size;
2730         int i;
2731
2732         if (count == 0 || !mv_list || !hw)
2733                 return I40E_ERR_PARAM;
2734
2735         buf_size = count * sizeof(*mv_list);
2736
2737         /* prep the rest of the request */
2738         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2739         cmd->num_addresses = cpu_to_le16(count);
2740         cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2741         cmd->seid[1] = 0;
2742         cmd->seid[2] = 0;
2743
2744         for (i = 0; i < count; i++)
2745                 if (is_multicast_ether_addr(mv_list[i].mac_addr))
2746                         mv_list[i].flags |=
2747                                cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2748
2749         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2750         if (buf_size > I40E_AQ_LARGE_BUF)
2751                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2752
2753         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2754                                        cmd_details);
2755
2756         return status;
2757 }
2758
2759 /**
2760  * i40e_aq_remove_macvlan
2761  * @hw: pointer to the hw struct
2762  * @seid: VSI for the mac address
2763  * @mv_list: list of macvlans to be removed
2764  * @count: length of the list
2765  * @cmd_details: pointer to command details structure or NULL
2766  *
2767  * Remove MAC/VLAN addresses from the HW filtering
2768  **/
2769 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2770                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
2771                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2772 {
2773         struct i40e_aq_desc desc;
2774         struct i40e_aqc_macvlan *cmd =
2775                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2776         i40e_status status;
2777         u16 buf_size;
2778
2779         if (count == 0 || !mv_list || !hw)
2780                 return I40E_ERR_PARAM;
2781
2782         buf_size = count * sizeof(*mv_list);
2783
2784         /* prep the rest of the request */
2785         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2786         cmd->num_addresses = cpu_to_le16(count);
2787         cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2788         cmd->seid[1] = 0;
2789         cmd->seid[2] = 0;
2790
2791         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2792         if (buf_size > I40E_AQ_LARGE_BUF)
2793                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2794
2795         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2796                                        cmd_details);
2797
2798         return status;
2799 }
2800
2801 /**
2802  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2803  * @hw: pointer to the hw struct
2804  * @opcode: AQ opcode for add or delete mirror rule
2805  * @sw_seid: Switch SEID (to which rule refers)
2806  * @rule_type: Rule Type (ingress/egress/VLAN)
2807  * @id: Destination VSI SEID or Rule ID
2808  * @count: length of the list
2809  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2810  * @cmd_details: pointer to command details structure or NULL
2811  * @rule_id: Rule ID returned from FW
2812  * @rules_used: Number of rules used in internal switch
2813  * @rules_free: Number of rules free in internal switch
2814  *
2815  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2816  * VEBs/VEPA elements only
2817  **/
2818 static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw,
2819                                 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2820                                 u16 count, __le16 *mr_list,
2821                                 struct i40e_asq_cmd_details *cmd_details,
2822                                 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2823 {
2824         struct i40e_aq_desc desc;
2825         struct i40e_aqc_add_delete_mirror_rule *cmd =
2826                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2827         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2828         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2829         i40e_status status;
2830         u16 buf_size;
2831
2832         buf_size = count * sizeof(*mr_list);
2833
2834         /* prep the rest of the request */
2835         i40e_fill_default_direct_cmd_desc(&desc, opcode);
2836         cmd->seid = cpu_to_le16(sw_seid);
2837         cmd->rule_type = cpu_to_le16(rule_type &
2838                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
2839         cmd->num_entries = cpu_to_le16(count);
2840         /* Dest VSI for add, rule_id for delete */
2841         cmd->destination = cpu_to_le16(id);
2842         if (mr_list) {
2843                 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2844                                                 I40E_AQ_FLAG_RD));
2845                 if (buf_size > I40E_AQ_LARGE_BUF)
2846                         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2847         }
2848
2849         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2850                                        cmd_details);
2851         if (!status ||
2852             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2853                 if (rule_id)
2854                         *rule_id = le16_to_cpu(resp->rule_id);
2855                 if (rules_used)
2856                         *rules_used = le16_to_cpu(resp->mirror_rules_used);
2857                 if (rules_free)
2858                         *rules_free = le16_to_cpu(resp->mirror_rules_free);
2859         }
2860         return status;
2861 }
2862
2863 /**
2864  * i40e_aq_add_mirrorrule - add a mirror rule
2865  * @hw: pointer to the hw struct
2866  * @sw_seid: Switch SEID (to which rule refers)
2867  * @rule_type: Rule Type (ingress/egress/VLAN)
2868  * @dest_vsi: SEID of VSI to which packets will be mirrored
2869  * @count: length of the list
2870  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2871  * @cmd_details: pointer to command details structure or NULL
2872  * @rule_id: Rule ID returned from FW
2873  * @rules_used: Number of rules used in internal switch
2874  * @rules_free: Number of rules free in internal switch
2875  *
2876  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
2877  **/
2878 i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2879                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
2880                         struct i40e_asq_cmd_details *cmd_details,
2881                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
2882 {
2883         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
2884             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
2885                 if (count == 0 || !mr_list)
2886                         return I40E_ERR_PARAM;
2887         }
2888
2889         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
2890                                   rule_type, dest_vsi, count, mr_list,
2891                                   cmd_details, rule_id, rules_used, rules_free);
2892 }
2893
2894 /**
2895  * i40e_aq_delete_mirrorrule - delete a mirror rule
2896  * @hw: pointer to the hw struct
2897  * @sw_seid: Switch SEID (to which rule refers)
2898  * @rule_type: Rule Type (ingress/egress/VLAN)
2899  * @count: length of the list
2900  * @rule_id: Rule ID that is returned in the receive desc as part of
2901  *              add_mirrorrule.
2902  * @mr_list: list of mirrored VLAN IDs to be removed
2903  * @cmd_details: pointer to command details structure or NULL
2904  * @rules_used: Number of rules used in internal switch
2905  * @rules_free: Number of rules free in internal switch
2906  *
2907  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
2908  **/
2909 i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2910                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
2911                         struct i40e_asq_cmd_details *cmd_details,
2912                         u16 *rules_used, u16 *rules_free)
2913 {
2914         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
2915         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
2916                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
2917                  * mirroring. For other rule_type, count and rule_type should
2918                  * not matter.
2919                  */
2920                 if (count == 0 || !mr_list)
2921                         return I40E_ERR_PARAM;
2922         }
2923
2924         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
2925                                   rule_type, rule_id, count, mr_list,
2926                                   cmd_details, NULL, rules_used, rules_free);
2927 }
2928
2929 /**
2930  * i40e_aq_send_msg_to_vf
2931  * @hw: pointer to the hardware structure
2932  * @vfid: VF id to send msg
2933  * @v_opcode: opcodes for VF-PF communication
2934  * @v_retval: return error code
2935  * @msg: pointer to the msg buffer
2936  * @msglen: msg length
2937  * @cmd_details: pointer to command details
2938  *
2939  * send msg to vf
2940  **/
2941 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2942                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2943                                 struct i40e_asq_cmd_details *cmd_details)
2944 {
2945         struct i40e_aq_desc desc;
2946         struct i40e_aqc_pf_vf_message *cmd =
2947                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2948         i40e_status status;
2949
2950         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2951         cmd->id = cpu_to_le32(vfid);
2952         desc.cookie_high = cpu_to_le32(v_opcode);
2953         desc.cookie_low = cpu_to_le32(v_retval);
2954         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2955         if (msglen) {
2956                 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2957                                                 I40E_AQ_FLAG_RD));
2958                 if (msglen > I40E_AQ_LARGE_BUF)
2959                         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2960                 desc.datalen = cpu_to_le16(msglen);
2961         }
2962         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2963
2964         return status;
2965 }
2966
2967 /**
2968  * i40e_aq_debug_read_register
2969  * @hw: pointer to the hw struct
2970  * @reg_addr: register address
2971  * @reg_val: register value
2972  * @cmd_details: pointer to command details structure or NULL
2973  *
2974  * Read the register using the admin queue commands
2975  **/
2976 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
2977                                 u32 reg_addr, u64 *reg_val,
2978                                 struct i40e_asq_cmd_details *cmd_details)
2979 {
2980         struct i40e_aq_desc desc;
2981         struct i40e_aqc_debug_reg_read_write *cmd_resp =
2982                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2983         i40e_status status;
2984
2985         if (reg_val == NULL)
2986                 return I40E_ERR_PARAM;
2987
2988         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2989
2990         cmd_resp->address = cpu_to_le32(reg_addr);
2991
2992         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2993
2994         if (!status) {
2995                 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
2996                            (u64)le32_to_cpu(cmd_resp->value_low);
2997         }
2998
2999         return status;
3000 }
3001
3002 /**
3003  * i40e_aq_debug_write_register
3004  * @hw: pointer to the hw struct
3005  * @reg_addr: register address
3006  * @reg_val: register value
3007  * @cmd_details: pointer to command details structure or NULL
3008  *
3009  * Write to a register using the admin queue commands
3010  **/
3011 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
3012                                         u32 reg_addr, u64 reg_val,
3013                                         struct i40e_asq_cmd_details *cmd_details)
3014 {
3015         struct i40e_aq_desc desc;
3016         struct i40e_aqc_debug_reg_read_write *cmd =
3017                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3018         i40e_status status;
3019
3020         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3021
3022         cmd->address = cpu_to_le32(reg_addr);
3023         cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
3024         cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
3025
3026         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3027
3028         return status;
3029 }
3030
3031 /**
3032  * i40e_aq_request_resource
3033  * @hw: pointer to the hw struct
3034  * @resource: resource id
3035  * @access: access type
3036  * @sdp_number: resource number
3037  * @timeout: the maximum time in ms that the driver may hold the resource
3038  * @cmd_details: pointer to command details structure or NULL
3039  *
3040  * requests common resource using the admin queue commands
3041  **/
3042 i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
3043                                 enum i40e_aq_resources_ids resource,
3044                                 enum i40e_aq_resource_access_type access,
3045                                 u8 sdp_number, u64 *timeout,
3046                                 struct i40e_asq_cmd_details *cmd_details)
3047 {
3048         struct i40e_aq_desc desc;
3049         struct i40e_aqc_request_resource *cmd_resp =
3050                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3051         i40e_status status;
3052
3053         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3054
3055         cmd_resp->resource_id = cpu_to_le16(resource);
3056         cmd_resp->access_type = cpu_to_le16(access);
3057         cmd_resp->resource_number = cpu_to_le32(sdp_number);
3058
3059         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3060         /* The completion specifies the maximum time in ms that the driver
3061          * may hold the resource in the Timeout field.
3062          * If the resource is held by someone else, the command completes with
3063          * busy return value and the timeout field indicates the maximum time
3064          * the current owner of the resource has to free it.
3065          */
3066         if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3067                 *timeout = le32_to_cpu(cmd_resp->timeout);
3068
3069         return status;
3070 }
3071
3072 /**
3073  * i40e_aq_release_resource
3074  * @hw: pointer to the hw struct
3075  * @resource: resource id
3076  * @sdp_number: resource number
3077  * @cmd_details: pointer to command details structure or NULL
3078  *
3079  * release common resource using the admin queue commands
3080  **/
3081 i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
3082                                 enum i40e_aq_resources_ids resource,
3083                                 u8 sdp_number,
3084                                 struct i40e_asq_cmd_details *cmd_details)
3085 {
3086         struct i40e_aq_desc desc;
3087         struct i40e_aqc_request_resource *cmd =
3088                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3089         i40e_status status;
3090
3091         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3092
3093         cmd->resource_id = cpu_to_le16(resource);
3094         cmd->resource_number = cpu_to_le32(sdp_number);
3095
3096         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3097
3098         return status;
3099 }
3100
3101 /**
3102  * i40e_aq_read_nvm
3103  * @hw: pointer to the hw struct
3104  * @module_pointer: module pointer location in words from the NVM beginning
3105  * @offset: byte offset from the module beginning
3106  * @length: length of the section to be read (in bytes from the offset)
3107  * @data: command buffer (size [bytes] = length)
3108  * @last_command: tells if this is the last command in a series
3109  * @cmd_details: pointer to command details structure or NULL
3110  *
3111  * Read the NVM using the admin queue commands
3112  **/
3113 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3114                                 u32 offset, u16 length, void *data,
3115                                 bool last_command,
3116                                 struct i40e_asq_cmd_details *cmd_details)
3117 {
3118         struct i40e_aq_desc desc;
3119         struct i40e_aqc_nvm_update *cmd =
3120                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3121         i40e_status status;
3122
3123         /* In offset the highest byte must be zeroed. */
3124         if (offset & 0xFF000000) {
3125                 status = I40E_ERR_PARAM;
3126                 goto i40e_aq_read_nvm_exit;
3127         }
3128
3129         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3130
3131         /* If this is the last command in a series, set the proper flag. */
3132         if (last_command)
3133                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3134         cmd->module_pointer = module_pointer;
3135         cmd->offset = cpu_to_le32(offset);
3136         cmd->length = cpu_to_le16(length);
3137
3138         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3139         if (length > I40E_AQ_LARGE_BUF)
3140                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3141
3142         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3143
3144 i40e_aq_read_nvm_exit:
3145         return status;
3146 }
3147
3148 /**
3149  * i40e_aq_erase_nvm
3150  * @hw: pointer to the hw struct
3151  * @module_pointer: module pointer location in words from the NVM beginning
3152  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3153  * @length: length of the section to be erased (expressed in 4 KB)
3154  * @last_command: tells if this is the last command in a series
3155  * @cmd_details: pointer to command details structure or NULL
3156  *
3157  * Erase the NVM sector using the admin queue commands
3158  **/
3159 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3160                               u32 offset, u16 length, bool last_command,
3161                               struct i40e_asq_cmd_details *cmd_details)
3162 {
3163         struct i40e_aq_desc desc;
3164         struct i40e_aqc_nvm_update *cmd =
3165                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3166         i40e_status status;
3167
3168         /* In offset the highest byte must be zeroed. */
3169         if (offset & 0xFF000000) {
3170                 status = I40E_ERR_PARAM;
3171                 goto i40e_aq_erase_nvm_exit;
3172         }
3173
3174         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3175
3176         /* If this is the last command in a series, set the proper flag. */
3177         if (last_command)
3178                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3179         cmd->module_pointer = module_pointer;
3180         cmd->offset = cpu_to_le32(offset);
3181         cmd->length = cpu_to_le16(length);
3182
3183         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3184
3185 i40e_aq_erase_nvm_exit:
3186         return status;
3187 }
3188
3189 /**
3190  * i40e_parse_discover_capabilities
3191  * @hw: pointer to the hw struct
3192  * @buff: pointer to a buffer containing device/function capability records
3193  * @cap_count: number of capability records in the list
3194  * @list_type_opc: type of capabilities list to parse
3195  *
3196  * Parse the device/function capabilities list.
3197  **/
3198 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3199                                      u32 cap_count,
3200                                      enum i40e_admin_queue_opc list_type_opc)
3201 {
3202         struct i40e_aqc_list_capabilities_element_resp *cap;
3203         u32 valid_functions, num_functions;
3204         u32 number, logical_id, phys_id;
3205         struct i40e_hw_capabilities *p;
3206         u16 id, ocp_cfg_word0;
3207         i40e_status status;
3208         u8 major_rev;
3209         u32 i = 0;
3210
3211         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3212
3213         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3214                 p = &hw->dev_caps;
3215         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3216                 p = &hw->func_caps;
3217         else
3218                 return;
3219
3220         for (i = 0; i < cap_count; i++, cap++) {
3221                 id = le16_to_cpu(cap->id);
3222                 number = le32_to_cpu(cap->number);
3223                 logical_id = le32_to_cpu(cap->logical_id);
3224                 phys_id = le32_to_cpu(cap->phys_id);
3225                 major_rev = cap->major_rev;
3226
3227                 switch (id) {
3228                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3229                         p->switch_mode = number;
3230                         break;
3231                 case I40E_AQ_CAP_ID_MNG_MODE:
3232                         p->management_mode = number;
3233                         if (major_rev > 1) {
3234                                 p->mng_protocols_over_mctp = logical_id;
3235                                 i40e_debug(hw, I40E_DEBUG_INIT,
3236                                            "HW Capability: Protocols over MCTP = %d\n",
3237                                            p->mng_protocols_over_mctp);
3238                         } else {
3239                                 p->mng_protocols_over_mctp = 0;
3240                         }
3241                         break;
3242                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3243                         p->npar_enable = number;
3244                         break;
3245                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3246                         p->os2bmc = number;
3247                         break;
3248                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3249                         p->valid_functions = number;
3250                         break;
3251                 case I40E_AQ_CAP_ID_SRIOV:
3252                         if (number == 1)
3253                                 p->sr_iov_1_1 = true;
3254                         break;
3255                 case I40E_AQ_CAP_ID_VF:
3256                         p->num_vfs = number;
3257                         p->vf_base_id = logical_id;
3258                         break;
3259                 case I40E_AQ_CAP_ID_VMDQ:
3260                         if (number == 1)
3261                                 p->vmdq = true;
3262                         break;
3263                 case I40E_AQ_CAP_ID_8021QBG:
3264                         if (number == 1)
3265                                 p->evb_802_1_qbg = true;
3266                         break;
3267                 case I40E_AQ_CAP_ID_8021QBR:
3268                         if (number == 1)
3269                                 p->evb_802_1_qbh = true;
3270                         break;
3271                 case I40E_AQ_CAP_ID_VSI:
3272                         p->num_vsis = number;
3273                         break;
3274                 case I40E_AQ_CAP_ID_DCB:
3275                         if (number == 1) {
3276                                 p->dcb = true;
3277                                 p->enabled_tcmap = logical_id;
3278                                 p->maxtc = phys_id;
3279                         }
3280                         break;
3281                 case I40E_AQ_CAP_ID_FCOE:
3282                         if (number == 1)
3283                                 p->fcoe = true;
3284                         break;
3285                 case I40E_AQ_CAP_ID_ISCSI:
3286                         if (number == 1)
3287                                 p->iscsi = true;
3288                         break;
3289                 case I40E_AQ_CAP_ID_RSS:
3290                         p->rss = true;
3291                         p->rss_table_size = number;
3292                         p->rss_table_entry_width = logical_id;
3293                         break;
3294                 case I40E_AQ_CAP_ID_RXQ:
3295                         p->num_rx_qp = number;
3296                         p->base_queue = phys_id;
3297                         break;
3298                 case I40E_AQ_CAP_ID_TXQ:
3299                         p->num_tx_qp = number;
3300                         p->base_queue = phys_id;
3301                         break;
3302                 case I40E_AQ_CAP_ID_MSIX:
3303                         p->num_msix_vectors = number;
3304                         i40e_debug(hw, I40E_DEBUG_INIT,
3305                                    "HW Capability: MSIX vector count = %d\n",
3306                                    p->num_msix_vectors);
3307                         break;
3308                 case I40E_AQ_CAP_ID_VF_MSIX:
3309                         p->num_msix_vectors_vf = number;
3310                         break;
3311                 case I40E_AQ_CAP_ID_FLEX10:
3312                         if (major_rev == 1) {
3313                                 if (number == 1) {
3314                                         p->flex10_enable = true;
3315                                         p->flex10_capable = true;
3316                                 }
3317                         } else {
3318                                 /* Capability revision >= 2 */
3319                                 if (number & 1)
3320                                         p->flex10_enable = true;
3321                                 if (number & 2)
3322                                         p->flex10_capable = true;
3323                         }
3324                         p->flex10_mode = logical_id;
3325                         p->flex10_status = phys_id;
3326                         break;
3327                 case I40E_AQ_CAP_ID_CEM:
3328                         if (number == 1)
3329                                 p->mgmt_cem = true;
3330                         break;
3331                 case I40E_AQ_CAP_ID_IWARP:
3332                         if (number == 1)
3333                                 p->iwarp = true;
3334                         break;
3335                 case I40E_AQ_CAP_ID_LED:
3336                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3337                                 p->led[phys_id] = true;
3338                         break;
3339                 case I40E_AQ_CAP_ID_SDP:
3340                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3341                                 p->sdp[phys_id] = true;
3342                         break;
3343                 case I40E_AQ_CAP_ID_MDIO:
3344                         if (number == 1) {
3345                                 p->mdio_port_num = phys_id;
3346                                 p->mdio_port_mode = logical_id;
3347                         }
3348                         break;
3349                 case I40E_AQ_CAP_ID_1588:
3350                         if (number == 1)
3351                                 p->ieee_1588 = true;
3352                         break;
3353                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3354                         p->fd = true;
3355                         p->fd_filters_guaranteed = number;
3356                         p->fd_filters_best_effort = logical_id;
3357                         break;
3358                 case I40E_AQ_CAP_ID_WSR_PROT:
3359                         p->wr_csr_prot = (u64)number;
3360                         p->wr_csr_prot |= (u64)logical_id << 32;
3361                         break;
3362                 case I40E_AQ_CAP_ID_NVM_MGMT:
3363                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3364                                 p->sec_rev_disabled = true;
3365                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3366                                 p->update_disabled = true;
3367                         break;
3368                 default:
3369                         break;
3370                 }
3371         }
3372
3373         if (p->fcoe)
3374                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3375
3376         /* Software override ensuring FCoE is disabled if npar or mfp
3377          * mode because it is not supported in these modes.
3378          */
3379         if (p->npar_enable || p->flex10_enable)
3380                 p->fcoe = false;
3381
3382         /* count the enabled ports (aka the "not disabled" ports) */
3383         hw->num_ports = 0;
3384         for (i = 0; i < 4; i++) {
3385                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3386                 u64 port_cfg = 0;
3387
3388                 /* use AQ read to get the physical register offset instead
3389                  * of the port relative offset
3390                  */
3391                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3392                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3393                         hw->num_ports++;
3394         }
3395
3396         /* OCP cards case: if a mezz is removed the Ethernet port is at
3397          * disabled state in PRTGEN_CNF register. Additional NVM read is
3398          * needed in order to check if we are dealing with OCP card.
3399          * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
3400          * physical ports results in wrong partition id calculation and thus
3401          * not supporting WoL.
3402          */
3403         if (hw->mac.type == I40E_MAC_X722) {
3404                 if (!i40e_acquire_nvm(hw, I40E_RESOURCE_READ)) {
3405                         status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
3406                                                   2 * I40E_SR_OCP_CFG_WORD0,
3407                                                   sizeof(ocp_cfg_word0),
3408                                                   &ocp_cfg_word0, true, NULL);
3409                         if (!status &&
3410                             (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
3411                                 hw->num_ports = 4;
3412                         i40e_release_nvm(hw);
3413                 }
3414         }
3415
3416         valid_functions = p->valid_functions;
3417         num_functions = 0;
3418         while (valid_functions) {
3419                 if (valid_functions & 1)
3420                         num_functions++;
3421                 valid_functions >>= 1;
3422         }
3423
3424         /* partition id is 1-based, and functions are evenly spread
3425          * across the ports as partitions
3426          */
3427         if (hw->num_ports != 0) {
3428                 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3429                 hw->num_partitions = num_functions / hw->num_ports;
3430         }
3431
3432         /* additional HW specific goodies that might
3433          * someday be HW version specific
3434          */
3435         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3436 }
3437
3438 /**
3439  * i40e_aq_discover_capabilities
3440  * @hw: pointer to the hw struct
3441  * @buff: a virtual buffer to hold the capabilities
3442  * @buff_size: Size of the virtual buffer
3443  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3444  * @list_type_opc: capabilities type to discover - pass in the command opcode
3445  * @cmd_details: pointer to command details structure or NULL
3446  *
3447  * Get the device capabilities descriptions from the firmware
3448  **/
3449 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
3450                                 void *buff, u16 buff_size, u16 *data_size,
3451                                 enum i40e_admin_queue_opc list_type_opc,
3452                                 struct i40e_asq_cmd_details *cmd_details)
3453 {
3454         struct i40e_aqc_list_capabilites *cmd;
3455         struct i40e_aq_desc desc;
3456         i40e_status status = 0;
3457
3458         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3459
3460         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3461                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3462                 status = I40E_ERR_PARAM;
3463                 goto exit;
3464         }
3465
3466         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3467
3468         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3469         if (buff_size > I40E_AQ_LARGE_BUF)
3470                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3471
3472         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3473         *data_size = le16_to_cpu(desc.datalen);
3474
3475         if (status)
3476                 goto exit;
3477
3478         i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
3479                                          list_type_opc);
3480
3481 exit:
3482         return status;
3483 }
3484
3485 /**
3486  * i40e_aq_update_nvm
3487  * @hw: pointer to the hw struct
3488  * @module_pointer: module pointer location in words from the NVM beginning
3489  * @offset: byte offset from the module beginning
3490  * @length: length of the section to be written (in bytes from the offset)
3491  * @data: command buffer (size [bytes] = length)
3492  * @last_command: tells if this is the last command in a series
3493  * @preservation_flags: Preservation mode flags
3494  * @cmd_details: pointer to command details structure or NULL
3495  *
3496  * Update the NVM using the admin queue commands
3497  **/
3498 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3499                                u32 offset, u16 length, void *data,
3500                                 bool last_command, u8 preservation_flags,
3501                                struct i40e_asq_cmd_details *cmd_details)
3502 {
3503         struct i40e_aq_desc desc;
3504         struct i40e_aqc_nvm_update *cmd =
3505                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3506         i40e_status status;
3507
3508         /* In offset the highest byte must be zeroed. */
3509         if (offset & 0xFF000000) {
3510                 status = I40E_ERR_PARAM;
3511                 goto i40e_aq_update_nvm_exit;
3512         }
3513
3514         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3515
3516         /* If this is the last command in a series, set the proper flag. */
3517         if (last_command)
3518                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3519         if (hw->mac.type == I40E_MAC_X722) {
3520                 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
3521                         cmd->command_flags |=
3522                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
3523                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
3524                 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
3525                         cmd->command_flags |=
3526                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
3527                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
3528         }
3529         cmd->module_pointer = module_pointer;
3530         cmd->offset = cpu_to_le32(offset);
3531         cmd->length = cpu_to_le16(length);
3532
3533         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3534         if (length > I40E_AQ_LARGE_BUF)
3535                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3536
3537         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3538
3539 i40e_aq_update_nvm_exit:
3540         return status;
3541 }
3542
3543 /**
3544  * i40e_aq_rearrange_nvm
3545  * @hw: pointer to the hw struct
3546  * @rearrange_nvm: defines direction of rearrangement
3547  * @cmd_details: pointer to command details structure or NULL
3548  *
3549  * Rearrange NVM structure, available only for transition FW
3550  **/
3551 i40e_status i40e_aq_rearrange_nvm(struct i40e_hw *hw,
3552                                   u8 rearrange_nvm,
3553                                   struct i40e_asq_cmd_details *cmd_details)
3554 {
3555         struct i40e_aqc_nvm_update *cmd;
3556         i40e_status status;
3557         struct i40e_aq_desc desc;
3558
3559         cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
3560
3561         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3562
3563         rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
3564                          I40E_AQ_NVM_REARRANGE_TO_STRUCT);
3565
3566         if (!rearrange_nvm) {
3567                 status = I40E_ERR_PARAM;
3568                 goto i40e_aq_rearrange_nvm_exit;
3569         }
3570
3571         cmd->command_flags |= rearrange_nvm;
3572         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3573
3574 i40e_aq_rearrange_nvm_exit:
3575         return status;
3576 }
3577
3578 /**
3579  * i40e_aq_get_lldp_mib
3580  * @hw: pointer to the hw struct
3581  * @bridge_type: type of bridge requested
3582  * @mib_type: Local, Remote or both Local and Remote MIBs
3583  * @buff: pointer to a user supplied buffer to store the MIB block
3584  * @buff_size: size of the buffer (in bytes)
3585  * @local_len : length of the returned Local LLDP MIB
3586  * @remote_len: length of the returned Remote LLDP MIB
3587  * @cmd_details: pointer to command details structure or NULL
3588  *
3589  * Requests the complete LLDP MIB (entire packet).
3590  **/
3591 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3592                                 u8 mib_type, void *buff, u16 buff_size,
3593                                 u16 *local_len, u16 *remote_len,
3594                                 struct i40e_asq_cmd_details *cmd_details)
3595 {
3596         struct i40e_aq_desc desc;
3597         struct i40e_aqc_lldp_get_mib *cmd =
3598                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3599         struct i40e_aqc_lldp_get_mib *resp =
3600                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3601         i40e_status status;
3602
3603         if (buff_size == 0 || !buff)
3604                 return I40E_ERR_PARAM;
3605
3606         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3607         /* Indirect Command */
3608         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3609
3610         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3611         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3612                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3613
3614         desc.datalen = cpu_to_le16(buff_size);
3615
3616         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3617         if (buff_size > I40E_AQ_LARGE_BUF)
3618                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3619
3620         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3621         if (!status) {
3622                 if (local_len != NULL)
3623                         *local_len = le16_to_cpu(resp->local_len);
3624                 if (remote_len != NULL)
3625                         *remote_len = le16_to_cpu(resp->remote_len);
3626         }
3627
3628         return status;
3629 }
3630
3631 /**
3632  * i40e_aq_cfg_lldp_mib_change_event
3633  * @hw: pointer to the hw struct
3634  * @enable_update: Enable or Disable event posting
3635  * @cmd_details: pointer to command details structure or NULL
3636  *
3637  * Enable or Disable posting of an event on ARQ when LLDP MIB
3638  * associated with the interface changes
3639  **/
3640 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3641                                 bool enable_update,
3642                                 struct i40e_asq_cmd_details *cmd_details)
3643 {
3644         struct i40e_aq_desc desc;
3645         struct i40e_aqc_lldp_update_mib *cmd =
3646                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3647         i40e_status status;
3648
3649         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3650
3651         if (!enable_update)
3652                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3653
3654         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3655
3656         return status;
3657 }
3658
3659 /**
3660  * i40e_aq_stop_lldp
3661  * @hw: pointer to the hw struct
3662  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3663  * @cmd_details: pointer to command details structure or NULL
3664  *
3665  * Stop or Shutdown the embedded LLDP Agent
3666  **/
3667 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3668                                 struct i40e_asq_cmd_details *cmd_details)
3669 {
3670         struct i40e_aq_desc desc;
3671         struct i40e_aqc_lldp_stop *cmd =
3672                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3673         i40e_status status;
3674
3675         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3676
3677         if (shutdown_agent)
3678                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3679
3680         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3681
3682         return status;
3683 }
3684
3685 /**
3686  * i40e_aq_start_lldp
3687  * @hw: pointer to the hw struct
3688  * @buff: buffer for result
3689  * @buff_size: buffer size
3690  * @cmd_details: pointer to command details structure or NULL
3691  *
3692  * Start the embedded LLDP Agent on all ports.
3693  **/
3694 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
3695                                 struct i40e_asq_cmd_details *cmd_details)
3696 {
3697         struct i40e_aq_desc desc;
3698         struct i40e_aqc_lldp_start *cmd =
3699                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3700         i40e_status status;
3701
3702         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3703
3704         cmd->command = I40E_AQ_LLDP_AGENT_START;
3705         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3706
3707         return status;
3708 }
3709
3710 /**
3711  * i40e_aq_set_dcb_parameters
3712  * @hw: pointer to the hw struct
3713  * @cmd_details: pointer to command details structure or NULL
3714  * @dcb_enable: True if DCB configuration needs to be applied
3715  *
3716  **/
3717 enum i40e_status_code
3718 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
3719                            struct i40e_asq_cmd_details *cmd_details)
3720 {
3721         struct i40e_aq_desc desc;
3722         struct i40e_aqc_set_dcb_parameters *cmd =
3723                 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
3724         i40e_status status;
3725
3726         i40e_fill_default_direct_cmd_desc(&desc,
3727                                           i40e_aqc_opc_set_dcb_parameters);
3728
3729         if (dcb_enable) {
3730                 cmd->valid_flags = I40E_DCB_VALID;
3731                 cmd->command = I40E_AQ_DCB_SET_AGENT;
3732         }
3733         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3734
3735         return status;
3736 }
3737
3738 /**
3739  * i40e_aq_get_cee_dcb_config
3740  * @hw: pointer to the hw struct
3741  * @buff: response buffer that stores CEE operational configuration
3742  * @buff_size: size of the buffer passed
3743  * @cmd_details: pointer to command details structure or NULL
3744  *
3745  * Get CEE DCBX mode operational configuration from firmware
3746  **/
3747 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3748                                        void *buff, u16 buff_size,
3749                                        struct i40e_asq_cmd_details *cmd_details)
3750 {
3751         struct i40e_aq_desc desc;
3752         i40e_status status;
3753
3754         if (buff_size == 0 || !buff)
3755                 return I40E_ERR_PARAM;
3756
3757         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3758
3759         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3760         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3761                                        cmd_details);
3762
3763         return status;
3764 }
3765
3766 /**
3767  * i40e_aq_add_udp_tunnel
3768  * @hw: pointer to the hw struct
3769  * @udp_port: the UDP port to add in Host byte order
3770  * @protocol_index: protocol index type
3771  * @filter_index: pointer to filter index
3772  * @cmd_details: pointer to command details structure or NULL
3773  *
3774  * Note: Firmware expects the udp_port value to be in Little Endian format,
3775  * and this function will call cpu_to_le16 to convert from Host byte order to
3776  * Little Endian order.
3777  **/
3778 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3779                                 u16 udp_port, u8 protocol_index,
3780                                 u8 *filter_index,
3781                                 struct i40e_asq_cmd_details *cmd_details)
3782 {
3783         struct i40e_aq_desc desc;
3784         struct i40e_aqc_add_udp_tunnel *cmd =
3785                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3786         struct i40e_aqc_del_udp_tunnel_completion *resp =
3787                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3788         i40e_status status;
3789
3790         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3791
3792         cmd->udp_port = cpu_to_le16(udp_port);
3793         cmd->protocol_type = protocol_index;
3794
3795         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3796
3797         if (!status && filter_index)
3798                 *filter_index = resp->index;
3799
3800         return status;
3801 }
3802
3803 /**
3804  * i40e_aq_del_udp_tunnel
3805  * @hw: pointer to the hw struct
3806  * @index: filter index
3807  * @cmd_details: pointer to command details structure or NULL
3808  **/
3809 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3810                                 struct i40e_asq_cmd_details *cmd_details)
3811 {
3812         struct i40e_aq_desc desc;
3813         struct i40e_aqc_remove_udp_tunnel *cmd =
3814                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3815         i40e_status status;
3816
3817         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3818
3819         cmd->index = index;
3820
3821         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3822
3823         return status;
3824 }
3825
3826 /**
3827  * i40e_aq_delete_element - Delete switch element
3828  * @hw: pointer to the hw struct
3829  * @seid: the SEID to delete from the switch
3830  * @cmd_details: pointer to command details structure or NULL
3831  *
3832  * This deletes a switch element from the switch.
3833  **/
3834 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3835                                 struct i40e_asq_cmd_details *cmd_details)
3836 {
3837         struct i40e_aq_desc desc;
3838         struct i40e_aqc_switch_seid *cmd =
3839                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3840         i40e_status status;
3841
3842         if (seid == 0)
3843                 return I40E_ERR_PARAM;
3844
3845         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3846
3847         cmd->seid = cpu_to_le16(seid);
3848
3849         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3850
3851         return status;
3852 }
3853
3854 /**
3855  * i40e_aq_dcb_updated - DCB Updated Command
3856  * @hw: pointer to the hw struct
3857  * @cmd_details: pointer to command details structure or NULL
3858  *
3859  * EMP will return when the shared RPB settings have been
3860  * recomputed and modified. The retval field in the descriptor
3861  * will be set to 0 when RPB is modified.
3862  **/
3863 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
3864                                 struct i40e_asq_cmd_details *cmd_details)
3865 {
3866         struct i40e_aq_desc desc;
3867         i40e_status status;
3868
3869         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3870
3871         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3872
3873         return status;
3874 }
3875
3876 /**
3877  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3878  * @hw: pointer to the hw struct
3879  * @seid: seid for the physical port/switching component/vsi
3880  * @buff: Indirect buffer to hold data parameters and response
3881  * @buff_size: Indirect buffer size
3882  * @opcode: Tx scheduler AQ command opcode
3883  * @cmd_details: pointer to command details structure or NULL
3884  *
3885  * Generic command handler for Tx scheduler AQ commands
3886  **/
3887 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3888                                 void *buff, u16 buff_size,
3889                                  enum i40e_admin_queue_opc opcode,
3890                                 struct i40e_asq_cmd_details *cmd_details)
3891 {
3892         struct i40e_aq_desc desc;
3893         struct i40e_aqc_tx_sched_ind *cmd =
3894                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3895         i40e_status status;
3896         bool cmd_param_flag = false;
3897
3898         switch (opcode) {
3899         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3900         case i40e_aqc_opc_configure_vsi_tc_bw:
3901         case i40e_aqc_opc_enable_switching_comp_ets:
3902         case i40e_aqc_opc_modify_switching_comp_ets:
3903         case i40e_aqc_opc_disable_switching_comp_ets:
3904         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3905         case i40e_aqc_opc_configure_switching_comp_bw_config:
3906                 cmd_param_flag = true;
3907                 break;
3908         case i40e_aqc_opc_query_vsi_bw_config:
3909         case i40e_aqc_opc_query_vsi_ets_sla_config:
3910         case i40e_aqc_opc_query_switching_comp_ets_config:
3911         case i40e_aqc_opc_query_port_ets_config:
3912         case i40e_aqc_opc_query_switching_comp_bw_config:
3913                 cmd_param_flag = false;
3914                 break;
3915         default:
3916                 return I40E_ERR_PARAM;
3917         }
3918
3919         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3920
3921         /* Indirect command */
3922         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3923         if (cmd_param_flag)
3924                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
3925         if (buff_size > I40E_AQ_LARGE_BUF)
3926                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3927
3928         desc.datalen = cpu_to_le16(buff_size);
3929
3930         cmd->vsi_seid = cpu_to_le16(seid);
3931
3932         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3933
3934         return status;
3935 }
3936
3937 /**
3938  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3939  * @hw: pointer to the hw struct
3940  * @seid: VSI seid
3941  * @credit: BW limit credits (0 = disabled)
3942  * @max_credit: Max BW limit credits
3943  * @cmd_details: pointer to command details structure or NULL
3944  **/
3945 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3946                                 u16 seid, u16 credit, u8 max_credit,
3947                                 struct i40e_asq_cmd_details *cmd_details)
3948 {
3949         struct i40e_aq_desc desc;
3950         struct i40e_aqc_configure_vsi_bw_limit *cmd =
3951                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3952         i40e_status status;
3953
3954         i40e_fill_default_direct_cmd_desc(&desc,
3955                                           i40e_aqc_opc_configure_vsi_bw_limit);
3956
3957         cmd->vsi_seid = cpu_to_le16(seid);
3958         cmd->credit = cpu_to_le16(credit);
3959         cmd->max_credit = max_credit;
3960
3961         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3962
3963         return status;
3964 }
3965
3966 /**
3967  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3968  * @hw: pointer to the hw struct
3969  * @seid: VSI seid
3970  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3971  * @cmd_details: pointer to command details structure or NULL
3972  **/
3973 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3974                         u16 seid,
3975                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3976                         struct i40e_asq_cmd_details *cmd_details)
3977 {
3978         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3979                                     i40e_aqc_opc_configure_vsi_tc_bw,
3980                                     cmd_details);
3981 }
3982
3983 /**
3984  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3985  * @hw: pointer to the hw struct
3986  * @seid: seid of the switching component connected to Physical Port
3987  * @ets_data: Buffer holding ETS parameters
3988  * @opcode: Tx scheduler AQ command opcode
3989  * @cmd_details: pointer to command details structure or NULL
3990  **/
3991 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
3992                 u16 seid,
3993                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
3994                 enum i40e_admin_queue_opc opcode,
3995                 struct i40e_asq_cmd_details *cmd_details)
3996 {
3997         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
3998                                     sizeof(*ets_data), opcode, cmd_details);
3999 }
4000
4001 /**
4002  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
4003  * @hw: pointer to the hw struct
4004  * @seid: seid of the switching component
4005  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
4006  * @cmd_details: pointer to command details structure or NULL
4007  **/
4008 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
4009         u16 seid,
4010         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
4011         struct i40e_asq_cmd_details *cmd_details)
4012 {
4013         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4014                             i40e_aqc_opc_configure_switching_comp_bw_config,
4015                             cmd_details);
4016 }
4017
4018 /**
4019  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4020  * @hw: pointer to the hw struct
4021  * @seid: seid of the VSI
4022  * @bw_data: Buffer to hold VSI BW configuration
4023  * @cmd_details: pointer to command details structure or NULL
4024  **/
4025 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4026                         u16 seid,
4027                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4028                         struct i40e_asq_cmd_details *cmd_details)
4029 {
4030         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4031                                     i40e_aqc_opc_query_vsi_bw_config,
4032                                     cmd_details);
4033 }
4034
4035 /**
4036  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4037  * @hw: pointer to the hw struct
4038  * @seid: seid of the VSI
4039  * @bw_data: Buffer to hold VSI BW configuration per TC
4040  * @cmd_details: pointer to command details structure or NULL
4041  **/
4042 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4043                         u16 seid,
4044                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4045                         struct i40e_asq_cmd_details *cmd_details)
4046 {
4047         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4048                                     i40e_aqc_opc_query_vsi_ets_sla_config,
4049                                     cmd_details);
4050 }
4051
4052 /**
4053  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4054  * @hw: pointer to the hw struct
4055  * @seid: seid of the switching component
4056  * @bw_data: Buffer to hold switching component's per TC BW config
4057  * @cmd_details: pointer to command details structure or NULL
4058  **/
4059 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4060                 u16 seid,
4061                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4062                 struct i40e_asq_cmd_details *cmd_details)
4063 {
4064         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4065                                    i40e_aqc_opc_query_switching_comp_ets_config,
4066                                    cmd_details);
4067 }
4068
4069 /**
4070  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4071  * @hw: pointer to the hw struct
4072  * @seid: seid of the VSI or switching component connected to Physical Port
4073  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4074  * @cmd_details: pointer to command details structure or NULL
4075  **/
4076 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4077                         u16 seid,
4078                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
4079                         struct i40e_asq_cmd_details *cmd_details)
4080 {
4081         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4082                                     i40e_aqc_opc_query_port_ets_config,
4083                                     cmd_details);
4084 }
4085
4086 /**
4087  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4088  * @hw: pointer to the hw struct
4089  * @seid: seid of the switching component
4090  * @bw_data: Buffer to hold switching component's BW configuration
4091  * @cmd_details: pointer to command details structure or NULL
4092  **/
4093 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4094                 u16 seid,
4095                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4096                 struct i40e_asq_cmd_details *cmd_details)
4097 {
4098         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4099                                     i40e_aqc_opc_query_switching_comp_bw_config,
4100                                     cmd_details);
4101 }
4102
4103 /**
4104  * i40e_validate_filter_settings
4105  * @hw: pointer to the hardware structure
4106  * @settings: Filter control settings
4107  *
4108  * Check and validate the filter control settings passed.
4109  * The function checks for the valid filter/context sizes being
4110  * passed for FCoE and PE.
4111  *
4112  * Returns 0 if the values passed are valid and within
4113  * range else returns an error.
4114  **/
4115 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
4116                                 struct i40e_filter_control_settings *settings)
4117 {
4118         u32 fcoe_cntx_size, fcoe_filt_size;
4119         u32 pe_cntx_size, pe_filt_size;
4120         u32 fcoe_fmax;
4121         u32 val;
4122
4123         /* Validate FCoE settings passed */
4124         switch (settings->fcoe_filt_num) {
4125         case I40E_HASH_FILTER_SIZE_1K:
4126         case I40E_HASH_FILTER_SIZE_2K:
4127         case I40E_HASH_FILTER_SIZE_4K:
4128         case I40E_HASH_FILTER_SIZE_8K:
4129         case I40E_HASH_FILTER_SIZE_16K:
4130         case I40E_HASH_FILTER_SIZE_32K:
4131                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4132                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4133                 break;
4134         default:
4135                 return I40E_ERR_PARAM;
4136         }
4137
4138         switch (settings->fcoe_cntx_num) {
4139         case I40E_DMA_CNTX_SIZE_512:
4140         case I40E_DMA_CNTX_SIZE_1K:
4141         case I40E_DMA_CNTX_SIZE_2K:
4142         case I40E_DMA_CNTX_SIZE_4K:
4143                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4144                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4145                 break;
4146         default:
4147                 return I40E_ERR_PARAM;
4148         }
4149
4150         /* Validate PE settings passed */
4151         switch (settings->pe_filt_num) {
4152         case I40E_HASH_FILTER_SIZE_1K:
4153         case I40E_HASH_FILTER_SIZE_2K:
4154         case I40E_HASH_FILTER_SIZE_4K:
4155         case I40E_HASH_FILTER_SIZE_8K:
4156         case I40E_HASH_FILTER_SIZE_16K:
4157         case I40E_HASH_FILTER_SIZE_32K:
4158         case I40E_HASH_FILTER_SIZE_64K:
4159         case I40E_HASH_FILTER_SIZE_128K:
4160         case I40E_HASH_FILTER_SIZE_256K:
4161         case I40E_HASH_FILTER_SIZE_512K:
4162         case I40E_HASH_FILTER_SIZE_1M:
4163                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4164                 pe_filt_size <<= (u32)settings->pe_filt_num;
4165                 break;
4166         default:
4167                 return I40E_ERR_PARAM;
4168         }
4169
4170         switch (settings->pe_cntx_num) {
4171         case I40E_DMA_CNTX_SIZE_512:
4172         case I40E_DMA_CNTX_SIZE_1K:
4173         case I40E_DMA_CNTX_SIZE_2K:
4174         case I40E_DMA_CNTX_SIZE_4K:
4175         case I40E_DMA_CNTX_SIZE_8K:
4176         case I40E_DMA_CNTX_SIZE_16K:
4177         case I40E_DMA_CNTX_SIZE_32K:
4178         case I40E_DMA_CNTX_SIZE_64K:
4179         case I40E_DMA_CNTX_SIZE_128K:
4180         case I40E_DMA_CNTX_SIZE_256K:
4181                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4182                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4183                 break;
4184         default:
4185                 return I40E_ERR_PARAM;
4186         }
4187
4188         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4189         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4190         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4191                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4192         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
4193                 return I40E_ERR_INVALID_SIZE;
4194
4195         return 0;
4196 }
4197
4198 /**
4199  * i40e_set_filter_control
4200  * @hw: pointer to the hardware structure
4201  * @settings: Filter control settings
4202  *
4203  * Set the Queue Filters for PE/FCoE and enable filters required
4204  * for a single PF. It is expected that these settings are programmed
4205  * at the driver initialization time.
4206  **/
4207 i40e_status i40e_set_filter_control(struct i40e_hw *hw,
4208                                 struct i40e_filter_control_settings *settings)
4209 {
4210         i40e_status ret = 0;
4211         u32 hash_lut_size = 0;
4212         u32 val;
4213
4214         if (!settings)
4215                 return I40E_ERR_PARAM;
4216
4217         /* Validate the input settings */
4218         ret = i40e_validate_filter_settings(hw, settings);
4219         if (ret)
4220                 return ret;
4221
4222         /* Read the PF Queue Filter control register */
4223         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
4224
4225         /* Program required PE hash buckets for the PF */
4226         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4227         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4228                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4229         /* Program required PE contexts for the PF */
4230         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4231         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4232                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4233
4234         /* Program required FCoE hash buckets for the PF */
4235         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4236         val |= ((u32)settings->fcoe_filt_num <<
4237                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4238                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4239         /* Program required FCoE DDP contexts for the PF */
4240         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4241         val |= ((u32)settings->fcoe_cntx_num <<
4242                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4243                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4244
4245         /* Program Hash LUT size for the PF */
4246         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4247         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4248                 hash_lut_size = 1;
4249         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4250                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4251
4252         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4253         if (settings->enable_fdir)
4254                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4255         if (settings->enable_ethtype)
4256                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4257         if (settings->enable_macvlan)
4258                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4259
4260         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
4261
4262         return 0;
4263 }
4264
4265 /**
4266  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4267  * @hw: pointer to the hw struct
4268  * @mac_addr: MAC address to use in the filter
4269  * @ethtype: Ethertype to use in the filter
4270  * @flags: Flags that needs to be applied to the filter
4271  * @vsi_seid: seid of the control VSI
4272  * @queue: VSI queue number to send the packet to
4273  * @is_add: Add control packet filter if True else remove
4274  * @stats: Structure to hold information on control filter counts
4275  * @cmd_details: pointer to command details structure or NULL
4276  *
4277  * This command will Add or Remove control packet filter for a control VSI.
4278  * In return it will update the total number of perfect filter count in
4279  * the stats member.
4280  **/
4281 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4282                                 u8 *mac_addr, u16 ethtype, u16 flags,
4283                                 u16 vsi_seid, u16 queue, bool is_add,
4284                                 struct i40e_control_filter_stats *stats,
4285                                 struct i40e_asq_cmd_details *cmd_details)
4286 {
4287         struct i40e_aq_desc desc;
4288         struct i40e_aqc_add_remove_control_packet_filter *cmd =
4289                 (struct i40e_aqc_add_remove_control_packet_filter *)
4290                 &desc.params.raw;
4291         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4292                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4293                 &desc.params.raw;
4294         i40e_status status;
4295
4296         if (vsi_seid == 0)
4297                 return I40E_ERR_PARAM;
4298
4299         if (is_add) {
4300                 i40e_fill_default_direct_cmd_desc(&desc,
4301                                 i40e_aqc_opc_add_control_packet_filter);
4302                 cmd->queue = cpu_to_le16(queue);
4303         } else {
4304                 i40e_fill_default_direct_cmd_desc(&desc,
4305                                 i40e_aqc_opc_remove_control_packet_filter);
4306         }
4307
4308         if (mac_addr)
4309                 ether_addr_copy(cmd->mac, mac_addr);
4310
4311         cmd->etype = cpu_to_le16(ethtype);
4312         cmd->flags = cpu_to_le16(flags);
4313         cmd->seid = cpu_to_le16(vsi_seid);
4314
4315         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4316
4317         if (!status && stats) {
4318                 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
4319                 stats->etype_used = le16_to_cpu(resp->etype_used);
4320                 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
4321                 stats->etype_free = le16_to_cpu(resp->etype_free);
4322         }
4323
4324         return status;
4325 }
4326
4327 /**
4328  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
4329  * @hw: pointer to the hw struct
4330  * @seid: VSI seid to add ethertype filter from
4331  **/
4332 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
4333                                                     u16 seid)
4334 {
4335 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
4336         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
4337                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
4338                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
4339         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
4340         i40e_status status;
4341
4342         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
4343                                                        seid, 0, true, NULL,
4344                                                        NULL);
4345         if (status)
4346                 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
4347 }
4348
4349 /**
4350  * i40e_aq_alternate_read
4351  * @hw: pointer to the hardware structure
4352  * @reg_addr0: address of first dword to be read
4353  * @reg_val0: pointer for data read from 'reg_addr0'
4354  * @reg_addr1: address of second dword to be read
4355  * @reg_val1: pointer for data read from 'reg_addr1'
4356  *
4357  * Read one or two dwords from alternate structure. Fields are indicated
4358  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4359  * is not passed then only register at 'reg_addr0' is read.
4360  *
4361  **/
4362 static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
4363                                           u32 reg_addr0, u32 *reg_val0,
4364                                           u32 reg_addr1, u32 *reg_val1)
4365 {
4366         struct i40e_aq_desc desc;
4367         struct i40e_aqc_alternate_write *cmd_resp =
4368                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4369         i40e_status status;
4370
4371         if (!reg_val0)
4372                 return I40E_ERR_PARAM;
4373
4374         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4375         cmd_resp->address0 = cpu_to_le32(reg_addr0);
4376         cmd_resp->address1 = cpu_to_le32(reg_addr1);
4377
4378         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4379
4380         if (!status) {
4381                 *reg_val0 = le32_to_cpu(cmd_resp->data0);
4382
4383                 if (reg_val1)
4384                         *reg_val1 = le32_to_cpu(cmd_resp->data1);
4385         }
4386
4387         return status;
4388 }
4389
4390 /**
4391  * i40e_aq_resume_port_tx
4392  * @hw: pointer to the hardware structure
4393  * @cmd_details: pointer to command details structure or NULL
4394  *
4395  * Resume port's Tx traffic
4396  **/
4397 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
4398                                    struct i40e_asq_cmd_details *cmd_details)
4399 {
4400         struct i40e_aq_desc desc;
4401         i40e_status status;
4402
4403         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4404
4405         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4406
4407         return status;
4408 }
4409
4410 /**
4411  * i40e_set_pci_config_data - store PCI bus info
4412  * @hw: pointer to hardware structure
4413  * @link_status: the link status word from PCI config space
4414  *
4415  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4416  **/
4417 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4418 {
4419         hw->bus.type = i40e_bus_type_pci_express;
4420
4421         switch (link_status & PCI_EXP_LNKSTA_NLW) {
4422         case PCI_EXP_LNKSTA_NLW_X1:
4423                 hw->bus.width = i40e_bus_width_pcie_x1;
4424                 break;
4425         case PCI_EXP_LNKSTA_NLW_X2:
4426                 hw->bus.width = i40e_bus_width_pcie_x2;
4427                 break;
4428         case PCI_EXP_LNKSTA_NLW_X4:
4429                 hw->bus.width = i40e_bus_width_pcie_x4;
4430                 break;
4431         case PCI_EXP_LNKSTA_NLW_X8:
4432                 hw->bus.width = i40e_bus_width_pcie_x8;
4433                 break;
4434         default:
4435                 hw->bus.width = i40e_bus_width_unknown;
4436                 break;
4437         }
4438
4439         switch (link_status & PCI_EXP_LNKSTA_CLS) {
4440         case PCI_EXP_LNKSTA_CLS_2_5GB:
4441                 hw->bus.speed = i40e_bus_speed_2500;
4442                 break;
4443         case PCI_EXP_LNKSTA_CLS_5_0GB:
4444                 hw->bus.speed = i40e_bus_speed_5000;
4445                 break;
4446         case PCI_EXP_LNKSTA_CLS_8_0GB:
4447                 hw->bus.speed = i40e_bus_speed_8000;
4448                 break;
4449         default:
4450                 hw->bus.speed = i40e_bus_speed_unknown;
4451                 break;
4452         }
4453 }
4454
4455 /**
4456  * i40e_aq_debug_dump
4457  * @hw: pointer to the hardware structure
4458  * @cluster_id: specific cluster to dump
4459  * @table_id: table id within cluster
4460  * @start_index: index of line in the block to read
4461  * @buff_size: dump buffer size
4462  * @buff: dump buffer
4463  * @ret_buff_size: actual buffer size returned
4464  * @ret_next_table: next block to read
4465  * @ret_next_index: next index to read
4466  * @cmd_details: pointer to command details structure or NULL
4467  *
4468  * Dump internal FW/HW data for debug purposes.
4469  *
4470  **/
4471 i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
4472                                u8 table_id, u32 start_index, u16 buff_size,
4473                                void *buff, u16 *ret_buff_size,
4474                                u8 *ret_next_table, u32 *ret_next_index,
4475                                struct i40e_asq_cmd_details *cmd_details)
4476 {
4477         struct i40e_aq_desc desc;
4478         struct i40e_aqc_debug_dump_internals *cmd =
4479                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4480         struct i40e_aqc_debug_dump_internals *resp =
4481                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4482         i40e_status status;
4483
4484         if (buff_size == 0 || !buff)
4485                 return I40E_ERR_PARAM;
4486
4487         i40e_fill_default_direct_cmd_desc(&desc,
4488                                           i40e_aqc_opc_debug_dump_internals);
4489         /* Indirect Command */
4490         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4491         if (buff_size > I40E_AQ_LARGE_BUF)
4492                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4493
4494         cmd->cluster_id = cluster_id;
4495         cmd->table_id = table_id;
4496         cmd->idx = cpu_to_le32(start_index);
4497
4498         desc.datalen = cpu_to_le16(buff_size);
4499
4500         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4501         if (!status) {
4502                 if (ret_buff_size)
4503                         *ret_buff_size = le16_to_cpu(desc.datalen);
4504                 if (ret_next_table)
4505                         *ret_next_table = resp->table_id;
4506                 if (ret_next_index)
4507                         *ret_next_index = le32_to_cpu(resp->idx);
4508         }
4509
4510         return status;
4511 }
4512
4513 /**
4514  * i40e_read_bw_from_alt_ram
4515  * @hw: pointer to the hardware structure
4516  * @max_bw: pointer for max_bw read
4517  * @min_bw: pointer for min_bw read
4518  * @min_valid: pointer for bool that is true if min_bw is a valid value
4519  * @max_valid: pointer for bool that is true if max_bw is a valid value
4520  *
4521  * Read bw from the alternate ram for the given pf
4522  **/
4523 i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4524                                       u32 *max_bw, u32 *min_bw,
4525                                       bool *min_valid, bool *max_valid)
4526 {
4527         i40e_status status;
4528         u32 max_bw_addr, min_bw_addr;
4529
4530         /* Calculate the address of the min/max bw registers */
4531         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4532                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
4533                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4534         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4535                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
4536                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4537
4538         /* Read the bandwidths from alt ram */
4539         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4540                                         min_bw_addr, min_bw);
4541
4542         if (*min_bw & I40E_ALT_BW_VALID_MASK)
4543                 *min_valid = true;
4544         else
4545                 *min_valid = false;
4546
4547         if (*max_bw & I40E_ALT_BW_VALID_MASK)
4548                 *max_valid = true;
4549         else
4550                 *max_valid = false;
4551
4552         return status;
4553 }
4554
4555 /**
4556  * i40e_aq_configure_partition_bw
4557  * @hw: pointer to the hardware structure
4558  * @bw_data: Buffer holding valid pfs and bw limits
4559  * @cmd_details: pointer to command details
4560  *
4561  * Configure partitions guaranteed/max bw
4562  **/
4563 i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4564                         struct i40e_aqc_configure_partition_bw_data *bw_data,
4565                         struct i40e_asq_cmd_details *cmd_details)
4566 {
4567         i40e_status status;
4568         struct i40e_aq_desc desc;
4569         u16 bwd_size = sizeof(*bw_data);
4570
4571         i40e_fill_default_direct_cmd_desc(&desc,
4572                                           i40e_aqc_opc_configure_partition_bw);
4573
4574         /* Indirect command */
4575         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4576         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4577
4578         if (bwd_size > I40E_AQ_LARGE_BUF)
4579                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4580
4581         desc.datalen = cpu_to_le16(bwd_size);
4582
4583         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
4584                                        cmd_details);
4585
4586         return status;
4587 }
4588
4589 /**
4590  * i40e_read_phy_register_clause22
4591  * @hw: pointer to the HW structure
4592  * @reg: register address in the page
4593  * @phy_addr: PHY address on MDIO interface
4594  * @value: PHY register value
4595  *
4596  * Reads specified PHY register value
4597  **/
4598 i40e_status i40e_read_phy_register_clause22(struct i40e_hw *hw,
4599                                             u16 reg, u8 phy_addr, u16 *value)
4600 {
4601         i40e_status status = I40E_ERR_TIMEOUT;
4602         u8 port_num = (u8)hw->func_caps.mdio_port_num;
4603         u32 command = 0;
4604         u16 retry = 1000;
4605
4606         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4607                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4608                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
4609                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
4610                   (I40E_GLGEN_MSCA_MDICMD_MASK);
4611         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4612         do {
4613                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4614                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4615                         status = 0;
4616                         break;
4617                 }
4618                 udelay(10);
4619                 retry--;
4620         } while (retry);
4621
4622         if (status) {
4623                 i40e_debug(hw, I40E_DEBUG_PHY,
4624                            "PHY: Can't write command to external PHY.\n");
4625         } else {
4626                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4627                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4628                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4629         }
4630
4631         return status;
4632 }
4633
4634 /**
4635  * i40e_write_phy_register_clause22
4636  * @hw: pointer to the HW structure
4637  * @reg: register address in the page
4638  * @phy_addr: PHY address on MDIO interface
4639  * @value: PHY register value
4640  *
4641  * Writes specified PHY register value
4642  **/
4643 i40e_status i40e_write_phy_register_clause22(struct i40e_hw *hw,
4644                                              u16 reg, u8 phy_addr, u16 value)
4645 {
4646         i40e_status status = I40E_ERR_TIMEOUT;
4647         u8 port_num = (u8)hw->func_caps.mdio_port_num;
4648         u32 command  = 0;
4649         u16 retry = 1000;
4650
4651         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4652         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4653
4654         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4655                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4656                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
4657                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
4658                   (I40E_GLGEN_MSCA_MDICMD_MASK);
4659
4660         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4661         do {
4662                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4663                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4664                         status = 0;
4665                         break;
4666                 }
4667                 udelay(10);
4668                 retry--;
4669         } while (retry);
4670
4671         return status;
4672 }
4673
4674 /**
4675  * i40e_read_phy_register_clause45
4676  * @hw: pointer to the HW structure
4677  * @page: registers page number
4678  * @reg: register address in the page
4679  * @phy_addr: PHY address on MDIO interface
4680  * @value: PHY register value
4681  *
4682  * Reads specified PHY register value
4683  **/
4684 i40e_status i40e_read_phy_register_clause45(struct i40e_hw *hw,
4685                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
4686 {
4687         i40e_status status = I40E_ERR_TIMEOUT;
4688         u32 command = 0;
4689         u16 retry = 1000;
4690         u8 port_num = hw->func_caps.mdio_port_num;
4691
4692         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4693                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4694                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4695                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4696                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4697                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
4698                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4699         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4700         do {
4701                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4702                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4703                         status = 0;
4704                         break;
4705                 }
4706                 usleep_range(10, 20);
4707                 retry--;
4708         } while (retry);
4709
4710         if (status) {
4711                 i40e_debug(hw, I40E_DEBUG_PHY,
4712                            "PHY: Can't write command to external PHY.\n");
4713                 goto phy_read_end;
4714         }
4715
4716         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4717                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4718                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
4719                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4720                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
4721                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4722         status = I40E_ERR_TIMEOUT;
4723         retry = 1000;
4724         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4725         do {
4726                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4727                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4728                         status = 0;
4729                         break;
4730                 }
4731                 usleep_range(10, 20);
4732                 retry--;
4733         } while (retry);
4734
4735         if (!status) {
4736                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4737                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4738                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4739         } else {
4740                 i40e_debug(hw, I40E_DEBUG_PHY,
4741                            "PHY: Can't read register value from external PHY.\n");
4742         }
4743
4744 phy_read_end:
4745         return status;
4746 }
4747
4748 /**
4749  * i40e_write_phy_register_clause45
4750  * @hw: pointer to the HW structure
4751  * @page: registers page number
4752  * @reg: register address in the page
4753  * @phy_addr: PHY address on MDIO interface
4754  * @value: PHY register value
4755  *
4756  * Writes value to specified PHY register
4757  **/
4758 i40e_status i40e_write_phy_register_clause45(struct i40e_hw *hw,
4759                                 u8 page, u16 reg, u8 phy_addr, u16 value)
4760 {
4761         i40e_status status = I40E_ERR_TIMEOUT;
4762         u32 command = 0;
4763         u16 retry = 1000;
4764         u8 port_num = hw->func_caps.mdio_port_num;
4765
4766         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4767                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4768                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4769                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4770                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4771                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
4772                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4773         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4774         do {
4775                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4776                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4777                         status = 0;
4778                         break;
4779                 }
4780                 usleep_range(10, 20);
4781                 retry--;
4782         } while (retry);
4783         if (status) {
4784                 i40e_debug(hw, I40E_DEBUG_PHY,
4785                            "PHY: Can't write command to external PHY.\n");
4786                 goto phy_write_end;
4787         }
4788
4789         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4790         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4791
4792         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4793                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4794                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
4795                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4796                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
4797                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4798         status = I40E_ERR_TIMEOUT;
4799         retry = 1000;
4800         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4801         do {
4802                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4803                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4804                         status = 0;
4805                         break;
4806                 }
4807                 usleep_range(10, 20);
4808                 retry--;
4809         } while (retry);
4810
4811 phy_write_end:
4812         return status;
4813 }
4814
4815 /**
4816  * i40e_write_phy_register
4817  * @hw: pointer to the HW structure
4818  * @page: registers page number
4819  * @reg: register address in the page
4820  * @phy_addr: PHY address on MDIO interface
4821  * @value: PHY register value
4822  *
4823  * Writes value to specified PHY register
4824  **/
4825 i40e_status i40e_write_phy_register(struct i40e_hw *hw,
4826                                     u8 page, u16 reg, u8 phy_addr, u16 value)
4827 {
4828         i40e_status status;
4829
4830         switch (hw->device_id) {
4831         case I40E_DEV_ID_1G_BASE_T_X722:
4832                 status = i40e_write_phy_register_clause22(hw, reg, phy_addr,
4833                                                           value);
4834                 break;
4835         case I40E_DEV_ID_10G_BASE_T:
4836         case I40E_DEV_ID_10G_BASE_T4:
4837         case I40E_DEV_ID_10G_BASE_T_X722:
4838         case I40E_DEV_ID_25G_B:
4839         case I40E_DEV_ID_25G_SFP28:
4840                 status = i40e_write_phy_register_clause45(hw, page, reg,
4841                                                           phy_addr, value);
4842                 break;
4843         default:
4844                 status = I40E_ERR_UNKNOWN_PHY;
4845                 break;
4846         }
4847
4848         return status;
4849 }
4850
4851 /**
4852  * i40e_read_phy_register
4853  * @hw: pointer to the HW structure
4854  * @page: registers page number
4855  * @reg: register address in the page
4856  * @phy_addr: PHY address on MDIO interface
4857  * @value: PHY register value
4858  *
4859  * Reads specified PHY register value
4860  **/
4861 i40e_status i40e_read_phy_register(struct i40e_hw *hw,
4862                                    u8 page, u16 reg, u8 phy_addr, u16 *value)
4863 {
4864         i40e_status status;
4865
4866         switch (hw->device_id) {
4867         case I40E_DEV_ID_1G_BASE_T_X722:
4868                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
4869                                                          value);
4870                 break;
4871         case I40E_DEV_ID_10G_BASE_T:
4872         case I40E_DEV_ID_10G_BASE_T4:
4873         case I40E_DEV_ID_10G_BASE_T_X722:
4874         case I40E_DEV_ID_25G_B:
4875         case I40E_DEV_ID_25G_SFP28:
4876                 status = i40e_read_phy_register_clause45(hw, page, reg,
4877                                                          phy_addr, value);
4878                 break;
4879         default:
4880                 status = I40E_ERR_UNKNOWN_PHY;
4881                 break;
4882         }
4883
4884         return status;
4885 }
4886
4887 /**
4888  * i40e_get_phy_address
4889  * @hw: pointer to the HW structure
4890  * @dev_num: PHY port num that address we want
4891  *
4892  * Gets PHY address for current port
4893  **/
4894 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
4895 {
4896         u8 port_num = hw->func_caps.mdio_port_num;
4897         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
4898
4899         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
4900 }
4901
4902 /**
4903  * i40e_blink_phy_led
4904  * @hw: pointer to the HW structure
4905  * @time: time how long led will blinks in secs
4906  * @interval: gap between LED on and off in msecs
4907  *
4908  * Blinks PHY link LED
4909  **/
4910 i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,
4911                                     u32 time, u32 interval)
4912 {
4913         i40e_status status = 0;
4914         u32 i;
4915         u16 led_ctl;
4916         u16 gpio_led_port;
4917         u16 led_reg;
4918         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
4919         u8 phy_addr = 0;
4920         u8 port_num;
4921
4922         i = rd32(hw, I40E_PFGEN_PORTNUM);
4923         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4924         phy_addr = i40e_get_phy_address(hw, port_num);
4925
4926         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4927              led_addr++) {
4928                 status = i40e_read_phy_register_clause45(hw,
4929                                                          I40E_PHY_COM_REG_PAGE,
4930                                                          led_addr, phy_addr,
4931                                                          &led_reg);
4932                 if (status)
4933                         goto phy_blinking_end;
4934                 led_ctl = led_reg;
4935                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4936                         led_reg = 0;
4937                         status = i40e_write_phy_register_clause45(hw,
4938                                                          I40E_PHY_COM_REG_PAGE,
4939                                                          led_addr, phy_addr,
4940                                                          led_reg);
4941                         if (status)
4942                                 goto phy_blinking_end;
4943                         break;
4944                 }
4945         }
4946
4947         if (time > 0 && interval > 0) {
4948                 for (i = 0; i < time * 1000; i += interval) {
4949                         status = i40e_read_phy_register_clause45(hw,
4950                                                 I40E_PHY_COM_REG_PAGE,
4951                                                 led_addr, phy_addr, &led_reg);
4952                         if (status)
4953                                 goto restore_config;
4954                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
4955                                 led_reg = 0;
4956                         else
4957                                 led_reg = I40E_PHY_LED_MANUAL_ON;
4958                         status = i40e_write_phy_register_clause45(hw,
4959                                                 I40E_PHY_COM_REG_PAGE,
4960                                                 led_addr, phy_addr, led_reg);
4961                         if (status)
4962                                 goto restore_config;
4963                         msleep(interval);
4964                 }
4965         }
4966
4967 restore_config:
4968         status = i40e_write_phy_register_clause45(hw,
4969                                                   I40E_PHY_COM_REG_PAGE,
4970                                                   led_addr, phy_addr, led_ctl);
4971
4972 phy_blinking_end:
4973         return status;
4974 }
4975
4976 /**
4977  * i40e_led_get_reg - read LED register
4978  * @hw: pointer to the HW structure
4979  * @led_addr: LED register address
4980  * @reg_val: read register value
4981  **/
4982 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
4983                                               u32 *reg_val)
4984 {
4985         enum i40e_status_code status;
4986         u8 phy_addr = 0;
4987         u8 port_num;
4988         u32 i;
4989
4990         *reg_val = 0;
4991         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
4992                 status =
4993                        i40e_aq_get_phy_register(hw,
4994                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
4995                                                 I40E_PHY_COM_REG_PAGE,
4996                                                 I40E_PHY_LED_PROV_REG_1,
4997                                                 reg_val, NULL);
4998         } else {
4999                 i = rd32(hw, I40E_PFGEN_PORTNUM);
5000                 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
5001                 phy_addr = i40e_get_phy_address(hw, port_num);
5002                 status = i40e_read_phy_register_clause45(hw,
5003                                                          I40E_PHY_COM_REG_PAGE,
5004                                                          led_addr, phy_addr,
5005                                                          (u16 *)reg_val);
5006         }
5007         return status;
5008 }
5009
5010 /**
5011  * i40e_led_set_reg - write LED register
5012  * @hw: pointer to the HW structure
5013  * @led_addr: LED register address
5014  * @reg_val: register value to write
5015  **/
5016 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
5017                                               u32 reg_val)
5018 {
5019         enum i40e_status_code status;
5020         u8 phy_addr = 0;
5021         u8 port_num;
5022         u32 i;
5023
5024         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
5025                 status =
5026                        i40e_aq_set_phy_register(hw,
5027                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
5028                                                 I40E_PHY_COM_REG_PAGE,
5029                                                 I40E_PHY_LED_PROV_REG_1,
5030                                                 reg_val, NULL);
5031         } else {
5032                 i = rd32(hw, I40E_PFGEN_PORTNUM);
5033                 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
5034                 phy_addr = i40e_get_phy_address(hw, port_num);
5035                 status = i40e_write_phy_register_clause45(hw,
5036                                                           I40E_PHY_COM_REG_PAGE,
5037                                                           led_addr, phy_addr,
5038                                                           (u16)reg_val);
5039         }
5040
5041         return status;
5042 }
5043
5044 /**
5045  * i40e_led_get_phy - return current on/off mode
5046  * @hw: pointer to the hw struct
5047  * @led_addr: address of led register to use
5048  * @val: original value of register to use
5049  *
5050  **/
5051 i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
5052                              u16 *val)
5053 {
5054         i40e_status status = 0;
5055         u16 gpio_led_port;
5056         u8 phy_addr = 0;
5057         u16 reg_val;
5058         u16 temp_addr;
5059         u8 port_num;
5060         u32 i;
5061         u32 reg_val_aq;
5062
5063         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
5064                 status =
5065                       i40e_aq_get_phy_register(hw,
5066                                                I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
5067                                                I40E_PHY_COM_REG_PAGE,
5068                                                I40E_PHY_LED_PROV_REG_1,
5069                                                &reg_val_aq, NULL);
5070                 if (status == I40E_SUCCESS)
5071                         *val = (u16)reg_val_aq;
5072                 return status;
5073         }
5074         temp_addr = I40E_PHY_LED_PROV_REG_1;
5075         i = rd32(hw, I40E_PFGEN_PORTNUM);
5076         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
5077         phy_addr = i40e_get_phy_address(hw, port_num);
5078
5079         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
5080              temp_addr++) {
5081                 status = i40e_read_phy_register_clause45(hw,
5082                                                          I40E_PHY_COM_REG_PAGE,
5083                                                          temp_addr, phy_addr,
5084                                                          &reg_val);
5085                 if (status)
5086                         return status;
5087                 *val = reg_val;
5088                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
5089                         *led_addr = temp_addr;
5090                         break;
5091                 }
5092         }
5093         return status;
5094 }
5095
5096 /**
5097  * i40e_led_set_phy
5098  * @hw: pointer to the HW structure
5099  * @on: true or false
5100  * @led_addr: address of led register to use
5101  * @mode: original val plus bit for set or ignore
5102  *
5103  * Set led's on or off when controlled by the PHY
5104  *
5105  **/
5106 i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on,
5107                              u16 led_addr, u32 mode)
5108 {
5109         i40e_status status = 0;
5110         u32 led_ctl = 0;
5111         u32 led_reg = 0;
5112
5113         status = i40e_led_get_reg(hw, led_addr, &led_reg);
5114         if (status)
5115                 return status;
5116         led_ctl = led_reg;
5117         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
5118                 led_reg = 0;
5119                 status = i40e_led_set_reg(hw, led_addr, led_reg);
5120                 if (status)
5121                         return status;
5122         }
5123         status = i40e_led_get_reg(hw, led_addr, &led_reg);
5124         if (status)
5125                 goto restore_config;
5126         if (on)
5127                 led_reg = I40E_PHY_LED_MANUAL_ON;
5128         else
5129                 led_reg = 0;
5130
5131         status = i40e_led_set_reg(hw, led_addr, led_reg);
5132         if (status)
5133                 goto restore_config;
5134         if (mode & I40E_PHY_LED_MODE_ORIG) {
5135                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
5136                 status = i40e_led_set_reg(hw, led_addr, led_ctl);
5137         }
5138         return status;
5139
5140 restore_config:
5141         status = i40e_led_set_reg(hw, led_addr, led_ctl);
5142         return status;
5143 }
5144
5145 /**
5146  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
5147  * @hw: pointer to the hw struct
5148  * @reg_addr: register address
5149  * @reg_val: ptr to register value
5150  * @cmd_details: pointer to command details structure or NULL
5151  *
5152  * Use the firmware to read the Rx control register,
5153  * especially useful if the Rx unit is under heavy pressure
5154  **/
5155 i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
5156                                 u32 reg_addr, u32 *reg_val,
5157                                 struct i40e_asq_cmd_details *cmd_details)
5158 {
5159         struct i40e_aq_desc desc;
5160         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
5161                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
5162         i40e_status status;
5163
5164         if (!reg_val)
5165                 return I40E_ERR_PARAM;
5166
5167         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
5168
5169         cmd_resp->address = cpu_to_le32(reg_addr);
5170
5171         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5172
5173         if (status == 0)
5174                 *reg_val = le32_to_cpu(cmd_resp->value);
5175
5176         return status;
5177 }
5178
5179 /**
5180  * i40e_read_rx_ctl - read from an Rx control register
5181  * @hw: pointer to the hw struct
5182  * @reg_addr: register address
5183  **/
5184 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
5185 {
5186         i40e_status status = 0;
5187         bool use_register;
5188         int retry = 5;
5189         u32 val = 0;
5190
5191         use_register = (((hw->aq.api_maj_ver == 1) &&
5192                         (hw->aq.api_min_ver < 5)) ||
5193                         (hw->mac.type == I40E_MAC_X722));
5194         if (!use_register) {
5195 do_retry:
5196                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
5197                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
5198                         usleep_range(1000, 2000);
5199                         retry--;
5200                         goto do_retry;
5201                 }
5202         }
5203
5204         /* if the AQ access failed, try the old-fashioned way */
5205         if (status || use_register)
5206                 val = rd32(hw, reg_addr);
5207
5208         return val;
5209 }
5210
5211 /**
5212  * i40e_aq_rx_ctl_write_register
5213  * @hw: pointer to the hw struct
5214  * @reg_addr: register address
5215  * @reg_val: register value
5216  * @cmd_details: pointer to command details structure or NULL
5217  *
5218  * Use the firmware to write to an Rx control register,
5219  * especially useful if the Rx unit is under heavy pressure
5220  **/
5221 i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
5222                                 u32 reg_addr, u32 reg_val,
5223                                 struct i40e_asq_cmd_details *cmd_details)
5224 {
5225         struct i40e_aq_desc desc;
5226         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
5227                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
5228         i40e_status status;
5229
5230         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
5231
5232         cmd->address = cpu_to_le32(reg_addr);
5233         cmd->value = cpu_to_le32(reg_val);
5234
5235         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5236
5237         return status;
5238 }
5239
5240 /**
5241  * i40e_write_rx_ctl - write to an Rx control register
5242  * @hw: pointer to the hw struct
5243  * @reg_addr: register address
5244  * @reg_val: register value
5245  **/
5246 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
5247 {
5248         i40e_status status = 0;
5249         bool use_register;
5250         int retry = 5;
5251
5252         use_register = (((hw->aq.api_maj_ver == 1) &&
5253                         (hw->aq.api_min_ver < 5)) ||
5254                         (hw->mac.type == I40E_MAC_X722));
5255         if (!use_register) {
5256 do_retry:
5257                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
5258                                                        reg_val, NULL);
5259                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
5260                         usleep_range(1000, 2000);
5261                         retry--;
5262                         goto do_retry;
5263                 }
5264         }
5265
5266         /* if the AQ access failed, try the old-fashioned way */
5267         if (status || use_register)
5268                 wr32(hw, reg_addr, reg_val);
5269 }
5270
5271 /**
5272  * i40e_aq_set_phy_register
5273  * @hw: pointer to the hw struct
5274  * @phy_select: select which phy should be accessed
5275  * @dev_addr: PHY device address
5276  * @reg_addr: PHY register address
5277  * @reg_val: new register value
5278  * @cmd_details: pointer to command details structure or NULL
5279  *
5280  * Write the external PHY register.
5281  **/
5282 i40e_status i40e_aq_set_phy_register(struct i40e_hw *hw,
5283                                      u8 phy_select, u8 dev_addr,
5284                                      u32 reg_addr, u32 reg_val,
5285                                      struct i40e_asq_cmd_details *cmd_details)
5286 {
5287         struct i40e_aq_desc desc;
5288         struct i40e_aqc_phy_register_access *cmd =
5289                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
5290         i40e_status status;
5291
5292         i40e_fill_default_direct_cmd_desc(&desc,
5293                                           i40e_aqc_opc_set_phy_register);
5294
5295         cmd->phy_interface = phy_select;
5296         cmd->dev_address = dev_addr;
5297         cmd->reg_address = cpu_to_le32(reg_addr);
5298         cmd->reg_value = cpu_to_le32(reg_val);
5299
5300         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5301
5302         return status;
5303 }
5304
5305 /**
5306  * i40e_aq_get_phy_register
5307  * @hw: pointer to the hw struct
5308  * @phy_select: select which phy should be accessed
5309  * @dev_addr: PHY device address
5310  * @reg_addr: PHY register address
5311  * @reg_val: read register value
5312  * @cmd_details: pointer to command details structure or NULL
5313  *
5314  * Read the external PHY register.
5315  **/
5316 i40e_status i40e_aq_get_phy_register(struct i40e_hw *hw,
5317                                      u8 phy_select, u8 dev_addr,
5318                                      u32 reg_addr, u32 *reg_val,
5319                                      struct i40e_asq_cmd_details *cmd_details)
5320 {
5321         struct i40e_aq_desc desc;
5322         struct i40e_aqc_phy_register_access *cmd =
5323                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
5324         i40e_status status;
5325
5326         i40e_fill_default_direct_cmd_desc(&desc,
5327                                           i40e_aqc_opc_get_phy_register);
5328
5329         cmd->phy_interface = phy_select;
5330         cmd->dev_address = dev_addr;
5331         cmd->reg_address = cpu_to_le32(reg_addr);
5332
5333         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5334         if (!status)
5335                 *reg_val = le32_to_cpu(cmd->reg_value);
5336
5337         return status;
5338 }
5339
5340 /**
5341  * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
5342  * @hw: pointer to the hw struct
5343  * @buff: command buffer (size in bytes = buff_size)
5344  * @buff_size: buffer size in bytes
5345  * @track_id: package tracking id
5346  * @error_offset: returns error offset
5347  * @error_info: returns error information
5348  * @cmd_details: pointer to command details structure or NULL
5349  **/
5350 enum
5351 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
5352                                    u16 buff_size, u32 track_id,
5353                                    u32 *error_offset, u32 *error_info,
5354                                    struct i40e_asq_cmd_details *cmd_details)
5355 {
5356         struct i40e_aq_desc desc;
5357         struct i40e_aqc_write_personalization_profile *cmd =
5358                 (struct i40e_aqc_write_personalization_profile *)
5359                 &desc.params.raw;
5360         struct i40e_aqc_write_ddp_resp *resp;
5361         i40e_status status;
5362
5363         i40e_fill_default_direct_cmd_desc(&desc,
5364                                           i40e_aqc_opc_write_personalization_profile);
5365
5366         desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
5367         if (buff_size > I40E_AQ_LARGE_BUF)
5368                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5369
5370         desc.datalen = cpu_to_le16(buff_size);
5371
5372         cmd->profile_track_id = cpu_to_le32(track_id);
5373
5374         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5375         if (!status) {
5376                 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
5377                 if (error_offset)
5378                         *error_offset = le32_to_cpu(resp->error_offset);
5379                 if (error_info)
5380                         *error_info = le32_to_cpu(resp->error_info);
5381         }
5382
5383         return status;
5384 }
5385
5386 /**
5387  * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
5388  * @hw: pointer to the hw struct
5389  * @buff: command buffer (size in bytes = buff_size)
5390  * @buff_size: buffer size in bytes
5391  * @flags: AdminQ command flags
5392  * @cmd_details: pointer to command details structure or NULL
5393  **/
5394 enum
5395 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
5396                                       u16 buff_size, u8 flags,
5397                                       struct i40e_asq_cmd_details *cmd_details)
5398 {
5399         struct i40e_aq_desc desc;
5400         struct i40e_aqc_get_applied_profiles *cmd =
5401                 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
5402         i40e_status status;
5403
5404         i40e_fill_default_direct_cmd_desc(&desc,
5405                                           i40e_aqc_opc_get_personalization_profile_list);
5406
5407         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
5408         if (buff_size > I40E_AQ_LARGE_BUF)
5409                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5410         desc.datalen = cpu_to_le16(buff_size);
5411
5412         cmd->flags = flags;
5413
5414         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5415
5416         return status;
5417 }
5418
5419 /**
5420  * i40e_find_segment_in_package
5421  * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
5422  * @pkg_hdr: pointer to the package header to be searched
5423  *
5424  * This function searches a package file for a particular segment type. On
5425  * success it returns a pointer to the segment header, otherwise it will
5426  * return NULL.
5427  **/
5428 struct i40e_generic_seg_header *
5429 i40e_find_segment_in_package(u32 segment_type,
5430                              struct i40e_package_header *pkg_hdr)
5431 {
5432         struct i40e_generic_seg_header *segment;
5433         u32 i;
5434
5435         /* Search all package segments for the requested segment type */
5436         for (i = 0; i < pkg_hdr->segment_count; i++) {
5437                 segment =
5438                         (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
5439                          pkg_hdr->segment_offset[i]);
5440
5441                 if (segment->type == segment_type)
5442                         return segment;
5443         }
5444
5445         return NULL;
5446 }
5447
5448 /**
5449  * i40e_write_profile
5450  * @hw: pointer to the hardware structure
5451  * @profile: pointer to the profile segment of the package to be downloaded
5452  * @track_id: package tracking id
5453  *
5454  * Handles the download of a complete package.
5455  */
5456 enum i40e_status_code
5457 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5458                    u32 track_id)
5459 {
5460         i40e_status status = 0;
5461         struct i40e_section_table *sec_tbl;
5462         struct i40e_profile_section_header *sec = NULL;
5463         u32 dev_cnt;
5464         u32 vendor_dev_id;
5465         u32 *nvm;
5466         u32 section_size = 0;
5467         u32 offset = 0, info = 0;
5468         u32 i;
5469
5470         dev_cnt = profile->device_table_count;
5471
5472         for (i = 0; i < dev_cnt; i++) {
5473                 vendor_dev_id = profile->device_table[i].vendor_dev_id;
5474                 if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL)
5475                         if (hw->device_id == (vendor_dev_id & 0xFFFF))
5476                                 break;
5477         }
5478         if (i == dev_cnt) {
5479                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Device doesn't support DDP");
5480                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
5481         }
5482
5483         nvm = (u32 *)&profile->device_table[dev_cnt];
5484         sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1];
5485
5486         for (i = 0; i < sec_tbl->section_count; i++) {
5487                 sec = (struct i40e_profile_section_header *)((u8 *)profile +
5488                                              sec_tbl->section_offset[i]);
5489
5490                 /* Skip 'AQ', 'note' and 'name' sections */
5491                 if (sec->section.type != SECTION_TYPE_MMIO)
5492                         continue;
5493
5494                 section_size = sec->section.size +
5495                         sizeof(struct i40e_profile_section_header);
5496
5497                 /* Write profile */
5498                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
5499                                            track_id, &offset, &info, NULL);
5500                 if (status) {
5501                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
5502                                    "Failed to write profile: offset %d, info %d",
5503                                    offset, info);
5504                         break;
5505                 }
5506         }
5507         return status;
5508 }
5509
5510 /**
5511  * i40e_add_pinfo_to_list
5512  * @hw: pointer to the hardware structure
5513  * @profile: pointer to the profile segment of the package
5514  * @profile_info_sec: buffer for information section
5515  * @track_id: package tracking id
5516  *
5517  * Register a profile to the list of loaded profiles.
5518  */
5519 enum i40e_status_code
5520 i40e_add_pinfo_to_list(struct i40e_hw *hw,
5521                        struct i40e_profile_segment *profile,
5522                        u8 *profile_info_sec, u32 track_id)
5523 {
5524         i40e_status status = 0;
5525         struct i40e_profile_section_header *sec = NULL;
5526         struct i40e_profile_info *pinfo;
5527         u32 offset = 0, info = 0;
5528
5529         sec = (struct i40e_profile_section_header *)profile_info_sec;
5530         sec->tbl_size = 1;
5531         sec->data_end = sizeof(struct i40e_profile_section_header) +
5532                         sizeof(struct i40e_profile_info);
5533         sec->section.type = SECTION_TYPE_INFO;
5534         sec->section.offset = sizeof(struct i40e_profile_section_header);
5535         sec->section.size = sizeof(struct i40e_profile_info);
5536         pinfo = (struct i40e_profile_info *)(profile_info_sec +
5537                                              sec->section.offset);
5538         pinfo->track_id = track_id;
5539         pinfo->version = profile->version;
5540         pinfo->op = I40E_DDP_ADD_TRACKID;
5541         memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE);
5542
5543         status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
5544                                    track_id, &offset, &info, NULL);
5545
5546         return status;
5547 }
5548
5549 /**
5550  * i40e_aq_add_cloud_filters
5551  * @hw: pointer to the hardware structure
5552  * @seid: VSI seid to add cloud filters from
5553  * @filters: Buffer which contains the filters to be added
5554  * @filter_count: number of filters contained in the buffer
5555  *
5556  * Set the cloud filters for a given VSI.  The contents of the
5557  * i40e_aqc_cloud_filters_element_data are filled in by the caller
5558  * of the function.
5559  *
5560  **/
5561 enum i40e_status_code
5562 i40e_aq_add_cloud_filters(struct i40e_hw *hw, u16 seid,
5563                           struct i40e_aqc_cloud_filters_element_data *filters,
5564                           u8 filter_count)
5565 {
5566         struct i40e_aq_desc desc;
5567         struct i40e_aqc_add_remove_cloud_filters *cmd =
5568         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5569         enum i40e_status_code status;
5570         u16 buff_len;
5571
5572         i40e_fill_default_direct_cmd_desc(&desc,
5573                                           i40e_aqc_opc_add_cloud_filters);
5574
5575         buff_len = filter_count * sizeof(*filters);
5576         desc.datalen = cpu_to_le16(buff_len);
5577         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5578         cmd->num_filters = filter_count;
5579         cmd->seid = cpu_to_le16(seid);
5580
5581         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5582
5583         return status;
5584 }
5585
5586 /**
5587  * i40e_aq_add_cloud_filters_bb
5588  * @hw: pointer to the hardware structure
5589  * @seid: VSI seid to add cloud filters from
5590  * @filters: Buffer which contains the filters in big buffer to be added
5591  * @filter_count: number of filters contained in the buffer
5592  *
5593  * Set the big buffer cloud filters for a given VSI.  The contents of the
5594  * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5595  * function.
5596  *
5597  **/
5598 enum i40e_status_code
5599 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5600                              struct i40e_aqc_cloud_filters_element_bb *filters,
5601                              u8 filter_count)
5602 {
5603         struct i40e_aq_desc desc;
5604         struct i40e_aqc_add_remove_cloud_filters *cmd =
5605         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5606         i40e_status status;
5607         u16 buff_len;
5608         int i;
5609
5610         i40e_fill_default_direct_cmd_desc(&desc,
5611                                           i40e_aqc_opc_add_cloud_filters);
5612
5613         buff_len = filter_count * sizeof(*filters);
5614         desc.datalen = cpu_to_le16(buff_len);
5615         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5616         cmd->num_filters = filter_count;
5617         cmd->seid = cpu_to_le16(seid);
5618         cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5619
5620         for (i = 0; i < filter_count; i++) {
5621                 u16 tnl_type;
5622                 u32 ti;
5623
5624                 tnl_type = (le16_to_cpu(filters[i].element.flags) &
5625                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5626                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5627
5628                 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5629                  * one more byte further than normally used for Tenant ID in
5630                  * other tunnel types.
5631                  */
5632                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5633                         ti = le32_to_cpu(filters[i].element.tenant_id);
5634                         filters[i].element.tenant_id = cpu_to_le32(ti << 8);
5635                 }
5636         }
5637
5638         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5639
5640         return status;
5641 }
5642
5643 /**
5644  * i40e_aq_rem_cloud_filters
5645  * @hw: pointer to the hardware structure
5646  * @seid: VSI seid to remove cloud filters from
5647  * @filters: Buffer which contains the filters to be removed
5648  * @filter_count: number of filters contained in the buffer
5649  *
5650  * Remove the cloud filters for a given VSI.  The contents of the
5651  * i40e_aqc_cloud_filters_element_data are filled in by the caller
5652  * of the function.
5653  *
5654  **/
5655 enum i40e_status_code
5656 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
5657                           struct i40e_aqc_cloud_filters_element_data *filters,
5658                           u8 filter_count)
5659 {
5660         struct i40e_aq_desc desc;
5661         struct i40e_aqc_add_remove_cloud_filters *cmd =
5662         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5663         enum i40e_status_code status;
5664         u16 buff_len;
5665
5666         i40e_fill_default_direct_cmd_desc(&desc,
5667                                           i40e_aqc_opc_remove_cloud_filters);
5668
5669         buff_len = filter_count * sizeof(*filters);
5670         desc.datalen = cpu_to_le16(buff_len);
5671         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5672         cmd->num_filters = filter_count;
5673         cmd->seid = cpu_to_le16(seid);
5674
5675         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5676
5677         return status;
5678 }
5679
5680 /**
5681  * i40e_aq_rem_cloud_filters_bb
5682  * @hw: pointer to the hardware structure
5683  * @seid: VSI seid to remove cloud filters from
5684  * @filters: Buffer which contains the filters in big buffer to be removed
5685  * @filter_count: number of filters contained in the buffer
5686  *
5687  * Remove the big buffer cloud filters for a given VSI.  The contents of the
5688  * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5689  * function.
5690  *
5691  **/
5692 enum i40e_status_code
5693 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5694                              struct i40e_aqc_cloud_filters_element_bb *filters,
5695                              u8 filter_count)
5696 {
5697         struct i40e_aq_desc desc;
5698         struct i40e_aqc_add_remove_cloud_filters *cmd =
5699         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5700         i40e_status status;
5701         u16 buff_len;
5702         int i;
5703
5704         i40e_fill_default_direct_cmd_desc(&desc,
5705                                           i40e_aqc_opc_remove_cloud_filters);
5706
5707         buff_len = filter_count * sizeof(*filters);
5708         desc.datalen = cpu_to_le16(buff_len);
5709         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5710         cmd->num_filters = filter_count;
5711         cmd->seid = cpu_to_le16(seid);
5712         cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5713
5714         for (i = 0; i < filter_count; i++) {
5715                 u16 tnl_type;
5716                 u32 ti;
5717
5718                 tnl_type = (le16_to_cpu(filters[i].element.flags) &
5719                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5720                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5721
5722                 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5723                  * one more byte further than normally used for Tenant ID in
5724                  * other tunnel types.
5725                  */
5726                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5727                         ti = le32_to_cpu(filters[i].element.tenant_id);
5728                         filters[i].element.tenant_id = cpu_to_le32(ti << 8);
5729                 }
5730         }
5731
5732         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5733
5734         return status;
5735 }