drivers/net/ethernet/intel/e1000e/ich8lan.c

   1 /* Intel PRO/1000 Linux driver
   2  * Copyright(c) 1999 - 2015 Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * The full GNU General Public License is included in this distribution in
  14  * the file called "COPYING".
  15  *
  16  * Contact Information:
  17  * Linux NICS <linux.nics@intel.com>
  18  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  19  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  20  */
  21
  22 /* 82562G 10/100 Network Connection
  23  * 82562G-2 10/100 Network Connection
  24  * 82562GT 10/100 Network Connection
  25  * 82562GT-2 10/100 Network Connection
  26  * 82562V 10/100 Network Connection
  27  * 82562V-2 10/100 Network Connection
  28  * 82566DC-2 Gigabit Network Connection
  29  * 82566DC Gigabit Network Connection
  30  * 82566DM-2 Gigabit Network Connection
  31  * 82566DM Gigabit Network Connection
  32  * 82566MC Gigabit Network Connection
  33  * 82566MM Gigabit Network Connection
  34  * 82567LM Gigabit Network Connection
  35  * 82567LF Gigabit Network Connection
  36  * 82567V Gigabit Network Connection
  37  * 82567LM-2 Gigabit Network Connection
  38  * 82567LF-2 Gigabit Network Connection
  39  * 82567V-2 Gigabit Network Connection
  40  * 82567LF-3 Gigabit Network Connection
  41  * 82567LM-3 Gigabit Network Connection
  42  * 82567LM-4 Gigabit Network Connection
  43  * 82577LM Gigabit Network Connection
  44  * 82577LC Gigabit Network Connection
  45  * 82578DM Gigabit Network Connection
  46  * 82578DC Gigabit Network Connection
  47  * 82579LM Gigabit Network Connection
  48  * 82579V Gigabit Network Connection
  49  * Ethernet Connection I217-LM
  50  * Ethernet Connection I217-V
  51  * Ethernet Connection I218-V
  52  * Ethernet Connection I218-LM
  53  * Ethernet Connection (2) I218-LM
  54  * Ethernet Connection (2) I218-V
  55  * Ethernet Connection (3) I218-LM
  56  * Ethernet Connection (3) I218-V
  57  */
  58
  59 #include "e1000.h"
  60
  61 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
  62 /* Offset 04h HSFSTS */
  63 union ich8_hws_flash_status {
  64         struct ich8_hsfsts {
  65                 u16 flcdone:1;  /* bit 0 Flash Cycle Done */
  66                 u16 flcerr:1;   /* bit 1 Flash Cycle Error */
  67                 u16 dael:1;     /* bit 2 Direct Access error Log */
  68                 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
  69                 u16 flcinprog:1;        /* bit 5 flash cycle in Progress */
  70                 u16 reserved1:2;        /* bit 13:6 Reserved */
  71                 u16 reserved2:6;        /* bit 13:6 Reserved */
  72                 u16 fldesvalid:1;       /* bit 14 Flash Descriptor Valid */
  73                 u16 flockdn:1;  /* bit 15 Flash Config Lock-Down */
  74         } hsf_status;
  75         u16 regval;
  76 };
  77
  78 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
  79 /* Offset 06h FLCTL */
  80 union ich8_hws_flash_ctrl {
  81         struct ich8_hsflctl {
  82                 u16 flcgo:1;    /* 0 Flash Cycle Go */
  83                 u16 flcycle:2;  /* 2:1 Flash Cycle */
  84                 u16 reserved:5; /* 7:3 Reserved  */
  85                 u16 fldbcount:2;        /* 9:8 Flash Data Byte Count */
  86                 u16 flockdn:6;  /* 15:10 Reserved */
  87         } hsf_ctrl;
  88         u16 regval;
  89 };
  90
  91 /* ICH Flash Region Access Permissions */
  92 union ich8_hws_flash_regacc {
  93         struct ich8_flracc {
  94                 u32 grra:8;     /* 0:7 GbE region Read Access */
  95                 u32 grwa:8;     /* 8:15 GbE region Write Access */
  96                 u32 gmrag:8;    /* 23:16 GbE Master Read Access Grant */
  97                 u32 gmwag:8;    /* 31:24 GbE Master Write Access Grant */
  98         } hsf_flregacc;
  99         u16 regval;
 100 };
 101
 102 /* ICH Flash Protected Region */
 103 union ich8_flash_protected_range {
 104         struct ich8_pr {
 105                 u32 base:13;    /* 0:12 Protected Range Base */
 106                 u32 reserved1:2;        /* 13:14 Reserved */
 107                 u32 rpe:1;      /* 15 Read Protection Enable */
 108                 u32 limit:13;   /* 16:28 Protected Range Limit */
 109                 u32 reserved2:2;        /* 29:30 Reserved */
 110                 u32 wpe:1;      /* 31 Write Protection Enable */
 111         } range;
 112         u32 regval;
 113 };
 114
 115 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 116 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 117 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 118 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 119                                                 u32 offset, u8 byte);
 120 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 121                                          u8 *data);
 122 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 123                                          u16 *data);
 124 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 125                                          u8 size, u16 *data);
 126 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
 127                                            u32 *data);
 128 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
 129                                           u32 offset, u32 *data);
 130 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
 131                                             u32 offset, u32 data);
 132 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
 133                                                  u32 offset, u32 dword);
 134 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 135 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 136 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 137 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 138 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 139 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 140 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 141 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 142 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 143 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 144 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 145 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 146 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 147 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 148 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 149 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 150 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
 151 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
 152 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw);
 153 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 154 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 155 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
 156 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
 157 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
 158
 159 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 160 {
 161         return readw(hw->flash_address + reg);
 162 }
 163
 164 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 165 {
 166         return readl(hw->flash_address + reg);
 167 }
 168
 169 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 170 {
 171         writew(val, hw->flash_address + reg);
 172 }
 173
 174 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 175 {
 176         writel(val, hw->flash_address + reg);
 177 }
 178
 179 #define er16flash(reg)          __er16flash(hw, (reg))
 180 #define er32flash(reg)          __er32flash(hw, (reg))
 181 #define ew16flash(reg, val)     __ew16flash(hw, (reg), (val))
 182 #define ew32flash(reg, val)     __ew32flash(hw, (reg), (val))
 183
 184 /**
 185  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 186  *  @hw: pointer to the HW structure
 187  *
 188  *  Test access to the PHY registers by reading the PHY ID registers.  If
 189  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 190  *  otherwise assume the read PHY ID is correct if it is valid.
 191  *
 192  *  Assumes the sw/fw/hw semaphore is already acquired.
 193  **/
 194 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 195 {
 196         u16 phy_reg = 0;
 197         u32 phy_id = 0;
 198         s32 ret_val = 0;
 199         u16 retry_count;
 200         u32 mac_reg = 0;
 201
 202         for (retry_count = 0; retry_count < 2; retry_count++) {
 203                 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
 204                 if (ret_val || (phy_reg == 0xFFFF))
 205                         continue;
 206                 phy_id = (u32)(phy_reg << 16);
 207
 208                 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
 209                 if (ret_val || (phy_reg == 0xFFFF)) {
 210                         phy_id = 0;
 211                         continue;
 212                 }
 213                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 214                 break;
 215         }
 216
 217         if (hw->phy.id) {
 218                 if (hw->phy.id == phy_id)
 219                         goto out;
 220         } else if (phy_id) {
 221                 hw->phy.id = phy_id;
 222                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 223                 goto out;
 224         }
 225
 226         /* In case the PHY needs to be in mdio slow mode,
 227          * set slow mode and try to get the PHY id again.
 228          */
 229         if (hw->mac.type < e1000_pch_lpt) {
 230                 hw->phy.ops.release(hw);
 231                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 232                 if (!ret_val)
 233                         ret_val = e1000e_get_phy_id(hw);
 234                 hw->phy.ops.acquire(hw);
 235         }
 236
 237         if (ret_val)
 238                 return false;
 239 out:
 240         if ((hw->mac.type == e1000_pch_lpt) || (hw->mac.type == e1000_pch_spt)) {
 241                 /* Only unforce SMBus if ME is not active */
 242                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
 243                         /* Unforce SMBus mode in PHY */
 244                         e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
 245                         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
 246                         e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
 247
 248                         /* Unforce SMBus mode in MAC */
 249                         mac_reg = er32(CTRL_EXT);
 250                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 251                         ew32(CTRL_EXT, mac_reg);
 252                 }
 253         }
 254
 255         return true;
 256 }
 257
 258 /**
 259  *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
 260  *  @hw: pointer to the HW structure
 261  *
 262  *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
 263  *  used to reset the PHY to a quiescent state when necessary.
 264  **/
 265 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
 266 {
 267         u32 mac_reg;
 268
 269         /* Set Phy Config Counter to 50msec */
 270         mac_reg = er32(FEXTNVM3);
 271         mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 272         mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 273         ew32(FEXTNVM3, mac_reg);
 274
 275         /* Toggle LANPHYPC Value bit */
 276         mac_reg = er32(CTRL);
 277         mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 278         mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 279         ew32(CTRL, mac_reg);
 280         e1e_flush();
 281         usleep_range(10, 20);
 282         mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 283         ew32(CTRL, mac_reg);
 284         e1e_flush();
 285
 286         if (hw->mac.type < e1000_pch_lpt) {
 287                 msleep(50);
 288         } else {
 289                 u16 count = 20;
 290
 291                 do {
 292                         usleep_range(5000, 10000);
 293                 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);
 294
 295                 msleep(30);
 296         }
 297 }
 298
 299 /**
 300  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 301  *  @hw: pointer to the HW structure
 302  *
 303  *  Workarounds/flow necessary for PHY initialization during driver load
 304  *  and resume paths.
 305  **/
 306 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 307 {
 308         struct e1000_adapter *adapter = hw->adapter;
 309         u32 mac_reg, fwsm = er32(FWSM);
 310         s32 ret_val;
 311
 312         /* Gate automatic PHY configuration by hardware on managed and
 313          * non-managed 82579 and newer adapters.
 314          */
 315         e1000_gate_hw_phy_config_ich8lan(hw, true);
 316
 317         /* It is not possible to be certain of the current state of ULP
 318          * so forcibly disable it.
 319          */
 320         hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
 321         e1000_disable_ulp_lpt_lp(hw, true);
 322
 323         ret_val = hw->phy.ops.acquire(hw);
 324         if (ret_val) {
 325                 e_dbg("Failed to initialize PHY flow\n");
 326                 goto out;
 327         }
 328
 329         /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 330          * inaccessible and resetting the PHY is not blocked, toggle the
 331          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 332          */
 333         switch (hw->mac.type) {
 334         case e1000_pch_lpt:
 335         case e1000_pch_spt:
 336                 if (e1000_phy_is_accessible_pchlan(hw))
 337                         break;
 338
 339                 /* Before toggling LANPHYPC, see if PHY is accessible by
 340                  * forcing MAC to SMBus mode first.
 341                  */
 342                 mac_reg = er32(CTRL_EXT);
 343                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
 344                 ew32(CTRL_EXT, mac_reg);
 345
 346                 /* Wait 50 milliseconds for MAC to finish any retries
 347                  * that it might be trying to perform from previous
 348                  * attempts to acknowledge any phy read requests.
 349                  */
 350                 msleep(50);
 351
 352                 /* fall-through */
 353         case e1000_pch2lan:
 354                 if (e1000_phy_is_accessible_pchlan(hw))
 355                         break;
 356
 357                 /* fall-through */
 358         case e1000_pchlan:
 359                 if ((hw->mac.type == e1000_pchlan) &&
 360                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 361                         break;
 362
 363                 if (hw->phy.ops.check_reset_block(hw)) {
 364                         e_dbg("Required LANPHYPC toggle blocked by ME\n");
 365                         ret_val = -E1000_ERR_PHY;
 366                         break;
 367                 }
 368
 369                 /* Toggle LANPHYPC Value bit */
 370                 e1000_toggle_lanphypc_pch_lpt(hw);
 371                 if (hw->mac.type >= e1000_pch_lpt) {
 372                         if (e1000_phy_is_accessible_pchlan(hw))
 373                                 break;
 374
 375                         /* Toggling LANPHYPC brings the PHY out of SMBus mode
 376                          * so ensure that the MAC is also out of SMBus mode
 377                          */
 378                         mac_reg = er32(CTRL_EXT);
 379                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 380                         ew32(CTRL_EXT, mac_reg);
 381
 382                         if (e1000_phy_is_accessible_pchlan(hw))
 383                                 break;
 384
 385                         ret_val = -E1000_ERR_PHY;
 386                 }
 387                 break;
 388         default:
 389                 break;
 390         }
 391
 392         hw->phy.ops.release(hw);
 393         if (!ret_val) {
 394
 395                 /* Check to see if able to reset PHY.  Print error if not */
 396                 if (hw->phy.ops.check_reset_block(hw)) {
 397                         e_err("Reset blocked by ME\n");
 398                         goto out;
 399                 }
 400
 401                 /* Reset the PHY before any access to it.  Doing so, ensures
 402                  * that the PHY is in a known good state before we read/write
 403                  * PHY registers.  The generic reset is sufficient here,
 404                  * because we haven't determined the PHY type yet.
 405                  */
 406                 ret_val = e1000e_phy_hw_reset_generic(hw);
 407                 if (ret_val)
 408                         goto out;
 409
 410                 /* On a successful reset, possibly need to wait for the PHY
 411                  * to quiesce to an accessible state before returning control
 412                  * to the calling function.  If the PHY does not quiesce, then
 413                  * return E1000E_BLK_PHY_RESET, as this is the condition that
 414                  *  the PHY is in.
 415                  */
 416                 ret_val = hw->phy.ops.check_reset_block(hw);
 417                 if (ret_val)
 418                         e_err("ME blocked access to PHY after reset\n");
 419         }
 420
 421 out:
 422         /* Ungate automatic PHY configuration on non-managed 82579 */
 423         if ((hw->mac.type == e1000_pch2lan) &&
 424             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 425                 usleep_range(10000, 20000);
 426                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 427         }
 428
 429         return ret_val;
 430 }
 431
 432 /**
 433  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 434  *  @hw: pointer to the HW structure
 435  *
 436  *  Initialize family-specific PHY parameters and function pointers.
 437  **/
 438 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 439 {
 440         struct e1000_phy_info *phy = &hw->phy;
 441         s32 ret_val;
 442
 443         phy->addr = 1;
 444         phy->reset_delay_us = 100;
 445
 446         phy->ops.set_page = e1000_set_page_igp;
 447         phy->ops.read_reg = e1000_read_phy_reg_hv;
 448         phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
 449         phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
 450         phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
 451         phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
 452         phy->ops.write_reg = e1000_write_phy_reg_hv;
 453         phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
 454         phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
 455         phy->ops.power_up = e1000_power_up_phy_copper;
 456         phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
 457         phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 458
 459         phy->id = e1000_phy_unknown;
 460
 461         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 462         if (ret_val)
 463                 return ret_val;
 464
 465         if (phy->id == e1000_phy_unknown)
 466                 switch (hw->mac.type) {
 467                 default:
 468                         ret_val = e1000e_get_phy_id(hw);
 469                         if (ret_val)
 470                                 return ret_val;
 471                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 472                                 break;
 473                         /* fall-through */
 474                 case e1000_pch2lan:
 475                 case e1000_pch_lpt:
 476                 case e1000_pch_spt:
 477                         /* In case the PHY needs to be in mdio slow mode,
 478                          * set slow mode and try to get the PHY id again.
 479                          */
 480                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 481                         if (ret_val)
 482                                 return ret_val;
 483                         ret_val = e1000e_get_phy_id(hw);
 484                         if (ret_val)
 485                                 return ret_val;
 486                         break;
 487                 }
 488         phy->type = e1000e_get_phy_type_from_id(phy->id);
 489
 490         switch (phy->type) {
 491         case e1000_phy_82577:
 492         case e1000_phy_82579:
 493         case e1000_phy_i217:
 494                 phy->ops.check_polarity = e1000_check_polarity_82577;
 495                 phy->ops.force_speed_duplex =
 496                     e1000_phy_force_speed_duplex_82577;
 497                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 498                 phy->ops.get_info = e1000_get_phy_info_82577;
 499                 phy->ops.commit = e1000e_phy_sw_reset;
 500                 break;
 501         case e1000_phy_82578:
 502                 phy->ops.check_polarity = e1000_check_polarity_m88;
 503                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 504                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 505                 phy->ops.get_info = e1000e_get_phy_info_m88;
 506                 break;
 507         default:
 508                 ret_val = -E1000_ERR_PHY;
 509                 break;
 510         }
 511
 512         return ret_val;
 513 }
 514
 515 /**
 516  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 517  *  @hw: pointer to the HW structure
 518  *
 519  *  Initialize family-specific PHY parameters and function pointers.
 520  **/
 521 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 522 {
 523         struct e1000_phy_info *phy = &hw->phy;
 524         s32 ret_val;
 525         u16 i = 0;
 526
 527         phy->addr = 1;
 528         phy->reset_delay_us = 100;
 529
 530         phy->ops.power_up = e1000_power_up_phy_copper;
 531         phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
 532
 533         /* We may need to do this twice - once for IGP and if that fails,
 534          * we'll set BM func pointers and try again
 535          */
 536         ret_val = e1000e_determine_phy_address(hw);
 537         if (ret_val) {
 538                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 539                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 540                 ret_val = e1000e_determine_phy_address(hw);
 541                 if (ret_val) {
 542                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 543                         return ret_val;
 544                 }
 545         }
 546
 547         phy->id = 0;
 548         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 549                (i++ < 100)) {
 550                 usleep_range(1000, 2000);
 551                 ret_val = e1000e_get_phy_id(hw);
 552                 if (ret_val)
 553                         return ret_val;
 554         }
 555
 556         /* Verify phy id */
 557         switch (phy->id) {
 558         case IGP03E1000_E_PHY_ID:
 559                 phy->type = e1000_phy_igp_3;
 560                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 561                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 562                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 563                 phy->ops.get_info = e1000e_get_phy_info_igp;
 564                 phy->ops.check_polarity = e1000_check_polarity_igp;
 565                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 566                 break;
 567         case IFE_E_PHY_ID:
 568         case IFE_PLUS_E_PHY_ID:
 569         case IFE_C_E_PHY_ID:
 570                 phy->type = e1000_phy_ife;
 571                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 572                 phy->ops.get_info = e1000_get_phy_info_ife;
 573                 phy->ops.check_polarity = e1000_check_polarity_ife;
 574                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 575                 break;
 576         case BME1000_E_PHY_ID:
 577                 phy->type = e1000_phy_bm;
 578                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 579                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 580                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 581                 phy->ops.commit = e1000e_phy_sw_reset;
 582                 phy->ops.get_info = e1000e_get_phy_info_m88;
 583                 phy->ops.check_polarity = e1000_check_polarity_m88;
 584                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 585                 break;
 586         default:
 587                 return -E1000_ERR_PHY;
 588         }
 589
 590         return 0;
 591 }
 592
 593 /**
 594  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 595  *  @hw: pointer to the HW structure
 596  *
 597  *  Initialize family-specific NVM parameters and function
 598  *  pointers.
 599  **/
 600 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 601 {
 602         struct e1000_nvm_info *nvm = &hw->nvm;
 603         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 604         u32 gfpreg, sector_base_addr, sector_end_addr;
 605         u16 i;
 606         u32 nvm_size;
 607
 608         nvm->type = e1000_nvm_flash_sw;
 609
 610         if (hw->mac.type == e1000_pch_spt) {
 611                 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
 612                  * STRAP register. This is because in SPT the GbE Flash region
 613                  * is no longer accessed through the flash registers. Instead,
 614                  * the mechanism has changed, and the Flash region access
 615                  * registers are now implemented in GbE memory space.
 616                  */
 617                 nvm->flash_base_addr = 0;
 618                 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1)
 619                     * NVM_SIZE_MULTIPLIER;
 620                 nvm->flash_bank_size = nvm_size / 2;
 621                 /* Adjust to word count */
 622                 nvm->flash_bank_size /= sizeof(u16);
 623                 /* Set the base address for flash register access */
 624                 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
 625         } else {
 626                 /* Can't read flash registers if register set isn't mapped. */
 627                 if (!hw->flash_address) {
 628                         e_dbg("ERROR: Flash registers not mapped\n");
 629                         return -E1000_ERR_CONFIG;
 630                 }
 631
 632                 gfpreg = er32flash(ICH_FLASH_GFPREG);
 633
 634                 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 635                  * Add 1 to sector_end_addr since this sector is included in
 636                  * the overall size.
 637                  */
 638                 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 639                 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 640
 641                 /* flash_base_addr is byte-aligned */
 642                 nvm->flash_base_addr = sector_base_addr
 643                     << FLASH_SECTOR_ADDR_SHIFT;
 644
 645                 /* find total size of the NVM, then cut in half since the total
 646                  * size represents two separate NVM banks.
 647                  */
 648                 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
 649                                         << FLASH_SECTOR_ADDR_SHIFT);
 650                 nvm->flash_bank_size /= 2;
 651                 /* Adjust to word count */
 652                 nvm->flash_bank_size /= sizeof(u16);
 653         }
 654
 655         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 656
 657         /* Clear shadow ram */
 658         for (i = 0; i < nvm->word_size; i++) {
 659                 dev_spec->shadow_ram[i].modified = false;
 660                 dev_spec->shadow_ram[i].value = 0xFFFF;
 661         }
 662
 663         return 0;
 664 }
 665
 666 /**
 667  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 668  *  @hw: pointer to the HW structure
 669  *
 670  *  Initialize family-specific MAC parameters and function
 671  *  pointers.
 672  **/
 673 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 674 {
 675         struct e1000_mac_info *mac = &hw->mac;
 676
 677         /* Set media type function pointer */
 678         hw->phy.media_type = e1000_media_type_copper;
 679
 680         /* Set mta register count */
 681         mac->mta_reg_count = 32;
 682         /* Set rar entry count */
 683         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 684         if (mac->type == e1000_ich8lan)
 685                 mac->rar_entry_count--;
 686         /* FWSM register */
 687         mac->has_fwsm = true;
 688         /* ARC subsystem not supported */
 689         mac->arc_subsystem_valid = false;
 690         /* Adaptive IFS supported */
 691         mac->adaptive_ifs = true;
 692
 693         /* LED and other operations */
 694         switch (mac->type) {
 695         case e1000_ich8lan:
 696         case e1000_ich9lan:
 697         case e1000_ich10lan:
 698                 /* check management mode */
 699                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 700                 /* ID LED init */
 701                 mac->ops.id_led_init = e1000e_id_led_init_generic;
 702                 /* blink LED */
 703                 mac->ops.blink_led = e1000e_blink_led_generic;
 704                 /* setup LED */
 705                 mac->ops.setup_led = e1000e_setup_led_generic;
 706                 /* cleanup LED */
 707                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 708                 /* turn on/off LED */
 709                 mac->ops.led_on = e1000_led_on_ich8lan;
 710                 mac->ops.led_off = e1000_led_off_ich8lan;
 711                 break;
 712         case e1000_pch2lan:
 713                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 714                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 715                 /* fall-through */
 716         case e1000_pch_lpt:
 717         case e1000_pch_spt:
 718         case e1000_pchlan:
 719                 /* check management mode */
 720                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 721                 /* ID LED init */
 722                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 723                 /* setup LED */
 724                 mac->ops.setup_led = e1000_setup_led_pchlan;
 725                 /* cleanup LED */
 726                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 727                 /* turn on/off LED */
 728                 mac->ops.led_on = e1000_led_on_pchlan;
 729                 mac->ops.led_off = e1000_led_off_pchlan;
 730                 break;
 731         default:
 732                 break;
 733         }
 734
 735         if ((mac->type == e1000_pch_lpt) || (mac->type == e1000_pch_spt)) {
 736                 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
 737                 mac->ops.rar_set = e1000_rar_set_pch_lpt;
 738                 mac->ops.setup_physical_interface =
 739                     e1000_setup_copper_link_pch_lpt;
 740                 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt;
 741         }
 742
 743         /* Enable PCS Lock-loss workaround for ICH8 */
 744         if (mac->type == e1000_ich8lan)
 745                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 746
 747         return 0;
 748 }
 749
 750 /**
 751  *  __e1000_access_emi_reg_locked - Read/write EMI register
 752  *  @hw: pointer to the HW structure
 753  *  @addr: EMI address to program
 754  *  @data: pointer to value to read/write from/to the EMI address
 755  *  @read: boolean flag to indicate read or write
 756  *
 757  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 758  **/
 759 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 760                                          u16 *data, bool read)
 761 {
 762         s32 ret_val;
 763
 764         ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
 765         if (ret_val)
 766                 return ret_val;
 767
 768         if (read)
 769                 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
 770         else
 771                 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
 772
 773         return ret_val;
 774 }
 775
 776 /**
 777  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 778  *  @hw: pointer to the HW structure
 779  *  @addr: EMI address to program
 780  *  @data: value to be read from the EMI address
 781  *
 782  *  Assumes the SW/FW/HW Semaphore is already acquired.
 783  **/
 784 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 785 {
 786         return __e1000_access_emi_reg_locked(hw, addr, data, true);
 787 }
 788
 789 /**
 790  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 791  *  @hw: pointer to the HW structure
 792  *  @addr: EMI address to program
 793  *  @data: value to be written to the EMI address
 794  *
 795  *  Assumes the SW/FW/HW Semaphore is already acquired.
 796  **/
 797 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 798 {
 799         return __e1000_access_emi_reg_locked(hw, addr, &data, false);
 800 }
 801
 802 /**
 803  *  e1000_set_eee_pchlan - Enable/disable EEE support
 804  *  @hw: pointer to the HW structure
 805  *
 806  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 807  *  the link and the EEE capabilities of the link partner.  The LPI Control
 808  *  register bits will remain set only if/when link is up.
 809  *
 810  *  EEE LPI must not be asserted earlier than one second after link is up.
 811  *  On 82579, EEE LPI should not be enabled until such time otherwise there
 812  *  can be link issues with some switches.  Other devices can have EEE LPI
 813  *  enabled immediately upon link up since they have a timer in hardware which
 814  *  prevents LPI from being asserted too early.
 815  **/
 816 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 817 {
 818         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 819         s32 ret_val;
 820         u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
 821
 822         switch (hw->phy.type) {
 823         case e1000_phy_82579:
 824                 lpa = I82579_EEE_LP_ABILITY;
 825                 pcs_status = I82579_EEE_PCS_STATUS;
 826                 adv_addr = I82579_EEE_ADVERTISEMENT;
 827                 break;
 828         case e1000_phy_i217:
 829                 lpa = I217_EEE_LP_ABILITY;
 830                 pcs_status = I217_EEE_PCS_STATUS;
 831                 adv_addr = I217_EEE_ADVERTISEMENT;
 832                 break;
 833         default:
 834                 return 0;
 835         }
 836
 837         ret_val = hw->phy.ops.acquire(hw);
 838         if (ret_val)
 839                 return ret_val;
 840
 841         ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 842         if (ret_val)
 843                 goto release;
 844
 845         /* Clear bits that enable EEE in various speeds */
 846         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 847
 848         /* Enable EEE if not disabled by user */
 849         if (!dev_spec->eee_disable) {
 850                 /* Save off link partner's EEE ability */
 851                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 852                                                     &dev_spec->eee_lp_ability);
 853                 if (ret_val)
 854                         goto release;
 855
 856                 /* Read EEE advertisement */
 857                 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
 858                 if (ret_val)
 859                         goto release;
 860
 861                 /* Enable EEE only for speeds in which the link partner is
 862                  * EEE capable and for which we advertise EEE.
 863                  */
 864                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 865                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 866
 867                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 868                         e1e_rphy_locked(hw, MII_LPA, &data);
 869                         if (data & LPA_100FULL)
 870                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 871                         else
 872                                 /* EEE is not supported in 100Half, so ignore
 873                                  * partner's EEE in 100 ability if full-duplex
 874                                  * is not advertised.
 875                                  */
 876                                 dev_spec->eee_lp_ability &=
 877                                     ~I82579_EEE_100_SUPPORTED;
 878                 }
 879         }
 880
 881         if (hw->phy.type == e1000_phy_82579) {
 882                 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 883                                                     &data);
 884                 if (ret_val)
 885                         goto release;
 886
 887                 data &= ~I82579_LPI_100_PLL_SHUT;
 888                 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 889                                                      data);
 890         }
 891
 892         /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 893         ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 894         if (ret_val)
 895                 goto release;
 896
 897         ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 898 release:
 899         hw->phy.ops.release(hw);
 900
 901         return ret_val;
 902 }
 903
 904 /**
 905  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
 906  *  @hw:   pointer to the HW structure
 907  *  @link: link up bool flag
 908  *
 909  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
 910  *  preventing further DMA write requests.  Workaround the issue by disabling
 911  *  the de-assertion of the clock request when in 1Gpbs mode.
 912  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
 913  *  speeds in order to avoid Tx hangs.
 914  **/
 915 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
 916 {
 917         u32 fextnvm6 = er32(FEXTNVM6);
 918         u32 status = er32(STATUS);
 919         s32 ret_val = 0;
 920         u16 reg;
 921
 922         if (link && (status & E1000_STATUS_SPEED_1000)) {
 923                 ret_val = hw->phy.ops.acquire(hw);
 924                 if (ret_val)
 925                         return ret_val;
 926
 927                 ret_val =
 928                     e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
 929                                                 &reg);
 930                 if (ret_val)
 931                         goto release;
 932
 933                 ret_val =
 934                     e1000e_write_kmrn_reg_locked(hw,
 935                                                  E1000_KMRNCTRLSTA_K1_CONFIG,
 936                                                  reg &
 937                                                  ~E1000_KMRNCTRLSTA_K1_ENABLE);
 938                 if (ret_val)
 939                         goto release;
 940
 941                 usleep_range(10, 20);
 942
 943                 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
 944
 945                 ret_val =
 946                     e1000e_write_kmrn_reg_locked(hw,
 947                                                  E1000_KMRNCTRLSTA_K1_CONFIG,
 948                                                  reg);
 949 release:
 950                 hw->phy.ops.release(hw);
 951         } else {
 952                 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
 953                 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
 954
 955                 if ((hw->phy.revision > 5) || !link ||
 956                     ((status & E1000_STATUS_SPEED_100) &&
 957                      (status & E1000_STATUS_FD)))
 958                         goto update_fextnvm6;
 959
 960                 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, &reg);
 961                 if (ret_val)
 962                         return ret_val;
 963
 964                 /* Clear link status transmit timeout */
 965                 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
 966
 967                 if (status & E1000_STATUS_SPEED_100) {
 968                         /* Set inband Tx timeout to 5x10us for 100Half */
 969                         reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
 970
 971                         /* Do not extend the K1 entry latency for 100Half */
 972                         fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
 973                 } else {
 974                         /* Set inband Tx timeout to 50x10us for 10Full/Half */
 975                         reg |= 50 <<
 976                             I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
 977
 978                         /* Extend the K1 entry latency for 10 Mbps */
 979                         fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
 980                 }
 981
 982                 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
 983                 if (ret_val)
 984                         return ret_val;
 985
 986 update_fextnvm6:
 987                 ew32(FEXTNVM6, fextnvm6);
 988         }
 989
 990         return ret_val;
 991 }
 992
 993 /**
 994  *  e1000_platform_pm_pch_lpt - Set platform power management values
 995  *  @hw: pointer to the HW structure
 996  *  @link: bool indicating link status
 997  *
 998  *  Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
 999  *  GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
1000  *  when link is up (which must not exceed the maximum latency supported
1001  *  by the platform), otherwise specify there is no LTR requirement.
1002  *  Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
1003  *  latencies in the LTR Extended Capability Structure in the PCIe Extended
1004  *  Capability register set, on this device LTR is set by writing the
1005  *  equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1006  *  set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1007  *  message to the PMC.
1008  **/
1009 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1010 {
1011         u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
1012             link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
1013         u16 lat_enc = 0;        /* latency encoded */
1014
1015         if (link) {
1016                 u16 speed, duplex, scale = 0;
1017                 u16 max_snoop, max_nosnoop;
1018                 u16 max_ltr_enc;        /* max LTR latency encoded */
1019                 u64 value;
1020                 u32 rxa;
1021
1022                 if (!hw->adapter->max_frame_size) {
1023                         e_dbg("max_frame_size not set.\n");
1024                         return -E1000_ERR_CONFIG;
1025                 }
1026
1027                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1028                 if (!speed) {
1029                         e_dbg("Speed not set.\n");
1030                         return -E1000_ERR_CONFIG;
1031                 }
1032
1033                 /* Rx Packet Buffer Allocation size (KB) */
1034                 rxa = er32(PBA) & E1000_PBA_RXA_MASK;
1035
1036                 /* Determine the maximum latency tolerated by the device.
1037                  *
1038                  * Per the PCIe spec, the tolerated latencies are encoded as
1039                  * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1040                  * a 10-bit value (0-1023) to provide a range from 1 ns to
1041                  * 2^25*(2^10-1) ns.  The scale is encoded as 0=2^0ns,
1042                  * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1043                  */
1044                 rxa *= 512;
1045                 value = (rxa > hw->adapter->max_frame_size) ?
1046                         (rxa - hw->adapter->max_frame_size) * (16000 / speed) :
1047                         0;
1048
1049                 while (value > PCI_LTR_VALUE_MASK) {
1050                         scale++;
1051                         value = DIV_ROUND_UP(value, BIT(5));
1052                 }
1053                 if (scale > E1000_LTRV_SCALE_MAX) {
1054                         e_dbg("Invalid LTR latency scale %d\n", scale);
1055                         return -E1000_ERR_CONFIG;
1056                 }
1057                 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
1058
1059                 /* Determine the maximum latency tolerated by the platform */
1060                 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
1061                                      &max_snoop);
1062                 pci_read_config_word(hw->adapter->pdev,
1063                                      E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1064                 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
1065
1066                 if (lat_enc > max_ltr_enc)
1067                         lat_enc = max_ltr_enc;
1068         }
1069
1070         /* Set Snoop and No-Snoop latencies the same */
1071         reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1072         ew32(LTRV, reg);
1073
1074         return 0;
1075 }
1076
1077 /**
1078  *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1079  *  @hw: pointer to the HW structure
1080  *  @to_sx: boolean indicating a system power state transition to Sx
1081  *
1082  *  When link is down, configure ULP mode to significantly reduce the power
1083  *  to the PHY.  If on a Manageability Engine (ME) enabled system, tell the
1084  *  ME firmware to start the ULP configuration.  If not on an ME enabled
1085  *  system, configure the ULP mode by software.
1086  */
1087 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1088 {
1089         u32 mac_reg;
1090         s32 ret_val = 0;
1091         u16 phy_reg;
1092         u16 oem_reg = 0;
1093
1094         if ((hw->mac.type < e1000_pch_lpt) ||
1095             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1096             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1097             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1098             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1099             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1100                 return 0;
1101
1102         if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1103                 /* Request ME configure ULP mode in the PHY */
1104                 mac_reg = er32(H2ME);
1105                 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1106                 ew32(H2ME, mac_reg);
1107
1108                 goto out;
1109         }
1110
1111         if (!to_sx) {
1112                 int i = 0;
1113
1114                 /* Poll up to 5 seconds for Cable Disconnected indication */
1115                 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1116                         /* Bail if link is re-acquired */
1117                         if (er32(STATUS) & E1000_STATUS_LU)
1118                                 return -E1000_ERR_PHY;
1119
1120                         if (i++ == 100)
1121                                 break;
1122
1123                         msleep(50);
1124                 }
1125                 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",
1126                       (er32(FEXT) &
1127                        E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50);
1128         }
1129
1130         ret_val = hw->phy.ops.acquire(hw);
1131         if (ret_val)
1132                 goto out;
1133
1134         /* Force SMBus mode in PHY */
1135         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1136         if (ret_val)
1137                 goto release;
1138         phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1139         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1140
1141         /* Force SMBus mode in MAC */
1142         mac_reg = er32(CTRL_EXT);
1143         mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1144         ew32(CTRL_EXT, mac_reg);
1145
1146         /* Si workaround for ULP entry flow on i127/rev6 h/w.  Enable
1147          * LPLU and disable Gig speed when entering ULP
1148          */
1149         if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1150                 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1151                                                        &oem_reg);
1152                 if (ret_val)
1153                         goto release;
1154
1155                 phy_reg = oem_reg;
1156                 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1157
1158                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1159                                                         phy_reg);
1160
1161                 if (ret_val)
1162                         goto release;
1163         }
1164
1165         /* Set Inband ULP Exit, Reset to SMBus mode and
1166          * Disable SMBus Release on PERST# in PHY
1167          */
1168         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1169         if (ret_val)
1170                 goto release;
1171         phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1172                     I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1173         if (to_sx) {
1174                 if (er32(WUFC) & E1000_WUFC_LNKC)
1175                         phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1176                 else
1177                         phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1178
1179                 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1180                 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1181         } else {
1182                 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1183                 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1184                 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1185         }
1186         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1187
1188         /* Set Disable SMBus Release on PERST# in MAC */
1189         mac_reg = er32(FEXTNVM7);
1190         mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1191         ew32(FEXTNVM7, mac_reg);
1192
1193         /* Commit ULP changes in PHY by starting auto ULP configuration */
1194         phy_reg |= I218_ULP_CONFIG1_START;
1195         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1196
1197         if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1198             to_sx && (er32(STATUS) & E1000_STATUS_LU)) {
1199                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1200                                                         oem_reg);
1201                 if (ret_val)
1202                         goto release;
1203         }
1204
1205 release:
1206         hw->phy.ops.release(hw);
1207 out:
1208         if (ret_val)
1209                 e_dbg("Error in ULP enable flow: %d\n", ret_val);
1210         else
1211                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1212
1213         return ret_val;
1214 }
1215
1216 /**
1217  *  e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1218  *  @hw: pointer to the HW structure
1219  *  @force: boolean indicating whether or not to force disabling ULP
1220  *
1221  *  Un-configure ULP mode when link is up, the system is transitioned from
1222  *  Sx or the driver is unloaded.  If on a Manageability Engine (ME) enabled
1223  *  system, poll for an indication from ME that ULP has been un-configured.
1224  *  If not on an ME enabled system, un-configure the ULP mode by software.
1225  *
1226  *  During nominal operation, this function is called when link is acquired
1227  *  to disable ULP mode (force=false); otherwise, for example when unloading
1228  *  the driver or during Sx->S0 transitions, this is called with force=true
1229  *  to forcibly disable ULP.
1230  */
1231 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1232 {
1233         s32 ret_val = 0;
1234         u32 mac_reg;
1235         u16 phy_reg;
1236         int i = 0;
1237
1238         if ((hw->mac.type < e1000_pch_lpt) ||
1239             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1240             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1241             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1242             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1243             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1244                 return 0;
1245
1246         if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1247                 if (force) {
1248                         /* Request ME un-configure ULP mode in the PHY */
1249                         mac_reg = er32(H2ME);
1250                         mac_reg &= ~E1000_H2ME_ULP;
1251                         mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1252                         ew32(H2ME, mac_reg);
1253                 }
1254
1255                 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1256                 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) {
1257                         if (i++ == 30) {
1258                                 ret_val = -E1000_ERR_PHY;
1259                                 goto out;
1260                         }
1261
1262                         usleep_range(10000, 20000);
1263                 }
1264                 e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1265
1266                 if (force) {
1267                         mac_reg = er32(H2ME);
1268                         mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1269                         ew32(H2ME, mac_reg);
1270                 } else {
1271                         /* Clear H2ME.ULP after ME ULP configuration */
1272                         mac_reg = er32(H2ME);
1273                         mac_reg &= ~E1000_H2ME_ULP;
1274                         ew32(H2ME, mac_reg);
1275                 }
1276
1277                 goto out;
1278         }
1279
1280         ret_val = hw->phy.ops.acquire(hw);
1281         if (ret_val)
1282                 goto out;
1283
1284         if (force)
1285                 /* Toggle LANPHYPC Value bit */
1286                 e1000_toggle_lanphypc_pch_lpt(hw);
1287
1288         /* Unforce SMBus mode in PHY */
1289         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1290         if (ret_val) {
1291                 /* The MAC might be in PCIe mode, so temporarily force to
1292                  * SMBus mode in order to access the PHY.
1293                  */
1294                 mac_reg = er32(CTRL_EXT);
1295                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1296                 ew32(CTRL_EXT, mac_reg);
1297
1298                 msleep(50);
1299
1300                 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1301                                                        &phy_reg);
1302                 if (ret_val)
1303                         goto release;
1304         }
1305         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1306         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1307
1308         /* Unforce SMBus mode in MAC */
1309         mac_reg = er32(CTRL_EXT);
1310         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1311         ew32(CTRL_EXT, mac_reg);
1312
1313         /* When ULP mode was previously entered, K1 was disabled by the
1314          * hardware.  Re-Enable K1 in the PHY when exiting ULP.
1315          */
1316         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1317         if (ret_val)
1318                 goto release;
1319         phy_reg |= HV_PM_CTRL_K1_ENABLE;
1320         e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1321
1322         /* Clear ULP enabled configuration */
1323         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1324         if (ret_val)
1325                 goto release;
1326         phy_reg &= ~(I218_ULP_CONFIG1_IND |
1327                      I218_ULP_CONFIG1_STICKY_ULP |
1328                      I218_ULP_CONFIG1_RESET_TO_SMBUS |
1329                      I218_ULP_CONFIG1_WOL_HOST |
1330                      I218_ULP_CONFIG1_INBAND_EXIT |
1331                      I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1332                      I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1333                      I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1334         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1335
1336         /* Commit ULP changes by starting auto ULP configuration */
1337         phy_reg |= I218_ULP_CONFIG1_START;
1338         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1339
1340         /* Clear Disable SMBus Release on PERST# in MAC */
1341         mac_reg = er32(FEXTNVM7);
1342         mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1343         ew32(FEXTNVM7, mac_reg);
1344
1345 release:
1346         hw->phy.ops.release(hw);
1347         if (force) {
1348                 e1000_phy_hw_reset(hw);
1349                 msleep(50);
1350         }
1351 out:
1352         if (ret_val)
1353                 e_dbg("Error in ULP disable flow: %d\n", ret_val);
1354         else
1355                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1356
1357         return ret_val;
1358 }
1359
1360 /**
1361  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1362  *  @hw: pointer to the HW structure
1363  *
1364  *  Checks to see of the link status of the hardware has changed.  If a
1365  *  change in link status has been detected, then we read the PHY registers
1366  *  to get the current speed/duplex if link exists.
1367  **/
1368 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1369 {
1370         struct e1000_mac_info *mac = &hw->mac;
1371         s32 ret_val, tipg_reg = 0;
1372         u16 emi_addr, emi_val = 0;
1373         bool link;
1374         u16 phy_reg;
1375
1376         /* We only want to go out to the PHY registers to see if Auto-Neg
1377          * has completed and/or if our link status has changed.  The
1378          * get_link_status flag is set upon receiving a Link Status
1379          * Change or Rx Sequence Error interrupt.
1380          */
1381         if (!mac->get_link_status)
1382                 return 0;
1383
1384         /* First we want to see if the MII Status Register reports
1385          * link.  If so, then we want to get the current speed/duplex
1386          * of the PHY.
1387          */
1388         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1389         if (ret_val)
1390                 return ret_val;
1391
1392         if (hw->mac.type == e1000_pchlan) {
1393                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1394                 if (ret_val)
1395                         return ret_val;
1396         }
1397
1398         /* When connected at 10Mbps half-duplex, some parts are excessively
1399          * aggressive resulting in many collisions. To avoid this, increase
1400          * the IPG and reduce Rx latency in the PHY.
1401          */
1402         if (((hw->mac.type == e1000_pch2lan) ||
1403              (hw->mac.type == e1000_pch_lpt) ||
1404              (hw->mac.type == e1000_pch_spt)) && link) {
1405                 u16 speed, duplex;
1406
1407                 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex);
1408                 tipg_reg = er32(TIPG);
1409                 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1410
1411                 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1412                         tipg_reg |= 0xFF;
1413                         /* Reduce Rx latency in analog PHY */
1414                         emi_val = 0;
1415                 } else if (hw->mac.type == e1000_pch_spt &&
1416                            duplex == FULL_DUPLEX && speed != SPEED_1000) {
1417                         tipg_reg |= 0xC;
1418                         emi_val = 1;
1419                 } else {
1420
1421                         /* Roll back the default values */
1422                         tipg_reg |= 0x08;
1423                         emi_val = 1;
1424                 }
1425
1426                 ew32(TIPG, tipg_reg);
1427
1428                 ret_val = hw->phy.ops.acquire(hw);
1429                 if (ret_val)
1430                         return ret_val;
1431
1432                 if (hw->mac.type == e1000_pch2lan)
1433                         emi_addr = I82579_RX_CONFIG;
1434                 else
1435                         emi_addr = I217_RX_CONFIG;
1436                 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1437
1438                 if (hw->mac.type == e1000_pch_lpt ||
1439                     hw->mac.type == e1000_pch_spt) {
1440                         u16 phy_reg;
1441
1442                         e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg);
1443                         phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1444                         if (speed == SPEED_100 || speed == SPEED_10)
1445                                 phy_reg |= 0x3E8;
1446                         else
1447                                 phy_reg |= 0xFA;
1448                         e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg);
1449                 }
1450                 hw->phy.ops.release(hw);
1451
1452                 if (ret_val)
1453                         return ret_val;
1454
1455                 if (hw->mac.type == e1000_pch_spt) {
1456                         u16 data;
1457                         u16 ptr_gap;
1458
1459                         if (speed == SPEED_1000) {
1460                                 ret_val = hw->phy.ops.acquire(hw);
1461                                 if (ret_val)
1462                                         return ret_val;
1463
1464                                 ret_val = e1e_rphy_locked(hw,
1465                                                           PHY_REG(776, 20),
1466                                                           &data);
1467                                 if (ret_val) {
1468                                         hw->phy.ops.release(hw);
1469                                         return ret_val;
1470                                 }
1471
1472                                 ptr_gap = (data & (0x3FF << 2)) >> 2;
1473                                 if (ptr_gap < 0x18) {
1474                                         data &= ~(0x3FF << 2);
1475                                         data |= (0x18 << 2);
1476                                         ret_val =
1477                                             e1e_wphy_locked(hw,
1478                                                             PHY_REG(776, 20),
1479                                                             data);
1480                                 }
1481                                 hw->phy.ops.release(hw);
1482                                 if (ret_val)
1483                                         return ret_val;
1484                         } else {
1485                                 ret_val = hw->phy.ops.acquire(hw);
1486                                 if (ret_val)
1487                                         return ret_val;
1488
1489                                 ret_val = e1e_wphy_locked(hw,
1490                                                           PHY_REG(776, 20),
1491                                                           0xC023);
1492                                 hw->phy.ops.release(hw);
1493                                 if (ret_val)
1494                                         return ret_val;
1495
1496                         }
1497                 }
1498         }
1499
1500         /* I217 Packet Loss issue:
1501          * ensure that FEXTNVM4 Beacon Duration is set correctly
1502          * on power up.
1503          * Set the Beacon Duration for I217 to 8 usec
1504          */
1505         if ((hw->mac.type == e1000_pch_lpt) || (hw->mac.type == e1000_pch_spt)) {
1506                 u32 mac_reg;
1507
1508                 mac_reg = er32(FEXTNVM4);
1509                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1510                 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1511                 ew32(FEXTNVM4, mac_reg);
1512         }
1513
1514         /* Work-around I218 hang issue */
1515         if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1516             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1517             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1518             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
1519                 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1520                 if (ret_val)
1521                         return ret_val;
1522         }
1523         if ((hw->mac.type == e1000_pch_lpt) ||
1524             (hw->mac.type == e1000_pch_spt)) {
1525                 /* Set platform power management values for
1526                  * Latency Tolerance Reporting (LTR)
1527                  */
1528                 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1529                 if (ret_val)
1530                         return ret_val;
1531         }
1532
1533         /* Clear link partner's EEE ability */
1534         hw->dev_spec.ich8lan.eee_lp_ability = 0;
1535
1536         /* FEXTNVM6 K1-off workaround */
1537         if (hw->mac.type == e1000_pch_spt) {
1538                 u32 pcieanacfg = er32(PCIEANACFG);
1539                 u32 fextnvm6 = er32(FEXTNVM6);
1540
1541                 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1542                         fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1543                 else
1544                         fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1545
1546                 ew32(FEXTNVM6, fextnvm6);
1547         }
1548
1549         if (!link)
1550                 return 0;       /* No link detected */
1551
1552         mac->get_link_status = false;
1553
1554         switch (hw->mac.type) {
1555         case e1000_pch2lan:
1556                 ret_val = e1000_k1_workaround_lv(hw);
1557                 if (ret_val)
1558                         return ret_val;
1559                 /* fall-thru */
1560         case e1000_pchlan:
1561                 if (hw->phy.type == e1000_phy_82578) {
1562                         ret_val = e1000_link_stall_workaround_hv(hw);
1563                         if (ret_val)
1564                                 return ret_val;
1565                 }
1566
1567                 /* Workaround for PCHx parts in half-duplex:
1568                  * Set the number of preambles removed from the packet
1569                  * when it is passed from the PHY to the MAC to prevent
1570                  * the MAC from misinterpreting the packet type.
1571                  */
1572                 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1573                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1574
1575                 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1576                         phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1577
1578                 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1579                 break;
1580         default:
1581                 break;
1582         }
1583
1584         /* Check if there was DownShift, must be checked
1585          * immediately after link-up
1586          */
1587         e1000e_check_downshift(hw);
1588
1589         /* Enable/Disable EEE after link up */
1590         if (hw->phy.type > e1000_phy_82579) {
1591                 ret_val = e1000_set_eee_pchlan(hw);
1592                 if (ret_val)
1593                         return ret_val;
1594         }
1595
1596         /* If we are forcing speed/duplex, then we simply return since
1597          * we have already determined whether we have link or not.
1598          */
1599         if (!mac->autoneg)
1600                 return -E1000_ERR_CONFIG;
1601
1602         /* Auto-Neg is enabled.  Auto Speed Detection takes care
1603          * of MAC speed/duplex configuration.  So we only need to
1604          * configure Collision Distance in the MAC.
1605          */
1606         mac->ops.config_collision_dist(hw);
1607
1608         /* Configure Flow Control now that Auto-Neg has completed.
1609          * First, we need to restore the desired flow control
1610          * settings because we may have had to re-autoneg with a
1611          * different link partner.
1612          */
1613         ret_val = e1000e_config_fc_after_link_up(hw);
1614         if (ret_val)
1615                 e_dbg("Error configuring flow control\n");
1616
1617         return ret_val;
1618 }
1619
1620 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1621 {
1622         struct e1000_hw *hw = &adapter->hw;
1623         s32 rc;
1624
1625         rc = e1000_init_mac_params_ich8lan(hw);
1626         if (rc)
1627                 return rc;
1628
1629         rc = e1000_init_nvm_params_ich8lan(hw);
1630         if (rc)
1631                 return rc;
1632
1633         switch (hw->mac.type) {
1634         case e1000_ich8lan:
1635         case e1000_ich9lan:
1636         case e1000_ich10lan:
1637                 rc = e1000_init_phy_params_ich8lan(hw);
1638                 break;
1639         case e1000_pchlan:
1640         case e1000_pch2lan:
1641         case e1000_pch_lpt:
1642         case e1000_pch_spt:
1643                 rc = e1000_init_phy_params_pchlan(hw);
1644                 break;
1645         default:
1646                 break;
1647         }
1648         if (rc)
1649                 return rc;
1650
1651         /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1652          * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1653          */
1654         if ((adapter->hw.phy.type == e1000_phy_ife) ||
1655             ((adapter->hw.mac.type >= e1000_pch2lan) &&
1656              (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1657                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1658                 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1659
1660                 hw->mac.ops.blink_led = NULL;
1661         }
1662
1663         if ((adapter->hw.mac.type == e1000_ich8lan) &&
1664             (adapter->hw.phy.type != e1000_phy_ife))
1665                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1666
1667         /* Enable workaround for 82579 w/ ME enabled */
1668         if ((adapter->hw.mac.type == e1000_pch2lan) &&
1669             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1670                 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1671
1672         return 0;
1673 }
1674
1675 static DEFINE_MUTEX(nvm_mutex);
1676
1677 /**
1678  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1679  *  @hw: pointer to the HW structure
1680  *
1681  *  Acquires the mutex for performing NVM operations.
1682  **/
1683 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1684 {
1685         mutex_lock(&nvm_mutex);
1686
1687         return 0;
1688 }
1689
1690 /**
1691  *  e1000_release_nvm_ich8lan - Release NVM mutex
1692  *  @hw: pointer to the HW structure
1693  *
1694  *  Releases the mutex used while performing NVM operations.
1695  **/
1696 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1697 {
1698         mutex_unlock(&nvm_mutex);
1699 }
1700
1701 /**
1702  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1703  *  @hw: pointer to the HW structure
1704  *
1705  *  Acquires the software control flag for performing PHY and select
1706  *  MAC CSR accesses.
1707  **/
1708 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1709 {
1710         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1711         s32 ret_val = 0;
1712
1713         if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1714                              &hw->adapter->state)) {
1715                 e_dbg("contention for Phy access\n");
1716                 return -E1000_ERR_PHY;
1717         }
1718
1719         while (timeout) {
1720                 extcnf_ctrl = er32(EXTCNF_CTRL);
1721                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1722                         break;
1723
1724                 mdelay(1);
1725                 timeout--;
1726         }
1727
1728         if (!timeout) {
1729                 e_dbg("SW has already locked the resource.\n");
1730                 ret_val = -E1000_ERR_CONFIG;
1731                 goto out;
1732         }
1733
1734         timeout = SW_FLAG_TIMEOUT;
1735
1736         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1737         ew32(EXTCNF_CTRL, extcnf_ctrl);
1738
1739         while (timeout) {
1740                 extcnf_ctrl = er32(EXTCNF_CTRL);
1741                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1742                         break;
1743
1744                 mdelay(1);
1745                 timeout--;
1746         }
1747
1748         if (!timeout) {
1749                 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1750                       er32(FWSM), extcnf_ctrl);
1751                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1752                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1753                 ret_val = -E1000_ERR_CONFIG;
1754                 goto out;
1755         }
1756
1757 out:
1758         if (ret_val)
1759                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1760
1761         return ret_val;
1762 }
1763
1764 /**
1765  *  e1000_release_swflag_ich8lan - Release software control flag
1766  *  @hw: pointer to the HW structure
1767  *
1768  *  Releases the software control flag for performing PHY and select
1769  *  MAC CSR accesses.
1770  **/
1771 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1772 {
1773         u32 extcnf_ctrl;
1774
1775         extcnf_ctrl = er32(EXTCNF_CTRL);
1776
1777         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1778                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1779                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1780         } else {
1781                 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1782         }
1783
1784         clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1785 }
1786
1787 /**
1788  *  e1000_check_mng_mode_ich8lan - Checks management mode
1789  *  @hw: pointer to the HW structure
1790  *
1791  *  This checks if the adapter has any manageability enabled.
1792  *  This is a function pointer entry point only called by read/write
1793  *  routines for the PHY and NVM parts.
1794  **/
1795 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1796 {
1797         u32 fwsm;
1798
1799         fwsm = er32(FWSM);
1800         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1801                 ((fwsm & E1000_FWSM_MODE_MASK) ==
1802                  (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1803 }
1804
1805 /**
1806  *  e1000_check_mng_mode_pchlan - Checks management mode
1807  *  @hw: pointer to the HW structure
1808  *
1809  *  This checks if the adapter has iAMT enabled.
1810  *  This is a function pointer entry point only called by read/write
1811  *  routines for the PHY and NVM parts.
1812  **/
1813 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1814 {
1815         u32 fwsm;
1816
1817         fwsm = er32(FWSM);
1818         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1819             (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1820 }
1821
1822 /**
1823  *  e1000_rar_set_pch2lan - Set receive address register
1824  *  @hw: pointer to the HW structure
1825  *  @addr: pointer to the receive address
1826  *  @index: receive address array register
1827  *
1828  *  Sets the receive address array register at index to the address passed
1829  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1830  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1831  *  Use SHRA[0-3] in place of those reserved for ME.
1832  **/
1833 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1834 {
1835         u32 rar_low, rar_high;
1836
1837         /* HW expects these in little endian so we reverse the byte order
1838          * from network order (big endian) to little endian
1839          */
1840         rar_low = ((u32)addr[0] |
1841                    ((u32)addr[1] << 8) |
1842                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1843
1844         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1845
1846         /* If MAC address zero, no need to set the AV bit */
1847         if (rar_low || rar_high)
1848                 rar_high |= E1000_RAH_AV;
1849
1850         if (index == 0) {
1851                 ew32(RAL(index), rar_low);
1852                 e1e_flush();
1853                 ew32(RAH(index), rar_high);
1854                 e1e_flush();
1855                 return 0;
1856         }
1857
1858         /* RAR[1-6] are owned by manageability.  Skip those and program the
1859          * next address into the SHRA register array.
1860          */
1861         if (index < (u32)(hw->mac.rar_entry_count)) {
1862                 s32 ret_val;
1863
1864                 ret_val = e1000_acquire_swflag_ich8lan(hw);
1865                 if (ret_val)
1866                         goto out;
1867
1868                 ew32(SHRAL(index - 1), rar_low);
1869                 e1e_flush();
1870                 ew32(SHRAH(index - 1), rar_high);
1871                 e1e_flush();
1872
1873                 e1000_release_swflag_ich8lan(hw);
1874
1875                 /* verify the register updates */
1876                 if ((er32(SHRAL(index - 1)) == rar_low) &&
1877                     (er32(SHRAH(index - 1)) == rar_high))
1878                         return 0;
1879
1880                 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1881                       (index - 1), er32(FWSM));
1882         }
1883
1884 out:
1885         e_dbg("Failed to write receive address at index %d\n", index);
1886         return -E1000_ERR_CONFIG;
1887 }
1888
1889 /**
1890  *  e1000_rar_get_count_pch_lpt - Get the number of available SHRA
1891  *  @hw: pointer to the HW structure
1892  *
1893  *  Get the number of available receive registers that the Host can
1894  *  program. SHRA[0-10] are the shared receive address registers
1895  *  that are shared between the Host and manageability engine (ME).
1896  *  ME can reserve any number of addresses and the host needs to be
1897  *  able to tell how many available registers it has access to.
1898  **/
1899 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw)
1900 {
1901         u32 wlock_mac;
1902         u32 num_entries;
1903
1904         wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1905         wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1906
1907         switch (wlock_mac) {
1908         case 0:
1909                 /* All SHRA[0..10] and RAR[0] available */
1910                 num_entries = hw->mac.rar_entry_count;
1911                 break;
1912         case 1:
1913                 /* Only RAR[0] available */
1914                 num_entries = 1;
1915                 break;
1916         default:
1917                 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */
1918                 num_entries = wlock_mac + 1;
1919                 break;
1920         }
1921
1922         return num_entries;
1923 }
1924
1925 /**
1926  *  e1000_rar_set_pch_lpt - Set receive address registers
1927  *  @hw: pointer to the HW structure
1928  *  @addr: pointer to the receive address
1929  *  @index: receive address array register
1930  *
1931  *  Sets the receive address register array at index to the address passed
1932  *  in by addr. For LPT, RAR[0] is the base address register that is to
1933  *  contain the MAC address. SHRA[0-10] are the shared receive address
1934  *  registers that are shared between the Host and manageability engine (ME).
1935  **/
1936 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1937 {
1938         u32 rar_low, rar_high;
1939         u32 wlock_mac;
1940
1941         /* HW expects these in little endian so we reverse the byte order
1942          * from network order (big endian) to little endian
1943          */
1944         rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1945                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1946
1947         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1948
1949         /* If MAC address zero, no need to set the AV bit */
1950         if (rar_low || rar_high)
1951                 rar_high |= E1000_RAH_AV;
1952
1953         if (index == 0) {
1954                 ew32(RAL(index), rar_low);
1955                 e1e_flush();
1956                 ew32(RAH(index), rar_high);
1957                 e1e_flush();
1958                 return 0;
1959         }
1960
1961         /* The manageability engine (ME) can lock certain SHRAR registers that
1962          * it is using - those registers are unavailable for use.
1963          */
1964         if (index < hw->mac.rar_entry_count) {
1965                 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1966                 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1967
1968                 /* Check if all SHRAR registers are locked */
1969                 if (wlock_mac == 1)
1970                         goto out;
1971
1972                 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1973                         s32 ret_val;
1974
1975                         ret_val = e1000_acquire_swflag_ich8lan(hw);
1976
1977                         if (ret_val)
1978                                 goto out;
1979
1980                         ew32(SHRAL_PCH_LPT(index - 1), rar_low);
1981                         e1e_flush();
1982                         ew32(SHRAH_PCH_LPT(index - 1), rar_high);
1983                         e1e_flush();
1984
1985                         e1000_release_swflag_ich8lan(hw);
1986
1987                         /* verify the register updates */
1988                         if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1989                             (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
1990                                 return 0;
1991                 }
1992         }
1993
1994 out:
1995         e_dbg("Failed to write receive address at index %d\n", index);
1996         return -E1000_ERR_CONFIG;
1997 }
1998
1999 /**
2000  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2001  *  @hw: pointer to the HW structure
2002  *
2003  *  Checks if firmware is blocking the reset of the PHY.
2004  *  This is a function pointer entry point only called by
2005  *  reset routines.
2006  **/
2007 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2008 {
2009         bool blocked = false;
2010         int i = 0;
2011
2012         while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
2013                (i++ < 30))
2014                 usleep_range(10000, 20000);
2015         return blocked ? E1000_BLK_PHY_RESET : 0;
2016 }
2017
2018 /**
2019  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2020  *  @hw: pointer to the HW structure
2021  *
2022  *  Assumes semaphore already acquired.
2023  *
2024  **/
2025 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2026 {
2027         u16 phy_data;
2028         u32 strap = er32(STRAP);
2029         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2030             E1000_STRAP_SMT_FREQ_SHIFT;
2031         s32 ret_val;
2032
2033         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2034
2035         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2036         if (ret_val)
2037                 return ret_val;
2038
2039         phy_data &= ~HV_SMB_ADDR_MASK;
2040         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2041         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2042
2043         if (hw->phy.type == e1000_phy_i217) {
2044                 /* Restore SMBus frequency */
2045                 if (freq--) {
2046                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2047                         phy_data |= (freq & BIT(0)) <<
2048                             HV_SMB_ADDR_FREQ_LOW_SHIFT;
2049                         phy_data |= (freq & BIT(1)) <<
2050                             (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2051                 } else {
2052                         e_dbg("Unsupported SMB frequency in PHY\n");
2053                 }
2054         }
2055
2056         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2057 }
2058
2059 /**
2060  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2061  *  @hw:   pointer to the HW structure
2062  *
2063  *  SW should configure the LCD from the NVM extended configuration region
2064  *  as a workaround for certain parts.
2065  **/
2066 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2067 {
2068         struct e1000_phy_info *phy = &hw->phy;
2069         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2070         s32 ret_val = 0;
2071         u16 word_addr, reg_data, reg_addr, phy_page = 0;
2072
2073         /* Initialize the PHY from the NVM on ICH platforms.  This
2074          * is needed due to an issue where the NVM configuration is
2075          * not properly autoloaded after power transitions.
2076          * Therefore, after each PHY reset, we will load the
2077          * configuration data out of the NVM manually.
2078          */
2079         switch (hw->mac.type) {
2080         case e1000_ich8lan:
2081                 if (phy->type != e1000_phy_igp_3)
2082                         return ret_val;
2083
2084                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
2085                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
2086                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2087                         break;
2088                 }
2089                 /* Fall-thru */
2090         case e1000_pchlan:
2091         case e1000_pch2lan:
2092         case e1000_pch_lpt:
2093         case e1000_pch_spt:
2094                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2095                 break;
2096         default:
2097                 return ret_val;
2098         }
2099
2100         ret_val = hw->phy.ops.acquire(hw);
2101         if (ret_val)
2102                 return ret_val;
2103
2104         data = er32(FEXTNVM);
2105         if (!(data & sw_cfg_mask))
2106                 goto release;
2107
2108         /* Make sure HW does not configure LCD from PHY
2109          * extended configuration before SW configuration
2110          */
2111         data = er32(EXTCNF_CTRL);
2112         if ((hw->mac.type < e1000_pch2lan) &&
2113             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2114                 goto release;
2115
2116         cnf_size = er32(EXTCNF_SIZE);
2117         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2118         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2119         if (!cnf_size)
2120                 goto release;
2121
2122         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2123         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2124
2125         if (((hw->mac.type == e1000_pchlan) &&
2126              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2127             (hw->mac.type > e1000_pchlan)) {
2128                 /* HW configures the SMBus address and LEDs when the
2129                  * OEM and LCD Write Enable bits are set in the NVM.
2130                  * When both NVM bits are cleared, SW will configure
2131                  * them instead.
2132                  */
2133                 ret_val = e1000_write_smbus_addr(hw);
2134                 if (ret_val)
2135                         goto release;
2136
2137                 data = er32(LEDCTL);
2138                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2139                                                         (u16)data);
2140                 if (ret_val)
2141                         goto release;
2142         }
2143
2144         /* Configure LCD from extended configuration region. */
2145
2146         /* cnf_base_addr is in DWORD */
2147         word_addr = (u16)(cnf_base_addr << 1);
2148
2149         for (i = 0; i < cnf_size; i++) {
2150                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, &reg_data);
2151                 if (ret_val)
2152                         goto release;
2153
2154                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
2155                                          1, &reg_addr);
2156                 if (ret_val)
2157                         goto release;
2158
2159                 /* Save off the PHY page for future writes. */
2160                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2161                         phy_page = reg_data;
2162                         continue;
2163                 }
2164
2165                 reg_addr &= PHY_REG_MASK;
2166                 reg_addr |= phy_page;
2167
2168                 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
2169                 if (ret_val)
2170                         goto release;
2171         }
2172
2173 release:
2174         hw->phy.ops.release(hw);
2175         return ret_val;
2176 }
2177
2178 /**
2179  *  e1000_k1_gig_workaround_hv - K1 Si workaround
2180  *  @hw:   pointer to the HW structure
2181  *  @link: link up bool flag
2182  *
2183  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2184  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
2185  *  If link is down, the function will restore the default K1 setting located
2186  *  in the NVM.
2187  **/
2188 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2189 {
2190         s32 ret_val = 0;
2191         u16 status_reg = 0;
2192         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2193
2194         if (hw->mac.type != e1000_pchlan)
2195                 return 0;
2196
2197         /* Wrap the whole flow with the sw flag */
2198         ret_val = hw->phy.ops.acquire(hw);
2199         if (ret_val)
2200                 return ret_val;
2201
2202         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2203         if (link) {
2204                 if (hw->phy.type == e1000_phy_82578) {
2205                         ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
2206                                                   &status_reg);
2207                         if (ret_val)
2208                                 goto release;
2209
2210                         status_reg &= (BM_CS_STATUS_LINK_UP |
2211                                        BM_CS_STATUS_RESOLVED |
2212                                        BM_CS_STATUS_SPEED_MASK);
2213
2214                         if (status_reg == (BM_CS_STATUS_LINK_UP |
2215                                            BM_CS_STATUS_RESOLVED |
2216                                            BM_CS_STATUS_SPEED_1000))
2217                                 k1_enable = false;
2218                 }
2219
2220                 if (hw->phy.type == e1000_phy_82577) {
2221                         ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
2222                         if (ret_val)
2223                                 goto release;
2224
2225                         status_reg &= (HV_M_STATUS_LINK_UP |
2226                                        HV_M_STATUS_AUTONEG_COMPLETE |
2227                                        HV_M_STATUS_SPEED_MASK);
2228
2229                         if (status_reg == (HV_M_STATUS_LINK_UP |
2230                                            HV_M_STATUS_AUTONEG_COMPLETE |
2231                                            HV_M_STATUS_SPEED_1000))
2232                                 k1_enable = false;
2233                 }
2234
2235                 /* Link stall fix for link up */
2236                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
2237                 if (ret_val)
2238                         goto release;
2239
2240         } else {
2241                 /* Link stall fix for link down */
2242                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
2243                 if (ret_val)
2244                         goto release;
2245         }
2246
2247         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2248
2249 release:
2250         hw->phy.ops.release(hw);
2251
2252         return ret_val;
2253 }
2254
2255 /**
2256  *  e1000_configure_k1_ich8lan - Configure K1 power state
2257  *  @hw: pointer to the HW structure
2258  *  @enable: K1 state to configure
2259  *
2260  *  Configure the K1 power state based on the provided parameter.
2261  *  Assumes semaphore already acquired.
2262  *
2263  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2264  **/
2265 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2266 {
2267         s32 ret_val;
2268         u32 ctrl_reg = 0;
2269         u32 ctrl_ext = 0;
2270         u32 reg = 0;
2271         u16 kmrn_reg = 0;
2272
2273         ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2274                                               &kmrn_reg);
2275         if (ret_val)
2276                 return ret_val;
2277
2278         if (k1_enable)
2279                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2280         else
2281                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2282
2283         ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2284                                                kmrn_reg);
2285         if (ret_val)
2286                 return ret_val;
2287
2288         usleep_range(20, 40);
2289         ctrl_ext = er32(CTRL_EXT);
2290         ctrl_reg = er32(CTRL);
2291
2292         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2293         reg |= E1000_CTRL_FRCSPD;
2294         ew32(CTRL, reg);
2295
2296         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2297         e1e_flush();
2298         usleep_range(20, 40);
2299         ew32(CTRL, ctrl_reg);
2300         ew32(CTRL_EXT, ctrl_ext);
2301         e1e_flush();
2302         usleep_range(20, 40);
2303
2304         return 0;
2305 }
2306
2307 /**
2308  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2309  *  @hw:       pointer to the HW structure
2310  *  @d0_state: boolean if entering d0 or d3 device state
2311  *
2312  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2313  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
2314  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
2315  **/
2316 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2317 {
2318         s32 ret_val = 0;
2319         u32 mac_reg;
2320         u16 oem_reg;
2321
2322         if (hw->mac.type < e1000_pchlan)
2323                 return ret_val;
2324
2325         ret_val = hw->phy.ops.acquire(hw);
2326         if (ret_val)
2327                 return ret_val;
2328
2329         if (hw->mac.type == e1000_pchlan) {
2330                 mac_reg = er32(EXTCNF_CTRL);
2331                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2332                         goto release;
2333         }
2334
2335         mac_reg = er32(FEXTNVM);
2336         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2337                 goto release;
2338
2339         mac_reg = er32(PHY_CTRL);
2340
2341         ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
2342         if (ret_val)
2343                 goto release;
2344
2345         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2346
2347         if (d0_state) {
2348                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2349                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2350
2351                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2352                         oem_reg |= HV_OEM_BITS_LPLU;
2353         } else {
2354                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2355                                E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2356                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2357
2358                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2359                                E1000_PHY_CTRL_NOND0A_LPLU))
2360                         oem_reg |= HV_OEM_BITS_LPLU;
2361         }
2362
2363         /* Set Restart auto-neg to activate the bits */
2364         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2365             !hw->phy.ops.check_reset_block(hw))
2366                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2367
2368         ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
2369
2370 release:
2371         hw->phy.ops.release(hw);
2372
2373         return ret_val;
2374 }
2375
2376 /**
2377  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2378  *  @hw:   pointer to the HW structure
2379  **/
2380 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2381 {
2382         s32 ret_val;
2383         u16 data;
2384
2385         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
2386         if (ret_val)
2387                 return ret_val;
2388
2389         data |= HV_KMRN_MDIO_SLOW;
2390
2391         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
2392
2393         return ret_val;
2394 }
2395
2396 /**
2397  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2398  *  done after every PHY reset.
2399  **/
2400 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2401 {
2402         s32 ret_val = 0;
2403         u16 phy_data;
2404
2405         if (hw->mac.type != e1000_pchlan)
2406                 return 0;
2407
2408         /* Set MDIO slow mode before any other MDIO access */
2409         if (hw->phy.type == e1000_phy_82577) {
2410                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2411                 if (ret_val)
2412                         return ret_val;
2413         }
2414
2415         if (((hw->phy.type == e1000_phy_82577) &&
2416              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2417             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2418                 /* Disable generation of early preamble */
2419                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
2420                 if (ret_val)
2421                         return ret_val;
2422
2423                 /* Preamble tuning for SSC */
2424                 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
2425                 if (ret_val)
2426                         return ret_val;
2427         }
2428
2429         if (hw->phy.type == e1000_phy_82578) {
2430                 /* Return registers to default by doing a soft reset then
2431                  * writing 0x3140 to the control register.
2432                  */
2433                 if (hw->phy.revision < 2) {
2434                         e1000e_phy_sw_reset(hw);
2435                         ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
2436                 }
2437         }
2438
2439         /* Select page 0 */
2440         ret_val = hw->phy.ops.acquire(hw);
2441         if (ret_val)
2442                 return ret_val;
2443
2444         hw->phy.addr = 1;
2445         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2446         hw->phy.ops.release(hw);
2447         if (ret_val)
2448                 return ret_val;
2449
2450         /* Configure the K1 Si workaround during phy reset assuming there is
2451          * link so that it disables K1 if link is in 1Gbps.
2452          */
2453         ret_val = e1000_k1_gig_workaround_hv(hw, true);
2454         if (ret_val)
2455                 return ret_val;
2456
2457         /* Workaround for link disconnects on a busy hub in half duplex */
2458         ret_val = hw->phy.ops.acquire(hw);
2459         if (ret_val)
2460                 return ret_val;
2461         ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2462         if (ret_val)
2463                 goto release;
2464         ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
2465         if (ret_val)
2466                 goto release;
2467
2468         /* set MSE higher to enable link to stay up when noise is high */
2469         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2470 release:
2471         hw->phy.ops.release(hw);
2472
2473         return ret_val;
2474 }
2475
2476 /**
2477  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2478  *  @hw:   pointer to the HW structure
2479  **/
2480 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2481 {
2482         u32 mac_reg;
2483         u16 i, phy_reg = 0;
2484         s32 ret_val;
2485
2486         ret_val = hw->phy.ops.acquire(hw);
2487         if (ret_val)
2488                 return;
2489         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2490         if (ret_val)
2491                 goto release;
2492
2493         /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2494         for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2495                 mac_reg = er32(RAL(i));
2496                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2497                                            (u16)(mac_reg & 0xFFFF));
2498                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2499                                            (u16)((mac_reg >> 16) & 0xFFFF));
2500
2501                 mac_reg = er32(RAH(i));
2502                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2503                                            (u16)(mac_reg & 0xFFFF));
2504                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2505                                            (u16)((mac_reg & E1000_RAH_AV)
2506                                                  >> 16));
2507         }
2508
2509         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2510
2511 release:
2512         hw->phy.ops.release(hw);
2513 }
2514
2515 /**
2516  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2517  *  with 82579 PHY
2518  *  @hw: pointer to the HW structure
2519  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
2520  **/
2521 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2522 {
2523         s32 ret_val = 0;
2524         u16 phy_reg, data;
2525         u32 mac_reg;
2526         u16 i;
2527
2528         if (hw->mac.type < e1000_pch2lan)
2529                 return 0;
2530
2531         /* disable Rx path while enabling/disabling workaround */
2532         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
2533         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14));
2534         if (ret_val)
2535                 return ret_val;
2536
2537         if (enable) {
2538                 /* Write Rx addresses (rar_entry_count for RAL/H, and
2539                  * SHRAL/H) and initial CRC values to the MAC
2540                  */
2541                 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2542                         u8 mac_addr[ETH_ALEN] = { 0 };
2543                         u32 addr_high, addr_low;
2544
2545                         addr_high = er32(RAH(i));
2546                         if (!(addr_high & E1000_RAH_AV))
2547                                 continue;
2548                         addr_low = er32(RAL(i));
2549                         mac_addr[0] = (addr_low & 0xFF);
2550                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
2551                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
2552                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
2553                         mac_addr[4] = (addr_high & 0xFF);
2554                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
2555
2556                         ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
2557                 }
2558
2559                 /* Write Rx addresses to the PHY */
2560                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2561
2562                 /* Enable jumbo frame workaround in the MAC */
2563                 mac_reg = er32(FFLT_DBG);
2564                 mac_reg &= ~BIT(14);
2565                 mac_reg |= (7 << 15);
2566                 ew32(FFLT_DBG, mac_reg);
2567
2568                 mac_reg = er32(RCTL);
2569                 mac_reg |= E1000_RCTL_SECRC;
2570                 ew32(RCTL, mac_reg);
2571
2572                 ret_val = e1000e_read_kmrn_reg(hw,
2573                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
2574                                                &data);
2575                 if (ret_val)
2576                         return ret_val;
2577                 ret_val = e1000e_write_kmrn_reg(hw,
2578                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2579                                                 data | BIT(0));
2580                 if (ret_val)
2581                         return ret_val;
2582                 ret_val = e1000e_read_kmrn_reg(hw,
2583                                                E1000_KMRNCTRLSTA_HD_CTRL,
2584                                                &data);
2585                 if (ret_val)
2586                         return ret_val;
2587                 data &= ~(0xF << 8);
2588                 data |= (0xB << 8);
2589                 ret_val = e1000e_write_kmrn_reg(hw,
2590                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2591                                                 data);
2592                 if (ret_val)
2593                         return ret_val;
2594
2595                 /* Enable jumbo frame workaround in the PHY */
2596                 e1e_rphy(hw, PHY_REG(769, 23), &data);
2597                 data &= ~(0x7F << 5);
2598                 data |= (0x37 << 5);
2599                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2600                 if (ret_val)
2601                         return ret_val;
2602                 e1e_rphy(hw, PHY_REG(769, 16), &data);
2603                 data &= ~BIT(13);
2604                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2605                 if (ret_val)
2606                         return ret_val;
2607                 e1e_rphy(hw, PHY_REG(776, 20), &data);
2608                 data &= ~(0x3FF << 2);
2609                 data |= (E1000_TX_PTR_GAP << 2);
2610                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2611                 if (ret_val)
2612                         return ret_val;
2613                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
2614                 if (ret_val)
2615                         return ret_val;
2616                 e1e_rphy(hw, HV_PM_CTRL, &data);
2617                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10));
2618                 if (ret_val)
2619                         return ret_val;
2620         } else {
2621                 /* Write MAC register values back to h/w defaults */
2622                 mac_reg = er32(FFLT_DBG);
2623                 mac_reg &= ~(0xF << 14);
2624                 ew32(FFLT_DBG, mac_reg);
2625
2626                 mac_reg = er32(RCTL);
2627                 mac_reg &= ~E1000_RCTL_SECRC;
2628                 ew32(RCTL, mac_reg);
2629
2630                 ret_val = e1000e_read_kmrn_reg(hw,
2631                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
2632                                                &data);
2633                 if (ret_val)
2634                         return ret_val;
2635                 ret_val = e1000e_write_kmrn_reg(hw,
2636                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2637                                                 data & ~BIT(0));
2638                 if (ret_val)
2639                         return ret_val;
2640                 ret_val = e1000e_read_kmrn_reg(hw,
2641                                                E1000_KMRNCTRLSTA_HD_CTRL,
2642                                                &data);
2643                 if (ret_val)
2644                         return ret_val;
2645                 data &= ~(0xF << 8);
2646                 data |= (0xB << 8);
2647                 ret_val = e1000e_write_kmrn_reg(hw,
2648                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2649                                                 data);
2650                 if (ret_val)
2651                         return ret_val;
2652
2653                 /* Write PHY register values back to h/w defaults */
2654                 e1e_rphy(hw, PHY_REG(769, 23), &data);
2655                 data &= ~(0x7F << 5);
2656                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2657                 if (ret_val)
2658                         return ret_val;
2659                 e1e_rphy(hw, PHY_REG(769, 16), &data);
2660                 data |= BIT(13);
2661                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2662                 if (ret_val)
2663                         return ret_val;
2664                 e1e_rphy(hw, PHY_REG(776, 20), &data);
2665                 data &= ~(0x3FF << 2);
2666                 data |= (0x8 << 2);
2667                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2668                 if (ret_val)
2669                         return ret_val;
2670                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2671                 if (ret_val)
2672                         return ret_val;
2673                 e1e_rphy(hw, HV_PM_CTRL, &data);
2674                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10));
2675                 if (ret_val)
2676                         return ret_val;
2677         }
2678
2679         /* re-enable Rx path after enabling/disabling workaround */
2680         return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14));
2681 }
2682
2683 /**
2684  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2685  *  done after every PHY reset.
2686  **/
2687 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2688 {
2689         s32 ret_val = 0;
2690
2691         if (hw->mac.type != e1000_pch2lan)
2692                 return 0;
2693
2694         /* Set MDIO slow mode before any other MDIO access */
2695         ret_val = e1000_set_mdio_slow_mode_hv(hw);
2696         if (ret_val)
2697                 return ret_val;
2698
2699         ret_val = hw->phy.ops.acquire(hw);
2700         if (ret_val)
2701                 return ret_val;
2702         /* set MSE higher to enable link to stay up when noise is high */
2703         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2704         if (ret_val)
2705                 goto release;
2706         /* drop link after 5 times MSE threshold was reached */
2707         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2708 release:
2709         hw->phy.ops.release(hw);
2710
2711         return ret_val;
2712 }
2713
2714 /**
2715  *  e1000_k1_gig_workaround_lv - K1 Si workaround
2716  *  @hw:   pointer to the HW structure
2717  *
2718  *  Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2719  *  Disable K1 in 1000Mbps and 100Mbps
2720  **/
2721 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2722 {
2723         s32 ret_val = 0;
2724         u16 status_reg = 0;
2725
2726         if (hw->mac.type != e1000_pch2lan)
2727                 return 0;
2728
2729         /* Set K1 beacon duration based on 10Mbs speed */
2730         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2731         if (ret_val)
2732                 return ret_val;
2733
2734         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2735             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2736                 if (status_reg &
2737                     (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2738                         u16 pm_phy_reg;
2739
2740                         /* LV 1G/100 Packet drop issue wa  */
2741                         ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2742                         if (ret_val)
2743                                 return ret_val;
2744                         pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2745                         ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2746                         if (ret_val)
2747                                 return ret_val;
2748                 } else {
2749                         u32 mac_reg;
2750
2751                         mac_reg = er32(FEXTNVM4);
2752                         mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2753                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2754                         ew32(FEXTNVM4, mac_reg);
2755                 }
2756         }
2757
2758         return ret_val;
2759 }
2760
2761 /**
2762  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2763  *  @hw:   pointer to the HW structure
2764  *  @gate: boolean set to true to gate, false to ungate
2765  *
2766  *  Gate/ungate the automatic PHY configuration via hardware; perform
2767  *  the configuration via software instead.
2768  **/
2769 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2770 {
2771         u32 extcnf_ctrl;
2772
2773         if (hw->mac.type < e1000_pch2lan)
2774                 return;
2775
2776         extcnf_ctrl = er32(EXTCNF_CTRL);
2777
2778         if (gate)
2779                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2780         else
2781                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2782
2783         ew32(EXTCNF_CTRL, extcnf_ctrl);
2784 }
2785
2786 /**
2787  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2788  *  @hw: pointer to the HW structure
2789  *
2790  *  Check the appropriate indication the MAC has finished configuring the
2791  *  PHY after a software reset.
2792  **/
2793 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2794 {
2795         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2796
2797         /* Wait for basic configuration completes before proceeding */
2798         do {
2799                 data = er32(STATUS);
2800                 data &= E1000_STATUS_LAN_INIT_DONE;
2801                 usleep_range(100, 200);
2802         } while ((!data) && --loop);
2803
2804         /* If basic configuration is incomplete before the above loop
2805          * count reaches 0, loading the configuration from NVM will
2806          * leave the PHY in a bad state possibly resulting in no link.
2807          */
2808         if (loop == 0)
2809                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2810
2811         /* Clear the Init Done bit for the next init event */
2812         data = er32(STATUS);
2813         data &= ~E1000_STATUS_LAN_INIT_DONE;
2814         ew32(STATUS, data);
2815 }
2816
2817 /**
2818  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2819  *  @hw: pointer to the HW structure
2820  **/
2821 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2822 {
2823         s32 ret_val = 0;
2824         u16 reg;
2825
2826         if (hw->phy.ops.check_reset_block(hw))
2827                 return 0;
2828
2829         /* Allow time for h/w to get to quiescent state after reset */
2830         usleep_range(10000, 20000);
2831
2832         /* Perform any necessary post-reset workarounds */
2833         switch (hw->mac.type) {
2834         case e1000_pchlan:
2835                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2836                 if (ret_val)
2837                         return ret_val;
2838                 break;
2839         case e1000_pch2lan:
2840                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2841                 if (ret_val)
2842                         return ret_val;
2843                 break;
2844         default:
2845                 break;
2846         }
2847
2848         /* Clear the host wakeup bit after lcd reset */
2849         if (hw->mac.type >= e1000_pchlan) {
2850                 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
2851                 reg &= ~BM_WUC_HOST_WU_BIT;
2852                 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2853         }
2854
2855         /* Configure the LCD with the extended configuration region in NVM */
2856         ret_val = e1000_sw_lcd_config_ich8lan(hw);
2857         if (ret_val)
2858                 return ret_val;
2859
2860         /* Configure the LCD with the OEM bits in NVM */
2861         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2862
2863         if (hw->mac.type == e1000_pch2lan) {
2864                 /* Ungate automatic PHY configuration on non-managed 82579 */
2865                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2866                         usleep_range(10000, 20000);
2867                         e1000_gate_hw_phy_config_ich8lan(hw, false);
2868                 }
2869
2870                 /* Set EEE LPI Update Timer to 200usec */
2871                 ret_val = hw->phy.ops.acquire(hw);
2872                 if (ret_val)
2873                         return ret_val;
2874                 ret_val = e1000_write_emi_reg_locked(hw,
2875                                                      I82579_LPI_UPDATE_TIMER,
2876                                                      0x1387);
2877                 hw->phy.ops.release(hw);
2878         }
2879
2880         return ret_val;
2881 }
2882
2883 /**
2884  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2885  *  @hw: pointer to the HW structure
2886  *
2887  *  Resets the PHY
2888  *  This is a function pointer entry point called by drivers
2889  *  or other shared routines.
2890  **/
2891 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2892 {
2893         s32 ret_val = 0;
2894
2895         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2896         if ((hw->mac.type == e1000_pch2lan) &&
2897             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2898                 e1000_gate_hw_phy_config_ich8lan(hw, true);
2899
2900         ret_val = e1000e_phy_hw_reset_generic(hw);
2901         if (ret_val)
2902                 return ret_val;
2903
2904         return e1000_post_phy_reset_ich8lan(hw);
2905 }
2906
2907 /**
2908  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2909  *  @hw: pointer to the HW structure
2910  *  @active: true to enable LPLU, false to disable
2911  *
2912  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
2913  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2914  *  the phy speed. This function will manually set the LPLU bit and restart
2915  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
2916  *  since it configures the same bit.
2917  **/
2918 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2919 {
2920         s32 ret_val;
2921         u16 oem_reg;
2922
2923         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2924         if (ret_val)
2925                 return ret_val;
2926
2927         if (active)
2928                 oem_reg |= HV_OEM_BITS_LPLU;
2929         else
2930                 oem_reg &= ~HV_OEM_BITS_LPLU;
2931
2932         if (!hw->phy.ops.check_reset_block(hw))
2933                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2934
2935         return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2936 }
2937
2938 /**
2939  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2940  *  @hw: pointer to the HW structure
2941  *  @active: true to enable LPLU, false to disable
2942  *
2943  *  Sets the LPLU D0 state according to the active flag.  When
2944  *  activating LPLU this function also disables smart speed
2945  *  and vice versa.  LPLU will not be activated unless the
2946  *  device autonegotiation advertisement meets standards of
2947  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2948  *  This is a function pointer entry point only called by
2949  *  PHY setup routines.
2950  **/
2951 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2952 {
2953         struct e1000_phy_info *phy = &hw->phy;
2954         u32 phy_ctrl;
2955         s32 ret_val = 0;
2956         u16 data;
2957
2958         if (phy->type == e1000_phy_ife)
2959                 return 0;
2960
2961         phy_ctrl = er32(PHY_CTRL);
2962
2963         if (active) {
2964                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2965                 ew32(PHY_CTRL, phy_ctrl);
2966
2967                 if (phy->type != e1000_phy_igp_3)
2968                         return 0;
2969
2970                 /* Call gig speed drop workaround on LPLU before accessing
2971                  * any PHY registers
2972                  */
2973                 if (hw->mac.type == e1000_ich8lan)
2974                         e1000e_gig_downshift_workaround_ich8lan(hw);
2975
2976                 /* When LPLU is enabled, we should disable SmartSpeed */
2977                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2978                 if (ret_val)
2979                         return ret_val;
2980                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2981                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2982                 if (ret_val)
2983                         return ret_val;
2984         } else {
2985                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2986                 ew32(PHY_CTRL, phy_ctrl);
2987
2988                 if (phy->type != e1000_phy_igp_3)
2989                         return 0;
2990
2991                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2992                  * during Dx states where the power conservation is most
2993                  * important.  During driver activity we should enable
2994                  * SmartSpeed, so performance is maintained.
2995                  */
2996                 if (phy->smart_speed == e1000_smart_speed_on) {
2997                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2998                                            &data);
2999                         if (ret_val)
3000                                 return ret_val;
3001
3002                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3003                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3004                                            data);
3005                         if (ret_val)
3006                                 return ret_val;
3007                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3008                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3009                                            &data);
3010                         if (ret_val)
3011                                 return ret_val;
3012
3013                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3014                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3015                                            data);
3016                         if (ret_val)
3017                                 return ret_val;
3018                 }
3019         }
3020
3021         return 0;
3022 }
3023
3024 /**
3025  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3026  *  @hw: pointer to the HW structure
3027  *  @active: true to enable LPLU, false to disable
3028  *
3029  *  Sets the LPLU D3 state according to the active flag.  When
3030  *  activating LPLU this function also disables smart speed
3031  *  and vice versa.  LPLU will not be activated unless the
3032  *  device autonegotiation advertisement meets standards of
3033  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3034  *  This is a function pointer entry point only called by
3035  *  PHY setup routines.
3036  **/
3037 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3038 {
3039         struct e1000_phy_info *phy = &hw->phy;
3040         u32 phy_ctrl;
3041         s32 ret_val = 0;
3042         u16 data;
3043
3044         phy_ctrl = er32(PHY_CTRL);
3045
3046         if (!active) {
3047                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3048                 ew32(PHY_CTRL, phy_ctrl);
3049
3050                 if (phy->type != e1000_phy_igp_3)
3051                         return 0;
3052
3053                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3054                  * during Dx states where the power conservation is most
3055                  * important.  During driver activity we should enable
3056                  * SmartSpeed, so performance is maintained.
3057                  */
3058                 if (phy->smart_speed == e1000_smart_speed_on) {
3059                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3060                                            &data);
3061                         if (ret_val)
3062                                 return ret_val;
3063
3064                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3065                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3066                                            data);
3067                         if (ret_val)
3068                                 return ret_val;
3069                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3070                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3071                                            &data);
3072                         if (ret_val)
3073                                 return ret_val;
3074
3075                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3076                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3077                                            data);
3078                         if (ret_val)
3079                                 return ret_val;
3080                 }
3081         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3082                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3083                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3084                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3085                 ew32(PHY_CTRL, phy_ctrl);
3086
3087                 if (phy->type != e1000_phy_igp_3)
3088                         return 0;
3089
3090                 /* Call gig speed drop workaround on LPLU before accessing
3091                  * any PHY registers
3092                  */
3093                 if (hw->mac.type == e1000_ich8lan)
3094                         e1000e_gig_downshift_workaround_ich8lan(hw);
3095
3096                 /* When LPLU is enabled, we should disable SmartSpeed */
3097                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3098                 if (ret_val)
3099                         return ret_val;
3100
3101                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3102                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3103         }
3104
3105         return ret_val;
3106 }
3107
3108 /**
3109  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3110  *  @hw: pointer to the HW structure
3111  *  @bank:  pointer to the variable that returns the active bank
3112  *
3113  *  Reads signature byte from the NVM using the flash access registers.
3114  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3115  **/
3116 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3117 {
3118         u32 eecd;
3119         struct e1000_nvm_info *nvm = &hw->nvm;
3120         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3121         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3122         u32 nvm_dword = 0;
3123         u8 sig_byte = 0;
3124         s32 ret_val;
3125
3126         switch (hw->mac.type) {
3127         case e1000_pch_spt:
3128                 bank1_offset = nvm->flash_bank_size;
3129                 act_offset = E1000_ICH_NVM_SIG_WORD;
3130
3131                 /* set bank to 0 in case flash read fails */
3132                 *bank = 0;
3133
3134                 /* Check bank 0 */
3135                 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3136                                                          &nvm_dword);
3137                 if (ret_val)
3138                         return ret_val;
3139                 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3140                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3141                     E1000_ICH_NVM_SIG_VALUE) {
3142                         *bank = 0;
3143                         return 0;
3144                 }
3145
3146                 /* Check bank 1 */
3147                 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3148                                                          bank1_offset,
3149                                                          &nvm_dword);
3150                 if (ret_val)
3151                         return ret_val;
3152                 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3153                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3154                     E1000_ICH_NVM_SIG_VALUE) {
3155                         *bank = 1;
3156                         return 0;
3157                 }
3158
3159                 e_dbg("ERROR: No valid NVM bank present\n");
3160                 return -E1000_ERR_NVM;
3161         case e1000_ich8lan:
3162         case e1000_ich9lan:
3163                 eecd = er32(EECD);
3164                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3165                     E1000_EECD_SEC1VAL_VALID_MASK) {
3166                         if (eecd & E1000_EECD_SEC1VAL)
3167                                 *bank = 1;
3168                         else
3169                                 *bank = 0;
3170
3171                         return 0;
3172                 }
3173                 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3174                 /* fall-thru */
3175         default:
3176                 /* set bank to 0 in case flash read fails */
3177                 *bank = 0;
3178
3179                 /* Check bank 0 */
3180                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3181                                                         &sig_byte);
3182                 if (ret_val)
3183                         return ret_val;
3184                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3185                     E1000_ICH_NVM_SIG_VALUE) {
3186                         *bank = 0;
3187                         return 0;
3188                 }
3189
3190                 /* Check bank 1 */
3191                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3192                                                         bank1_offset,
3193                                                         &sig_byte);
3194                 if (ret_val)
3195                         return ret_val;
3196                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3197                     E1000_ICH_NVM_SIG_VALUE) {
3198                         *bank = 1;
3199                         return 0;
3200                 }
3201
3202                 e_dbg("ERROR: No valid NVM bank present\n");
3203                 return -E1000_ERR_NVM;
3204         }
3205 }
3206
3207 /**
3208  *  e1000_read_nvm_spt - NVM access for SPT
3209  *  @hw: pointer to the HW structure
3210  *  @offset: The offset (in bytes) of the word(s) to read.
3211  *  @words: Size of data to read in words.
3212  *  @data: pointer to the word(s) to read at offset.
3213  *
3214  *  Reads a word(s) from the NVM
3215  **/
3216 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3217                               u16 *data)
3218 {
3219         struct e1000_nvm_info *nvm = &hw->nvm;
3220         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3221         u32 act_offset;
3222         s32 ret_val = 0;
3223         u32 bank = 0;
3224         u32 dword = 0;
3225         u16 offset_to_read;
3226         u16 i;
3227
3228         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3229             (words == 0)) {
3230                 e_dbg("nvm parameter(s) out of bounds\n");
3231                 ret_val = -E1000_ERR_NVM;
3232                 goto out;
3233         }
3234
3235         nvm->ops.acquire(hw);
3236
3237         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3238         if (ret_val) {
3239                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3240                 bank = 0;
3241         }
3242
3243         act_offset = (bank) ? nvm->flash_bank_size : 0;
3244         act_offset += offset;
3245
3246         ret_val = 0;
3247
3248         for (i = 0; i < words; i += 2) {
3249                 if (words - i == 1) {
3250                         if (dev_spec->shadow_ram[offset + i].modified) {
3251                                 data[i] =
3252                                     dev_spec->shadow_ram[offset + i].value;
3253                         } else {
3254                                 offset_to_read = act_offset + i -
3255                                     ((act_offset + i) % 2);
3256                                 ret_val =
3257                                   e1000_read_flash_dword_ich8lan(hw,
3258                                                                  offset_to_read,
3259                                                                  &dword);
3260                                 if (ret_val)
3261                                         break;
3262                                 if ((act_offset + i) % 2 == 0)
3263                                         data[i] = (u16)(dword & 0xFFFF);
3264                                 else
3265                                         data[i] = (u16)((dword >> 16) & 0xFFFF);
3266                         }
3267                 } else {
3268                         offset_to_read = act_offset + i;
3269                         if (!(dev_spec->shadow_ram[offset + i].modified) ||
3270                             !(dev_spec->shadow_ram[offset + i + 1].modified)) {
3271                                 ret_val =
3272                                   e1000_read_flash_dword_ich8lan(hw,
3273                                                                  offset_to_read,
3274                                                                  &dword);
3275                                 if (ret_val)
3276                                         break;
3277                         }
3278                         if (dev_spec->shadow_ram[offset + i].modified)
3279                                 data[i] =
3280                                     dev_spec->shadow_ram[offset + i].value;
3281                         else
3282                                 data[i] = (u16)(dword & 0xFFFF);
3283                         if (dev_spec->shadow_ram[offset + i].modified)
3284                                 data[i + 1] =
3285                                     dev_spec->shadow_ram[offset + i + 1].value;
3286                         else
3287                                 data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3288                 }
3289         }
3290
3291         nvm->ops.release(hw);
3292
3293 out:
3294         if (ret_val)
3295                 e_dbg("NVM read error: %d\n", ret_val);
3296
3297         return ret_val;
3298 }
3299
3300 /**
3301  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
3302  *  @hw: pointer to the HW structure
3303  *  @offset: The offset (in bytes) of the word(s) to read.
3304  *  @words: Size of data to read in words
3305  *  @data: Pointer to the word(s) to read at offset.
3306  *
3307  *  Reads a word(s) from the NVM using the flash access registers.
3308  **/
3309 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3310                                   u16 *data)
3311 {
3312         struct e1000_nvm_info *nvm = &hw->nvm;
3313         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3314         u32 act_offset;
3315         s32 ret_val = 0;
3316         u32 bank = 0;
3317         u16 i, word;
3318
3319         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3320             (words == 0)) {
3321                 e_dbg("nvm parameter(s) out of bounds\n");
3322                 ret_val = -E1000_ERR_NVM;
3323                 goto out;
3324         }
3325
3326         nvm->ops.acquire(hw);
3327
3328         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3329         if (ret_val) {
3330                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3331                 bank = 0;
3332         }
3333
3334         act_offset = (bank) ? nvm->flash_bank_size : 0;
3335         act_offset += offset;
3336
3337         ret_val = 0;
3338         for (i = 0; i < words; i++) {
3339                 if (dev_spec->shadow_ram[offset + i].modified) {
3340                         data[i] = dev_spec->shadow_ram[offset + i].value;
3341                 } else {
3342                         ret_val = e1000_read_flash_word_ich8lan(hw,
3343                                                                 act_offset + i,
3344                                                                 &word);
3345                         if (ret_val)
3346                                 break;
3347                         data[i] = word;
3348                 }
3349         }
3350
3351         nvm->ops.release(hw);
3352
3353 out:
3354         if (ret_val)
3355                 e_dbg("NVM read error: %d\n", ret_val);
3356
3357         return ret_val;
3358 }
3359
3360 /**
3361  *  e1000_flash_cycle_init_ich8lan - Initialize flash
3362  *  @hw: pointer to the HW structure
3363  *
3364  *  This function does initial flash setup so that a new read/write/erase cycle
3365  *  can be started.
3366  **/
3367 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3368 {
3369         union ich8_hws_flash_status hsfsts;
3370         s32 ret_val = -E1000_ERR_NVM;
3371
3372         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3373
3374         /* Check if the flash descriptor is valid */
3375         if (!hsfsts.hsf_status.fldesvalid) {
3376                 e_dbg("Flash descriptor invalid.  SW Sequencing must be used.\n");
3377                 return -E1000_ERR_NVM;
3378         }
3379
3380         /* Clear FCERR and DAEL in hw status by writing 1 */
3381         hsfsts.hsf_status.flcerr = 1;
3382         hsfsts.hsf_status.dael = 1;
3383         if (hw->mac.type == e1000_pch_spt)
3384                 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3385         else
3386                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3387
3388         /* Either we should have a hardware SPI cycle in progress
3389          * bit to check against, in order to start a new cycle or
3390          * FDONE bit should be changed in the hardware so that it
3391          * is 1 after hardware reset, which can then be used as an
3392          * indication whether a cycle is in progress or has been
3393          * completed.
3394          */
3395
3396         if (!hsfsts.hsf_status.flcinprog) {
3397                 /* There is no cycle running at present,
3398                  * so we can start a cycle.
3399                  * Begin by setting Flash Cycle Done.
3400                  */
3401                 hsfsts.hsf_status.flcdone = 1;
3402                 if (hw->mac.type == e1000_pch_spt)
3403                         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3404                 else
3405                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3406                 ret_val = 0;
3407         } else {
3408                 s32 i;
3409
3410                 /* Otherwise poll for sometime so the current
3411                  * cycle has a chance to end before giving up.
3412                  */
3413                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3414                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3415                         if (!hsfsts.hsf_status.flcinprog) {
3416                                 ret_val = 0;
3417                                 break;
3418                         }
3419                         udelay(1);
3420                 }
3421                 if (!ret_val) {
3422                         /* Successful in waiting for previous cycle to timeout,
3423                          * now set the Flash Cycle Done.
3424                          */
3425                         hsfsts.hsf_status.flcdone = 1;
3426                         if (hw->mac.type == e1000_pch_spt)
3427                                 ew32flash(ICH_FLASH_HSFSTS,
3428                                           hsfsts.regval & 0xFFFF);
3429                         else
3430                                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3431                 } else {
3432                         e_dbg("Flash controller busy, cannot get access\n");
3433                 }
3434         }
3435
3436         return ret_val;
3437 }
3438
3439 /**
3440  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3441  *  @hw: pointer to the HW structure
3442  *  @timeout: maximum time to wait for completion
3443  *
3444  *  This function starts a flash cycle and waits for its completion.
3445  **/
3446 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3447 {
3448         union ich8_hws_flash_ctrl hsflctl;
3449         union ich8_hws_flash_status hsfsts;
3450         u32 i = 0;
3451
3452         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3453         if (hw->mac.type == e1000_pch_spt)
3454                 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3455         else
3456                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3457         hsflctl.hsf_ctrl.flcgo = 1;
3458
3459         if (hw->mac.type == e1000_pch_spt)
3460                 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
3461         else
3462                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3463
3464         /* wait till FDONE bit is set to 1 */
3465         do {
3466                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3467                 if (hsfsts.hsf_status.flcdone)
3468                         break;
3469                 udelay(1);
3470         } while (i++ < timeout);
3471
3472         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3473                 return 0;
3474
3475         return -E1000_ERR_NVM;
3476 }
3477
3478 /**
3479  *  e1000_read_flash_dword_ich8lan - Read dword from flash
3480  *  @hw: pointer to the HW structure
3481  *  @offset: offset to data location
3482  *  @data: pointer to the location for storing the data
3483  *
3484  *  Reads the flash dword at offset into data.  Offset is converted
3485  *  to bytes before read.
3486  **/
3487 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3488                                           u32 *data)
3489 {
3490         /* Must convert word offset into bytes. */
3491         offset <<= 1;
3492         return e1000_read_flash_data32_ich8lan(hw, offset, data);
3493 }
3494
3495 /**
3496  *  e1000_read_flash_word_ich8lan - Read word from flash
3497  *  @hw: pointer to the HW structure
3498  *  @offset: offset to data location
3499  *  @data: pointer to the location for storing the data
3500  *
3501  *  Reads the flash word at offset into data.  Offset is converted
3502  *  to bytes before read.
3503  **/
3504 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3505                                          u16 *data)
3506 {
3507         /* Must convert offset into bytes. */
3508         offset <<= 1;
3509
3510         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3511 }
3512
3513 /**
3514  *  e1000_read_flash_byte_ich8lan - Read byte from flash
3515  *  @hw: pointer to the HW structure
3516  *  @offset: The offset of the byte to read.
3517  *  @data: Pointer to a byte to store the value read.
3518  *
3519  *  Reads a single byte from the NVM using the flash access registers.
3520  **/
3521 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3522                                          u8 *data)
3523 {
3524         s32 ret_val;
3525         u16 word = 0;
3526
3527         /* In SPT, only 32 bits access is supported,
3528          * so this function should not be called.
3529          */
3530         if (hw->mac.type == e1000_pch_spt)
3531                 return -E1000_ERR_NVM;
3532         else
3533                 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3534
3535         if (ret_val)
3536                 return ret_val;
3537
3538         *data = (u8)word;
3539
3540         return 0;
3541 }
3542
3543 /**
3544  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
3545  *  @hw: pointer to the HW structure
3546  *  @offset: The offset (in bytes) of the byte or word to read.
3547  *  @size: Size of data to read, 1=byte 2=word
3548  *  @data: Pointer to the word to store the value read.
3549  *
3550  *  Reads a byte or word from the NVM using the flash access registers.
3551  **/
3552 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3553                                          u8 size, u16 *data)
3554 {
3555         union ich8_hws_flash_status hsfsts;
3556         union ich8_hws_flash_ctrl hsflctl;
3557         u32 flash_linear_addr;
3558         u32 flash_data = 0;
3559         s32 ret_val = -E1000_ERR_NVM;
3560         u8 count = 0;
3561
3562         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3563                 return -E1000_ERR_NVM;
3564
3565         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3566                              hw->nvm.flash_base_addr);
3567
3568         do {
3569                 udelay(1);
3570                 /* Steps */
3571                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3572                 if (ret_val)
3573                         break;
3574
3575                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3576                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3577                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3578                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3579                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3580
3581                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3582
3583                 ret_val =
3584                     e1000_flash_cycle_ich8lan(hw,
3585                                               ICH_FLASH_READ_COMMAND_TIMEOUT);
3586
3587                 /* Check if FCERR is set to 1, if set to 1, clear it
3588                  * and try the whole sequence a few more times, else
3589                  * read in (shift in) the Flash Data0, the order is
3590                  * least significant byte first msb to lsb
3591                  */
3592                 if (!ret_val) {
3593                         flash_data = er32flash(ICH_FLASH_FDATA0);
3594                         if (size == 1)
3595                                 *data = (u8)(flash_data & 0x000000FF);
3596                         else if (size == 2)
3597                                 *data = (u16)(flash_data & 0x0000FFFF);
3598                         break;
3599                 } else {
3600                         /* If we've gotten here, then things are probably
3601                          * completely hosed, but if the error condition is
3602                          * detected, it won't hurt to give it another try...
3603                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3604                          */
3605                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3606                         if (hsfsts.hsf_status.flcerr) {
3607                                 /* Repeat for some time before giving up. */
3608                                 continue;
3609                         } else if (!hsfsts.hsf_status.flcdone) {
3610                                 e_dbg("Timeout error - flash cycle did not complete.\n");
3611                                 break;
3612                         }
3613                 }
3614         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3615
3616         return ret_val;
3617 }
3618
3619 /**
3620  *  e1000_read_flash_data32_ich8lan - Read dword from NVM
3621  *  @hw: pointer to the HW structure
3622  *  @offset: The offset (in bytes) of the dword to read.
3623  *  @data: Pointer to the dword to store the value read.
3624  *
3625  *  Reads a byte or word from the NVM using the flash access registers.
3626  **/
3627
3628 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3629                                            u32 *data)
3630 {
3631         union ich8_hws_flash_status hsfsts;
3632         union ich8_hws_flash_ctrl hsflctl;
3633         u32 flash_linear_addr;
3634         s32 ret_val = -E1000_ERR_NVM;
3635         u8 count = 0;
3636
3637         if (offset > ICH_FLASH_LINEAR_ADDR_MASK ||
3638             hw->mac.type != e1000_pch_spt)
3639                 return -E1000_ERR_NVM;
3640         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3641                              hw->nvm.flash_base_addr);
3642
3643         do {
3644                 udelay(1);
3645                 /* Steps */
3646                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3647                 if (ret_val)
3648                         break;
3649                 /* In SPT, This register is in Lan memory space, not flash.
3650                  * Therefore, only 32 bit access is supported
3651                  */
3652                 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3653
3654                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3655                 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3656                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3657                 /* In SPT, This register is in Lan memory space, not flash.
3658                  * Therefore, only 32 bit access is supported
3659                  */
3660                 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16);
3661                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3662
3663                 ret_val =
3664                    e1000_flash_cycle_ich8lan(hw,
3665                                              ICH_FLASH_READ_COMMAND_TIMEOUT);
3666
3667                 /* Check if FCERR is set to 1, if set to 1, clear it
3668                  * and try the whole sequence a few more times, else
3669                  * read in (shift in) the Flash Data0, the order is
3670                  * least significant byte first msb to lsb
3671                  */
3672                 if (!ret_val) {
3673                         *data = er32flash(ICH_FLASH_FDATA0);
3674                         break;
3675                 } else {
3676                         /* If we've gotten here, then things are probably
3677                          * completely hosed, but if the error condition is
3678                          * detected, it won't hurt to give it another try...
3679                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3680                          */
3681                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3682                         if (hsfsts.hsf_status.flcerr) {
3683                                 /* Repeat for some time before giving up. */
3684                                 continue;
3685                         } else if (!hsfsts.hsf_status.flcdone) {
3686                                 e_dbg("Timeout error - flash cycle did not complete.\n");
3687                                 break;
3688                         }
3689                 }
3690         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3691
3692         return ret_val;
3693 }
3694
3695 /**
3696  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
3697  *  @hw: pointer to the HW structure
3698  *  @offset: The offset (in bytes) of the word(s) to write.
3699  *  @words: Size of data to write in words
3700  *  @data: Pointer to the word(s) to write at offset.
3701  *
3702  *  Writes a byte or word to the NVM using the flash access registers.
3703  **/
3704 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3705                                    u16 *data)
3706 {
3707         struct e1000_nvm_info *nvm = &hw->nvm;
3708         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3709         u16 i;
3710
3711         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3712             (words == 0)) {
3713                 e_dbg("nvm parameter(s) out of bounds\n");
3714                 return -E1000_ERR_NVM;
3715         }
3716
3717         nvm->ops.acquire(hw);
3718
3719         for (i = 0; i < words; i++) {
3720                 dev_spec->shadow_ram[offset + i].modified = true;
3721                 dev_spec->shadow_ram[offset + i].value = data[i];
3722         }
3723
3724         nvm->ops.release(hw);
3725
3726         return 0;
3727 }
3728
3729 /**
3730  *  e1000_update_nvm_checksum_spt - Update the checksum for NVM
3731  *  @hw: pointer to the HW structure
3732  *
3733  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3734  *  which writes the checksum to the shadow ram.  The changes in the shadow
3735  *  ram are then committed to the EEPROM by processing each bank at a time
3736  *  checking for the modified bit and writing only the pending changes.
3737  *  After a successful commit, the shadow ram is cleared and is ready for
3738  *  future writes.
3739  **/
3740 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
3741 {
3742         struct e1000_nvm_info *nvm = &hw->nvm;
3743         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3744         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3745         s32 ret_val;
3746         u32 dword = 0;
3747
3748         ret_val = e1000e_update_nvm_checksum_generic(hw);
3749         if (ret_val)
3750                 goto out;
3751
3752         if (nvm->type != e1000_nvm_flash_sw)
3753                 goto out;
3754
3755         nvm->ops.acquire(hw);
3756
3757         /* We're writing to the opposite bank so if we're on bank 1,
3758          * write to bank 0 etc.  We also need to erase the segment that
3759          * is going to be written
3760          */
3761         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3762         if (ret_val) {
3763                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3764                 bank = 0;
3765         }
3766
3767         if (bank == 0) {
3768                 new_bank_offset = nvm->flash_bank_size;
3769                 old_bank_offset = 0;
3770                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3771                 if (ret_val)
3772                         goto release;
3773         } else {
3774                 old_bank_offset = nvm->flash_bank_size;
3775                 new_bank_offset = 0;
3776                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3777                 if (ret_val)
3778                         goto release;
3779         }
3780         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) {
3781                 /* Determine whether to write the value stored
3782                  * in the other NVM bank or a modified value stored
3783                  * in the shadow RAM
3784                  */
3785                 ret_val = e1000_read_flash_dword_ich8lan(hw,
3786                                                          i + old_bank_offset,
3787                                                          &dword);
3788
3789                 if (dev_spec->shadow_ram[i].modified) {
3790                         dword &= 0xffff0000;
3791                         dword |= (dev_spec->shadow_ram[i].value & 0xffff);
3792                 }
3793                 if (dev_spec->shadow_ram[i + 1].modified) {
3794                         dword &= 0x0000ffff;
3795                         dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
3796                                   << 16);
3797                 }
3798                 if (ret_val)
3799                         break;
3800
3801                 /* If the word is 0x13, then make sure the signature bits
3802                  * (15:14) are 11b until the commit has completed.
3803                  * This will allow us to write 10b which indicates the
3804                  * signature is valid.  We want to do this after the write
3805                  * has completed so that we don't mark the segment valid
3806                  * while the write is still in progress
3807                  */
3808                 if (i == E1000_ICH_NVM_SIG_WORD - 1)
3809                         dword |= E1000_ICH_NVM_SIG_MASK << 16;
3810
3811                 /* Convert offset to bytes. */
3812                 act_offset = (i + new_bank_offset) << 1;
3813
3814                 usleep_range(100, 200);
3815
3816                 /* Write the data to the new bank. Offset in words */
3817                 act_offset = i + new_bank_offset;
3818                 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
3819                                                                 dword);
3820                 if (ret_val)
3821                         break;
3822         }
3823
3824         /* Don't bother writing the segment valid bits if sector
3825          * programming failed.
3826          */
3827         if (ret_val) {
3828                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3829                 e_dbg("Flash commit failed.\n");
3830                 goto release;
3831         }
3832
3833         /* Finally validate the new segment by setting bit 15:14
3834          * to 10b in word 0x13 , this can be done without an
3835          * erase as well since these bits are 11 to start with
3836          * and we need to change bit 14 to 0b
3837          */
3838         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3839
3840         /*offset in words but we read dword */
3841         --act_offset;
3842         ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3843
3844         if (ret_val)
3845                 goto release;
3846
3847         dword &= 0xBFFFFFFF;
3848         ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3849
3850         if (ret_val)
3851                 goto release;
3852
3853         /* And invalidate the previously valid segment by setting
3854          * its signature word (0x13) high_byte to 0b. This can be
3855          * done without an erase because flash erase sets all bits
3856          * to 1's. We can write 1's to 0's without an erase
3857          */
3858         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3859
3860         /* offset in words but we read dword */
3861         act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
3862         ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3863
3864         if (ret_val)
3865                 goto release;
3866
3867         dword &= 0x00FFFFFF;
3868         ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3869
3870         if (ret_val)
3871                 goto release;
3872
3873         /* Great!  Everything worked, we can now clear the cached entries. */
3874         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3875                 dev_spec->shadow_ram[i].modified = false;
3876                 dev_spec->shadow_ram[i].value = 0xFFFF;
3877         }
3878
3879 release:
3880         nvm->ops.release(hw);
3881
3882         /* Reload the EEPROM, or else modifications will not appear
3883          * until after the next adapter reset.
3884          */
3885         if (!ret_val) {
3886                 nvm->ops.reload(hw);
3887                 usleep_range(10000, 20000);
3888         }
3889
3890 out:
3891         if (ret_val)
3892                 e_dbg("NVM update error: %d\n", ret_val);
3893
3894         return ret_val;
3895 }
3896
3897 /**
3898  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3899  *  @hw: pointer to the HW structure
3900  *
3901  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3902  *  which writes the checksum to the shadow ram.  The changes in the shadow
3903  *  ram are then committed to the EEPROM by processing each bank at a time
3904  *  checking for the modified bit and writing only the pending changes.
3905  *  After a successful commit, the shadow ram is cleared and is ready for
3906  *  future writes.
3907  **/
3908 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3909 {
3910         struct e1000_nvm_info *nvm = &hw->nvm;
3911         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3912         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3913         s32 ret_val;
3914         u16 data = 0;
3915
3916         ret_val = e1000e_update_nvm_checksum_generic(hw);
3917         if (ret_val)
3918                 goto out;
3919
3920         if (nvm->type != e1000_nvm_flash_sw)
3921                 goto out;
3922
3923         nvm->ops.acquire(hw);
3924
3925         /* We're writing to the opposite bank so if we're on bank 1,
3926          * write to bank 0 etc.  We also need to erase the segment that
3927          * is going to be written
3928          */
3929         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3930         if (ret_val) {
3931                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3932                 bank = 0;
3933         }
3934
3935         if (bank == 0) {
3936                 new_bank_offset = nvm->flash_bank_size;
3937                 old_bank_offset = 0;
3938                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3939                 if (ret_val)
3940                         goto release;
3941         } else {
3942                 old_bank_offset = nvm->flash_bank_size;
3943                 new_bank_offset = 0;
3944                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3945                 if (ret_val)
3946                         goto release;
3947         }
3948         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3949                 if (dev_spec->shadow_ram[i].modified) {
3950                         data = dev_spec->shadow_ram[i].value;
3951                 } else {
3952                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
3953                                                                 old_bank_offset,
3954                                                                 &data);
3955                         if (ret_val)
3956                                 break;
3957                 }
3958
3959                 /* If the word is 0x13, then make sure the signature bits
3960                  * (15:14) are 11b until the commit has completed.
3961                  * This will allow us to write 10b which indicates the
3962                  * signature is valid.  We want to do this after the write
3963                  * has completed so that we don't mark the segment valid
3964                  * while the write is still in progress
3965                  */
3966                 if (i == E1000_ICH_NVM_SIG_WORD)
3967                         data |= E1000_ICH_NVM_SIG_MASK;
3968
3969                 /* Convert offset to bytes. */
3970                 act_offset = (i + new_bank_offset) << 1;
3971
3972                 usleep_range(100, 200);
3973                 /* Write the bytes to the new bank. */
3974                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3975                                                                act_offset,
3976                                                                (u8)data);
3977                 if (ret_val)
3978                         break;
3979
3980                 usleep_range(100, 200);
3981                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3982                                                                act_offset + 1,
3983                                                                (u8)(data >> 8));
3984                 if (ret_val)
3985                         break;
3986         }
3987
3988         /* Don't bother writing the segment valid bits if sector
3989          * programming failed.
3990          */
3991         if (ret_val) {
3992                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3993                 e_dbg("Flash commit failed.\n");
3994                 goto release;
3995         }
3996
3997         /* Finally validate the new segment by setting bit 15:14
3998          * to 10b in word 0x13 , this can be done without an
3999          * erase as well since these bits are 11 to start with
4000          * and we need to change bit 14 to 0b
4001          */
4002         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4003         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4004         if (ret_val)
4005                 goto release;
4006
4007         data &= 0xBFFF;
4008         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4009                                                        act_offset * 2 + 1,
4010                                                        (u8)(data >> 8));
4011         if (ret_val)
4012                 goto release;
4013
4014         /* And invalidate the previously valid segment by setting
4015          * its signature word (0x13) high_byte to 0b. This can be
4016          * done without an erase because flash erase sets all bits
4017          * to 1's. We can write 1's to 0's without an erase
4018          */
4019         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4020         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4021         if (ret_val)
4022                 goto release;
4023
4024         /* Great!  Everything worked, we can now clear the cached entries. */
4025         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
4026                 dev_spec->shadow_ram[i].modified = false;
4027                 dev_spec->shadow_ram[i].value = 0xFFFF;
4028         }
4029
4030 release:
4031         nvm->ops.release(hw);
4032
4033         /* Reload the EEPROM, or else modifications will not appear
4034          * until after the next adapter reset.
4035          */
4036         if (!ret_val) {
4037                 nvm->ops.reload(hw);
4038                 usleep_range(10000, 20000);
4039         }
4040
4041 out:
4042         if (ret_val)
4043                 e_dbg("NVM update error: %d\n", ret_val);
4044
4045         return ret_val;
4046 }
4047
4048 /**
4049  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4050  *  @hw: pointer to the HW structure
4051  *
4052  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4053  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
4054  *  calculated, in which case we need to calculate the checksum and set bit 6.
4055  **/
4056 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4057 {
4058         s32 ret_val;
4059         u16 data;
4060         u16 word;
4061         u16 valid_csum_mask;
4062
4063         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
4064          * the checksum needs to be fixed.  This bit is an indication that
4065          * the NVM was prepared by OEM software and did not calculate
4066          * the checksum...a likely scenario.
4067          */
4068         switch (hw->mac.type) {
4069         case e1000_pch_lpt:
4070         case e1000_pch_spt:
4071                 word = NVM_COMPAT;
4072                 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4073                 break;
4074         default:
4075                 word = NVM_FUTURE_INIT_WORD1;
4076                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4077                 break;
4078         }
4079
4080         ret_val = e1000_read_nvm(hw, word, 1, &data);
4081         if (ret_val)
4082                 return ret_val;
4083
4084         if (!(data & valid_csum_mask)) {
4085                 data |= valid_csum_mask;
4086                 ret_val = e1000_write_nvm(hw, word, 1, &data);
4087                 if (ret_val)
4088                         return ret_val;
4089                 ret_val = e1000e_update_nvm_checksum(hw);
4090                 if (ret_val)
4091                         return ret_val;
4092         }
4093
4094         return e1000e_validate_nvm_checksum_generic(hw);
4095 }
4096
4097 /**
4098  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
4099  *  @hw: pointer to the HW structure
4100  *
4101  *  To prevent malicious write/erase of the NVM, set it to be read-only
4102  *  so that the hardware ignores all write/erase cycles of the NVM via
4103  *  the flash control registers.  The shadow-ram copy of the NVM will
4104  *  still be updated, however any updates to this copy will not stick
4105  *  across driver reloads.
4106  **/
4107 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
4108 {
4109         struct e1000_nvm_info *nvm = &hw->nvm;
4110         union ich8_flash_protected_range pr0;
4111         union ich8_hws_flash_status hsfsts;
4112         u32 gfpreg;
4113
4114         nvm->ops.acquire(hw);
4115
4116         gfpreg = er32flash(ICH_FLASH_GFPREG);
4117
4118         /* Write-protect GbE Sector of NVM */
4119         pr0.regval = er32flash(ICH_FLASH_PR0);
4120         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
4121         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
4122         pr0.range.wpe = true;
4123         ew32flash(ICH_FLASH_PR0, pr0.regval);
4124
4125         /* Lock down a subset of GbE Flash Control Registers, e.g.
4126          * PR0 to prevent the write-protection from being lifted.
4127          * Once FLOCKDN is set, the registers protected by it cannot
4128          * be written until FLOCKDN is cleared by a hardware reset.
4129          */
4130         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4131         hsfsts.hsf_status.flockdn = true;
4132         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
4133
4134         nvm->ops.release(hw);
4135 }
4136
4137 /**
4138  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4139  *  @hw: pointer to the HW structure
4140  *  @offset: The offset (in bytes) of the byte/word to read.
4141  *  @size: Size of data to read, 1=byte 2=word
4142  *  @data: The byte(s) to write to the NVM.
4143  *
4144  *  Writes one/two bytes to the NVM using the flash access registers.
4145  **/
4146 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4147                                           u8 size, u16 data)
4148 {
4149         union ich8_hws_flash_status hsfsts;
4150         union ich8_hws_flash_ctrl hsflctl;
4151         u32 flash_linear_addr;
4152         u32 flash_data = 0;
4153         s32 ret_val;
4154         u8 count = 0;
4155
4156         if (hw->mac.type == e1000_pch_spt) {
4157                 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4158                         return -E1000_ERR_NVM;
4159         } else {
4160                 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4161                         return -E1000_ERR_NVM;
4162         }
4163
4164         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4165                              hw->nvm.flash_base_addr);
4166
4167         do {
4168                 udelay(1);
4169                 /* Steps */
4170                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4171                 if (ret_val)
4172                         break;
4173                 /* In SPT, This register is in Lan memory space, not
4174                  * flash.  Therefore, only 32 bit access is supported
4175                  */
4176                 if (hw->mac.type == e1000_pch_spt)
4177                         hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
4178                 else
4179                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4180
4181                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4182                 hsflctl.hsf_ctrl.fldbcount = size - 1;
4183                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4184                 /* In SPT, This register is in Lan memory space,
4185                  * not flash.  Therefore, only 32 bit access is
4186                  * supported
4187                  */
4188                 if (hw->mac.type == e1000_pch_spt)
4189                         ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4190                 else
4191                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4192
4193                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4194
4195                 if (size == 1)
4196                         flash_data = (u32)data & 0x00FF;
4197                 else
4198                         flash_data = (u32)data;
4199
4200                 ew32flash(ICH_FLASH_FDATA0, flash_data);
4201
4202                 /* check if FCERR is set to 1 , if set to 1, clear it
4203                  * and try the whole sequence a few more times else done
4204                  */
4205                 ret_val =
4206                     e1000_flash_cycle_ich8lan(hw,
4207                                               ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4208                 if (!ret_val)
4209                         break;
4210
4211                 /* If we're here, then things are most likely
4212                  * completely hosed, but if the error condition
4213                  * is detected, it won't hurt to give it another
4214                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4215                  */
4216                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4217                 if (hsfsts.hsf_status.flcerr)
4218                         /* Repeat for some time before giving up. */
4219                         continue;
4220                 if (!hsfsts.hsf_status.flcdone) {
4221                         e_dbg("Timeout error - flash cycle did not complete.\n");
4222                         break;
4223                 }
4224         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4225
4226         return ret_val;
4227 }
4228
4229 /**
4230 *  e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4231 *  @hw: pointer to the HW structure
4232 *  @offset: The offset (in bytes) of the dwords to read.
4233 *  @data: The 4 bytes to write to the NVM.
4234 *
4235 *  Writes one/two/four bytes to the NVM using the flash access registers.
4236 **/
4237 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4238                                             u32 data)
4239 {
4240         union ich8_hws_flash_status hsfsts;
4241         union ich8_hws_flash_ctrl hsflctl;
4242         u32 flash_linear_addr;
4243         s32 ret_val;
4244         u8 count = 0;
4245
4246         if (hw->mac.type == e1000_pch_spt) {
4247                 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4248                         return -E1000_ERR_NVM;
4249         }
4250         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4251                              hw->nvm.flash_base_addr);
4252         do {
4253                 udelay(1);
4254                 /* Steps */
4255                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4256                 if (ret_val)
4257                         break;
4258
4259                 /* In SPT, This register is in Lan memory space, not
4260                  * flash.  Therefore, only 32 bit access is supported
4261                  */
4262                 if (hw->mac.type == e1000_pch_spt)
4263                         hsflctl.regval = er32flash(ICH_FLASH_HSFSTS)
4264                             >> 16;
4265                 else
4266                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4267
4268                 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4269                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4270
4271                 /* In SPT, This register is in Lan memory space,
4272                  * not flash.  Therefore, only 32 bit access is
4273                  * supported
4274                  */
4275                 if (hw->mac.type == e1000_pch_spt)
4276                         ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4277                 else
4278                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4279
4280                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4281
4282                 ew32flash(ICH_FLASH_FDATA0, data);
4283
4284                 /* check if FCERR is set to 1 , if set to 1, clear it
4285                  * and try the whole sequence a few more times else done
4286                  */
4287                 ret_val =
4288                    e1000_flash_cycle_ich8lan(hw,
4289                                              ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4290
4291                 if (!ret_val)
4292                         break;
4293
4294                 /* If we're here, then things are most likely
4295                  * completely hosed, but if the error condition
4296                  * is detected, it won't hurt to give it another
4297                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4298                  */
4299                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4300
4301                 if (hsfsts.hsf_status.flcerr)
4302                         /* Repeat for some time before giving up. */
4303                         continue;
4304                 if (!hsfsts.hsf_status.flcdone) {
4305                         e_dbg("Timeout error - flash cycle did not complete.\n");
4306                         break;
4307                 }
4308         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4309
4310         return ret_val;
4311 }
4312
4313 /**
4314  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4315  *  @hw: pointer to the HW structure
4316  *  @offset: The index of the byte to read.
4317  *  @data: The byte to write to the NVM.
4318  *
4319  *  Writes a single byte to the NVM using the flash access registers.
4320  **/
4321 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4322                                           u8 data)
4323 {
4324         u16 word = (u16)data;
4325
4326         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4327 }
4328
4329 /**
4330 *  e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4331 *  @hw: pointer to the HW structure
4332 *  @offset: The offset of the word to write.
4333 *  @dword: The dword to write to the NVM.
4334 *
4335 *  Writes a single dword to the NVM using the flash access registers.
4336 *  Goes through a retry algorithm before giving up.
4337 **/
4338 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4339                                                  u32 offset, u32 dword)
4340 {
4341         s32 ret_val;
4342         u16 program_retries;
4343
4344         /* Must convert word offset into bytes. */
4345         offset <<= 1;
4346         ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4347
4348         if (!ret_val)
4349                 return ret_val;
4350         for (program_retries = 0; program_retries < 100; program_retries++) {
4351                 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset);
4352                 usleep_range(100, 200);
4353                 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4354                 if (!ret_val)
4355                         break;
4356         }
4357         if (program_retries == 100)
4358                 return -E1000_ERR_NVM;
4359
4360         return 0;
4361 }
4362
4363 /**
4364  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4365  *  @hw: pointer to the HW structure
4366  *  @offset: The offset of the byte to write.
4367  *  @byte: The byte to write to the NVM.
4368  *
4369  *  Writes a single byte to the NVM using the flash access registers.
4370  *  Goes through a retry algorithm before giving up.
4371  **/
4372 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4373                                                 u32 offset, u8 byte)
4374 {
4375         s32 ret_val;
4376         u16 program_retries;
4377
4378         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4379         if (!ret_val)
4380                 return ret_val;
4381
4382         for (program_retries = 0; program_retries < 100; program_retries++) {
4383                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
4384                 usleep_range(100, 200);
4385                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4386                 if (!ret_val)
4387                         break;
4388         }
4389         if (program_retries == 100)
4390                 return -E1000_ERR_NVM;
4391
4392         return 0;
4393 }
4394
4395 /**
4396  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4397  *  @hw: pointer to the HW structure
4398  *  @bank: 0 for first bank, 1 for second bank, etc.
4399  *
4400  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4401  *  bank N is 4096 * N + flash_reg_addr.
4402  **/
4403 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4404 {
4405         struct e1000_nvm_info *nvm = &hw->nvm;
4406         union ich8_hws_flash_status hsfsts;
4407         union ich8_hws_flash_ctrl hsflctl;
4408         u32 flash_linear_addr;
4409         /* bank size is in 16bit words - adjust to bytes */
4410         u32 flash_bank_size = nvm->flash_bank_size * 2;
4411         s32 ret_val;
4412         s32 count = 0;
4413         s32 j, iteration, sector_size;
4414
4415         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4416
4417         /* Determine HW Sector size: Read BERASE bits of hw flash status
4418          * register
4419          * 00: The Hw sector is 256 bytes, hence we need to erase 16
4420          *     consecutive sectors.  The start index for the nth Hw sector
4421          *     can be calculated as = bank * 4096 + n * 256
4422          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4423          *     The start index for the nth Hw sector can be calculated
4424          *     as = bank * 4096
4425          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4426          *     (ich9 only, otherwise error condition)
4427          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4428          */
4429         switch (hsfsts.hsf_status.berasesz) {
4430         case 0:
4431                 /* Hw sector size 256 */
4432                 sector_size = ICH_FLASH_SEG_SIZE_256;
4433                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4434                 break;
4435         case 1:
4436                 sector_size = ICH_FLASH_SEG_SIZE_4K;
4437                 iteration = 1;
4438                 break;
4439         case 2:
4440                 sector_size = ICH_FLASH_SEG_SIZE_8K;
4441                 iteration = 1;
4442                 break;
4443         case 3:
4444                 sector_size = ICH_FLASH_SEG_SIZE_64K;
4445                 iteration = 1;
4446                 break;
4447         default:
4448                 return -E1000_ERR_NVM;
4449         }
4450
4451         /* Start with the base address, then add the sector offset. */
4452         flash_linear_addr = hw->nvm.flash_base_addr;
4453         flash_linear_addr += (bank) ? flash_bank_size : 0;
4454
4455         for (j = 0; j < iteration; j++) {
4456                 do {
4457                         u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4458
4459                         /* Steps */
4460                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
4461                         if (ret_val)
4462                                 return ret_val;
4463
4464                         /* Write a value 11 (block Erase) in Flash
4465                          * Cycle field in hw flash control
4466                          */
4467                         if (hw->mac.type == e1000_pch_spt)
4468                                 hsflctl.regval =
4469                                     er32flash(ICH_FLASH_HSFSTS) >> 16;
4470                         else
4471                                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4472
4473                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4474                         if (hw->mac.type == e1000_pch_spt)
4475                                 ew32flash(ICH_FLASH_HSFSTS,
4476                                           hsflctl.regval << 16);
4477                         else
4478                                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4479
4480                         /* Write the last 24 bits of an index within the
4481                          * block into Flash Linear address field in Flash
4482                          * Address.
4483                          */
4484                         flash_linear_addr += (j * sector_size);
4485                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4486
4487                         ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4488                         if (!ret_val)
4489                                 break;
4490
4491                         /* Check if FCERR is set to 1.  If 1,
4492                          * clear it and try the whole sequence
4493                          * a few more times else Done
4494                          */
4495                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4496                         if (hsfsts.hsf_status.flcerr)
4497                                 /* repeat for some time before giving up */
4498                                 continue;
4499                         else if (!hsfsts.hsf_status.flcdone)
4500                                 return ret_val;
4501                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4502         }
4503
4504         return 0;
4505 }
4506
4507 /**
4508  *  e1000_valid_led_default_ich8lan - Set the default LED settings
4509  *  @hw: pointer to the HW structure
4510  *  @data: Pointer to the LED settings
4511  *
4512  *  Reads the LED default settings from the NVM to data.  If the NVM LED
4513  *  settings is all 0's or F's, set the LED default to a valid LED default
4514  *  setting.
4515  **/
4516 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4517 {
4518         s32 ret_val;
4519
4520         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
4521         if (ret_val) {
4522                 e_dbg("NVM Read Error\n");
4523                 return ret_val;
4524         }
4525
4526         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4527                 *data = ID_LED_DEFAULT_ICH8LAN;
4528
4529         return 0;
4530 }
4531
4532 /**
4533  *  e1000_id_led_init_pchlan - store LED configurations
4534  *  @hw: pointer to the HW structure
4535  *
4536  *  PCH does not control LEDs via the LEDCTL register, rather it uses
4537  *  the PHY LED configuration register.
4538  *
4539  *  PCH also does not have an "always on" or "always off" mode which
4540  *  complicates the ID feature.  Instead of using the "on" mode to indicate
4541  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
4542  *  use "link_up" mode.  The LEDs will still ID on request if there is no
4543  *  link based on logic in e1000_led_[on|off]_pchlan().
4544  **/
4545 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4546 {
4547         struct e1000_mac_info *mac = &hw->mac;
4548         s32 ret_val;
4549         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4550         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4551         u16 data, i, temp, shift;
4552
4553         /* Get default ID LED modes */
4554         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4555         if (ret_val)
4556                 return ret_val;
4557
4558         mac->ledctl_default = er32(LEDCTL);
4559         mac->ledctl_mode1 = mac->ledctl_default;
4560         mac->ledctl_mode2 = mac->ledctl_default;
4561
4562         for (i = 0; i < 4; i++) {
4563                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4564                 shift = (i * 5);
4565                 switch (temp) {
4566                 case ID_LED_ON1_DEF2:
4567                 case ID_LED_ON1_ON2:
4568                 case ID_LED_ON1_OFF2:
4569                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4570                         mac->ledctl_mode1 |= (ledctl_on << shift);
4571                         break;
4572                 case ID_LED_OFF1_DEF2:
4573                 case ID_LED_OFF1_ON2:
4574                 case ID_LED_OFF1_OFF2:
4575                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4576                         mac->ledctl_mode1 |= (ledctl_off << shift);
4577                         break;
4578                 default:
4579                         /* Do nothing */
4580                         break;
4581                 }
4582                 switch (temp) {
4583                 case ID_LED_DEF1_ON2:
4584                 case ID_LED_ON1_ON2:
4585                 case ID_LED_OFF1_ON2:
4586                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4587                         mac->ledctl_mode2 |= (ledctl_on << shift);
4588                         break;
4589                 case ID_LED_DEF1_OFF2:
4590                 case ID_LED_ON1_OFF2:
4591                 case ID_LED_OFF1_OFF2:
4592                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4593                         mac->ledctl_mode2 |= (ledctl_off << shift);
4594                         break;
4595                 default:
4596                         /* Do nothing */
4597                         break;
4598                 }
4599         }
4600
4601         return 0;
4602 }
4603
4604 /**
4605  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4606  *  @hw: pointer to the HW structure
4607  *
4608  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4609  *  register, so the the bus width is hard coded.
4610  **/
4611 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4612 {
4613         struct e1000_bus_info *bus = &hw->bus;
4614         s32 ret_val;
4615
4616         ret_val = e1000e_get_bus_info_pcie(hw);
4617
4618         /* ICH devices are "PCI Express"-ish.  They have
4619          * a configuration space, but do not contain
4620          * PCI Express Capability registers, so bus width
4621          * must be hardcoded.
4622          */
4623         if (bus->width == e1000_bus_width_unknown)
4624                 bus->width = e1000_bus_width_pcie_x1;
4625
4626         return ret_val;
4627 }
4628
4629 /**
4630  *  e1000_reset_hw_ich8lan - Reset the hardware
4631  *  @hw: pointer to the HW structure
4632  *
4633  *  Does a full reset of the hardware which includes a reset of the PHY and
4634  *  MAC.
4635  **/
4636 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4637 {
4638         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4639         u16 kum_cfg;
4640         u32 ctrl, reg;
4641         s32 ret_val;
4642
4643         /* Prevent the PCI-E bus from sticking if there is no TLP connection
4644          * on the last TLP read/write transaction when MAC is reset.
4645          */
4646         ret_val = e1000e_disable_pcie_master(hw);
4647         if (ret_val)
4648                 e_dbg("PCI-E Master disable polling has failed.\n");
4649
4650         e_dbg("Masking off all interrupts\n");
4651         ew32(IMC, 0xffffffff);
4652
4653         /* Disable the Transmit and Receive units.  Then delay to allow
4654          * any pending transactions to complete before we hit the MAC
4655          * with the global reset.
4656          */
4657         ew32(RCTL, 0);
4658         ew32(TCTL, E1000_TCTL_PSP);
4659         e1e_flush();
4660
4661         usleep_range(10000, 20000);
4662
4663         /* Workaround for ICH8 bit corruption issue in FIFO memory */
4664         if (hw->mac.type == e1000_ich8lan) {
4665                 /* Set Tx and Rx buffer allocation to 8k apiece. */
4666                 ew32(PBA, E1000_PBA_8K);
4667                 /* Set Packet Buffer Size to 16k. */
4668                 ew32(PBS, E1000_PBS_16K);
4669         }
4670
4671         if (hw->mac.type == e1000_pchlan) {
4672                 /* Save the NVM K1 bit setting */
4673                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4674                 if (ret_val)
4675                         return ret_val;
4676
4677                 if (kum_cfg & E1000_NVM_K1_ENABLE)
4678                         dev_spec->nvm_k1_enabled = true;
4679                 else
4680                         dev_spec->nvm_k1_enabled = false;
4681         }
4682
4683         ctrl = er32(CTRL);
4684
4685         if (!hw->phy.ops.check_reset_block(hw)) {
4686                 /* Full-chip reset requires MAC and PHY reset at the same
4687                  * time to make sure the interface between MAC and the
4688                  * external PHY is reset.
4689                  */
4690                 ctrl |= E1000_CTRL_PHY_RST;
4691
4692                 /* Gate automatic PHY configuration by hardware on
4693                  * non-managed 82579
4694                  */
4695                 if ((hw->mac.type == e1000_pch2lan) &&
4696                     !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
4697                         e1000_gate_hw_phy_config_ich8lan(hw, true);
4698         }
4699         ret_val = e1000_acquire_swflag_ich8lan(hw);
4700         e_dbg("Issuing a global reset to ich8lan\n");
4701         ew32(CTRL, (ctrl | E1000_CTRL_RST));
4702         /* cannot issue a flush here because it hangs the hardware */
4703         msleep(20);
4704
4705         /* Set Phy Config Counter to 50msec */
4706         if (hw->mac.type == e1000_pch2lan) {
4707                 reg = er32(FEXTNVM3);
4708                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4709                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4710                 ew32(FEXTNVM3, reg);
4711         }
4712
4713         if (!ret_val)
4714                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
4715
4716         if (ctrl & E1000_CTRL_PHY_RST) {
4717                 ret_val = hw->phy.ops.get_cfg_done(hw);
4718                 if (ret_val)
4719                         return ret_val;
4720
4721                 ret_val = e1000_post_phy_reset_ich8lan(hw);
4722                 if (ret_val)
4723                         return ret_val;
4724         }
4725
4726         /* For PCH, this write will make sure that any noise
4727          * will be detected as a CRC error and be dropped rather than show up
4728          * as a bad packet to the DMA engine.
4729          */
4730         if (hw->mac.type == e1000_pchlan)
4731                 ew32(CRC_OFFSET, 0x65656565);
4732
4733         ew32(IMC, 0xffffffff);
4734         er32(ICR);
4735
4736         reg = er32(KABGTXD);
4737         reg |= E1000_KABGTXD_BGSQLBIAS;
4738         ew32(KABGTXD, reg);
4739
4740         return 0;
4741 }
4742
4743 /**
4744  *  e1000_init_hw_ich8lan - Initialize the hardware
4745  *  @hw: pointer to the HW structure
4746  *
4747  *  Prepares the hardware for transmit and receive by doing the following:
4748  *   - initialize hardware bits
4749  *   - initialize LED identification
4750  *   - setup receive address registers
4751  *   - setup flow control
4752  *   - setup transmit descriptors
4753  *   - clear statistics
4754  **/
4755 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4756 {
4757         struct e1000_mac_info *mac = &hw->mac;
4758         u32 ctrl_ext, txdctl, snoop;
4759         s32 ret_val;
4760         u16 i;
4761
4762         e1000_initialize_hw_bits_ich8lan(hw);
4763
4764         /* Initialize identification LED */
4765         ret_val = mac->ops.id_led_init(hw);
4766         /* An error is not fatal and we should not stop init due to this */
4767         if (ret_val)
4768                 e_dbg("Error initializing identification LED\n");
4769
4770         /* Setup the receive address. */
4771         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
4772
4773         /* Zero out the Multicast HASH table */
4774         e_dbg("Zeroing the MTA\n");
4775         for (i = 0; i < mac->mta_reg_count; i++)
4776                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4777
4778         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4779          * the ME.  Disable wakeup by clearing the host wakeup bit.
4780          * Reset the phy after disabling host wakeup to reset the Rx buffer.
4781          */
4782         if (hw->phy.type == e1000_phy_82578) {
4783                 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
4784                 i &= ~BM_WUC_HOST_WU_BIT;
4785                 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
4786                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4787                 if (ret_val)
4788                         return ret_val;
4789         }
4790
4791         /* Setup link and flow control */
4792         ret_val = mac->ops.setup_link(hw);
4793
4794         /* Set the transmit descriptor write-back policy for both queues */
4795         txdctl = er32(TXDCTL(0));
4796         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4797                   E1000_TXDCTL_FULL_TX_DESC_WB);
4798         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4799                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4800         ew32(TXDCTL(0), txdctl);
4801         txdctl = er32(TXDCTL(1));
4802         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4803                   E1000_TXDCTL_FULL_TX_DESC_WB);
4804         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4805                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4806         ew32(TXDCTL(1), txdctl);
4807
4808         /* ICH8 has opposite polarity of no_snoop bits.
4809          * By default, we should use snoop behavior.
4810          */
4811         if (mac->type == e1000_ich8lan)
4812                 snoop = PCIE_ICH8_SNOOP_ALL;
4813         else
4814                 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
4815         e1000e_set_pcie_no_snoop(hw, snoop);
4816
4817         ctrl_ext = er32(CTRL_EXT);
4818         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4819         ew32(CTRL_EXT, ctrl_ext);
4820
4821         /* Clear all of the statistics registers (clear on read).  It is
4822          * important that we do this after we have tried to establish link
4823          * because the symbol error count will increment wildly if there
4824          * is no link.
4825          */
4826         e1000_clear_hw_cntrs_ich8lan(hw);
4827
4828         return ret_val;
4829 }
4830
4831 /**
4832  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4833  *  @hw: pointer to the HW structure
4834  *
4835  *  Sets/Clears required hardware bits necessary for correctly setting up the
4836  *  hardware for transmit and receive.
4837  **/
4838 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4839 {
4840         u32 reg;
4841
4842         /* Extended Device Control */
4843         reg = er32(CTRL_EXT);
4844         reg |= BIT(22);
4845         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4846         if (hw->mac.type >= e1000_pchlan)
4847                 reg |= E1000_CTRL_EXT_PHYPDEN;
4848         ew32(CTRL_EXT, reg);
4849
4850         /* Transmit Descriptor Control 0 */
4851         reg = er32(TXDCTL(0));
4852         reg |= BIT(22);
4853         ew32(TXDCTL(0), reg);
4854
4855         /* Transmit Descriptor Control 1 */
4856         reg = er32(TXDCTL(1));
4857         reg |= BIT(22);
4858         ew32(TXDCTL(1), reg);
4859
4860         /* Transmit Arbitration Control 0 */
4861         reg = er32(TARC(0));
4862         if (hw->mac.type == e1000_ich8lan)
4863                 reg |= BIT(28) | BIT(29);
4864         reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27);
4865         ew32(TARC(0), reg);
4866
4867         /* Transmit Arbitration Control 1 */
4868         reg = er32(TARC(1));
4869         if (er32(TCTL) & E1000_TCTL_MULR)
4870                 reg &= ~BIT(28);
4871         else
4872                 reg |= BIT(28);
4873         reg |= BIT(24) | BIT(26) | BIT(30);
4874         ew32(TARC(1), reg);
4875
4876         /* Device Status */
4877         if (hw->mac.type == e1000_ich8lan) {
4878                 reg = er32(STATUS);
4879                 reg &= ~BIT(31);
4880                 ew32(STATUS, reg);
4881         }
4882
4883         /* work-around descriptor data corruption issue during nfs v2 udp
4884          * traffic, just disable the nfs filtering capability
4885          */
4886         reg = er32(RFCTL);
4887         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4888
4889         /* Disable IPv6 extension header parsing because some malformed
4890          * IPv6 headers can hang the Rx.
4891          */
4892         if (hw->mac.type == e1000_ich8lan)
4893                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4894         ew32(RFCTL, reg);
4895
4896         /* Enable ECC on Lynxpoint */
4897         if ((hw->mac.type == e1000_pch_lpt) ||
4898             (hw->mac.type == e1000_pch_spt)) {
4899                 reg = er32(PBECCSTS);
4900                 reg |= E1000_PBECCSTS_ECC_ENABLE;
4901                 ew32(PBECCSTS, reg);
4902
4903                 reg = er32(CTRL);
4904                 reg |= E1000_CTRL_MEHE;
4905                 ew32(CTRL, reg);
4906         }
4907 }
4908
4909 /**
4910  *  e1000_setup_link_ich8lan - Setup flow control and link settings
4911  *  @hw: pointer to the HW structure
4912  *
4913  *  Determines which flow control settings to use, then configures flow
4914  *  control.  Calls the appropriate media-specific link configuration
4915  *  function.  Assuming the adapter has a valid link partner, a valid link
4916  *  should be established.  Assumes the hardware has previously been reset
4917  *  and the transmitter and receiver are not enabled.
4918  **/
4919 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4920 {
4921         s32 ret_val;
4922
4923         if (hw->phy.ops.check_reset_block(hw))
4924                 return 0;
4925
4926         /* ICH parts do not have a word in the NVM to determine
4927          * the default flow control setting, so we explicitly
4928          * set it to full.
4929          */
4930         if (hw->fc.requested_mode == e1000_fc_default) {
4931                 /* Workaround h/w hang when Tx flow control enabled */
4932                 if (hw->mac.type == e1000_pchlan)
4933                         hw->fc.requested_mode = e1000_fc_rx_pause;
4934                 else
4935                         hw->fc.requested_mode = e1000_fc_full;
4936         }
4937
4938         /* Save off the requested flow control mode for use later.  Depending
4939          * on the link partner's capabilities, we may or may not use this mode.
4940          */
4941         hw->fc.current_mode = hw->fc.requested_mode;
4942
4943         e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
4944
4945         /* Continue to configure the copper link. */
4946         ret_val = hw->mac.ops.setup_physical_interface(hw);
4947         if (ret_val)
4948                 return ret_val;
4949
4950         ew32(FCTTV, hw->fc.pause_time);
4951         if ((hw->phy.type == e1000_phy_82578) ||
4952             (hw->phy.type == e1000_phy_82579) ||
4953             (hw->phy.type == e1000_phy_i217) ||
4954             (hw->phy.type == e1000_phy_82577)) {
4955                 ew32(FCRTV_PCH, hw->fc.refresh_time);
4956
4957                 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
4958                                    hw->fc.pause_time);
4959                 if (ret_val)
4960                         return ret_val;
4961         }
4962
4963         return e1000e_set_fc_watermarks(hw);
4964 }
4965
4966 /**
4967  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4968  *  @hw: pointer to the HW structure
4969  *
4970  *  Configures the kumeran interface to the PHY to wait the appropriate time
4971  *  when polling the PHY, then call the generic setup_copper_link to finish
4972  *  configuring the copper link.
4973  **/
4974 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
4975 {
4976         u32 ctrl;
4977         s32 ret_val;
4978         u16 reg_data;
4979
4980         ctrl = er32(CTRL);
4981         ctrl |= E1000_CTRL_SLU;
4982         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4983         ew32(CTRL, ctrl);
4984
4985         /* Set the mac to wait the maximum time between each iteration
4986          * and increase the max iterations when polling the phy;
4987          * this fixes erroneous timeouts at 10Mbps.
4988          */
4989         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
4990         if (ret_val)
4991                 return ret_val;
4992         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
4993                                        &reg_data);
4994         if (ret_val)
4995                 return ret_val;
4996         reg_data |= 0x3F;
4997         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
4998                                         reg_data);
4999         if (ret_val)
5000                 return ret_val;
5001
5002         switch (hw->phy.type) {
5003         case e1000_phy_igp_3:
5004                 ret_val = e1000e_copper_link_setup_igp(hw);
5005                 if (ret_val)
5006                         return ret_val;
5007                 break;
5008         case e1000_phy_bm:
5009         case e1000_phy_82578:
5010                 ret_val = e1000e_copper_link_setup_m88(hw);
5011                 if (ret_val)
5012                         return ret_val;
5013                 break;
5014         case e1000_phy_82577:
5015         case e1000_phy_82579:
5016                 ret_val = e1000_copper_link_setup_82577(hw);
5017                 if (ret_val)
5018                         return ret_val;
5019                 break;
5020         case e1000_phy_ife:
5021                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
5022                 if (ret_val)
5023                         return ret_val;
5024
5025                 reg_data &= ~IFE_PMC_AUTO_MDIX;
5026
5027                 switch (hw->phy.mdix) {
5028                 case 1:
5029                         reg_data &= ~IFE_PMC_FORCE_MDIX;
5030                         break;
5031                 case 2:
5032                         reg_data |= IFE_PMC_FORCE_MDIX;
5033                         break;
5034                 case 0:
5035                 default:
5036                         reg_data |= IFE_PMC_AUTO_MDIX;
5037                         break;
5038                 }
5039                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
5040                 if (ret_val)
5041                         return ret_val;
5042                 break;
5043         default:
5044                 break;
5045         }
5046
5047         return e1000e_setup_copper_link(hw);
5048 }
5049
5050 /**
5051  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5052  *  @hw: pointer to the HW structure
5053  *
5054  *  Calls the PHY specific link setup function and then calls the
5055  *  generic setup_copper_link to finish configuring the link for
5056  *  Lynxpoint PCH devices
5057  **/
5058 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5059 {
5060         u32 ctrl;
5061         s32 ret_val;
5062
5063         ctrl = er32(CTRL);
5064         ctrl |= E1000_CTRL_SLU;
5065         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5066         ew32(CTRL, ctrl);
5067
5068         ret_val = e1000_copper_link_setup_82577(hw);
5069         if (ret_val)
5070                 return ret_val;
5071
5072         return e1000e_setup_copper_link(hw);
5073 }
5074
5075 /**
5076  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5077  *  @hw: pointer to the HW structure
5078  *  @speed: pointer to store current link speed
5079  *  @duplex: pointer to store the current link duplex
5080  *
5081  *  Calls the generic get_speed_and_duplex to retrieve the current link
5082  *  information and then calls the Kumeran lock loss workaround for links at
5083  *  gigabit speeds.
5084  **/
5085 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5086                                           u16 *duplex)
5087 {
5088         s32 ret_val;
5089
5090         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
5091         if (ret_val)
5092                 return ret_val;
5093
5094         if ((hw->mac.type == e1000_ich8lan) &&
5095             (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
5096                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5097         }
5098
5099         return ret_val;
5100 }
5101
5102 /**
5103  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5104  *  @hw: pointer to the HW structure
5105  *
5106  *  Work-around for 82566 Kumeran PCS lock loss:
5107  *  On link status change (i.e. PCI reset, speed change) and link is up and
5108  *  speed is gigabit-
5109  *    0) if workaround is optionally disabled do nothing
5110  *    1) wait 1ms for Kumeran link to come up
5111  *    2) check Kumeran Diagnostic register PCS lock loss bit
5112  *    3) if not set the link is locked (all is good), otherwise...
5113  *    4) reset the PHY
5114  *    5) repeat up to 10 times
5115  *  Note: this is only called for IGP3 copper when speed is 1gb.
5116  **/
5117 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5118 {
5119         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5120         u32 phy_ctrl;
5121         s32 ret_val;
5122         u16 i, data;
5123         bool link;
5124
5125         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5126                 return 0;
5127
5128         /* Make sure link is up before proceeding.  If not just return.
5129          * Attempting this while link is negotiating fouled up link
5130          * stability
5131          */
5132         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
5133         if (!link)
5134                 return 0;
5135
5136         for (i = 0; i < 10; i++) {
5137                 /* read once to clear */
5138                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5139                 if (ret_val)
5140                         return ret_val;
5141                 /* and again to get new status */
5142                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5143                 if (ret_val)
5144                         return ret_val;
5145
5146                 /* check for PCS lock */
5147                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5148                         return 0;
5149
5150                 /* Issue PHY reset */
5151                 e1000_phy_hw_reset(hw);
5152                 mdelay(5);
5153         }
5154         /* Disable GigE link negotiation */
5155         phy_ctrl = er32(PHY_CTRL);
5156         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5157                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5158         ew32(PHY_CTRL, phy_ctrl);
5159
5160         /* Call gig speed drop workaround on Gig disable before accessing
5161          * any PHY registers
5162          */
5163         e1000e_gig_downshift_workaround_ich8lan(hw);
5164
5165         /* unable to acquire PCS lock */
5166         return -E1000_ERR_PHY;
5167 }
5168
5169 /**
5170  *  e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5171  *  @hw: pointer to the HW structure
5172  *  @state: boolean value used to set the current Kumeran workaround state
5173  *
5174  *  If ICH8, set the current Kumeran workaround state (enabled - true
5175  *  /disabled - false).
5176  **/
5177 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5178                                                   bool state)
5179 {
5180         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5181
5182         if (hw->mac.type != e1000_ich8lan) {
5183                 e_dbg("Workaround applies to ICH8 only.\n");
5184                 return;
5185         }
5186
5187         dev_spec->kmrn_lock_loss_workaround_enabled = state;
5188 }
5189
5190 /**
5191  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5192  *  @hw: pointer to the HW structure
5193  *
5194  *  Workaround for 82566 power-down on D3 entry:
5195  *    1) disable gigabit link
5196  *    2) write VR power-down enable
5197  *    3) read it back
5198  *  Continue if successful, else issue LCD reset and repeat
5199  **/
5200 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5201 {
5202         u32 reg;
5203         u16 data;
5204         u8 retry = 0;
5205
5206         if (hw->phy.type != e1000_phy_igp_3)
5207                 return;
5208
5209         /* Try the workaround twice (if needed) */
5210         do {
5211                 /* Disable link */
5212                 reg = er32(PHY_CTRL);
5213                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5214                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5215                 ew32(PHY_CTRL, reg);
5216
5217                 /* Call gig speed drop workaround on Gig disable before
5218                  * accessing any PHY registers
5219                  */
5220                 if (hw->mac.type == e1000_ich8lan)
5221                         e1000e_gig_downshift_workaround_ich8lan(hw);
5222
5223                 /* Write VR power-down enable */
5224                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5225                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5226                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5227
5228                 /* Read it back and test */
5229                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5230                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5231                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5232                         break;
5233
5234                 /* Issue PHY reset and repeat at most one more time */
5235                 reg = er32(CTRL);
5236                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
5237                 retry++;
5238         } while (retry);
5239 }
5240
5241 /**
5242  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5243  *  @hw: pointer to the HW structure
5244  *
5245  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5246  *  LPLU, Gig disable, MDIC PHY reset):
5247  *    1) Set Kumeran Near-end loopback
5248  *    2) Clear Kumeran Near-end loopback
5249  *  Should only be called for ICH8[m] devices with any 1G Phy.
5250  **/
5251 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5252 {
5253         s32 ret_val;
5254         u16 reg_data;
5255
5256         if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
5257                 return;
5258
5259         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5260                                        &reg_data);
5261         if (ret_val)
5262                 return;
5263         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5264         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5265                                         reg_data);
5266         if (ret_val)
5267                 return;
5268         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5269         e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
5270 }
5271
5272 /**
5273  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5274  *  @hw: pointer to the HW structure
5275  *
5276  *  During S0 to Sx transition, it is possible the link remains at gig
5277  *  instead of negotiating to a lower speed.  Before going to Sx, set
5278  *  'Gig Disable' to force link speed negotiation to a lower speed based on
5279  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
5280  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5281  *  needs to be written.
5282  *  Parts that support (and are linked to a partner which support) EEE in
5283  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5284  *  than 10Mbps w/o EEE.
5285  **/
5286 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5287 {
5288         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5289         u32 phy_ctrl;
5290         s32 ret_val;
5291
5292         phy_ctrl = er32(PHY_CTRL);
5293         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5294
5295         if (hw->phy.type == e1000_phy_i217) {
5296                 u16 phy_reg, device_id = hw->adapter->pdev->device;
5297
5298                 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5299                     (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5300                     (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5301                     (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5302                     (hw->mac.type == e1000_pch_spt)) {
5303                         u32 fextnvm6 = er32(FEXTNVM6);
5304
5305                         ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5306                 }
5307
5308                 ret_val = hw->phy.ops.acquire(hw);
5309                 if (ret_val)
5310                         goto out;
5311
5312                 if (!dev_spec->eee_disable) {
5313                         u16 eee_advert;
5314
5315                         ret_val =
5316                             e1000_read_emi_reg_locked(hw,
5317                                                       I217_EEE_ADVERTISEMENT,
5318                                                       &eee_advert);
5319                         if (ret_val)
5320                                 goto release;
5321
5322                         /* Disable LPLU if both link partners support 100BaseT
5323                          * EEE and 100Full is advertised on both ends of the
5324                          * link, and enable Auto Enable LPI since there will
5325                          * be no driver to enable LPI while in Sx.
5326                          */
5327                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5328                             (dev_spec->eee_lp_ability &
5329                              I82579_EEE_100_SUPPORTED) &&
5330                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5331                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5332                                               E1000_PHY_CTRL_NOND0A_LPLU);
5333
5334                                 /* Set Auto Enable LPI after link up */
5335                                 e1e_rphy_locked(hw,
5336                                                 I217_LPI_GPIO_CTRL, &phy_reg);
5337                                 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5338                                 e1e_wphy_locked(hw,
5339                                                 I217_LPI_GPIO_CTRL, phy_reg);
5340                         }
5341                 }
5342
5343                 /* For i217 Intel Rapid Start Technology support,
5344                  * when the system is going into Sx and no manageability engine
5345                  * is present, the driver must configure proxy to reset only on
5346                  * power good.  LPI (Low Power Idle) state must also reset only
5347                  * on power good, as well as the MTA (Multicast table array).
5348                  * The SMBus release must also be disabled on LCD reset.
5349                  */
5350                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5351                         /* Enable proxy to reset only on power good. */
5352                         e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
5353                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5354                         e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
5355
5356                         /* Set bit enable LPI (EEE) to reset only on
5357                          * power good.
5358                          */
5359                         e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
5360                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5361                         e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
5362
5363                         /* Disable the SMB release on LCD reset. */
5364                         e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5365                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5366                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5367                 }
5368
5369                 /* Enable MTA to reset for Intel Rapid Start Technology
5370                  * Support
5371                  */
5372                 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5373                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5374                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5375
5376 release:
5377                 hw->phy.ops.release(hw);
5378         }
5379 out:
5380         ew32(PHY_CTRL, phy_ctrl);
5381
5382         if (hw->mac.type == e1000_ich8lan)
5383                 e1000e_gig_downshift_workaround_ich8lan(hw);
5384
5385         if (hw->mac.type >= e1000_pchlan) {
5386                 e1000_oem_bits_config_ich8lan(hw, false);
5387
5388                 /* Reset PHY to activate OEM bits on 82577/8 */
5389                 if (hw->mac.type == e1000_pchlan)
5390                         e1000e_phy_hw_reset_generic(hw);
5391
5392                 ret_val = hw->phy.ops.acquire(hw);
5393                 if (ret_val)
5394                         return;
5395                 e1000_write_smbus_addr(hw);
5396                 hw->phy.ops.release(hw);
5397         }
5398 }
5399
5400 /**
5401  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5402  *  @hw: pointer to the HW structure
5403  *
5404  *  During Sx to S0 transitions on non-managed devices or managed devices
5405  *  on which PHY resets are not blocked, if the PHY registers cannot be
5406  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
5407  *  the PHY.
5408  *  On i217, setup Intel Rapid Start Technology.
5409  **/
5410 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5411 {
5412         s32 ret_val;
5413
5414         if (hw->mac.type < e1000_pch2lan)
5415                 return;
5416
5417         ret_val = e1000_init_phy_workarounds_pchlan(hw);
5418         if (ret_val) {
5419                 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
5420                 return;
5421         }
5422
5423         /* For i217 Intel Rapid Start Technology support when the system
5424          * is transitioning from Sx and no manageability engine is present
5425          * configure SMBus to restore on reset, disable proxy, and enable
5426          * the reset on MTA (Multicast table array).
5427          */
5428         if (hw->phy.type == e1000_phy_i217) {
5429                 u16 phy_reg;
5430
5431                 ret_val = hw->phy.ops.acquire(hw);
5432                 if (ret_val) {
5433                         e_dbg("Failed to setup iRST\n");
5434                         return;
5435                 }
5436
5437                 /* Clear Auto Enable LPI after link up */
5438                 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5439                 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5440                 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5441
5442                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5443                         /* Restore clear on SMB if no manageability engine
5444                          * is present
5445                          */
5446                         ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5447                         if (ret_val)
5448                                 goto release;
5449                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5450                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5451
5452                         /* Disable Proxy */
5453                         e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
5454                 }
5455                 /* Enable reset on MTA */
5456                 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5457                 if (ret_val)
5458                         goto release;
5459                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5460                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5461 release:
5462                 if (ret_val)
5463                         e_dbg("Error %d in resume workarounds\n", ret_val);
5464                 hw->phy.ops.release(hw);
5465         }
5466 }
5467
5468 /**
5469  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
5470  *  @hw: pointer to the HW structure
5471  *
5472  *  Return the LED back to the default configuration.
5473  **/
5474 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5475 {
5476         if (hw->phy.type == e1000_phy_ife)
5477                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
5478
5479         ew32(LEDCTL, hw->mac.ledctl_default);
5480         return 0;
5481 }
5482
5483 /**
5484  *  e1000_led_on_ich8lan - Turn LEDs on
5485  *  @hw: pointer to the HW structure
5486  *
5487  *  Turn on the LEDs.
5488  **/
5489 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5490 {
5491         if (hw->phy.type == e1000_phy_ife)
5492                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5493                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5494
5495         ew32(LEDCTL, hw->mac.ledctl_mode2);
5496         return 0;
5497 }
5498
5499 /**
5500  *  e1000_led_off_ich8lan - Turn LEDs off
5501  *  @hw: pointer to the HW structure
5502  *
5503  *  Turn off the LEDs.
5504  **/
5505 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5506 {
5507         if (hw->phy.type == e1000_phy_ife)
5508                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5509                                 (IFE_PSCL_PROBE_MODE |
5510                                  IFE_PSCL_PROBE_LEDS_OFF));
5511
5512         ew32(LEDCTL, hw->mac.ledctl_mode1);
5513         return 0;
5514 }
5515
5516 /**
5517  *  e1000_setup_led_pchlan - Configures SW controllable LED
5518  *  @hw: pointer to the HW structure
5519  *
5520  *  This prepares the SW controllable LED for use.
5521  **/
5522 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5523 {
5524         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
5525 }
5526
5527 /**
5528  *  e1000_cleanup_led_pchlan - Restore the default LED operation
5529  *  @hw: pointer to the HW structure
5530  *
5531  *  Return the LED back to the default configuration.
5532  **/
5533 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5534 {
5535         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
5536 }
5537
5538 /**
5539  *  e1000_led_on_pchlan - Turn LEDs on
5540  *  @hw: pointer to the HW structure
5541  *
5542  *  Turn on the LEDs.
5543  **/
5544 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5545 {
5546         u16 data = (u16)hw->mac.ledctl_mode2;
5547         u32 i, led;
5548
5549         /* If no link, then turn LED on by setting the invert bit
5550          * for each LED that's mode is "link_up" in ledctl_mode2.
5551          */
5552         if (!(er32(STATUS) & E1000_STATUS_LU)) {
5553                 for (i = 0; i < 3; i++) {
5554                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5555                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5556                             E1000_LEDCTL_MODE_LINK_UP)
5557                                 continue;
5558                         if (led & E1000_PHY_LED0_IVRT)
5559                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5560                         else
5561                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5562                 }
5563         }
5564
5565         return e1e_wphy(hw, HV_LED_CONFIG, data);
5566 }
5567
5568 /**
5569  *  e1000_led_off_pchlan - Turn LEDs off
5570  *  @hw: pointer to the HW structure
5571  *
5572  *  Turn off the LEDs.
5573  **/
5574 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5575 {
5576         u16 data = (u16)hw->mac.ledctl_mode1;
5577         u32 i, led;
5578
5579         /* If no link, then turn LED off by clearing the invert bit
5580          * for each LED that's mode is "link_up" in ledctl_mode1.
5581          */
5582         if (!(er32(STATUS) & E1000_STATUS_LU)) {
5583                 for (i = 0; i < 3; i++) {
5584                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5585                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5586                             E1000_LEDCTL_MODE_LINK_UP)
5587                                 continue;
5588                         if (led & E1000_PHY_LED0_IVRT)
5589                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5590                         else
5591                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5592                 }
5593         }
5594
5595         return e1e_wphy(hw, HV_LED_CONFIG, data);
5596 }
5597
5598 /**
5599  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5600  *  @hw: pointer to the HW structure
5601  *
5602  *  Read appropriate register for the config done bit for completion status
5603  *  and configure the PHY through s/w for EEPROM-less parts.
5604  *
5605  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
5606  *  config done bit, so only an error is logged and continues.  If we were
5607  *  to return with error, EEPROM-less silicon would not be able to be reset
5608  *  or change link.
5609  **/
5610 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5611 {
5612         s32 ret_val = 0;
5613         u32 bank = 0;
5614         u32 status;
5615
5616         e1000e_get_cfg_done_generic(hw);
5617
5618         /* Wait for indication from h/w that it has completed basic config */
5619         if (hw->mac.type >= e1000_ich10lan) {
5620                 e1000_lan_init_done_ich8lan(hw);
5621         } else {
5622                 ret_val = e1000e_get_auto_rd_done(hw);
5623                 if (ret_val) {
5624                         /* When auto config read does not complete, do not
5625                          * return with an error. This can happen in situations
5626                          * where there is no eeprom and prevents getting link.
5627                          */
5628                         e_dbg("Auto Read Done did not complete\n");
5629                         ret_val = 0;
5630                 }
5631         }
5632
5633         /* Clear PHY Reset Asserted bit */
5634         status = er32(STATUS);
5635         if (status & E1000_STATUS_PHYRA)
5636                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
5637         else
5638                 e_dbg("PHY Reset Asserted not set - needs delay\n");
5639
5640         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5641         if (hw->mac.type <= e1000_ich9lan) {
5642                 if (!(er32(EECD) & E1000_EECD_PRES) &&
5643                     (hw->phy.type == e1000_phy_igp_3)) {
5644                         e1000e_phy_init_script_igp3(hw);
5645                 }
5646         } else {
5647                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5648                         /* Maybe we should do a basic PHY config */
5649                         e_dbg("EEPROM not present\n");
5650                         ret_val = -E1000_ERR_CONFIG;
5651                 }
5652         }
5653
5654         return ret_val;
5655 }
5656
5657 /**
5658  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5659  * @hw: pointer to the HW structure
5660  *
5661  * In the case of a PHY power down to save power, or to turn off link during a
5662  * driver unload, or wake on lan is not enabled, remove the link.
5663  **/
5664 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5665 {
5666         /* If the management interface is not enabled, then power down */
5667         if (!(hw->mac.ops.check_mng_mode(hw) ||
5668               hw->phy.ops.check_reset_block(hw)))
5669                 e1000_power_down_phy_copper(hw);
5670 }
5671
5672 /**
5673  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5674  *  @hw: pointer to the HW structure
5675  *
5676  *  Clears hardware counters specific to the silicon family and calls
5677  *  clear_hw_cntrs_generic to clear all general purpose counters.
5678  **/
5679 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5680 {
5681         u16 phy_data;
5682         s32 ret_val;
5683
5684         e1000e_clear_hw_cntrs_base(hw);
5685
5686         er32(ALGNERRC);
5687         er32(RXERRC);
5688         er32(TNCRS);
5689         er32(CEXTERR);
5690         er32(TSCTC);
5691         er32(TSCTFC);
5692
5693         er32(MGTPRC);
5694         er32(MGTPDC);
5695         er32(MGTPTC);
5696
5697         er32(IAC);
5698         er32(ICRXOC);
5699
5700         /* Clear PHY statistics registers */
5701         if ((hw->phy.type == e1000_phy_82578) ||
5702             (hw->phy.type == e1000_phy_82579) ||
5703             (hw->phy.type == e1000_phy_i217) ||
5704             (hw->phy.type == e1000_phy_82577)) {
5705                 ret_val = hw->phy.ops.acquire(hw);
5706                 if (ret_val)
5707                         return;
5708                 ret_val = hw->phy.ops.set_page(hw,
5709                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
5710                 if (ret_val)
5711                         goto release;
5712                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5713                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5714                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5715                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5716                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5717                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5718                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5719                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5720                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5721                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5722                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5723                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5724                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5725                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5726 release:
5727                 hw->phy.ops.release(hw);
5728         }
5729 }
5730
5731 static const struct e1000_mac_operations ich8_mac_ops = {
5732         /* check_mng_mode dependent on mac type */
5733         .check_for_link         = e1000_check_for_copper_link_ich8lan,
5734         /* cleanup_led dependent on mac type */
5735         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
5736         .get_bus_info           = e1000_get_bus_info_ich8lan,
5737         .set_lan_id             = e1000_set_lan_id_single_port,
5738         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
5739         /* led_on dependent on mac type */
5740         /* led_off dependent on mac type */
5741         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
5742         .reset_hw               = e1000_reset_hw_ich8lan,
5743         .init_hw                = e1000_init_hw_ich8lan,
5744         .setup_link             = e1000_setup_link_ich8lan,
5745         .setup_physical_interface = e1000_setup_copper_link_ich8lan,
5746         /* id_led_init dependent on mac type */
5747         .config_collision_dist  = e1000e_config_collision_dist_generic,
5748         .rar_set                = e1000e_rar_set_generic,
5749         .rar_get_count          = e1000e_rar_get_count_generic,
5750 };
5751
5752 static const struct e1000_phy_operations ich8_phy_ops = {
5753         .acquire                = e1000_acquire_swflag_ich8lan,
5754         .check_reset_block      = e1000_check_reset_block_ich8lan,
5755         .commit                 = NULL,
5756         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
5757         .get_cable_length       = e1000e_get_cable_length_igp_2,
5758         .read_reg               = e1000e_read_phy_reg_igp,
5759         .release                = e1000_release_swflag_ich8lan,
5760         .reset                  = e1000_phy_hw_reset_ich8lan,
5761         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
5762         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
5763         .write_reg              = e1000e_write_phy_reg_igp,
5764 };
5765
5766 static const struct e1000_nvm_operations ich8_nvm_ops = {
5767         .acquire                = e1000_acquire_nvm_ich8lan,
5768         .read                   = e1000_read_nvm_ich8lan,
5769         .release                = e1000_release_nvm_ich8lan,
5770         .reload                 = e1000e_reload_nvm_generic,
5771         .update                 = e1000_update_nvm_checksum_ich8lan,
5772         .valid_led_default      = e1000_valid_led_default_ich8lan,
5773         .validate               = e1000_validate_nvm_checksum_ich8lan,
5774         .write                  = e1000_write_nvm_ich8lan,
5775 };
5776
5777 static const struct e1000_nvm_operations spt_nvm_ops = {
5778         .acquire                = e1000_acquire_nvm_ich8lan,
5779         .release                = e1000_release_nvm_ich8lan,
5780         .read                   = e1000_read_nvm_spt,
5781         .update                 = e1000_update_nvm_checksum_spt,
5782         .reload                 = e1000e_reload_nvm_generic,
5783         .valid_led_default      = e1000_valid_led_default_ich8lan,
5784         .validate               = e1000_validate_nvm_checksum_ich8lan,
5785         .write                  = e1000_write_nvm_ich8lan,
5786 };
5787
5788 const struct e1000_info e1000_ich8_info = {
5789         .mac                    = e1000_ich8lan,
5790         .flags                  = FLAG_HAS_WOL
5791                                   | FLAG_IS_ICH
5792                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5793                                   | FLAG_HAS_AMT
5794                                   | FLAG_HAS_FLASH
5795                                   | FLAG_APME_IN_WUC,
5796         .pba                    = 8,
5797         .max_hw_frame_size      = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
5798         .get_variants           = e1000_get_variants_ich8lan,
5799         .mac_ops                = &ich8_mac_ops,
5800         .phy_ops                = &ich8_phy_ops,
5801         .nvm_ops                = &ich8_nvm_ops,
5802 };
5803
5804 const struct e1000_info e1000_ich9_info = {
5805         .mac                    = e1000_ich9lan,
5806         .flags                  = FLAG_HAS_JUMBO_FRAMES
5807                                   | FLAG_IS_ICH
5808                                   | FLAG_HAS_WOL
5809                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5810                                   | FLAG_HAS_AMT
5811                                   | FLAG_HAS_FLASH
5812                                   | FLAG_APME_IN_WUC,
5813         .pba                    = 18,
5814         .max_hw_frame_size      = DEFAULT_JUMBO,
5815         .get_variants           = e1000_get_variants_ich8lan,
5816         .mac_ops                = &ich8_mac_ops,
5817         .phy_ops                = &ich8_phy_ops,
5818         .nvm_ops                = &ich8_nvm_ops,
5819 };
5820
5821 const struct e1000_info e1000_ich10_info = {
5822         .mac                    = e1000_ich10lan,
5823         .flags                  = FLAG_HAS_JUMBO_FRAMES
5824                                   | FLAG_IS_ICH
5825                                   | FLAG_HAS_WOL
5826                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5827                                   | FLAG_HAS_AMT
5828                                   | FLAG_HAS_FLASH
5829                                   | FLAG_APME_IN_WUC,
5830         .pba                    = 18,
5831         .max_hw_frame_size      = DEFAULT_JUMBO,
5832         .get_variants           = e1000_get_variants_ich8lan,
5833         .mac_ops                = &ich8_mac_ops,
5834         .phy_ops                = &ich8_phy_ops,
5835         .nvm_ops                = &ich8_nvm_ops,
5836 };
5837
5838 const struct e1000_info e1000_pch_info = {
5839         .mac                    = e1000_pchlan,
5840         .flags                  = FLAG_IS_ICH
5841                                   | FLAG_HAS_WOL
5842                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5843                                   | FLAG_HAS_AMT
5844                                   | FLAG_HAS_FLASH
5845                                   | FLAG_HAS_JUMBO_FRAMES
5846                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
5847                                   | FLAG_APME_IN_WUC,
5848         .flags2                 = FLAG2_HAS_PHY_STATS,
5849         .pba                    = 26,
5850         .max_hw_frame_size      = 4096,
5851         .get_variants           = e1000_get_variants_ich8lan,
5852         .mac_ops                = &ich8_mac_ops,
5853         .phy_ops                = &ich8_phy_ops,
5854         .nvm_ops                = &ich8_nvm_ops,
5855 };
5856
5857 const struct e1000_info e1000_pch2_info = {
5858         .mac                    = e1000_pch2lan,
5859         .flags                  = FLAG_IS_ICH
5860                                   | FLAG_HAS_WOL
5861                                   | FLAG_HAS_HW_TIMESTAMP
5862                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5863                                   | FLAG_HAS_AMT
5864                                   | FLAG_HAS_FLASH
5865                                   | FLAG_HAS_JUMBO_FRAMES
5866                                   | FLAG_APME_IN_WUC,
5867         .flags2                 = FLAG2_HAS_PHY_STATS
5868                                   | FLAG2_HAS_EEE,
5869         .pba                    = 26,
5870         .max_hw_frame_size      = 9022,
5871         .get_variants           = e1000_get_variants_ich8lan,
5872         .mac_ops                = &ich8_mac_ops,
5873         .phy_ops                = &ich8_phy_ops,
5874         .nvm_ops                = &ich8_nvm_ops,
5875 };
5876
5877 const struct e1000_info e1000_pch_lpt_info = {
5878         .mac                    = e1000_pch_lpt,
5879         .flags                  = FLAG_IS_ICH
5880                                   | FLAG_HAS_WOL
5881                                   | FLAG_HAS_HW_TIMESTAMP
5882                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5883                                   | FLAG_HAS_AMT
5884                                   | FLAG_HAS_FLASH
5885                                   | FLAG_HAS_JUMBO_FRAMES
5886                                   | FLAG_APME_IN_WUC,
5887         .flags2                 = FLAG2_HAS_PHY_STATS
5888                                   | FLAG2_HAS_EEE,
5889         .pba                    = 26,
5890         .max_hw_frame_size      = 9022,
5891         .get_variants           = e1000_get_variants_ich8lan,
5892         .mac_ops                = &ich8_mac_ops,
5893         .phy_ops                = &ich8_phy_ops,
5894         .nvm_ops                = &ich8_nvm_ops,
5895 };
5896
5897 const struct e1000_info e1000_pch_spt_info = {
5898         .mac                    = e1000_pch_spt,
5899         .flags                  = FLAG_IS_ICH
5900                                   | FLAG_HAS_WOL
5901                                   | FLAG_HAS_HW_TIMESTAMP
5902                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5903                                   | FLAG_HAS_AMT
5904                                   | FLAG_HAS_FLASH
5905                                   | FLAG_HAS_JUMBO_FRAMES
5906                                   | FLAG_APME_IN_WUC,
5907         .flags2                 = FLAG2_HAS_PHY_STATS
5908                                   | FLAG2_HAS_EEE,
5909         .pba                    = 26,
5910         .max_hw_frame_size      = 9022,
5911         .get_variants           = e1000_get_variants_ich8lan,
5912         .mac_ops                = &ich8_mac_ops,
5913         .phy_ops                = &ich8_phy_ops,
5914         .nvm_ops                = &spt_nvm_ops,
5915 };