1 /* Intel PRO/1000 Linux driver
2 * Copyright(c) 1999 - 2015 Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
16 * Contact Information:
17 * Linux NICS <linux.nics@intel.com>
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 /* Linux PRO/1000 Ethernet Driver main header file */
27 #include <linux/bitops.h>
28 #include <linux/types.h>
29 #include <linux/timer.h>
30 #include <linux/workqueue.h>
32 #include <linux/netdevice.h>
33 #include <linux/pci.h>
34 #include <linux/pci-aspm.h>
35 #include <linux/crc32.h>
36 #include <linux/if_vlan.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/ptp_classify.h>
41 #include <linux/mii.h>
42 #include <linux/mdio.h>
43 #include <linux/pm_qos.h>
48 #define e_dbg(format, arg...) \
49 netdev_dbg(hw->adapter->netdev, format, ## arg)
50 #define e_err(format, arg...) \
51 netdev_err(adapter->netdev, format, ## arg)
52 #define e_info(format, arg...) \
53 netdev_info(adapter->netdev, format, ## arg)
54 #define e_warn(format, arg...) \
55 netdev_warn(adapter->netdev, format, ## arg)
56 #define e_notice(format, arg...) \
57 netdev_notice(adapter->netdev, format, ## arg)
59 /* Interrupt modes, as used by the IntMode parameter */
60 #define E1000E_INT_MODE_LEGACY 0
61 #define E1000E_INT_MODE_MSI 1
62 #define E1000E_INT_MODE_MSIX 2
64 /* Tx/Rx descriptor defines */
65 #define E1000_DEFAULT_TXD 256
66 #define E1000_MAX_TXD 4096
67 #define E1000_MIN_TXD 64
69 #define E1000_DEFAULT_RXD 256
70 #define E1000_MAX_RXD 4096
71 #define E1000_MIN_RXD 64
73 #define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */
74 #define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */
76 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
78 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
79 /* How many Rx Buffers do we bundle into one write to the hardware ? */
80 #define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
82 #define AUTO_ALL_MODES 0
83 #define E1000_EEPROM_APME 0x0400
85 #define E1000_MNG_VLAN_NONE (-1)
87 #define DEFAULT_JUMBO 9234
89 /* Time to wait before putting the device into D3 if there's no link (in ms). */
90 #define LINK_TIMEOUT 100
92 /* Count for polling __E1000_RESET condition every 10-20msec.
93 * Experimentation has shown the reset can take approximately 210msec.
95 #define E1000_CHECK_RESET_COUNT 25
97 #define DEFAULT_RDTR 0
98 #define DEFAULT_RADV 8
99 #define BURST_RDTR 0x20
100 #define BURST_RADV 0x20
101 #define PCICFG_DESC_RING_STATUS 0xe4
102 #define FLUSH_DESC_REQUIRED 0x100
104 /* in the case of WTHRESH, it appears at least the 82571/2 hardware
105 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
106 * WTHRESH=4, so a setting of 5 gives the most efficient bus
107 * utilization but to avoid possible Tx stalls, set it to 1
109 #define E1000_TXDCTL_DMA_BURST_ENABLE \
110 (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \
111 E1000_TXDCTL_COUNT_DESC | \
112 (1u << 16) | /* wthresh must be +1 more than desired */\
113 (1u << 8) | /* hthresh */ \
116 #define E1000_RXDCTL_DMA_BURST_ENABLE \
117 (0x01000000 | /* set descriptor granularity */ \
118 (4u << 16) | /* set writeback threshold */ \
119 (4u << 8) | /* set prefetch threshold */ \
120 0x20) /* set hthresh */
122 #define E1000_TIDV_FPD BIT(31)
123 #define E1000_RDTR_FPD BIT(31)
141 struct e1000_ps_page {
143 u64 dma; /* must be u64 - written to hw */
146 /* wrappers around a pointer to a socket buffer,
147 * so a DMA handle can be stored along with the buffer
149 struct e1000_buffer {
155 unsigned long time_stamp;
159 unsigned int bytecount;
164 /* arrays of page information for packet split */
165 struct e1000_ps_page *ps_pages;
172 struct e1000_adapter *adapter; /* back pointer to adapter */
173 void *desc; /* pointer to ring memory */
174 dma_addr_t dma; /* phys address of ring */
175 unsigned int size; /* length of ring in bytes */
176 unsigned int count; /* number of desc. in ring */
184 /* array of buffer information structs */
185 struct e1000_buffer *buffer_info;
187 char name[IFNAMSIZ + 5];
190 void __iomem *itr_register;
193 struct sk_buff *rx_skb_top;
196 /* PHY register snapshot values */
197 struct e1000_phy_regs {
198 u16 bmcr; /* basic mode control register */
199 u16 bmsr; /* basic mode status register */
200 u16 advertise; /* auto-negotiation advertisement */
201 u16 lpa; /* link partner ability register */
202 u16 expansion; /* auto-negotiation expansion reg */
203 u16 ctrl1000; /* 1000BASE-T control register */
204 u16 stat1000; /* 1000BASE-T status register */
205 u16 estatus; /* extended status register */
208 /* board specific private data structure */
209 struct e1000_adapter {
210 struct timer_list watchdog_timer;
211 struct timer_list phy_info_timer;
212 struct timer_list blink_timer;
214 struct work_struct reset_task;
215 struct work_struct watchdog_task;
217 const struct e1000_info *ei;
219 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
227 /* track device up/down/testing state */
230 /* Interrupt Throttle Rate */
236 /* Tx - one ring per active queue */
237 struct e1000_ring *tx_ring ____cacheline_aligned_in_smp;
240 struct napi_struct napi;
242 unsigned int uncorr_errors; /* uncorrectable ECC errors */
243 unsigned int corr_errors; /* correctable ECC errors */
244 unsigned int restart_queue;
248 bool tx_hang_recheck;
249 u8 tx_timeout_factor;
252 u32 tx_abs_int_delay;
254 unsigned int total_tx_bytes;
255 unsigned int total_tx_packets;
256 unsigned int total_rx_bytes;
257 unsigned int total_rx_packets;
264 u32 tx_timeout_count;
269 u32 tx_hwtstamp_timeouts;
272 bool (*clean_rx)(struct e1000_ring *ring, int *work_done,
273 int work_to_do) ____cacheline_aligned_in_smp;
274 void (*alloc_rx_buf)(struct e1000_ring *ring, int cleaned_count,
276 struct e1000_ring *rx_ring;
279 u32 rx_abs_int_delay;
287 u32 alloc_rx_buff_failed;
289 u32 rx_hwtstamp_cleared;
291 unsigned int rx_ps_pages;
296 /* OS defined structs */
297 struct net_device *netdev;
298 struct pci_dev *pdev;
300 /* structs defined in e1000_hw.h */
303 spinlock_t stats64_lock; /* protects statistics counters */
304 struct e1000_hw_stats stats;
305 struct e1000_phy_info phy_info;
306 struct e1000_phy_stats phy_stats;
308 /* Snapshot of PHY registers */
309 struct e1000_phy_regs phy_regs;
311 struct e1000_ring test_tx_ring;
312 struct e1000_ring test_rx_ring;
316 unsigned int num_vectors;
317 struct msix_entry *msix_entries;
324 u32 max_hw_frame_size;
330 struct work_struct downshift_task;
331 struct work_struct update_phy_task;
332 struct work_struct print_hang_task;
339 struct hwtstamp_config hwtstamp_config;
340 struct delayed_work systim_overflow_work;
341 struct sk_buff *tx_hwtstamp_skb;
342 unsigned long tx_hwtstamp_start;
343 struct work_struct tx_hwtstamp_work;
344 spinlock_t systim_lock; /* protects SYSTIML/H regsters */
345 struct cyclecounter cc;
346 struct timecounter tc;
347 struct ptp_clock *ptp_clock;
348 struct ptp_clock_info ptp_clock_info;
349 struct pm_qos_request pm_qos_req;
356 enum e1000_mac_type mac;
360 u32 max_hw_frame_size;
361 s32 (*get_variants)(struct e1000_adapter *);
362 const struct e1000_mac_operations *mac_ops;
363 const struct e1000_phy_operations *phy_ops;
364 const struct e1000_nvm_operations *nvm_ops;
367 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca);
369 /* The system time is maintained by a 64-bit counter comprised of the 32-bit
370 * SYSTIMH and SYSTIML registers. How the counter increments (and therefore
371 * its resolution) is based on the contents of the TIMINCA register - it
372 * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0).
373 * For the best accuracy, the incperiod should be as small as possible. The
374 * incvalue is scaled by a factor as large as possible (while still fitting
375 * in bits 23:0) so that relatively small clock corrections can be made.
377 * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of
378 * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n)
379 * bits to count nanoseconds leaving the rest for fractional nonseconds.
381 #define INCVALUE_96MHz 125
382 #define INCVALUE_SHIFT_96MHz 17
383 #define INCPERIOD_SHIFT_96MHz 2
384 #define INCPERIOD_96MHz (12 >> INCPERIOD_SHIFT_96MHz)
386 #define INCVALUE_25MHz 40
387 #define INCVALUE_SHIFT_25MHz 18
388 #define INCPERIOD_25MHz 1
390 #define INCVALUE_24MHz 125
391 #define INCVALUE_SHIFT_24MHz 14
392 #define INCPERIOD_24MHz 3
394 /* Another drawback of scaling the incvalue by a large factor is the
395 * 64-bit SYSTIM register overflows more quickly. This is dealt with
396 * by simply reading the clock before it overflows.
398 * Clock ns bits Overflows after
399 * ~~~~~~ ~~~~~~~ ~~~~~~~~~~~~~~~
400 * 96MHz 47-bit 2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs
401 * 25MHz 46-bit 2^46 / 10^9 / 3600 = 19.55 hours
403 #define E1000_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 60 * 4)
404 #define E1000_MAX_82574_SYSTIM_REREADS 50
405 #define E1000_82574_SYSTIM_EPSILON (1ULL << 35ULL)
407 /* hardware capability, feature, and workaround flags */
408 #define FLAG_HAS_AMT BIT(0)
409 #define FLAG_HAS_FLASH BIT(1)
410 #define FLAG_HAS_HW_VLAN_FILTER BIT(2)
411 #define FLAG_HAS_WOL BIT(3)
412 /* reserved BIT(4) */
413 #define FLAG_HAS_CTRLEXT_ON_LOAD BIT(5)
414 #define FLAG_HAS_SWSM_ON_LOAD BIT(6)
415 #define FLAG_HAS_JUMBO_FRAMES BIT(7)
416 #define FLAG_READ_ONLY_NVM BIT(8)
417 #define FLAG_IS_ICH BIT(9)
418 #define FLAG_HAS_MSIX BIT(10)
419 #define FLAG_HAS_SMART_POWER_DOWN BIT(11)
420 #define FLAG_IS_QUAD_PORT_A BIT(12)
421 #define FLAG_IS_QUAD_PORT BIT(13)
422 #define FLAG_HAS_HW_TIMESTAMP BIT(14)
423 #define FLAG_APME_IN_WUC BIT(15)
424 #define FLAG_APME_IN_CTRL3 BIT(16)
425 #define FLAG_APME_CHECK_PORT_B BIT(17)
426 #define FLAG_DISABLE_FC_PAUSE_TIME BIT(18)
427 #define FLAG_NO_WAKE_UCAST BIT(19)
428 #define FLAG_MNG_PT_ENABLED BIT(20)
429 #define FLAG_RESET_OVERWRITES_LAA BIT(21)
430 #define FLAG_TARC_SPEED_MODE_BIT BIT(22)
431 #define FLAG_TARC_SET_BIT_ZERO BIT(23)
432 #define FLAG_RX_NEEDS_RESTART BIT(24)
433 #define FLAG_LSC_GIG_SPEED_DROP BIT(25)
434 #define FLAG_SMART_POWER_DOWN BIT(26)
435 #define FLAG_MSI_ENABLED BIT(27)
436 /* reserved BIT(28) */
437 #define FLAG_TSO_FORCE BIT(29)
438 #define FLAG_RESTART_NOW BIT(30)
439 #define FLAG_MSI_TEST_FAILED BIT(31)
441 #define FLAG2_CRC_STRIPPING BIT(0)
442 #define FLAG2_HAS_PHY_WAKEUP BIT(1)
443 #define FLAG2_IS_DISCARDING BIT(2)
444 #define FLAG2_DISABLE_ASPM_L1 BIT(3)
445 #define FLAG2_HAS_PHY_STATS BIT(4)
446 #define FLAG2_HAS_EEE BIT(5)
447 #define FLAG2_DMA_BURST BIT(6)
448 #define FLAG2_DISABLE_ASPM_L0S BIT(7)
449 #define FLAG2_DISABLE_AIM BIT(8)
450 #define FLAG2_CHECK_PHY_HANG BIT(9)
451 #define FLAG2_NO_DISABLE_RX BIT(10)
452 #define FLAG2_PCIM2PCI_ARBITER_WA BIT(11)
453 #define FLAG2_DFLT_CRC_STRIPPING BIT(12)
454 #define FLAG2_CHECK_RX_HWTSTAMP BIT(13)
456 #define E1000_RX_DESC_PS(R, i) \
457 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
458 #define E1000_RX_DESC_EXT(R, i) \
459 (&(((union e1000_rx_desc_extended *)((R).desc))[i]))
460 #define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
461 #define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
462 #define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc)
467 __E1000_ACCESS_SHARED_RESOURCE,
475 latency_invalid = 255
478 extern char e1000e_driver_name[];
479 extern const char e1000e_driver_version[];
481 void e1000e_check_options(struct e1000_adapter *adapter);
482 void e1000e_set_ethtool_ops(struct net_device *netdev);
484 int e1000e_open(struct net_device *netdev);
485 int e1000e_close(struct net_device *netdev);
486 void e1000e_up(struct e1000_adapter *adapter);
487 void e1000e_down(struct e1000_adapter *adapter, bool reset);
488 void e1000e_reinit_locked(struct e1000_adapter *adapter);
489 void e1000e_reset(struct e1000_adapter *adapter);
490 void e1000e_power_up_phy(struct e1000_adapter *adapter);
491 int e1000e_setup_rx_resources(struct e1000_ring *ring);
492 int e1000e_setup_tx_resources(struct e1000_ring *ring);
493 void e1000e_free_rx_resources(struct e1000_ring *ring);
494 void e1000e_free_tx_resources(struct e1000_ring *ring);
495 struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
496 struct rtnl_link_stats64 *stats);
497 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
498 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
499 void e1000e_get_hw_control(struct e1000_adapter *adapter);
500 void e1000e_release_hw_control(struct e1000_adapter *adapter);
501 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr);
503 extern unsigned int copybreak;
505 extern const struct e1000_info e1000_82571_info;
506 extern const struct e1000_info e1000_82572_info;
507 extern const struct e1000_info e1000_82573_info;
508 extern const struct e1000_info e1000_82574_info;
509 extern const struct e1000_info e1000_82583_info;
510 extern const struct e1000_info e1000_ich8_info;
511 extern const struct e1000_info e1000_ich9_info;
512 extern const struct e1000_info e1000_ich10_info;
513 extern const struct e1000_info e1000_pch_info;
514 extern const struct e1000_info e1000_pch2_info;
515 extern const struct e1000_info e1000_pch_lpt_info;
516 extern const struct e1000_info e1000_pch_spt_info;
517 extern const struct e1000_info e1000_es2_info;
519 void e1000e_ptp_init(struct e1000_adapter *adapter);
520 void e1000e_ptp_remove(struct e1000_adapter *adapter);
522 static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
524 return hw->phy.ops.reset(hw);
527 static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
529 return hw->phy.ops.read_reg(hw, offset, data);
532 static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data)
534 return hw->phy.ops.read_reg_locked(hw, offset, data);
537 static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
539 return hw->phy.ops.write_reg(hw, offset, data);
542 static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data)
544 return hw->phy.ops.write_reg_locked(hw, offset, data);
547 void e1000e_reload_nvm_generic(struct e1000_hw *hw);
549 static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
551 if (hw->mac.ops.read_mac_addr)
552 return hw->mac.ops.read_mac_addr(hw);
554 return e1000_read_mac_addr_generic(hw);
557 static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
559 return hw->nvm.ops.validate(hw);
562 static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
564 return hw->nvm.ops.update(hw);
567 static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words,
570 return hw->nvm.ops.read(hw, offset, words, data);
573 static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words,
576 return hw->nvm.ops.write(hw, offset, words, data);
579 static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
581 return hw->phy.ops.get_info(hw);
584 static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
586 return readl(hw->hw_addr + reg);
589 #define er32(reg) __er32(hw, E1000_##reg)
591 s32 __ew32_prepare(struct e1000_hw *hw);
592 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val);
594 #define ew32(reg, val) __ew32(hw, E1000_##reg, (val))
596 #define e1e_flush() er32(STATUS)
598 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
599 (__ew32((a), (reg + ((offset) << 2)), (value)))
601 #define E1000_READ_REG_ARRAY(a, reg, offset) \
602 (readl((a)->hw_addr + reg + ((offset) << 2)))
604 #endif /* _E1000_H_ */