drivers/net/ethernet/intel/e1000e/80003es2lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2012 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 80003ES2LAN Gigabit Ethernet Controller (Copper)
  31  * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
  32  */
  33
  34 #include "e1000.h"
  35
  36 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL       0x00
  37 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL        0x02
  38 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL         0x10
  39 #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE  0x1F
  40
  41 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS    0x0008
  42 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS    0x0800
  43 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING   0x0010
  44
  45 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
  46 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT   0x0000
  47 #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE          0x2000
  48
  49 #define E1000_KMRNCTRLSTA_OPMODE_MASK            0x000C
  50 #define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO     0x0004
  51
  52 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
  53 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN        0x00010000
  54
  55 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN       0x8
  56 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN     0x9
  57
  58 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
  59 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE   0x0002 /* 1=Reversal Disab. */
  60 #define GG82563_PSCR_CROSSOVER_MODE_MASK         0x0060
  61 #define GG82563_PSCR_CROSSOVER_MODE_MDI          0x0000 /* 00=Manual MDI */
  62 #define GG82563_PSCR_CROSSOVER_MODE_MDIX         0x0020 /* 01=Manual MDIX */
  63 #define GG82563_PSCR_CROSSOVER_MODE_AUTO         0x0060 /* 11=Auto crossover */
  64
  65 /* PHY Specific Control Register 2 (Page 0, Register 26) */
  66 #define GG82563_PSCR2_REVERSE_AUTO_NEG           0x2000
  67                                                 /* 1=Reverse Auto-Negotiation */
  68
  69 /* MAC Specific Control Register (Page 2, Register 21) */
  70 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
  71 #define GG82563_MSCR_TX_CLK_MASK                 0x0007
  72 #define GG82563_MSCR_TX_CLK_10MBPS_2_5           0x0004
  73 #define GG82563_MSCR_TX_CLK_100MBPS_25           0x0005
  74 #define GG82563_MSCR_TX_CLK_1000MBPS_25          0x0007
  75
  76 #define GG82563_MSCR_ASSERT_CRS_ON_TX            0x0010 /* 1=Assert */
  77
  78 /* DSP Distance Register (Page 5, Register 26) */
  79 #define GG82563_DSPD_CABLE_LENGTH                0x0007 /* 0 = <50M
  80                                                            1 = 50-80M
  81                                                            2 = 80-110M
  82                                                            3 = 110-140M
  83                                                            4 = >140M */
  84
  85 /* Kumeran Mode Control Register (Page 193, Register 16) */
  86 #define GG82563_KMCR_PASS_FALSE_CARRIER          0x0800
  87
  88 /* Max number of times Kumeran read/write should be validated */
  89 #define GG82563_MAX_KMRN_RETRY  0x5
  90
  91 /* Power Management Control Register (Page 193, Register 20) */
  92 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE      0x0001
  93                                            /* 1=Enable SERDES Electrical Idle */
  94
  95 /* In-Band Control Register (Page 194, Register 18) */
  96 #define GG82563_ICR_DIS_PADDING                  0x0010 /* Disable Padding */
  97
  98 /*
  99  * A table for the GG82563 cable length where the range is defined
 100  * with a lower bound at "index" and the upper bound at
 101  * "index + 5".
 102  */
 103 static const u16 e1000_gg82563_cable_length_table[] = {
 104          0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
 105 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
 106                 ARRAY_SIZE(e1000_gg82563_cable_length_table)
 107
 108 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
 109 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
 110 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
 111 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
 112 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
 113 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
 114 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
 115 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
 116 static s32  e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
 117                                             u16 *data);
 118 static s32  e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
 119                                              u16 data);
 120 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
 121
 122 /**
 123  *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
 124  *  @hw: pointer to the HW structure
 125  **/
 126 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
 127 {
 128         struct e1000_phy_info *phy = &hw->phy;
 129         s32 ret_val;
 130
 131         if (hw->phy.media_type != e1000_media_type_copper) {
 132                 phy->type       = e1000_phy_none;
 133                 return 0;
 134         } else {
 135                 phy->ops.power_up = e1000_power_up_phy_copper;
 136                 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
 137         }
 138
 139         phy->addr               = 1;
 140         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 141         phy->reset_delay_us      = 100;
 142         phy->type               = e1000_phy_gg82563;
 143
 144         /* This can only be done after all function pointers are setup. */
 145         ret_val = e1000e_get_phy_id(hw);
 146
 147         /* Verify phy id */
 148         if (phy->id != GG82563_E_PHY_ID)
 149                 return -E1000_ERR_PHY;
 150
 151         return ret_val;
 152 }
 153
 154 /**
 155  *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
 156  *  @hw: pointer to the HW structure
 157  **/
 158 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
 159 {
 160         struct e1000_nvm_info *nvm = &hw->nvm;
 161         u32 eecd = er32(EECD);
 162         u16 size;
 163
 164         nvm->opcode_bits        = 8;
 165         nvm->delay_usec  = 1;
 166         switch (nvm->override) {
 167         case e1000_nvm_override_spi_large:
 168                 nvm->page_size    = 32;
 169                 nvm->address_bits = 16;
 170                 break;
 171         case e1000_nvm_override_spi_small:
 172                 nvm->page_size    = 8;
 173                 nvm->address_bits = 8;
 174                 break;
 175         default:
 176                 nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 177                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 178                 break;
 179         }
 180
 181         nvm->type = e1000_nvm_eeprom_spi;
 182
 183         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 184                           E1000_EECD_SIZE_EX_SHIFT);
 185
 186         /*
 187          * Added to a constant, "size" becomes the left-shift value
 188          * for setting word_size.
 189          */
 190         size += NVM_WORD_SIZE_BASE_SHIFT;
 191
 192         /* EEPROM access above 16k is unsupported */
 193         if (size > 14)
 194                 size = 14;
 195         nvm->word_size  = 1 << size;
 196
 197         return 0;
 198 }
 199
 200 /**
 201  *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
 202  *  @hw: pointer to the HW structure
 203  **/
 204 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
 205 {
 206         struct e1000_mac_info *mac = &hw->mac;
 207
 208         /* Set media type and media-dependent function pointers */
 209         switch (hw->adapter->pdev->device) {
 210         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
 211                 hw->phy.media_type = e1000_media_type_internal_serdes;
 212                 mac->ops.check_for_link = e1000e_check_for_serdes_link;
 213                 mac->ops.setup_physical_interface =
 214                     e1000e_setup_fiber_serdes_link;
 215                 break;
 216         default:
 217                 hw->phy.media_type = e1000_media_type_copper;
 218                 mac->ops.check_for_link = e1000e_check_for_copper_link;
 219                 mac->ops.setup_physical_interface =
 220                     e1000_setup_copper_link_80003es2lan;
 221                 break;
 222         }
 223
 224         /* Set mta register count */
 225         mac->mta_reg_count = 128;
 226         /* Set rar entry count */
 227         mac->rar_entry_count = E1000_RAR_ENTRIES;
 228         /* FWSM register */
 229         mac->has_fwsm = true;
 230         /* ARC supported; valid only if manageability features are enabled. */
 231         mac->arc_subsystem_valid =
 232                 (er32(FWSM) & E1000_FWSM_MODE_MASK)
 233                         ? true : false;
 234         /* Adaptive IFS not supported */
 235         mac->adaptive_ifs = false;
 236
 237         /* set lan id for port to determine which phy lock to use */
 238         hw->mac.ops.set_lan_id(hw);
 239
 240         return 0;
 241 }
 242
 243 static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
 244 {
 245         struct e1000_hw *hw = &adapter->hw;
 246         s32 rc;
 247
 248         rc = e1000_init_mac_params_80003es2lan(hw);
 249         if (rc)
 250                 return rc;
 251
 252         rc = e1000_init_nvm_params_80003es2lan(hw);
 253         if (rc)
 254                 return rc;
 255
 256         rc = e1000_init_phy_params_80003es2lan(hw);
 257         if (rc)
 258                 return rc;
 259
 260         return 0;
 261 }
 262
 263 /**
 264  *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
 265  *  @hw: pointer to the HW structure
 266  *
 267  *  A wrapper to acquire access rights to the correct PHY.
 268  **/
 269 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
 270 {
 271         u16 mask;
 272
 273         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 274         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 275 }
 276
 277 /**
 278  *  e1000_release_phy_80003es2lan - Release rights to access PHY
 279  *  @hw: pointer to the HW structure
 280  *
 281  *  A wrapper to release access rights to the correct PHY.
 282  **/
 283 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
 284 {
 285         u16 mask;
 286
 287         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 288         e1000_release_swfw_sync_80003es2lan(hw, mask);
 289 }
 290
 291 /**
 292  *  e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register
 293  *  @hw: pointer to the HW structure
 294  *
 295  *  Acquire the semaphore to access the Kumeran interface.
 296  *
 297  **/
 298 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
 299 {
 300         u16 mask;
 301
 302         mask = E1000_SWFW_CSR_SM;
 303
 304         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 305 }
 306
 307 /**
 308  *  e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register
 309  *  @hw: pointer to the HW structure
 310  *
 311  *  Release the semaphore used to access the Kumeran interface
 312  **/
 313 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
 314 {
 315         u16 mask;
 316
 317         mask = E1000_SWFW_CSR_SM;
 318
 319         e1000_release_swfw_sync_80003es2lan(hw, mask);
 320 }
 321
 322 /**
 323  *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
 324  *  @hw: pointer to the HW structure
 325  *
 326  *  Acquire the semaphore to access the EEPROM.
 327  **/
 328 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
 329 {
 330         s32 ret_val;
 331
 332         ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 333         if (ret_val)
 334                 return ret_val;
 335
 336         ret_val = e1000e_acquire_nvm(hw);
 337
 338         if (ret_val)
 339                 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 340
 341         return ret_val;
 342 }
 343
 344 /**
 345  *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
 346  *  @hw: pointer to the HW structure
 347  *
 348  *  Release the semaphore used to access the EEPROM.
 349  **/
 350 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
 351 {
 352         e1000e_release_nvm(hw);
 353         e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 354 }
 355
 356 /**
 357  *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
 358  *  @hw: pointer to the HW structure
 359  *  @mask: specifies which semaphore to acquire
 360  *
 361  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
 362  *  will also specify which port we're acquiring the lock for.
 363  **/
 364 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 365 {
 366         u32 swfw_sync;
 367         u32 swmask = mask;
 368         u32 fwmask = mask << 16;
 369         s32 i = 0;
 370         s32 timeout = 50;
 371
 372         while (i < timeout) {
 373                 if (e1000e_get_hw_semaphore(hw))
 374                         return -E1000_ERR_SWFW_SYNC;
 375
 376                 swfw_sync = er32(SW_FW_SYNC);
 377                 if (!(swfw_sync & (fwmask | swmask)))
 378                         break;
 379
 380                 /*
 381                  * Firmware currently using resource (fwmask)
 382                  * or other software thread using resource (swmask)
 383                  */
 384                 e1000e_put_hw_semaphore(hw);
 385                 mdelay(5);
 386                 i++;
 387         }
 388
 389         if (i == timeout) {
 390                 e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
 391                 return -E1000_ERR_SWFW_SYNC;
 392         }
 393
 394         swfw_sync |= swmask;
 395         ew32(SW_FW_SYNC, swfw_sync);
 396
 397         e1000e_put_hw_semaphore(hw);
 398
 399         return 0;
 400 }
 401
 402 /**
 403  *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
 404  *  @hw: pointer to the HW structure
 405  *  @mask: specifies which semaphore to acquire
 406  *
 407  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
 408  *  will also specify which port we're releasing the lock for.
 409  **/
 410 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 411 {
 412         u32 swfw_sync;
 413
 414         while (e1000e_get_hw_semaphore(hw) != 0)
 415                 ; /* Empty */
 416
 417         swfw_sync = er32(SW_FW_SYNC);
 418         swfw_sync &= ~mask;
 419         ew32(SW_FW_SYNC, swfw_sync);
 420
 421         e1000e_put_hw_semaphore(hw);
 422 }
 423
 424 /**
 425  *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
 426  *  @hw: pointer to the HW structure
 427  *  @offset: offset of the register to read
 428  *  @data: pointer to the data returned from the operation
 429  *
 430  *  Read the GG82563 PHY register.
 431  **/
 432 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 433                                                   u32 offset, u16 *data)
 434 {
 435         s32 ret_val;
 436         u32 page_select;
 437         u16 temp;
 438
 439         ret_val = e1000_acquire_phy_80003es2lan(hw);
 440         if (ret_val)
 441                 return ret_val;
 442
 443         /* Select Configuration Page */
 444         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 445                 page_select = GG82563_PHY_PAGE_SELECT;
 446         } else {
 447                 /*
 448                  * Use Alternative Page Select register to access
 449                  * registers 30 and 31
 450                  */
 451                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 452         }
 453
 454         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 455         ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
 456         if (ret_val) {
 457                 e1000_release_phy_80003es2lan(hw);
 458                 return ret_val;
 459         }
 460
 461         if (hw->dev_spec.e80003es2lan.mdic_wa_enable == true) {
 462                 /*
 463                  * The "ready" bit in the MDIC register may be incorrectly set
 464                  * before the device has completed the "Page Select" MDI
 465                  * transaction.  So we wait 200us after each MDI command...
 466                  */
 467                 udelay(200);
 468
 469                 /* ...and verify the command was successful. */
 470                 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
 471
 472                 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 473                         ret_val = -E1000_ERR_PHY;
 474                         e1000_release_phy_80003es2lan(hw);
 475                         return ret_val;
 476                 }
 477
 478                 udelay(200);
 479
 480                 ret_val = e1000e_read_phy_reg_mdic(hw,
 481                                                   MAX_PHY_REG_ADDRESS & offset,
 482                                                   data);
 483
 484                 udelay(200);
 485         } else {
 486                 ret_val = e1000e_read_phy_reg_mdic(hw,
 487                                                   MAX_PHY_REG_ADDRESS & offset,
 488                                                   data);
 489         }
 490
 491         e1000_release_phy_80003es2lan(hw);
 492
 493         return ret_val;
 494 }
 495
 496 /**
 497  *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
 498  *  @hw: pointer to the HW structure
 499  *  @offset: offset of the register to read
 500  *  @data: value to write to the register
 501  *
 502  *  Write to the GG82563 PHY register.
 503  **/
 504 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 505                                                    u32 offset, u16 data)
 506 {
 507         s32 ret_val;
 508         u32 page_select;
 509         u16 temp;
 510
 511         ret_val = e1000_acquire_phy_80003es2lan(hw);
 512         if (ret_val)
 513                 return ret_val;
 514
 515         /* Select Configuration Page */
 516         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 517                 page_select = GG82563_PHY_PAGE_SELECT;
 518         } else {
 519                 /*
 520                  * Use Alternative Page Select register to access
 521                  * registers 30 and 31
 522                  */
 523                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 524         }
 525
 526         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 527         ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
 528         if (ret_val) {
 529                 e1000_release_phy_80003es2lan(hw);
 530                 return ret_val;
 531         }
 532
 533         if (hw->dev_spec.e80003es2lan.mdic_wa_enable == true) {
 534                 /*
 535                  * The "ready" bit in the MDIC register may be incorrectly set
 536                  * before the device has completed the "Page Select" MDI
 537                  * transaction.  So we wait 200us after each MDI command...
 538                  */
 539                 udelay(200);
 540
 541                 /* ...and verify the command was successful. */
 542                 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
 543
 544                 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 545                         e1000_release_phy_80003es2lan(hw);
 546                         return -E1000_ERR_PHY;
 547                 }
 548
 549                 udelay(200);
 550
 551                 ret_val = e1000e_write_phy_reg_mdic(hw,
 552                                                   MAX_PHY_REG_ADDRESS & offset,
 553                                                   data);
 554
 555                 udelay(200);
 556         } else {
 557                 ret_val = e1000e_write_phy_reg_mdic(hw,
 558                                                   MAX_PHY_REG_ADDRESS & offset,
 559                                                   data);
 560         }
 561
 562         e1000_release_phy_80003es2lan(hw);
 563
 564         return ret_val;
 565 }
 566
 567 /**
 568  *  e1000_write_nvm_80003es2lan - Write to ESB2 NVM
 569  *  @hw: pointer to the HW structure
 570  *  @offset: offset of the register to read
 571  *  @words: number of words to write
 572  *  @data: buffer of data to write to the NVM
 573  *
 574  *  Write "words" of data to the ESB2 NVM.
 575  **/
 576 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
 577                                        u16 words, u16 *data)
 578 {
 579         return e1000e_write_nvm_spi(hw, offset, words, data);
 580 }
 581
 582 /**
 583  *  e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
 584  *  @hw: pointer to the HW structure
 585  *
 586  *  Wait a specific amount of time for manageability processes to complete.
 587  *  This is a function pointer entry point called by the phy module.
 588  **/
 589 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
 590 {
 591         s32 timeout = PHY_CFG_TIMEOUT;
 592         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
 593
 594         if (hw->bus.func == 1)
 595                 mask = E1000_NVM_CFG_DONE_PORT_1;
 596
 597         while (timeout) {
 598                 if (er32(EEMNGCTL) & mask)
 599                         break;
 600                 usleep_range(1000, 2000);
 601                 timeout--;
 602         }
 603         if (!timeout) {
 604                 e_dbg("MNG configuration cycle has not completed.\n");
 605                 return -E1000_ERR_RESET;
 606         }
 607
 608         return 0;
 609 }
 610
 611 /**
 612  *  e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
 613  *  @hw: pointer to the HW structure
 614  *
 615  *  Force the speed and duplex settings onto the PHY.  This is a
 616  *  function pointer entry point called by the phy module.
 617  **/
 618 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
 619 {
 620         s32 ret_val;
 621         u16 phy_data;
 622         bool link;
 623
 624         /*
 625          * Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
 626          * forced whenever speed and duplex are forced.
 627          */
 628         ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
 629         if (ret_val)
 630                 return ret_val;
 631
 632         phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
 633         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
 634         if (ret_val)
 635                 return ret_val;
 636
 637         e_dbg("GG82563 PSCR: %X\n", phy_data);
 638
 639         ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
 640         if (ret_val)
 641                 return ret_val;
 642
 643         e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
 644
 645         /* Reset the phy to commit changes. */
 646         phy_data |= MII_CR_RESET;
 647
 648         ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
 649         if (ret_val)
 650                 return ret_val;
 651
 652         udelay(1);
 653
 654         if (hw->phy.autoneg_wait_to_complete) {
 655                 e_dbg("Waiting for forced speed/duplex link on GG82563 phy.\n");
 656
 657                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 658                                                      100000, &link);
 659                 if (ret_val)
 660                         return ret_val;
 661
 662                 if (!link) {
 663                         /*
 664                          * We didn't get link.
 665                          * Reset the DSP and cross our fingers.
 666                          */
 667                         ret_val = e1000e_phy_reset_dsp(hw);
 668                         if (ret_val)
 669                                 return ret_val;
 670                 }
 671
 672                 /* Try once more */
 673                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 674                                                      100000, &link);
 675                 if (ret_val)
 676                         return ret_val;
 677         }
 678
 679         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
 680         if (ret_val)
 681                 return ret_val;
 682
 683         /*
 684          * Resetting the phy means we need to verify the TX_CLK corresponds
 685          * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
 686          */
 687         phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
 688         if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
 689                 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
 690         else
 691                 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
 692
 693         /*
 694          * In addition, we must re-enable CRS on Tx for both half and full
 695          * duplex.
 696          */
 697         phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 698         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
 699
 700         return ret_val;
 701 }
 702
 703 /**
 704  *  e1000_get_cable_length_80003es2lan - Set approximate cable length
 705  *  @hw: pointer to the HW structure
 706  *
 707  *  Find the approximate cable length as measured by the GG82563 PHY.
 708  *  This is a function pointer entry point called by the phy module.
 709  **/
 710 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
 711 {
 712         struct e1000_phy_info *phy = &hw->phy;
 713         s32 ret_val = 0;
 714         u16 phy_data, index;
 715
 716         ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
 717         if (ret_val)
 718                 goto out;
 719
 720         index = phy_data & GG82563_DSPD_CABLE_LENGTH;
 721
 722         if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) {
 723                 ret_val = -E1000_ERR_PHY;
 724                 goto out;
 725         }
 726
 727         phy->min_cable_length = e1000_gg82563_cable_length_table[index];
 728         phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
 729
 730         phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
 731
 732 out:
 733         return ret_val;
 734 }
 735
 736 /**
 737  *  e1000_get_link_up_info_80003es2lan - Report speed and duplex
 738  *  @hw: pointer to the HW structure
 739  *  @speed: pointer to speed buffer
 740  *  @duplex: pointer to duplex buffer
 741  *
 742  *  Retrieve the current speed and duplex configuration.
 743  **/
 744 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
 745                                               u16 *duplex)
 746 {
 747         s32 ret_val;
 748
 749         if (hw->phy.media_type == e1000_media_type_copper) {
 750                 ret_val = e1000e_get_speed_and_duplex_copper(hw,
 751                                                                     speed,
 752                                                                     duplex);
 753                 hw->phy.ops.cfg_on_link_up(hw);
 754         } else {
 755                 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
 756                                                                   speed,
 757                                                                   duplex);
 758         }
 759
 760         return ret_val;
 761 }
 762
 763 /**
 764  *  e1000_reset_hw_80003es2lan - Reset the ESB2 controller
 765  *  @hw: pointer to the HW structure
 766  *
 767  *  Perform a global reset to the ESB2 controller.
 768  **/
 769 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
 770 {
 771         u32 ctrl;
 772         s32 ret_val;
 773
 774         /*
 775          * Prevent the PCI-E bus from sticking if there is no TLP connection
 776          * on the last TLP read/write transaction when MAC is reset.
 777          */
 778         ret_val = e1000e_disable_pcie_master(hw);
 779         if (ret_val)
 780                 e_dbg("PCI-E Master disable polling has failed.\n");
 781
 782         e_dbg("Masking off all interrupts\n");
 783         ew32(IMC, 0xffffffff);
 784
 785         ew32(RCTL, 0);
 786         ew32(TCTL, E1000_TCTL_PSP);
 787         e1e_flush();
 788
 789         usleep_range(10000, 20000);
 790
 791         ctrl = er32(CTRL);
 792
 793         ret_val = e1000_acquire_phy_80003es2lan(hw);
 794         e_dbg("Issuing a global reset to MAC\n");
 795         ew32(CTRL, ctrl | E1000_CTRL_RST);
 796         e1000_release_phy_80003es2lan(hw);
 797
 798         ret_val = e1000e_get_auto_rd_done(hw);
 799         if (ret_val)
 800                 /* We don't want to continue accessing MAC registers. */
 801                 return ret_val;
 802
 803         /* Clear any pending interrupt events. */
 804         ew32(IMC, 0xffffffff);
 805         er32(ICR);
 806
 807         ret_val = e1000_check_alt_mac_addr_generic(hw);
 808
 809         return ret_val;
 810 }
 811
 812 /**
 813  *  e1000_init_hw_80003es2lan - Initialize the ESB2 controller
 814  *  @hw: pointer to the HW structure
 815  *
 816  *  Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
 817  **/
 818 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
 819 {
 820         struct e1000_mac_info *mac = &hw->mac;
 821         u32 reg_data;
 822         s32 ret_val;
 823         u16 kum_reg_data;
 824         u16 i;
 825
 826         e1000_initialize_hw_bits_80003es2lan(hw);
 827
 828         /* Initialize identification LED */
 829         ret_val = e1000e_id_led_init(hw);
 830         if (ret_val)
 831                 e_dbg("Error initializing identification LED\n");
 832                 /* This is not fatal and we should not stop init due to this */
 833
 834         /* Disabling VLAN filtering */
 835         e_dbg("Initializing the IEEE VLAN\n");
 836         mac->ops.clear_vfta(hw);
 837
 838         /* Setup the receive address. */
 839         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
 840
 841         /* Zero out the Multicast HASH table */
 842         e_dbg("Zeroing the MTA\n");
 843         for (i = 0; i < mac->mta_reg_count; i++)
 844                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 845
 846         /* Setup link and flow control */
 847         ret_val = e1000e_setup_link(hw);
 848
 849         /* Disable IBIST slave mode (far-end loopback) */
 850         e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 851                                         &kum_reg_data);
 852         kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
 853         e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 854                                          kum_reg_data);
 855
 856         /* Set the transmit descriptor write-back policy */
 857         reg_data = er32(TXDCTL(0));
 858         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 859                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
 860         ew32(TXDCTL(0), reg_data);
 861
 862         /* ...for both queues. */
 863         reg_data = er32(TXDCTL(1));
 864         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 865                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
 866         ew32(TXDCTL(1), reg_data);
 867
 868         /* Enable retransmit on late collisions */
 869         reg_data = er32(TCTL);
 870         reg_data |= E1000_TCTL_RTLC;
 871         ew32(TCTL, reg_data);
 872
 873         /* Configure Gigabit Carry Extend Padding */
 874         reg_data = er32(TCTL_EXT);
 875         reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
 876         reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
 877         ew32(TCTL_EXT, reg_data);
 878
 879         /* Configure Transmit Inter-Packet Gap */
 880         reg_data = er32(TIPG);
 881         reg_data &= ~E1000_TIPG_IPGT_MASK;
 882         reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
 883         ew32(TIPG, reg_data);
 884
 885         reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
 886         reg_data &= ~0x00100000;
 887         E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
 888
 889         /* default to true to enable the MDIC W/A */
 890         hw->dev_spec.e80003es2lan.mdic_wa_enable = true;
 891
 892         ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
 893                                       E1000_KMRNCTRLSTA_OFFSET >>
 894                                       E1000_KMRNCTRLSTA_OFFSET_SHIFT,
 895                                       &i);
 896         if (!ret_val) {
 897                 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
 898                      E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
 899                         hw->dev_spec.e80003es2lan.mdic_wa_enable = false;
 900         }
 901
 902         /*
 903          * Clear all of the statistics registers (clear on read).  It is
 904          * important that we do this after we have tried to establish link
 905          * because the symbol error count will increment wildly if there
 906          * is no link.
 907          */
 908         e1000_clear_hw_cntrs_80003es2lan(hw);
 909
 910         return ret_val;
 911 }
 912
 913 /**
 914  *  e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
 915  *  @hw: pointer to the HW structure
 916  *
 917  *  Initializes required hardware-dependent bits needed for normal operation.
 918  **/
 919 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
 920 {
 921         u32 reg;
 922
 923         /* Transmit Descriptor Control 0 */
 924         reg = er32(TXDCTL(0));
 925         reg |= (1 << 22);
 926         ew32(TXDCTL(0), reg);
 927
 928         /* Transmit Descriptor Control 1 */
 929         reg = er32(TXDCTL(1));
 930         reg |= (1 << 22);
 931         ew32(TXDCTL(1), reg);
 932
 933         /* Transmit Arbitration Control 0 */
 934         reg = er32(TARC(0));
 935         reg &= ~(0xF << 27); /* 30:27 */
 936         if (hw->phy.media_type != e1000_media_type_copper)
 937                 reg &= ~(1 << 20);
 938         ew32(TARC(0), reg);
 939
 940         /* Transmit Arbitration Control 1 */
 941         reg = er32(TARC(1));
 942         if (er32(TCTL) & E1000_TCTL_MULR)
 943                 reg &= ~(1 << 28);
 944         else
 945                 reg |= (1 << 28);
 946         ew32(TARC(1), reg);
 947 }
 948
 949 /**
 950  *  e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
 951  *  @hw: pointer to the HW structure
 952  *
 953  *  Setup some GG82563 PHY registers for obtaining link
 954  **/
 955 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
 956 {
 957         struct e1000_phy_info *phy = &hw->phy;
 958         s32 ret_val;
 959         u32 ctrl_ext;
 960         u16 data;
 961
 962         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
 963         if (ret_val)
 964                 return ret_val;
 965
 966         data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 967         /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
 968         data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
 969
 970         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
 971         if (ret_val)
 972                 return ret_val;
 973
 974         /*
 975          * Options:
 976          *   MDI/MDI-X = 0 (default)
 977          *   0 - Auto for all speeds
 978          *   1 - MDI mode
 979          *   2 - MDI-X mode
 980          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
 981          */
 982         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
 983         if (ret_val)
 984                 return ret_val;
 985
 986         data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
 987
 988         switch (phy->mdix) {
 989         case 1:
 990                 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
 991                 break;
 992         case 2:
 993                 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
 994                 break;
 995         case 0:
 996         default:
 997                 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
 998                 break;
 999         }
1000
1001         /*
1002          * Options:
1003          *   disable_polarity_correction = 0 (default)
1004          *       Automatic Correction for Reversed Cable Polarity
1005          *   0 - Disabled
1006          *   1 - Enabled
1007          */
1008         data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1009         if (phy->disable_polarity_correction)
1010                 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1011
1012         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
1013         if (ret_val)
1014                 return ret_val;
1015
1016         /* SW Reset the PHY so all changes take effect */
1017         ret_val = e1000e_commit_phy(hw);
1018         if (ret_val) {
1019                 e_dbg("Error Resetting the PHY\n");
1020                 return ret_val;
1021         }
1022
1023         /* Bypass Rx and Tx FIFO's */
1024         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1025                                         E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
1026                                         E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1027                                         E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1028         if (ret_val)
1029                 return ret_val;
1030
1031         ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1032                                        E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1033                                        &data);
1034         if (ret_val)
1035                 return ret_val;
1036         data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1037         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1038                                         E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1039                                         data);
1040         if (ret_val)
1041                 return ret_val;
1042
1043         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1044         if (ret_val)
1045                 return ret_val;
1046
1047         data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1048         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
1049         if (ret_val)
1050                 return ret_val;
1051
1052         ctrl_ext = er32(CTRL_EXT);
1053         ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1054         ew32(CTRL_EXT, ctrl_ext);
1055
1056         ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1057         if (ret_val)
1058                 return ret_val;
1059
1060         /*
1061          * Do not init these registers when the HW is in IAMT mode, since the
1062          * firmware will have already initialized them.  We only initialize
1063          * them if the HW is not in IAMT mode.
1064          */
1065         if (!e1000e_check_mng_mode(hw)) {
1066                 /* Enable Electrical Idle on the PHY */
1067                 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1068                 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
1069                 if (ret_val)
1070                         return ret_val;
1071
1072                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
1073                 if (ret_val)
1074                         return ret_val;
1075
1076                 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1077                 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
1078                 if (ret_val)
1079                         return ret_val;
1080         }
1081
1082         /*
1083          * Workaround: Disable padding in Kumeran interface in the MAC
1084          * and in the PHY to avoid CRC errors.
1085          */
1086         ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
1087         if (ret_val)
1088                 return ret_val;
1089
1090         data |= GG82563_ICR_DIS_PADDING;
1091         ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1092         if (ret_val)
1093                 return ret_val;
1094
1095         return 0;
1096 }
1097
1098 /**
1099  *  e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1100  *  @hw: pointer to the HW structure
1101  *
1102  *  Essentially a wrapper for setting up all things "copper" related.
1103  *  This is a function pointer entry point called by the mac module.
1104  **/
1105 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1106 {
1107         u32 ctrl;
1108         s32 ret_val;
1109         u16 reg_data;
1110
1111         ctrl = er32(CTRL);
1112         ctrl |= E1000_CTRL_SLU;
1113         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1114         ew32(CTRL, ctrl);
1115
1116         /*
1117          * Set the mac to wait the maximum time between each
1118          * iteration and increase the max iterations when
1119          * polling the phy; this fixes erroneous timeouts at 10Mbps.
1120          */
1121         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1122                                                    0xFFFF);
1123         if (ret_val)
1124                 return ret_val;
1125         ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1126                                                   &reg_data);
1127         if (ret_val)
1128                 return ret_val;
1129         reg_data |= 0x3F;
1130         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1131                                                    reg_data);
1132         if (ret_val)
1133                 return ret_val;
1134         ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1135                                       E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1136                                       &reg_data);
1137         if (ret_val)
1138                 return ret_val;
1139         reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1140         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1141                                         E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1142                                         reg_data);
1143         if (ret_val)
1144                 return ret_val;
1145
1146         ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1147         if (ret_val)
1148                 return ret_val;
1149
1150         return e1000e_setup_copper_link(hw);
1151 }
1152
1153 /**
1154  *  e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1155  *  @hw: pointer to the HW structure
1156  *  @duplex: current duplex setting
1157  *
1158  *  Configure the KMRN interface by applying last minute quirks for
1159  *  10/100 operation.
1160  **/
1161 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1162 {
1163         s32 ret_val = 0;
1164         u16 speed;
1165         u16 duplex;
1166
1167         if (hw->phy.media_type == e1000_media_type_copper) {
1168                 ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed,
1169                                                              &duplex);
1170                 if (ret_val)
1171                         return ret_val;
1172
1173                 if (speed == SPEED_1000)
1174                         ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1175                 else
1176                         ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1177         }
1178
1179         return ret_val;
1180 }
1181
1182 /**
1183  *  e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1184  *  @hw: pointer to the HW structure
1185  *  @duplex: current duplex setting
1186  *
1187  *  Configure the KMRN interface by applying last minute quirks for
1188  *  10/100 operation.
1189  **/
1190 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1191 {
1192         s32 ret_val;
1193         u32 tipg;
1194         u32 i = 0;
1195         u16 reg_data, reg_data2;
1196
1197         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1198         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1199                                        E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1200                                        reg_data);
1201         if (ret_val)
1202                 return ret_val;
1203
1204         /* Configure Transmit Inter-Packet Gap */
1205         tipg = er32(TIPG);
1206         tipg &= ~E1000_TIPG_IPGT_MASK;
1207         tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1208         ew32(TIPG, tipg);
1209
1210         do {
1211                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1212                 if (ret_val)
1213                         return ret_val;
1214
1215                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1216                 if (ret_val)
1217                         return ret_val;
1218                 i++;
1219         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1220
1221         if (duplex == HALF_DUPLEX)
1222                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1223         else
1224                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1225
1226         return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1227 }
1228
1229 /**
1230  *  e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1231  *  @hw: pointer to the HW structure
1232  *
1233  *  Configure the KMRN interface by applying last minute quirks for
1234  *  gigabit operation.
1235  **/
1236 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1237 {
1238         s32 ret_val;
1239         u16 reg_data, reg_data2;
1240         u32 tipg;
1241         u32 i = 0;
1242
1243         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1244         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1245                                        E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1246                                        reg_data);
1247         if (ret_val)
1248                 return ret_val;
1249
1250         /* Configure Transmit Inter-Packet Gap */
1251         tipg = er32(TIPG);
1252         tipg &= ~E1000_TIPG_IPGT_MASK;
1253         tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1254         ew32(TIPG, tipg);
1255
1256         do {
1257                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1258                 if (ret_val)
1259                         return ret_val;
1260
1261                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1262                 if (ret_val)
1263                         return ret_val;
1264                 i++;
1265         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1266
1267         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1268         ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1269
1270         return ret_val;
1271 }
1272
1273 /**
1274  *  e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1275  *  @hw: pointer to the HW structure
1276  *  @offset: register offset to be read
1277  *  @data: pointer to the read data
1278  *
1279  *  Acquire semaphore, then read the PHY register at offset
1280  *  using the kumeran interface.  The information retrieved is stored in data.
1281  *  Release the semaphore before exiting.
1282  **/
1283 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1284                                            u16 *data)
1285 {
1286         u32 kmrnctrlsta;
1287         s32 ret_val = 0;
1288
1289         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1290         if (ret_val)
1291                 return ret_val;
1292
1293         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1294                        E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1295         ew32(KMRNCTRLSTA, kmrnctrlsta);
1296         e1e_flush();
1297
1298         udelay(2);
1299
1300         kmrnctrlsta = er32(KMRNCTRLSTA);
1301         *data = (u16)kmrnctrlsta;
1302
1303         e1000_release_mac_csr_80003es2lan(hw);
1304
1305         return ret_val;
1306 }
1307
1308 /**
1309  *  e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1310  *  @hw: pointer to the HW structure
1311  *  @offset: register offset to write to
1312  *  @data: data to write at register offset
1313  *
1314  *  Acquire semaphore, then write the data to PHY register
1315  *  at the offset using the kumeran interface.  Release semaphore
1316  *  before exiting.
1317  **/
1318 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1319                                             u16 data)
1320 {
1321         u32 kmrnctrlsta;
1322         s32 ret_val = 0;
1323
1324         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1325         if (ret_val)
1326                 return ret_val;
1327
1328         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1329                        E1000_KMRNCTRLSTA_OFFSET) | data;
1330         ew32(KMRNCTRLSTA, kmrnctrlsta);
1331         e1e_flush();
1332
1333         udelay(2);
1334
1335         e1000_release_mac_csr_80003es2lan(hw);
1336
1337         return ret_val;
1338 }
1339
1340 /**
1341  *  e1000_read_mac_addr_80003es2lan - Read device MAC address
1342  *  @hw: pointer to the HW structure
1343  **/
1344 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1345 {
1346         s32 ret_val = 0;
1347
1348         /*
1349          * If there's an alternate MAC address place it in RAR0
1350          * so that it will override the Si installed default perm
1351          * address.
1352          */
1353         ret_val = e1000_check_alt_mac_addr_generic(hw);
1354         if (ret_val)
1355                 goto out;
1356
1357         ret_val = e1000_read_mac_addr_generic(hw);
1358
1359 out:
1360         return ret_val;
1361 }
1362
1363 /**
1364  * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1365  * @hw: pointer to the HW structure
1366  *
1367  * In the case of a PHY power down to save power, or to turn off link during a
1368  * driver unload, or wake on lan is not enabled, remove the link.
1369  **/
1370 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1371 {
1372         /* If the management interface is not enabled, then power down */
1373         if (!(hw->mac.ops.check_mng_mode(hw) ||
1374               hw->phy.ops.check_reset_block(hw)))
1375                 e1000_power_down_phy_copper(hw);
1376 }
1377
1378 /**
1379  *  e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1380  *  @hw: pointer to the HW structure
1381  *
1382  *  Clears the hardware counters by reading the counter registers.
1383  **/
1384 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1385 {
1386         e1000e_clear_hw_cntrs_base(hw);
1387
1388         er32(PRC64);
1389         er32(PRC127);
1390         er32(PRC255);
1391         er32(PRC511);
1392         er32(PRC1023);
1393         er32(PRC1522);
1394         er32(PTC64);
1395         er32(PTC127);
1396         er32(PTC255);
1397         er32(PTC511);
1398         er32(PTC1023);
1399         er32(PTC1522);
1400
1401         er32(ALGNERRC);
1402         er32(RXERRC);
1403         er32(TNCRS);
1404         er32(CEXTERR);
1405         er32(TSCTC);
1406         er32(TSCTFC);
1407
1408         er32(MGTPRC);
1409         er32(MGTPDC);
1410         er32(MGTPTC);
1411
1412         er32(IAC);
1413         er32(ICRXOC);
1414
1415         er32(ICRXPTC);
1416         er32(ICRXATC);
1417         er32(ICTXPTC);
1418         er32(ICTXATC);
1419         er32(ICTXQEC);
1420         er32(ICTXQMTC);
1421         er32(ICRXDMTC);
1422 }
1423
1424 static const struct e1000_mac_operations es2_mac_ops = {
1425         .read_mac_addr          = e1000_read_mac_addr_80003es2lan,
1426         .id_led_init            = e1000e_id_led_init,
1427         .blink_led              = e1000e_blink_led_generic,
1428         .check_mng_mode         = e1000e_check_mng_mode_generic,
1429         /* check_for_link dependent on media type */
1430         .cleanup_led            = e1000e_cleanup_led_generic,
1431         .clear_hw_cntrs         = e1000_clear_hw_cntrs_80003es2lan,
1432         .get_bus_info           = e1000e_get_bus_info_pcie,
1433         .set_lan_id             = e1000_set_lan_id_multi_port_pcie,
1434         .get_link_up_info       = e1000_get_link_up_info_80003es2lan,
1435         .led_on                 = e1000e_led_on_generic,
1436         .led_off                = e1000e_led_off_generic,
1437         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
1438         .write_vfta             = e1000_write_vfta_generic,
1439         .clear_vfta             = e1000_clear_vfta_generic,
1440         .reset_hw               = e1000_reset_hw_80003es2lan,
1441         .init_hw                = e1000_init_hw_80003es2lan,
1442         .setup_link             = e1000e_setup_link,
1443         /* setup_physical_interface dependent on media type */
1444         .setup_led              = e1000e_setup_led_generic,
1445 };
1446
1447 static const struct e1000_phy_operations es2_phy_ops = {
1448         .acquire                = e1000_acquire_phy_80003es2lan,
1449         .check_polarity         = e1000_check_polarity_m88,
1450         .check_reset_block      = e1000e_check_reset_block_generic,
1451         .commit                 = e1000e_phy_sw_reset,
1452         .force_speed_duplex     = e1000_phy_force_speed_duplex_80003es2lan,
1453         .get_cfg_done           = e1000_get_cfg_done_80003es2lan,
1454         .get_cable_length       = e1000_get_cable_length_80003es2lan,
1455         .get_info               = e1000e_get_phy_info_m88,
1456         .read_reg               = e1000_read_phy_reg_gg82563_80003es2lan,
1457         .release                = e1000_release_phy_80003es2lan,
1458         .reset                  = e1000e_phy_hw_reset_generic,
1459         .set_d0_lplu_state      = NULL,
1460         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1461         .write_reg              = e1000_write_phy_reg_gg82563_80003es2lan,
1462         .cfg_on_link_up         = e1000_cfg_on_link_up_80003es2lan,
1463 };
1464
1465 static const struct e1000_nvm_operations es2_nvm_ops = {
1466         .acquire                = e1000_acquire_nvm_80003es2lan,
1467         .read                   = e1000e_read_nvm_eerd,
1468         .release                = e1000_release_nvm_80003es2lan,
1469         .update                 = e1000e_update_nvm_checksum_generic,
1470         .valid_led_default      = e1000e_valid_led_default,
1471         .validate               = e1000e_validate_nvm_checksum_generic,
1472         .write                  = e1000_write_nvm_80003es2lan,
1473 };
1474
1475 const struct e1000_info e1000_es2_info = {
1476         .mac                    = e1000_80003es2lan,
1477         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1478                                   | FLAG_HAS_JUMBO_FRAMES
1479                                   | FLAG_HAS_WOL
1480                                   | FLAG_APME_IN_CTRL3
1481                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1482                                   | FLAG_RX_NEEDS_RESTART /* errata */
1483                                   | FLAG_TARC_SET_BIT_ZERO /* errata */
1484                                   | FLAG_APME_CHECK_PORT_B
1485                                   | FLAG_DISABLE_FC_PAUSE_TIME, /* errata */
1486         .flags2                 = FLAG2_DMA_BURST,
1487         .pba                    = 38,
1488         .max_hw_frame_size      = DEFAULT_JUMBO,
1489         .get_variants           = e1000_get_variants_80003es2lan,
1490         .mac_ops                = &es2_mac_ops,
1491         .phy_ops                = &es2_phy_ops,
1492         .nvm_ops                = &es2_nvm_ops,
1493 };
1494