drivers/net/ethernet/intel/e1000e/80003es2lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2012 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 80003ES2LAN Gigabit Ethernet Controller (Copper)
  31  * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
  32  */
  33
  34 #include "e1000.h"
  35
  36 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL       0x00
  37 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL        0x02
  38 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL         0x10
  39 #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE  0x1F
  40
  41 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS    0x0008
  42 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS    0x0800
  43 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING   0x0010
  44
  45 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
  46 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT   0x0000
  47 #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE          0x2000
  48
  49 #define E1000_KMRNCTRLSTA_OPMODE_MASK            0x000C
  50 #define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO     0x0004
  51
  52 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
  53 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN        0x00010000
  54
  55 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN       0x8
  56 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN     0x9
  57
  58 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
  59 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE   0x0002 /* 1=Reversal Disab. */
  60 #define GG82563_PSCR_CROSSOVER_MODE_MASK         0x0060
  61 #define GG82563_PSCR_CROSSOVER_MODE_MDI          0x0000 /* 00=Manual MDI */
  62 #define GG82563_PSCR_CROSSOVER_MODE_MDIX         0x0020 /* 01=Manual MDIX */
  63 #define GG82563_PSCR_CROSSOVER_MODE_AUTO         0x0060 /* 11=Auto crossover */
  64
  65 /* PHY Specific Control Register 2 (Page 0, Register 26) */
  66 #define GG82563_PSCR2_REVERSE_AUTO_NEG           0x2000
  67                                                 /* 1=Reverse Auto-Negotiation */
  68
  69 /* MAC Specific Control Register (Page 2, Register 21) */
  70 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
  71 #define GG82563_MSCR_TX_CLK_MASK                 0x0007
  72 #define GG82563_MSCR_TX_CLK_10MBPS_2_5           0x0004
  73 #define GG82563_MSCR_TX_CLK_100MBPS_25           0x0005
  74 #define GG82563_MSCR_TX_CLK_1000MBPS_25          0x0007
  75
  76 #define GG82563_MSCR_ASSERT_CRS_ON_TX            0x0010 /* 1=Assert */
  77
  78 /* DSP Distance Register (Page 5, Register 26) */
  79 #define GG82563_DSPD_CABLE_LENGTH                0x0007 /* 0 = <50M
  80                                                            1 = 50-80M
  81                                                            2 = 80-110M
  82                                                            3 = 110-140M
  83                                                            4 = >140M */
  84
  85 /* Kumeran Mode Control Register (Page 193, Register 16) */
  86 #define GG82563_KMCR_PASS_FALSE_CARRIER          0x0800
  87
  88 /* Max number of times Kumeran read/write should be validated */
  89 #define GG82563_MAX_KMRN_RETRY  0x5
  90
  91 /* Power Management Control Register (Page 193, Register 20) */
  92 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE      0x0001
  93                                            /* 1=Enable SERDES Electrical Idle */
  94
  95 /* In-Band Control Register (Page 194, Register 18) */
  96 #define GG82563_ICR_DIS_PADDING                  0x0010 /* Disable Padding */
  97
  98 /*
  99  * A table for the GG82563 cable length where the range is defined
 100  * with a lower bound at "index" and the upper bound at
 101  * "index + 5".
 102  */
 103 static const u16 e1000_gg82563_cable_length_table[] = {
 104          0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
 105 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
 106                 ARRAY_SIZE(e1000_gg82563_cable_length_table)
 107
 108 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
 109 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
 110 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
 111 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
 112 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
 113 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
 114 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
 115 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
 116 static s32  e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
 117                                             u16 *data);
 118 static s32  e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
 119                                              u16 data);
 120 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
 121
 122 /**
 123  *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
 124  *  @hw: pointer to the HW structure
 125  **/
 126 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
 127 {
 128         struct e1000_phy_info *phy = &hw->phy;
 129         s32 ret_val;
 130
 131         if (hw->phy.media_type != e1000_media_type_copper) {
 132                 phy->type       = e1000_phy_none;
 133                 return 0;
 134         } else {
 135                 phy->ops.power_up = e1000_power_up_phy_copper;
 136                 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
 137         }
 138
 139         phy->addr               = 1;
 140         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 141         phy->reset_delay_us      = 100;
 142         phy->type               = e1000_phy_gg82563;
 143
 144         /* This can only be done after all function pointers are setup. */
 145         ret_val = e1000e_get_phy_id(hw);
 146
 147         /* Verify phy id */
 148         if (phy->id != GG82563_E_PHY_ID)
 149                 return -E1000_ERR_PHY;
 150
 151         return ret_val;
 152 }
 153
 154 /**
 155  *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
 156  *  @hw: pointer to the HW structure
 157  **/
 158 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
 159 {
 160         struct e1000_nvm_info *nvm = &hw->nvm;
 161         u32 eecd = er32(EECD);
 162         u16 size;
 163
 164         nvm->opcode_bits        = 8;
 165         nvm->delay_usec  = 1;
 166         switch (nvm->override) {
 167         case e1000_nvm_override_spi_large:
 168                 nvm->page_size    = 32;
 169                 nvm->address_bits = 16;
 170                 break;
 171         case e1000_nvm_override_spi_small:
 172                 nvm->page_size    = 8;
 173                 nvm->address_bits = 8;
 174                 break;
 175         default:
 176                 nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 177                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 178                 break;
 179         }
 180
 181         nvm->type = e1000_nvm_eeprom_spi;
 182
 183         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 184                           E1000_EECD_SIZE_EX_SHIFT);
 185
 186         /*
 187          * Added to a constant, "size" becomes the left-shift value
 188          * for setting word_size.
 189          */
 190         size += NVM_WORD_SIZE_BASE_SHIFT;
 191
 192         /* EEPROM access above 16k is unsupported */
 193         if (size > 14)
 194                 size = 14;
 195         nvm->word_size  = 1 << size;
 196
 197         return 0;
 198 }
 199
 200 /**
 201  *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
 202  *  @hw: pointer to the HW structure
 203  **/
 204 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
 205 {
 206         struct e1000_mac_info *mac = &hw->mac;
 207
 208         /* Set media type and media-dependent function pointers */
 209         switch (hw->adapter->pdev->device) {
 210         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
 211                 hw->phy.media_type = e1000_media_type_internal_serdes;
 212                 mac->ops.check_for_link = e1000e_check_for_serdes_link;
 213                 mac->ops.setup_physical_interface =
 214                     e1000e_setup_fiber_serdes_link;
 215                 break;
 216         default:
 217                 hw->phy.media_type = e1000_media_type_copper;
 218                 mac->ops.check_for_link = e1000e_check_for_copper_link;
 219                 mac->ops.setup_physical_interface =
 220                     e1000_setup_copper_link_80003es2lan;
 221                 break;
 222         }
 223
 224         /* Set mta register count */
 225         mac->mta_reg_count = 128;
 226         /* Set rar entry count */
 227         mac->rar_entry_count = E1000_RAR_ENTRIES;
 228         /* FWSM register */
 229         mac->has_fwsm = true;
 230         /* ARC supported; valid only if manageability features are enabled. */
 231         mac->arc_subsystem_valid =
 232                 (er32(FWSM) & E1000_FWSM_MODE_MASK)
 233                         ? true : false;
 234         /* Adaptive IFS not supported */
 235         mac->adaptive_ifs = false;
 236
 237         /* set lan id for port to determine which phy lock to use */
 238         hw->mac.ops.set_lan_id(hw);
 239
 240         return 0;
 241 }
 242
 243 static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
 244 {
 245         struct e1000_hw *hw = &adapter->hw;
 246         s32 rc;
 247
 248         rc = e1000_init_mac_params_80003es2lan(hw);
 249         if (rc)
 250                 return rc;
 251
 252         rc = e1000_init_nvm_params_80003es2lan(hw);
 253         if (rc)
 254                 return rc;
 255
 256         rc = e1000_init_phy_params_80003es2lan(hw);
 257         if (rc)
 258                 return rc;
 259
 260         return 0;
 261 }
 262
 263 /**
 264  *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
 265  *  @hw: pointer to the HW structure
 266  *
 267  *  A wrapper to acquire access rights to the correct PHY.
 268  **/
 269 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
 270 {
 271         u16 mask;
 272
 273         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 274         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 275 }
 276
 277 /**
 278  *  e1000_release_phy_80003es2lan - Release rights to access PHY
 279  *  @hw: pointer to the HW structure
 280  *
 281  *  A wrapper to release access rights to the correct PHY.
 282  **/
 283 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
 284 {
 285         u16 mask;
 286
 287         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 288         e1000_release_swfw_sync_80003es2lan(hw, mask);
 289 }
 290
 291 /**
 292  *  e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register
 293  *  @hw: pointer to the HW structure
 294  *
 295  *  Acquire the semaphore to access the Kumeran interface.
 296  *
 297  **/
 298 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
 299 {
 300         u16 mask;
 301
 302         mask = E1000_SWFW_CSR_SM;
 303
 304         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 305 }
 306
 307 /**
 308  *  e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register
 309  *  @hw: pointer to the HW structure
 310  *
 311  *  Release the semaphore used to access the Kumeran interface
 312  **/
 313 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
 314 {
 315         u16 mask;
 316
 317         mask = E1000_SWFW_CSR_SM;
 318
 319         e1000_release_swfw_sync_80003es2lan(hw, mask);
 320 }
 321
 322 /**
 323  *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
 324  *  @hw: pointer to the HW structure
 325  *
 326  *  Acquire the semaphore to access the EEPROM.
 327  **/
 328 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
 329 {
 330         s32 ret_val;
 331
 332         ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 333         if (ret_val)
 334                 return ret_val;
 335
 336         ret_val = e1000e_acquire_nvm(hw);
 337
 338         if (ret_val)
 339                 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 340
 341         return ret_val;
 342 }
 343
 344 /**
 345  *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
 346  *  @hw: pointer to the HW structure
 347  *
 348  *  Release the semaphore used to access the EEPROM.
 349  **/
 350 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
 351 {
 352         e1000e_release_nvm(hw);
 353         e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 354 }
 355
 356 /**
 357  *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
 358  *  @hw: pointer to the HW structure
 359  *  @mask: specifies which semaphore to acquire
 360  *
 361  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
 362  *  will also specify which port we're acquiring the lock for.
 363  **/
 364 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 365 {
 366         u32 swfw_sync;
 367         u32 swmask = mask;
 368         u32 fwmask = mask << 16;
 369         s32 i = 0;
 370         s32 timeout = 50;
 371
 372         while (i < timeout) {
 373                 if (e1000e_get_hw_semaphore(hw))
 374                         return -E1000_ERR_SWFW_SYNC;
 375
 376                 swfw_sync = er32(SW_FW_SYNC);
 377                 if (!(swfw_sync & (fwmask | swmask)))
 378                         break;
 379
 380                 /*
 381                  * Firmware currently using resource (fwmask)
 382                  * or other software thread using resource (swmask)
 383                  */
 384                 e1000e_put_hw_semaphore(hw);
 385                 mdelay(5);
 386                 i++;
 387         }
 388
 389         if (i == timeout) {
 390                 e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
 391                 return -E1000_ERR_SWFW_SYNC;
 392         }
 393
 394         swfw_sync |= swmask;
 395         ew32(SW_FW_SYNC, swfw_sync);
 396
 397         e1000e_put_hw_semaphore(hw);
 398
 399         return 0;
 400 }
 401
 402 /**
 403  *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
 404  *  @hw: pointer to the HW structure
 405  *  @mask: specifies which semaphore to acquire
 406  *
 407  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
 408  *  will also specify which port we're releasing the lock for.
 409  **/
 410 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 411 {
 412         u32 swfw_sync;
 413
 414         while (e1000e_get_hw_semaphore(hw) != 0)
 415                 ; /* Empty */
 416
 417         swfw_sync = er32(SW_FW_SYNC);
 418         swfw_sync &= ~mask;
 419         ew32(SW_FW_SYNC, swfw_sync);
 420
 421         e1000e_put_hw_semaphore(hw);
 422 }
 423
 424 /**
 425  *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
 426  *  @hw: pointer to the HW structure
 427  *  @offset: offset of the register to read
 428  *  @data: pointer to the data returned from the operation
 429  *
 430  *  Read the GG82563 PHY register.
 431  **/
 432 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 433                                                   u32 offset, u16 *data)
 434 {
 435         s32 ret_val;
 436         u32 page_select;
 437         u16 temp;
 438
 439         ret_val = e1000_acquire_phy_80003es2lan(hw);
 440         if (ret_val)
 441                 return ret_val;
 442
 443         /* Select Configuration Page */
 444         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 445                 page_select = GG82563_PHY_PAGE_SELECT;
 446         } else {
 447                 /*
 448                  * Use Alternative Page Select register to access
 449                  * registers 30 and 31
 450                  */
 451                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 452         }
 453
 454         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 455         ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
 456         if (ret_val) {
 457                 e1000_release_phy_80003es2lan(hw);
 458                 return ret_val;
 459         }
 460
 461         if (hw->dev_spec.e80003es2lan.mdic_wa_enable == true) {
 462                 /*
 463                  * The "ready" bit in the MDIC register may be incorrectly set
 464                  * before the device has completed the "Page Select" MDI
 465                  * transaction.  So we wait 200us after each MDI command...
 466                  */
 467                 udelay(200);
 468
 469                 /* ...and verify the command was successful. */
 470                 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
 471
 472                 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 473                         e1000_release_phy_80003es2lan(hw);
 474                         return -E1000_ERR_PHY;
 475                 }
 476
 477                 udelay(200);
 478
 479                 ret_val = e1000e_read_phy_reg_mdic(hw,
 480                                                   MAX_PHY_REG_ADDRESS & offset,
 481                                                   data);
 482
 483                 udelay(200);
 484         } else {
 485                 ret_val = e1000e_read_phy_reg_mdic(hw,
 486                                                   MAX_PHY_REG_ADDRESS & offset,
 487                                                   data);
 488         }
 489
 490         e1000_release_phy_80003es2lan(hw);
 491
 492         return ret_val;
 493 }
 494
 495 /**
 496  *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
 497  *  @hw: pointer to the HW structure
 498  *  @offset: offset of the register to read
 499  *  @data: value to write to the register
 500  *
 501  *  Write to the GG82563 PHY register.
 502  **/
 503 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 504                                                    u32 offset, u16 data)
 505 {
 506         s32 ret_val;
 507         u32 page_select;
 508         u16 temp;
 509
 510         ret_val = e1000_acquire_phy_80003es2lan(hw);
 511         if (ret_val)
 512                 return ret_val;
 513
 514         /* Select Configuration Page */
 515         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 516                 page_select = GG82563_PHY_PAGE_SELECT;
 517         } else {
 518                 /*
 519                  * Use Alternative Page Select register to access
 520                  * registers 30 and 31
 521                  */
 522                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 523         }
 524
 525         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 526         ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
 527         if (ret_val) {
 528                 e1000_release_phy_80003es2lan(hw);
 529                 return ret_val;
 530         }
 531
 532         if (hw->dev_spec.e80003es2lan.mdic_wa_enable == true) {
 533                 /*
 534                  * The "ready" bit in the MDIC register may be incorrectly set
 535                  * before the device has completed the "Page Select" MDI
 536                  * transaction.  So we wait 200us after each MDI command...
 537                  */
 538                 udelay(200);
 539
 540                 /* ...and verify the command was successful. */
 541                 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
 542
 543                 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 544                         e1000_release_phy_80003es2lan(hw);
 545                         return -E1000_ERR_PHY;
 546                 }
 547
 548                 udelay(200);
 549
 550                 ret_val = e1000e_write_phy_reg_mdic(hw,
 551                                                   MAX_PHY_REG_ADDRESS & offset,
 552                                                   data);
 553
 554                 udelay(200);
 555         } else {
 556                 ret_val = e1000e_write_phy_reg_mdic(hw,
 557                                                   MAX_PHY_REG_ADDRESS & offset,
 558                                                   data);
 559         }
 560
 561         e1000_release_phy_80003es2lan(hw);
 562
 563         return ret_val;
 564 }
 565
 566 /**
 567  *  e1000_write_nvm_80003es2lan - Write to ESB2 NVM
 568  *  @hw: pointer to the HW structure
 569  *  @offset: offset of the register to read
 570  *  @words: number of words to write
 571  *  @data: buffer of data to write to the NVM
 572  *
 573  *  Write "words" of data to the ESB2 NVM.
 574  **/
 575 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
 576                                        u16 words, u16 *data)
 577 {
 578         return e1000e_write_nvm_spi(hw, offset, words, data);
 579 }
 580
 581 /**
 582  *  e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
 583  *  @hw: pointer to the HW structure
 584  *
 585  *  Wait a specific amount of time for manageability processes to complete.
 586  *  This is a function pointer entry point called by the phy module.
 587  **/
 588 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
 589 {
 590         s32 timeout = PHY_CFG_TIMEOUT;
 591         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
 592
 593         if (hw->bus.func == 1)
 594                 mask = E1000_NVM_CFG_DONE_PORT_1;
 595
 596         while (timeout) {
 597                 if (er32(EEMNGCTL) & mask)
 598                         break;
 599                 usleep_range(1000, 2000);
 600                 timeout--;
 601         }
 602         if (!timeout) {
 603                 e_dbg("MNG configuration cycle has not completed.\n");
 604                 return -E1000_ERR_RESET;
 605         }
 606
 607         return 0;
 608 }
 609
 610 /**
 611  *  e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
 612  *  @hw: pointer to the HW structure
 613  *
 614  *  Force the speed and duplex settings onto the PHY.  This is a
 615  *  function pointer entry point called by the phy module.
 616  **/
 617 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
 618 {
 619         s32 ret_val;
 620         u16 phy_data;
 621         bool link;
 622
 623         /*
 624          * Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
 625          * forced whenever speed and duplex are forced.
 626          */
 627         ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
 628         if (ret_val)
 629                 return ret_val;
 630
 631         phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
 632         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
 633         if (ret_val)
 634                 return ret_val;
 635
 636         e_dbg("GG82563 PSCR: %X\n", phy_data);
 637
 638         ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
 639         if (ret_val)
 640                 return ret_val;
 641
 642         e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
 643
 644         /* Reset the phy to commit changes. */
 645         phy_data |= MII_CR_RESET;
 646
 647         ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
 648         if (ret_val)
 649                 return ret_val;
 650
 651         udelay(1);
 652
 653         if (hw->phy.autoneg_wait_to_complete) {
 654                 e_dbg("Waiting for forced speed/duplex link on GG82563 phy.\n");
 655
 656                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 657                                                      100000, &link);
 658                 if (ret_val)
 659                         return ret_val;
 660
 661                 if (!link) {
 662                         /*
 663                          * We didn't get link.
 664                          * Reset the DSP and cross our fingers.
 665                          */
 666                         ret_val = e1000e_phy_reset_dsp(hw);
 667                         if (ret_val)
 668                                 return ret_val;
 669                 }
 670
 671                 /* Try once more */
 672                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 673                                                      100000, &link);
 674                 if (ret_val)
 675                         return ret_val;
 676         }
 677
 678         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
 679         if (ret_val)
 680                 return ret_val;
 681
 682         /*
 683          * Resetting the phy means we need to verify the TX_CLK corresponds
 684          * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
 685          */
 686         phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
 687         if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
 688                 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
 689         else
 690                 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
 691
 692         /*
 693          * In addition, we must re-enable CRS on Tx for both half and full
 694          * duplex.
 695          */
 696         phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 697         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
 698
 699         return ret_val;
 700 }
 701
 702 /**
 703  *  e1000_get_cable_length_80003es2lan - Set approximate cable length
 704  *  @hw: pointer to the HW structure
 705  *
 706  *  Find the approximate cable length as measured by the GG82563 PHY.
 707  *  This is a function pointer entry point called by the phy module.
 708  **/
 709 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
 710 {
 711         struct e1000_phy_info *phy = &hw->phy;
 712         s32 ret_val = 0;
 713         u16 phy_data, index;
 714
 715         ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
 716         if (ret_val)
 717                 goto out;
 718
 719         index = phy_data & GG82563_DSPD_CABLE_LENGTH;
 720
 721         if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) {
 722                 ret_val = -E1000_ERR_PHY;
 723                 goto out;
 724         }
 725
 726         phy->min_cable_length = e1000_gg82563_cable_length_table[index];
 727         phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
 728
 729         phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
 730
 731 out:
 732         return ret_val;
 733 }
 734
 735 /**
 736  *  e1000_get_link_up_info_80003es2lan - Report speed and duplex
 737  *  @hw: pointer to the HW structure
 738  *  @speed: pointer to speed buffer
 739  *  @duplex: pointer to duplex buffer
 740  *
 741  *  Retrieve the current speed and duplex configuration.
 742  **/
 743 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
 744                                               u16 *duplex)
 745 {
 746         s32 ret_val;
 747
 748         if (hw->phy.media_type == e1000_media_type_copper) {
 749                 ret_val = e1000e_get_speed_and_duplex_copper(hw,
 750                                                                     speed,
 751                                                                     duplex);
 752                 hw->phy.ops.cfg_on_link_up(hw);
 753         } else {
 754                 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
 755                                                                   speed,
 756                                                                   duplex);
 757         }
 758
 759         return ret_val;
 760 }
 761
 762 /**
 763  *  e1000_reset_hw_80003es2lan - Reset the ESB2 controller
 764  *  @hw: pointer to the HW structure
 765  *
 766  *  Perform a global reset to the ESB2 controller.
 767  **/
 768 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
 769 {
 770         u32 ctrl;
 771         s32 ret_val;
 772
 773         /*
 774          * Prevent the PCI-E bus from sticking if there is no TLP connection
 775          * on the last TLP read/write transaction when MAC is reset.
 776          */
 777         ret_val = e1000e_disable_pcie_master(hw);
 778         if (ret_val)
 779                 e_dbg("PCI-E Master disable polling has failed.\n");
 780
 781         e_dbg("Masking off all interrupts\n");
 782         ew32(IMC, 0xffffffff);
 783
 784         ew32(RCTL, 0);
 785         ew32(TCTL, E1000_TCTL_PSP);
 786         e1e_flush();
 787
 788         usleep_range(10000, 20000);
 789
 790         ctrl = er32(CTRL);
 791
 792         ret_val = e1000_acquire_phy_80003es2lan(hw);
 793         e_dbg("Issuing a global reset to MAC\n");
 794         ew32(CTRL, ctrl | E1000_CTRL_RST);
 795         e1000_release_phy_80003es2lan(hw);
 796
 797         ret_val = e1000e_get_auto_rd_done(hw);
 798         if (ret_val)
 799                 /* We don't want to continue accessing MAC registers. */
 800                 return ret_val;
 801
 802         /* Clear any pending interrupt events. */
 803         ew32(IMC, 0xffffffff);
 804         er32(ICR);
 805
 806         return e1000_check_alt_mac_addr_generic(hw);
 807 }
 808
 809 /**
 810  *  e1000_init_hw_80003es2lan - Initialize the ESB2 controller
 811  *  @hw: pointer to the HW structure
 812  *
 813  *  Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
 814  **/
 815 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
 816 {
 817         struct e1000_mac_info *mac = &hw->mac;
 818         u32 reg_data;
 819         s32 ret_val;
 820         u16 kum_reg_data;
 821         u16 i;
 822
 823         e1000_initialize_hw_bits_80003es2lan(hw);
 824
 825         /* Initialize identification LED */
 826         ret_val = e1000e_id_led_init(hw);
 827         if (ret_val)
 828                 e_dbg("Error initializing identification LED\n");
 829                 /* This is not fatal and we should not stop init due to this */
 830
 831         /* Disabling VLAN filtering */
 832         e_dbg("Initializing the IEEE VLAN\n");
 833         mac->ops.clear_vfta(hw);
 834
 835         /* Setup the receive address. */
 836         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
 837
 838         /* Zero out the Multicast HASH table */
 839         e_dbg("Zeroing the MTA\n");
 840         for (i = 0; i < mac->mta_reg_count; i++)
 841                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 842
 843         /* Setup link and flow control */
 844         ret_val = e1000e_setup_link(hw);
 845
 846         /* Disable IBIST slave mode (far-end loopback) */
 847         e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 848                                         &kum_reg_data);
 849         kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
 850         e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 851                                          kum_reg_data);
 852
 853         /* Set the transmit descriptor write-back policy */
 854         reg_data = er32(TXDCTL(0));
 855         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 856                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
 857         ew32(TXDCTL(0), reg_data);
 858
 859         /* ...for both queues. */
 860         reg_data = er32(TXDCTL(1));
 861         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 862                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
 863         ew32(TXDCTL(1), reg_data);
 864
 865         /* Enable retransmit on late collisions */
 866         reg_data = er32(TCTL);
 867         reg_data |= E1000_TCTL_RTLC;
 868         ew32(TCTL, reg_data);
 869
 870         /* Configure Gigabit Carry Extend Padding */
 871         reg_data = er32(TCTL_EXT);
 872         reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
 873         reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
 874         ew32(TCTL_EXT, reg_data);
 875
 876         /* Configure Transmit Inter-Packet Gap */
 877         reg_data = er32(TIPG);
 878         reg_data &= ~E1000_TIPG_IPGT_MASK;
 879         reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
 880         ew32(TIPG, reg_data);
 881
 882         reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
 883         reg_data &= ~0x00100000;
 884         E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
 885
 886         /* default to true to enable the MDIC W/A */
 887         hw->dev_spec.e80003es2lan.mdic_wa_enable = true;
 888
 889         ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
 890                                       E1000_KMRNCTRLSTA_OFFSET >>
 891                                       E1000_KMRNCTRLSTA_OFFSET_SHIFT,
 892                                       &i);
 893         if (!ret_val) {
 894                 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
 895                      E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
 896                         hw->dev_spec.e80003es2lan.mdic_wa_enable = false;
 897         }
 898
 899         /*
 900          * Clear all of the statistics registers (clear on read).  It is
 901          * important that we do this after we have tried to establish link
 902          * because the symbol error count will increment wildly if there
 903          * is no link.
 904          */
 905         e1000_clear_hw_cntrs_80003es2lan(hw);
 906
 907         return ret_val;
 908 }
 909
 910 /**
 911  *  e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
 912  *  @hw: pointer to the HW structure
 913  *
 914  *  Initializes required hardware-dependent bits needed for normal operation.
 915  **/
 916 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
 917 {
 918         u32 reg;
 919
 920         /* Transmit Descriptor Control 0 */
 921         reg = er32(TXDCTL(0));
 922         reg |= (1 << 22);
 923         ew32(TXDCTL(0), reg);
 924
 925         /* Transmit Descriptor Control 1 */
 926         reg = er32(TXDCTL(1));
 927         reg |= (1 << 22);
 928         ew32(TXDCTL(1), reg);
 929
 930         /* Transmit Arbitration Control 0 */
 931         reg = er32(TARC(0));
 932         reg &= ~(0xF << 27); /* 30:27 */
 933         if (hw->phy.media_type != e1000_media_type_copper)
 934                 reg &= ~(1 << 20);
 935         ew32(TARC(0), reg);
 936
 937         /* Transmit Arbitration Control 1 */
 938         reg = er32(TARC(1));
 939         if (er32(TCTL) & E1000_TCTL_MULR)
 940                 reg &= ~(1 << 28);
 941         else
 942                 reg |= (1 << 28);
 943         ew32(TARC(1), reg);
 944 }
 945
 946 /**
 947  *  e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
 948  *  @hw: pointer to the HW structure
 949  *
 950  *  Setup some GG82563 PHY registers for obtaining link
 951  **/
 952 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
 953 {
 954         struct e1000_phy_info *phy = &hw->phy;
 955         s32 ret_val;
 956         u32 ctrl_ext;
 957         u16 data;
 958
 959         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
 960         if (ret_val)
 961                 return ret_val;
 962
 963         data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 964         /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
 965         data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
 966
 967         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
 968         if (ret_val)
 969                 return ret_val;
 970
 971         /*
 972          * Options:
 973          *   MDI/MDI-X = 0 (default)
 974          *   0 - Auto for all speeds
 975          *   1 - MDI mode
 976          *   2 - MDI-X mode
 977          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
 978          */
 979         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
 980         if (ret_val)
 981                 return ret_val;
 982
 983         data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
 984
 985         switch (phy->mdix) {
 986         case 1:
 987                 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
 988                 break;
 989         case 2:
 990                 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
 991                 break;
 992         case 0:
 993         default:
 994                 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
 995                 break;
 996         }
 997
 998         /*
 999          * Options:
1000          *   disable_polarity_correction = 0 (default)
1001          *       Automatic Correction for Reversed Cable Polarity
1002          *   0 - Disabled
1003          *   1 - Enabled
1004          */
1005         data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1006         if (phy->disable_polarity_correction)
1007                 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1008
1009         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
1010         if (ret_val)
1011                 return ret_val;
1012
1013         /* SW Reset the PHY so all changes take effect */
1014         ret_val = e1000e_commit_phy(hw);
1015         if (ret_val) {
1016                 e_dbg("Error Resetting the PHY\n");
1017                 return ret_val;
1018         }
1019
1020         /* Bypass Rx and Tx FIFO's */
1021         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1022                                         E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
1023                                         E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1024                                         E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1025         if (ret_val)
1026                 return ret_val;
1027
1028         ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1029                                        E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1030                                        &data);
1031         if (ret_val)
1032                 return ret_val;
1033         data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1034         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1035                                         E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1036                                         data);
1037         if (ret_val)
1038                 return ret_val;
1039
1040         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1041         if (ret_val)
1042                 return ret_val;
1043
1044         data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1045         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
1046         if (ret_val)
1047                 return ret_val;
1048
1049         ctrl_ext = er32(CTRL_EXT);
1050         ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1051         ew32(CTRL_EXT, ctrl_ext);
1052
1053         ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1054         if (ret_val)
1055                 return ret_val;
1056
1057         /*
1058          * Do not init these registers when the HW is in IAMT mode, since the
1059          * firmware will have already initialized them.  We only initialize
1060          * them if the HW is not in IAMT mode.
1061          */
1062         if (!e1000e_check_mng_mode(hw)) {
1063                 /* Enable Electrical Idle on the PHY */
1064                 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1065                 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
1066                 if (ret_val)
1067                         return ret_val;
1068
1069                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
1070                 if (ret_val)
1071                         return ret_val;
1072
1073                 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1074                 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
1075                 if (ret_val)
1076                         return ret_val;
1077         }
1078
1079         /*
1080          * Workaround: Disable padding in Kumeran interface in the MAC
1081          * and in the PHY to avoid CRC errors.
1082          */
1083         ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
1084         if (ret_val)
1085                 return ret_val;
1086
1087         data |= GG82563_ICR_DIS_PADDING;
1088         ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1089         if (ret_val)
1090                 return ret_val;
1091
1092         return 0;
1093 }
1094
1095 /**
1096  *  e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1097  *  @hw: pointer to the HW structure
1098  *
1099  *  Essentially a wrapper for setting up all things "copper" related.
1100  *  This is a function pointer entry point called by the mac module.
1101  **/
1102 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1103 {
1104         u32 ctrl;
1105         s32 ret_val;
1106         u16 reg_data;
1107
1108         ctrl = er32(CTRL);
1109         ctrl |= E1000_CTRL_SLU;
1110         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1111         ew32(CTRL, ctrl);
1112
1113         /*
1114          * Set the mac to wait the maximum time between each
1115          * iteration and increase the max iterations when
1116          * polling the phy; this fixes erroneous timeouts at 10Mbps.
1117          */
1118         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1119                                                    0xFFFF);
1120         if (ret_val)
1121                 return ret_val;
1122         ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1123                                                   &reg_data);
1124         if (ret_val)
1125                 return ret_val;
1126         reg_data |= 0x3F;
1127         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1128                                                    reg_data);
1129         if (ret_val)
1130                 return ret_val;
1131         ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1132                                       E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1133                                       &reg_data);
1134         if (ret_val)
1135                 return ret_val;
1136         reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1137         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1138                                         E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1139                                         reg_data);
1140         if (ret_val)
1141                 return ret_val;
1142
1143         ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1144         if (ret_val)
1145                 return ret_val;
1146
1147         return e1000e_setup_copper_link(hw);
1148 }
1149
1150 /**
1151  *  e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1152  *  @hw: pointer to the HW structure
1153  *  @duplex: current duplex setting
1154  *
1155  *  Configure the KMRN interface by applying last minute quirks for
1156  *  10/100 operation.
1157  **/
1158 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1159 {
1160         s32 ret_val = 0;
1161         u16 speed;
1162         u16 duplex;
1163
1164         if (hw->phy.media_type == e1000_media_type_copper) {
1165                 ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed,
1166                                                              &duplex);
1167                 if (ret_val)
1168                         return ret_val;
1169
1170                 if (speed == SPEED_1000)
1171                         ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1172                 else
1173                         ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1174         }
1175
1176         return ret_val;
1177 }
1178
1179 /**
1180  *  e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1181  *  @hw: pointer to the HW structure
1182  *  @duplex: current duplex setting
1183  *
1184  *  Configure the KMRN interface by applying last minute quirks for
1185  *  10/100 operation.
1186  **/
1187 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1188 {
1189         s32 ret_val;
1190         u32 tipg;
1191         u32 i = 0;
1192         u16 reg_data, reg_data2;
1193
1194         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1195         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1196                                        E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1197                                        reg_data);
1198         if (ret_val)
1199                 return ret_val;
1200
1201         /* Configure Transmit Inter-Packet Gap */
1202         tipg = er32(TIPG);
1203         tipg &= ~E1000_TIPG_IPGT_MASK;
1204         tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1205         ew32(TIPG, tipg);
1206
1207         do {
1208                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1209                 if (ret_val)
1210                         return ret_val;
1211
1212                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1213                 if (ret_val)
1214                         return ret_val;
1215                 i++;
1216         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1217
1218         if (duplex == HALF_DUPLEX)
1219                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1220         else
1221                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1222
1223         return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1224 }
1225
1226 /**
1227  *  e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1228  *  @hw: pointer to the HW structure
1229  *
1230  *  Configure the KMRN interface by applying last minute quirks for
1231  *  gigabit operation.
1232  **/
1233 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1234 {
1235         s32 ret_val;
1236         u16 reg_data, reg_data2;
1237         u32 tipg;
1238         u32 i = 0;
1239
1240         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1241         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1242                                        E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1243                                        reg_data);
1244         if (ret_val)
1245                 return ret_val;
1246
1247         /* Configure Transmit Inter-Packet Gap */
1248         tipg = er32(TIPG);
1249         tipg &= ~E1000_TIPG_IPGT_MASK;
1250         tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1251         ew32(TIPG, tipg);
1252
1253         do {
1254                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1255                 if (ret_val)
1256                         return ret_val;
1257
1258                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1259                 if (ret_val)
1260                         return ret_val;
1261                 i++;
1262         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1263
1264         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1265
1266         return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1267 }
1268
1269 /**
1270  *  e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1271  *  @hw: pointer to the HW structure
1272  *  @offset: register offset to be read
1273  *  @data: pointer to the read data
1274  *
1275  *  Acquire semaphore, then read the PHY register at offset
1276  *  using the kumeran interface.  The information retrieved is stored in data.
1277  *  Release the semaphore before exiting.
1278  **/
1279 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1280                                            u16 *data)
1281 {
1282         u32 kmrnctrlsta;
1283         s32 ret_val = 0;
1284
1285         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1286         if (ret_val)
1287                 return ret_val;
1288
1289         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1290                        E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1291         ew32(KMRNCTRLSTA, kmrnctrlsta);
1292         e1e_flush();
1293
1294         udelay(2);
1295
1296         kmrnctrlsta = er32(KMRNCTRLSTA);
1297         *data = (u16)kmrnctrlsta;
1298
1299         e1000_release_mac_csr_80003es2lan(hw);
1300
1301         return ret_val;
1302 }
1303
1304 /**
1305  *  e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1306  *  @hw: pointer to the HW structure
1307  *  @offset: register offset to write to
1308  *  @data: data to write at register offset
1309  *
1310  *  Acquire semaphore, then write the data to PHY register
1311  *  at the offset using the kumeran interface.  Release semaphore
1312  *  before exiting.
1313  **/
1314 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1315                                             u16 data)
1316 {
1317         u32 kmrnctrlsta;
1318         s32 ret_val = 0;
1319
1320         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1321         if (ret_val)
1322                 return ret_val;
1323
1324         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1325                        E1000_KMRNCTRLSTA_OFFSET) | data;
1326         ew32(KMRNCTRLSTA, kmrnctrlsta);
1327         e1e_flush();
1328
1329         udelay(2);
1330
1331         e1000_release_mac_csr_80003es2lan(hw);
1332
1333         return ret_val;
1334 }
1335
1336 /**
1337  *  e1000_read_mac_addr_80003es2lan - Read device MAC address
1338  *  @hw: pointer to the HW structure
1339  **/
1340 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1341 {
1342         s32 ret_val = 0;
1343
1344         /*
1345          * If there's an alternate MAC address place it in RAR0
1346          * so that it will override the Si installed default perm
1347          * address.
1348          */
1349         ret_val = e1000_check_alt_mac_addr_generic(hw);
1350         if (ret_val)
1351                 goto out;
1352
1353         ret_val = e1000_read_mac_addr_generic(hw);
1354
1355 out:
1356         return ret_val;
1357 }
1358
1359 /**
1360  * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1361  * @hw: pointer to the HW structure
1362  *
1363  * In the case of a PHY power down to save power, or to turn off link during a
1364  * driver unload, or wake on lan is not enabled, remove the link.
1365  **/
1366 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1367 {
1368         /* If the management interface is not enabled, then power down */
1369         if (!(hw->mac.ops.check_mng_mode(hw) ||
1370               hw->phy.ops.check_reset_block(hw)))
1371                 e1000_power_down_phy_copper(hw);
1372 }
1373
1374 /**
1375  *  e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1376  *  @hw: pointer to the HW structure
1377  *
1378  *  Clears the hardware counters by reading the counter registers.
1379  **/
1380 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1381 {
1382         e1000e_clear_hw_cntrs_base(hw);
1383
1384         er32(PRC64);
1385         er32(PRC127);
1386         er32(PRC255);
1387         er32(PRC511);
1388         er32(PRC1023);
1389         er32(PRC1522);
1390         er32(PTC64);
1391         er32(PTC127);
1392         er32(PTC255);
1393         er32(PTC511);
1394         er32(PTC1023);
1395         er32(PTC1522);
1396
1397         er32(ALGNERRC);
1398         er32(RXERRC);
1399         er32(TNCRS);
1400         er32(CEXTERR);
1401         er32(TSCTC);
1402         er32(TSCTFC);
1403
1404         er32(MGTPRC);
1405         er32(MGTPDC);
1406         er32(MGTPTC);
1407
1408         er32(IAC);
1409         er32(ICRXOC);
1410
1411         er32(ICRXPTC);
1412         er32(ICRXATC);
1413         er32(ICTXPTC);
1414         er32(ICTXATC);
1415         er32(ICTXQEC);
1416         er32(ICTXQMTC);
1417         er32(ICRXDMTC);
1418 }
1419
1420 static const struct e1000_mac_operations es2_mac_ops = {
1421         .read_mac_addr          = e1000_read_mac_addr_80003es2lan,
1422         .id_led_init            = e1000e_id_led_init,
1423         .blink_led              = e1000e_blink_led_generic,
1424         .check_mng_mode         = e1000e_check_mng_mode_generic,
1425         /* check_for_link dependent on media type */
1426         .cleanup_led            = e1000e_cleanup_led_generic,
1427         .clear_hw_cntrs         = e1000_clear_hw_cntrs_80003es2lan,
1428         .get_bus_info           = e1000e_get_bus_info_pcie,
1429         .set_lan_id             = e1000_set_lan_id_multi_port_pcie,
1430         .get_link_up_info       = e1000_get_link_up_info_80003es2lan,
1431         .led_on                 = e1000e_led_on_generic,
1432         .led_off                = e1000e_led_off_generic,
1433         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
1434         .write_vfta             = e1000_write_vfta_generic,
1435         .clear_vfta             = e1000_clear_vfta_generic,
1436         .reset_hw               = e1000_reset_hw_80003es2lan,
1437         .init_hw                = e1000_init_hw_80003es2lan,
1438         .setup_link             = e1000e_setup_link,
1439         /* setup_physical_interface dependent on media type */
1440         .setup_led              = e1000e_setup_led_generic,
1441 };
1442
1443 static const struct e1000_phy_operations es2_phy_ops = {
1444         .acquire                = e1000_acquire_phy_80003es2lan,
1445         .check_polarity         = e1000_check_polarity_m88,
1446         .check_reset_block      = e1000e_check_reset_block_generic,
1447         .commit                 = e1000e_phy_sw_reset,
1448         .force_speed_duplex     = e1000_phy_force_speed_duplex_80003es2lan,
1449         .get_cfg_done           = e1000_get_cfg_done_80003es2lan,
1450         .get_cable_length       = e1000_get_cable_length_80003es2lan,
1451         .get_info               = e1000e_get_phy_info_m88,
1452         .read_reg               = e1000_read_phy_reg_gg82563_80003es2lan,
1453         .release                = e1000_release_phy_80003es2lan,
1454         .reset                  = e1000e_phy_hw_reset_generic,
1455         .set_d0_lplu_state      = NULL,
1456         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1457         .write_reg              = e1000_write_phy_reg_gg82563_80003es2lan,
1458         .cfg_on_link_up         = e1000_cfg_on_link_up_80003es2lan,
1459 };
1460
1461 static const struct e1000_nvm_operations es2_nvm_ops = {
1462         .acquire                = e1000_acquire_nvm_80003es2lan,
1463         .read                   = e1000e_read_nvm_eerd,
1464         .release                = e1000_release_nvm_80003es2lan,
1465         .update                 = e1000e_update_nvm_checksum_generic,
1466         .valid_led_default      = e1000e_valid_led_default,
1467         .validate               = e1000e_validate_nvm_checksum_generic,
1468         .write                  = e1000_write_nvm_80003es2lan,
1469 };
1470
1471 const struct e1000_info e1000_es2_info = {
1472         .mac                    = e1000_80003es2lan,
1473         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1474                                   | FLAG_HAS_JUMBO_FRAMES
1475                                   | FLAG_HAS_WOL
1476                                   | FLAG_APME_IN_CTRL3
1477                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1478                                   | FLAG_RX_NEEDS_RESTART /* errata */
1479                                   | FLAG_TARC_SET_BIT_ZERO /* errata */
1480                                   | FLAG_APME_CHECK_PORT_B
1481                                   | FLAG_DISABLE_FC_PAUSE_TIME, /* errata */
1482         .flags2                 = FLAG2_DMA_BURST,
1483         .pba                    = 38,
1484         .max_hw_frame_size      = DEFAULT_JUMBO,
1485         .get_variants           = e1000_get_variants_80003es2lan,
1486         .mac_ops                = &es2_mac_ops,
1487         .phy_ops                = &es2_phy_ops,
1488         .nvm_ops                = &es2_nvm_ops,
1489 };
1490