drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Huawei HiNIC PCI Express Linux driver
   4  * Copyright(c) 2017 Huawei Technologies Co., Ltd
   5  */
   6
   7 #ifndef HINIC_HW_DEV_H
   8 #define HINIC_HW_DEV_H
   9
  10 #include <linux/pci.h>
  11 #include <linux/types.h>
  12 #include <linux/bitops.h>
  13
  14 #include "hinic_hw_if.h"
  15 #include "hinic_hw_eqs.h"
  16 #include "hinic_hw_mgmt.h"
  17 #include "hinic_hw_qp.h"
  18 #include "hinic_hw_io.h"
  19
  20 #define HINIC_MAX_QPS   32
  21
  22 #define HINIC_MGMT_NUM_MSG_CMD  (HINIC_MGMT_MSG_CMD_MAX - \
  23                                  HINIC_MGMT_MSG_CMD_BASE)
  24
  25 struct hinic_cap {
  26         u16     max_qps;
  27         u16     num_qps;
  28 };
  29
  30 enum hinic_port_cmd {
  31         HINIC_PORT_CMD_CHANGE_MTU       = 2,
  32
  33         HINIC_PORT_CMD_ADD_VLAN         = 3,
  34         HINIC_PORT_CMD_DEL_VLAN         = 4,
  35
  36         HINIC_PORT_CMD_SET_MAC          = 9,
  37         HINIC_PORT_CMD_GET_MAC          = 10,
  38         HINIC_PORT_CMD_DEL_MAC          = 11,
  39
  40         HINIC_PORT_CMD_SET_RX_MODE      = 12,
  41
  42         HINIC_PORT_CMD_GET_LINK_STATE   = 24,
  43
  44         HINIC_PORT_CMD_SET_LRO          = 25,
  45
  46         HINIC_PORT_CMD_SET_RX_CSUM      = 26,
  47
  48         HINIC_PORT_CMD_SET_RX_VLAN_OFFLOAD = 27,
  49
  50         HINIC_PORT_CMD_GET_PORT_STATISTICS = 28,
  51
  52         HINIC_PORT_CMD_CLEAR_PORT_STATISTICS = 29,
  53
  54         HINIC_PORT_CMD_GET_VPORT_STAT   = 30,
  55
  56         HINIC_PORT_CMD_CLEAN_VPORT_STAT = 31,
  57
  58         HINIC_PORT_CMD_GET_RSS_TEMPLATE_INDIR_TBL = 37,
  59
  60         HINIC_PORT_CMD_SET_PORT_STATE   = 41,
  61
  62         HINIC_PORT_CMD_SET_RSS_TEMPLATE_TBL = 43,
  63
  64         HINIC_PORT_CMD_GET_RSS_TEMPLATE_TBL = 44,
  65
  66         HINIC_PORT_CMD_SET_RSS_HASH_ENGINE = 45,
  67
  68         HINIC_PORT_CMD_GET_RSS_HASH_ENGINE = 46,
  69
  70         HINIC_PORT_CMD_GET_RSS_CTX_TBL  = 47,
  71
  72         HINIC_PORT_CMD_SET_RSS_CTX_TBL  = 48,
  73
  74         HINIC_PORT_CMD_RSS_TEMP_MGR     = 49,
  75
  76         HINIC_PORT_CMD_RSS_CFG          = 66,
  77
  78         HINIC_PORT_CMD_FWCTXT_INIT      = 69,
  79
  80         HINIC_PORT_CMD_GET_MGMT_VERSION = 88,
  81
  82         HINIC_PORT_CMD_SET_FUNC_STATE   = 93,
  83
  84         HINIC_PORT_CMD_GET_GLOBAL_QPN   = 102,
  85
  86         HINIC_PORT_CMD_SET_TSO          = 112,
  87
  88         HINIC_PORT_CMD_SET_RQ_IQ_MAP    = 115,
  89
  90         HINIC_PORT_CMD_GET_CAP          = 170,
  91
  92         HINIC_PORT_CMD_SET_LRO_TIMER    = 244,
  93 };
  94
  95 enum hinic_ucode_cmd {
  96         HINIC_UCODE_CMD_MODIFY_QUEUE_CONTEXT    = 0,
  97         HINIC_UCODE_CMD_CLEAN_QUEUE_CONTEXT,
  98         HINIC_UCODE_CMD_ARM_SQ,
  99         HINIC_UCODE_CMD_ARM_RQ,
 100         HINIC_UCODE_CMD_SET_RSS_INDIR_TABLE,
 101         HINIC_UCODE_CMD_SET_RSS_CONTEXT_TABLE,
 102         HINIC_UCODE_CMD_GET_RSS_INDIR_TABLE,
 103         HINIC_UCODE_CMD_GET_RSS_CONTEXT_TABLE,
 104         HINIC_UCODE_CMD_SET_IQ_ENABLE,
 105         HINIC_UCODE_CMD_SET_RQ_FLUSH            = 10
 106 };
 107
 108 #define NIC_RSS_CMD_TEMP_ALLOC  0x01
 109 #define NIC_RSS_CMD_TEMP_FREE   0x02
 110
 111 enum hinic_mgmt_msg_cmd {
 112         HINIC_MGMT_MSG_CMD_BASE         = 160,
 113
 114         HINIC_MGMT_MSG_CMD_LINK_STATUS  = 160,
 115
 116         HINIC_MGMT_MSG_CMD_MAX,
 117 };
 118
 119 enum hinic_cb_state {
 120         HINIC_CB_ENABLED = BIT(0),
 121         HINIC_CB_RUNNING = BIT(1),
 122 };
 123
 124 enum hinic_res_state {
 125         HINIC_RES_CLEAN         = 0,
 126         HINIC_RES_ACTIVE        = 1,
 127 };
 128
 129 struct hinic_cmd_fw_ctxt {
 130         u8      status;
 131         u8      version;
 132         u8      rsvd0[6];
 133
 134         u16     func_idx;
 135         u16     rx_buf_sz;
 136
 137         u32     rsvd1;
 138 };
 139
 140 struct hinic_cmd_hw_ioctxt {
 141         u8      status;
 142         u8      version;
 143         u8      rsvd0[6];
 144
 145         u16     func_idx;
 146
 147         u16     rsvd1;
 148
 149         u8      set_cmdq_depth;
 150         u8      cmdq_depth;
 151
 152         u8      lro_en;
 153         u8      rsvd3;
 154         u8      ppf_idx;
 155         u8      rsvd4;
 156
 157         u16     rq_depth;
 158         u16     rx_buf_sz_idx;
 159         u16     sq_depth;
 160 };
 161
 162 struct hinic_cmd_io_status {
 163         u8      status;
 164         u8      version;
 165         u8      rsvd0[6];
 166
 167         u16     func_idx;
 168         u8      rsvd1;
 169         u8      rsvd2;
 170         u32     io_status;
 171 };
 172
 173 struct hinic_cmd_clear_io_res {
 174         u8      status;
 175         u8      version;
 176         u8      rsvd0[6];
 177
 178         u16     func_idx;
 179         u8      rsvd1;
 180         u8      rsvd2;
 181 };
 182
 183 struct hinic_cmd_set_res_state {
 184         u8      status;
 185         u8      version;
 186         u8      rsvd0[6];
 187
 188         u16     func_idx;
 189         u8      state;
 190         u8      rsvd1;
 191         u32     rsvd2;
 192 };
 193
 194 struct hinic_cmd_base_qpn {
 195         u8      status;
 196         u8      version;
 197         u8      rsvd0[6];
 198
 199         u16     func_idx;
 200         u16     qpn;
 201 };
 202
 203 struct hinic_cmd_hw_ci {
 204         u8      status;
 205         u8      version;
 206         u8      rsvd0[6];
 207
 208         u16     func_idx;
 209
 210         u8      dma_attr_off;
 211         u8      pending_limit;
 212         u8      coalesc_timer;
 213
 214         u8      msix_en;
 215         u16     msix_entry_idx;
 216
 217         u32     sq_id;
 218         u32     rsvd1;
 219         u64     ci_addr;
 220 };
 221
 222 struct hinic_hwdev {
 223         struct hinic_hwif               *hwif;
 224         struct msix_entry               *msix_entries;
 225
 226         struct hinic_aeqs               aeqs;
 227         struct hinic_func_to_io         func_to_io;
 228
 229         struct hinic_cap                nic_cap;
 230 };
 231
 232 struct hinic_nic_cb {
 233         void    (*handler)(void *handle, void *buf_in,
 234                            u16 in_size, void *buf_out,
 235                            u16 *out_size);
 236
 237         void            *handle;
 238         unsigned long   cb_state;
 239 };
 240
 241 struct hinic_pfhwdev {
 242         struct hinic_hwdev              hwdev;
 243
 244         struct hinic_pf_to_mgmt         pf_to_mgmt;
 245
 246         struct hinic_nic_cb             nic_cb[HINIC_MGMT_NUM_MSG_CMD];
 247 };
 248
 249 void hinic_hwdev_cb_register(struct hinic_hwdev *hwdev,
 250                              enum hinic_mgmt_msg_cmd cmd, void *handle,
 251                              void (*handler)(void *handle, void *buf_in,
 252                                              u16 in_size, void *buf_out,
 253                                              u16 *out_size));
 254
 255 void hinic_hwdev_cb_unregister(struct hinic_hwdev *hwdev,
 256                                enum hinic_mgmt_msg_cmd cmd);
 257
 258 int hinic_port_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_port_cmd cmd,
 259                        void *buf_in, u16 in_size, void *buf_out,
 260                        u16 *out_size);
 261
 262 int hinic_hwdev_ifup(struct hinic_hwdev *hwdev);
 263
 264 void hinic_hwdev_ifdown(struct hinic_hwdev *hwdev);
 265
 266 struct hinic_hwdev *hinic_init_hwdev(struct pci_dev *pdev);
 267
 268 void hinic_free_hwdev(struct hinic_hwdev *hwdev);
 269
 270 int hinic_hwdev_max_num_qps(struct hinic_hwdev *hwdev);
 271
 272 int hinic_hwdev_num_qps(struct hinic_hwdev *hwdev);
 273
 274 struct hinic_sq *hinic_hwdev_get_sq(struct hinic_hwdev *hwdev, int i);
 275
 276 struct hinic_rq *hinic_hwdev_get_rq(struct hinic_hwdev *hwdev, int i);
 277
 278 int hinic_hwdev_msix_cnt_set(struct hinic_hwdev *hwdev, u16 msix_index);
 279
 280 int hinic_hwdev_msix_set(struct hinic_hwdev *hwdev, u16 msix_index,
 281                          u8 pending_limit, u8 coalesc_timer,
 282                          u8 lli_timer_cfg, u8 lli_credit_limit,
 283                          u8 resend_timer);
 284
 285 int hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev *hwdev, struct hinic_sq *sq,
 286                                u8 pending_limit, u8 coalesc_timer);
 287
 288 void hinic_hwdev_set_msix_state(struct hinic_hwdev *hwdev, u16 msix_index,
 289                                 enum hinic_msix_state flag);
 290
 291 #endif