drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4 #include <linux/device.h>
   5 #include <linux/dma-direction.h>
   6 #include <linux/dma-mapping.h>
   7 #include <linux/err.h>
   8 #include <linux/pci.h>
   9 #include <linux/slab.h>
  10 #include "hclgevf_cmd.h"
  11 #include "hclgevf_main.h"
  12 #include "hnae3.h"
  13
  14 #define hclgevf_is_csq(ring) ((ring)->flag & HCLGEVF_TYPE_CSQ)
  15 #define hclgevf_ring_to_dma_dir(ring) (hclgevf_is_csq(ring) ? \
  16                                         DMA_TO_DEVICE : DMA_FROM_DEVICE)
  17 #define cmq_ring_to_dev(ring)   (&(ring)->dev->pdev->dev)
  18
  19 static int hclgevf_ring_space(struct hclgevf_cmq_ring *ring)
  20 {
  21         int ntc = ring->next_to_clean;
  22         int ntu = ring->next_to_use;
  23         int used;
  24
  25         used = (ntu - ntc + ring->desc_num) % ring->desc_num;
  26
  27         return ring->desc_num - used - 1;
  28 }
  29
  30 static int hclgevf_is_valid_csq_clean_head(struct hclgevf_cmq_ring *ring,
  31                                            int head)
  32 {
  33         int ntu = ring->next_to_use;
  34         int ntc = ring->next_to_clean;
  35
  36         if (ntu > ntc)
  37                 return head >= ntc && head <= ntu;
  38
  39         return head >= ntc || head <= ntu;
  40 }
  41
  42 static int hclgevf_cmd_csq_clean(struct hclgevf_hw *hw)
  43 {
  44         struct hclgevf_dev *hdev = container_of(hw, struct hclgevf_dev, hw);
  45         struct hclgevf_cmq_ring *csq = &hw->cmq.csq;
  46         int clean = 0;
  47         u32 head;
  48
  49         head = hclgevf_read_dev(hw, HCLGEVF_NIC_CSQ_HEAD_REG);
  50         rmb(); /* Make sure head is ready before touch any data */
  51
  52         if (!hclgevf_is_valid_csq_clean_head(csq, head)) {
  53                 dev_warn(&hdev->pdev->dev, "wrong cmd head (%d, %d-%d)\n", head,
  54                          csq->next_to_use, csq->next_to_clean);
  55                 dev_warn(&hdev->pdev->dev,
  56                          "Disabling any further commands to IMP firmware\n");
  57                 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
  58                 return -EIO;
  59         }
  60
  61         clean = (head - csq->next_to_clean + csq->desc_num) % csq->desc_num;
  62         csq->next_to_clean = head;
  63         return clean;
  64 }
  65
  66 static bool hclgevf_cmd_csq_done(struct hclgevf_hw *hw)
  67 {
  68         u32 head;
  69
  70         head = hclgevf_read_dev(hw, HCLGEVF_NIC_CSQ_HEAD_REG);
  71
  72         return head == hw->cmq.csq.next_to_use;
  73 }
  74
  75 static bool hclgevf_is_special_opcode(u16 opcode)
  76 {
  77         u16 spec_opcode[] = {0x30, 0x31, 0x32};
  78         int i;
  79
  80         for (i = 0; i < ARRAY_SIZE(spec_opcode); i++) {
  81                 if (spec_opcode[i] == opcode)
  82                         return true;
  83         }
  84
  85         return false;
  86 }
  87
  88 static void hclgevf_cmd_config_regs(struct hclgevf_cmq_ring *ring)
  89 {
  90         struct hclgevf_dev *hdev = ring->dev;
  91         struct hclgevf_hw *hw = &hdev->hw;
  92         u32 reg_val;
  93
  94         if (ring->flag == HCLGEVF_TYPE_CSQ) {
  95                 reg_val = (u32)ring->desc_dma_addr;
  96                 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_BASEADDR_L_REG, reg_val);
  97                 reg_val = (u32)((ring->desc_dma_addr >> 31) >> 1);
  98                 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_BASEADDR_H_REG, reg_val);
  99
 100                 reg_val = (ring->desc_num >> HCLGEVF_NIC_CMQ_DESC_NUM_S);
 101                 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_DEPTH_REG, reg_val);
 102
 103                 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_HEAD_REG, 0);
 104                 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_TAIL_REG, 0);
 105         } else {
 106                 reg_val = (u32)ring->desc_dma_addr;
 107                 hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_BASEADDR_L_REG, reg_val);
 108                 reg_val = (u32)((ring->desc_dma_addr >> 31) >> 1);
 109                 hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_BASEADDR_H_REG, reg_val);
 110
 111                 reg_val = (ring->desc_num >> HCLGEVF_NIC_CMQ_DESC_NUM_S);
 112                 hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_DEPTH_REG, reg_val);
 113
 114                 hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_HEAD_REG, 0);
 115                 hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_TAIL_REG, 0);
 116         }
 117 }
 118
 119 static void hclgevf_cmd_init_regs(struct hclgevf_hw *hw)
 120 {
 121         hclgevf_cmd_config_regs(&hw->cmq.csq);
 122         hclgevf_cmd_config_regs(&hw->cmq.crq);
 123 }
 124
 125 static int hclgevf_alloc_cmd_desc(struct hclgevf_cmq_ring *ring)
 126 {
 127         int size = ring->desc_num * sizeof(struct hclgevf_desc);
 128
 129         ring->desc = dma_alloc_coherent(cmq_ring_to_dev(ring), size,
 130                                         &ring->desc_dma_addr, GFP_KERNEL);
 131         if (!ring->desc)
 132                 return -ENOMEM;
 133
 134         return 0;
 135 }
 136
 137 static void hclgevf_free_cmd_desc(struct hclgevf_cmq_ring *ring)
 138 {
 139         int size  = ring->desc_num * sizeof(struct hclgevf_desc);
 140
 141         if (ring->desc) {
 142                 dma_free_coherent(cmq_ring_to_dev(ring), size,
 143                                   ring->desc, ring->desc_dma_addr);
 144                 ring->desc = NULL;
 145         }
 146 }
 147
 148 static int hclgevf_alloc_cmd_queue(struct hclgevf_dev *hdev, int ring_type)
 149 {
 150         struct hclgevf_hw *hw = &hdev->hw;
 151         struct hclgevf_cmq_ring *ring =
 152                 (ring_type == HCLGEVF_TYPE_CSQ) ? &hw->cmq.csq : &hw->cmq.crq;
 153         int ret;
 154
 155         ring->dev = hdev;
 156         ring->flag = ring_type;
 157
 158         /* allocate CSQ/CRQ descriptor */
 159         ret = hclgevf_alloc_cmd_desc(ring);
 160         if (ret)
 161                 dev_err(&hdev->pdev->dev, "failed(%d) to alloc %s desc\n", ret,
 162                         (ring_type == HCLGEVF_TYPE_CSQ) ? "CSQ" : "CRQ");
 163
 164         return ret;
 165 }
 166
 167 void hclgevf_cmd_setup_basic_desc(struct hclgevf_desc *desc,
 168                                   enum hclgevf_opcode_type opcode, bool is_read)
 169 {
 170         memset(desc, 0, sizeof(struct hclgevf_desc));
 171         desc->opcode = cpu_to_le16(opcode);
 172         desc->flag = cpu_to_le16(HCLGEVF_CMD_FLAG_NO_INTR |
 173                                  HCLGEVF_CMD_FLAG_IN);
 174         if (is_read)
 175                 desc->flag |= cpu_to_le16(HCLGEVF_CMD_FLAG_WR);
 176         else
 177                 desc->flag &= cpu_to_le16(~HCLGEVF_CMD_FLAG_WR);
 178 }
 179
 180 static int hclgevf_cmd_convert_err_code(u16 desc_ret)
 181 {
 182         switch (desc_ret) {
 183         case HCLGEVF_CMD_EXEC_SUCCESS:
 184                 return 0;
 185         case HCLGEVF_CMD_NO_AUTH:
 186                 return -EPERM;
 187         case HCLGEVF_CMD_NOT_SUPPORTED:
 188                 return -EOPNOTSUPP;
 189         case HCLGEVF_CMD_QUEUE_FULL:
 190                 return -EXFULL;
 191         case HCLGEVF_CMD_NEXT_ERR:
 192                 return -ENOSR;
 193         case HCLGEVF_CMD_UNEXE_ERR:
 194                 return -ENOTBLK;
 195         case HCLGEVF_CMD_PARA_ERR:
 196                 return -EINVAL;
 197         case HCLGEVF_CMD_RESULT_ERR:
 198                 return -ERANGE;
 199         case HCLGEVF_CMD_TIMEOUT:
 200                 return -ETIME;
 201         case HCLGEVF_CMD_HILINK_ERR:
 202                 return -ENOLINK;
 203         case HCLGEVF_CMD_QUEUE_ILLEGAL:
 204                 return -ENXIO;
 205         case HCLGEVF_CMD_INVALID:
 206                 return -EBADR;
 207         default:
 208                 return -EIO;
 209         }
 210 }
 211
 212 /* hclgevf_cmd_send - send command to command queue
 213  * @hw: pointer to the hw struct
 214  * @desc: prefilled descriptor for describing the command
 215  * @num : the number of descriptors to be sent
 216  *
 217  * This is the main send command for command queue, it
 218  * sends the queue, cleans the queue, etc
 219  */
 220 int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclgevf_desc *desc, int num)
 221 {
 222         struct hclgevf_dev *hdev = (struct hclgevf_dev *)hw->hdev;
 223         struct hclgevf_cmq_ring *csq = &hw->cmq.csq;
 224         struct hclgevf_desc *desc_to_use;
 225         bool complete = false;
 226         u32 timeout = 0;
 227         int handle = 0;
 228         int status = 0;
 229         u16 retval;
 230         u16 opcode;
 231         int ntc;
 232
 233         spin_lock_bh(&hw->cmq.csq.lock);
 234
 235         if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) {
 236                 spin_unlock_bh(&hw->cmq.csq.lock);
 237                 return -EBUSY;
 238         }
 239
 240         if (num > hclgevf_ring_space(&hw->cmq.csq)) {
 241                 /* If CMDQ ring is full, SW HEAD and HW HEAD may be different,
 242                  * need update the SW HEAD pointer csq->next_to_clean
 243                  */
 244                 csq->next_to_clean = hclgevf_read_dev(hw,
 245                                                       HCLGEVF_NIC_CSQ_HEAD_REG);
 246                 spin_unlock_bh(&hw->cmq.csq.lock);
 247                 return -EBUSY;
 248         }
 249
 250         /* Record the location of desc in the ring for this time
 251          * which will be use for hardware to write back
 252          */
 253         ntc = hw->cmq.csq.next_to_use;
 254         opcode = le16_to_cpu(desc[0].opcode);
 255         while (handle < num) {
 256                 desc_to_use = &hw->cmq.csq.desc[hw->cmq.csq.next_to_use];
 257                 *desc_to_use = desc[handle];
 258                 (hw->cmq.csq.next_to_use)++;
 259                 if (hw->cmq.csq.next_to_use == hw->cmq.csq.desc_num)
 260                         hw->cmq.csq.next_to_use = 0;
 261                 handle++;
 262         }
 263
 264         /* Write to hardware */
 265         hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_TAIL_REG,
 266                           hw->cmq.csq.next_to_use);
 267
 268         /* If the command is sync, wait for the firmware to write back,
 269          * if multi descriptors to be sent, use the first one to check
 270          */
 271         if (HCLGEVF_SEND_SYNC(le16_to_cpu(desc->flag))) {
 272                 do {
 273                         if (hclgevf_cmd_csq_done(hw))
 274                                 break;
 275                         udelay(1);
 276                         timeout++;
 277                 } while (timeout < hw->cmq.tx_timeout);
 278         }
 279
 280         if (hclgevf_cmd_csq_done(hw)) {
 281                 complete = true;
 282                 handle = 0;
 283
 284                 while (handle < num) {
 285                         /* Get the result of hardware write back */
 286                         desc_to_use = &hw->cmq.csq.desc[ntc];
 287                         desc[handle] = *desc_to_use;
 288
 289                         if (likely(!hclgevf_is_special_opcode(opcode)))
 290                                 retval = le16_to_cpu(desc[handle].retval);
 291                         else
 292                                 retval = le16_to_cpu(desc[0].retval);
 293
 294                         status = hclgevf_cmd_convert_err_code(retval);
 295                         hw->cmq.last_status = (enum hclgevf_cmd_status)retval;
 296                         ntc++;
 297                         handle++;
 298                         if (ntc == hw->cmq.csq.desc_num)
 299                                 ntc = 0;
 300                 }
 301         }
 302
 303         if (!complete)
 304                 status = -EBADE;
 305
 306         /* Clean the command send queue */
 307         handle = hclgevf_cmd_csq_clean(hw);
 308         if (handle != num)
 309                 dev_warn(&hdev->pdev->dev,
 310                          "cleaned %d, need to clean %d\n", handle, num);
 311
 312         spin_unlock_bh(&hw->cmq.csq.lock);
 313
 314         return status;
 315 }
 316
 317 static int  hclgevf_cmd_query_firmware_version(struct hclgevf_hw *hw,
 318                                                u32 *version)
 319 {
 320         struct hclgevf_query_version_cmd *resp;
 321         struct hclgevf_desc desc;
 322         int status;
 323
 324         resp = (struct hclgevf_query_version_cmd *)desc.data;
 325
 326         hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_FW_VER, 1);
 327         status = hclgevf_cmd_send(hw, &desc, 1);
 328         if (!status)
 329                 *version = le32_to_cpu(resp->firmware);
 330
 331         return status;
 332 }
 333
 334 int hclgevf_cmd_queue_init(struct hclgevf_dev *hdev)
 335 {
 336         int ret;
 337
 338         /* Setup the lock for command queue */
 339         spin_lock_init(&hdev->hw.cmq.csq.lock);
 340         spin_lock_init(&hdev->hw.cmq.crq.lock);
 341
 342         hdev->hw.cmq.tx_timeout = HCLGEVF_CMDQ_TX_TIMEOUT;
 343         hdev->hw.cmq.csq.desc_num = HCLGEVF_NIC_CMQ_DESC_NUM;
 344         hdev->hw.cmq.crq.desc_num = HCLGEVF_NIC_CMQ_DESC_NUM;
 345
 346         ret = hclgevf_alloc_cmd_queue(hdev, HCLGEVF_TYPE_CSQ);
 347         if (ret) {
 348                 dev_err(&hdev->pdev->dev,
 349                         "CSQ ring setup error %d\n", ret);
 350                 return ret;
 351         }
 352
 353         ret = hclgevf_alloc_cmd_queue(hdev, HCLGEVF_TYPE_CRQ);
 354         if (ret) {
 355                 dev_err(&hdev->pdev->dev,
 356                         "CRQ ring setup error %d\n", ret);
 357                 goto err_csq;
 358         }
 359
 360         return 0;
 361 err_csq:
 362         hclgevf_free_cmd_desc(&hdev->hw.cmq.csq);
 363         return ret;
 364 }
 365
 366 int hclgevf_cmd_init(struct hclgevf_dev *hdev)
 367 {
 368         u32 version;
 369         int ret;
 370
 371         spin_lock_bh(&hdev->hw.cmq.csq.lock);
 372         spin_lock(&hdev->hw.cmq.crq.lock);
 373
 374         /* initialize the pointers of async rx queue of mailbox */
 375         hdev->arq.hdev = hdev;
 376         hdev->arq.head = 0;
 377         hdev->arq.tail = 0;
 378         atomic_set(&hdev->arq.count, 0);
 379         hdev->hw.cmq.csq.next_to_clean = 0;
 380         hdev->hw.cmq.csq.next_to_use = 0;
 381         hdev->hw.cmq.crq.next_to_clean = 0;
 382         hdev->hw.cmq.crq.next_to_use = 0;
 383
 384         hclgevf_cmd_init_regs(&hdev->hw);
 385
 386         spin_unlock(&hdev->hw.cmq.crq.lock);
 387         spin_unlock_bh(&hdev->hw.cmq.csq.lock);
 388
 389         clear_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
 390
 391         /* Check if there is new reset pending, because the higher level
 392          * reset may happen when lower level reset is being processed.
 393          */
 394         if (hclgevf_is_reset_pending(hdev)) {
 395                 ret = -EBUSY;
 396                 goto err_cmd_init;
 397         }
 398
 399         /* get firmware version */
 400         ret = hclgevf_cmd_query_firmware_version(&hdev->hw, &version);
 401         if (ret) {
 402                 dev_err(&hdev->pdev->dev,
 403                         "failed(%d) to query firmware version\n", ret);
 404                 goto err_cmd_init;
 405         }
 406         hdev->fw_version = version;
 407
 408         dev_info(&hdev->pdev->dev, "The firmware version is %08x\n", version);
 409
 410         return 0;
 411
 412 err_cmd_init:
 413         set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
 414
 415         return ret;
 416 }
 417
 418 static void hclgevf_cmd_uninit_regs(struct hclgevf_hw *hw)
 419 {
 420         hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_BASEADDR_L_REG, 0);
 421         hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_BASEADDR_H_REG, 0);
 422         hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 0);
 423         hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_HEAD_REG, 0);
 424         hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_TAIL_REG, 0);
 425         hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_BASEADDR_L_REG, 0);
 426         hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_BASEADDR_H_REG, 0);
 427         hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_DEPTH_REG, 0);
 428         hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_HEAD_REG, 0);
 429         hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_TAIL_REG, 0);
 430 }
 431
 432 void hclgevf_cmd_uninit(struct hclgevf_dev *hdev)
 433 {
 434         spin_lock_bh(&hdev->hw.cmq.csq.lock);
 435         spin_lock(&hdev->hw.cmq.crq.lock);
 436         clear_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
 437         hclgevf_cmd_uninit_regs(&hdev->hw);
 438         spin_unlock(&hdev->hw.cmq.crq.lock);
 439         spin_unlock_bh(&hdev->hw.cmq.csq.lock);
 440         hclgevf_free_cmd_desc(&hdev->hw.cmq.csq);
 441         hclgevf_free_cmd_desc(&hdev->hw.cmq.crq);
 442 }