drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 // Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4 #ifndef __HCLGE_TM_H
   5 #define __HCLGE_TM_H
   6
   7 #include <linux/types.h>
   8
   9 #include "hnae3.h"
  10
  11 struct hclge_dev;
  12 struct hclge_vport;
  13 enum hclge_opcode_type;
  14
  15 /* MAC Pause */
  16 #define HCLGE_TX_MAC_PAUSE_EN_MSK       BIT(0)
  17 #define HCLGE_RX_MAC_PAUSE_EN_MSK       BIT(1)
  18
  19 #define HCLGE_TM_PORT_BASE_MODE_MSK     BIT(0)
  20
  21 #define HCLGE_DEFAULT_PAUSE_TRANS_GAP   0x7F
  22 #define HCLGE_DEFAULT_PAUSE_TRANS_TIME  0xFFFF
  23
  24 /* SP or DWRR */
  25 #define HCLGE_TM_TX_SCHD_DWRR_MSK       BIT(0)
  26 #define HCLGE_TM_TX_SCHD_SP_MSK         0xFE
  27
  28 #define HCLGE_ETHER_MAX_RATE    100000
  29
  30 #define HCLGE_TM_PF_MAX_PRI_NUM         8
  31 #define HCLGE_TM_PF_MAX_QSET_NUM        8
  32
  33 struct hclge_pg_to_pri_link_cmd {
  34         u8 pg_id;
  35         u8 rsvd1[3];
  36         u8 pri_bit_map;
  37 };
  38
  39 struct hclge_qs_to_pri_link_cmd {
  40         __le16 qs_id;
  41         __le16 rsvd;
  42         u8 priority;
  43 #define HCLGE_TM_QS_PRI_LINK_VLD_MSK    BIT(0)
  44         u8 link_vld;
  45 };
  46
  47 struct hclge_nq_to_qs_link_cmd {
  48         __le16 nq_id;
  49         __le16 rsvd;
  50 #define HCLGE_TM_Q_QS_LINK_VLD_MSK      BIT(10)
  51 #define HCLGE_TM_QS_ID_L_MSK            GENMASK(9, 0)
  52 #define HCLGE_TM_QS_ID_L_S              0
  53 #define HCLGE_TM_QS_ID_H_MSK            GENMASK(14, 10)
  54 #define HCLGE_TM_QS_ID_H_S              10
  55 #define HCLGE_TM_QS_ID_H_EXT_S          11
  56 #define HCLGE_TM_QS_ID_H_EXT_MSK        GENMASK(15, 11)
  57         __le16 qset_id;
  58 };
  59
  60 struct hclge_tqp_tx_queue_tc_cmd {
  61         __le16 queue_id;
  62         __le16 rsvd;
  63         u8 tc_id;
  64         u8 rev[3];
  65 };
  66
  67 struct hclge_pg_weight_cmd {
  68         u8 pg_id;
  69         u8 dwrr;
  70 };
  71
  72 struct hclge_priority_weight_cmd {
  73         u8 pri_id;
  74         u8 dwrr;
  75 };
  76
  77 struct hclge_pri_sch_mode_cfg_cmd {
  78         u8 pri_id;
  79         u8 rsvd[3];
  80         u8 sch_mode;
  81 };
  82
  83 struct hclge_qs_sch_mode_cfg_cmd {
  84         __le16 qs_id;
  85         u8 rsvd[2];
  86         u8 sch_mode;
  87 };
  88
  89 struct hclge_qs_weight_cmd {
  90         __le16 qs_id;
  91         u8 dwrr;
  92 };
  93
  94 struct hclge_ets_tc_weight_cmd {
  95         u8 tc_weight[HNAE3_MAX_TC];
  96         u8 weight_offset;
  97         u8 rsvd[15];
  98 };
  99
 100 #define HCLGE_TM_SHAP_IR_B_MSK  GENMASK(7, 0)
 101 #define HCLGE_TM_SHAP_IR_B_LSH  0
 102 #define HCLGE_TM_SHAP_IR_U_MSK  GENMASK(11, 8)
 103 #define HCLGE_TM_SHAP_IR_U_LSH  8
 104 #define HCLGE_TM_SHAP_IR_S_MSK  GENMASK(15, 12)
 105 #define HCLGE_TM_SHAP_IR_S_LSH  12
 106 #define HCLGE_TM_SHAP_BS_B_MSK  GENMASK(20, 16)
 107 #define HCLGE_TM_SHAP_BS_B_LSH  16
 108 #define HCLGE_TM_SHAP_BS_S_MSK  GENMASK(25, 21)
 109 #define HCLGE_TM_SHAP_BS_S_LSH  21
 110
 111 enum hclge_shap_bucket {
 112         HCLGE_TM_SHAP_C_BUCKET = 0,
 113         HCLGE_TM_SHAP_P_BUCKET,
 114 };
 115
 116 /* set bit HCLGE_TM_RATE_VLD to 1 means use 'rate' to config shaping */
 117 #define HCLGE_TM_RATE_VLD       0
 118
 119 struct hclge_pri_shapping_cmd {
 120         u8 pri_id;
 121         u8 rsvd[3];
 122         __le32 pri_shapping_para;
 123         u8 flag;
 124         u8 rsvd1[3];
 125         __le32 pri_rate;
 126 };
 127
 128 struct hclge_pg_shapping_cmd {
 129         u8 pg_id;
 130         u8 rsvd[3];
 131         __le32 pg_shapping_para;
 132         u8 flag;
 133         u8 rsvd1[3];
 134         __le32 pg_rate;
 135 };
 136
 137 struct hclge_qs_shapping_cmd {
 138         __le16 qs_id;
 139         u8 rsvd[2];
 140         __le32 qs_shapping_para;
 141         u8 flag;
 142         u8 rsvd1[3];
 143         __le32 qs_rate;
 144 };
 145
 146 #define HCLGE_BP_GRP_NUM                32
 147 #define HCLGE_BP_SUB_GRP_ID_S           0
 148 #define HCLGE_BP_SUB_GRP_ID_M           GENMASK(4, 0)
 149 #define HCLGE_BP_GRP_ID_S               5
 150 #define HCLGE_BP_GRP_ID_M               GENMASK(9, 5)
 151
 152 #define HCLGE_BP_EXT_GRP_NUM            40
 153 #define HCLGE_BP_EXT_GRP_ID_S           5
 154 #define HCLGE_BP_EXT_GRP_ID_M           GENMASK(10, 5)
 155
 156 struct hclge_bp_to_qs_map_cmd {
 157         u8 tc_id;
 158         u8 rsvd[2];
 159         u8 qs_group_id;
 160         __le32 qs_bit_map;
 161         u32 rsvd1;
 162 };
 163
 164 struct hclge_pfc_en_cmd {
 165         u8 tx_rx_en_bitmap;
 166         u8 pri_en_bitmap;
 167 };
 168
 169 struct hclge_cfg_pause_param_cmd {
 170         u8 mac_addr[ETH_ALEN];
 171         u8 pause_trans_gap;
 172         u8 rsvd;
 173         __le16 pause_trans_time;
 174         u8 rsvd1[6];
 175         /* extra mac address to do double check for pause frame */
 176         u8 mac_addr_extra[ETH_ALEN];
 177         u16 rsvd2;
 178 };
 179
 180 struct hclge_pfc_stats_cmd {
 181         __le64 pkt_num[3];
 182 };
 183
 184 struct hclge_port_shapping_cmd {
 185         __le32 port_shapping_para;
 186         u8 flag;
 187         u8 rsvd[3];
 188         __le32 port_rate;
 189 };
 190
 191 struct hclge_shaper_ir_para {
 192         u8 ir_b; /* IR_B parameter of IR shaper */
 193         u8 ir_u; /* IR_U parameter of IR shaper */
 194         u8 ir_s; /* IR_S parameter of IR shaper */
 195 };
 196
 197 struct hclge_tm_nodes_cmd {
 198         u8 pg_base_id;
 199         u8 pri_base_id;
 200         __le16 qset_base_id;
 201         __le16 queue_base_id;
 202         u8 pg_num;
 203         u8 pri_num;
 204         __le16 qset_num;
 205         __le16 queue_num;
 206 };
 207
 208 struct hclge_tm_shaper_para {
 209         u32 rate;
 210         u8 ir_b;
 211         u8 ir_u;
 212         u8 ir_s;
 213         u8 bs_b;
 214         u8 bs_s;
 215         u8 flag;
 216 };
 217
 218 #define hclge_tm_set_field(dest, string, val) \
 219                            hnae3_set_field((dest), \
 220                            (HCLGE_TM_SHAP_##string##_MSK), \
 221                            (HCLGE_TM_SHAP_##string##_LSH), val)
 222 #define hclge_tm_get_field(src, string) \
 223                         hnae3_get_field((src), HCLGE_TM_SHAP_##string##_MSK, \
 224                                         HCLGE_TM_SHAP_##string##_LSH)
 225
 226 int hclge_tm_schd_init(struct hclge_dev *hdev);
 227 int hclge_tm_vport_map_update(struct hclge_dev *hdev);
 228 int hclge_pause_setup_hw(struct hclge_dev *hdev, bool init);
 229 int hclge_tm_schd_setup_hw(struct hclge_dev *hdev);
 230 void hclge_tm_prio_tc_info_update(struct hclge_dev *hdev, u8 *prio_tc);
 231 void hclge_tm_schd_info_update(struct hclge_dev *hdev, u8 num_tc);
 232 void hclge_tm_pfc_info_update(struct hclge_dev *hdev);
 233 int hclge_tm_dwrr_cfg(struct hclge_dev *hdev);
 234 int hclge_tm_init_hw(struct hclge_dev *hdev, bool init);
 235 int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx);
 236 int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr);
 237 void hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats);
 238 void hclge_pfc_tx_stats_get(struct hclge_dev *hdev, u64 *stats);
 239 int hclge_tm_qs_shaper_cfg(struct hclge_vport *vport, int max_tx_rate);
 240 int hclge_tm_get_qset_num(struct hclge_dev *hdev, u16 *qset_num);
 241 int hclge_tm_get_pri_num(struct hclge_dev *hdev, u8 *pri_num);
 242 int hclge_tm_get_qset_map_pri(struct hclge_dev *hdev, u16 qset_id, u8 *priority,
 243                               u8 *link_vld);
 244 int hclge_tm_get_qset_sch_mode(struct hclge_dev *hdev, u16 qset_id, u8 *mode);
 245 int hclge_tm_get_qset_weight(struct hclge_dev *hdev, u16 qset_id, u8 *weight);
 246 int hclge_tm_get_qset_shaper(struct hclge_dev *hdev, u16 qset_id,
 247                              struct hclge_tm_shaper_para *para);
 248 int hclge_tm_get_pri_sch_mode(struct hclge_dev *hdev, u8 pri_id, u8 *mode);
 249 int hclge_tm_get_pri_weight(struct hclge_dev *hdev, u8 pri_id, u8 *weight);
 250 int hclge_tm_get_pri_shaper(struct hclge_dev *hdev, u8 pri_id,
 251                             enum hclge_opcode_type cmd,
 252                             struct hclge_tm_shaper_para *para);
 253 int hclge_tm_get_q_to_qs_map(struct hclge_dev *hdev, u16 q_id, u16 *qset_id);
 254 int hclge_tm_get_q_to_tc(struct hclge_dev *hdev, u16 q_id, u8 *tc_id);
 255 int hclge_tm_get_pg_to_pri_map(struct hclge_dev *hdev, u8 pg_id,
 256                                u8 *pri_bit_map);
 257 int hclge_tm_get_pg_weight(struct hclge_dev *hdev, u8 pg_id, u8 *weight);
 258 int hclge_tm_get_pg_sch_mode(struct hclge_dev *hdev, u8 pg_id, u8 *mode);
 259 int hclge_tm_get_pg_shaper(struct hclge_dev *hdev, u8 pg_id,
 260                            enum hclge_opcode_type cmd,
 261                            struct hclge_tm_shaper_para *para);
 262 int hclge_tm_get_port_shaper(struct hclge_dev *hdev,
 263                              struct hclge_tm_shaper_para *para);
 264 #endif