1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
4 #include <linux/etherdevice.h>
7 #include "hclge_main.h"
10 enum hclge_shaper_level {
11 HCLGE_SHAPER_LVL_PRI = 0,
12 HCLGE_SHAPER_LVL_PG = 1,
13 HCLGE_SHAPER_LVL_PORT = 2,
14 HCLGE_SHAPER_LVL_QSET = 3,
15 HCLGE_SHAPER_LVL_CNT = 4,
16 HCLGE_SHAPER_LVL_VF = 0,
17 HCLGE_SHAPER_LVL_PF = 1,
20 #define HCLGE_TM_PFC_PKT_GET_CMD_NUM 3
21 #define HCLGE_TM_PFC_NUM_GET_PER_CMD 3
23 #define HCLGE_SHAPER_BS_U_DEF 5
24 #define HCLGE_SHAPER_BS_S_DEF 20
26 #define HCLGE_ETHER_MAX_RATE 100000
28 /* hclge_shaper_para_calc: calculate ir parameter for the shaper
29 * @ir: Rate to be config, its unit is Mbps
30 * @shaper_level: the shaper level. eg: port, pg, priority, queueset
31 * @ir_b: IR_B parameter of IR shaper
32 * @ir_u: IR_U parameter of IR shaper
33 * @ir_s: IR_S parameter of IR shaper
37 * IR_b * (2 ^ IR_u) * 8
38 * IR(Mbps) = ------------------------- * CLOCK(1000Mbps)
41 * @return: 0: calculate sucessful, negative: fail
43 static int hclge_shaper_para_calc(u32 ir, u8 shaper_level,
44 u8 *ir_b, u8 *ir_u, u8 *ir_s)
46 #define DIVISOR_CLK (1000 * 8)
47 #define DIVISOR_IR_B_126 (126 * DIVISOR_CLK)
49 const u16 tick_array[HCLGE_SHAPER_LVL_CNT] = {
50 6 * 256, /* Prioriy level */
51 6 * 32, /* Prioriy group level */
52 6 * 8, /* Port level */
53 6 * 256 /* Qset level */
61 if (shaper_level >= HCLGE_SHAPER_LVL_CNT ||
62 ir > HCLGE_ETHER_MAX_RATE)
65 tick = tick_array[shaper_level];
68 * Calc the speed if ir_b = 126, ir_u = 0 and ir_s = 0
69 * the formula is changed to:
71 * ir_calc = ---------------- * 1000
74 ir_calc = (DIVISOR_IR_B_126 + (tick >> 1) - 1) / tick;
82 } else if (ir_calc > ir) {
83 /* Increasing the denominator to select ir_s value */
84 while (ir_calc > ir) {
86 ir_calc = DIVISOR_IR_B_126 / (tick * (1 << ir_s_calc));
92 *ir_b = (ir * tick * (1 << ir_s_calc) +
93 (DIVISOR_CLK >> 1)) / DIVISOR_CLK;
95 /* Increasing the numerator to select ir_u value */
98 while (ir_calc < ir) {
100 numerator = DIVISOR_IR_B_126 * (1 << ir_u_calc);
101 ir_calc = (numerator + (tick >> 1)) / tick;
107 u32 denominator = (DIVISOR_CLK * (1 << --ir_u_calc));
108 *ir_b = (ir * tick + (denominator >> 1)) / denominator;
118 static int hclge_pfc_stats_get(struct hclge_dev *hdev,
119 enum hclge_opcode_type opcode, u64 *stats)
121 struct hclge_desc desc[HCLGE_TM_PFC_PKT_GET_CMD_NUM];
124 if (!(opcode == HCLGE_OPC_QUERY_PFC_RX_PKT_CNT ||
125 opcode == HCLGE_OPC_QUERY_PFC_TX_PKT_CNT))
128 for (i = 0; i < HCLGE_TM_PFC_PKT_GET_CMD_NUM - 1; i++) {
129 hclge_cmd_setup_basic_desc(&desc[i], opcode, true);
130 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
133 hclge_cmd_setup_basic_desc(&desc[i], opcode, true);
135 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_TM_PFC_PKT_GET_CMD_NUM);
139 for (i = 0; i < HCLGE_TM_PFC_PKT_GET_CMD_NUM; i++) {
140 struct hclge_pfc_stats_cmd *pfc_stats =
141 (struct hclge_pfc_stats_cmd *)desc[i].data;
143 for (j = 0; j < HCLGE_TM_PFC_NUM_GET_PER_CMD; j++) {
144 u32 index = i * HCLGE_TM_PFC_PKT_GET_CMD_NUM + j;
146 if (index < HCLGE_MAX_TC_NUM)
148 le64_to_cpu(pfc_stats->pkt_num[j]);
154 int hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats)
156 return hclge_pfc_stats_get(hdev, HCLGE_OPC_QUERY_PFC_RX_PKT_CNT, stats);
159 int hclge_pfc_tx_stats_get(struct hclge_dev *hdev, u64 *stats)
161 return hclge_pfc_stats_get(hdev, HCLGE_OPC_QUERY_PFC_TX_PKT_CNT, stats);
164 int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx)
166 struct hclge_desc desc;
168 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PAUSE_EN, false);
170 desc.data[0] = cpu_to_le32((tx ? HCLGE_TX_MAC_PAUSE_EN_MSK : 0) |
171 (rx ? HCLGE_RX_MAC_PAUSE_EN_MSK : 0));
173 return hclge_cmd_send(&hdev->hw, &desc, 1);
176 static int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap,
179 struct hclge_desc desc;
180 struct hclge_pfc_en_cmd *pfc = (struct hclge_pfc_en_cmd *)desc.data;
182 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PFC_PAUSE_EN, false);
184 pfc->tx_rx_en_bitmap = tx_rx_bitmap;
185 pfc->pri_en_bitmap = pfc_bitmap;
187 return hclge_cmd_send(&hdev->hw, &desc, 1);
190 static int hclge_pause_param_cfg(struct hclge_dev *hdev, const u8 *addr,
191 u8 pause_trans_gap, u16 pause_trans_time)
193 struct hclge_cfg_pause_param_cmd *pause_param;
194 struct hclge_desc desc;
196 pause_param = (struct hclge_cfg_pause_param_cmd *)desc.data;
198 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, false);
200 ether_addr_copy(pause_param->mac_addr, addr);
201 ether_addr_copy(pause_param->mac_addr_extra, addr);
202 pause_param->pause_trans_gap = pause_trans_gap;
203 pause_param->pause_trans_time = cpu_to_le16(pause_trans_time);
205 return hclge_cmd_send(&hdev->hw, &desc, 1);
208 int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr)
210 struct hclge_cfg_pause_param_cmd *pause_param;
211 struct hclge_desc desc;
216 pause_param = (struct hclge_cfg_pause_param_cmd *)desc.data;
218 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, true);
220 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
224 trans_gap = pause_param->pause_trans_gap;
225 trans_time = le16_to_cpu(pause_param->pause_trans_time);
227 return hclge_pause_param_cfg(hdev, mac_addr, trans_gap, trans_time);
230 static int hclge_fill_pri_array(struct hclge_dev *hdev, u8 *pri, u8 pri_id)
234 tc = hdev->tm_info.prio_tc[pri_id];
236 if (tc >= hdev->tm_info.num_tc)
240 * the register for priority has four bytes, the first bytes includes
241 * priority0 and priority1, the higher 4bit stands for priority1
242 * while the lower 4bit stands for priority0, as below:
243 * first byte: | pri_1 | pri_0 |
244 * second byte: | pri_3 | pri_2 |
245 * third byte: | pri_5 | pri_4 |
246 * fourth byte: | pri_7 | pri_6 |
248 pri[pri_id >> 1] |= tc << ((pri_id & 1) * 4);
253 static int hclge_up_to_tc_map(struct hclge_dev *hdev)
255 struct hclge_desc desc;
256 u8 *pri = (u8 *)desc.data;
260 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PRI_TO_TC_MAPPING, false);
262 for (pri_id = 0; pri_id < HNAE3_MAX_USER_PRIO; pri_id++) {
263 ret = hclge_fill_pri_array(hdev, pri, pri_id);
268 return hclge_cmd_send(&hdev->hw, &desc, 1);
271 static int hclge_tm_pg_to_pri_map_cfg(struct hclge_dev *hdev,
272 u8 pg_id, u8 pri_bit_map)
274 struct hclge_pg_to_pri_link_cmd *map;
275 struct hclge_desc desc;
277 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_TO_PRI_LINK, false);
279 map = (struct hclge_pg_to_pri_link_cmd *)desc.data;
282 map->pri_bit_map = pri_bit_map;
284 return hclge_cmd_send(&hdev->hw, &desc, 1);
287 static int hclge_tm_qs_to_pri_map_cfg(struct hclge_dev *hdev,
290 struct hclge_qs_to_pri_link_cmd *map;
291 struct hclge_desc desc;
293 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_TO_PRI_LINK, false);
295 map = (struct hclge_qs_to_pri_link_cmd *)desc.data;
297 map->qs_id = cpu_to_le16(qs_id);
299 map->link_vld = HCLGE_TM_QS_PRI_LINK_VLD_MSK;
301 return hclge_cmd_send(&hdev->hw, &desc, 1);
304 static int hclge_tm_q_to_qs_map_cfg(struct hclge_dev *hdev,
307 struct hclge_nq_to_qs_link_cmd *map;
308 struct hclge_desc desc;
310 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_NQ_TO_QS_LINK, false);
312 map = (struct hclge_nq_to_qs_link_cmd *)desc.data;
314 map->nq_id = cpu_to_le16(q_id);
315 map->qset_id = cpu_to_le16(qs_id | HCLGE_TM_Q_QS_LINK_VLD_MSK);
317 return hclge_cmd_send(&hdev->hw, &desc, 1);
320 static int hclge_tm_pg_weight_cfg(struct hclge_dev *hdev, u8 pg_id,
323 struct hclge_pg_weight_cmd *weight;
324 struct hclge_desc desc;
326 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_WEIGHT, false);
328 weight = (struct hclge_pg_weight_cmd *)desc.data;
330 weight->pg_id = pg_id;
333 return hclge_cmd_send(&hdev->hw, &desc, 1);
336 static int hclge_tm_pri_weight_cfg(struct hclge_dev *hdev, u8 pri_id,
339 struct hclge_priority_weight_cmd *weight;
340 struct hclge_desc desc;
342 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_WEIGHT, false);
344 weight = (struct hclge_priority_weight_cmd *)desc.data;
346 weight->pri_id = pri_id;
349 return hclge_cmd_send(&hdev->hw, &desc, 1);
352 static int hclge_tm_qs_weight_cfg(struct hclge_dev *hdev, u16 qs_id,
355 struct hclge_qs_weight_cmd *weight;
356 struct hclge_desc desc;
358 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_WEIGHT, false);
360 weight = (struct hclge_qs_weight_cmd *)desc.data;
362 weight->qs_id = cpu_to_le16(qs_id);
365 return hclge_cmd_send(&hdev->hw, &desc, 1);
368 static u32 hclge_tm_get_shapping_para(u8 ir_b, u8 ir_u, u8 ir_s,
371 u32 shapping_para = 0;
373 hclge_tm_set_field(shapping_para, IR_B, ir_b);
374 hclge_tm_set_field(shapping_para, IR_U, ir_u);
375 hclge_tm_set_field(shapping_para, IR_S, ir_s);
376 hclge_tm_set_field(shapping_para, BS_B, bs_b);
377 hclge_tm_set_field(shapping_para, BS_S, bs_s);
379 return shapping_para;
382 static int hclge_tm_pg_shapping_cfg(struct hclge_dev *hdev,
383 enum hclge_shap_bucket bucket, u8 pg_id,
386 struct hclge_pg_shapping_cmd *shap_cfg_cmd;
387 enum hclge_opcode_type opcode;
388 struct hclge_desc desc;
390 opcode = bucket ? HCLGE_OPC_TM_PG_P_SHAPPING :
391 HCLGE_OPC_TM_PG_C_SHAPPING;
392 hclge_cmd_setup_basic_desc(&desc, opcode, false);
394 shap_cfg_cmd = (struct hclge_pg_shapping_cmd *)desc.data;
396 shap_cfg_cmd->pg_id = pg_id;
398 shap_cfg_cmd->pg_shapping_para = cpu_to_le32(shapping_para);
400 return hclge_cmd_send(&hdev->hw, &desc, 1);
403 static int hclge_tm_port_shaper_cfg(struct hclge_dev *hdev)
405 struct hclge_port_shapping_cmd *shap_cfg_cmd;
406 struct hclge_desc desc;
407 u32 shapping_para = 0;
411 ret = hclge_shaper_para_calc(hdev->hw.mac.speed,
412 HCLGE_SHAPER_LVL_PORT,
413 &ir_b, &ir_u, &ir_s);
417 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PORT_SHAPPING, false);
418 shap_cfg_cmd = (struct hclge_port_shapping_cmd *)desc.data;
420 shapping_para = hclge_tm_get_shapping_para(ir_b, ir_u, ir_s,
421 HCLGE_SHAPER_BS_U_DEF,
422 HCLGE_SHAPER_BS_S_DEF);
424 shap_cfg_cmd->port_shapping_para = cpu_to_le32(shapping_para);
426 return hclge_cmd_send(&hdev->hw, &desc, 1);
429 static int hclge_tm_pri_shapping_cfg(struct hclge_dev *hdev,
430 enum hclge_shap_bucket bucket, u8 pri_id,
433 struct hclge_pri_shapping_cmd *shap_cfg_cmd;
434 enum hclge_opcode_type opcode;
435 struct hclge_desc desc;
437 opcode = bucket ? HCLGE_OPC_TM_PRI_P_SHAPPING :
438 HCLGE_OPC_TM_PRI_C_SHAPPING;
440 hclge_cmd_setup_basic_desc(&desc, opcode, false);
442 shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data;
444 shap_cfg_cmd->pri_id = pri_id;
446 shap_cfg_cmd->pri_shapping_para = cpu_to_le32(shapping_para);
448 return hclge_cmd_send(&hdev->hw, &desc, 1);
451 static int hclge_tm_pg_schd_mode_cfg(struct hclge_dev *hdev, u8 pg_id)
453 struct hclge_desc desc;
455 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_SCH_MODE_CFG, false);
457 if (hdev->tm_info.pg_info[pg_id].pg_sch_mode == HCLGE_SCH_MODE_DWRR)
458 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK);
462 desc.data[0] = cpu_to_le32(pg_id);
464 return hclge_cmd_send(&hdev->hw, &desc, 1);
467 static int hclge_tm_pri_schd_mode_cfg(struct hclge_dev *hdev, u8 pri_id)
469 struct hclge_desc desc;
471 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_SCH_MODE_CFG, false);
473 if (hdev->tm_info.tc_info[pri_id].tc_sch_mode == HCLGE_SCH_MODE_DWRR)
474 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK);
478 desc.data[0] = cpu_to_le32(pri_id);
480 return hclge_cmd_send(&hdev->hw, &desc, 1);
483 static int hclge_tm_qs_schd_mode_cfg(struct hclge_dev *hdev, u16 qs_id, u8 mode)
485 struct hclge_desc desc;
487 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_SCH_MODE_CFG, false);
489 if (mode == HCLGE_SCH_MODE_DWRR)
490 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK);
494 desc.data[0] = cpu_to_le32(qs_id);
496 return hclge_cmd_send(&hdev->hw, &desc, 1);
499 static int hclge_tm_qs_bp_cfg(struct hclge_dev *hdev, u8 tc, u8 grp_id,
502 struct hclge_bp_to_qs_map_cmd *bp_to_qs_map_cmd;
503 struct hclge_desc desc;
505 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_BP_TO_QSET_MAPPING,
508 bp_to_qs_map_cmd = (struct hclge_bp_to_qs_map_cmd *)desc.data;
510 bp_to_qs_map_cmd->tc_id = tc;
511 bp_to_qs_map_cmd->qs_group_id = grp_id;
512 bp_to_qs_map_cmd->qs_bit_map = cpu_to_le32(bit_map);
514 return hclge_cmd_send(&hdev->hw, &desc, 1);
517 static void hclge_tm_vport_tc_info_update(struct hclge_vport *vport)
519 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
520 struct hclge_dev *hdev = vport->back;
524 /* TC configuration is shared by PF/VF in one port, only allow
525 * one tc for VF for simplicity. VF's vport_id is non zero.
527 kinfo->num_tc = vport->vport_id ? 1 :
528 min_t(u16, vport->alloc_tqps, hdev->tm_info.num_tc);
529 vport->qs_offset = (vport->vport_id ? hdev->tm_info.num_tc : 0) +
530 (vport->vport_id ? (vport->vport_id - 1) : 0);
532 max_rss_size = min_t(u16, hdev->rss_size_max,
533 vport->alloc_tqps / kinfo->num_tc);
535 /* Set to user value, no larger than max_rss_size. */
536 if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size &&
537 kinfo->req_rss_size <= max_rss_size) {
538 dev_info(&hdev->pdev->dev, "rss changes from %d to %d\n",
539 kinfo->rss_size, kinfo->req_rss_size);
540 kinfo->rss_size = kinfo->req_rss_size;
541 } else if (kinfo->rss_size > max_rss_size ||
542 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) {
543 /* Set to the maximum specification value (max_rss_size). */
544 dev_info(&hdev->pdev->dev, "rss changes from %d to %d\n",
545 kinfo->rss_size, max_rss_size);
546 kinfo->rss_size = max_rss_size;
549 kinfo->num_tqps = kinfo->num_tc * kinfo->rss_size;
550 vport->dwrr = 100; /* 100 percent as init */
551 vport->alloc_rss_size = kinfo->rss_size;
552 vport->bw_limit = hdev->tm_info.pg_info[0].bw_limit;
554 for (i = 0; i < HNAE3_MAX_TC; i++) {
555 if (hdev->hw_tc_map & BIT(i) && i < kinfo->num_tc) {
556 kinfo->tc_info[i].enable = true;
557 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
558 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
559 kinfo->tc_info[i].tc = i;
561 /* Set to default queue if TC is disable */
562 kinfo->tc_info[i].enable = false;
563 kinfo->tc_info[i].tqp_offset = 0;
564 kinfo->tc_info[i].tqp_count = 1;
565 kinfo->tc_info[i].tc = 0;
569 memcpy(kinfo->prio_tc, hdev->tm_info.prio_tc,
570 FIELD_SIZEOF(struct hnae3_knic_private_info, prio_tc));
573 static void hclge_tm_vport_info_update(struct hclge_dev *hdev)
575 struct hclge_vport *vport = hdev->vport;
578 for (i = 0; i < hdev->num_alloc_vport; i++) {
579 hclge_tm_vport_tc_info_update(vport);
585 static void hclge_tm_tc_info_init(struct hclge_dev *hdev)
589 for (i = 0; i < hdev->tm_info.num_tc; i++) {
590 hdev->tm_info.tc_info[i].tc_id = i;
591 hdev->tm_info.tc_info[i].tc_sch_mode = HCLGE_SCH_MODE_DWRR;
592 hdev->tm_info.tc_info[i].pgid = 0;
593 hdev->tm_info.tc_info[i].bw_limit =
594 hdev->tm_info.pg_info[0].bw_limit;
597 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
598 hdev->tm_info.prio_tc[i] =
599 (i >= hdev->tm_info.num_tc) ? 0 : i;
601 /* DCB is enabled if we have more than 1 TC or pfc_en is
604 if (hdev->tm_info.num_tc > 1 || hdev->tm_info.pfc_en)
605 hdev->flag |= HCLGE_FLAG_DCB_ENABLE;
607 hdev->flag &= ~HCLGE_FLAG_DCB_ENABLE;
610 static void hclge_tm_pg_info_init(struct hclge_dev *hdev)
612 #define BW_PERCENT 100
616 for (i = 0; i < hdev->tm_info.num_pg; i++) {
619 hdev->tm_info.pg_dwrr[i] = i ? 0 : BW_PERCENT;
621 hdev->tm_info.pg_info[i].pg_id = i;
622 hdev->tm_info.pg_info[i].pg_sch_mode = HCLGE_SCH_MODE_DWRR;
624 hdev->tm_info.pg_info[i].bw_limit = HCLGE_ETHER_MAX_RATE;
629 hdev->tm_info.pg_info[i].tc_bit_map = hdev->hw_tc_map;
630 for (k = 0; k < hdev->tm_info.num_tc; k++)
631 hdev->tm_info.pg_info[i].tc_dwrr[k] = BW_PERCENT;
635 static void hclge_pfc_info_init(struct hclge_dev *hdev)
637 if (!(hdev->flag & HCLGE_FLAG_DCB_ENABLE)) {
638 if (hdev->fc_mode_last_time == HCLGE_FC_PFC)
639 dev_warn(&hdev->pdev->dev,
640 "DCB is disable, but last mode is FC_PFC\n");
642 hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
643 } else if (hdev->tm_info.fc_mode != HCLGE_FC_PFC) {
644 /* fc_mode_last_time record the last fc_mode when
645 * DCB is enabled, so that fc_mode can be set to
646 * the correct value when DCB is disabled.
648 hdev->fc_mode_last_time = hdev->tm_info.fc_mode;
649 hdev->tm_info.fc_mode = HCLGE_FC_PFC;
653 static int hclge_tm_schd_info_init(struct hclge_dev *hdev)
655 if ((hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) &&
656 (hdev->tm_info.num_pg != 1))
659 hclge_tm_pg_info_init(hdev);
661 hclge_tm_tc_info_init(hdev);
663 hclge_tm_vport_info_update(hdev);
665 hclge_pfc_info_init(hdev);
670 static int hclge_tm_pg_to_pri_map(struct hclge_dev *hdev)
675 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE)
678 for (i = 0; i < hdev->tm_info.num_pg; i++) {
680 ret = hclge_tm_pg_to_pri_map_cfg(
681 hdev, i, hdev->tm_info.pg_info[i].tc_bit_map);
689 static int hclge_tm_pg_shaper_cfg(struct hclge_dev *hdev)
697 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE)
701 for (i = 0; i < hdev->tm_info.num_pg; i++) {
702 /* Calc shaper para */
703 ret = hclge_shaper_para_calc(
704 hdev->tm_info.pg_info[i].bw_limit,
706 &ir_b, &ir_u, &ir_s);
710 shaper_para = hclge_tm_get_shapping_para(0, 0, 0,
711 HCLGE_SHAPER_BS_U_DEF,
712 HCLGE_SHAPER_BS_S_DEF);
713 ret = hclge_tm_pg_shapping_cfg(hdev,
714 HCLGE_TM_SHAP_C_BUCKET, i,
719 shaper_para = hclge_tm_get_shapping_para(ir_b, ir_u, ir_s,
720 HCLGE_SHAPER_BS_U_DEF,
721 HCLGE_SHAPER_BS_S_DEF);
722 ret = hclge_tm_pg_shapping_cfg(hdev,
723 HCLGE_TM_SHAP_P_BUCKET, i,
732 static int hclge_tm_pg_dwrr_cfg(struct hclge_dev *hdev)
738 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE)
742 for (i = 0; i < hdev->tm_info.num_pg; i++) {
744 ret = hclge_tm_pg_weight_cfg(hdev, i, hdev->tm_info.pg_dwrr[i]);
752 static int hclge_vport_q_to_qs_map(struct hclge_dev *hdev,
753 struct hclge_vport *vport)
755 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
756 struct hnae3_queue **tqp = kinfo->tqp;
757 struct hnae3_tc_info *v_tc_info;
761 for (i = 0; i < kinfo->num_tc; i++) {
762 v_tc_info = &kinfo->tc_info[i];
763 for (j = 0; j < v_tc_info->tqp_count; j++) {
764 struct hnae3_queue *q = tqp[v_tc_info->tqp_offset + j];
766 ret = hclge_tm_q_to_qs_map_cfg(hdev,
767 hclge_get_queue_id(q),
768 vport->qs_offset + i);
777 static int hclge_tm_pri_q_qs_cfg(struct hclge_dev *hdev)
779 struct hclge_vport *vport = hdev->vport;
783 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {
784 /* Cfg qs -> pri mapping, one by one mapping */
785 for (k = 0; k < hdev->num_alloc_vport; k++) {
786 struct hnae3_knic_private_info *kinfo =
789 for (i = 0; i < kinfo->num_tc; i++) {
790 ret = hclge_tm_qs_to_pri_map_cfg(
791 hdev, vport[k].qs_offset + i, i);
796 } else if (hdev->tx_sch_mode == HCLGE_FLAG_VNET_BASE_SCH_MODE) {
797 /* Cfg qs -> pri mapping, qs = tc, pri = vf, 8 qs -> 1 pri */
798 for (k = 0; k < hdev->num_alloc_vport; k++)
799 for (i = 0; i < HNAE3_MAX_TC; i++) {
800 ret = hclge_tm_qs_to_pri_map_cfg(
801 hdev, vport[k].qs_offset + i, k);
809 /* Cfg q -> qs mapping */
810 for (i = 0; i < hdev->num_alloc_vport; i++) {
811 ret = hclge_vport_q_to_qs_map(hdev, vport);
821 static int hclge_tm_pri_tc_base_shaper_cfg(struct hclge_dev *hdev)
828 for (i = 0; i < hdev->tm_info.num_tc; i++) {
829 ret = hclge_shaper_para_calc(
830 hdev->tm_info.tc_info[i].bw_limit,
831 HCLGE_SHAPER_LVL_PRI,
832 &ir_b, &ir_u, &ir_s);
836 shaper_para = hclge_tm_get_shapping_para(0, 0, 0,
837 HCLGE_SHAPER_BS_U_DEF,
838 HCLGE_SHAPER_BS_S_DEF);
839 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_C_BUCKET, i,
844 shaper_para = hclge_tm_get_shapping_para(ir_b, ir_u, ir_s,
845 HCLGE_SHAPER_BS_U_DEF,
846 HCLGE_SHAPER_BS_S_DEF);
847 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_P_BUCKET, i,
856 static int hclge_tm_pri_vnet_base_shaper_pri_cfg(struct hclge_vport *vport)
858 struct hclge_dev *hdev = vport->back;
863 ret = hclge_shaper_para_calc(vport->bw_limit, HCLGE_SHAPER_LVL_VF,
864 &ir_b, &ir_u, &ir_s);
868 shaper_para = hclge_tm_get_shapping_para(0, 0, 0,
869 HCLGE_SHAPER_BS_U_DEF,
870 HCLGE_SHAPER_BS_S_DEF);
871 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_C_BUCKET,
872 vport->vport_id, shaper_para);
876 shaper_para = hclge_tm_get_shapping_para(ir_b, ir_u, ir_s,
877 HCLGE_SHAPER_BS_U_DEF,
878 HCLGE_SHAPER_BS_S_DEF);
879 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_P_BUCKET,
880 vport->vport_id, shaper_para);
887 static int hclge_tm_pri_vnet_base_shaper_qs_cfg(struct hclge_vport *vport)
889 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
890 struct hclge_dev *hdev = vport->back;
895 for (i = 0; i < kinfo->num_tc; i++) {
896 ret = hclge_shaper_para_calc(
897 hdev->tm_info.tc_info[i].bw_limit,
898 HCLGE_SHAPER_LVL_QSET,
899 &ir_b, &ir_u, &ir_s);
907 static int hclge_tm_pri_vnet_base_shaper_cfg(struct hclge_dev *hdev)
909 struct hclge_vport *vport = hdev->vport;
913 /* Need config vport shaper */
914 for (i = 0; i < hdev->num_alloc_vport; i++) {
915 ret = hclge_tm_pri_vnet_base_shaper_pri_cfg(vport);
919 ret = hclge_tm_pri_vnet_base_shaper_qs_cfg(vport);
929 static int hclge_tm_pri_shaper_cfg(struct hclge_dev *hdev)
933 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {
934 ret = hclge_tm_pri_tc_base_shaper_cfg(hdev);
938 ret = hclge_tm_pri_vnet_base_shaper_cfg(hdev);
946 static int hclge_tm_pri_tc_base_dwrr_cfg(struct hclge_dev *hdev)
948 struct hclge_vport *vport = hdev->vport;
949 struct hclge_pg_info *pg_info;
954 for (i = 0; i < hdev->tm_info.num_tc; i++) {
956 &hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid];
957 dwrr = pg_info->tc_dwrr[i];
959 ret = hclge_tm_pri_weight_cfg(hdev, i, dwrr);
963 for (k = 0; k < hdev->num_alloc_vport; k++) {
964 ret = hclge_tm_qs_weight_cfg(
965 hdev, vport[k].qs_offset + i,
975 static int hclge_tm_ets_tc_dwrr_cfg(struct hclge_dev *hdev)
977 #define DEFAULT_TC_WEIGHT 1
978 #define DEFAULT_TC_OFFSET 14
980 struct hclge_ets_tc_weight_cmd *ets_weight;
981 struct hclge_desc desc;
984 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ETS_TC_WEIGHT, false);
985 ets_weight = (struct hclge_ets_tc_weight_cmd *)desc.data;
987 for (i = 0; i < HNAE3_MAX_TC; i++) {
988 struct hclge_pg_info *pg_info;
990 ets_weight->tc_weight[i] = DEFAULT_TC_WEIGHT;
992 if (!(hdev->hw_tc_map & BIT(i)))
996 &hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid];
997 ets_weight->tc_weight[i] = pg_info->tc_dwrr[i];
1000 ets_weight->weight_offset = DEFAULT_TC_OFFSET;
1002 return hclge_cmd_send(&hdev->hw, &desc, 1);
1005 static int hclge_tm_pri_vnet_base_dwrr_pri_cfg(struct hclge_vport *vport)
1007 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
1008 struct hclge_dev *hdev = vport->back;
1013 ret = hclge_tm_pri_weight_cfg(hdev, vport->vport_id, vport->dwrr);
1018 for (i = 0; i < kinfo->num_tc; i++) {
1019 ret = hclge_tm_qs_weight_cfg(
1020 hdev, vport->qs_offset + i,
1021 hdev->tm_info.pg_info[0].tc_dwrr[i]);
1029 static int hclge_tm_pri_vnet_base_dwrr_cfg(struct hclge_dev *hdev)
1031 struct hclge_vport *vport = hdev->vport;
1035 for (i = 0; i < hdev->num_alloc_vport; i++) {
1036 ret = hclge_tm_pri_vnet_base_dwrr_pri_cfg(vport);
1046 static int hclge_tm_pri_dwrr_cfg(struct hclge_dev *hdev)
1050 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {
1051 ret = hclge_tm_pri_tc_base_dwrr_cfg(hdev);
1055 if (!hnae3_dev_dcb_supported(hdev))
1058 ret = hclge_tm_ets_tc_dwrr_cfg(hdev);
1059 if (ret == -EOPNOTSUPP) {
1060 dev_warn(&hdev->pdev->dev,
1061 "fw %08x does't support ets tc weight cmd\n",
1068 ret = hclge_tm_pri_vnet_base_dwrr_cfg(hdev);
1076 static int hclge_tm_map_cfg(struct hclge_dev *hdev)
1080 ret = hclge_up_to_tc_map(hdev);
1084 ret = hclge_tm_pg_to_pri_map(hdev);
1088 return hclge_tm_pri_q_qs_cfg(hdev);
1091 static int hclge_tm_shaper_cfg(struct hclge_dev *hdev)
1095 ret = hclge_tm_port_shaper_cfg(hdev);
1099 ret = hclge_tm_pg_shaper_cfg(hdev);
1103 return hclge_tm_pri_shaper_cfg(hdev);
1106 int hclge_tm_dwrr_cfg(struct hclge_dev *hdev)
1110 ret = hclge_tm_pg_dwrr_cfg(hdev);
1114 return hclge_tm_pri_dwrr_cfg(hdev);
1117 static int hclge_tm_lvl2_schd_mode_cfg(struct hclge_dev *hdev)
1122 /* Only being config on TC-Based scheduler mode */
1123 if (hdev->tx_sch_mode == HCLGE_FLAG_VNET_BASE_SCH_MODE)
1126 for (i = 0; i < hdev->tm_info.num_pg; i++) {
1127 ret = hclge_tm_pg_schd_mode_cfg(hdev, i);
1135 static int hclge_tm_schd_mode_vnet_base_cfg(struct hclge_vport *vport)
1137 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
1138 struct hclge_dev *hdev = vport->back;
1142 if (vport->vport_id >= HNAE3_MAX_TC)
1145 ret = hclge_tm_pri_schd_mode_cfg(hdev, vport->vport_id);
1149 for (i = 0; i < kinfo->num_tc; i++) {
1150 u8 sch_mode = hdev->tm_info.tc_info[i].tc_sch_mode;
1152 ret = hclge_tm_qs_schd_mode_cfg(hdev, vport->qs_offset + i,
1161 static int hclge_tm_lvl34_schd_mode_cfg(struct hclge_dev *hdev)
1163 struct hclge_vport *vport = hdev->vport;
1167 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {
1168 for (i = 0; i < hdev->tm_info.num_tc; i++) {
1169 ret = hclge_tm_pri_schd_mode_cfg(hdev, i);
1173 for (k = 0; k < hdev->num_alloc_vport; k++) {
1174 ret = hclge_tm_qs_schd_mode_cfg(
1175 hdev, vport[k].qs_offset + i,
1176 HCLGE_SCH_MODE_DWRR);
1182 for (i = 0; i < hdev->num_alloc_vport; i++) {
1183 ret = hclge_tm_schd_mode_vnet_base_cfg(vport);
1194 static int hclge_tm_schd_mode_hw(struct hclge_dev *hdev)
1198 ret = hclge_tm_lvl2_schd_mode_cfg(hdev);
1202 return hclge_tm_lvl34_schd_mode_cfg(hdev);
1205 int hclge_tm_schd_setup_hw(struct hclge_dev *hdev)
1209 /* Cfg tm mapping */
1210 ret = hclge_tm_map_cfg(hdev);
1215 ret = hclge_tm_shaper_cfg(hdev);
1220 ret = hclge_tm_dwrr_cfg(hdev);
1224 /* Cfg schd mode for each level schd */
1225 return hclge_tm_schd_mode_hw(hdev);
1228 static int hclge_pause_param_setup_hw(struct hclge_dev *hdev)
1230 struct hclge_mac *mac = &hdev->hw.mac;
1232 return hclge_pause_param_cfg(hdev, mac->mac_addr,
1233 HCLGE_DEFAULT_PAUSE_TRANS_GAP,
1234 HCLGE_DEFAULT_PAUSE_TRANS_TIME);
1237 static int hclge_pfc_setup_hw(struct hclge_dev *hdev)
1239 u8 enable_bitmap = 0;
1241 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
1242 enable_bitmap = HCLGE_TX_MAC_PAUSE_EN_MSK |
1243 HCLGE_RX_MAC_PAUSE_EN_MSK;
1245 return hclge_pfc_pause_en_cfg(hdev, enable_bitmap,
1246 hdev->tm_info.pfc_en);
1249 /* Each Tc has a 1024 queue sets to backpress, it divides to
1250 * 32 group, each group contains 32 queue sets, which can be
1251 * represented by u32 bitmap.
1253 static int hclge_bp_setup_hw(struct hclge_dev *hdev, u8 tc)
1257 for (i = 0; i < HCLGE_BP_GRP_NUM; i++) {
1261 for (k = 0; k < hdev->num_alloc_vport; k++) {
1262 struct hclge_vport *vport = &hdev->vport[k];
1263 u16 qs_id = vport->qs_offset + tc;
1266 grp = hnae3_get_field(qs_id, HCLGE_BP_GRP_ID_M,
1268 sub_grp = hnae3_get_field(qs_id, HCLGE_BP_SUB_GRP_ID_M,
1269 HCLGE_BP_SUB_GRP_ID_S);
1271 qs_bitmap |= (1 << sub_grp);
1274 ret = hclge_tm_qs_bp_cfg(hdev, tc, i, qs_bitmap);
1282 static int hclge_mac_pause_setup_hw(struct hclge_dev *hdev)
1286 switch (hdev->tm_info.fc_mode) {
1291 case HCLGE_FC_RX_PAUSE:
1295 case HCLGE_FC_TX_PAUSE:
1312 return hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
1315 static int hclge_tm_bp_setup(struct hclge_dev *hdev)
1320 for (i = 0; i < hdev->tm_info.num_tc; i++) {
1321 ret = hclge_bp_setup_hw(hdev, i);
1329 int hclge_pause_setup_hw(struct hclge_dev *hdev, bool init)
1333 ret = hclge_pause_param_setup_hw(hdev);
1337 ret = hclge_mac_pause_setup_hw(hdev);
1341 /* Only DCB-supported dev supports qset back pressure and pfc cmd */
1342 if (!hnae3_dev_dcb_supported(hdev))
1345 /* GE MAC does not support PFC, when driver is initializing and MAC
1346 * is in GE Mode, ignore the error here, otherwise initialization
1349 ret = hclge_pfc_setup_hw(hdev);
1350 if (init && ret == -EOPNOTSUPP)
1351 dev_warn(&hdev->pdev->dev, "GE MAC does not support pfc\n");
1353 dev_err(&hdev->pdev->dev, "config pfc failed! ret = %d\n",
1358 return hclge_tm_bp_setup(hdev);
1361 void hclge_tm_prio_tc_info_update(struct hclge_dev *hdev, u8 *prio_tc)
1363 struct hclge_vport *vport = hdev->vport;
1364 struct hnae3_knic_private_info *kinfo;
1367 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
1368 hdev->tm_info.prio_tc[i] = prio_tc[i];
1370 for (k = 0; k < hdev->num_alloc_vport; k++) {
1371 kinfo = &vport[k].nic.kinfo;
1372 kinfo->prio_tc[i] = prio_tc[i];
1377 void hclge_tm_schd_info_update(struct hclge_dev *hdev, u8 num_tc)
1382 hdev->tm_info.num_tc = num_tc;
1384 for (i = 0; i < hdev->tm_info.num_tc; i++)
1389 hdev->tm_info.num_tc = 1;
1392 hdev->hw_tc_map = bit_map;
1394 hclge_tm_schd_info_init(hdev);
1397 void hclge_tm_pfc_info_update(struct hclge_dev *hdev)
1399 /* DCB is enabled if we have more than 1 TC or pfc_en is
1402 if (hdev->tm_info.num_tc > 1 || hdev->tm_info.pfc_en)
1403 hdev->flag |= HCLGE_FLAG_DCB_ENABLE;
1405 hdev->flag &= ~HCLGE_FLAG_DCB_ENABLE;
1407 hclge_pfc_info_init(hdev);
1410 int hclge_tm_init_hw(struct hclge_dev *hdev, bool init)
1414 if ((hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) &&
1415 (hdev->tx_sch_mode != HCLGE_FLAG_VNET_BASE_SCH_MODE))
1418 ret = hclge_tm_schd_setup_hw(hdev);
1422 ret = hclge_pause_setup_hw(hdev, init);
1429 int hclge_tm_schd_init(struct hclge_dev *hdev)
1433 /* fc_mode is HCLGE_FC_FULL on reset */
1434 hdev->tm_info.fc_mode = HCLGE_FC_FULL;
1435 hdev->fc_mode_last_time = hdev->tm_info.fc_mode;
1437 ret = hclge_tm_schd_info_init(hdev);
1441 return hclge_tm_init_hw(hdev, true);
1444 int hclge_tm_vport_map_update(struct hclge_dev *hdev)
1446 struct hclge_vport *vport = hdev->vport;
1449 hclge_tm_vport_tc_info_update(vport);
1451 ret = hclge_vport_q_to_qs_map(hdev, vport);
1455 if (!(hdev->flag & HCLGE_FLAG_DCB_ENABLE))
1458 return hclge_tm_bp_setup(hdev);