drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4 #include <linux/acpi.h>
   5 #include <linux/device.h>
   6 #include <linux/etherdevice.h>
   7 #include <linux/init.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/netdevice.h>
  12 #include <linux/pci.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/if_vlan.h>
  15 #include <linux/crash_dump.h>
  16 #include <net/ipv6.h>
  17 #include <net/rtnetlink.h>
  18 #include "hclge_cmd.h"
  19 #include "hclge_dcb.h"
  20 #include "hclge_main.h"
  21 #include "hclge_mbx.h"
  22 #include "hclge_mdio.h"
  23 #include "hclge_tm.h"
  24 #include "hclge_err.h"
  25 #include "hnae3.h"
  26 #include "hclge_devlink.h"
  27 #include "hclge_comm_cmd.h"
  28
  29 #define HCLGE_NAME                      "hclge"
  30
  31 #define HCLGE_BUF_SIZE_UNIT     256U
  32 #define HCLGE_BUF_MUL_BY        2
  33 #define HCLGE_BUF_DIV_BY        2
  34 #define NEED_RESERVE_TC_NUM     2
  35 #define BUF_MAX_PERCENT         100
  36 #define BUF_RESERVE_PERCENT     90
  37
  38 #define HCLGE_RESET_MAX_FAIL_CNT        5
  39 #define HCLGE_RESET_SYNC_TIME           100
  40 #define HCLGE_PF_RESET_SYNC_TIME        20
  41 #define HCLGE_PF_RESET_SYNC_CNT         1500
  42
  43 /* Get DFX BD number offset */
  44 #define HCLGE_DFX_BIOS_BD_OFFSET        1
  45 #define HCLGE_DFX_SSU_0_BD_OFFSET       2
  46 #define HCLGE_DFX_SSU_1_BD_OFFSET       3
  47 #define HCLGE_DFX_IGU_BD_OFFSET         4
  48 #define HCLGE_DFX_RPU_0_BD_OFFSET       5
  49 #define HCLGE_DFX_RPU_1_BD_OFFSET       6
  50 #define HCLGE_DFX_NCSI_BD_OFFSET        7
  51 #define HCLGE_DFX_RTC_BD_OFFSET         8
  52 #define HCLGE_DFX_PPP_BD_OFFSET         9
  53 #define HCLGE_DFX_RCB_BD_OFFSET         10
  54 #define HCLGE_DFX_TQP_BD_OFFSET         11
  55 #define HCLGE_DFX_SSU_2_BD_OFFSET       12
  56
  57 #define HCLGE_LINK_STATUS_MS    10
  58
  59 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps);
  60 static int hclge_init_vlan_config(struct hclge_dev *hdev);
  61 static void hclge_sync_vlan_filter(struct hclge_dev *hdev);
  62 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
  63 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle);
  64 static void hclge_rfs_filter_expire(struct hclge_dev *hdev);
  65 static int hclge_clear_arfs_rules(struct hclge_dev *hdev);
  66 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev,
  67                                                    unsigned long *addr);
  68 static int hclge_set_default_loopback(struct hclge_dev *hdev);
  69
  70 static void hclge_sync_mac_table(struct hclge_dev *hdev);
  71 static void hclge_restore_hw_table(struct hclge_dev *hdev);
  72 static void hclge_sync_promisc_mode(struct hclge_dev *hdev);
  73 static void hclge_sync_fd_table(struct hclge_dev *hdev);
  74 static void hclge_update_fec_stats(struct hclge_dev *hdev);
  75
  76 static struct hnae3_ae_algo ae_algo;
  77
  78 static struct workqueue_struct *hclge_wq;
  79
  80 static const struct pci_device_id ae_algo_pci_tbl[] = {
  81         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
  82         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
  83         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
  84         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
  85         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
  86         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
  87         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
  88         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0},
  89         /* required last entry */
  90         {0, }
  91 };
  92
  93 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
  94
  95 static const u32 cmdq_reg_addr_list[] = {HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG,
  96                                          HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG,
  97                                          HCLGE_COMM_NIC_CSQ_DEPTH_REG,
  98                                          HCLGE_COMM_NIC_CSQ_TAIL_REG,
  99                                          HCLGE_COMM_NIC_CSQ_HEAD_REG,
 100                                          HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG,
 101                                          HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG,
 102                                          HCLGE_COMM_NIC_CRQ_DEPTH_REG,
 103                                          HCLGE_COMM_NIC_CRQ_TAIL_REG,
 104                                          HCLGE_COMM_NIC_CRQ_HEAD_REG,
 105                                          HCLGE_COMM_VECTOR0_CMDQ_SRC_REG,
 106                                          HCLGE_COMM_CMDQ_INTR_STS_REG,
 107                                          HCLGE_COMM_CMDQ_INTR_EN_REG,
 108                                          HCLGE_COMM_CMDQ_INTR_GEN_REG};
 109
 110 static const u32 common_reg_addr_list[] = {HCLGE_MISC_VECTOR_REG_BASE,
 111                                            HCLGE_PF_OTHER_INT_REG,
 112                                            HCLGE_MISC_RESET_STS_REG,
 113                                            HCLGE_MISC_VECTOR_INT_STS,
 114                                            HCLGE_GLOBAL_RESET_REG,
 115                                            HCLGE_FUN_RST_ING,
 116                                            HCLGE_GRO_EN_REG};
 117
 118 static const u32 ring_reg_addr_list[] = {HCLGE_RING_RX_ADDR_L_REG,
 119                                          HCLGE_RING_RX_ADDR_H_REG,
 120                                          HCLGE_RING_RX_BD_NUM_REG,
 121                                          HCLGE_RING_RX_BD_LENGTH_REG,
 122                                          HCLGE_RING_RX_MERGE_EN_REG,
 123                                          HCLGE_RING_RX_TAIL_REG,
 124                                          HCLGE_RING_RX_HEAD_REG,
 125                                          HCLGE_RING_RX_FBD_NUM_REG,
 126                                          HCLGE_RING_RX_OFFSET_REG,
 127                                          HCLGE_RING_RX_FBD_OFFSET_REG,
 128                                          HCLGE_RING_RX_STASH_REG,
 129                                          HCLGE_RING_RX_BD_ERR_REG,
 130                                          HCLGE_RING_TX_ADDR_L_REG,
 131                                          HCLGE_RING_TX_ADDR_H_REG,
 132                                          HCLGE_RING_TX_BD_NUM_REG,
 133                                          HCLGE_RING_TX_PRIORITY_REG,
 134                                          HCLGE_RING_TX_TC_REG,
 135                                          HCLGE_RING_TX_MERGE_EN_REG,
 136                                          HCLGE_RING_TX_TAIL_REG,
 137                                          HCLGE_RING_TX_HEAD_REG,
 138                                          HCLGE_RING_TX_FBD_NUM_REG,
 139                                          HCLGE_RING_TX_OFFSET_REG,
 140                                          HCLGE_RING_TX_EBD_NUM_REG,
 141                                          HCLGE_RING_TX_EBD_OFFSET_REG,
 142                                          HCLGE_RING_TX_BD_ERR_REG,
 143                                          HCLGE_RING_EN_REG};
 144
 145 static const u32 tqp_intr_reg_addr_list[] = {HCLGE_TQP_INTR_CTRL_REG,
 146                                              HCLGE_TQP_INTR_GL0_REG,
 147                                              HCLGE_TQP_INTR_GL1_REG,
 148                                              HCLGE_TQP_INTR_GL2_REG,
 149                                              HCLGE_TQP_INTR_RL_REG};
 150
 151 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
 152         "External Loopback test",
 153         "App      Loopback test",
 154         "Serdes   serial Loopback test",
 155         "Serdes   parallel Loopback test",
 156         "Phy      Loopback test"
 157 };
 158
 159 static const struct hclge_comm_stats_str g_mac_stats_string[] = {
 160         {"mac_tx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 161                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
 162         {"mac_rx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 163                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
 164         {"mac_tx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 165                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pause_xoff_time)},
 166         {"mac_rx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 167                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pause_xoff_time)},
 168         {"mac_tx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 169                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_ctrl_pkt_num)},
 170         {"mac_rx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 171                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_ctrl_pkt_num)},
 172         {"mac_tx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 173                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pause_pkt_num)},
 174         {"mac_tx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 175                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
 176         {"mac_tx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 177                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
 178         {"mac_tx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 179                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
 180         {"mac_tx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 181                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
 182         {"mac_tx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 183                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
 184         {"mac_tx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 185                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
 186         {"mac_tx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 187                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
 188         {"mac_tx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 189                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
 190         {"mac_tx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 191                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_xoff_time)},
 192         {"mac_tx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 193                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_xoff_time)},
 194         {"mac_tx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 195                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_xoff_time)},
 196         {"mac_tx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 197                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_xoff_time)},
 198         {"mac_tx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 199                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_xoff_time)},
 200         {"mac_tx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 201                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_xoff_time)},
 202         {"mac_tx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 203                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_xoff_time)},
 204         {"mac_tx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 205                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_xoff_time)},
 206         {"mac_rx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 207                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pause_pkt_num)},
 208         {"mac_rx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 209                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
 210         {"mac_rx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 211                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
 212         {"mac_rx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 213                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
 214         {"mac_rx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 215                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
 216         {"mac_rx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 217                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
 218         {"mac_rx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 219                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
 220         {"mac_rx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 221                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
 222         {"mac_rx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 223                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
 224         {"mac_rx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 225                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_xoff_time)},
 226         {"mac_rx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 227                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_xoff_time)},
 228         {"mac_rx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 229                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_xoff_time)},
 230         {"mac_rx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 231                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_xoff_time)},
 232         {"mac_rx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 233                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_xoff_time)},
 234         {"mac_rx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 235                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_xoff_time)},
 236         {"mac_rx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 237                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_xoff_time)},
 238         {"mac_rx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 239                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_xoff_time)},
 240         {"mac_tx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 241                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
 242         {"mac_tx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 243                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
 244         {"mac_tx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 245                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
 246         {"mac_tx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 247                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
 248         {"mac_tx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 249                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
 250         {"mac_tx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 251                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
 252         {"mac_tx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 253                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
 254         {"mac_tx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 255                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
 256         {"mac_tx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 257                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
 258         {"mac_tx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 259                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
 260         {"mac_tx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 261                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
 262         {"mac_tx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 263                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
 264         {"mac_tx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 265                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
 266         {"mac_tx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 267                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
 268         {"mac_tx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 269                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
 270         {"mac_tx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 271                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
 272         {"mac_tx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 273                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
 274         {"mac_tx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 275                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
 276         {"mac_tx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 277                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
 278         {"mac_tx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 279                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
 280         {"mac_tx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 281                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
 282         {"mac_tx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 283                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
 284         {"mac_tx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 285                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
 286         {"mac_tx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 287                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
 288         {"mac_tx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 289                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
 290         {"mac_rx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 291                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
 292         {"mac_rx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 293                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
 294         {"mac_rx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 295                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
 296         {"mac_rx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 297                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
 298         {"mac_rx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 299                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
 300         {"mac_rx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 301                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
 302         {"mac_rx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 303                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
 304         {"mac_rx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 305                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
 306         {"mac_rx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 307                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
 308         {"mac_rx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 309                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
 310         {"mac_rx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 311                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
 312         {"mac_rx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 313                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
 314         {"mac_rx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 315                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
 316         {"mac_rx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 317                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
 318         {"mac_rx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 319                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
 320         {"mac_rx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 321                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
 322         {"mac_rx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 323                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
 324         {"mac_rx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 325                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
 326         {"mac_rx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 327                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
 328         {"mac_rx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 329                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
 330         {"mac_rx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 331                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
 332         {"mac_rx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 333                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
 334         {"mac_rx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 335                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
 336         {"mac_rx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 337                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
 338         {"mac_rx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 339                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
 340
 341         {"mac_tx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 342                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
 343         {"mac_tx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 344                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
 345         {"mac_tx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 346                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
 347         {"mac_tx_err_all_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 348                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
 349         {"mac_tx_from_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 350                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
 351         {"mac_tx_from_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 352                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
 353         {"mac_rx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 354                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
 355         {"mac_rx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 356                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
 357         {"mac_rx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 358                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
 359         {"mac_rx_fcs_err_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 360                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
 361         {"mac_rx_send_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 362                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
 363         {"mac_rx_send_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 364                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
 365 };
 366
 367 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
 368         {
 369                 .flags = HCLGE_MAC_MGR_MASK_VLAN_B,
 370                 .ethter_type = cpu_to_le16(ETH_P_LLDP),
 371                 .mac_addr = {0x01, 0x80, 0xc2, 0x00, 0x00, 0x0e},
 372                 .i_port_bitmap = 0x1,
 373         },
 374 };
 375
 376 static const u32 hclge_dfx_bd_offset_list[] = {
 377         HCLGE_DFX_BIOS_BD_OFFSET,
 378         HCLGE_DFX_SSU_0_BD_OFFSET,
 379         HCLGE_DFX_SSU_1_BD_OFFSET,
 380         HCLGE_DFX_IGU_BD_OFFSET,
 381         HCLGE_DFX_RPU_0_BD_OFFSET,
 382         HCLGE_DFX_RPU_1_BD_OFFSET,
 383         HCLGE_DFX_NCSI_BD_OFFSET,
 384         HCLGE_DFX_RTC_BD_OFFSET,
 385         HCLGE_DFX_PPP_BD_OFFSET,
 386         HCLGE_DFX_RCB_BD_OFFSET,
 387         HCLGE_DFX_TQP_BD_OFFSET,
 388         HCLGE_DFX_SSU_2_BD_OFFSET
 389 };
 390
 391 static const enum hclge_opcode_type hclge_dfx_reg_opcode_list[] = {
 392         HCLGE_OPC_DFX_BIOS_COMMON_REG,
 393         HCLGE_OPC_DFX_SSU_REG_0,
 394         HCLGE_OPC_DFX_SSU_REG_1,
 395         HCLGE_OPC_DFX_IGU_EGU_REG,
 396         HCLGE_OPC_DFX_RPU_REG_0,
 397         HCLGE_OPC_DFX_RPU_REG_1,
 398         HCLGE_OPC_DFX_NCSI_REG,
 399         HCLGE_OPC_DFX_RTC_REG,
 400         HCLGE_OPC_DFX_PPP_REG,
 401         HCLGE_OPC_DFX_RCB_REG,
 402         HCLGE_OPC_DFX_TQP_REG,
 403         HCLGE_OPC_DFX_SSU_REG_2
 404 };
 405
 406 static const struct key_info meta_data_key_info[] = {
 407         { PACKET_TYPE_ID, 6 },
 408         { IP_FRAGEMENT, 1 },
 409         { ROCE_TYPE, 1 },
 410         { NEXT_KEY, 5 },
 411         { VLAN_NUMBER, 2 },
 412         { SRC_VPORT, 12 },
 413         { DST_VPORT, 12 },
 414         { TUNNEL_PACKET, 1 },
 415 };
 416
 417 static const struct key_info tuple_key_info[] = {
 418         { OUTER_DST_MAC, 48, KEY_OPT_MAC, -1, -1 },
 419         { OUTER_SRC_MAC, 48, KEY_OPT_MAC, -1, -1 },
 420         { OUTER_VLAN_TAG_FST, 16, KEY_OPT_LE16, -1, -1 },
 421         { OUTER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 },
 422         { OUTER_ETH_TYPE, 16, KEY_OPT_LE16, -1, -1 },
 423         { OUTER_L2_RSV, 16, KEY_OPT_LE16, -1, -1 },
 424         { OUTER_IP_TOS, 8, KEY_OPT_U8, -1, -1 },
 425         { OUTER_IP_PROTO, 8, KEY_OPT_U8, -1, -1 },
 426         { OUTER_SRC_IP, 32, KEY_OPT_IP, -1, -1 },
 427         { OUTER_DST_IP, 32, KEY_OPT_IP, -1, -1 },
 428         { OUTER_L3_RSV, 16, KEY_OPT_LE16, -1, -1 },
 429         { OUTER_SRC_PORT, 16, KEY_OPT_LE16, -1, -1 },
 430         { OUTER_DST_PORT, 16, KEY_OPT_LE16, -1, -1 },
 431         { OUTER_L4_RSV, 32, KEY_OPT_LE32, -1, -1 },
 432         { OUTER_TUN_VNI, 24, KEY_OPT_VNI, -1, -1 },
 433         { OUTER_TUN_FLOW_ID, 8, KEY_OPT_U8, -1, -1 },
 434         { INNER_DST_MAC, 48, KEY_OPT_MAC,
 435           offsetof(struct hclge_fd_rule, tuples.dst_mac),
 436           offsetof(struct hclge_fd_rule, tuples_mask.dst_mac) },
 437         { INNER_SRC_MAC, 48, KEY_OPT_MAC,
 438           offsetof(struct hclge_fd_rule, tuples.src_mac),
 439           offsetof(struct hclge_fd_rule, tuples_mask.src_mac) },
 440         { INNER_VLAN_TAG_FST, 16, KEY_OPT_LE16,
 441           offsetof(struct hclge_fd_rule, tuples.vlan_tag1),
 442           offsetof(struct hclge_fd_rule, tuples_mask.vlan_tag1) },
 443         { INNER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 },
 444         { INNER_ETH_TYPE, 16, KEY_OPT_LE16,
 445           offsetof(struct hclge_fd_rule, tuples.ether_proto),
 446           offsetof(struct hclge_fd_rule, tuples_mask.ether_proto) },
 447         { INNER_L2_RSV, 16, KEY_OPT_LE16,
 448           offsetof(struct hclge_fd_rule, tuples.l2_user_def),
 449           offsetof(struct hclge_fd_rule, tuples_mask.l2_user_def) },
 450         { INNER_IP_TOS, 8, KEY_OPT_U8,
 451           offsetof(struct hclge_fd_rule, tuples.ip_tos),
 452           offsetof(struct hclge_fd_rule, tuples_mask.ip_tos) },
 453         { INNER_IP_PROTO, 8, KEY_OPT_U8,
 454           offsetof(struct hclge_fd_rule, tuples.ip_proto),
 455           offsetof(struct hclge_fd_rule, tuples_mask.ip_proto) },
 456         { INNER_SRC_IP, 32, KEY_OPT_IP,
 457           offsetof(struct hclge_fd_rule, tuples.src_ip),
 458           offsetof(struct hclge_fd_rule, tuples_mask.src_ip) },
 459         { INNER_DST_IP, 32, KEY_OPT_IP,
 460           offsetof(struct hclge_fd_rule, tuples.dst_ip),
 461           offsetof(struct hclge_fd_rule, tuples_mask.dst_ip) },
 462         { INNER_L3_RSV, 16, KEY_OPT_LE16,
 463           offsetof(struct hclge_fd_rule, tuples.l3_user_def),
 464           offsetof(struct hclge_fd_rule, tuples_mask.l3_user_def) },
 465         { INNER_SRC_PORT, 16, KEY_OPT_LE16,
 466           offsetof(struct hclge_fd_rule, tuples.src_port),
 467           offsetof(struct hclge_fd_rule, tuples_mask.src_port) },
 468         { INNER_DST_PORT, 16, KEY_OPT_LE16,
 469           offsetof(struct hclge_fd_rule, tuples.dst_port),
 470           offsetof(struct hclge_fd_rule, tuples_mask.dst_port) },
 471         { INNER_L4_RSV, 32, KEY_OPT_LE32,
 472           offsetof(struct hclge_fd_rule, tuples.l4_user_def),
 473           offsetof(struct hclge_fd_rule, tuples_mask.l4_user_def) },
 474 };
 475
 476 /**
 477  * hclge_cmd_send - send command to command queue
 478  * @hw: pointer to the hw struct
 479  * @desc: prefilled descriptor for describing the command
 480  * @num : the number of descriptors to be sent
 481  *
 482  * This is the main send command for command queue, it
 483  * sends the queue, cleans the queue, etc
 484  **/
 485 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num)
 486 {
 487         return hclge_comm_cmd_send(&hw->hw, desc, num);
 488 }
 489
 490 static int hclge_mac_update_stats_defective(struct hclge_dev *hdev)
 491 {
 492 #define HCLGE_MAC_CMD_NUM 21
 493
 494         u64 *data = (u64 *)(&hdev->mac_stats);
 495         struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
 496         __le64 *desc_data;
 497         u32 data_size;
 498         int ret;
 499         u32 i;
 500
 501         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
 502         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
 503         if (ret) {
 504                 dev_err(&hdev->pdev->dev,
 505                         "Get MAC pkt stats fail, status = %d.\n", ret);
 506
 507                 return ret;
 508         }
 509
 510         /* The first desc has a 64-bit header, so data size need to minus 1 */
 511         data_size = sizeof(desc) / (sizeof(u64)) - 1;
 512
 513         desc_data = (__le64 *)(&desc[0].data[0]);
 514         for (i = 0; i < data_size; i++) {
 515                 /* data memory is continuous becase only the first desc has a
 516                  * header in this command
 517                  */
 518                 *data += le64_to_cpu(*desc_data);
 519                 data++;
 520                 desc_data++;
 521         }
 522
 523         return 0;
 524 }
 525
 526 static int hclge_mac_update_stats_complete(struct hclge_dev *hdev)
 527 {
 528 #define HCLGE_REG_NUM_PER_DESC          4
 529
 530         u32 reg_num = hdev->ae_dev->dev_specs.mac_stats_num;
 531         u64 *data = (u64 *)(&hdev->mac_stats);
 532         struct hclge_desc *desc;
 533         __le64 *desc_data;
 534         u32 data_size;
 535         u32 desc_num;
 536         int ret;
 537         u32 i;
 538
 539         /* The first desc has a 64-bit header, so need to consider it */
 540         desc_num = reg_num / HCLGE_REG_NUM_PER_DESC + 1;
 541
 542         /* This may be called inside atomic sections,
 543          * so GFP_ATOMIC is more suitalbe here
 544          */
 545         desc = kcalloc(desc_num, sizeof(struct hclge_desc), GFP_ATOMIC);
 546         if (!desc)
 547                 return -ENOMEM;
 548
 549         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC_ALL, true);
 550         ret = hclge_cmd_send(&hdev->hw, desc, desc_num);
 551         if (ret) {
 552                 kfree(desc);
 553                 return ret;
 554         }
 555
 556         data_size = min_t(u32, sizeof(hdev->mac_stats) / sizeof(u64), reg_num);
 557
 558         desc_data = (__le64 *)(&desc[0].data[0]);
 559         for (i = 0; i < data_size; i++) {
 560                 /* data memory is continuous becase only the first desc has a
 561                  * header in this command
 562                  */
 563                 *data += le64_to_cpu(*desc_data);
 564                 data++;
 565                 desc_data++;
 566         }
 567
 568         kfree(desc);
 569
 570         return 0;
 571 }
 572
 573 static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *reg_num)
 574 {
 575         struct hclge_desc desc;
 576         int ret;
 577
 578         /* Driver needs total register number of both valid registers and
 579          * reserved registers, but the old firmware only returns number
 580          * of valid registers in device V2. To be compatible with these
 581          * devices, driver uses a fixed value.
 582          */
 583         if (hdev->ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) {
 584                 *reg_num = HCLGE_MAC_STATS_MAX_NUM_V1;
 585                 return 0;
 586         }
 587
 588         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_REG_NUM, true);
 589         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 590         if (ret) {
 591                 dev_err(&hdev->pdev->dev,
 592                         "failed to query mac statistic reg number, ret = %d\n",
 593                         ret);
 594                 return ret;
 595         }
 596
 597         *reg_num = le32_to_cpu(desc.data[0]);
 598         if (*reg_num == 0) {
 599                 dev_err(&hdev->pdev->dev,
 600                         "mac statistic reg number is invalid!\n");
 601                 return -ENODATA;
 602         }
 603
 604         return 0;
 605 }
 606
 607 int hclge_mac_update_stats(struct hclge_dev *hdev)
 608 {
 609         /* The firmware supports the new statistics acquisition method */
 610         if (hdev->ae_dev->dev_specs.mac_stats_num)
 611                 return hclge_mac_update_stats_complete(hdev);
 612         else
 613                 return hclge_mac_update_stats_defective(hdev);
 614 }
 615
 616 static int hclge_comm_get_count(struct hclge_dev *hdev,
 617                                 const struct hclge_comm_stats_str strs[],
 618                                 u32 size)
 619 {
 620         int count = 0;
 621         u32 i;
 622
 623         for (i = 0; i < size; i++)
 624                 if (strs[i].stats_num <= hdev->ae_dev->dev_specs.mac_stats_num)
 625                         count++;
 626
 627         return count;
 628 }
 629
 630 static u64 *hclge_comm_get_stats(struct hclge_dev *hdev,
 631                                  const struct hclge_comm_stats_str strs[],
 632                                  int size, u64 *data)
 633 {
 634         u64 *buf = data;
 635         u32 i;
 636
 637         for (i = 0; i < size; i++) {
 638                 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num)
 639                         continue;
 640
 641                 *buf = HCLGE_STATS_READ(&hdev->mac_stats, strs[i].offset);
 642                 buf++;
 643         }
 644
 645         return buf;
 646 }
 647
 648 static u8 *hclge_comm_get_strings(struct hclge_dev *hdev, u32 stringset,
 649                                   const struct hclge_comm_stats_str strs[],
 650                                   int size, u8 *data)
 651 {
 652         char *buff = (char *)data;
 653         u32 i;
 654
 655         if (stringset != ETH_SS_STATS)
 656                 return buff;
 657
 658         for (i = 0; i < size; i++) {
 659                 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num)
 660                         continue;
 661
 662                 snprintf(buff, ETH_GSTRING_LEN, "%s", strs[i].desc);
 663                 buff = buff + ETH_GSTRING_LEN;
 664         }
 665
 666         return (u8 *)buff;
 667 }
 668
 669 static void hclge_update_stats_for_all(struct hclge_dev *hdev)
 670 {
 671         struct hnae3_handle *handle;
 672         int status;
 673
 674         handle = &hdev->vport[0].nic;
 675         if (handle->client) {
 676                 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw);
 677                 if (status) {
 678                         dev_err(&hdev->pdev->dev,
 679                                 "Update TQPS stats fail, status = %d.\n",
 680                                 status);
 681                 }
 682         }
 683
 684         hclge_update_fec_stats(hdev);
 685
 686         status = hclge_mac_update_stats(hdev);
 687         if (status)
 688                 dev_err(&hdev->pdev->dev,
 689                         "Update MAC stats fail, status = %d.\n", status);
 690 }
 691
 692 static void hclge_update_stats(struct hnae3_handle *handle,
 693                                struct net_device_stats *net_stats)
 694 {
 695         struct hclge_vport *vport = hclge_get_vport(handle);
 696         struct hclge_dev *hdev = vport->back;
 697         int status;
 698
 699         if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
 700                 return;
 701
 702         status = hclge_mac_update_stats(hdev);
 703         if (status)
 704                 dev_err(&hdev->pdev->dev,
 705                         "Update MAC stats fail, status = %d.\n",
 706                         status);
 707
 708         status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw);
 709         if (status)
 710                 dev_err(&hdev->pdev->dev,
 711                         "Update TQPS stats fail, status = %d.\n",
 712                         status);
 713
 714         clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
 715 }
 716
 717 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
 718 {
 719 #define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK | \
 720                 HNAE3_SUPPORT_PHY_LOOPBACK | \
 721                 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK | \
 722                 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK | \
 723                 HNAE3_SUPPORT_EXTERNAL_LOOPBACK)
 724
 725         struct hclge_vport *vport = hclge_get_vport(handle);
 726         struct hclge_dev *hdev = vport->back;
 727         int count = 0;
 728
 729         /* Loopback test support rules:
 730          * mac: only GE mode support
 731          * serdes: all mac mode will support include GE/XGE/LGE/CGE
 732          * phy: only support when phy device exist on board
 733          */
 734         if (stringset == ETH_SS_TEST) {
 735                 /* clear loopback bit flags at first */
 736                 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
 737                 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 ||
 738                     hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
 739                     hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
 740                     hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
 741                         count += 1;
 742                         handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK;
 743                 }
 744
 745                 count += 1;
 746                 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK;
 747                 count += 1;
 748                 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK;
 749                 count += 1;
 750                 handle->flags |= HNAE3_SUPPORT_EXTERNAL_LOOPBACK;
 751
 752                 if ((hdev->hw.mac.phydev && hdev->hw.mac.phydev->drv &&
 753                      hdev->hw.mac.phydev->drv->set_loopback) ||
 754                     hnae3_dev_phy_imp_supported(hdev)) {
 755                         count += 1;
 756                         handle->flags |= HNAE3_SUPPORT_PHY_LOOPBACK;
 757                 }
 758         } else if (stringset == ETH_SS_STATS) {
 759                 count = hclge_comm_get_count(hdev, g_mac_stats_string,
 760                                              ARRAY_SIZE(g_mac_stats_string)) +
 761                         hclge_comm_tqps_get_sset_count(handle);
 762         }
 763
 764         return count;
 765 }
 766
 767 static void hclge_get_strings(struct hnae3_handle *handle, u32 stringset,
 768                               u8 *data)
 769 {
 770         struct hclge_vport *vport = hclge_get_vport(handle);
 771         struct hclge_dev *hdev = vport->back;
 772         u8 *p = (char *)data;
 773         int size;
 774
 775         if (stringset == ETH_SS_STATS) {
 776                 size = ARRAY_SIZE(g_mac_stats_string);
 777                 p = hclge_comm_get_strings(hdev, stringset, g_mac_stats_string,
 778                                            size, p);
 779                 p = hclge_comm_tqps_get_strings(handle, p);
 780         } else if (stringset == ETH_SS_TEST) {
 781                 if (handle->flags & HNAE3_SUPPORT_EXTERNAL_LOOPBACK) {
 782                         memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_EXTERNAL],
 783                                ETH_GSTRING_LEN);
 784                         p += ETH_GSTRING_LEN;
 785                 }
 786                 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) {
 787                         memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_APP],
 788                                ETH_GSTRING_LEN);
 789                         p += ETH_GSTRING_LEN;
 790                 }
 791                 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) {
 792                         memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES],
 793                                ETH_GSTRING_LEN);
 794                         p += ETH_GSTRING_LEN;
 795                 }
 796                 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) {
 797                         memcpy(p,
 798                                hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES],
 799                                ETH_GSTRING_LEN);
 800                         p += ETH_GSTRING_LEN;
 801                 }
 802                 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
 803                         memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_PHY],
 804                                ETH_GSTRING_LEN);
 805                         p += ETH_GSTRING_LEN;
 806                 }
 807         }
 808 }
 809
 810 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
 811 {
 812         struct hclge_vport *vport = hclge_get_vport(handle);
 813         struct hclge_dev *hdev = vport->back;
 814         u64 *p;
 815
 816         p = hclge_comm_get_stats(hdev, g_mac_stats_string,
 817                                  ARRAY_SIZE(g_mac_stats_string), data);
 818         p = hclge_comm_tqps_get_stats(handle, p);
 819 }
 820
 821 static void hclge_get_mac_stat(struct hnae3_handle *handle,
 822                                struct hns3_mac_stats *mac_stats)
 823 {
 824         struct hclge_vport *vport = hclge_get_vport(handle);
 825         struct hclge_dev *hdev = vport->back;
 826
 827         hclge_update_stats(handle, NULL);
 828
 829         mac_stats->tx_pause_cnt = hdev->mac_stats.mac_tx_mac_pause_num;
 830         mac_stats->rx_pause_cnt = hdev->mac_stats.mac_rx_mac_pause_num;
 831 }
 832
 833 static int hclge_parse_func_status(struct hclge_dev *hdev,
 834                                    struct hclge_func_status_cmd *status)
 835 {
 836 #define HCLGE_MAC_ID_MASK       0xF
 837
 838         if (!(status->pf_state & HCLGE_PF_STATE_DONE))
 839                 return -EINVAL;
 840
 841         /* Set the pf to main pf */
 842         if (status->pf_state & HCLGE_PF_STATE_MAIN)
 843                 hdev->flag |= HCLGE_FLAG_MAIN;
 844         else
 845                 hdev->flag &= ~HCLGE_FLAG_MAIN;
 846
 847         hdev->hw.mac.mac_id = status->mac_id & HCLGE_MAC_ID_MASK;
 848         return 0;
 849 }
 850
 851 static int hclge_query_function_status(struct hclge_dev *hdev)
 852 {
 853 #define HCLGE_QUERY_MAX_CNT     5
 854
 855         struct hclge_func_status_cmd *req;
 856         struct hclge_desc desc;
 857         int timeout = 0;
 858         int ret;
 859
 860         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
 861         req = (struct hclge_func_status_cmd *)desc.data;
 862
 863         do {
 864                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 865                 if (ret) {
 866                         dev_err(&hdev->pdev->dev,
 867                                 "query function status failed %d.\n", ret);
 868                         return ret;
 869                 }
 870
 871                 /* Check pf reset is done */
 872                 if (req->pf_state)
 873                         break;
 874                 usleep_range(1000, 2000);
 875         } while (timeout++ < HCLGE_QUERY_MAX_CNT);
 876
 877         return hclge_parse_func_status(hdev, req);
 878 }
 879
 880 static int hclge_query_pf_resource(struct hclge_dev *hdev)
 881 {
 882         struct hclge_pf_res_cmd *req;
 883         struct hclge_desc desc;
 884         int ret;
 885
 886         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
 887         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 888         if (ret) {
 889                 dev_err(&hdev->pdev->dev,
 890                         "query pf resource failed %d.\n", ret);
 891                 return ret;
 892         }
 893
 894         req = (struct hclge_pf_res_cmd *)desc.data;
 895         hdev->num_tqps = le16_to_cpu(req->tqp_num) +
 896                          le16_to_cpu(req->ext_tqp_num);
 897         hdev->pkt_buf_size = le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
 898
 899         if (req->tx_buf_size)
 900                 hdev->tx_buf_size =
 901                         le16_to_cpu(req->tx_buf_size) << HCLGE_BUF_UNIT_S;
 902         else
 903                 hdev->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
 904
 905         hdev->tx_buf_size = roundup(hdev->tx_buf_size, HCLGE_BUF_SIZE_UNIT);
 906
 907         if (req->dv_buf_size)
 908                 hdev->dv_buf_size =
 909                         le16_to_cpu(req->dv_buf_size) << HCLGE_BUF_UNIT_S;
 910         else
 911                 hdev->dv_buf_size = HCLGE_DEFAULT_DV;
 912
 913         hdev->dv_buf_size = roundup(hdev->dv_buf_size, HCLGE_BUF_SIZE_UNIT);
 914
 915         hdev->num_nic_msi = le16_to_cpu(req->msixcap_localid_number_nic);
 916         if (hdev->num_nic_msi < HNAE3_MIN_VECTOR_NUM) {
 917                 dev_err(&hdev->pdev->dev,
 918                         "only %u msi resources available, not enough for pf(min:2).\n",
 919                         hdev->num_nic_msi);
 920                 return -EINVAL;
 921         }
 922
 923         if (hnae3_dev_roce_supported(hdev)) {
 924                 hdev->num_roce_msi =
 925                         le16_to_cpu(req->pf_intr_vector_number_roce);
 926
 927                 /* PF should have NIC vectors and Roce vectors,
 928                  * NIC vectors are queued before Roce vectors.
 929                  */
 930                 hdev->num_msi = hdev->num_nic_msi + hdev->num_roce_msi;
 931         } else {
 932                 hdev->num_msi = hdev->num_nic_msi;
 933         }
 934
 935         return 0;
 936 }
 937
 938 static int hclge_parse_speed(u8 speed_cmd, u32 *speed)
 939 {
 940         switch (speed_cmd) {
 941         case HCLGE_FW_MAC_SPEED_10M:
 942                 *speed = HCLGE_MAC_SPEED_10M;
 943                 break;
 944         case HCLGE_FW_MAC_SPEED_100M:
 945                 *speed = HCLGE_MAC_SPEED_100M;
 946                 break;
 947         case HCLGE_FW_MAC_SPEED_1G:
 948                 *speed = HCLGE_MAC_SPEED_1G;
 949                 break;
 950         case HCLGE_FW_MAC_SPEED_10G:
 951                 *speed = HCLGE_MAC_SPEED_10G;
 952                 break;
 953         case HCLGE_FW_MAC_SPEED_25G:
 954                 *speed = HCLGE_MAC_SPEED_25G;
 955                 break;
 956         case HCLGE_FW_MAC_SPEED_40G:
 957                 *speed = HCLGE_MAC_SPEED_40G;
 958                 break;
 959         case HCLGE_FW_MAC_SPEED_50G:
 960                 *speed = HCLGE_MAC_SPEED_50G;
 961                 break;
 962         case HCLGE_FW_MAC_SPEED_100G:
 963                 *speed = HCLGE_MAC_SPEED_100G;
 964                 break;
 965         case HCLGE_FW_MAC_SPEED_200G:
 966                 *speed = HCLGE_MAC_SPEED_200G;
 967                 break;
 968         default:
 969                 return -EINVAL;
 970         }
 971
 972         return 0;
 973 }
 974
 975 static const struct hclge_speed_bit_map speed_bit_map[] = {
 976         {HCLGE_MAC_SPEED_10M, HCLGE_SUPPORT_10M_BIT},
 977         {HCLGE_MAC_SPEED_100M, HCLGE_SUPPORT_100M_BIT},
 978         {HCLGE_MAC_SPEED_1G, HCLGE_SUPPORT_1G_BIT},
 979         {HCLGE_MAC_SPEED_10G, HCLGE_SUPPORT_10G_BIT},
 980         {HCLGE_MAC_SPEED_25G, HCLGE_SUPPORT_25G_BIT},
 981         {HCLGE_MAC_SPEED_40G, HCLGE_SUPPORT_40G_BIT},
 982         {HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BIT},
 983         {HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BIT},
 984         {HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BIT},
 985 };
 986
 987 static int hclge_get_speed_bit(u32 speed, u32 *speed_bit)
 988 {
 989         u16 i;
 990
 991         for (i = 0; i < ARRAY_SIZE(speed_bit_map); i++) {
 992                 if (speed == speed_bit_map[i].speed) {
 993                         *speed_bit = speed_bit_map[i].speed_bit;
 994                         return 0;
 995                 }
 996         }
 997
 998         return -EINVAL;
 999 }
1000
1001 static int hclge_check_port_speed(struct hnae3_handle *handle, u32 speed)
1002 {
1003         struct hclge_vport *vport = hclge_get_vport(handle);
1004         struct hclge_dev *hdev = vport->back;
1005         u32 speed_ability = hdev->hw.mac.speed_ability;
1006         u32 speed_bit = 0;
1007         int ret;
1008
1009         ret = hclge_get_speed_bit(speed, &speed_bit);
1010         if (ret)
1011                 return ret;
1012
1013         if (speed_bit & speed_ability)
1014                 return 0;
1015
1016         return -EINVAL;
1017 }
1018
1019 static void hclge_update_fec_support(struct hclge_mac *mac)
1020 {
1021         linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, mac->supported);
1022         linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mac->supported);
1023         linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, mac->supported);
1024         linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported);
1025
1026         if (mac->fec_ability & BIT(HNAE3_FEC_BASER))
1027                 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
1028                                  mac->supported);
1029         if (mac->fec_ability & BIT(HNAE3_FEC_RS))
1030                 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
1031                                  mac->supported);
1032         if (mac->fec_ability & BIT(HNAE3_FEC_LLRS))
1033                 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
1034                                  mac->supported);
1035         if (mac->fec_ability & BIT(HNAE3_FEC_NONE))
1036                 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
1037                                  mac->supported);
1038 }
1039
1040 static void hclge_convert_setting_sr(u16 speed_ability,
1041                                      unsigned long *link_mode)
1042 {
1043         if (speed_ability & HCLGE_SUPPORT_10G_BIT)
1044                 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
1045                                  link_mode);
1046         if (speed_ability & HCLGE_SUPPORT_25G_BIT)
1047                 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
1048                                  link_mode);
1049         if (speed_ability & HCLGE_SUPPORT_40G_BIT)
1050                 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
1051                                  link_mode);
1052         if (speed_ability & HCLGE_SUPPORT_50G_BIT)
1053                 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
1054                                  link_mode);
1055         if (speed_ability & HCLGE_SUPPORT_100G_BIT)
1056                 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
1057                                  link_mode);
1058         if (speed_ability & HCLGE_SUPPORT_200G_BIT)
1059                 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
1060                                  link_mode);
1061 }
1062
1063 static void hclge_convert_setting_lr(u16 speed_ability,
1064                                      unsigned long *link_mode)
1065 {
1066         if (speed_ability & HCLGE_SUPPORT_10G_BIT)
1067                 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
1068                                  link_mode);
1069         if (speed_ability & HCLGE_SUPPORT_25G_BIT)
1070                 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
1071                                  link_mode);
1072         if (speed_ability & HCLGE_SUPPORT_50G_BIT)
1073                 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
1074                                  link_mode);
1075         if (speed_ability & HCLGE_SUPPORT_40G_BIT)
1076                 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
1077                                  link_mode);
1078         if (speed_ability & HCLGE_SUPPORT_100G_BIT)
1079                 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
1080                                  link_mode);
1081         if (speed_ability & HCLGE_SUPPORT_200G_BIT)
1082                 linkmode_set_bit(
1083                         ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
1084                         link_mode);
1085 }
1086
1087 static void hclge_convert_setting_cr(u16 speed_ability,
1088                                      unsigned long *link_mode)
1089 {
1090         if (speed_ability & HCLGE_SUPPORT_10G_BIT)
1091                 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
1092                                  link_mode);
1093         if (speed_ability & HCLGE_SUPPORT_25G_BIT)
1094                 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
1095                                  link_mode);
1096         if (speed_ability & HCLGE_SUPPORT_40G_BIT)
1097                 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
1098                                  link_mode);
1099         if (speed_ability & HCLGE_SUPPORT_50G_BIT)
1100                 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
1101                                  link_mode);
1102         if (speed_ability & HCLGE_SUPPORT_100G_BIT)
1103                 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
1104                                  link_mode);
1105         if (speed_ability & HCLGE_SUPPORT_200G_BIT)
1106                 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT,
1107                                  link_mode);
1108 }
1109
1110 static void hclge_convert_setting_kr(u16 speed_ability,
1111                                      unsigned long *link_mode)
1112 {
1113         if (speed_ability & HCLGE_SUPPORT_1G_BIT)
1114                 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
1115                                  link_mode);
1116         if (speed_ability & HCLGE_SUPPORT_10G_BIT)
1117                 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
1118                                  link_mode);
1119         if (speed_ability & HCLGE_SUPPORT_25G_BIT)
1120                 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
1121                                  link_mode);
1122         if (speed_ability & HCLGE_SUPPORT_40G_BIT)
1123                 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
1124                                  link_mode);
1125         if (speed_ability & HCLGE_SUPPORT_50G_BIT)
1126                 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
1127                                  link_mode);
1128         if (speed_ability & HCLGE_SUPPORT_100G_BIT)
1129                 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
1130                                  link_mode);
1131         if (speed_ability & HCLGE_SUPPORT_200G_BIT)
1132                 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
1133                                  link_mode);
1134 }
1135
1136 static void hclge_convert_setting_fec(struct hclge_mac *mac)
1137 {
1138         /* If firmware has reported fec_ability, don't need to convert by speed */
1139         if (mac->fec_ability)
1140                 goto out;
1141
1142         switch (mac->speed) {
1143         case HCLGE_MAC_SPEED_10G:
1144         case HCLGE_MAC_SPEED_40G:
1145                 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_AUTO) |
1146                                    BIT(HNAE3_FEC_NONE);
1147                 break;
1148         case HCLGE_MAC_SPEED_25G:
1149         case HCLGE_MAC_SPEED_50G:
1150                 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_RS) |
1151                                    BIT(HNAE3_FEC_AUTO) | BIT(HNAE3_FEC_NONE);
1152                 break;
1153         case HCLGE_MAC_SPEED_100G:
1154                 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) |
1155                                    BIT(HNAE3_FEC_NONE);
1156                 break;
1157         case HCLGE_MAC_SPEED_200G:
1158                 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) |
1159                                    BIT(HNAE3_FEC_LLRS);
1160                 break;
1161         default:
1162                 mac->fec_ability = 0;
1163                 break;
1164         }
1165
1166 out:
1167         hclge_update_fec_support(mac);
1168 }
1169
1170 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
1171                                         u16 speed_ability)
1172 {
1173         struct hclge_mac *mac = &hdev->hw.mac;
1174
1175         if (speed_ability & HCLGE_SUPPORT_1G_BIT)
1176                 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
1177                                  mac->supported);
1178
1179         hclge_convert_setting_sr(speed_ability, mac->supported);
1180         hclge_convert_setting_lr(speed_ability, mac->supported);
1181         hclge_convert_setting_cr(speed_ability, mac->supported);
1182         if (hnae3_dev_fec_supported(hdev))
1183                 hclge_convert_setting_fec(mac);
1184
1185         if (hnae3_dev_pause_supported(hdev))
1186                 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported);
1187
1188         linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mac->supported);
1189         linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported);
1190 }
1191
1192 static void hclge_parse_backplane_link_mode(struct hclge_dev *hdev,
1193                                             u16 speed_ability)
1194 {
1195         struct hclge_mac *mac = &hdev->hw.mac;
1196
1197         hclge_convert_setting_kr(speed_ability, mac->supported);
1198         if (hnae3_dev_fec_supported(hdev))
1199                 hclge_convert_setting_fec(mac);
1200
1201         if (hnae3_dev_pause_supported(hdev))
1202                 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported);
1203
1204         linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mac->supported);
1205         linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported);
1206 }
1207
1208 static void hclge_parse_copper_link_mode(struct hclge_dev *hdev,
1209                                          u16 speed_ability)
1210 {
1211         unsigned long *supported = hdev->hw.mac.supported;
1212
1213         /* default to support all speed for GE port */
1214         if (!speed_ability)
1215                 speed_ability = HCLGE_SUPPORT_GE;
1216
1217         if (speed_ability & HCLGE_SUPPORT_1G_BIT)
1218                 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1219                                  supported);
1220
1221         if (speed_ability & HCLGE_SUPPORT_100M_BIT) {
1222                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
1223                                  supported);
1224                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
1225                                  supported);
1226         }
1227
1228         if (speed_ability & HCLGE_SUPPORT_10M_BIT) {
1229                 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, supported);
1230                 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, supported);
1231         }
1232
1233         if (hnae3_dev_pause_supported(hdev)) {
1234                 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
1235                 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported);
1236         }
1237
1238         linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported);
1239         linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported);
1240 }
1241
1242 static void hclge_parse_link_mode(struct hclge_dev *hdev, u16 speed_ability)
1243 {
1244         u8 media_type = hdev->hw.mac.media_type;
1245
1246         if (media_type == HNAE3_MEDIA_TYPE_FIBER)
1247                 hclge_parse_fiber_link_mode(hdev, speed_ability);
1248         else if (media_type == HNAE3_MEDIA_TYPE_COPPER)
1249                 hclge_parse_copper_link_mode(hdev, speed_ability);
1250         else if (media_type == HNAE3_MEDIA_TYPE_BACKPLANE)
1251                 hclge_parse_backplane_link_mode(hdev, speed_ability);
1252 }
1253
1254 static u32 hclge_get_max_speed(u16 speed_ability)
1255 {
1256         if (speed_ability & HCLGE_SUPPORT_200G_BIT)
1257                 return HCLGE_MAC_SPEED_200G;
1258
1259         if (speed_ability & HCLGE_SUPPORT_100G_BIT)
1260                 return HCLGE_MAC_SPEED_100G;
1261
1262         if (speed_ability & HCLGE_SUPPORT_50G_BIT)
1263                 return HCLGE_MAC_SPEED_50G;
1264
1265         if (speed_ability & HCLGE_SUPPORT_40G_BIT)
1266                 return HCLGE_MAC_SPEED_40G;
1267
1268         if (speed_ability & HCLGE_SUPPORT_25G_BIT)
1269                 return HCLGE_MAC_SPEED_25G;
1270
1271         if (speed_ability & HCLGE_SUPPORT_10G_BIT)
1272                 return HCLGE_MAC_SPEED_10G;
1273
1274         if (speed_ability & HCLGE_SUPPORT_1G_BIT)
1275                 return HCLGE_MAC_SPEED_1G;
1276
1277         if (speed_ability & HCLGE_SUPPORT_100M_BIT)
1278                 return HCLGE_MAC_SPEED_100M;
1279
1280         if (speed_ability & HCLGE_SUPPORT_10M_BIT)
1281                 return HCLGE_MAC_SPEED_10M;
1282
1283         return HCLGE_MAC_SPEED_1G;
1284 }
1285
1286 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
1287 {
1288 #define HCLGE_TX_SPARE_SIZE_UNIT                4096
1289 #define SPEED_ABILITY_EXT_SHIFT                 8
1290
1291         struct hclge_cfg_param_cmd *req;
1292         u64 mac_addr_tmp_high;
1293         u16 speed_ability_ext;
1294         u64 mac_addr_tmp;
1295         unsigned int i;
1296
1297         req = (struct hclge_cfg_param_cmd *)desc[0].data;
1298
1299         /* get the configuration */
1300         cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1301                                       HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
1302         cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1303                                             HCLGE_CFG_TQP_DESC_N_M,
1304                                             HCLGE_CFG_TQP_DESC_N_S);
1305
1306         cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]),
1307                                         HCLGE_CFG_PHY_ADDR_M,
1308                                         HCLGE_CFG_PHY_ADDR_S);
1309         cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]),
1310                                           HCLGE_CFG_MEDIA_TP_M,
1311                                           HCLGE_CFG_MEDIA_TP_S);
1312         cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]),
1313                                           HCLGE_CFG_RX_BUF_LEN_M,
1314                                           HCLGE_CFG_RX_BUF_LEN_S);
1315         /* get mac_address */
1316         mac_addr_tmp = __le32_to_cpu(req->param[2]);
1317         mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]),
1318                                             HCLGE_CFG_MAC_ADDR_H_M,
1319                                             HCLGE_CFG_MAC_ADDR_H_S);
1320
1321         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
1322
1323         cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]),
1324                                              HCLGE_CFG_DEFAULT_SPEED_M,
1325                                              HCLGE_CFG_DEFAULT_SPEED_S);
1326         cfg->vf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]),
1327                                                HCLGE_CFG_RSS_SIZE_M,
1328                                                HCLGE_CFG_RSS_SIZE_S);
1329
1330         for (i = 0; i < ETH_ALEN; i++)
1331                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
1332
1333         req = (struct hclge_cfg_param_cmd *)desc[1].data;
1334         cfg->numa_node_map = __le32_to_cpu(req->param[0]);
1335
1336         cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]),
1337                                              HCLGE_CFG_SPEED_ABILITY_M,
1338                                              HCLGE_CFG_SPEED_ABILITY_S);
1339         speed_ability_ext = hnae3_get_field(__le32_to_cpu(req->param[1]),
1340                                             HCLGE_CFG_SPEED_ABILITY_EXT_M,
1341                                             HCLGE_CFG_SPEED_ABILITY_EXT_S);
1342         cfg->speed_ability |= speed_ability_ext << SPEED_ABILITY_EXT_SHIFT;
1343
1344         cfg->vlan_fliter_cap = hnae3_get_field(__le32_to_cpu(req->param[1]),
1345                                                HCLGE_CFG_VLAN_FLTR_CAP_M,
1346                                                HCLGE_CFG_VLAN_FLTR_CAP_S);
1347
1348         cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]),
1349                                          HCLGE_CFG_UMV_TBL_SPACE_M,
1350                                          HCLGE_CFG_UMV_TBL_SPACE_S);
1351
1352         cfg->pf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[2]),
1353                                                HCLGE_CFG_PF_RSS_SIZE_M,
1354                                                HCLGE_CFG_PF_RSS_SIZE_S);
1355
1356         /* HCLGE_CFG_PF_RSS_SIZE_M is the PF max rss size, which is a
1357          * power of 2, instead of reading out directly. This would
1358          * be more flexible for future changes and expansions.
1359          * When VF max  rss size field is HCLGE_CFG_RSS_SIZE_S,
1360          * it does not make sense if PF's field is 0. In this case, PF and VF
1361          * has the same max rss size filed: HCLGE_CFG_RSS_SIZE_S.
1362          */
1363         cfg->pf_rss_size_max = cfg->pf_rss_size_max ?
1364                                1U << cfg->pf_rss_size_max :
1365                                cfg->vf_rss_size_max;
1366
1367         /* The unit of the tx spare buffer size queried from configuration
1368          * file is HCLGE_TX_SPARE_SIZE_UNIT(4096) bytes, so a conversion is
1369          * needed here.
1370          */
1371         cfg->tx_spare_buf_size = hnae3_get_field(__le32_to_cpu(req->param[2]),
1372                                                  HCLGE_CFG_TX_SPARE_BUF_SIZE_M,
1373                                                  HCLGE_CFG_TX_SPARE_BUF_SIZE_S);
1374         cfg->tx_spare_buf_size *= HCLGE_TX_SPARE_SIZE_UNIT;
1375 }
1376
1377 /* hclge_get_cfg: query the static parameter from flash
1378  * @hdev: pointer to struct hclge_dev
1379  * @hcfg: the config structure to be getted
1380  */
1381 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
1382 {
1383         struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
1384         struct hclge_cfg_param_cmd *req;
1385         unsigned int i;
1386         int ret;
1387
1388         for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
1389                 u32 offset = 0;
1390
1391                 req = (struct hclge_cfg_param_cmd *)desc[i].data;
1392                 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
1393                                            true);
1394                 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M,
1395                                 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
1396                 /* Len should be united by 4 bytes when send to hardware */
1397                 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
1398                                 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
1399                 req->offset = cpu_to_le32(offset);
1400         }
1401
1402         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1403         if (ret) {
1404                 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret);
1405                 return ret;
1406         }
1407
1408         hclge_parse_cfg(hcfg, desc);
1409
1410         return 0;
1411 }
1412
1413 static void hclge_set_default_dev_specs(struct hclge_dev *hdev)
1414 {
1415 #define HCLGE_MAX_NON_TSO_BD_NUM                        8U
1416
1417         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
1418
1419         ae_dev->dev_specs.max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM;
1420         ae_dev->dev_specs.rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE;
1421         ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE;
1422         ae_dev->dev_specs.max_tm_rate = HCLGE_ETHER_MAX_RATE;
1423         ae_dev->dev_specs.max_int_gl = HCLGE_DEF_MAX_INT_GL;
1424         ae_dev->dev_specs.max_frm_size = HCLGE_MAC_MAX_FRAME;
1425         ae_dev->dev_specs.max_qset_num = HCLGE_MAX_QSET_NUM;
1426         ae_dev->dev_specs.umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF;
1427 }
1428
1429 static void hclge_parse_dev_specs(struct hclge_dev *hdev,
1430                                   struct hclge_desc *desc)
1431 {
1432         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
1433         struct hclge_dev_specs_0_cmd *req0;
1434         struct hclge_dev_specs_1_cmd *req1;
1435
1436         req0 = (struct hclge_dev_specs_0_cmd *)desc[0].data;
1437         req1 = (struct hclge_dev_specs_1_cmd *)desc[1].data;
1438
1439         ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num;
1440         ae_dev->dev_specs.rss_ind_tbl_size =
1441                 le16_to_cpu(req0->rss_ind_tbl_size);
1442         ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max);
1443         ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size);
1444         ae_dev->dev_specs.max_tm_rate = le32_to_cpu(req0->max_tm_rate);
1445         ae_dev->dev_specs.max_qset_num = le16_to_cpu(req1->max_qset_num);
1446         ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl);
1447         ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size);
1448         ae_dev->dev_specs.umv_size = le16_to_cpu(req1->umv_size);
1449         ae_dev->dev_specs.mc_mac_size = le16_to_cpu(req1->mc_mac_size);
1450 }
1451
1452 static void hclge_check_dev_specs(struct hclge_dev *hdev)
1453 {
1454         struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs;
1455
1456         if (!dev_specs->max_non_tso_bd_num)
1457                 dev_specs->max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM;
1458         if (!dev_specs->rss_ind_tbl_size)
1459                 dev_specs->rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE;
1460         if (!dev_specs->rss_key_size)
1461                 dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE;
1462         if (!dev_specs->max_tm_rate)
1463                 dev_specs->max_tm_rate = HCLGE_ETHER_MAX_RATE;
1464         if (!dev_specs->max_qset_num)
1465                 dev_specs->max_qset_num = HCLGE_MAX_QSET_NUM;
1466         if (!dev_specs->max_int_gl)
1467                 dev_specs->max_int_gl = HCLGE_DEF_MAX_INT_GL;
1468         if (!dev_specs->max_frm_size)
1469                 dev_specs->max_frm_size = HCLGE_MAC_MAX_FRAME;
1470         if (!dev_specs->umv_size)
1471                 dev_specs->umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF;
1472 }
1473
1474 static int hclge_query_mac_stats_num(struct hclge_dev *hdev)
1475 {
1476         u32 reg_num = 0;
1477         int ret;
1478
1479         ret = hclge_mac_query_reg_num(hdev, &reg_num);
1480         if (ret && ret != -EOPNOTSUPP)
1481                 return ret;
1482
1483         hdev->ae_dev->dev_specs.mac_stats_num = reg_num;
1484         return 0;
1485 }
1486
1487 static int hclge_query_dev_specs(struct hclge_dev *hdev)
1488 {
1489         struct hclge_desc desc[HCLGE_QUERY_DEV_SPECS_BD_NUM];
1490         int ret;
1491         int i;
1492
1493         ret = hclge_query_mac_stats_num(hdev);
1494         if (ret)
1495                 return ret;
1496
1497         /* set default specifications as devices lower than version V3 do not
1498          * support querying specifications from firmware.
1499          */
1500         if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) {
1501                 hclge_set_default_dev_specs(hdev);
1502                 return 0;
1503         }
1504
1505         for (i = 0; i < HCLGE_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1506                 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS,
1507                                            true);
1508                 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
1509         }
1510         hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true);
1511
1512         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_QUERY_DEV_SPECS_BD_NUM);
1513         if (ret)
1514                 return ret;
1515
1516         hclge_parse_dev_specs(hdev, desc);
1517         hclge_check_dev_specs(hdev);
1518
1519         return 0;
1520 }
1521
1522 static int hclge_get_cap(struct hclge_dev *hdev)
1523 {
1524         int ret;
1525
1526         ret = hclge_query_function_status(hdev);
1527         if (ret) {
1528                 dev_err(&hdev->pdev->dev,
1529                         "query function status error %d.\n", ret);
1530                 return ret;
1531         }
1532
1533         /* get pf resource */
1534         return hclge_query_pf_resource(hdev);
1535 }
1536
1537 static void hclge_init_kdump_kernel_config(struct hclge_dev *hdev)
1538 {
1539 #define HCLGE_MIN_TX_DESC       64
1540 #define HCLGE_MIN_RX_DESC       64
1541
1542         if (!is_kdump_kernel())
1543                 return;
1544
1545         dev_info(&hdev->pdev->dev,
1546                  "Running kdump kernel. Using minimal resources\n");
1547
1548         /* minimal queue pairs equals to the number of vports */
1549         hdev->num_tqps = hdev->num_req_vfs + 1;
1550         hdev->num_tx_desc = HCLGE_MIN_TX_DESC;
1551         hdev->num_rx_desc = HCLGE_MIN_RX_DESC;
1552 }
1553
1554 static void hclge_init_tc_config(struct hclge_dev *hdev)
1555 {
1556         unsigned int i;
1557
1558         if (hdev->tc_max > HNAE3_MAX_TC ||
1559             hdev->tc_max < 1) {
1560                 dev_warn(&hdev->pdev->dev, "TC num = %u.\n",
1561                          hdev->tc_max);
1562                 hdev->tc_max = 1;
1563         }
1564
1565         /* Dev does not support DCB */
1566         if (!hnae3_dev_dcb_supported(hdev)) {
1567                 hdev->tc_max = 1;
1568                 hdev->pfc_max = 0;
1569         } else {
1570                 hdev->pfc_max = hdev->tc_max;
1571         }
1572
1573         hdev->tm_info.num_tc = 1;
1574
1575         /* Currently not support uncontiuous tc */
1576         for (i = 0; i < hdev->tm_info.num_tc; i++)
1577                 hnae3_set_bit(hdev->hw_tc_map, i, 1);
1578
1579         hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
1580 }
1581
1582 static int hclge_configure(struct hclge_dev *hdev)
1583 {
1584         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
1585         struct hclge_cfg cfg;
1586         int ret;
1587
1588         ret = hclge_get_cfg(hdev, &cfg);
1589         if (ret)
1590                 return ret;
1591
1592         hdev->base_tqp_pid = 0;
1593         hdev->vf_rss_size_max = cfg.vf_rss_size_max;
1594         hdev->pf_rss_size_max = cfg.pf_rss_size_max;
1595         hdev->rx_buf_len = cfg.rx_buf_len;
1596         ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
1597         hdev->hw.mac.media_type = cfg.media_type;
1598         hdev->hw.mac.phy_addr = cfg.phy_addr;
1599         hdev->num_tx_desc = cfg.tqp_desc_num;
1600         hdev->num_rx_desc = cfg.tqp_desc_num;
1601         hdev->tm_info.num_pg = 1;
1602         hdev->tc_max = cfg.tc_num;
1603         hdev->tm_info.hw_pfc_map = 0;
1604         if (cfg.umv_space)
1605                 hdev->wanted_umv_size = cfg.umv_space;
1606         else
1607                 hdev->wanted_umv_size = hdev->ae_dev->dev_specs.umv_size;
1608         hdev->tx_spare_buf_size = cfg.tx_spare_buf_size;
1609         hdev->gro_en = true;
1610         if (cfg.vlan_fliter_cap == HCLGE_VLAN_FLTR_CAN_MDF)
1611                 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps);
1612
1613         if (hnae3_ae_dev_fd_supported(hdev->ae_dev)) {
1614                 hdev->fd_en = true;
1615                 hdev->fd_active_type = HCLGE_FD_RULE_NONE;
1616         }
1617
1618         ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1619         if (ret) {
1620                 dev_err(&hdev->pdev->dev, "failed to parse speed %u, ret = %d\n",
1621                         cfg.default_speed, ret);
1622                 return ret;
1623         }
1624
1625         hclge_parse_link_mode(hdev, cfg.speed_ability);
1626
1627         hdev->hw.mac.max_speed = hclge_get_max_speed(cfg.speed_ability);
1628
1629         hclge_init_tc_config(hdev);
1630         hclge_init_kdump_kernel_config(hdev);
1631
1632         return ret;
1633 }
1634
1635 static int hclge_config_tso(struct hclge_dev *hdev, u16 tso_mss_min,
1636                             u16 tso_mss_max)
1637 {
1638         struct hclge_cfg_tso_status_cmd *req;
1639         struct hclge_desc desc;
1640
1641         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1642
1643         req = (struct hclge_cfg_tso_status_cmd *)desc.data;
1644         req->tso_mss_min = cpu_to_le16(tso_mss_min);
1645         req->tso_mss_max = cpu_to_le16(tso_mss_max);
1646
1647         return hclge_cmd_send(&hdev->hw, &desc, 1);
1648 }
1649
1650 static int hclge_config_gro(struct hclge_dev *hdev)
1651 {
1652         struct hclge_cfg_gro_status_cmd *req;
1653         struct hclge_desc desc;
1654         int ret;
1655
1656         if (!hnae3_ae_dev_gro_supported(hdev->ae_dev))
1657                 return 0;
1658
1659         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, false);
1660         req = (struct hclge_cfg_gro_status_cmd *)desc.data;
1661
1662         req->gro_en = hdev->gro_en ? 1 : 0;
1663
1664         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1665         if (ret)
1666                 dev_err(&hdev->pdev->dev,
1667                         "GRO hardware config cmd failed, ret = %d\n", ret);
1668
1669         return ret;
1670 }
1671
1672 static int hclge_alloc_tqps(struct hclge_dev *hdev)
1673 {
1674         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
1675         struct hclge_comm_tqp *tqp;
1676         int i;
1677
1678         hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1679                                   sizeof(struct hclge_comm_tqp), GFP_KERNEL);
1680         if (!hdev->htqp)
1681                 return -ENOMEM;
1682
1683         tqp = hdev->htqp;
1684
1685         for (i = 0; i < hdev->num_tqps; i++) {
1686                 tqp->dev = &hdev->pdev->dev;
1687                 tqp->index = i;
1688
1689                 tqp->q.ae_algo = &ae_algo;
1690                 tqp->q.buf_size = hdev->rx_buf_len;
1691                 tqp->q.tx_desc_num = hdev->num_tx_desc;
1692                 tqp->q.rx_desc_num = hdev->num_rx_desc;
1693
1694                 /* need an extended offset to configure queues >=
1695                  * HCLGE_TQP_MAX_SIZE_DEV_V2
1696                  */
1697                 if (i < HCLGE_TQP_MAX_SIZE_DEV_V2)
1698                         tqp->q.io_base = hdev->hw.hw.io_base +
1699                                          HCLGE_TQP_REG_OFFSET +
1700                                          i * HCLGE_TQP_REG_SIZE;
1701                 else
1702                         tqp->q.io_base = hdev->hw.hw.io_base +
1703                                          HCLGE_TQP_REG_OFFSET +
1704                                          HCLGE_TQP_EXT_REG_OFFSET +
1705                                          (i - HCLGE_TQP_MAX_SIZE_DEV_V2) *
1706                                          HCLGE_TQP_REG_SIZE;
1707
1708                 /* when device supports tx push and has device memory,
1709                  * the queue can execute push mode or doorbell mode on
1710                  * device memory.
1711                  */
1712                 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps))
1713                         tqp->q.mem_base = hdev->hw.hw.mem_base +
1714                                           HCLGE_TQP_MEM_OFFSET(hdev, i);
1715
1716                 tqp++;
1717         }
1718
1719         return 0;
1720 }
1721
1722 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1723                                   u16 tqp_pid, u16 tqp_vid, bool is_pf)
1724 {
1725         struct hclge_tqp_map_cmd *req;
1726         struct hclge_desc desc;
1727         int ret;
1728
1729         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1730
1731         req = (struct hclge_tqp_map_cmd *)desc.data;
1732         req->tqp_id = cpu_to_le16(tqp_pid);
1733         req->tqp_vf = func_id;
1734         req->tqp_flag = 1U << HCLGE_TQP_MAP_EN_B;
1735         if (!is_pf)
1736                 req->tqp_flag |= 1U << HCLGE_TQP_MAP_TYPE_B;
1737         req->tqp_vid = cpu_to_le16(tqp_vid);
1738
1739         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1740         if (ret)
1741                 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret);
1742
1743         return ret;
1744 }
1745
1746 static int  hclge_assign_tqp(struct hclge_vport *vport, u16 num_tqps)
1747 {
1748         struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
1749         struct hclge_dev *hdev = vport->back;
1750         int i, alloced;
1751
1752         for (i = 0, alloced = 0; i < hdev->num_tqps &&
1753              alloced < num_tqps; i++) {
1754                 if (!hdev->htqp[i].alloced) {
1755                         hdev->htqp[i].q.handle = &vport->nic;
1756                         hdev->htqp[i].q.tqp_index = alloced;
1757                         hdev->htqp[i].q.tx_desc_num = kinfo->num_tx_desc;
1758                         hdev->htqp[i].q.rx_desc_num = kinfo->num_rx_desc;
1759                         kinfo->tqp[alloced] = &hdev->htqp[i].q;
1760                         hdev->htqp[i].alloced = true;
1761                         alloced++;
1762                 }
1763         }
1764         vport->alloc_tqps = alloced;
1765         kinfo->rss_size = min_t(u16, hdev->pf_rss_size_max,
1766                                 vport->alloc_tqps / hdev->tm_info.num_tc);
1767
1768         /* ensure one to one mapping between irq and queue at default */
1769         kinfo->rss_size = min_t(u16, kinfo->rss_size,
1770                                 (hdev->num_nic_msi - 1) / hdev->tm_info.num_tc);
1771
1772         return 0;
1773 }
1774
1775 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps,
1776                             u16 num_tx_desc, u16 num_rx_desc)
1777
1778 {
1779         struct hnae3_handle *nic = &vport->nic;
1780         struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1781         struct hclge_dev *hdev = vport->back;
1782         int ret;
1783
1784         kinfo->num_tx_desc = num_tx_desc;
1785         kinfo->num_rx_desc = num_rx_desc;
1786
1787         kinfo->rx_buf_len = hdev->rx_buf_len;
1788         kinfo->tx_spare_buf_size = hdev->tx_spare_buf_size;
1789
1790         kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, num_tqps,
1791                                   sizeof(struct hnae3_queue *), GFP_KERNEL);
1792         if (!kinfo->tqp)
1793                 return -ENOMEM;
1794
1795         ret = hclge_assign_tqp(vport, num_tqps);
1796         if (ret)
1797                 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1798
1799         return ret;
1800 }
1801
1802 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1803                                   struct hclge_vport *vport)
1804 {
1805         struct hnae3_handle *nic = &vport->nic;
1806         struct hnae3_knic_private_info *kinfo;
1807         u16 i;
1808
1809         kinfo = &nic->kinfo;
1810         for (i = 0; i < vport->alloc_tqps; i++) {
1811                 struct hclge_comm_tqp *q =
1812                         container_of(kinfo->tqp[i], struct hclge_comm_tqp, q);
1813                 bool is_pf;
1814                 int ret;
1815
1816                 is_pf = !(vport->vport_id);
1817                 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1818                                              i, is_pf);
1819                 if (ret)
1820                         return ret;
1821         }
1822
1823         return 0;
1824 }
1825
1826 static int hclge_map_tqp(struct hclge_dev *hdev)
1827 {
1828         struct hclge_vport *vport = hdev->vport;
1829         u16 i, num_vport;
1830
1831         num_vport = hdev->num_req_vfs + 1;
1832         for (i = 0; i < num_vport; i++) {
1833                 int ret;
1834
1835                 ret = hclge_map_tqp_to_vport(hdev, vport);
1836                 if (ret)
1837                         return ret;
1838
1839                 vport++;
1840         }
1841
1842         return 0;
1843 }
1844
1845 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1846 {
1847         struct hnae3_handle *nic = &vport->nic;
1848         struct hclge_dev *hdev = vport->back;
1849         int ret;
1850
1851         nic->pdev = hdev->pdev;
1852         nic->ae_algo = &ae_algo;
1853         nic->numa_node_mask = hdev->numa_node_mask;
1854         nic->kinfo.io_base = hdev->hw.hw.io_base;
1855
1856         ret = hclge_knic_setup(vport, num_tqps,
1857                                hdev->num_tx_desc, hdev->num_rx_desc);
1858         if (ret)
1859                 dev_err(&hdev->pdev->dev, "knic setup failed %d\n", ret);
1860
1861         return ret;
1862 }
1863
1864 static int hclge_alloc_vport(struct hclge_dev *hdev)
1865 {
1866         struct pci_dev *pdev = hdev->pdev;
1867         struct hclge_vport *vport;
1868         u32 tqp_main_vport;
1869         u32 tqp_per_vport;
1870         int num_vport, i;
1871         int ret;
1872
1873         /* We need to alloc a vport for main NIC of PF */
1874         num_vport = hdev->num_req_vfs + 1;
1875
1876         if (hdev->num_tqps < num_vport) {
1877                 dev_err(&hdev->pdev->dev, "tqps(%u) is less than vports(%d)",
1878                         hdev->num_tqps, num_vport);
1879                 return -EINVAL;
1880         }
1881
1882         /* Alloc the same number of TQPs for every vport */
1883         tqp_per_vport = hdev->num_tqps / num_vport;
1884         tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1885
1886         vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1887                              GFP_KERNEL);
1888         if (!vport)
1889                 return -ENOMEM;
1890
1891         hdev->vport = vport;
1892         hdev->num_alloc_vport = num_vport;
1893
1894         if (IS_ENABLED(CONFIG_PCI_IOV))
1895                 hdev->num_alloc_vfs = hdev->num_req_vfs;
1896
1897         for (i = 0; i < num_vport; i++) {
1898                 vport->back = hdev;
1899                 vport->vport_id = i;
1900                 vport->vf_info.link_state = IFLA_VF_LINK_STATE_AUTO;
1901                 vport->mps = HCLGE_MAC_DEFAULT_FRAME;
1902                 vport->port_base_vlan_cfg.state = HNAE3_PORT_BASE_VLAN_DISABLE;
1903                 vport->port_base_vlan_cfg.tbl_sta = true;
1904                 vport->rxvlan_cfg.rx_vlan_offload_en = true;
1905                 vport->req_vlan_fltr_en = true;
1906                 INIT_LIST_HEAD(&vport->vlan_list);
1907                 INIT_LIST_HEAD(&vport->uc_mac_list);
1908                 INIT_LIST_HEAD(&vport->mc_mac_list);
1909                 spin_lock_init(&vport->mac_list_lock);
1910
1911                 if (i == 0)
1912                         ret = hclge_vport_setup(vport, tqp_main_vport);
1913                 else
1914                         ret = hclge_vport_setup(vport, tqp_per_vport);
1915                 if (ret) {
1916                         dev_err(&pdev->dev,
1917                                 "vport setup failed for vport %d, %d\n",
1918                                 i, ret);
1919                         return ret;
1920                 }
1921
1922                 vport++;
1923         }
1924
1925         return 0;
1926 }
1927
1928 static int  hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1929                                     struct hclge_pkt_buf_alloc *buf_alloc)
1930 {
1931 /* TX buffer size is unit by 128 byte */
1932 #define HCLGE_BUF_SIZE_UNIT_SHIFT       7
1933 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK    BIT(15)
1934         struct hclge_tx_buff_alloc_cmd *req;
1935         struct hclge_desc desc;
1936         int ret;
1937         u8 i;
1938
1939         req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
1940
1941         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
1942         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1943                 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
1944
1945                 req->tx_pkt_buff[i] =
1946                         cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1947                                      HCLGE_BUF_SIZE_UPDATE_EN_MSK);
1948         }
1949
1950         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1951         if (ret)
1952                 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1953                         ret);
1954
1955         return ret;
1956 }
1957
1958 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1959                                  struct hclge_pkt_buf_alloc *buf_alloc)
1960 {
1961         int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
1962
1963         if (ret)
1964                 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret);
1965
1966         return ret;
1967 }
1968
1969 static u32 hclge_get_tc_num(struct hclge_dev *hdev)
1970 {
1971         unsigned int i;
1972         u32 cnt = 0;
1973
1974         for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1975                 if (hdev->hw_tc_map & BIT(i))
1976                         cnt++;
1977         return cnt;
1978 }
1979
1980 /* Get the number of pfc enabled TCs, which have private buffer */
1981 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1982                                   struct hclge_pkt_buf_alloc *buf_alloc)
1983 {
1984         struct hclge_priv_buf *priv;
1985         unsigned int i;
1986         int cnt = 0;
1987
1988         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1989                 priv = &buf_alloc->priv_buf[i];
1990                 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1991                     priv->enable)
1992                         cnt++;
1993         }
1994
1995         return cnt;
1996 }
1997
1998 /* Get the number of pfc disabled TCs, which have private buffer */
1999 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
2000                                      struct hclge_pkt_buf_alloc *buf_alloc)
2001 {
2002         struct hclge_priv_buf *priv;
2003         unsigned int i;
2004         int cnt = 0;
2005
2006         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2007                 priv = &buf_alloc->priv_buf[i];
2008                 if (hdev->hw_tc_map & BIT(i) &&
2009                     !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
2010                     priv->enable)
2011                         cnt++;
2012         }
2013
2014         return cnt;
2015 }
2016
2017 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
2018 {
2019         struct hclge_priv_buf *priv;
2020         u32 rx_priv = 0;
2021         int i;
2022
2023         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2024                 priv = &buf_alloc->priv_buf[i];
2025                 if (priv->enable)
2026                         rx_priv += priv->buf_size;
2027         }
2028         return rx_priv;
2029 }
2030
2031 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
2032 {
2033         u32 i, total_tx_size = 0;
2034
2035         for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
2036                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
2037
2038         return total_tx_size;
2039 }
2040
2041 static bool  hclge_is_rx_buf_ok(struct hclge_dev *hdev,
2042                                 struct hclge_pkt_buf_alloc *buf_alloc,
2043                                 u32 rx_all)
2044 {
2045         u32 shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
2046         u32 tc_num = hclge_get_tc_num(hdev);
2047         u32 shared_buf, aligned_mps;
2048         u32 rx_priv;
2049         int i;
2050
2051         aligned_mps = roundup(hdev->mps, HCLGE_BUF_SIZE_UNIT);
2052
2053         if (hnae3_dev_dcb_supported(hdev))
2054                 shared_buf_min = HCLGE_BUF_MUL_BY * aligned_mps +
2055                                         hdev->dv_buf_size;
2056         else
2057                 shared_buf_min = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF
2058                                         + hdev->dv_buf_size;
2059
2060         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
2061         shared_std = roundup(max_t(u32, shared_buf_min, shared_buf_tc),
2062                              HCLGE_BUF_SIZE_UNIT);
2063
2064         rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
2065         if (rx_all < rx_priv + shared_std)
2066                 return false;
2067
2068         shared_buf = rounddown(rx_all - rx_priv, HCLGE_BUF_SIZE_UNIT);
2069         buf_alloc->s_buf.buf_size = shared_buf;
2070         if (hnae3_dev_dcb_supported(hdev)) {
2071                 buf_alloc->s_buf.self.high = shared_buf - hdev->dv_buf_size;
2072                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
2073                         - roundup(aligned_mps / HCLGE_BUF_DIV_BY,
2074                                   HCLGE_BUF_SIZE_UNIT);
2075         } else {
2076                 buf_alloc->s_buf.self.high = aligned_mps +
2077                                                 HCLGE_NON_DCB_ADDITIONAL_BUF;
2078                 buf_alloc->s_buf.self.low = aligned_mps;
2079         }
2080
2081         if (hnae3_dev_dcb_supported(hdev)) {
2082                 hi_thrd = shared_buf - hdev->dv_buf_size;
2083
2084                 if (tc_num <= NEED_RESERVE_TC_NUM)
2085                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
2086                                         / BUF_MAX_PERCENT;
2087
2088                 if (tc_num)
2089                         hi_thrd = hi_thrd / tc_num;
2090
2091                 hi_thrd = max_t(u32, hi_thrd, HCLGE_BUF_MUL_BY * aligned_mps);
2092                 hi_thrd = rounddown(hi_thrd, HCLGE_BUF_SIZE_UNIT);
2093                 lo_thrd = hi_thrd - aligned_mps / HCLGE_BUF_DIV_BY;
2094         } else {
2095                 hi_thrd = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF;
2096                 lo_thrd = aligned_mps;
2097         }
2098
2099         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2100                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
2101                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
2102         }
2103
2104         return true;
2105 }
2106
2107 static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
2108                                 struct hclge_pkt_buf_alloc *buf_alloc)
2109 {
2110         u32 i, total_size;
2111
2112         total_size = hdev->pkt_buf_size;
2113
2114         /* alloc tx buffer for all enabled tc */
2115         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2116                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
2117
2118                 if (hdev->hw_tc_map & BIT(i)) {
2119                         if (total_size < hdev->tx_buf_size)
2120                                 return -ENOMEM;
2121
2122                         priv->tx_buf_size = hdev->tx_buf_size;
2123                 } else {
2124                         priv->tx_buf_size = 0;
2125                 }
2126
2127                 total_size -= priv->tx_buf_size;
2128         }
2129
2130         return 0;
2131 }
2132
2133 static bool hclge_rx_buf_calc_all(struct hclge_dev *hdev, bool max,
2134                                   struct hclge_pkt_buf_alloc *buf_alloc)
2135 {
2136         u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc);
2137         u32 aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT);
2138         unsigned int i;
2139
2140         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2141                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
2142
2143                 priv->enable = 0;
2144                 priv->wl.low = 0;
2145                 priv->wl.high = 0;
2146                 priv->buf_size = 0;
2147
2148                 if (!(hdev->hw_tc_map & BIT(i)))
2149                         continue;
2150
2151                 priv->enable = 1;
2152
2153                 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
2154                         priv->wl.low = max ? aligned_mps : HCLGE_BUF_SIZE_UNIT;
2155                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
2156                                                 HCLGE_BUF_SIZE_UNIT);
2157                 } else {
2158                         priv->wl.low = 0;
2159                         priv->wl.high = max ? (aligned_mps * HCLGE_BUF_MUL_BY) :
2160                                         aligned_mps;
2161                 }
2162
2163                 priv->buf_size = priv->wl.high + hdev->dv_buf_size;
2164         }
2165
2166         return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all);
2167 }
2168
2169 static bool hclge_drop_nopfc_buf_till_fit(struct hclge_dev *hdev,
2170                                           struct hclge_pkt_buf_alloc *buf_alloc)
2171 {
2172         u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc);
2173         int no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
2174         int i;
2175
2176         /* let the last to be cleared first */
2177         for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
2178                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
2179                 unsigned int mask = BIT((unsigned int)i);
2180
2181                 if (hdev->hw_tc_map & mask &&
2182                     !(hdev->tm_info.hw_pfc_map & mask)) {
2183                         /* Clear the no pfc TC private buffer */
2184                         priv->wl.low = 0;
2185                         priv->wl.high = 0;
2186                         priv->buf_size = 0;
2187                         priv->enable = 0;
2188                         no_pfc_priv_num--;
2189                 }
2190
2191                 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
2192                     no_pfc_priv_num == 0)
2193                         break;
2194         }
2195
2196         return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all);
2197 }
2198
2199 static bool hclge_drop_pfc_buf_till_fit(struct hclge_dev *hdev,
2200                                         struct hclge_pkt_buf_alloc *buf_alloc)
2201 {
2202         u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc);
2203         int pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
2204         int i;
2205
2206         /* let the last to be cleared first */
2207         for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
2208                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
2209                 unsigned int mask = BIT((unsigned int)i);
2210
2211                 if (hdev->hw_tc_map & mask &&
2212                     hdev->tm_info.hw_pfc_map & mask) {
2213                         /* Reduce the number of pfc TC with private buffer */
2214                         priv->wl.low = 0;
2215                         priv->enable = 0;
2216                         priv->wl.high = 0;
2217                         priv->buf_size = 0;
2218                         pfc_priv_num--;
2219                 }
2220
2221                 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
2222                     pfc_priv_num == 0)
2223                         break;
2224         }
2225
2226         return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all);
2227 }
2228
2229 static int hclge_only_alloc_priv_buff(struct hclge_dev *hdev,
2230                                       struct hclge_pkt_buf_alloc *buf_alloc)
2231 {
2232 #define COMPENSATE_BUFFER       0x3C00
2233 #define COMPENSATE_HALF_MPS_NUM 5
2234 #define PRIV_WL_GAP             0x1800
2235
2236         u32 rx_priv = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc);
2237         u32 tc_num = hclge_get_tc_num(hdev);
2238         u32 half_mps = hdev->mps >> 1;
2239         u32 min_rx_priv;
2240         unsigned int i;
2241
2242         if (tc_num)
2243                 rx_priv = rx_priv / tc_num;
2244
2245         if (tc_num <= NEED_RESERVE_TC_NUM)
2246                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
2247
2248         min_rx_priv = hdev->dv_buf_size + COMPENSATE_BUFFER +
2249                         COMPENSATE_HALF_MPS_NUM * half_mps;
2250         min_rx_priv = round_up(min_rx_priv, HCLGE_BUF_SIZE_UNIT);
2251         rx_priv = round_down(rx_priv, HCLGE_BUF_SIZE_UNIT);
2252         if (rx_priv < min_rx_priv)
2253                 return false;
2254
2255         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2256                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
2257
2258                 priv->enable = 0;
2259                 priv->wl.low = 0;
2260                 priv->wl.high = 0;
2261                 priv->buf_size = 0;
2262
2263                 if (!(hdev->hw_tc_map & BIT(i)))
2264                         continue;
2265
2266                 priv->enable = 1;
2267                 priv->buf_size = rx_priv;
2268                 priv->wl.high = rx_priv - hdev->dv_buf_size;
2269                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
2270         }
2271
2272         buf_alloc->s_buf.buf_size = 0;
2273
2274         return true;
2275 }
2276
2277 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
2278  * @hdev: pointer to struct hclge_dev
2279  * @buf_alloc: pointer to buffer calculation data
2280  * @return: 0: calculate successful, negative: fail
2281  */
2282 static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
2283                                 struct hclge_pkt_buf_alloc *buf_alloc)
2284 {
2285         /* When DCB is not supported, rx private buffer is not allocated. */
2286         if (!hnae3_dev_dcb_supported(hdev)) {
2287                 u32 rx_all = hdev->pkt_buf_size;
2288
2289                 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
2290                 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
2291                         return -ENOMEM;
2292
2293                 return 0;
2294         }
2295
2296         if (hclge_only_alloc_priv_buff(hdev, buf_alloc))
2297                 return 0;
2298
2299         if (hclge_rx_buf_calc_all(hdev, true, buf_alloc))
2300                 return 0;
2301
2302         /* try to decrease the buffer size */
2303         if (hclge_rx_buf_calc_all(hdev, false, buf_alloc))
2304                 return 0;
2305
2306         if (hclge_drop_nopfc_buf_till_fit(hdev, buf_alloc))
2307                 return 0;
2308
2309         if (hclge_drop_pfc_buf_till_fit(hdev, buf_alloc))
2310                 return 0;
2311
2312         return -ENOMEM;
2313 }
2314
2315 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
2316                                    struct hclge_pkt_buf_alloc *buf_alloc)
2317 {
2318         struct hclge_rx_priv_buff_cmd *req;
2319         struct hclge_desc desc;
2320         int ret;
2321         int i;
2322
2323         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
2324         req = (struct hclge_rx_priv_buff_cmd *)desc.data;
2325
2326         /* Alloc private buffer TCs */
2327         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2328                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
2329
2330                 req->buf_num[i] =
2331                         cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
2332                 req->buf_num[i] |=
2333                         cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
2334         }
2335
2336         req->shared_buf =
2337                 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
2338                             (1 << HCLGE_TC0_PRI_BUF_EN_B));
2339
2340         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2341         if (ret)
2342                 dev_err(&hdev->pdev->dev,
2343                         "rx private buffer alloc cmd failed %d\n", ret);
2344
2345         return ret;
2346 }
2347
2348 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
2349                                    struct hclge_pkt_buf_alloc *buf_alloc)
2350 {
2351         struct hclge_rx_priv_wl_buf *req;
2352         struct hclge_priv_buf *priv;
2353         struct hclge_desc desc[2];
2354         int i, j;
2355         int ret;
2356
2357         for (i = 0; i < 2; i++) {
2358                 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
2359                                            false);
2360                 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
2361
2362                 /* The first descriptor set the NEXT bit to 1 */
2363                 if (i == 0)
2364                         desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2365                 else
2366                         desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2367
2368                 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
2369                         u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
2370
2371                         priv = &buf_alloc->priv_buf[idx];
2372                         req->tc_wl[j].high =
2373                                 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
2374                         req->tc_wl[j].high |=
2375                                 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
2376                         req->tc_wl[j].low =
2377                                 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
2378                         req->tc_wl[j].low |=
2379                                  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
2380                 }
2381         }
2382
2383         /* Send 2 descriptor at one time */
2384         ret = hclge_cmd_send(&hdev->hw, desc, 2);
2385         if (ret)
2386                 dev_err(&hdev->pdev->dev,
2387                         "rx private waterline config cmd failed %d\n",
2388                         ret);
2389         return ret;
2390 }
2391
2392 static int hclge_common_thrd_config(struct hclge_dev *hdev,
2393                                     struct hclge_pkt_buf_alloc *buf_alloc)
2394 {
2395         struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
2396         struct hclge_rx_com_thrd *req;
2397         struct hclge_desc desc[2];
2398         struct hclge_tc_thrd *tc;
2399         int i, j;
2400         int ret;
2401
2402         for (i = 0; i < 2; i++) {
2403                 hclge_cmd_setup_basic_desc(&desc[i],
2404                                            HCLGE_OPC_RX_COM_THRD_ALLOC, false);
2405                 req = (struct hclge_rx_com_thrd *)&desc[i].data;
2406
2407                 /* The first descriptor set the NEXT bit to 1 */
2408                 if (i == 0)
2409                         desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2410                 else
2411                         desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2412
2413                 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
2414                         tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
2415
2416                         req->com_thrd[j].high =
2417                                 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
2418                         req->com_thrd[j].high |=
2419                                  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
2420                         req->com_thrd[j].low =
2421                                 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
2422                         req->com_thrd[j].low |=
2423                                  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
2424                 }
2425         }
2426
2427         /* Send 2 descriptors at one time */
2428         ret = hclge_cmd_send(&hdev->hw, desc, 2);
2429         if (ret)
2430                 dev_err(&hdev->pdev->dev,
2431                         "common threshold config cmd failed %d\n", ret);
2432         return ret;
2433 }
2434
2435 static int hclge_common_wl_config(struct hclge_dev *hdev,
2436                                   struct hclge_pkt_buf_alloc *buf_alloc)
2437 {
2438         struct hclge_shared_buf *buf = &buf_alloc->s_buf;
2439         struct hclge_rx_com_wl *req;
2440         struct hclge_desc desc;
2441         int ret;
2442
2443         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
2444
2445         req = (struct hclge_rx_com_wl *)desc.data;
2446         req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
2447         req->com_wl.high |=  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
2448
2449         req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
2450         req->com_wl.low |=  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
2451
2452         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2453         if (ret)
2454                 dev_err(&hdev->pdev->dev,
2455                         "common waterline config cmd failed %d\n", ret);
2456
2457         return ret;
2458 }
2459
2460 int hclge_buffer_alloc(struct hclge_dev *hdev)
2461 {
2462         struct hclge_pkt_buf_alloc *pkt_buf;
2463         int ret;
2464
2465         pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
2466         if (!pkt_buf)
2467                 return -ENOMEM;
2468
2469         ret = hclge_tx_buffer_calc(hdev, pkt_buf);
2470         if (ret) {
2471                 dev_err(&hdev->pdev->dev,
2472                         "could not calc tx buffer size for all TCs %d\n", ret);
2473                 goto out;
2474         }
2475
2476         ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
2477         if (ret) {
2478                 dev_err(&hdev->pdev->dev,
2479                         "could not alloc tx buffers %d\n", ret);
2480                 goto out;
2481         }
2482
2483         ret = hclge_rx_buffer_calc(hdev, pkt_buf);
2484         if (ret) {
2485                 dev_err(&hdev->pdev->dev,
2486                         "could not calc rx priv buffer size for all TCs %d\n",
2487                         ret);
2488                 goto out;
2489         }
2490
2491         ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
2492         if (ret) {
2493                 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
2494                         ret);
2495                 goto out;
2496         }
2497
2498         if (hnae3_dev_dcb_supported(hdev)) {
2499                 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
2500                 if (ret) {
2501                         dev_err(&hdev->pdev->dev,
2502                                 "could not configure rx private waterline %d\n",
2503                                 ret);
2504                         goto out;
2505                 }
2506
2507                 ret = hclge_common_thrd_config(hdev, pkt_buf);
2508                 if (ret) {
2509                         dev_err(&hdev->pdev->dev,
2510                                 "could not configure common threshold %d\n",
2511                                 ret);
2512                         goto out;
2513                 }
2514         }
2515
2516         ret = hclge_common_wl_config(hdev, pkt_buf);
2517         if (ret)
2518                 dev_err(&hdev->pdev->dev,
2519                         "could not configure common waterline %d\n", ret);
2520
2521 out:
2522         kfree(pkt_buf);
2523         return ret;
2524 }
2525
2526 static int hclge_init_roce_base_info(struct hclge_vport *vport)
2527 {
2528         struct hnae3_handle *roce = &vport->roce;
2529         struct hnae3_handle *nic = &vport->nic;
2530         struct hclge_dev *hdev = vport->back;
2531
2532         roce->rinfo.num_vectors = vport->back->num_roce_msi;
2533
2534         if (hdev->num_msi < hdev->num_nic_msi + hdev->num_roce_msi)
2535                 return -EINVAL;
2536
2537         roce->rinfo.base_vector = hdev->num_nic_msi;
2538
2539         roce->rinfo.netdev = nic->kinfo.netdev;
2540         roce->rinfo.roce_io_base = hdev->hw.hw.io_base;
2541         roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base;
2542
2543         roce->pdev = nic->pdev;
2544         roce->ae_algo = nic->ae_algo;
2545         roce->numa_node_mask = nic->numa_node_mask;
2546
2547         return 0;
2548 }
2549
2550 static int hclge_init_msi(struct hclge_dev *hdev)
2551 {
2552         struct pci_dev *pdev = hdev->pdev;
2553         int vectors;
2554         int i;
2555
2556         vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM,
2557                                         hdev->num_msi,
2558                                         PCI_IRQ_MSI | PCI_IRQ_MSIX);
2559         if (vectors < 0) {
2560                 dev_err(&pdev->dev,
2561                         "failed(%d) to allocate MSI/MSI-X vectors\n",
2562                         vectors);
2563                 return vectors;
2564         }
2565         if (vectors < hdev->num_msi)
2566                 dev_warn(&hdev->pdev->dev,
2567                          "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2568                          hdev->num_msi, vectors);
2569
2570         hdev->num_msi = vectors;
2571         hdev->num_msi_left = vectors;
2572
2573         hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2574                                            sizeof(u16), GFP_KERNEL);
2575         if (!hdev->vector_status) {
2576                 pci_free_irq_vectors(pdev);
2577                 return -ENOMEM;
2578         }
2579
2580         for (i = 0; i < hdev->num_msi; i++)
2581                 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
2582
2583         hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2584                                         sizeof(int), GFP_KERNEL);
2585         if (!hdev->vector_irq) {
2586                 pci_free_irq_vectors(pdev);
2587                 return -ENOMEM;
2588         }
2589
2590         return 0;
2591 }
2592
2593 static u8 hclge_check_speed_dup(u8 duplex, int speed)
2594 {
2595         if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M))
2596                 duplex = HCLGE_MAC_FULL;
2597
2598         return duplex;
2599 }
2600
2601 static struct hclge_mac_speed_map hclge_mac_speed_map_to_fw[] = {
2602         {HCLGE_MAC_SPEED_10M, HCLGE_FW_MAC_SPEED_10M},
2603         {HCLGE_MAC_SPEED_100M, HCLGE_FW_MAC_SPEED_100M},
2604         {HCLGE_MAC_SPEED_1G, HCLGE_FW_MAC_SPEED_1G},
2605         {HCLGE_MAC_SPEED_10G, HCLGE_FW_MAC_SPEED_10G},
2606         {HCLGE_MAC_SPEED_25G, HCLGE_FW_MAC_SPEED_25G},
2607         {HCLGE_MAC_SPEED_40G, HCLGE_FW_MAC_SPEED_40G},
2608         {HCLGE_MAC_SPEED_50G, HCLGE_FW_MAC_SPEED_50G},
2609         {HCLGE_MAC_SPEED_100G, HCLGE_FW_MAC_SPEED_100G},
2610         {HCLGE_MAC_SPEED_200G, HCLGE_FW_MAC_SPEED_200G},
2611 };
2612
2613 static int hclge_convert_to_fw_speed(u32 speed_drv, u32 *speed_fw)
2614 {
2615         u16 i;
2616
2617         for (i = 0; i < ARRAY_SIZE(hclge_mac_speed_map_to_fw); i++) {
2618                 if (hclge_mac_speed_map_to_fw[i].speed_drv == speed_drv) {
2619                         *speed_fw = hclge_mac_speed_map_to_fw[i].speed_fw;
2620                         return 0;
2621                 }
2622         }
2623
2624         return -EINVAL;
2625 }
2626
2627 static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed,
2628                                       u8 duplex, u8 lane_num)
2629 {
2630         struct hclge_config_mac_speed_dup_cmd *req;
2631         struct hclge_desc desc;
2632         u32 speed_fw;
2633         int ret;
2634
2635         req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
2636
2637         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
2638
2639         if (duplex)
2640                 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, 1);
2641
2642         ret = hclge_convert_to_fw_speed(speed, &speed_fw);
2643         if (ret) {
2644                 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
2645                 return ret;
2646         }
2647
2648         hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, HCLGE_CFG_SPEED_S,
2649                         speed_fw);
2650         hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
2651                       1);
2652         req->lane_num = lane_num;
2653
2654         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2655         if (ret) {
2656                 dev_err(&hdev->pdev->dev,
2657                         "mac speed/duplex config cmd failed %d.\n", ret);
2658                 return ret;
2659         }
2660
2661         return 0;
2662 }
2663
2664 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex, u8 lane_num)
2665 {
2666         struct hclge_mac *mac = &hdev->hw.mac;
2667         int ret;
2668
2669         duplex = hclge_check_speed_dup(duplex, speed);
2670         if (!mac->support_autoneg && mac->speed == speed &&
2671             mac->duplex == duplex && (mac->lane_num == lane_num || lane_num == 0))
2672                 return 0;
2673
2674         ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex, lane_num);
2675         if (ret)
2676                 return ret;
2677
2678         hdev->hw.mac.speed = speed;
2679         hdev->hw.mac.duplex = duplex;
2680         if (!lane_num)
2681                 hdev->hw.mac.lane_num = lane_num;
2682
2683         return 0;
2684 }
2685
2686 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2687                                      u8 duplex, u8 lane_num)
2688 {
2689         struct hclge_vport *vport = hclge_get_vport(handle);
2690         struct hclge_dev *hdev = vport->back;
2691
2692         return hclge_cfg_mac_speed_dup(hdev, speed, duplex, lane_num);
2693 }
2694
2695 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2696 {
2697         struct hclge_config_auto_neg_cmd *req;
2698         struct hclge_desc desc;
2699         u32 flag = 0;
2700         int ret;
2701
2702         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2703
2704         req = (struct hclge_config_auto_neg_cmd *)desc.data;
2705         if (enable)
2706                 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, 1U);
2707         req->cfg_an_cmd_flag = cpu_to_le32(flag);
2708
2709         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2710         if (ret)
2711                 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2712                         ret);
2713
2714         return ret;
2715 }
2716
2717 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2718 {
2719         struct hclge_vport *vport = hclge_get_vport(handle);
2720         struct hclge_dev *hdev = vport->back;
2721
2722         if (!hdev->hw.mac.support_autoneg) {
2723                 if (enable) {
2724                         dev_err(&hdev->pdev->dev,
2725                                 "autoneg is not supported by current port\n");
2726                         return -EOPNOTSUPP;
2727                 } else {
2728                         return 0;
2729                 }
2730         }
2731
2732         return hclge_set_autoneg_en(hdev, enable);
2733 }
2734
2735 static int hclge_get_autoneg(struct hnae3_handle *handle)
2736 {
2737         struct hclge_vport *vport = hclge_get_vport(handle);
2738         struct hclge_dev *hdev = vport->back;
2739         struct phy_device *phydev = hdev->hw.mac.phydev;
2740
2741         if (phydev)
2742                 return phydev->autoneg;
2743
2744         return hdev->hw.mac.autoneg;
2745 }
2746
2747 static int hclge_restart_autoneg(struct hnae3_handle *handle)
2748 {
2749         struct hclge_vport *vport = hclge_get_vport(handle);
2750         struct hclge_dev *hdev = vport->back;
2751         int ret;
2752
2753         dev_dbg(&hdev->pdev->dev, "restart autoneg\n");
2754
2755         ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2756         if (ret)
2757                 return ret;
2758         return hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2759 }
2760
2761 static int hclge_halt_autoneg(struct hnae3_handle *handle, bool halt)
2762 {
2763         struct hclge_vport *vport = hclge_get_vport(handle);
2764         struct hclge_dev *hdev = vport->back;
2765
2766         if (hdev->hw.mac.support_autoneg && hdev->hw.mac.autoneg)
2767                 return hclge_set_autoneg_en(hdev, !halt);
2768
2769         return 0;
2770 }
2771
2772 static void hclge_parse_fec_stats_lanes(struct hclge_dev *hdev,
2773                                         struct hclge_desc *desc, u32 desc_len)
2774 {
2775         u32 lane_size = HCLGE_FEC_STATS_MAX_LANES * 2;
2776         u32 desc_index = 0;
2777         u32 data_index = 0;
2778         u32 i;
2779
2780         for (i = 0; i < lane_size; i++) {
2781                 if (data_index >= HCLGE_DESC_DATA_LEN) {
2782                         desc_index++;
2783                         data_index = 0;
2784                 }
2785
2786                 if (desc_index >= desc_len)
2787                         return;
2788
2789                 hdev->fec_stats.per_lanes[i] +=
2790                         le32_to_cpu(desc[desc_index].data[data_index]);
2791                 data_index++;
2792         }
2793 }
2794
2795 static void hclge_parse_fec_stats(struct hclge_dev *hdev,
2796                                   struct hclge_desc *desc, u32 desc_len)
2797 {
2798         struct hclge_query_fec_stats_cmd *req;
2799
2800         req = (struct hclge_query_fec_stats_cmd *)desc[0].data;
2801
2802         hdev->fec_stats.base_r_lane_num = req->base_r_lane_num;
2803         hdev->fec_stats.rs_corr_blocks +=
2804                 le32_to_cpu(req->rs_fec_corr_blocks);
2805         hdev->fec_stats.rs_uncorr_blocks +=
2806                 le32_to_cpu(req->rs_fec_uncorr_blocks);
2807         hdev->fec_stats.rs_error_blocks +=
2808                 le32_to_cpu(req->rs_fec_error_blocks);
2809         hdev->fec_stats.base_r_corr_blocks +=
2810                 le32_to_cpu(req->base_r_fec_corr_blocks);
2811         hdev->fec_stats.base_r_uncorr_blocks +=
2812                 le32_to_cpu(req->base_r_fec_uncorr_blocks);
2813
2814         hclge_parse_fec_stats_lanes(hdev, &desc[1], desc_len - 1);
2815 }
2816
2817 static int hclge_update_fec_stats_hw(struct hclge_dev *hdev)
2818 {
2819         struct hclge_desc desc[HCLGE_FEC_STATS_CMD_NUM];
2820         int ret;
2821         u32 i;
2822
2823         for (i = 0; i < HCLGE_FEC_STATS_CMD_NUM; i++) {
2824                 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_FEC_STATS,
2825                                            true);
2826                 if (i != (HCLGE_FEC_STATS_CMD_NUM - 1))
2827                         desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2828         }
2829
2830         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_FEC_STATS_CMD_NUM);
2831         if (ret)
2832                 return ret;
2833
2834         hclge_parse_fec_stats(hdev, desc, HCLGE_FEC_STATS_CMD_NUM);
2835
2836         return 0;
2837 }
2838
2839 static void hclge_update_fec_stats(struct hclge_dev *hdev)
2840 {
2841         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
2842         int ret;
2843
2844         if (!hnae3_ae_dev_fec_stats_supported(ae_dev) ||
2845             test_and_set_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state))
2846                 return;
2847
2848         ret = hclge_update_fec_stats_hw(hdev);
2849         if (ret)
2850                 dev_err(&hdev->pdev->dev,
2851                         "failed to update fec stats, ret = %d\n", ret);
2852
2853         clear_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state);
2854 }
2855
2856 static void hclge_get_fec_stats_total(struct hclge_dev *hdev,
2857                                       struct ethtool_fec_stats *fec_stats)
2858 {
2859         fec_stats->corrected_blocks.total = hdev->fec_stats.rs_corr_blocks;
2860         fec_stats->uncorrectable_blocks.total =
2861                 hdev->fec_stats.rs_uncorr_blocks;
2862 }
2863
2864 static void hclge_get_fec_stats_lanes(struct hclge_dev *hdev,
2865                                       struct ethtool_fec_stats *fec_stats)
2866 {
2867         u32 i;
2868
2869         if (hdev->fec_stats.base_r_lane_num == 0 ||
2870             hdev->fec_stats.base_r_lane_num > HCLGE_FEC_STATS_MAX_LANES) {
2871                 dev_err(&hdev->pdev->dev,
2872                         "fec stats lane number(%llu) is invalid\n",
2873                         hdev->fec_stats.base_r_lane_num);
2874                 return;
2875         }
2876
2877         for (i = 0; i < hdev->fec_stats.base_r_lane_num; i++) {
2878                 fec_stats->corrected_blocks.lanes[i] =
2879                         hdev->fec_stats.base_r_corr_per_lanes[i];
2880                 fec_stats->uncorrectable_blocks.lanes[i] =
2881                         hdev->fec_stats.base_r_uncorr_per_lanes[i];
2882         }
2883 }
2884
2885 static void hclge_comm_get_fec_stats(struct hclge_dev *hdev,
2886                                      struct ethtool_fec_stats *fec_stats)
2887 {
2888         u32 fec_mode = hdev->hw.mac.fec_mode;
2889
2890         switch (fec_mode) {
2891         case BIT(HNAE3_FEC_RS):
2892         case BIT(HNAE3_FEC_LLRS):
2893                 hclge_get_fec_stats_total(hdev, fec_stats);
2894                 break;
2895         case BIT(HNAE3_FEC_BASER):
2896                 hclge_get_fec_stats_lanes(hdev, fec_stats);
2897                 break;
2898         default:
2899                 dev_err(&hdev->pdev->dev,
2900                         "fec stats is not supported by current fec mode(0x%x)\n",
2901                         fec_mode);
2902                 break;
2903         }
2904 }
2905
2906 static void hclge_get_fec_stats(struct hnae3_handle *handle,
2907                                 struct ethtool_fec_stats *fec_stats)
2908 {
2909         struct hclge_vport *vport = hclge_get_vport(handle);
2910         struct hclge_dev *hdev = vport->back;
2911         u32 fec_mode = hdev->hw.mac.fec_mode;
2912
2913         if (fec_mode == BIT(HNAE3_FEC_NONE) ||
2914             fec_mode == BIT(HNAE3_FEC_AUTO) ||
2915             fec_mode == BIT(HNAE3_FEC_USER_DEF))
2916                 return;
2917
2918         hclge_update_fec_stats(hdev);
2919
2920         hclge_comm_get_fec_stats(hdev, fec_stats);
2921 }
2922
2923 static int hclge_set_fec_hw(struct hclge_dev *hdev, u32 fec_mode)
2924 {
2925         struct hclge_config_fec_cmd *req;
2926         struct hclge_desc desc;
2927         int ret;
2928
2929         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_FEC_MODE, false);
2930
2931         req = (struct hclge_config_fec_cmd *)desc.data;
2932         if (fec_mode & BIT(HNAE3_FEC_AUTO))
2933                 hnae3_set_bit(req->fec_mode, HCLGE_MAC_CFG_FEC_AUTO_EN_B, 1);
2934         if (fec_mode & BIT(HNAE3_FEC_RS))
2935                 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M,
2936                                 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_RS);
2937         if (fec_mode & BIT(HNAE3_FEC_LLRS))
2938                 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M,
2939                                 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_LLRS);
2940         if (fec_mode & BIT(HNAE3_FEC_BASER))
2941                 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M,
2942                                 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_BASER);
2943
2944         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2945         if (ret)
2946                 dev_err(&hdev->pdev->dev, "set fec mode failed %d.\n", ret);
2947
2948         return ret;
2949 }
2950
2951 static int hclge_set_fec(struct hnae3_handle *handle, u32 fec_mode)
2952 {
2953         struct hclge_vport *vport = hclge_get_vport(handle);
2954         struct hclge_dev *hdev = vport->back;
2955         struct hclge_mac *mac = &hdev->hw.mac;
2956         int ret;
2957
2958         if (fec_mode && !(mac->fec_ability & fec_mode)) {
2959                 dev_err(&hdev->pdev->dev, "unsupported fec mode\n");
2960                 return -EINVAL;
2961         }
2962
2963         ret = hclge_set_fec_hw(hdev, fec_mode);
2964         if (ret)
2965                 return ret;
2966
2967         mac->user_fec_mode = fec_mode | BIT(HNAE3_FEC_USER_DEF);
2968         return 0;
2969 }
2970
2971 static void hclge_get_fec(struct hnae3_handle *handle, u8 *fec_ability,
2972                           u8 *fec_mode)
2973 {
2974         struct hclge_vport *vport = hclge_get_vport(handle);
2975         struct hclge_dev *hdev = vport->back;
2976         struct hclge_mac *mac = &hdev->hw.mac;
2977
2978         if (fec_ability)
2979                 *fec_ability = mac->fec_ability;
2980         if (fec_mode)
2981                 *fec_mode = mac->fec_mode;
2982 }
2983
2984 static int hclge_mac_init(struct hclge_dev *hdev)
2985 {
2986         struct hclge_mac *mac = &hdev->hw.mac;
2987         int ret;
2988
2989         hdev->support_sfp_query = true;
2990         hdev->hw.mac.duplex = HCLGE_MAC_FULL;
2991         ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed,
2992                                          hdev->hw.mac.duplex, hdev->hw.mac.lane_num);
2993         if (ret)
2994                 return ret;
2995
2996         if (hdev->hw.mac.support_autoneg) {
2997                 ret = hclge_set_autoneg_en(hdev, hdev->hw.mac.autoneg);
2998                 if (ret)
2999                         return ret;
3000         }
3001
3002         mac->link = 0;
3003
3004         if (mac->user_fec_mode & BIT(HNAE3_FEC_USER_DEF)) {
3005                 ret = hclge_set_fec_hw(hdev, mac->user_fec_mode);
3006                 if (ret)
3007                         return ret;
3008         }
3009
3010         ret = hclge_set_mac_mtu(hdev, hdev->mps);
3011         if (ret) {
3012                 dev_err(&hdev->pdev->dev, "set mtu failed ret=%d\n", ret);
3013                 return ret;
3014         }
3015
3016         ret = hclge_set_default_loopback(hdev);
3017         if (ret)
3018                 return ret;
3019
3020         ret = hclge_buffer_alloc(hdev);
3021         if (ret)
3022                 dev_err(&hdev->pdev->dev,
3023                         "allocate buffer fail, ret=%d\n", ret);
3024
3025         return ret;
3026 }
3027
3028 static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
3029 {
3030         if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
3031             !test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) {
3032                 hdev->last_mbx_scheduled = jiffies;
3033                 mod_delayed_work(hclge_wq, &hdev->service_task, 0);
3034         }
3035 }
3036
3037 static void hclge_reset_task_schedule(struct hclge_dev *hdev)
3038 {
3039         if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
3040             test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state) &&
3041             !test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) {
3042                 hdev->last_rst_scheduled = jiffies;
3043                 mod_delayed_work(hclge_wq, &hdev->service_task, 0);
3044         }
3045 }
3046
3047 static void hclge_errhand_task_schedule(struct hclge_dev *hdev)
3048 {
3049         if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
3050             !test_and_set_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state))
3051                 mod_delayed_work(hclge_wq, &hdev->service_task, 0);
3052 }
3053
3054 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time)
3055 {
3056         if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
3057             !test_bit(HCLGE_STATE_RST_FAIL, &hdev->state))
3058                 mod_delayed_work(hclge_wq, &hdev->service_task, delay_time);
3059 }
3060
3061 static int hclge_get_mac_link_status(struct hclge_dev *hdev, int *link_status)
3062 {
3063         struct hclge_link_status_cmd *req;
3064         struct hclge_desc desc;
3065         int ret;
3066
3067         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
3068         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3069         if (ret) {
3070                 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
3071                         ret);
3072                 return ret;
3073         }
3074
3075         req = (struct hclge_link_status_cmd *)desc.data;
3076         *link_status = (req->status & HCLGE_LINK_STATUS_UP_M) > 0 ?
3077                 HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN;
3078
3079         return 0;
3080 }
3081
3082 static int hclge_get_mac_phy_link(struct hclge_dev *hdev, int *link_status)
3083 {
3084         struct phy_device *phydev = hdev->hw.mac.phydev;
3085
3086         *link_status = HCLGE_LINK_STATUS_DOWN;
3087
3088         if (test_bit(HCLGE_STATE_DOWN, &hdev->state))
3089                 return 0;
3090
3091         if (phydev && (phydev->state != PHY_RUNNING || !phydev->link))
3092                 return 0;
3093
3094         return hclge_get_mac_link_status(hdev, link_status);
3095 }
3096
3097 static void hclge_push_link_status(struct hclge_dev *hdev)
3098 {
3099         struct hclge_vport *vport;
3100         int ret;
3101         u16 i;
3102
3103         for (i = 0; i < pci_num_vf(hdev->pdev); i++) {
3104                 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM];
3105
3106                 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) ||
3107                     vport->vf_info.link_state != IFLA_VF_LINK_STATE_AUTO)
3108                         continue;
3109
3110                 ret = hclge_push_vf_link_status(vport);
3111                 if (ret) {
3112                         dev_err(&hdev->pdev->dev,
3113                                 "failed to push link status to vf%u, ret = %d\n",
3114                                 i, ret);
3115                 }
3116         }
3117 }
3118
3119 static void hclge_update_link_status(struct hclge_dev *hdev)
3120 {
3121         struct hnae3_handle *rhandle = &hdev->vport[0].roce;
3122         struct hnae3_handle *handle = &hdev->vport[0].nic;
3123         struct hnae3_client *rclient = hdev->roce_client;
3124         struct hnae3_client *client = hdev->nic_client;
3125         int state;
3126         int ret;
3127
3128         if (!client)
3129                 return;
3130
3131         if (test_and_set_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state))
3132                 return;
3133
3134         ret = hclge_get_mac_phy_link(hdev, &state);
3135         if (ret) {
3136                 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state);
3137                 return;
3138         }
3139
3140         if (state != hdev->hw.mac.link) {
3141                 hdev->hw.mac.link = state;
3142                 client->ops->link_status_change(handle, state);
3143                 hclge_config_mac_tnl_int(hdev, state);
3144                 if (rclient && rclient->ops->link_status_change)
3145                         rclient->ops->link_status_change(rhandle, state);
3146
3147                 hclge_push_link_status(hdev);
3148         }
3149
3150         clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state);
3151 }
3152
3153 static void hclge_update_speed_advertising(struct hclge_mac *mac)
3154 {
3155         u32 speed_ability;
3156
3157         if (hclge_get_speed_bit(mac->speed, &speed_ability))
3158                 return;
3159
3160         switch (mac->module_type) {
3161         case HNAE3_MODULE_TYPE_FIBRE_LR:
3162                 hclge_convert_setting_lr(speed_ability, mac->advertising);
3163                 break;
3164         case HNAE3_MODULE_TYPE_FIBRE_SR:
3165         case HNAE3_MODULE_TYPE_AOC:
3166                 hclge_convert_setting_sr(speed_ability, mac->advertising);
3167                 break;
3168         case HNAE3_MODULE_TYPE_CR:
3169                 hclge_convert_setting_cr(speed_ability, mac->advertising);
3170                 break;
3171         case HNAE3_MODULE_TYPE_KR:
3172                 hclge_convert_setting_kr(speed_ability, mac->advertising);
3173                 break;
3174         default:
3175                 break;
3176         }
3177 }
3178
3179 static void hclge_update_fec_advertising(struct hclge_mac *mac)
3180 {
3181         if (mac->fec_mode & BIT(HNAE3_FEC_RS))
3182                 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
3183                                  mac->advertising);
3184         else if (mac->fec_mode & BIT(HNAE3_FEC_LLRS))
3185                 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
3186                                  mac->advertising);
3187         else if (mac->fec_mode & BIT(HNAE3_FEC_BASER))
3188                 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
3189                                  mac->advertising);
3190         else
3191                 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
3192                                  mac->advertising);
3193 }
3194
3195 static void hclge_update_pause_advertising(struct hclge_dev *hdev)
3196 {
3197         struct hclge_mac *mac = &hdev->hw.mac;
3198         bool rx_en, tx_en;
3199
3200         switch (hdev->fc_mode_last_time) {
3201         case HCLGE_FC_RX_PAUSE:
3202                 rx_en = true;
3203                 tx_en = false;
3204                 break;
3205         case HCLGE_FC_TX_PAUSE:
3206                 rx_en = false;
3207                 tx_en = true;
3208                 break;
3209         case HCLGE_FC_FULL:
3210                 rx_en = true;
3211                 tx_en = true;
3212                 break;
3213         default:
3214                 rx_en = false;
3215                 tx_en = false;
3216                 break;
3217         }
3218
3219         linkmode_set_pause(mac->advertising, tx_en, rx_en);
3220 }
3221
3222 static void hclge_update_advertising(struct hclge_dev *hdev)
3223 {
3224         struct hclge_mac *mac = &hdev->hw.mac;
3225
3226         linkmode_zero(mac->advertising);
3227         hclge_update_speed_advertising(mac);
3228         hclge_update_fec_advertising(mac);
3229         hclge_update_pause_advertising(hdev);
3230 }
3231
3232 static void hclge_update_port_capability(struct hclge_dev *hdev,
3233                                          struct hclge_mac *mac)
3234 {
3235         if (hnae3_dev_fec_supported(hdev))
3236                 hclge_convert_setting_fec(mac);
3237
3238         /* firmware can not identify back plane type, the media type
3239          * read from configuration can help deal it
3240          */
3241         if (mac->media_type == HNAE3_MEDIA_TYPE_BACKPLANE &&
3242             mac->module_type == HNAE3_MODULE_TYPE_UNKNOWN)
3243                 mac->module_type = HNAE3_MODULE_TYPE_KR;
3244         else if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER)
3245                 mac->module_type = HNAE3_MODULE_TYPE_TP;
3246
3247         if (mac->support_autoneg) {
3248                 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mac->supported);
3249                 linkmode_copy(mac->advertising, mac->supported);
3250         } else {
3251                 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
3252                                    mac->supported);
3253                 hclge_update_advertising(hdev);
3254         }
3255 }
3256
3257 static int hclge_get_sfp_speed(struct hclge_dev *hdev, u32 *speed)
3258 {
3259         struct hclge_sfp_info_cmd *resp;
3260         struct hclge_desc desc;
3261         int ret;
3262
3263         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true);
3264         resp = (struct hclge_sfp_info_cmd *)desc.data;
3265         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3266         if (ret == -EOPNOTSUPP) {
3267                 dev_warn(&hdev->pdev->dev,
3268                          "IMP do not support get SFP speed %d\n", ret);
3269                 return ret;
3270         } else if (ret) {
3271                 dev_err(&hdev->pdev->dev, "get sfp speed failed %d\n", ret);
3272                 return ret;
3273         }
3274
3275         *speed = le32_to_cpu(resp->speed);
3276
3277         return 0;
3278 }
3279
3280 static int hclge_get_sfp_info(struct hclge_dev *hdev, struct hclge_mac *mac)
3281 {
3282         struct hclge_sfp_info_cmd *resp;
3283         struct hclge_desc desc;
3284         int ret;
3285
3286         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true);
3287         resp = (struct hclge_sfp_info_cmd *)desc.data;
3288
3289         resp->query_type = QUERY_ACTIVE_SPEED;
3290
3291         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3292         if (ret == -EOPNOTSUPP) {
3293                 dev_warn(&hdev->pdev->dev,
3294                          "IMP does not support get SFP info %d\n", ret);
3295                 return ret;
3296         } else if (ret) {
3297                 dev_err(&hdev->pdev->dev, "get sfp info failed %d\n", ret);
3298                 return ret;
3299         }
3300
3301         /* In some case, mac speed get from IMP may be 0, it shouldn't be
3302          * set to mac->speed.
3303          */
3304         if (!le32_to_cpu(resp->speed))
3305                 return 0;
3306
3307         mac->speed = le32_to_cpu(resp->speed);
3308         /* if resp->speed_ability is 0, it means it's an old version
3309          * firmware, do not update these params
3310          */
3311         if (resp->speed_ability) {
3312                 mac->module_type = le32_to_cpu(resp->module_type);
3313                 mac->speed_ability = le32_to_cpu(resp->speed_ability);
3314                 mac->autoneg = resp->autoneg;
3315                 mac->support_autoneg = resp->autoneg_ability;
3316                 mac->speed_type = QUERY_ACTIVE_SPEED;
3317                 mac->lane_num = resp->lane_num;
3318                 if (!resp->active_fec)
3319                         mac->fec_mode = 0;
3320                 else
3321                         mac->fec_mode = BIT(resp->active_fec);
3322                 mac->fec_ability = resp->fec_ability;
3323         } else {
3324                 mac->speed_type = QUERY_SFP_SPEED;
3325         }
3326
3327         return 0;
3328 }
3329
3330 static int hclge_get_phy_link_ksettings(struct hnae3_handle *handle,
3331                                         struct ethtool_link_ksettings *cmd)
3332 {
3333         struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM];
3334         struct hclge_vport *vport = hclge_get_vport(handle);
3335         struct hclge_phy_link_ksetting_0_cmd *req0;
3336         struct hclge_phy_link_ksetting_1_cmd *req1;
3337         u32 supported, advertising, lp_advertising;
3338         struct hclge_dev *hdev = vport->back;
3339         int ret;
3340
3341         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING,
3342                                    true);
3343         desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
3344         hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING,
3345                                    true);
3346
3347         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM);
3348         if (ret) {
3349                 dev_err(&hdev->pdev->dev,
3350                         "failed to get phy link ksetting, ret = %d.\n", ret);
3351                 return ret;
3352         }
3353
3354         req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data;
3355         cmd->base.autoneg = req0->autoneg;
3356         cmd->base.speed = le32_to_cpu(req0->speed);
3357         cmd->base.duplex = req0->duplex;
3358         cmd->base.port = req0->port;
3359         cmd->base.transceiver = req0->transceiver;
3360         cmd->base.phy_address = req0->phy_address;
3361         cmd->base.eth_tp_mdix = req0->eth_tp_mdix;
3362         cmd->base.eth_tp_mdix_ctrl = req0->eth_tp_mdix_ctrl;
3363         supported = le32_to_cpu(req0->supported);
3364         advertising = le32_to_cpu(req0->advertising);
3365         lp_advertising = le32_to_cpu(req0->lp_advertising);
3366         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
3367                                                 supported);
3368         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
3369                                                 advertising);
3370         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising,
3371                                                 lp_advertising);
3372
3373         req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data;
3374         cmd->base.master_slave_cfg = req1->master_slave_cfg;
3375         cmd->base.master_slave_state = req1->master_slave_state;
3376
3377         return 0;
3378 }
3379
3380 static int
3381 hclge_set_phy_link_ksettings(struct hnae3_handle *handle,
3382                              const struct ethtool_link_ksettings *cmd)
3383 {
3384         struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM];
3385         struct hclge_vport *vport = hclge_get_vport(handle);
3386         struct hclge_phy_link_ksetting_0_cmd *req0;
3387         struct hclge_phy_link_ksetting_1_cmd *req1;
3388         struct hclge_dev *hdev = vport->back;
3389         u32 advertising;
3390         int ret;
3391
3392         if (cmd->base.autoneg == AUTONEG_DISABLE &&
3393             ((cmd->base.speed != SPEED_100 && cmd->base.speed != SPEED_10) ||
3394              (cmd->base.duplex != DUPLEX_HALF &&
3395               cmd->base.duplex != DUPLEX_FULL)))
3396                 return -EINVAL;
3397
3398         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING,
3399                                    false);
3400         desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
3401         hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING,
3402                                    false);
3403
3404         req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data;
3405         req0->autoneg = cmd->base.autoneg;
3406         req0->speed = cpu_to_le32(cmd->base.speed);
3407         req0->duplex = cmd->base.duplex;
3408         ethtool_convert_link_mode_to_legacy_u32(&advertising,
3409                                                 cmd->link_modes.advertising);
3410         req0->advertising = cpu_to_le32(advertising);
3411         req0->eth_tp_mdix_ctrl = cmd->base.eth_tp_mdix_ctrl;
3412
3413         req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data;
3414         req1->master_slave_cfg = cmd->base.master_slave_cfg;
3415
3416         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM);
3417         if (ret) {
3418                 dev_err(&hdev->pdev->dev,
3419                         "failed to set phy link ksettings, ret = %d.\n", ret);
3420                 return ret;
3421         }
3422
3423         hdev->hw.mac.autoneg = cmd->base.autoneg;
3424         hdev->hw.mac.speed = cmd->base.speed;
3425         hdev->hw.mac.duplex = cmd->base.duplex;
3426         linkmode_copy(hdev->hw.mac.advertising, cmd->link_modes.advertising);
3427
3428         return 0;
3429 }
3430
3431 static int hclge_update_tp_port_info(struct hclge_dev *hdev)
3432 {
3433         struct ethtool_link_ksettings cmd;
3434         int ret;
3435
3436         if (!hnae3_dev_phy_imp_supported(hdev))
3437                 return 0;
3438
3439         ret = hclge_get_phy_link_ksettings(&hdev->vport->nic, &cmd);
3440         if (ret)
3441                 return ret;
3442
3443         hdev->hw.mac.autoneg = cmd.base.autoneg;
3444         hdev->hw.mac.speed = cmd.base.speed;
3445         hdev->hw.mac.duplex = cmd.base.duplex;
3446
3447         return 0;
3448 }
3449
3450 static int hclge_tp_port_init(struct hclge_dev *hdev)
3451 {
3452         struct ethtool_link_ksettings cmd;
3453
3454         if (!hnae3_dev_phy_imp_supported(hdev))
3455                 return 0;
3456
3457         cmd.base.autoneg = hdev->hw.mac.autoneg;
3458         cmd.base.speed = hdev->hw.mac.speed;
3459         cmd.base.duplex = hdev->hw.mac.duplex;
3460         linkmode_copy(cmd.link_modes.advertising, hdev->hw.mac.advertising);
3461
3462         return hclge_set_phy_link_ksettings(&hdev->vport->nic, &cmd);
3463 }
3464
3465 static int hclge_update_port_info(struct hclge_dev *hdev)
3466 {
3467         struct hclge_mac *mac = &hdev->hw.mac;
3468         int speed;
3469         int ret;
3470
3471         /* get the port info from SFP cmd if not copper port */
3472         if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER)
3473                 return hclge_update_tp_port_info(hdev);
3474
3475         /* if IMP does not support get SFP/qSFP info, return directly */
3476         if (!hdev->support_sfp_query)
3477                 return 0;
3478
3479         if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
3480                 speed = mac->speed;
3481                 ret = hclge_get_sfp_info(hdev, mac);
3482         } else {
3483                 speed = HCLGE_MAC_SPEED_UNKNOWN;
3484                 ret = hclge_get_sfp_speed(hdev, &speed);
3485         }
3486
3487         if (ret == -EOPNOTSUPP) {
3488                 hdev->support_sfp_query = false;
3489                 return ret;
3490         } else if (ret) {
3491                 return ret;
3492         }
3493
3494         if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
3495                 if (mac->speed_type == QUERY_ACTIVE_SPEED) {
3496                         hclge_update_port_capability(hdev, mac);
3497                         if (mac->speed != speed)
3498                                 (void)hclge_tm_port_shaper_cfg(hdev);
3499                         return 0;
3500                 }
3501                 return hclge_cfg_mac_speed_dup(hdev, mac->speed,
3502                                                HCLGE_MAC_FULL, mac->lane_num);
3503         } else {
3504                 if (speed == HCLGE_MAC_SPEED_UNKNOWN)
3505                         return 0; /* do nothing if no SFP */
3506
3507                 /* must config full duplex for SFP */
3508                 return hclge_cfg_mac_speed_dup(hdev, speed, HCLGE_MAC_FULL, 0);
3509         }
3510 }
3511
3512 static int hclge_get_status(struct hnae3_handle *handle)
3513 {
3514         struct hclge_vport *vport = hclge_get_vport(handle);
3515         struct hclge_dev *hdev = vport->back;
3516
3517         hclge_update_link_status(hdev);
3518
3519         return hdev->hw.mac.link;
3520 }
3521
3522 static struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf)
3523 {
3524         if (!pci_num_vf(hdev->pdev)) {
3525                 dev_err(&hdev->pdev->dev,
3526                         "SRIOV is disabled, can not get vport(%d) info.\n", vf);
3527                 return NULL;
3528         }
3529
3530         if (vf < 0 || vf >= pci_num_vf(hdev->pdev)) {
3531                 dev_err(&hdev->pdev->dev,
3532                         "vf id(%d) is out of range(0 <= vfid < %d)\n",
3533                         vf, pci_num_vf(hdev->pdev));
3534                 return NULL;
3535         }
3536
3537         /* VF start from 1 in vport */
3538         vf += HCLGE_VF_VPORT_START_NUM;
3539         return &hdev->vport[vf];
3540 }
3541
3542 static int hclge_get_vf_config(struct hnae3_handle *handle, int vf,
3543                                struct ifla_vf_info *ivf)
3544 {
3545         struct hclge_vport *vport = hclge_get_vport(handle);
3546         struct hclge_dev *hdev = vport->back;
3547
3548         vport = hclge_get_vf_vport(hdev, vf);
3549         if (!vport)
3550                 return -EINVAL;
3551
3552         ivf->vf = vf;
3553         ivf->linkstate = vport->vf_info.link_state;
3554         ivf->spoofchk = vport->vf_info.spoofchk;
3555         ivf->trusted = vport->vf_info.trusted;
3556         ivf->min_tx_rate = 0;
3557         ivf->max_tx_rate = vport->vf_info.max_tx_rate;
3558         ivf->vlan = vport->port_base_vlan_cfg.vlan_info.vlan_tag;
3559         ivf->vlan_proto = htons(vport->port_base_vlan_cfg.vlan_info.vlan_proto);
3560         ivf->qos = vport->port_base_vlan_cfg.vlan_info.qos;
3561         ether_addr_copy(ivf->mac, vport->vf_info.mac);
3562
3563         return 0;
3564 }
3565
3566 static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf,
3567                                    int link_state)
3568 {
3569         struct hclge_vport *vport = hclge_get_vport(handle);
3570         struct hclge_dev *hdev = vport->back;
3571         int link_state_old;
3572         int ret;
3573
3574         vport = hclge_get_vf_vport(hdev, vf);
3575         if (!vport)
3576                 return -EINVAL;
3577
3578         link_state_old = vport->vf_info.link_state;
3579         vport->vf_info.link_state = link_state;
3580
3581         /* return success directly if the VF is unalive, VF will
3582          * query link state itself when it starts work.
3583          */
3584         if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state))
3585                 return 0;
3586
3587         ret = hclge_push_vf_link_status(vport);
3588         if (ret) {
3589                 vport->vf_info.link_state = link_state_old;
3590                 dev_err(&hdev->pdev->dev,
3591                         "failed to push vf%d link status, ret = %d\n", vf, ret);
3592         }
3593
3594         return ret;
3595 }
3596
3597 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
3598 {
3599         u32 cmdq_src_reg, msix_src_reg, hw_err_src_reg;
3600
3601         /* fetch the events from their corresponding regs */
3602         cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
3603         msix_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
3604         hw_err_src_reg = hclge_read_dev(&hdev->hw,
3605                                         HCLGE_RAS_PF_OTHER_INT_STS_REG);
3606
3607         /* Assumption: If by any chance reset and mailbox events are reported
3608          * together then we will only process reset event in this go and will
3609          * defer the processing of the mailbox events. Since, we would have not
3610          * cleared RX CMDQ event this time we would receive again another
3611          * interrupt from H/W just for the mailbox.
3612          *
3613          * check for vector0 reset event sources
3614          */
3615         if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) {
3616                 dev_info(&hdev->pdev->dev, "IMP reset interrupt\n");
3617                 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
3618                 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
3619                 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
3620                 hdev->rst_stats.imp_rst_cnt++;
3621                 return HCLGE_VECTOR0_EVENT_RST;
3622         }
3623
3624         if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & msix_src_reg) {
3625                 dev_info(&hdev->pdev->dev, "global reset interrupt\n");
3626                 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
3627                 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
3628                 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
3629                 hdev->rst_stats.global_rst_cnt++;
3630                 return HCLGE_VECTOR0_EVENT_RST;
3631         }
3632
3633         /* check for vector0 msix event and hardware error event source */
3634         if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK ||
3635             hw_err_src_reg & HCLGE_RAS_REG_ERR_MASK)
3636                 return HCLGE_VECTOR0_EVENT_ERR;
3637
3638         /* check for vector0 ptp event source */
3639         if (BIT(HCLGE_VECTOR0_REG_PTP_INT_B) & msix_src_reg) {
3640                 *clearval = msix_src_reg;
3641                 return HCLGE_VECTOR0_EVENT_PTP;
3642         }
3643
3644         /* check for vector0 mailbox(=CMDQ RX) event source */
3645         if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
3646                 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
3647                 *clearval = cmdq_src_reg;
3648                 return HCLGE_VECTOR0_EVENT_MBX;
3649         }
3650
3651         /* print other vector0 event source */
3652         dev_info(&hdev->pdev->dev,
3653                  "INT status: CMDQ(%#x) HW errors(%#x) other(%#x)\n",
3654                  cmdq_src_reg, hw_err_src_reg, msix_src_reg);
3655
3656         return HCLGE_VECTOR0_EVENT_OTHER;
3657 }
3658
3659 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
3660                                     u32 regclr)
3661 {
3662         switch (event_type) {
3663         case HCLGE_VECTOR0_EVENT_PTP:
3664         case HCLGE_VECTOR0_EVENT_RST:
3665                 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
3666                 break;
3667         case HCLGE_VECTOR0_EVENT_MBX:
3668                 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
3669                 break;
3670         default:
3671                 break;
3672         }
3673 }
3674
3675 static void hclge_clear_all_event_cause(struct hclge_dev *hdev)
3676 {
3677         hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST,
3678                                 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) |
3679                                 BIT(HCLGE_VECTOR0_CORERESET_INT_B) |
3680                                 BIT(HCLGE_VECTOR0_IMPRESET_INT_B));
3681         hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0);
3682 }
3683
3684 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
3685 {
3686         writel(enable ? 1 : 0, vector->addr);
3687 }
3688
3689 static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
3690 {
3691         struct hclge_dev *hdev = data;
3692         unsigned long flags;
3693         u32 clearval = 0;
3694         u32 event_cause;
3695
3696         hclge_enable_vector(&hdev->misc_vector, false);
3697         event_cause = hclge_check_event_cause(hdev, &clearval);
3698
3699         /* vector 0 interrupt is shared with reset and mailbox source events. */
3700         switch (event_cause) {
3701         case HCLGE_VECTOR0_EVENT_ERR:
3702                 hclge_errhand_task_schedule(hdev);
3703                 break;
3704         case HCLGE_VECTOR0_EVENT_RST:
3705                 hclge_reset_task_schedule(hdev);
3706                 break;
3707         case HCLGE_VECTOR0_EVENT_PTP:
3708                 spin_lock_irqsave(&hdev->ptp->lock, flags);
3709                 hclge_ptp_clean_tx_hwts(hdev);
3710                 spin_unlock_irqrestore(&hdev->ptp->lock, flags);
3711                 break;
3712         case HCLGE_VECTOR0_EVENT_MBX:
3713                 /* If we are here then,
3714                  * 1. Either we are not handling any mbx task and we are not
3715                  *    scheduled as well
3716                  *                        OR
3717                  * 2. We could be handling a mbx task but nothing more is
3718                  *    scheduled.
3719                  * In both cases, we should schedule mbx task as there are more
3720                  * mbx messages reported by this interrupt.
3721                  */
3722                 hclge_mbx_task_schedule(hdev);
3723                 break;
3724         default:
3725                 dev_warn(&hdev->pdev->dev,
3726                          "received unknown or unhandled event of vector0\n");
3727                 break;
3728         }
3729
3730         hclge_clear_event_cause(hdev, event_cause, clearval);
3731
3732         /* Enable interrupt if it is not caused by reset event or error event */
3733         if (event_cause == HCLGE_VECTOR0_EVENT_PTP ||
3734             event_cause == HCLGE_VECTOR0_EVENT_MBX ||
3735             event_cause == HCLGE_VECTOR0_EVENT_OTHER)
3736                 hclge_enable_vector(&hdev->misc_vector, true);
3737
3738         return IRQ_HANDLED;
3739 }
3740
3741 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
3742 {
3743         if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) {
3744                 dev_warn(&hdev->pdev->dev,
3745                          "vector(vector_id %d) has been freed.\n", vector_id);
3746                 return;
3747         }
3748
3749         hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
3750         hdev->num_msi_left += 1;
3751         hdev->num_msi_used -= 1;
3752 }
3753
3754 static void hclge_get_misc_vector(struct hclge_dev *hdev)
3755 {
3756         struct hclge_misc_vector *vector = &hdev->misc_vector;
3757
3758         vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
3759
3760         vector->addr = hdev->hw.hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
3761         hdev->vector_status[0] = 0;
3762
3763         hdev->num_msi_left -= 1;
3764         hdev->num_msi_used += 1;
3765 }
3766
3767 static int hclge_misc_irq_init(struct hclge_dev *hdev)
3768 {
3769         int ret;
3770
3771         hclge_get_misc_vector(hdev);
3772
3773         /* this would be explicitly freed in the end */
3774         snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s",
3775                  HCLGE_NAME, pci_name(hdev->pdev));
3776         ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
3777                           0, hdev->misc_vector.name, hdev);
3778         if (ret) {
3779                 hclge_free_vector(hdev, 0);
3780                 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
3781                         hdev->misc_vector.vector_irq);
3782         }
3783
3784         return ret;
3785 }
3786
3787 static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
3788 {
3789         free_irq(hdev->misc_vector.vector_irq, hdev);
3790         hclge_free_vector(hdev, 0);
3791 }
3792
3793 int hclge_notify_client(struct hclge_dev *hdev,
3794                         enum hnae3_reset_notify_type type)
3795 {
3796         struct hnae3_handle *handle = &hdev->vport[0].nic;
3797         struct hnae3_client *client = hdev->nic_client;
3798         int ret;
3799
3800         if (!test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state) || !client)
3801                 return 0;
3802
3803         if (!client->ops->reset_notify)
3804                 return -EOPNOTSUPP;
3805
3806         ret = client->ops->reset_notify(handle, type);
3807         if (ret)
3808                 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n",
3809                         type, ret);
3810
3811         return ret;
3812 }
3813
3814 static int hclge_notify_roce_client(struct hclge_dev *hdev,
3815                                     enum hnae3_reset_notify_type type)
3816 {
3817         struct hnae3_handle *handle = &hdev->vport[0].roce;
3818         struct hnae3_client *client = hdev->roce_client;
3819         int ret;
3820
3821         if (!test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state) || !client)
3822                 return 0;
3823
3824         if (!client->ops->reset_notify)
3825                 return -EOPNOTSUPP;
3826
3827         ret = client->ops->reset_notify(handle, type);
3828         if (ret)
3829                 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)",
3830                         type, ret);
3831
3832         return ret;
3833 }
3834
3835 static int hclge_reset_wait(struct hclge_dev *hdev)
3836 {
3837 #define HCLGE_RESET_WATI_MS     100
3838 #define HCLGE_RESET_WAIT_CNT    350
3839
3840         u32 val, reg, reg_bit;
3841         u32 cnt = 0;
3842
3843         switch (hdev->reset_type) {
3844         case HNAE3_IMP_RESET:
3845                 reg = HCLGE_GLOBAL_RESET_REG;
3846                 reg_bit = HCLGE_IMP_RESET_BIT;
3847                 break;
3848         case HNAE3_GLOBAL_RESET:
3849                 reg = HCLGE_GLOBAL_RESET_REG;
3850                 reg_bit = HCLGE_GLOBAL_RESET_BIT;
3851                 break;
3852         case HNAE3_FUNC_RESET:
3853                 reg = HCLGE_FUN_RST_ING;
3854                 reg_bit = HCLGE_FUN_RST_ING_B;
3855                 break;
3856         default:
3857                 dev_err(&hdev->pdev->dev,
3858                         "Wait for unsupported reset type: %d\n",
3859                         hdev->reset_type);
3860                 return -EINVAL;
3861         }
3862
3863         val = hclge_read_dev(&hdev->hw, reg);
3864         while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
3865                 msleep(HCLGE_RESET_WATI_MS);
3866                 val = hclge_read_dev(&hdev->hw, reg);
3867                 cnt++;
3868         }
3869
3870         if (cnt >= HCLGE_RESET_WAIT_CNT) {
3871                 dev_warn(&hdev->pdev->dev,
3872                          "Wait for reset timeout: %d\n", hdev->reset_type);
3873                 return -EBUSY;
3874         }
3875
3876         return 0;
3877 }
3878
3879 static int hclge_set_vf_rst(struct hclge_dev *hdev, int func_id, bool reset)
3880 {
3881         struct hclge_vf_rst_cmd *req;
3882         struct hclge_desc desc;
3883
3884         req = (struct hclge_vf_rst_cmd *)desc.data;
3885         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GBL_RST_STATUS, false);
3886         req->dest_vfid = func_id;
3887
3888         if (reset)
3889                 req->vf_rst = 0x1;
3890
3891         return hclge_cmd_send(&hdev->hw, &desc, 1);
3892 }
3893
3894 static int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset)
3895 {
3896         int i;
3897
3898         for (i = HCLGE_VF_VPORT_START_NUM; i < hdev->num_alloc_vport; i++) {
3899                 struct hclge_vport *vport = &hdev->vport[i];
3900                 int ret;
3901
3902                 /* Send cmd to set/clear VF's FUNC_RST_ING */
3903                 ret = hclge_set_vf_rst(hdev, vport->vport_id, reset);
3904                 if (ret) {
3905                         dev_err(&hdev->pdev->dev,
3906                                 "set vf(%u) rst failed %d!\n",
3907                                 vport->vport_id - HCLGE_VF_VPORT_START_NUM,
3908                                 ret);
3909                         return ret;
3910                 }
3911
3912                 if (!reset || !test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state))
3913                         continue;
3914
3915                 /* Inform VF to process the reset.
3916                  * hclge_inform_reset_assert_to_vf may fail if VF
3917                  * driver is not loaded.
3918                  */
3919                 ret = hclge_inform_reset_assert_to_vf(vport);
3920                 if (ret)
3921                         dev_warn(&hdev->pdev->dev,
3922                                  "inform reset to vf(%u) failed %d!\n",
3923                                  vport->vport_id - HCLGE_VF_VPORT_START_NUM,
3924                                  ret);
3925         }
3926
3927         return 0;
3928 }
3929
3930 static void hclge_mailbox_service_task(struct hclge_dev *hdev)
3931 {
3932         if (!test_and_clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state) ||
3933             test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state) ||
3934             test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
3935                 return;
3936
3937         if (time_is_before_jiffies(hdev->last_mbx_scheduled +
3938                                    HCLGE_MBX_SCHED_TIMEOUT))
3939                 dev_warn(&hdev->pdev->dev,
3940                          "mbx service task is scheduled after %ums on cpu%u!\n",
3941                          jiffies_to_msecs(jiffies - hdev->last_mbx_scheduled),
3942                          smp_processor_id());
3943
3944         hclge_mbx_handler(hdev);
3945
3946         clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
3947 }
3948
3949 static void hclge_func_reset_sync_vf(struct hclge_dev *hdev)
3950 {
3951         struct hclge_pf_rst_sync_cmd *req;
3952         struct hclge_desc desc;
3953         int cnt = 0;
3954         int ret;
3955
3956         req = (struct hclge_pf_rst_sync_cmd *)desc.data;
3957         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RST_RDY, true);
3958
3959         do {
3960                 /* vf need to down netdev by mbx during PF or FLR reset */
3961                 hclge_mailbox_service_task(hdev);
3962
3963                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3964                 /* for compatible with old firmware, wait
3965                  * 100 ms for VF to stop IO
3966                  */
3967                 if (ret == -EOPNOTSUPP) {
3968                         msleep(HCLGE_RESET_SYNC_TIME);
3969                         return;
3970                 } else if (ret) {
3971                         dev_warn(&hdev->pdev->dev, "sync with VF fail %d!\n",
3972                                  ret);
3973                         return;
3974                 } else if (req->all_vf_ready) {
3975                         return;
3976                 }
3977                 msleep(HCLGE_PF_RESET_SYNC_TIME);
3978                 hclge_comm_cmd_reuse_desc(&desc, true);
3979         } while (cnt++ < HCLGE_PF_RESET_SYNC_CNT);
3980
3981         dev_warn(&hdev->pdev->dev, "sync with VF timeout!\n");
3982 }
3983
3984 void hclge_report_hw_error(struct hclge_dev *hdev,
3985                            enum hnae3_hw_error_type type)
3986 {
3987         struct hnae3_client *client = hdev->nic_client;
3988
3989         if (!client || !client->ops->process_hw_error ||
3990             !test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state))
3991                 return;
3992
3993         client->ops->process_hw_error(&hdev->vport[0].nic, type);
3994 }
3995
3996 static void hclge_handle_imp_error(struct hclge_dev *hdev)
3997 {
3998         u32 reg_val;
3999
4000         reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);
4001         if (reg_val & BIT(HCLGE_VECTOR0_IMP_RD_POISON_B)) {
4002                 hclge_report_hw_error(hdev, HNAE3_IMP_RD_POISON_ERROR);
4003                 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_RD_POISON_B);
4004                 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val);
4005         }
4006
4007         if (reg_val & BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B)) {
4008                 hclge_report_hw_error(hdev, HNAE3_CMDQ_ECC_ERROR);
4009                 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B);
4010                 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val);
4011         }
4012 }
4013
4014 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
4015 {
4016         struct hclge_desc desc;
4017         struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
4018         int ret;
4019
4020         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
4021         hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
4022         req->fun_reset_vfid = func_id;
4023
4024         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4025         if (ret)
4026                 dev_err(&hdev->pdev->dev,
4027                         "send function reset cmd fail, status =%d\n", ret);
4028
4029         return ret;
4030 }
4031
4032 static void hclge_do_reset(struct hclge_dev *hdev)
4033 {
4034         struct hnae3_handle *handle = &hdev->vport[0].nic;
4035         struct pci_dev *pdev = hdev->pdev;
4036         u32 val;
4037
4038         if (hclge_get_hw_reset_stat(handle)) {
4039                 dev_info(&pdev->dev, "hardware reset not finish\n");
4040                 dev_info(&pdev->dev, "func_rst_reg:0x%x, global_rst_reg:0x%x\n",
4041                          hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING),
4042                          hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG));
4043                 return;
4044         }
4045
4046         switch (hdev->reset_type) {
4047         case HNAE3_IMP_RESET:
4048                 dev_info(&pdev->dev, "IMP reset requested\n");
4049                 val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);
4050                 hnae3_set_bit(val, HCLGE_TRIGGER_IMP_RESET_B, 1);
4051                 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, val);
4052                 break;
4053         case HNAE3_GLOBAL_RESET:
4054                 dev_info(&pdev->dev, "global reset requested\n");
4055                 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
4056                 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
4057                 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
4058                 break;
4059         case HNAE3_FUNC_RESET:
4060                 dev_info(&pdev->dev, "PF reset requested\n");
4061                 /* schedule again to check later */
4062                 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
4063                 hclge_reset_task_schedule(hdev);
4064                 break;
4065         default:
4066                 dev_warn(&pdev->dev,
4067                          "unsupported reset type: %d\n", hdev->reset_type);
4068                 break;
4069         }
4070 }
4071
4072 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev,
4073                                                    unsigned long *addr)
4074 {
4075         enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
4076         struct hclge_dev *hdev = ae_dev->priv;
4077
4078         /* return the highest priority reset level amongst all */
4079         if (test_bit(HNAE3_IMP_RESET, addr)) {
4080                 rst_level = HNAE3_IMP_RESET;
4081                 clear_bit(HNAE3_IMP_RESET, addr);
4082                 clear_bit(HNAE3_GLOBAL_RESET, addr);
4083                 clear_bit(HNAE3_FUNC_RESET, addr);
4084         } else if (test_bit(HNAE3_GLOBAL_RESET, addr)) {
4085                 rst_level = HNAE3_GLOBAL_RESET;
4086                 clear_bit(HNAE3_GLOBAL_RESET, addr);
4087                 clear_bit(HNAE3_FUNC_RESET, addr);
4088         } else if (test_bit(HNAE3_FUNC_RESET, addr)) {
4089                 rst_level = HNAE3_FUNC_RESET;
4090                 clear_bit(HNAE3_FUNC_RESET, addr);
4091         } else if (test_bit(HNAE3_FLR_RESET, addr)) {
4092                 rst_level = HNAE3_FLR_RESET;
4093                 clear_bit(HNAE3_FLR_RESET, addr);
4094         }
4095
4096         if (hdev->reset_type != HNAE3_NONE_RESET &&
4097             rst_level < hdev->reset_type)
4098                 return HNAE3_NONE_RESET;
4099
4100         return rst_level;
4101 }
4102
4103 static void hclge_clear_reset_cause(struct hclge_dev *hdev)
4104 {
4105         u32 clearval = 0;
4106
4107         switch (hdev->reset_type) {
4108         case HNAE3_IMP_RESET:
4109                 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
4110                 break;
4111         case HNAE3_GLOBAL_RESET:
4112                 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
4113                 break;
4114         default:
4115                 break;
4116         }
4117
4118         if (!clearval)
4119                 return;
4120
4121         /* For revision 0x20, the reset interrupt source
4122          * can only be cleared after hardware reset done
4123          */
4124         if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
4125                 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG,
4126                                 clearval);
4127
4128         hclge_enable_vector(&hdev->misc_vector, true);
4129 }
4130
4131 static void hclge_reset_handshake(struct hclge_dev *hdev, bool enable)
4132 {
4133         u32 reg_val;
4134
4135         reg_val = hclge_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG);
4136         if (enable)
4137                 reg_val |= HCLGE_COMM_NIC_SW_RST_RDY;
4138         else
4139                 reg_val &= ~HCLGE_COMM_NIC_SW_RST_RDY;
4140
4141         hclge_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, reg_val);
4142 }
4143
4144 static int hclge_func_reset_notify_vf(struct hclge_dev *hdev)
4145 {
4146         int ret;
4147
4148         ret = hclge_set_all_vf_rst(hdev, true);
4149         if (ret)
4150                 return ret;
4151
4152         hclge_func_reset_sync_vf(hdev);
4153
4154         return 0;
4155 }
4156
4157 static int hclge_reset_prepare_wait(struct hclge_dev *hdev)
4158 {
4159         u32 reg_val;
4160         int ret = 0;
4161
4162         switch (hdev->reset_type) {
4163         case HNAE3_FUNC_RESET:
4164                 ret = hclge_func_reset_notify_vf(hdev);
4165                 if (ret)
4166                         return ret;
4167
4168                 ret = hclge_func_reset_cmd(hdev, 0);
4169                 if (ret) {
4170                         dev_err(&hdev->pdev->dev,
4171                                 "asserting function reset fail %d!\n", ret);
4172                         return ret;
4173                 }
4174
4175                 /* After performaning pf reset, it is not necessary to do the
4176                  * mailbox handling or send any command to firmware, because
4177                  * any mailbox handling or command to firmware is only valid
4178                  * after hclge_comm_cmd_init is called.
4179                  */
4180                 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
4181                 hdev->rst_stats.pf_rst_cnt++;
4182                 break;
4183         case HNAE3_FLR_RESET:
4184                 ret = hclge_func_reset_notify_vf(hdev);
4185                 if (ret)
4186                         return ret;
4187                 break;
4188         case HNAE3_IMP_RESET:
4189                 hclge_handle_imp_error(hdev);
4190                 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);
4191                 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG,
4192                                 BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val);
4193                 break;
4194         default:
4195                 break;
4196         }
4197
4198         /* inform hardware that preparatory work is done */
4199         msleep(HCLGE_RESET_SYNC_TIME);
4200         hclge_reset_handshake(hdev, true);
4201         dev_info(&hdev->pdev->dev, "prepare wait ok\n");
4202
4203         return ret;
4204 }
4205
4206 static void hclge_show_rst_info(struct hclge_dev *hdev)
4207 {
4208         char *buf;
4209
4210         buf = kzalloc(HCLGE_DBG_RESET_INFO_LEN, GFP_KERNEL);
4211         if (!buf)
4212                 return;
4213
4214         hclge_dbg_dump_rst_info(hdev, buf, HCLGE_DBG_RESET_INFO_LEN);
4215
4216         dev_info(&hdev->pdev->dev, "dump reset info:\n%s", buf);
4217
4218         kfree(buf);
4219 }
4220
4221 static bool hclge_reset_err_handle(struct hclge_dev *hdev)
4222 {
4223 #define MAX_RESET_FAIL_CNT 5
4224
4225         if (hdev->reset_pending) {
4226                 dev_info(&hdev->pdev->dev, "Reset pending %lu\n",
4227                          hdev->reset_pending);
4228                 return true;
4229         } else if (hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) &
4230                    HCLGE_RESET_INT_M) {
4231                 dev_info(&hdev->pdev->dev,
4232                          "reset failed because new reset interrupt\n");
4233                 hclge_clear_reset_cause(hdev);
4234                 return false;
4235         } else if (hdev->rst_stats.reset_fail_cnt < MAX_RESET_FAIL_CNT) {
4236                 hdev->rst_stats.reset_fail_cnt++;
4237                 set_bit(hdev->reset_type, &hdev->reset_pending);
4238                 dev_info(&hdev->pdev->dev,
4239                          "re-schedule reset task(%u)\n",
4240                          hdev->rst_stats.reset_fail_cnt);
4241                 return true;
4242         }
4243
4244         hclge_clear_reset_cause(hdev);
4245
4246         /* recover the handshake status when reset fail */
4247         hclge_reset_handshake(hdev, true);
4248
4249         dev_err(&hdev->pdev->dev, "Reset fail!\n");
4250
4251         hclge_show_rst_info(hdev);
4252
4253         set_bit(HCLGE_STATE_RST_FAIL, &hdev->state);
4254
4255         return false;
4256 }
4257
4258 static void hclge_update_reset_level(struct hclge_dev *hdev)
4259 {
4260         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
4261         enum hnae3_reset_type reset_level;
4262
4263         /* reset request will not be set during reset, so clear
4264          * pending reset request to avoid unnecessary reset
4265          * caused by the same reason.
4266          */
4267         hclge_get_reset_level(ae_dev, &hdev->reset_request);
4268
4269         /* if default_reset_request has a higher level reset request,
4270          * it should be handled as soon as possible. since some errors
4271          * need this kind of reset to fix.
4272          */
4273         reset_level = hclge_get_reset_level(ae_dev,
4274                                             &hdev->default_reset_request);
4275         if (reset_level != HNAE3_NONE_RESET)
4276                 set_bit(reset_level, &hdev->reset_request);
4277 }
4278
4279 static int hclge_set_rst_done(struct hclge_dev *hdev)
4280 {
4281         struct hclge_pf_rst_done_cmd *req;
4282         struct hclge_desc desc;
4283         int ret;
4284
4285         req = (struct hclge_pf_rst_done_cmd *)desc.data;
4286         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PF_RST_DONE, false);
4287         req->pf_rst_done |= HCLGE_PF_RESET_DONE_BIT;
4288
4289         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4290         /* To be compatible with the old firmware, which does not support
4291          * command HCLGE_OPC_PF_RST_DONE, just print a warning and
4292          * return success
4293          */
4294         if (ret == -EOPNOTSUPP) {
4295                 dev_warn(&hdev->pdev->dev,
4296                          "current firmware does not support command(0x%x)!\n",
4297                          HCLGE_OPC_PF_RST_DONE);
4298                 return 0;
4299         } else if (ret) {
4300                 dev_err(&hdev->pdev->dev, "assert PF reset done fail %d!\n",
4301                         ret);
4302         }
4303
4304         return ret;
4305 }
4306
4307 static int hclge_reset_prepare_up(struct hclge_dev *hdev)
4308 {
4309         int ret = 0;
4310
4311         switch (hdev->reset_type) {
4312         case HNAE3_FUNC_RESET:
4313         case HNAE3_FLR_RESET:
4314                 ret = hclge_set_all_vf_rst(hdev, false);
4315                 break;
4316         case HNAE3_GLOBAL_RESET:
4317         case HNAE3_IMP_RESET:
4318                 ret = hclge_set_rst_done(hdev);
4319                 break;
4320         default:
4321                 break;
4322         }
4323
4324         /* clear up the handshake status after re-initialize done */
4325         hclge_reset_handshake(hdev, false);
4326
4327         return ret;
4328 }
4329
4330 static int hclge_reset_stack(struct hclge_dev *hdev)
4331 {
4332         int ret;
4333
4334         ret = hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
4335         if (ret)
4336                 return ret;
4337
4338         ret = hclge_reset_ae_dev(hdev->ae_dev);
4339         if (ret)
4340                 return ret;
4341
4342         return hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
4343 }
4344
4345 static int hclge_reset_prepare(struct hclge_dev *hdev)
4346 {
4347         int ret;
4348
4349         hdev->rst_stats.reset_cnt++;
4350         /* perform reset of the stack & ae device for a client */
4351         ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT);
4352         if (ret)
4353                 return ret;
4354
4355         rtnl_lock();
4356         ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
4357         rtnl_unlock();
4358         if (ret)
4359                 return ret;
4360
4361         return hclge_reset_prepare_wait(hdev);
4362 }
4363
4364 static int hclge_reset_rebuild(struct hclge_dev *hdev)
4365 {
4366         int ret;
4367
4368         hdev->rst_stats.hw_reset_done_cnt++;
4369
4370         ret = hclge_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT);
4371         if (ret)
4372                 return ret;
4373
4374         rtnl_lock();
4375         ret = hclge_reset_stack(hdev);
4376         rtnl_unlock();
4377         if (ret)
4378                 return ret;
4379
4380         hclge_clear_reset_cause(hdev);
4381
4382         ret = hclge_notify_roce_client(hdev, HNAE3_INIT_CLIENT);
4383         /* ignore RoCE notify error if it fails HCLGE_RESET_MAX_FAIL_CNT - 1
4384          * times
4385          */
4386         if (ret &&
4387             hdev->rst_stats.reset_fail_cnt < HCLGE_RESET_MAX_FAIL_CNT - 1)
4388                 return ret;
4389
4390         ret = hclge_reset_prepare_up(hdev);
4391         if (ret)
4392                 return ret;
4393
4394         rtnl_lock();
4395         ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT);
4396         rtnl_unlock();
4397         if (ret)
4398                 return ret;
4399
4400         ret = hclge_notify_roce_client(hdev, HNAE3_UP_CLIENT);
4401         if (ret)
4402                 return ret;
4403
4404         hdev->last_reset_time = jiffies;
4405         hdev->rst_stats.reset_fail_cnt = 0;
4406         hdev->rst_stats.reset_done_cnt++;
4407         clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state);
4408
4409         hclge_update_reset_level(hdev);
4410
4411         return 0;
4412 }
4413
4414 static void hclge_reset(struct hclge_dev *hdev)
4415 {
4416         if (hclge_reset_prepare(hdev))
4417                 goto err_reset;
4418
4419         if (hclge_reset_wait(hdev))
4420                 goto err_reset;
4421
4422         if (hclge_reset_rebuild(hdev))
4423                 goto err_reset;
4424
4425         return;
4426
4427 err_reset:
4428         if (hclge_reset_err_handle(hdev))
4429                 hclge_reset_task_schedule(hdev);
4430 }
4431
4432 static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle)
4433 {
4434         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
4435         struct hclge_dev *hdev = ae_dev->priv;
4436
4437         /* We might end up getting called broadly because of 2 below cases:
4438          * 1. Recoverable error was conveyed through APEI and only way to bring
4439          *    normalcy is to reset.
4440          * 2. A new reset request from the stack due to timeout
4441          *
4442          * check if this is a new reset request and we are not here just because
4443          * last reset attempt did not succeed and watchdog hit us again. We will
4444          * know this if last reset request did not occur very recently (watchdog
4445          * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
4446          * In case of new request we reset the "reset level" to PF reset.
4447          * And if it is a repeat reset request of the most recent one then we
4448          * want to make sure we throttle the reset request. Therefore, we will
4449          * not allow it again before 3*HZ times.
4450          */
4451
4452         if (time_before(jiffies, (hdev->last_reset_time +
4453                                   HCLGE_RESET_INTERVAL))) {
4454                 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL);
4455                 return;
4456         }
4457
4458         if (hdev->default_reset_request) {
4459                 hdev->reset_level =
4460                         hclge_get_reset_level(ae_dev,
4461                                               &hdev->default_reset_request);
4462         } else if (time_after(jiffies, (hdev->last_reset_time + 4 * 5 * HZ))) {
4463                 hdev->reset_level = HNAE3_FUNC_RESET;
4464         }
4465
4466         dev_info(&hdev->pdev->dev, "received reset event, reset type is %d\n",
4467                  hdev->reset_level);
4468
4469         /* request reset & schedule reset task */
4470         set_bit(hdev->reset_level, &hdev->reset_request);
4471         hclge_reset_task_schedule(hdev);
4472
4473         if (hdev->reset_level < HNAE3_GLOBAL_RESET)
4474                 hdev->reset_level++;
4475 }
4476
4477 static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
4478                                         enum hnae3_reset_type rst_type)
4479 {
4480         struct hclge_dev *hdev = ae_dev->priv;
4481
4482         set_bit(rst_type, &hdev->default_reset_request);
4483 }
4484
4485 static void hclge_reset_timer(struct timer_list *t)
4486 {
4487         struct hclge_dev *hdev = from_timer(hdev, t, reset_timer);
4488
4489         /* if default_reset_request has no value, it means that this reset
4490          * request has already be handled, so just return here
4491          */
4492         if (!hdev->default_reset_request)
4493                 return;
4494
4495         dev_info(&hdev->pdev->dev,
4496                  "triggering reset in reset timer\n");
4497         hclge_reset_event(hdev->pdev, NULL);
4498 }
4499
4500 static void hclge_reset_subtask(struct hclge_dev *hdev)
4501 {
4502         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
4503
4504         /* check if there is any ongoing reset in the hardware. This status can
4505          * be checked from reset_pending. If there is then, we need to wait for
4506          * hardware to complete reset.
4507          *    a. If we are able to figure out in reasonable time that hardware
4508          *       has fully resetted then, we can proceed with driver, client
4509          *       reset.
4510          *    b. else, we can come back later to check this status so re-sched
4511          *       now.
4512          */
4513         hdev->last_reset_time = jiffies;
4514         hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_pending);
4515         if (hdev->reset_type != HNAE3_NONE_RESET)
4516                 hclge_reset(hdev);
4517
4518         /* check if we got any *new* reset requests to be honored */
4519         hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_request);
4520         if (hdev->reset_type != HNAE3_NONE_RESET)
4521                 hclge_do_reset(hdev);
4522
4523         hdev->reset_type = HNAE3_NONE_RESET;
4524 }
4525
4526 static void hclge_handle_err_reset_request(struct hclge_dev *hdev)
4527 {
4528         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
4529         enum hnae3_reset_type reset_type;
4530
4531         if (ae_dev->hw_err_reset_req) {
4532                 reset_type = hclge_get_reset_level(ae_dev,
4533                                                    &ae_dev->hw_err_reset_req);
4534                 hclge_set_def_reset_request(ae_dev, reset_type);
4535         }
4536
4537         if (hdev->default_reset_request && ae_dev->ops->reset_event)
4538                 ae_dev->ops->reset_event(hdev->pdev, NULL);
4539
4540         /* enable interrupt after error handling complete */
4541         hclge_enable_vector(&hdev->misc_vector, true);
4542 }
4543
4544 static void hclge_handle_err_recovery(struct hclge_dev *hdev)
4545 {
4546         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
4547
4548         ae_dev->hw_err_reset_req = 0;
4549
4550         if (hclge_find_error_source(hdev)) {
4551                 hclge_handle_error_info_log(ae_dev);
4552                 hclge_handle_mac_tnl(hdev);
4553         }
4554
4555         hclge_handle_err_reset_request(hdev);
4556 }
4557
4558 static void hclge_misc_err_recovery(struct hclge_dev *hdev)
4559 {
4560         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
4561         struct device *dev = &hdev->pdev->dev;
4562         u32 msix_sts_reg;
4563
4564         msix_sts_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
4565         if (msix_sts_reg & HCLGE_VECTOR0_REG_MSIX_MASK) {
4566                 if (hclge_handle_hw_msix_error
4567                                 (hdev, &hdev->default_reset_request))
4568                         dev_info(dev, "received msix interrupt 0x%x\n",
4569                                  msix_sts_reg);
4570         }
4571
4572         hclge_handle_hw_ras_error(ae_dev);
4573
4574         hclge_handle_err_reset_request(hdev);
4575 }
4576
4577 static void hclge_errhand_service_task(struct hclge_dev *hdev)
4578 {
4579         if (!test_and_clear_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state))
4580                 return;
4581
4582         if (hnae3_dev_ras_imp_supported(hdev))
4583                 hclge_handle_err_recovery(hdev);
4584         else
4585                 hclge_misc_err_recovery(hdev);
4586 }
4587
4588 static void hclge_reset_service_task(struct hclge_dev *hdev)
4589 {
4590         if (!test_and_clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
4591                 return;
4592
4593         if (time_is_before_jiffies(hdev->last_rst_scheduled +
4594                                    HCLGE_RESET_SCHED_TIMEOUT))
4595                 dev_warn(&hdev->pdev->dev,
4596                          "reset service task is scheduled after %ums on cpu%u!\n",
4597                          jiffies_to_msecs(jiffies - hdev->last_rst_scheduled),
4598                          smp_processor_id());
4599
4600         down(&hdev->reset_sem);
4601         set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
4602
4603         hclge_reset_subtask(hdev);
4604
4605         clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
4606         up(&hdev->reset_sem);
4607 }
4608
4609 static void hclge_update_vport_alive(struct hclge_dev *hdev)
4610 {
4611         int i;
4612
4613         /* start from vport 1 for PF is always alive */
4614         for (i = 1; i < hdev->num_alloc_vport; i++) {
4615                 struct hclge_vport *vport = &hdev->vport[i];
4616
4617                 if (time_after(jiffies, vport->last_active_jiffies + 8 * HZ))
4618                         clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
4619
4620                 /* If vf is not alive, set to default value */
4621                 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state))
4622                         vport->mps = HCLGE_MAC_DEFAULT_FRAME;
4623         }
4624 }
4625
4626 static void hclge_periodic_service_task(struct hclge_dev *hdev)
4627 {
4628         unsigned long delta = round_jiffies_relative(HZ);
4629
4630         if (test_bit(HCLGE_STATE_RST_FAIL, &hdev->state))
4631                 return;
4632
4633         /* Always handle the link updating to make sure link state is
4634          * updated when it is triggered by mbx.
4635          */
4636         hclge_update_link_status(hdev);
4637         hclge_sync_mac_table(hdev);
4638         hclge_sync_promisc_mode(hdev);
4639         hclge_sync_fd_table(hdev);
4640
4641         if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) {
4642                 delta = jiffies - hdev->last_serv_processed;
4643
4644                 if (delta < round_jiffies_relative(HZ)) {
4645                         delta = round_jiffies_relative(HZ) - delta;
4646                         goto out;
4647                 }
4648         }
4649
4650         hdev->serv_processed_cnt++;
4651         hclge_update_vport_alive(hdev);
4652
4653         if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) {
4654                 hdev->last_serv_processed = jiffies;
4655                 goto out;
4656         }
4657
4658         if (!(hdev->serv_processed_cnt % HCLGE_STATS_TIMER_INTERVAL))
4659                 hclge_update_stats_for_all(hdev);
4660
4661         hclge_update_port_info(hdev);
4662         hclge_sync_vlan_filter(hdev);
4663
4664         if (!(hdev->serv_processed_cnt % HCLGE_ARFS_EXPIRE_INTERVAL))
4665                 hclge_rfs_filter_expire(hdev);
4666
4667         hdev->last_serv_processed = jiffies;
4668
4669 out:
4670         hclge_task_schedule(hdev, delta);
4671 }
4672
4673 static void hclge_ptp_service_task(struct hclge_dev *hdev)
4674 {
4675         unsigned long flags;
4676
4677         if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state) ||
4678             !test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state) ||
4679             !time_is_before_jiffies(hdev->ptp->tx_start + HZ))
4680                 return;
4681
4682         /* to prevent concurrence with the irq handler */
4683         spin_lock_irqsave(&hdev->ptp->lock, flags);
4684
4685         /* check HCLGE_STATE_PTP_TX_HANDLING here again, since the irq
4686          * handler may handle it just before spin_lock_irqsave().
4687          */
4688         if (test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state))
4689                 hclge_ptp_clean_tx_hwts(hdev);
4690
4691         spin_unlock_irqrestore(&hdev->ptp->lock, flags);
4692 }
4693
4694 static void hclge_service_task(struct work_struct *work)
4695 {
4696         struct hclge_dev *hdev =
4697                 container_of(work, struct hclge_dev, service_task.work);
4698
4699         hclge_errhand_service_task(hdev);
4700         hclge_reset_service_task(hdev);
4701         hclge_ptp_service_task(hdev);
4702         hclge_mailbox_service_task(hdev);
4703         hclge_periodic_service_task(hdev);
4704
4705         /* Handle error recovery, reset and mbx again in case periodical task
4706          * delays the handling by calling hclge_task_schedule() in
4707          * hclge_periodic_service_task().
4708          */
4709         hclge_errhand_service_task(hdev);
4710         hclge_reset_service_task(hdev);
4711         hclge_mailbox_service_task(hdev);
4712 }
4713
4714 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
4715 {
4716         /* VF handle has no client */
4717         if (!handle->client)
4718                 return container_of(handle, struct hclge_vport, nic);
4719         else if (handle->client->type == HNAE3_CLIENT_ROCE)
4720                 return container_of(handle, struct hclge_vport, roce);
4721         else
4722                 return container_of(handle, struct hclge_vport, nic);
4723 }
4724
4725 static void hclge_get_vector_info(struct hclge_dev *hdev, u16 idx,
4726                                   struct hnae3_vector_info *vector_info)
4727 {
4728 #define HCLGE_PF_MAX_VECTOR_NUM_DEV_V2  64
4729
4730         vector_info->vector = pci_irq_vector(hdev->pdev, idx);
4731
4732         /* need an extend offset to config vector >= 64 */
4733         if (idx - 1 < HCLGE_PF_MAX_VECTOR_NUM_DEV_V2)
4734                 vector_info->io_addr = hdev->hw.hw.io_base +
4735                                 HCLGE_VECTOR_REG_BASE +
4736                                 (idx - 1) * HCLGE_VECTOR_REG_OFFSET;
4737         else
4738                 vector_info->io_addr = hdev->hw.hw.io_base +
4739                                 HCLGE_VECTOR_EXT_REG_BASE +
4740                                 (idx - 1) / HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 *
4741                                 HCLGE_VECTOR_REG_OFFSET_H +
4742                                 (idx - 1) % HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 *
4743                                 HCLGE_VECTOR_REG_OFFSET;
4744
4745         hdev->vector_status[idx] = hdev->vport[0].vport_id;
4746         hdev->vector_irq[idx] = vector_info->vector;
4747 }
4748
4749 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
4750                             struct hnae3_vector_info *vector_info)
4751 {
4752         struct hclge_vport *vport = hclge_get_vport(handle);
4753         struct hnae3_vector_info *vector = vector_info;
4754         struct hclge_dev *hdev = vport->back;
4755         int alloc = 0;
4756         u16 i = 0;
4757         u16 j;
4758
4759         vector_num = min_t(u16, hdev->num_nic_msi - 1, vector_num);
4760         vector_num = min(hdev->num_msi_left, vector_num);
4761
4762         for (j = 0; j < vector_num; j++) {
4763                 while (++i < hdev->num_nic_msi) {
4764                         if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
4765                                 hclge_get_vector_info(hdev, i, vector);
4766                                 vector++;
4767                                 alloc++;
4768
4769                                 break;
4770                         }
4771                 }
4772         }
4773         hdev->num_msi_left -= alloc;
4774         hdev->num_msi_used += alloc;
4775
4776         return alloc;
4777 }
4778
4779 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
4780 {
4781         int i;
4782
4783         for (i = 0; i < hdev->num_msi; i++)
4784                 if (vector == hdev->vector_irq[i])
4785                         return i;
4786
4787         return -EINVAL;
4788 }
4789
4790 static int hclge_put_vector(struct hnae3_handle *handle, int vector)
4791 {
4792         struct hclge_vport *vport = hclge_get_vport(handle);
4793         struct hclge_dev *hdev = vport->back;
4794         int vector_id;
4795
4796         vector_id = hclge_get_vector_index(hdev, vector);
4797         if (vector_id < 0) {
4798                 dev_err(&hdev->pdev->dev,
4799                         "Get vector index fail. vector = %d\n", vector);
4800                 return vector_id;
4801         }
4802
4803         hclge_free_vector(hdev, vector_id);
4804
4805         return 0;
4806 }
4807
4808 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
4809                          u8 *key, u8 *hfunc)
4810 {
4811         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
4812         struct hclge_vport *vport = hclge_get_vport(handle);
4813         struct hclge_comm_rss_cfg *rss_cfg = &vport->back->rss_cfg;
4814
4815         hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc);
4816
4817         hclge_comm_get_rss_indir_tbl(rss_cfg, indir,
4818                                      ae_dev->dev_specs.rss_ind_tbl_size);
4819
4820         return 0;
4821 }
4822
4823 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
4824                          const  u8 *key, const  u8 hfunc)
4825 {
4826         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
4827         struct hclge_vport *vport = hclge_get_vport(handle);
4828         struct hclge_dev *hdev = vport->back;
4829         struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg;
4830         int ret, i;
4831
4832         ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, hfunc);
4833         if (ret) {
4834                 dev_err(&hdev->pdev->dev, "invalid hfunc type %u\n", hfunc);
4835                 return ret;
4836         }
4837
4838         /* Update the shadow RSS table with user specified qids */
4839         for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++)
4840                 rss_cfg->rss_indirection_tbl[i] = indir[i];
4841
4842         /* Update the hardware */
4843         return hclge_comm_set_rss_indir_table(ae_dev, &hdev->hw.hw,
4844                                               rss_cfg->rss_indirection_tbl);
4845 }
4846
4847 static int hclge_set_rss_tuple(struct hnae3_handle *handle,
4848                                struct ethtool_rxnfc *nfc)
4849 {
4850         struct hclge_vport *vport = hclge_get_vport(handle);
4851         struct hclge_dev *hdev = vport->back;
4852         int ret;
4853
4854         ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw,
4855                                        &hdev->rss_cfg, nfc);
4856         if (ret) {
4857                 dev_err(&hdev->pdev->dev,
4858                         "failed to set rss tuple, ret = %d.\n", ret);
4859                 return ret;
4860         }
4861
4862         hclge_comm_get_rss_type(&vport->nic, &hdev->rss_cfg.rss_tuple_sets);
4863         return 0;
4864 }
4865
4866 static int hclge_get_rss_tuple(struct hnae3_handle *handle,
4867                                struct ethtool_rxnfc *nfc)
4868 {
4869         struct hclge_vport *vport = hclge_get_vport(handle);
4870         u8 tuple_sets;
4871         int ret;
4872
4873         nfc->data = 0;
4874
4875         ret = hclge_comm_get_rss_tuple(&vport->back->rss_cfg, nfc->flow_type,
4876                                        &tuple_sets);
4877         if (ret || !tuple_sets)
4878                 return ret;
4879
4880         nfc->data = hclge_comm_convert_rss_tuple(tuple_sets);
4881
4882         return 0;
4883 }
4884
4885 static int hclge_get_tc_size(struct hnae3_handle *handle)
4886 {
4887         struct hclge_vport *vport = hclge_get_vport(handle);
4888         struct hclge_dev *hdev = vport->back;
4889
4890         return hdev->pf_rss_size_max;
4891 }
4892
4893 static int hclge_init_rss_tc_mode(struct hclge_dev *hdev)
4894 {
4895         struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
4896         struct hclge_vport *vport = hdev->vport;
4897         u16 tc_offset[HCLGE_MAX_TC_NUM] = {0};
4898         u16 tc_valid[HCLGE_MAX_TC_NUM] = {0};
4899         u16 tc_size[HCLGE_MAX_TC_NUM] = {0};
4900         struct hnae3_tc_info *tc_info;
4901         u16 roundup_size;
4902         u16 rss_size;
4903         int i;
4904
4905         tc_info = &vport->nic.kinfo.tc_info;
4906         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
4907                 rss_size = tc_info->tqp_count[i];
4908                 tc_valid[i] = 0;
4909
4910                 if (!(hdev->hw_tc_map & BIT(i)))
4911                         continue;
4912
4913                 /* tc_size set to hardware is the log2 of roundup power of two
4914                  * of rss_size, the acutal queue size is limited by indirection
4915                  * table.
4916                  */
4917                 if (rss_size > ae_dev->dev_specs.rss_ind_tbl_size ||
4918                     rss_size == 0) {
4919                         dev_err(&hdev->pdev->dev,
4920                                 "Configure rss tc size failed, invalid TC_SIZE = %u\n",
4921                                 rss_size);
4922                         return -EINVAL;
4923                 }
4924
4925                 roundup_size = roundup_pow_of_two(rss_size);
4926                 roundup_size = ilog2(roundup_size);
4927
4928                 tc_valid[i] = 1;
4929                 tc_size[i] = roundup_size;
4930                 tc_offset[i] = tc_info->tqp_offset[i];
4931         }
4932
4933         return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid,
4934                                           tc_size);
4935 }
4936
4937 int hclge_rss_init_hw(struct hclge_dev *hdev)
4938 {
4939         u16 *rss_indir = hdev->rss_cfg.rss_indirection_tbl;
4940         u8 *key = hdev->rss_cfg.rss_hash_key;
4941         u8 hfunc = hdev->rss_cfg.rss_algo;
4942         int ret;
4943
4944         ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw,
4945                                              rss_indir);
4946         if (ret)
4947                 return ret;
4948
4949         ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, hfunc, key);
4950         if (ret)
4951                 return ret;
4952
4953         ret = hclge_comm_set_rss_input_tuple(&hdev->vport[0].nic,
4954                                              &hdev->hw.hw, true,
4955                                              &hdev->rss_cfg);
4956         if (ret)
4957                 return ret;
4958
4959         return hclge_init_rss_tc_mode(hdev);
4960 }
4961
4962 int hclge_bind_ring_with_vector(struct hclge_vport *vport,
4963                                 int vector_id, bool en,
4964                                 struct hnae3_ring_chain_node *ring_chain)
4965 {
4966         struct hclge_dev *hdev = vport->back;
4967         struct hnae3_ring_chain_node *node;
4968         struct hclge_desc desc;
4969         struct hclge_ctrl_vector_chain_cmd *req =
4970                 (struct hclge_ctrl_vector_chain_cmd *)desc.data;
4971         enum hclge_comm_cmd_status status;
4972         enum hclge_opcode_type op;
4973         u16 tqp_type_and_id;
4974         int i;
4975
4976         op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
4977         hclge_cmd_setup_basic_desc(&desc, op, false);
4978         req->int_vector_id_l = hnae3_get_field(vector_id,
4979                                                HCLGE_VECTOR_ID_L_M,
4980                                                HCLGE_VECTOR_ID_L_S);
4981         req->int_vector_id_h = hnae3_get_field(vector_id,
4982                                                HCLGE_VECTOR_ID_H_M,
4983                                                HCLGE_VECTOR_ID_H_S);
4984
4985         i = 0;
4986         for (node = ring_chain; node; node = node->next) {
4987                 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
4988                 hnae3_set_field(tqp_type_and_id,  HCLGE_INT_TYPE_M,
4989                                 HCLGE_INT_TYPE_S,
4990                                 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B));
4991                 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
4992                                 HCLGE_TQP_ID_S, node->tqp_index);
4993                 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
4994                                 HCLGE_INT_GL_IDX_S,
4995                                 hnae3_get_field(node->int_gl_idx,
4996                                                 HNAE3_RING_GL_IDX_M,
4997                                                 HNAE3_RING_GL_IDX_S));
4998                 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
4999                 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
5000                         req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
5001                         req->vfid = vport->vport_id;
5002
5003                         status = hclge_cmd_send(&hdev->hw, &desc, 1);
5004                         if (status) {
5005                                 dev_err(&hdev->pdev->dev,
5006                                         "Map TQP fail, status is %d.\n",
5007                                         status);
5008                                 return -EIO;
5009                         }
5010                         i = 0;
5011
5012                         hclge_cmd_setup_basic_desc(&desc,
5013                                                    op,
5014                                                    false);
5015                         req->int_vector_id_l =
5016                                 hnae3_get_field(vector_id,
5017                                                 HCLGE_VECTOR_ID_L_M,
5018                                                 HCLGE_VECTOR_ID_L_S);
5019                         req->int_vector_id_h =
5020                                 hnae3_get_field(vector_id,
5021                                                 HCLGE_VECTOR_ID_H_M,
5022                                                 HCLGE_VECTOR_ID_H_S);
5023                 }
5024         }
5025
5026         if (i > 0) {
5027                 req->int_cause_num = i;
5028                 req->vfid = vport->vport_id;
5029                 status = hclge_cmd_send(&hdev->hw, &desc, 1);
5030                 if (status) {
5031                         dev_err(&hdev->pdev->dev,
5032                                 "Map TQP fail, status is %d.\n", status);
5033                         return -EIO;
5034                 }
5035         }
5036
5037         return 0;
5038 }
5039
5040 static int hclge_map_ring_to_vector(struct hnae3_handle *handle, int vector,
5041                                     struct hnae3_ring_chain_node *ring_chain)
5042 {
5043         struct hclge_vport *vport = hclge_get_vport(handle);
5044         struct hclge_dev *hdev = vport->back;
5045         int vector_id;
5046
5047         vector_id = hclge_get_vector_index(hdev, vector);
5048         if (vector_id < 0) {
5049                 dev_err(&hdev->pdev->dev,
5050                         "failed to get vector index. vector=%d\n", vector);
5051                 return vector_id;
5052         }
5053
5054         return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
5055 }
5056
5057 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, int vector,
5058                                        struct hnae3_ring_chain_node *ring_chain)
5059 {
5060         struct hclge_vport *vport = hclge_get_vport(handle);
5061         struct hclge_dev *hdev = vport->back;
5062         int vector_id, ret;
5063
5064         if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
5065                 return 0;
5066
5067         vector_id = hclge_get_vector_index(hdev, vector);
5068         if (vector_id < 0) {
5069                 dev_err(&handle->pdev->dev,
5070                         "Get vector index fail. ret =%d\n", vector_id);
5071                 return vector_id;
5072         }
5073
5074         ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
5075         if (ret)
5076                 dev_err(&handle->pdev->dev,
5077                         "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
5078                         vector_id, ret);
5079
5080         return ret;
5081 }
5082
5083 static int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, u8 vf_id,
5084                                       bool en_uc, bool en_mc, bool en_bc)
5085 {
5086         struct hclge_vport *vport = &hdev->vport[vf_id];
5087         struct hnae3_handle *handle = &vport->nic;
5088         struct hclge_promisc_cfg_cmd *req;
5089         struct hclge_desc desc;
5090         bool uc_tx_en = en_uc;
5091         u8 promisc_cfg = 0;
5092         int ret;
5093
5094         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
5095
5096         req = (struct hclge_promisc_cfg_cmd *)desc.data;
5097         req->vf_id = vf_id;
5098
5099         if (test_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->priv_flags))
5100                 uc_tx_en = false;
5101
5102         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_RX_EN, en_uc ? 1 : 0);
5103         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_RX_EN, en_mc ? 1 : 0);
5104         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_RX_EN, en_bc ? 1 : 0);
5105         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_TX_EN, uc_tx_en ? 1 : 0);
5106         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_TX_EN, en_mc ? 1 : 0);
5107         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_TX_EN, en_bc ? 1 : 0);
5108         req->extend_promisc = promisc_cfg;
5109
5110         /* to be compatible with DEVICE_VERSION_V1/2 */
5111         promisc_cfg = 0;
5112         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_UC, en_uc ? 1 : 0);
5113         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_MC, en_mc ? 1 : 0);
5114         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_BC, en_bc ? 1 : 0);
5115         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_TX_EN, 1);
5116         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_RX_EN, 1);
5117         req->promisc = promisc_cfg;
5118
5119         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5120         if (ret)
5121                 dev_err(&hdev->pdev->dev,
5122                         "failed to set vport %u promisc mode, ret = %d.\n",
5123                         vf_id, ret);
5124
5125         return ret;
5126 }
5127
5128 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc,
5129                                  bool en_mc_pmc, bool en_bc_pmc)
5130 {
5131         return hclge_cmd_set_promisc_mode(vport->back, vport->vport_id,
5132                                           en_uc_pmc, en_mc_pmc, en_bc_pmc);
5133 }
5134
5135 static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
5136                                   bool en_mc_pmc)
5137 {
5138         struct hclge_vport *vport = hclge_get_vport(handle);
5139         struct hclge_dev *hdev = vport->back;
5140         bool en_bc_pmc = true;
5141
5142         /* For device whose version below V2, if broadcast promisc enabled,
5143          * vlan filter is always bypassed. So broadcast promisc should be
5144          * disabled until user enable promisc mode
5145          */
5146         if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
5147                 en_bc_pmc = handle->netdev_flags & HNAE3_BPE ? true : false;
5148
5149         return hclge_set_vport_promisc_mode(vport, en_uc_pmc, en_mc_pmc,
5150                                             en_bc_pmc);
5151 }
5152
5153 static void hclge_request_update_promisc_mode(struct hnae3_handle *handle)
5154 {
5155         struct hclge_vport *vport = hclge_get_vport(handle);
5156
5157         set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
5158 }
5159
5160 static void hclge_sync_fd_state(struct hclge_dev *hdev)
5161 {
5162         if (hlist_empty(&hdev->fd_rule_list))
5163                 hdev->fd_active_type = HCLGE_FD_RULE_NONE;
5164 }
5165
5166 static void hclge_fd_inc_rule_cnt(struct hclge_dev *hdev, u16 location)
5167 {
5168         if (!test_bit(location, hdev->fd_bmap)) {
5169                 set_bit(location, hdev->fd_bmap);
5170                 hdev->hclge_fd_rule_num++;
5171         }
5172 }
5173
5174 static void hclge_fd_dec_rule_cnt(struct hclge_dev *hdev, u16 location)
5175 {
5176         if (test_bit(location, hdev->fd_bmap)) {
5177                 clear_bit(location, hdev->fd_bmap);
5178                 hdev->hclge_fd_rule_num--;
5179         }
5180 }
5181
5182 static void hclge_fd_free_node(struct hclge_dev *hdev,
5183                                struct hclge_fd_rule *rule)
5184 {
5185         hlist_del(&rule->rule_node);
5186         kfree(rule);
5187         hclge_sync_fd_state(hdev);
5188 }
5189
5190 static void hclge_update_fd_rule_node(struct hclge_dev *hdev,
5191                                       struct hclge_fd_rule *old_rule,
5192                                       struct hclge_fd_rule *new_rule,
5193                                       enum HCLGE_FD_NODE_STATE state)
5194 {
5195         switch (state) {
5196         case HCLGE_FD_TO_ADD:
5197         case HCLGE_FD_ACTIVE:
5198                 /* 1) if the new state is TO_ADD, just replace the old rule
5199                  * with the same location, no matter its state, because the
5200                  * new rule will be configured to the hardware.
5201                  * 2) if the new state is ACTIVE, it means the new rule
5202                  * has been configured to the hardware, so just replace
5203                  * the old rule node with the same location.
5204                  * 3) for it doesn't add a new node to the list, so it's
5205                  * unnecessary to update the rule number and fd_bmap.
5206                  */
5207                 new_rule->rule_node.next = old_rule->rule_node.next;
5208                 new_rule->rule_node.pprev = old_rule->rule_node.pprev;
5209                 memcpy(old_rule, new_rule, sizeof(*old_rule));
5210                 kfree(new_rule);
5211                 break;
5212         case HCLGE_FD_DELETED:
5213                 hclge_fd_dec_rule_cnt(hdev, old_rule->location);
5214                 hclge_fd_free_node(hdev, old_rule);
5215                 break;
5216         case HCLGE_FD_TO_DEL:
5217                 /* if new request is TO_DEL, and old rule is existent
5218                  * 1) the state of old rule is TO_DEL, we need do nothing,
5219                  * because we delete rule by location, other rule content
5220                  * is unncessary.
5221                  * 2) the state of old rule is ACTIVE, we need to change its
5222                  * state to TO_DEL, so the rule will be deleted when periodic
5223                  * task being scheduled.
5224                  * 3) the state of old rule is TO_ADD, it means the rule hasn't
5225                  * been added to hardware, so we just delete the rule node from
5226                  * fd_rule_list directly.
5227                  */
5228                 if (old_rule->state == HCLGE_FD_TO_ADD) {
5229                         hclge_fd_dec_rule_cnt(hdev, old_rule->location);
5230                         hclge_fd_free_node(hdev, old_rule);
5231                         return;
5232                 }
5233                 old_rule->state = HCLGE_FD_TO_DEL;
5234                 break;
5235         }
5236 }
5237
5238 static struct hclge_fd_rule *hclge_find_fd_rule(struct hlist_head *hlist,
5239                                                 u16 location,
5240                                                 struct hclge_fd_rule **parent)
5241 {
5242         struct hclge_fd_rule *rule;
5243         struct hlist_node *node;
5244
5245         hlist_for_each_entry_safe(rule, node, hlist, rule_node) {
5246                 if (rule->location == location)
5247                         return rule;
5248                 else if (rule->location > location)
5249                         return NULL;
5250                 /* record the parent node, use to keep the nodes in fd_rule_list
5251                  * in ascend order.
5252                  */
5253                 *parent = rule;
5254         }
5255
5256         return NULL;
5257 }
5258
5259 /* insert fd rule node in ascend order according to rule->location */
5260 static void hclge_fd_insert_rule_node(struct hlist_head *hlist,
5261                                       struct hclge_fd_rule *rule,
5262                                       struct hclge_fd_rule *parent)
5263 {
5264         INIT_HLIST_NODE(&rule->rule_node);
5265
5266         if (parent)
5267                 hlist_add_behind(&rule->rule_node, &parent->rule_node);
5268         else
5269                 hlist_add_head(&rule->rule_node, hlist);
5270 }
5271
5272 static int hclge_fd_set_user_def_cmd(struct hclge_dev *hdev,
5273                                      struct hclge_fd_user_def_cfg *cfg)
5274 {
5275         struct hclge_fd_user_def_cfg_cmd *req;
5276         struct hclge_desc desc;
5277         u16 data = 0;
5278         int ret;
5279
5280         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_USER_DEF_OP, false);
5281
5282         req = (struct hclge_fd_user_def_cfg_cmd *)desc.data;
5283
5284         hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[0].ref_cnt > 0);
5285         hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M,
5286                         HCLGE_FD_USER_DEF_OFT_S, cfg[0].offset);
5287         req->ol2_cfg = cpu_to_le16(data);
5288
5289         data = 0;
5290         hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[1].ref_cnt > 0);
5291         hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M,
5292                         HCLGE_FD_USER_DEF_OFT_S, cfg[1].offset);
5293         req->ol3_cfg = cpu_to_le16(data);
5294
5295         data = 0;
5296         hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[2].ref_cnt > 0);
5297         hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M,
5298                         HCLGE_FD_USER_DEF_OFT_S, cfg[2].offset);
5299         req->ol4_cfg = cpu_to_le16(data);
5300
5301         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5302         if (ret)
5303                 dev_err(&hdev->pdev->dev,
5304                         "failed to set fd user def data, ret= %d\n", ret);
5305         return ret;
5306 }
5307
5308 static void hclge_sync_fd_user_def_cfg(struct hclge_dev *hdev, bool locked)
5309 {
5310         int ret;
5311
5312         if (!test_and_clear_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state))
5313                 return;
5314
5315         if (!locked)
5316                 spin_lock_bh(&hdev->fd_rule_lock);
5317
5318         ret = hclge_fd_set_user_def_cmd(hdev, hdev->fd_cfg.user_def_cfg);
5319         if (ret)
5320                 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state);
5321
5322         if (!locked)
5323                 spin_unlock_bh(&hdev->fd_rule_lock);
5324 }
5325
5326 static int hclge_fd_check_user_def_refcnt(struct hclge_dev *hdev,
5327                                           struct hclge_fd_rule *rule)
5328 {
5329         struct hlist_head *hlist = &hdev->fd_rule_list;
5330         struct hclge_fd_rule *fd_rule, *parent = NULL;
5331         struct hclge_fd_user_def_info *info, *old_info;
5332         struct hclge_fd_user_def_cfg *cfg;
5333
5334         if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE ||
5335             rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE)
5336                 return 0;
5337
5338         /* for valid layer is start from 1, so need minus 1 to get the cfg */
5339         cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1];
5340         info = &rule->ep.user_def;
5341
5342         if (!cfg->ref_cnt || cfg->offset == info->offset)
5343                 return 0;
5344
5345         if (cfg->ref_cnt > 1)
5346                 goto error;
5347
5348         fd_rule = hclge_find_fd_rule(hlist, rule->location, &parent);
5349         if (fd_rule) {
5350                 old_info = &fd_rule->ep.user_def;
5351                 if (info->layer == old_info->layer)
5352                         return 0;
5353         }
5354
5355 error:
5356         dev_err(&hdev->pdev->dev,
5357                 "No available offset for layer%d fd rule, each layer only support one user def offset.\n",
5358                 info->layer + 1);
5359         return -ENOSPC;
5360 }
5361
5362 static void hclge_fd_inc_user_def_refcnt(struct hclge_dev *hdev,
5363                                          struct hclge_fd_rule *rule)
5364 {
5365         struct hclge_fd_user_def_cfg *cfg;
5366
5367         if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE ||
5368             rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE)
5369                 return;
5370
5371         cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1];
5372         if (!cfg->ref_cnt) {
5373                 cfg->offset = rule->ep.user_def.offset;
5374                 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state);
5375         }
5376         cfg->ref_cnt++;
5377 }
5378
5379 static void hclge_fd_dec_user_def_refcnt(struct hclge_dev *hdev,
5380                                          struct hclge_fd_rule *rule)
5381 {
5382         struct hclge_fd_user_def_cfg *cfg;
5383
5384         if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE ||
5385             rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE)
5386                 return;
5387
5388         cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1];
5389         if (!cfg->ref_cnt)
5390                 return;
5391
5392         cfg->ref_cnt--;
5393         if (!cfg->ref_cnt) {
5394                 cfg->offset = 0;
5395                 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state);
5396         }
5397 }
5398
5399 static void hclge_update_fd_list(struct hclge_dev *hdev,
5400                                  enum HCLGE_FD_NODE_STATE state, u16 location,
5401                                  struct hclge_fd_rule *new_rule)
5402 {
5403         struct hlist_head *hlist = &hdev->fd_rule_list;
5404         struct hclge_fd_rule *fd_rule, *parent = NULL;
5405
5406         fd_rule = hclge_find_fd_rule(hlist, location, &parent);
5407         if (fd_rule) {
5408                 hclge_fd_dec_user_def_refcnt(hdev, fd_rule);
5409                 if (state == HCLGE_FD_ACTIVE)
5410                         hclge_fd_inc_user_def_refcnt(hdev, new_rule);
5411                 hclge_sync_fd_user_def_cfg(hdev, true);
5412
5413                 hclge_update_fd_rule_node(hdev, fd_rule, new_rule, state);
5414                 return;
5415         }
5416
5417         /* it's unlikely to fail here, because we have checked the rule
5418          * exist before.
5419          */
5420         if (unlikely(state == HCLGE_FD_TO_DEL || state == HCLGE_FD_DELETED)) {
5421                 dev_warn(&hdev->pdev->dev,
5422                          "failed to delete fd rule %u, it's inexistent\n",
5423                          location);
5424                 return;
5425         }
5426
5427         hclge_fd_inc_user_def_refcnt(hdev, new_rule);
5428         hclge_sync_fd_user_def_cfg(hdev, true);
5429
5430         hclge_fd_insert_rule_node(hlist, new_rule, parent);
5431         hclge_fd_inc_rule_cnt(hdev, new_rule->location);
5432
5433         if (state == HCLGE_FD_TO_ADD) {
5434                 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state);
5435                 hclge_task_schedule(hdev, 0);
5436         }
5437 }
5438
5439 static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode)
5440 {
5441         struct hclge_get_fd_mode_cmd *req;
5442         struct hclge_desc desc;
5443         int ret;
5444
5445         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_MODE_CTRL, true);
5446
5447         req = (struct hclge_get_fd_mode_cmd *)desc.data;
5448
5449         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5450         if (ret) {
5451                 dev_err(&hdev->pdev->dev, "get fd mode fail, ret=%d\n", ret);
5452                 return ret;
5453         }
5454
5455         *fd_mode = req->mode;
5456
5457         return ret;
5458 }
5459
5460 static int hclge_get_fd_allocation(struct hclge_dev *hdev,
5461                                    u32 *stage1_entry_num,
5462                                    u32 *stage2_entry_num,
5463                                    u16 *stage1_counter_num,
5464                                    u16 *stage2_counter_num)
5465 {
5466         struct hclge_get_fd_allocation_cmd *req;
5467         struct hclge_desc desc;
5468         int ret;
5469
5470         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_GET_ALLOCATION, true);
5471
5472         req = (struct hclge_get_fd_allocation_cmd *)desc.data;
5473
5474         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5475         if (ret) {
5476                 dev_err(&hdev->pdev->dev, "query fd allocation fail, ret=%d\n",
5477                         ret);
5478                 return ret;
5479         }
5480
5481         *stage1_entry_num = le32_to_cpu(req->stage1_entry_num);
5482         *stage2_entry_num = le32_to_cpu(req->stage2_entry_num);
5483         *stage1_counter_num = le16_to_cpu(req->stage1_counter_num);
5484         *stage2_counter_num = le16_to_cpu(req->stage2_counter_num);
5485
5486         return ret;
5487 }
5488
5489 static int hclge_set_fd_key_config(struct hclge_dev *hdev,
5490                                    enum HCLGE_FD_STAGE stage_num)
5491 {
5492         struct hclge_set_fd_key_config_cmd *req;
5493         struct hclge_fd_key_cfg *stage;
5494         struct hclge_desc desc;
5495         int ret;
5496
5497         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_KEY_CONFIG, false);
5498
5499         req = (struct hclge_set_fd_key_config_cmd *)desc.data;
5500         stage = &hdev->fd_cfg.key_cfg[stage_num];
5501         req->stage = stage_num;
5502         req->key_select = stage->key_sel;
5503         req->inner_sipv6_word_en = stage->inner_sipv6_word_en;
5504         req->inner_dipv6_word_en = stage->inner_dipv6_word_en;
5505         req->outer_sipv6_word_en = stage->outer_sipv6_word_en;
5506         req->outer_dipv6_word_en = stage->outer_dipv6_word_en;
5507         req->tuple_mask = cpu_to_le32(~stage->tuple_active);
5508         req->meta_data_mask = cpu_to_le32(~stage->meta_data_active);
5509
5510         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5511         if (ret)
5512                 dev_err(&hdev->pdev->dev, "set fd key fail, ret=%d\n", ret);
5513
5514         return ret;
5515 }
5516
5517 static void hclge_fd_disable_user_def(struct hclge_dev *hdev)
5518 {
5519         struct hclge_fd_user_def_cfg *cfg = hdev->fd_cfg.user_def_cfg;
5520
5521         spin_lock_bh(&hdev->fd_rule_lock);
5522         memset(cfg, 0, sizeof(hdev->fd_cfg.user_def_cfg));
5523         spin_unlock_bh(&hdev->fd_rule_lock);
5524
5525         hclge_fd_set_user_def_cmd(hdev, cfg);
5526 }
5527
5528 static int hclge_init_fd_config(struct hclge_dev *hdev)
5529 {
5530 #define LOW_2_WORDS             0x03
5531         struct hclge_fd_key_cfg *key_cfg;
5532         int ret;
5533
5534         if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
5535                 return 0;
5536
5537         ret = hclge_get_fd_mode(hdev, &hdev->fd_cfg.fd_mode);
5538         if (ret)
5539                 return ret;
5540
5541         switch (hdev->fd_cfg.fd_mode) {
5542         case HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1:
5543                 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH;
5544                 break;
5545         case HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1:
5546                 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH / 2;
5547                 break;
5548         default:
5549                 dev_err(&hdev->pdev->dev,
5550                         "Unsupported flow director mode %u\n",
5551                         hdev->fd_cfg.fd_mode);
5552                 return -EOPNOTSUPP;
5553         }
5554
5555         key_cfg = &hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1];
5556         key_cfg->key_sel = HCLGE_FD_KEY_BASE_ON_TUPLE;
5557         key_cfg->inner_sipv6_word_en = LOW_2_WORDS;
5558         key_cfg->inner_dipv6_word_en = LOW_2_WORDS;
5559         key_cfg->outer_sipv6_word_en = 0;
5560         key_cfg->outer_dipv6_word_en = 0;
5561
5562         key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) |
5563                                 BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) |
5564                                 BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) |
5565                                 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
5566
5567         /* If use max 400bit key, we can support tuples for ether type */
5568         if (hdev->fd_cfg.fd_mode == HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) {
5569                 key_cfg->tuple_active |=
5570                                 BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC);
5571                 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
5572                         key_cfg->tuple_active |= HCLGE_FD_TUPLE_USER_DEF_TUPLES;
5573         }
5574
5575         /* roce_type is used to filter roce frames
5576          * dst_vport is used to specify the rule
5577          */
5578         key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT);
5579
5580         ret = hclge_get_fd_allocation(hdev,
5581                                       &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1],
5582                                       &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2],
5583                                       &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1],
5584                                       &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]);
5585         if (ret)
5586                 return ret;
5587
5588         return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1);
5589 }
5590
5591 static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x,
5592                                 int loc, u8 *key, bool is_add)
5593 {
5594         struct hclge_fd_tcam_config_1_cmd *req1;
5595         struct hclge_fd_tcam_config_2_cmd *req2;
5596         struct hclge_fd_tcam_config_3_cmd *req3;
5597         struct hclge_desc desc[3];
5598         int ret;
5599
5600         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false);
5601         desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
5602         hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false);
5603         desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
5604         hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false);
5605
5606         req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data;
5607         req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data;
5608         req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data;
5609
5610         req1->stage = stage;
5611         req1->xy_sel = sel_x ? 1 : 0;
5612         hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0);
5613         req1->index = cpu_to_le32(loc);
5614         req1->entry_vld = sel_x ? is_add : 0;
5615
5616         if (key) {
5617                 memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data));
5618                 memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)],
5619                        sizeof(req2->tcam_data));
5620                 memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) +
5621                        sizeof(req2->tcam_data)], sizeof(req3->tcam_data));
5622         }
5623
5624         ret = hclge_cmd_send(&hdev->hw, desc, 3);
5625         if (ret)
5626                 dev_err(&hdev->pdev->dev,
5627                         "config tcam key fail, ret=%d\n",
5628                         ret);
5629
5630         return ret;
5631 }
5632
5633 static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc,
5634                               struct hclge_fd_ad_data *action)
5635 {
5636         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
5637         struct hclge_fd_ad_config_cmd *req;
5638         struct hclge_desc desc;
5639         u64 ad_data = 0;
5640         int ret;
5641
5642         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false);
5643
5644         req = (struct hclge_fd_ad_config_cmd *)desc.data;
5645         req->index = cpu_to_le32(loc);
5646         req->stage = stage;
5647
5648         hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B,
5649                       action->write_rule_id_to_bd);
5650         hnae3_set_field(ad_data, HCLGE_FD_AD_RULE_ID_M, HCLGE_FD_AD_RULE_ID_S,
5651                         action->rule_id);
5652         if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps)) {
5653                 hnae3_set_bit(ad_data, HCLGE_FD_AD_TC_OVRD_B,
5654                               action->override_tc);
5655                 hnae3_set_field(ad_data, HCLGE_FD_AD_TC_SIZE_M,
5656                                 HCLGE_FD_AD_TC_SIZE_S, (u32)action->tc_size);
5657         }
5658         ad_data <<= 32;
5659         hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet);
5660         hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B,
5661                       action->forward_to_direct_queue);
5662         hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S,
5663                         action->queue_id);
5664         hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter);
5665         hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M,
5666                         HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id);
5667         hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage);
5668         hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S,
5669                         action->counter_id);
5670
5671         req->ad_data = cpu_to_le64(ad_data);
5672         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5673         if (ret)
5674                 dev_err(&hdev->pdev->dev, "fd ad config fail, ret=%d\n", ret);
5675
5676         return ret;
5677 }
5678
5679 static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y,
5680                                    struct hclge_fd_rule *rule)
5681 {
5682         int offset, moffset, ip_offset;
5683         enum HCLGE_FD_KEY_OPT key_opt;
5684         u16 tmp_x_s, tmp_y_s;
5685         u32 tmp_x_l, tmp_y_l;
5686         u8 *p = (u8 *)rule;
5687         int i;
5688
5689         if (rule->unused_tuple & BIT(tuple_bit))
5690                 return true;
5691
5692         key_opt = tuple_key_info[tuple_bit].key_opt;
5693         offset = tuple_key_info[tuple_bit].offset;
5694         moffset = tuple_key_info[tuple_bit].moffset;
5695
5696         switch (key_opt) {
5697         case KEY_OPT_U8:
5698                 calc_x(*key_x, p[offset], p[moffset]);
5699                 calc_y(*key_y, p[offset], p[moffset]);
5700
5701                 return true;
5702         case KEY_OPT_LE16:
5703                 calc_x(tmp_x_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset]));
5704                 calc_y(tmp_y_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset]));
5705                 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
5706                 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
5707
5708                 return true;
5709         case KEY_OPT_LE32:
5710                 calc_x(tmp_x_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset]));
5711                 calc_y(tmp_y_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset]));
5712                 *(__le32 *)key_x = cpu_to_le32(tmp_x_l);
5713                 *(__le32 *)key_y = cpu_to_le32(tmp_y_l);
5714
5715                 return true;
5716         case KEY_OPT_MAC:
5717                 for (i = 0; i < ETH_ALEN; i++) {
5718                         calc_x(key_x[ETH_ALEN - 1 - i], p[offset + i],
5719                                p[moffset + i]);
5720                         calc_y(key_y[ETH_ALEN - 1 - i], p[offset + i],
5721                                p[moffset + i]);
5722                 }
5723
5724                 return true;
5725         case KEY_OPT_IP:
5726                 ip_offset = IPV4_INDEX * sizeof(u32);
5727                 calc_x(tmp_x_l, *(u32 *)(&p[offset + ip_offset]),
5728                        *(u32 *)(&p[moffset + ip_offset]));
5729                 calc_y(tmp_y_l, *(u32 *)(&p[offset + ip_offset]),
5730                        *(u32 *)(&p[moffset + ip_offset]));
5731                 *(__le32 *)key_x = cpu_to_le32(tmp_x_l);
5732                 *(__le32 *)key_y = cpu_to_le32(tmp_y_l);
5733
5734                 return true;
5735         default:
5736                 return false;
5737         }
5738 }
5739
5740 static u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id,
5741                                  u8 vf_id, u8 network_port_id)
5742 {
5743         u32 port_number = 0;
5744
5745         if (port_type == HOST_PORT) {
5746                 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S,
5747                                 pf_id);
5748                 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S,
5749                                 vf_id);
5750                 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT);
5751         } else {
5752                 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M,
5753                                 HCLGE_NETWORK_PORT_ID_S, network_port_id);
5754                 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT);
5755         }
5756
5757         return port_number;
5758 }
5759
5760 static void hclge_fd_convert_meta_data(struct hclge_fd_key_cfg *key_cfg,
5761                                        __le32 *key_x, __le32 *key_y,
5762                                        struct hclge_fd_rule *rule)
5763 {
5764         u32 tuple_bit, meta_data = 0, tmp_x, tmp_y, port_number;
5765         u8 cur_pos = 0, tuple_size, shift_bits;
5766         unsigned int i;
5767
5768         for (i = 0; i < MAX_META_DATA; i++) {
5769                 tuple_size = meta_data_key_info[i].key_length;
5770                 tuple_bit = key_cfg->meta_data_active & BIT(i);
5771
5772                 switch (tuple_bit) {
5773                 case BIT(ROCE_TYPE):
5774                         hnae3_set_bit(meta_data, cur_pos, NIC_PACKET);
5775                         cur_pos += tuple_size;
5776                         break;
5777                 case BIT(DST_VPORT):
5778                         port_number = hclge_get_port_number(HOST_PORT, 0,
5779                                                             rule->vf_id, 0);
5780                         hnae3_set_field(meta_data,
5781                                         GENMASK(cur_pos + tuple_size, cur_pos),
5782                                         cur_pos, port_number);
5783                         cur_pos += tuple_size;
5784                         break;
5785                 default:
5786                         break;
5787                 }
5788         }
5789
5790         calc_x(tmp_x, meta_data, 0xFFFFFFFF);
5791         calc_y(tmp_y, meta_data, 0xFFFFFFFF);
5792         shift_bits = sizeof(meta_data) * 8 - cur_pos;
5793
5794         *key_x = cpu_to_le32(tmp_x << shift_bits);
5795         *key_y = cpu_to_le32(tmp_y << shift_bits);
5796 }
5797
5798 /* A complete key is combined with meta data key and tuple key.
5799  * Meta data key is stored at the MSB region, and tuple key is stored at
5800  * the LSB region, unused bits will be filled 0.
5801  */
5802 static int hclge_config_key(struct hclge_dev *hdev, u8 stage,
5803                             struct hclge_fd_rule *rule)
5804 {
5805         struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage];
5806         u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES];
5807         u8 *cur_key_x, *cur_key_y;
5808         u8 meta_data_region;
5809         u8 tuple_size;
5810         int ret;
5811         u32 i;
5812
5813         memset(key_x, 0, sizeof(key_x));
5814         memset(key_y, 0, sizeof(key_y));
5815         cur_key_x = key_x;
5816         cur_key_y = key_y;
5817
5818         for (i = 0; i < MAX_TUPLE; i++) {
5819                 bool tuple_valid;
5820
5821                 tuple_size = tuple_key_info[i].key_length / 8;
5822                 if (!(key_cfg->tuple_active & BIT(i)))
5823                         continue;
5824
5825                 tuple_valid = hclge_fd_convert_tuple(i, cur_key_x,
5826                                                      cur_key_y, rule);
5827                 if (tuple_valid) {
5828                         cur_key_x += tuple_size;
5829                         cur_key_y += tuple_size;
5830                 }
5831         }
5832
5833         meta_data_region = hdev->fd_cfg.max_key_length / 8 -
5834                         MAX_META_DATA_LENGTH / 8;
5835
5836         hclge_fd_convert_meta_data(key_cfg,
5837                                    (__le32 *)(key_x + meta_data_region),
5838                                    (__le32 *)(key_y + meta_data_region),
5839                                    rule);
5840
5841         ret = hclge_fd_tcam_config(hdev, stage, false, rule->location, key_y,
5842                                    true);
5843         if (ret) {
5844                 dev_err(&hdev->pdev->dev,
5845                         "fd key_y config fail, loc=%u, ret=%d\n",
5846                         rule->queue_id, ret);
5847                 return ret;
5848         }
5849
5850         ret = hclge_fd_tcam_config(hdev, stage, true, rule->location, key_x,
5851                                    true);
5852         if (ret)
5853                 dev_err(&hdev->pdev->dev,
5854                         "fd key_x config fail, loc=%u, ret=%d\n",
5855                         rule->queue_id, ret);
5856         return ret;
5857 }
5858
5859 static int hclge_config_action(struct hclge_dev *hdev, u8 stage,
5860                                struct hclge_fd_rule *rule)
5861 {
5862         struct hclge_vport *vport = hdev->vport;
5863         struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5864         struct hclge_fd_ad_data ad_data;
5865
5866         memset(&ad_data, 0, sizeof(struct hclge_fd_ad_data));
5867         ad_data.ad_id = rule->location;
5868
5869         if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) {
5870                 ad_data.drop_packet = true;
5871         } else if (rule->action == HCLGE_FD_ACTION_SELECT_TC) {
5872                 ad_data.override_tc = true;
5873                 ad_data.queue_id =
5874                         kinfo->tc_info.tqp_offset[rule->cls_flower.tc];
5875                 ad_data.tc_size =
5876                         ilog2(kinfo->tc_info.tqp_count[rule->cls_flower.tc]);
5877         } else {
5878                 ad_data.forward_to_direct_queue = true;
5879                 ad_data.queue_id = rule->queue_id;
5880         }
5881
5882         if (hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]) {
5883                 ad_data.use_counter = true;
5884                 ad_data.counter_id = rule->vf_id %
5885                                      hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1];
5886         } else {
5887                 ad_data.use_counter = false;
5888                 ad_data.counter_id = 0;
5889         }
5890
5891         ad_data.use_next_stage = false;
5892         ad_data.next_input_key = 0;
5893
5894         ad_data.write_rule_id_to_bd = true;
5895         ad_data.rule_id = rule->location;
5896
5897         return hclge_fd_ad_config(hdev, stage, ad_data.ad_id, &ad_data);
5898 }
5899
5900 static int hclge_fd_check_tcpip4_tuple(struct ethtool_tcpip4_spec *spec,
5901                                        u32 *unused_tuple)
5902 {
5903         if (!spec || !unused_tuple)
5904                 return -EINVAL;
5905
5906         *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC);
5907
5908         if (!spec->ip4src)
5909                 *unused_tuple |= BIT(INNER_SRC_IP);
5910
5911         if (!spec->ip4dst)
5912                 *unused_tuple |= BIT(INNER_DST_IP);
5913
5914         if (!spec->psrc)
5915                 *unused_tuple |= BIT(INNER_SRC_PORT);
5916
5917         if (!spec->pdst)
5918                 *unused_tuple |= BIT(INNER_DST_PORT);
5919
5920         if (!spec->tos)
5921                 *unused_tuple |= BIT(INNER_IP_TOS);
5922
5923         return 0;
5924 }
5925
5926 static int hclge_fd_check_ip4_tuple(struct ethtool_usrip4_spec *spec,
5927                                     u32 *unused_tuple)
5928 {
5929         if (!spec || !unused_tuple)
5930                 return -EINVAL;
5931
5932         *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
5933                 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
5934
5935         if (!spec->ip4src)
5936                 *unused_tuple |= BIT(INNER_SRC_IP);
5937
5938         if (!spec->ip4dst)
5939                 *unused_tuple |= BIT(INNER_DST_IP);
5940
5941         if (!spec->tos)
5942                 *unused_tuple |= BIT(INNER_IP_TOS);
5943
5944         if (!spec->proto)
5945                 *unused_tuple |= BIT(INNER_IP_PROTO);
5946
5947         if (spec->l4_4_bytes)
5948                 return -EOPNOTSUPP;
5949
5950         if (spec->ip_ver != ETH_RX_NFC_IP4)
5951                 return -EOPNOTSUPP;
5952
5953         return 0;
5954 }
5955
5956 static int hclge_fd_check_tcpip6_tuple(struct ethtool_tcpip6_spec *spec,
5957                                        u32 *unused_tuple)
5958 {
5959         if (!spec || !unused_tuple)
5960                 return -EINVAL;
5961
5962         *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC);
5963
5964         /* check whether src/dst ip address used */
5965         if (ipv6_addr_any((struct in6_addr *)spec->ip6src))
5966                 *unused_tuple |= BIT(INNER_SRC_IP);
5967
5968         if (ipv6_addr_any((struct in6_addr *)spec->ip6dst))
5969                 *unused_tuple |= BIT(INNER_DST_IP);
5970
5971         if (!spec->psrc)
5972                 *unused_tuple |= BIT(INNER_SRC_PORT);
5973
5974         if (!spec->pdst)
5975                 *unused_tuple |= BIT(INNER_DST_PORT);
5976
5977         if (!spec->tclass)
5978                 *unused_tuple |= BIT(INNER_IP_TOS);
5979
5980         return 0;
5981 }
5982
5983 static int hclge_fd_check_ip6_tuple(struct ethtool_usrip6_spec *spec,
5984                                     u32 *unused_tuple)
5985 {
5986         if (!spec || !unused_tuple)
5987                 return -EINVAL;
5988
5989         *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
5990                         BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
5991
5992         /* check whether src/dst ip address used */
5993         if (ipv6_addr_any((struct in6_addr *)spec->ip6src))
5994                 *unused_tuple |= BIT(INNER_SRC_IP);
5995
5996         if (ipv6_addr_any((struct in6_addr *)spec->ip6dst))
5997                 *unused_tuple |= BIT(INNER_DST_IP);
5998
5999         if (!spec->l4_proto)
6000                 *unused_tuple |= BIT(INNER_IP_PROTO);
6001
6002         if (!spec->tclass)
6003                 *unused_tuple |= BIT(INNER_IP_TOS);
6004
6005         if (spec->l4_4_bytes)
6006                 return -EOPNOTSUPP;
6007
6008         return 0;
6009 }
6010
6011 static int hclge_fd_check_ether_tuple(struct ethhdr *spec, u32 *unused_tuple)
6012 {
6013         if (!spec || !unused_tuple)
6014                 return -EINVAL;
6015
6016         *unused_tuple |= BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) |
6017                 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT) |
6018                 BIT(INNER_IP_TOS) | BIT(INNER_IP_PROTO);
6019
6020         if (is_zero_ether_addr(spec->h_source))
6021                 *unused_tuple |= BIT(INNER_SRC_MAC);
6022
6023         if (is_zero_ether_addr(spec->h_dest))
6024                 *unused_tuple |= BIT(INNER_DST_MAC);
6025
6026         if (!spec->h_proto)
6027                 *unused_tuple |= BIT(INNER_ETH_TYPE);
6028
6029         return 0;
6030 }
6031
6032 static int hclge_fd_check_ext_tuple(struct hclge_dev *hdev,
6033                                     struct ethtool_rx_flow_spec *fs,
6034                                     u32 *unused_tuple)
6035 {
6036         if (fs->flow_type & FLOW_EXT) {
6037                 if (fs->h_ext.vlan_etype) {
6038                         dev_err(&hdev->pdev->dev, "vlan-etype is not supported!\n");
6039                         return -EOPNOTSUPP;
6040                 }
6041
6042                 if (!fs->h_ext.vlan_tci)
6043                         *unused_tuple |= BIT(INNER_VLAN_TAG_FST);
6044
6045                 if (fs->m_ext.vlan_tci &&
6046                     be16_to_cpu(fs->h_ext.vlan_tci) >= VLAN_N_VID) {
6047                         dev_err(&hdev->pdev->dev,
6048                                 "failed to config vlan_tci, invalid vlan_tci: %u, max is %d.\n",
6049                                 ntohs(fs->h_ext.vlan_tci), VLAN_N_VID - 1);
6050                         return -EINVAL;
6051                 }
6052         } else {
6053                 *unused_tuple |= BIT(INNER_VLAN_TAG_FST);
6054         }
6055
6056         if (fs->flow_type & FLOW_MAC_EXT) {
6057                 if (hdev->fd_cfg.fd_mode !=
6058                     HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) {
6059                         dev_err(&hdev->pdev->dev,
6060                                 "FLOW_MAC_EXT is not supported in current fd mode!\n");
6061                         return -EOPNOTSUPP;
6062                 }
6063
6064                 if (is_zero_ether_addr(fs->h_ext.h_dest))
6065                         *unused_tuple |= BIT(INNER_DST_MAC);
6066                 else
6067                         *unused_tuple &= ~BIT(INNER_DST_MAC);
6068         }
6069
6070         return 0;
6071 }
6072
6073 static int hclge_fd_get_user_def_layer(u32 flow_type, u32 *unused_tuple,
6074                                        struct hclge_fd_user_def_info *info)
6075 {
6076         switch (flow_type) {
6077         case ETHER_FLOW:
6078                 info->layer = HCLGE_FD_USER_DEF_L2;
6079                 *unused_tuple &= ~BIT(INNER_L2_RSV);
6080                 break;
6081         case IP_USER_FLOW:
6082         case IPV6_USER_FLOW:
6083                 info->layer = HCLGE_FD_USER_DEF_L3;
6084                 *unused_tuple &= ~BIT(INNER_L3_RSV);
6085                 break;
6086         case TCP_V4_FLOW:
6087         case UDP_V4_FLOW:
6088         case TCP_V6_FLOW:
6089         case UDP_V6_FLOW:
6090                 info->layer = HCLGE_FD_USER_DEF_L4;
6091                 *unused_tuple &= ~BIT(INNER_L4_RSV);
6092                 break;
6093         default:
6094                 return -EOPNOTSUPP;
6095         }
6096
6097         return 0;
6098 }
6099
6100 static bool hclge_fd_is_user_def_all_masked(struct ethtool_rx_flow_spec *fs)
6101 {
6102         return be32_to_cpu(fs->m_ext.data[1] | fs->m_ext.data[0]) == 0;
6103 }
6104
6105 static int hclge_fd_parse_user_def_field(struct hclge_dev *hdev,
6106                                          struct ethtool_rx_flow_spec *fs,
6107                                          u32 *unused_tuple,
6108                                          struct hclge_fd_user_def_info *info)
6109 {
6110         u32 tuple_active = hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1].tuple_active;
6111         u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT);
6112         u16 data, offset, data_mask, offset_mask;
6113         int ret;
6114
6115         info->layer = HCLGE_FD_USER_DEF_NONE;
6116         *unused_tuple |= HCLGE_FD_TUPLE_USER_DEF_TUPLES;
6117
6118         if (!(fs->flow_type & FLOW_EXT) || hclge_fd_is_user_def_all_masked(fs))
6119                 return 0;
6120
6121         /* user-def data from ethtool is 64 bit value, the bit0~15 is used
6122          * for data, and bit32~47 is used for offset.
6123          */
6124         data = be32_to_cpu(fs->h_ext.data[1]) & HCLGE_FD_USER_DEF_DATA;
6125         data_mask = be32_to_cpu(fs->m_ext.data[1]) & HCLGE_FD_USER_DEF_DATA;
6126         offset = be32_to_cpu(fs->h_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET;
6127         offset_mask = be32_to_cpu(fs->m_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET;
6128
6129         if (!(tuple_active & HCLGE_FD_TUPLE_USER_DEF_TUPLES)) {
6130                 dev_err(&hdev->pdev->dev, "user-def bytes are not supported\n");
6131                 return -EOPNOTSUPP;
6132         }
6133
6134         if (offset > HCLGE_FD_MAX_USER_DEF_OFFSET) {
6135                 dev_err(&hdev->pdev->dev,
6136                         "user-def offset[%u] should be no more than %u\n",
6137                         offset, HCLGE_FD_MAX_USER_DEF_OFFSET);
6138                 return -EINVAL;
6139         }
6140
6141         if (offset_mask != HCLGE_FD_USER_DEF_OFFSET_UNMASK) {
6142                 dev_err(&hdev->pdev->dev, "user-def offset can't be masked\n");
6143                 return -EINVAL;
6144         }
6145
6146         ret = hclge_fd_get_user_def_layer(flow_type, unused_tuple, info);
6147         if (ret) {
6148                 dev_err(&hdev->pdev->dev,
6149                         "unsupported flow type for user-def bytes, ret = %d\n",
6150                         ret);
6151                 return ret;
6152         }
6153
6154         info->data = data;
6155         info->data_mask = data_mask;
6156         info->offset = offset;
6157
6158         return 0;
6159 }
6160
6161 static int hclge_fd_check_spec(struct hclge_dev *hdev,
6162                                struct ethtool_rx_flow_spec *fs,
6163                                u32 *unused_tuple,
6164                                struct hclge_fd_user_def_info *info)
6165 {
6166         u32 flow_type;
6167         int ret;
6168
6169         if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) {
6170                 dev_err(&hdev->pdev->dev,
6171                         "failed to config fd rules, invalid rule location: %u, max is %u\n.",
6172                         fs->location,
6173                         hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1] - 1);
6174                 return -EINVAL;
6175         }
6176
6177         ret = hclge_fd_parse_user_def_field(hdev, fs, unused_tuple, info);
6178         if (ret)
6179                 return ret;
6180
6181         flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT);
6182         switch (flow_type) {
6183         case SCTP_V4_FLOW:
6184         case TCP_V4_FLOW:
6185         case UDP_V4_FLOW:
6186                 ret = hclge_fd_check_tcpip4_tuple(&fs->h_u.tcp_ip4_spec,
6187                                                   unused_tuple);
6188                 break;
6189         case IP_USER_FLOW:
6190                 ret = hclge_fd_check_ip4_tuple(&fs->h_u.usr_ip4_spec,
6191                                                unused_tuple);
6192                 break;
6193         case SCTP_V6_FLOW:
6194         case TCP_V6_FLOW:
6195         case UDP_V6_FLOW:
6196                 ret = hclge_fd_check_tcpip6_tuple(&fs->h_u.tcp_ip6_spec,
6197                                                   unused_tuple);
6198                 break;
6199         case IPV6_USER_FLOW:
6200                 ret = hclge_fd_check_ip6_tuple(&fs->h_u.usr_ip6_spec,
6201                                                unused_tuple);
6202                 break;
6203         case ETHER_FLOW:
6204                 if (hdev->fd_cfg.fd_mode !=
6205                         HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) {
6206                         dev_err(&hdev->pdev->dev,
6207                                 "ETHER_FLOW is not supported in current fd mode!\n");
6208                         return -EOPNOTSUPP;
6209                 }
6210
6211                 ret = hclge_fd_check_ether_tuple(&fs->h_u.ether_spec,
6212                                                  unused_tuple);
6213                 break;
6214         default:
6215                 dev_err(&hdev->pdev->dev,
6216                         "unsupported protocol type, protocol type = %#x\n",
6217                         flow_type);
6218                 return -EOPNOTSUPP;
6219         }
6220
6221         if (ret) {
6222                 dev_err(&hdev->pdev->dev,
6223                         "failed to check flow union tuple, ret = %d\n",
6224                         ret);
6225                 return ret;
6226         }
6227
6228         return hclge_fd_check_ext_tuple(hdev, fs, unused_tuple);
6229 }
6230
6231 static void hclge_fd_get_tcpip4_tuple(struct hclge_dev *hdev,
6232                                       struct ethtool_rx_flow_spec *fs,
6233                                       struct hclge_fd_rule *rule, u8 ip_proto)
6234 {
6235         rule->tuples.src_ip[IPV4_INDEX] =
6236                         be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4src);
6237         rule->tuples_mask.src_ip[IPV4_INDEX] =
6238                         be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4src);
6239
6240         rule->tuples.dst_ip[IPV4_INDEX] =
6241                         be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4dst);
6242         rule->tuples_mask.dst_ip[IPV4_INDEX] =
6243                         be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4dst);
6244
6245         rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc);
6246         rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.psrc);
6247
6248         rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst);
6249         rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.pdst);
6250
6251         rule->tuples.ip_tos = fs->h_u.tcp_ip4_spec.tos;
6252         rule->tuples_mask.ip_tos = fs->m_u.tcp_ip4_spec.tos;
6253
6254         rule->tuples.ether_proto = ETH_P_IP;
6255         rule->tuples_mask.ether_proto = 0xFFFF;
6256
6257         rule->tuples.ip_proto = ip_proto;
6258         rule->tuples_mask.ip_proto = 0xFF;
6259 }
6260
6261 static void hclge_fd_get_ip4_tuple(struct hclge_dev *hdev,
6262                                    struct ethtool_rx_flow_spec *fs,
6263                                    struct hclge_fd_rule *rule)
6264 {
6265         rule->tuples.src_ip[IPV4_INDEX] =
6266                         be32_to_cpu(fs->h_u.usr_ip4_spec.ip4src);
6267         rule->tuples_mask.src_ip[IPV4_INDEX] =
6268                         be32_to_cpu(fs->m_u.usr_ip4_spec.ip4src);
6269
6270         rule->tuples.dst_ip[IPV4_INDEX] =
6271                         be32_to_cpu(fs->h_u.usr_ip4_spec.ip4dst);
6272         rule->tuples_mask.dst_ip[IPV4_INDEX] =
6273                         be32_to_cpu(fs->m_u.usr_ip4_spec.ip4dst);
6274
6275         rule->tuples.ip_tos = fs->h_u.usr_ip4_spec.tos;
6276         rule->tuples_mask.ip_tos = fs->m_u.usr_ip4_spec.tos;
6277
6278         rule->tuples.ip_proto = fs->h_u.usr_ip4_spec.proto;
6279         rule->tuples_mask.ip_proto = fs->m_u.usr_ip4_spec.proto;
6280
6281         rule->tuples.ether_proto = ETH_P_IP;
6282         rule->tuples_mask.ether_proto = 0xFFFF;
6283 }
6284
6285 static void hclge_fd_get_tcpip6_tuple(struct hclge_dev *hdev,
6286                                       struct ethtool_rx_flow_spec *fs,
6287                                       struct hclge_fd_rule *rule, u8 ip_proto)
6288 {
6289         be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.tcp_ip6_spec.ip6src,
6290                           IPV6_SIZE);
6291         be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.tcp_ip6_spec.ip6src,
6292                           IPV6_SIZE);
6293
6294         be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.tcp_ip6_spec.ip6dst,
6295                           IPV6_SIZE);
6296         be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.tcp_ip6_spec.ip6dst,
6297                           IPV6_SIZE);
6298
6299         rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.psrc);
6300         rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.psrc);
6301
6302         rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.pdst);
6303         rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.pdst);
6304
6305         rule->tuples.ether_proto = ETH_P_IPV6;
6306         rule->tuples_mask.ether_proto = 0xFFFF;
6307
6308         rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass;
6309         rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass;
6310
6311         rule->tuples.ip_proto = ip_proto;
6312         rule->tuples_mask.ip_proto = 0xFF;
6313 }
6314
6315 static void hclge_fd_get_ip6_tuple(struct hclge_dev *hdev,
6316                                    struct ethtool_rx_flow_spec *fs,
6317                                    struct hclge_fd_rule *rule)
6318 {
6319         be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.usr_ip6_spec.ip6src,
6320                           IPV6_SIZE);
6321         be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.usr_ip6_spec.ip6src,
6322                           IPV6_SIZE);
6323
6324         be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.usr_ip6_spec.ip6dst,
6325                           IPV6_SIZE);
6326         be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.usr_ip6_spec.ip6dst,
6327                           IPV6_SIZE);
6328
6329         rule->tuples.ip_proto = fs->h_u.usr_ip6_spec.l4_proto;
6330         rule->tuples_mask.ip_proto = fs->m_u.usr_ip6_spec.l4_proto;
6331
6332         rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass;
6333         rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass;
6334
6335         rule->tuples.ether_proto = ETH_P_IPV6;
6336         rule->tuples_mask.ether_proto = 0xFFFF;
6337 }
6338
6339 static void hclge_fd_get_ether_tuple(struct hclge_dev *hdev,
6340                                      struct ethtool_rx_flow_spec *fs,
6341                                      struct hclge_fd_rule *rule)
6342 {
6343         ether_addr_copy(rule->tuples.src_mac, fs->h_u.ether_spec.h_source);
6344         ether_addr_copy(rule->tuples_mask.src_mac, fs->m_u.ether_spec.h_source);
6345
6346         ether_addr_copy(rule->tuples.dst_mac, fs->h_u.ether_spec.h_dest);
6347         ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_u.ether_spec.h_dest);
6348
6349         rule->tuples.ether_proto = be16_to_cpu(fs->h_u.ether_spec.h_proto);
6350         rule->tuples_mask.ether_proto = be16_to_cpu(fs->m_u.ether_spec.h_proto);
6351 }
6352
6353 static void hclge_fd_get_user_def_tuple(struct hclge_fd_user_def_info *info,
6354                                         struct hclge_fd_rule *rule)
6355 {
6356         switch (info->layer) {
6357         case HCLGE_FD_USER_DEF_L2:
6358                 rule->tuples.l2_user_def = info->data;
6359                 rule->tuples_mask.l2_user_def = info->data_mask;
6360                 break;
6361         case HCLGE_FD_USER_DEF_L3:
6362                 rule->tuples.l3_user_def = info->data;
6363                 rule->tuples_mask.l3_user_def = info->data_mask;
6364                 break;
6365         case HCLGE_FD_USER_DEF_L4:
6366                 rule->tuples.l4_user_def = (u32)info->data << 16;
6367                 rule->tuples_mask.l4_user_def = (u32)info->data_mask << 16;
6368                 break;
6369         default:
6370                 break;
6371         }
6372
6373         rule->ep.user_def = *info;
6374 }
6375
6376 static int hclge_fd_get_tuple(struct hclge_dev *hdev,
6377                               struct ethtool_rx_flow_spec *fs,
6378                               struct hclge_fd_rule *rule,
6379                               struct hclge_fd_user_def_info *info)
6380 {
6381         u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT);
6382
6383         switch (flow_type) {
6384         case SCTP_V4_FLOW:
6385                 hclge_fd_get_tcpip4_tuple(hdev, fs, rule, IPPROTO_SCTP);
6386                 break;
6387         case TCP_V4_FLOW:
6388                 hclge_fd_get_tcpip4_tuple(hdev, fs, rule, IPPROTO_TCP);
6389                 break;
6390         case UDP_V4_FLOW:
6391                 hclge_fd_get_tcpip4_tuple(hdev, fs, rule, IPPROTO_UDP);
6392                 break;
6393         case IP_USER_FLOW:
6394                 hclge_fd_get_ip4_tuple(hdev, fs, rule);
6395                 break;
6396         case SCTP_V6_FLOW:
6397                 hclge_fd_get_tcpip6_tuple(hdev, fs, rule, IPPROTO_SCTP);
6398                 break;
6399         case TCP_V6_FLOW:
6400                 hclge_fd_get_tcpip6_tuple(hdev, fs, rule, IPPROTO_TCP);
6401                 break;
6402         case UDP_V6_FLOW:
6403                 hclge_fd_get_tcpip6_tuple(hdev, fs, rule, IPPROTO_UDP);
6404                 break;
6405         case IPV6_USER_FLOW:
6406                 hclge_fd_get_ip6_tuple(hdev, fs, rule);
6407                 break;
6408         case ETHER_FLOW:
6409                 hclge_fd_get_ether_tuple(hdev, fs, rule);
6410                 break;
6411         default:
6412                 return -EOPNOTSUPP;
6413         }
6414
6415         if (fs->flow_type & FLOW_EXT) {
6416                 rule->tuples.vlan_tag1 = be16_to_cpu(fs->h_ext.vlan_tci);
6417                 rule->tuples_mask.vlan_tag1 = be16_to_cpu(fs->m_ext.vlan_tci);
6418                 hclge_fd_get_user_def_tuple(info, rule);
6419         }
6420
6421         if (fs->flow_type & FLOW_MAC_EXT) {
6422                 ether_addr_copy(rule->tuples.dst_mac, fs->h_ext.h_dest);
6423                 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_ext.h_dest);
6424         }
6425
6426         return 0;
6427 }
6428
6429 static int hclge_fd_config_rule(struct hclge_dev *hdev,
6430                                 struct hclge_fd_rule *rule)
6431 {
6432         int ret;
6433
6434         ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule);
6435         if (ret)
6436                 return ret;
6437
6438         return hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule);
6439 }
6440
6441 static int hclge_add_fd_entry_common(struct hclge_dev *hdev,
6442                                      struct hclge_fd_rule *rule)
6443 {
6444         int ret;
6445
6446         spin_lock_bh(&hdev->fd_rule_lock);
6447
6448         if (hdev->fd_active_type != rule->rule_type &&
6449             (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE ||
6450              hdev->fd_active_type == HCLGE_FD_EP_ACTIVE)) {
6451                 dev_err(&hdev->pdev->dev,
6452                         "mode conflict(new type %d, active type %d), please delete existent rules first\n",
6453                         rule->rule_type, hdev->fd_active_type);
6454                 spin_unlock_bh(&hdev->fd_rule_lock);
6455                 return -EINVAL;
6456         }
6457
6458         ret = hclge_fd_check_user_def_refcnt(hdev, rule);
6459         if (ret)
6460                 goto out;
6461
6462         ret = hclge_clear_arfs_rules(hdev);
6463         if (ret)
6464                 goto out;
6465
6466         ret = hclge_fd_config_rule(hdev, rule);
6467         if (ret)
6468                 goto out;
6469
6470         rule->state = HCLGE_FD_ACTIVE;
6471         hdev->fd_active_type = rule->rule_type;
6472         hclge_update_fd_list(hdev, rule->state, rule->location, rule);
6473
6474 out:
6475         spin_unlock_bh(&hdev->fd_rule_lock);
6476         return ret;
6477 }
6478
6479 static bool hclge_is_cls_flower_active(struct hnae3_handle *handle)
6480 {
6481         struct hclge_vport *vport = hclge_get_vport(handle);
6482         struct hclge_dev *hdev = vport->back;
6483
6484         return hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE;
6485 }
6486
6487 static int hclge_fd_parse_ring_cookie(struct hclge_dev *hdev, u64 ring_cookie,
6488                                       u16 *vport_id, u8 *action, u16 *queue_id)
6489 {
6490         struct hclge_vport *vport = hdev->vport;
6491
6492         if (ring_cookie == RX_CLS_FLOW_DISC) {
6493                 *action = HCLGE_FD_ACTION_DROP_PACKET;
6494         } else {
6495                 u32 ring = ethtool_get_flow_spec_ring(ring_cookie);
6496                 u8 vf = ethtool_get_flow_spec_ring_vf(ring_cookie);
6497                 u16 tqps;
6498
6499                 /* To keep consistent with user's configuration, minus 1 when
6500                  * printing 'vf', because vf id from ethtool is added 1 for vf.
6501                  */
6502                 if (vf > hdev->num_req_vfs) {
6503                         dev_err(&hdev->pdev->dev,
6504                                 "Error: vf id (%u) should be less than %u\n",
6505                                 vf - 1U, hdev->num_req_vfs);
6506                         return -EINVAL;
6507                 }
6508
6509                 *vport_id = vf ? hdev->vport[vf].vport_id : vport->vport_id;
6510                 tqps = hdev->vport[vf].nic.kinfo.num_tqps;
6511
6512                 if (ring >= tqps) {
6513                         dev_err(&hdev->pdev->dev,
6514                                 "Error: queue id (%u) > max tqp num (%u)\n",
6515                                 ring, tqps - 1U);
6516                         return -EINVAL;
6517                 }
6518
6519                 *action = HCLGE_FD_ACTION_SELECT_QUEUE;
6520                 *queue_id = ring;
6521         }
6522
6523         return 0;
6524 }
6525
6526 static int hclge_add_fd_entry(struct hnae3_handle *handle,
6527                               struct ethtool_rxnfc *cmd)
6528 {
6529         struct hclge_vport *vport = hclge_get_vport(handle);
6530         struct hclge_dev *hdev = vport->back;
6531         struct hclge_fd_user_def_info info;
6532         u16 dst_vport_id = 0, q_index = 0;
6533         struct ethtool_rx_flow_spec *fs;
6534         struct hclge_fd_rule *rule;
6535         u32 unused = 0;
6536         u8 action;
6537         int ret;
6538
6539         if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) {
6540                 dev_err(&hdev->pdev->dev,
6541                         "flow table director is not supported\n");
6542                 return -EOPNOTSUPP;
6543         }
6544
6545         if (!hdev->fd_en) {
6546                 dev_err(&hdev->pdev->dev,
6547                         "please enable flow director first\n");
6548                 return -EOPNOTSUPP;
6549         }
6550
6551         fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
6552
6553         ret = hclge_fd_check_spec(hdev, fs, &unused, &info);
6554         if (ret)
6555                 return ret;
6556
6557         ret = hclge_fd_parse_ring_cookie(hdev, fs->ring_cookie, &dst_vport_id,
6558                                          &action, &q_index);
6559         if (ret)
6560                 return ret;
6561
6562         rule = kzalloc(sizeof(*rule), GFP_KERNEL);
6563         if (!rule)
6564                 return -ENOMEM;
6565
6566         ret = hclge_fd_get_tuple(hdev, fs, rule, &info);
6567         if (ret) {
6568                 kfree(rule);
6569                 return ret;
6570         }
6571
6572         rule->flow_type = fs->flow_type;
6573         rule->location = fs->location;
6574         rule->unused_tuple = unused;
6575         rule->vf_id = dst_vport_id;
6576         rule->queue_id = q_index;
6577         rule->action = action;
6578         rule->rule_type = HCLGE_FD_EP_ACTIVE;
6579
6580         ret = hclge_add_fd_entry_common(hdev, rule);
6581         if (ret)
6582                 kfree(rule);
6583
6584         return ret;
6585 }
6586
6587 static int hclge_del_fd_entry(struct hnae3_handle *handle,
6588                               struct ethtool_rxnfc *cmd)
6589 {
6590         struct hclge_vport *vport = hclge_get_vport(handle);
6591         struct hclge_dev *hdev = vport->back;
6592         struct ethtool_rx_flow_spec *fs;
6593         int ret;
6594
6595         if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
6596                 return -EOPNOTSUPP;
6597
6598         fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
6599
6600         if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1])
6601                 return -EINVAL;
6602
6603         spin_lock_bh(&hdev->fd_rule_lock);
6604         if (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE ||
6605             !test_bit(fs->location, hdev->fd_bmap)) {
6606                 dev_err(&hdev->pdev->dev,
6607                         "Delete fail, rule %u is inexistent\n", fs->location);
6608                 spin_unlock_bh(&hdev->fd_rule_lock);
6609                 return -ENOENT;
6610         }
6611
6612         ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, fs->location,
6613                                    NULL, false);
6614         if (ret)
6615                 goto out;
6616
6617         hclge_update_fd_list(hdev, HCLGE_FD_DELETED, fs->location, NULL);
6618
6619 out:
6620         spin_unlock_bh(&hdev->fd_rule_lock);
6621         return ret;
6622 }
6623
6624 static void hclge_clear_fd_rules_in_list(struct hclge_dev *hdev,
6625                                          bool clear_list)
6626 {
6627         struct hclge_fd_rule *rule;
6628         struct hlist_node *node;
6629         u16 location;
6630
6631         if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
6632                 return;
6633
6634         spin_lock_bh(&hdev->fd_rule_lock);
6635
6636         for_each_set_bit(location, hdev->fd_bmap,
6637                          hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1])
6638                 hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, location,
6639                                      NULL, false);
6640
6641         if (clear_list) {
6642                 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list,
6643                                           rule_node) {
6644                         hlist_del(&rule->rule_node);
6645                         kfree(rule);
6646                 }
6647                 hdev->fd_active_type = HCLGE_FD_RULE_NONE;
6648                 hdev->hclge_fd_rule_num = 0;
6649                 bitmap_zero(hdev->fd_bmap,
6650                             hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]);
6651         }
6652
6653         spin_unlock_bh(&hdev->fd_rule_lock);
6654 }
6655
6656 static void hclge_del_all_fd_entries(struct hclge_dev *hdev)
6657 {
6658         hclge_clear_fd_rules_in_list(hdev, true);
6659         hclge_fd_disable_user_def(hdev);
6660 }
6661
6662 static int hclge_restore_fd_entries(struct hnae3_handle *handle)
6663 {
6664         struct hclge_vport *vport = hclge_get_vport(handle);
6665         struct hclge_dev *hdev = vport->back;
6666         struct hclge_fd_rule *rule;
6667         struct hlist_node *node;
6668
6669         /* Return ok here, because reset error handling will check this
6670          * return value. If error is returned here, the reset process will
6671          * fail.
6672          */
6673         if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
6674                 return 0;
6675
6676         /* if fd is disabled, should not restore it when reset */
6677         if (!hdev->fd_en)
6678                 return 0;
6679
6680         spin_lock_bh(&hdev->fd_rule_lock);
6681         hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
6682                 if (rule->state == HCLGE_FD_ACTIVE)
6683                         rule->state = HCLGE_FD_TO_ADD;
6684         }
6685         spin_unlock_bh(&hdev->fd_rule_lock);
6686         set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state);
6687
6688         return 0;
6689 }
6690
6691 static int hclge_get_fd_rule_cnt(struct hnae3_handle *handle,
6692                                  struct ethtool_rxnfc *cmd)
6693 {
6694         struct hclge_vport *vport = hclge_get_vport(handle);
6695         struct hclge_dev *hdev = vport->back;
6696
6697         if (!hnae3_ae_dev_fd_supported(hdev->ae_dev) || hclge_is_cls_flower_active(handle))
6698                 return -EOPNOTSUPP;
6699
6700         cmd->rule_cnt = hdev->hclge_fd_rule_num;
6701         cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1];
6702
6703         return 0;
6704 }
6705
6706 static void hclge_fd_get_tcpip4_info(struct hclge_fd_rule *rule,
6707                                      struct ethtool_tcpip4_spec *spec,
6708                                      struct ethtool_tcpip4_spec *spec_mask)
6709 {
6710         spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]);
6711         spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ?
6712                         0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]);
6713
6714         spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]);
6715         spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ?
6716                         0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]);
6717
6718         spec->psrc = cpu_to_be16(rule->tuples.src_port);
6719         spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ?
6720                         0 : cpu_to_be16(rule->tuples_mask.src_port);
6721
6722         spec->pdst = cpu_to_be16(rule->tuples.dst_port);
6723         spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ?
6724                         0 : cpu_to_be16(rule->tuples_mask.dst_port);
6725
6726         spec->tos = rule->tuples.ip_tos;
6727         spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ?
6728                         0 : rule->tuples_mask.ip_tos;
6729 }
6730
6731 static void hclge_fd_get_ip4_info(struct hclge_fd_rule *rule,
6732                                   struct ethtool_usrip4_spec *spec,
6733                                   struct ethtool_usrip4_spec *spec_mask)
6734 {
6735         spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]);
6736         spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ?
6737                         0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]);
6738
6739         spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]);
6740         spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ?
6741                         0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]);
6742
6743         spec->tos = rule->tuples.ip_tos;
6744         spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ?
6745                         0 : rule->tuples_mask.ip_tos;
6746
6747         spec->proto = rule->tuples.ip_proto;
6748         spec_mask->proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ?
6749                         0 : rule->tuples_mask.ip_proto;
6750
6751         spec->ip_ver = ETH_RX_NFC_IP4;
6752 }
6753
6754 static void hclge_fd_get_tcpip6_info(struct hclge_fd_rule *rule,
6755                                      struct ethtool_tcpip6_spec *spec,
6756                                      struct ethtool_tcpip6_spec *spec_mask)
6757 {
6758         cpu_to_be32_array(spec->ip6src,
6759                           rule->tuples.src_ip, IPV6_SIZE);
6760         cpu_to_be32_array(spec->ip6dst,
6761                           rule->tuples.dst_ip, IPV6_SIZE);
6762         if (rule->unused_tuple & BIT(INNER_SRC_IP))
6763                 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src));
6764         else
6765                 cpu_to_be32_array(spec_mask->ip6src, rule->tuples_mask.src_ip,
6766                                   IPV6_SIZE);
6767
6768         if (rule->unused_tuple & BIT(INNER_DST_IP))
6769                 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst));
6770         else
6771                 cpu_to_be32_array(spec_mask->ip6dst, rule->tuples_mask.dst_ip,
6772                                   IPV6_SIZE);
6773
6774         spec->tclass = rule->tuples.ip_tos;
6775         spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ?
6776                         0 : rule->tuples_mask.ip_tos;
6777
6778         spec->psrc = cpu_to_be16(rule->tuples.src_port);
6779         spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ?
6780                         0 : cpu_to_be16(rule->tuples_mask.src_port);
6781
6782         spec->pdst = cpu_to_be16(rule->tuples.dst_port);
6783         spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ?
6784                         0 : cpu_to_be16(rule->tuples_mask.dst_port);
6785 }
6786
6787 static void hclge_fd_get_ip6_info(struct hclge_fd_rule *rule,
6788                                   struct ethtool_usrip6_spec *spec,
6789                                   struct ethtool_usrip6_spec *spec_mask)
6790 {
6791         cpu_to_be32_array(spec->ip6src, rule->tuples.src_ip, IPV6_SIZE);
6792         cpu_to_be32_array(spec->ip6dst, rule->tuples.dst_ip, IPV6_SIZE);
6793         if (rule->unused_tuple & BIT(INNER_SRC_IP))
6794                 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src));
6795         else
6796                 cpu_to_be32_array(spec_mask->ip6src,
6797                                   rule->tuples_mask.src_ip, IPV6_SIZE);
6798
6799         if (rule->unused_tuple & BIT(INNER_DST_IP))
6800                 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst));
6801         else
6802                 cpu_to_be32_array(spec_mask->ip6dst,
6803                                   rule->tuples_mask.dst_ip, IPV6_SIZE);
6804
6805         spec->tclass = rule->tuples.ip_tos;
6806         spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ?
6807                         0 : rule->tuples_mask.ip_tos;
6808
6809         spec->l4_proto = rule->tuples.ip_proto;
6810         spec_mask->l4_proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ?
6811                         0 : rule->tuples_mask.ip_proto;
6812 }
6813
6814 static void hclge_fd_get_ether_info(struct hclge_fd_rule *rule,
6815                                     struct ethhdr *spec,
6816                                     struct ethhdr *spec_mask)
6817 {
6818         ether_addr_copy(spec->h_source, rule->tuples.src_mac);
6819         ether_addr_copy(spec->h_dest, rule->tuples.dst_mac);
6820
6821         if (rule->unused_tuple & BIT(INNER_SRC_MAC))
6822                 eth_zero_addr(spec_mask->h_source);
6823         else
6824                 ether_addr_copy(spec_mask->h_source, rule->tuples_mask.src_mac);
6825
6826         if (rule->unused_tuple & BIT(INNER_DST_MAC))
6827                 eth_zero_addr(spec_mask->h_dest);
6828         else
6829                 ether_addr_copy(spec_mask->h_dest, rule->tuples_mask.dst_mac);
6830
6831         spec->h_proto = cpu_to_be16(rule->tuples.ether_proto);
6832         spec_mask->h_proto = rule->unused_tuple & BIT(INNER_ETH_TYPE) ?
6833                         0 : cpu_to_be16(rule->tuples_mask.ether_proto);
6834 }
6835
6836 static void hclge_fd_get_user_def_info(struct ethtool_rx_flow_spec *fs,
6837                                        struct hclge_fd_rule *rule)
6838 {
6839         if ((rule->unused_tuple & HCLGE_FD_TUPLE_USER_DEF_TUPLES) ==
6840             HCLGE_FD_TUPLE_USER_DEF_TUPLES) {
6841                 fs->h_ext.data[0] = 0;
6842                 fs->h_ext.data[1] = 0;
6843                 fs->m_ext.data[0] = 0;
6844                 fs->m_ext.data[1] = 0;
6845         } else {
6846                 fs->h_ext.data[0] = cpu_to_be32(rule->ep.user_def.offset);
6847                 fs->h_ext.data[1] = cpu_to_be32(rule->ep.user_def.data);
6848                 fs->m_ext.data[0] =
6849                                 cpu_to_be32(HCLGE_FD_USER_DEF_OFFSET_UNMASK);
6850                 fs->m_ext.data[1] = cpu_to_be32(rule->ep.user_def.data_mask);
6851         }
6852 }
6853
6854 static void hclge_fd_get_ext_info(struct ethtool_rx_flow_spec *fs,
6855                                   struct hclge_fd_rule *rule)
6856 {
6857         if (fs->flow_type & FLOW_EXT) {
6858                 fs->h_ext.vlan_tci = cpu_to_be16(rule->tuples.vlan_tag1);
6859                 fs->m_ext.vlan_tci =
6860                                 rule->unused_tuple & BIT(INNER_VLAN_TAG_FST) ?
6861                                 0 : cpu_to_be16(rule->tuples_mask.vlan_tag1);
6862
6863                 hclge_fd_get_user_def_info(fs, rule);
6864         }
6865
6866         if (fs->flow_type & FLOW_MAC_EXT) {
6867                 ether_addr_copy(fs->h_ext.h_dest, rule->tuples.dst_mac);
6868                 if (rule->unused_tuple & BIT(INNER_DST_MAC))
6869                         eth_zero_addr(fs->m_u.ether_spec.h_dest);
6870                 else
6871                         ether_addr_copy(fs->m_u.ether_spec.h_dest,
6872                                         rule->tuples_mask.dst_mac);
6873         }
6874 }
6875
6876 static struct hclge_fd_rule *hclge_get_fd_rule(struct hclge_dev *hdev,
6877                                                u16 location)
6878 {
6879         struct hclge_fd_rule *rule = NULL;
6880         struct hlist_node *node2;
6881
6882         hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) {
6883                 if (rule->location == location)
6884                         return rule;
6885                 else if (rule->location > location)
6886                         return NULL;
6887         }
6888
6889         return NULL;
6890 }
6891
6892 static void hclge_fd_get_ring_cookie(struct ethtool_rx_flow_spec *fs,
6893                                      struct hclge_fd_rule *rule)
6894 {
6895         if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) {
6896                 fs->ring_cookie = RX_CLS_FLOW_DISC;
6897         } else {
6898                 u64 vf_id;
6899
6900                 fs->ring_cookie = rule->queue_id;
6901                 vf_id = rule->vf_id;
6902                 vf_id <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
6903                 fs->ring_cookie |= vf_id;
6904         }
6905 }
6906
6907 static int hclge_get_fd_rule_info(struct hnae3_handle *handle,
6908                                   struct ethtool_rxnfc *cmd)
6909 {
6910         struct hclge_vport *vport = hclge_get_vport(handle);
6911         struct hclge_fd_rule *rule = NULL;
6912         struct hclge_dev *hdev = vport->back;
6913         struct ethtool_rx_flow_spec *fs;
6914
6915         if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
6916                 return -EOPNOTSUPP;
6917
6918         fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
6919
6920         spin_lock_bh(&hdev->fd_rule_lock);
6921
6922         rule = hclge_get_fd_rule(hdev, fs->location);
6923         if (!rule) {
6924                 spin_unlock_bh(&hdev->fd_rule_lock);
6925                 return -ENOENT;
6926         }
6927
6928         fs->flow_type = rule->flow_type;
6929         switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
6930         case SCTP_V4_FLOW:
6931         case TCP_V4_FLOW:
6932         case UDP_V4_FLOW:
6933                 hclge_fd_get_tcpip4_info(rule, &fs->h_u.tcp_ip4_spec,
6934                                          &fs->m_u.tcp_ip4_spec);
6935                 break;
6936         case IP_USER_FLOW:
6937                 hclge_fd_get_ip4_info(rule, &fs->h_u.usr_ip4_spec,
6938                                       &fs->m_u.usr_ip4_spec);
6939                 break;
6940         case SCTP_V6_FLOW:
6941         case TCP_V6_FLOW:
6942         case UDP_V6_FLOW:
6943                 hclge_fd_get_tcpip6_info(rule, &fs->h_u.tcp_ip6_spec,
6944                                          &fs->m_u.tcp_ip6_spec);
6945                 break;
6946         case IPV6_USER_FLOW:
6947                 hclge_fd_get_ip6_info(rule, &fs->h_u.usr_ip6_spec,
6948                                       &fs->m_u.usr_ip6_spec);
6949                 break;
6950         /* The flow type of fd rule has been checked before adding in to rule
6951          * list. As other flow types have been handled, it must be ETHER_FLOW
6952          * for the default case
6953          */
6954         default:
6955                 hclge_fd_get_ether_info(rule, &fs->h_u.ether_spec,
6956                                         &fs->m_u.ether_spec);
6957                 break;
6958         }
6959
6960         hclge_fd_get_ext_info(fs, rule);
6961
6962         hclge_fd_get_ring_cookie(fs, rule);
6963
6964         spin_unlock_bh(&hdev->fd_rule_lock);
6965
6966         return 0;
6967 }
6968
6969 static int hclge_get_all_rules(struct hnae3_handle *handle,
6970                                struct ethtool_rxnfc *cmd, u32 *rule_locs)
6971 {
6972         struct hclge_vport *vport = hclge_get_vport(handle);
6973         struct hclge_dev *hdev = vport->back;
6974         struct hclge_fd_rule *rule;
6975         struct hlist_node *node2;
6976         int cnt = 0;
6977
6978         if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
6979                 return -EOPNOTSUPP;
6980
6981         cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1];
6982
6983         spin_lock_bh(&hdev->fd_rule_lock);
6984         hlist_for_each_entry_safe(rule, node2,
6985                                   &hdev->fd_rule_list, rule_node) {
6986                 if (cnt == cmd->rule_cnt) {
6987                         spin_unlock_bh(&hdev->fd_rule_lock);
6988                         return -EMSGSIZE;
6989                 }
6990
6991                 if (rule->state == HCLGE_FD_TO_DEL)
6992                         continue;
6993
6994                 rule_locs[cnt] = rule->location;
6995                 cnt++;
6996         }
6997
6998         spin_unlock_bh(&hdev->fd_rule_lock);
6999
7000         cmd->rule_cnt = cnt;
7001
7002         return 0;
7003 }
7004
7005 static void hclge_fd_get_flow_tuples(const struct flow_keys *fkeys,
7006                                      struct hclge_fd_rule_tuples *tuples)
7007 {
7008 #define flow_ip6_src fkeys->addrs.v6addrs.src.in6_u.u6_addr32
7009 #define flow_ip6_dst fkeys->addrs.v6addrs.dst.in6_u.u6_addr32
7010
7011         tuples->ether_proto = be16_to_cpu(fkeys->basic.n_proto);
7012         tuples->ip_proto = fkeys->basic.ip_proto;
7013         tuples->dst_port = be16_to_cpu(fkeys->ports.dst);
7014
7015         if (fkeys->basic.n_proto == htons(ETH_P_IP)) {
7016                 tuples->src_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.src);
7017                 tuples->dst_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.dst);
7018         } else {
7019                 int i;
7020
7021                 for (i = 0; i < IPV6_SIZE; i++) {
7022                         tuples->src_ip[i] = be32_to_cpu(flow_ip6_src[i]);
7023                         tuples->dst_ip[i] = be32_to_cpu(flow_ip6_dst[i]);
7024                 }
7025         }
7026 }
7027
7028 /* traverse all rules, check whether an existed rule has the same tuples */
7029 static struct hclge_fd_rule *
7030 hclge_fd_search_flow_keys(struct hclge_dev *hdev,
7031                           const struct hclge_fd_rule_tuples *tuples)
7032 {
7033         struct hclge_fd_rule *rule = NULL;
7034         struct hlist_node *node;
7035
7036         hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
7037                 if (!memcmp(tuples, &rule->tuples, sizeof(*tuples)))
7038                         return rule;
7039         }
7040
7041         return NULL;
7042 }
7043
7044 static void hclge_fd_build_arfs_rule(const struct hclge_fd_rule_tuples *tuples,
7045                                      struct hclge_fd_rule *rule)
7046 {
7047         rule->unused_tuple = BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
7048                              BIT(INNER_VLAN_TAG_FST) | BIT(INNER_IP_TOS) |
7049                              BIT(INNER_SRC_PORT);
7050         rule->action = 0;
7051         rule->vf_id = 0;
7052         rule->rule_type = HCLGE_FD_ARFS_ACTIVE;
7053         rule->state = HCLGE_FD_TO_ADD;
7054         if (tuples->ether_proto == ETH_P_IP) {
7055                 if (tuples->ip_proto == IPPROTO_TCP)
7056                         rule->flow_type = TCP_V4_FLOW;
7057                 else
7058                         rule->flow_type = UDP_V4_FLOW;
7059         } else {
7060                 if (tuples->ip_proto == IPPROTO_TCP)
7061                         rule->flow_type = TCP_V6_FLOW;
7062                 else
7063                         rule->flow_type = UDP_V6_FLOW;
7064         }
7065         memcpy(&rule->tuples, tuples, sizeof(rule->tuples));
7066         memset(&rule->tuples_mask, 0xFF, sizeof(rule->tuples_mask));
7067 }
7068
7069 static int hclge_add_fd_entry_by_arfs(struct hnae3_handle *handle, u16 queue_id,
7070                                       u16 flow_id, struct flow_keys *fkeys)
7071 {
7072         struct hclge_vport *vport = hclge_get_vport(handle);
7073         struct hclge_fd_rule_tuples new_tuples = {};
7074         struct hclge_dev *hdev = vport->back;
7075         struct hclge_fd_rule *rule;
7076         u16 bit_id;
7077
7078         if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
7079                 return -EOPNOTSUPP;
7080
7081         /* when there is already fd rule existed add by user,
7082          * arfs should not work
7083          */
7084         spin_lock_bh(&hdev->fd_rule_lock);
7085         if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE &&
7086             hdev->fd_active_type != HCLGE_FD_RULE_NONE) {
7087                 spin_unlock_bh(&hdev->fd_rule_lock);
7088                 return -EOPNOTSUPP;
7089         }
7090
7091         hclge_fd_get_flow_tuples(fkeys, &new_tuples);
7092
7093         /* check is there flow director filter existed for this flow,
7094          * if not, create a new filter for it;
7095          * if filter exist with different queue id, modify the filter;
7096          * if filter exist with same queue id, do nothing
7097          */
7098         rule = hclge_fd_search_flow_keys(hdev, &new_tuples);
7099         if (!rule) {
7100                 bit_id = find_first_zero_bit(hdev->fd_bmap, MAX_FD_FILTER_NUM);
7101                 if (bit_id >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) {
7102                         spin_unlock_bh(&hdev->fd_rule_lock);
7103                         return -ENOSPC;
7104                 }
7105
7106                 rule = kzalloc(sizeof(*rule), GFP_ATOMIC);
7107                 if (!rule) {
7108                         spin_unlock_bh(&hdev->fd_rule_lock);
7109                         return -ENOMEM;
7110                 }
7111
7112                 rule->location = bit_id;
7113                 rule->arfs.flow_id = flow_id;
7114                 rule->queue_id = queue_id;
7115                 hclge_fd_build_arfs_rule(&new_tuples, rule);
7116                 hclge_update_fd_list(hdev, rule->state, rule->location, rule);
7117                 hdev->fd_active_type = HCLGE_FD_ARFS_ACTIVE;
7118         } else if (rule->queue_id != queue_id) {
7119                 rule->queue_id = queue_id;
7120                 rule->state = HCLGE_FD_TO_ADD;
7121                 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state);
7122                 hclge_task_schedule(hdev, 0);
7123         }
7124         spin_unlock_bh(&hdev->fd_rule_lock);
7125         return rule->location;
7126 }
7127
7128 static void hclge_rfs_filter_expire(struct hclge_dev *hdev)
7129 {
7130 #ifdef CONFIG_RFS_ACCEL
7131         struct hnae3_handle *handle = &hdev->vport[0].nic;
7132         struct hclge_fd_rule *rule;
7133         struct hlist_node *node;
7134
7135         spin_lock_bh(&hdev->fd_rule_lock);
7136         if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) {
7137                 spin_unlock_bh(&hdev->fd_rule_lock);
7138                 return;
7139         }
7140         hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
7141                 if (rule->state != HCLGE_FD_ACTIVE)
7142                         continue;
7143                 if (rps_may_expire_flow(handle->netdev, rule->queue_id,
7144                                         rule->arfs.flow_id, rule->location)) {
7145                         rule->state = HCLGE_FD_TO_DEL;
7146                         set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state);
7147                 }
7148         }
7149         spin_unlock_bh(&hdev->fd_rule_lock);
7150 #endif
7151 }
7152
7153 /* make sure being called after lock up with fd_rule_lock */
7154 static int hclge_clear_arfs_rules(struct hclge_dev *hdev)
7155 {
7156 #ifdef CONFIG_RFS_ACCEL
7157         struct hclge_fd_rule *rule;
7158         struct hlist_node *node;
7159         int ret;
7160
7161         if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE)
7162                 return 0;
7163
7164         hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
7165                 switch (rule->state) {
7166                 case HCLGE_FD_TO_DEL:
7167                 case HCLGE_FD_ACTIVE:
7168                         ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
7169                                                    rule->location, NULL, false);
7170                         if (ret)
7171                                 return ret;
7172                         fallthrough;
7173                 case HCLGE_FD_TO_ADD:
7174                         hclge_fd_dec_rule_cnt(hdev, rule->location);
7175                         hlist_del(&rule->rule_node);
7176                         kfree(rule);
7177                         break;
7178                 default:
7179                         break;
7180                 }
7181         }
7182         hclge_sync_fd_state(hdev);
7183
7184 #endif
7185         return 0;
7186 }
7187
7188 static void hclge_get_cls_key_basic(const struct flow_rule *flow,
7189                                     struct hclge_fd_rule *rule)
7190 {
7191         if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_BASIC)) {
7192                 struct flow_match_basic match;
7193                 u16 ethtype_key, ethtype_mask;
7194
7195                 flow_rule_match_basic(flow, &match);
7196                 ethtype_key = ntohs(match.key->n_proto);
7197                 ethtype_mask = ntohs(match.mask->n_proto);
7198
7199                 if (ethtype_key == ETH_P_ALL) {
7200                         ethtype_key = 0;
7201                         ethtype_mask = 0;
7202                 }
7203                 rule->tuples.ether_proto = ethtype_key;
7204                 rule->tuples_mask.ether_proto = ethtype_mask;
7205                 rule->tuples.ip_proto = match.key->ip_proto;
7206                 rule->tuples_mask.ip_proto = match.mask->ip_proto;
7207         } else {
7208                 rule->unused_tuple |= BIT(INNER_IP_PROTO);
7209                 rule->unused_tuple |= BIT(INNER_ETH_TYPE);
7210         }
7211 }
7212
7213 static void hclge_get_cls_key_mac(const struct flow_rule *flow,
7214                                   struct hclge_fd_rule *rule)
7215 {
7216         if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
7217                 struct flow_match_eth_addrs match;
7218
7219                 flow_rule_match_eth_addrs(flow, &match);
7220                 ether_addr_copy(rule->tuples.dst_mac, match.key->dst);
7221                 ether_addr_copy(rule->tuples_mask.dst_mac, match.mask->dst);
7222                 ether_addr_copy(rule->tuples.src_mac, match.key->src);
7223                 ether_addr_copy(rule->tuples_mask.src_mac, match.mask->src);
7224         } else {
7225                 rule->unused_tuple |= BIT(INNER_DST_MAC);
7226                 rule->unused_tuple |= BIT(INNER_SRC_MAC);
7227         }
7228 }
7229
7230 static void hclge_get_cls_key_vlan(const struct flow_rule *flow,
7231                                    struct hclge_fd_rule *rule)
7232 {
7233         if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_VLAN)) {
7234                 struct flow_match_vlan match;
7235
7236                 flow_rule_match_vlan(flow, &match);
7237                 rule->tuples.vlan_tag1 = match.key->vlan_id |
7238                                 (match.key->vlan_priority << VLAN_PRIO_SHIFT);
7239                 rule->tuples_mask.vlan_tag1 = match.mask->vlan_id |
7240                                 (match.mask->vlan_priority << VLAN_PRIO_SHIFT);
7241         } else {
7242                 rule->unused_tuple |= BIT(INNER_VLAN_TAG_FST);
7243         }
7244 }
7245
7246 static void hclge_get_cls_key_ip(const struct flow_rule *flow,
7247                                  struct hclge_fd_rule *rule)
7248 {
7249         u16 addr_type = 0;
7250
7251         if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_CONTROL)) {
7252                 struct flow_match_control match;
7253
7254                 flow_rule_match_control(flow, &match);
7255                 addr_type = match.key->addr_type;
7256         }
7257
7258         if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
7259                 struct flow_match_ipv4_addrs match;
7260
7261                 flow_rule_match_ipv4_addrs(flow, &match);
7262                 rule->tuples.src_ip[IPV4_INDEX] = be32_to_cpu(match.key->src);
7263                 rule->tuples_mask.src_ip[IPV4_INDEX] =
7264                                                 be32_to_cpu(match.mask->src);
7265                 rule->tuples.dst_ip[IPV4_INDEX] = be32_to_cpu(match.key->dst);
7266                 rule->tuples_mask.dst_ip[IPV4_INDEX] =
7267                                                 be32_to_cpu(match.mask->dst);
7268         } else if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
7269                 struct flow_match_ipv6_addrs match;
7270
7271                 flow_rule_match_ipv6_addrs(flow, &match);
7272                 be32_to_cpu_array(rule->tuples.src_ip, match.key->src.s6_addr32,
7273                                   IPV6_SIZE);
7274                 be32_to_cpu_array(rule->tuples_mask.src_ip,
7275                                   match.mask->src.s6_addr32, IPV6_SIZE);
7276                 be32_to_cpu_array(rule->tuples.dst_ip, match.key->dst.s6_addr32,
7277                                   IPV6_SIZE);
7278                 be32_to_cpu_array(rule->tuples_mask.dst_ip,
7279                                   match.mask->dst.s6_addr32, IPV6_SIZE);
7280         } else {
7281                 rule->unused_tuple |= BIT(INNER_SRC_IP);
7282                 rule->unused_tuple |= BIT(INNER_DST_IP);
7283         }
7284 }
7285
7286 static void hclge_get_cls_key_port(const struct flow_rule *flow,
7287                                    struct hclge_fd_rule *rule)
7288 {
7289         if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_PORTS)) {
7290                 struct flow_match_ports match;
7291
7292                 flow_rule_match_ports(flow, &match);
7293
7294                 rule->tuples.src_port = be16_to_cpu(match.key->src);
7295                 rule->tuples_mask.src_port = be16_to_cpu(match.mask->src);
7296                 rule->tuples.dst_port = be16_to_cpu(match.key->dst);
7297                 rule->tuples_mask.dst_port = be16_to_cpu(match.mask->dst);
7298         } else {
7299                 rule->unused_tuple |= BIT(INNER_SRC_PORT);
7300                 rule->unused_tuple |= BIT(INNER_DST_PORT);
7301         }
7302 }
7303
7304 static int hclge_parse_cls_flower(struct hclge_dev *hdev,
7305                                   struct flow_cls_offload *cls_flower,
7306                                   struct hclge_fd_rule *rule)
7307 {
7308         struct flow_rule *flow = flow_cls_offload_flow_rule(cls_flower);
7309         struct flow_dissector *dissector = flow->match.dissector;
7310
7311         if (dissector->used_keys &
7312             ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
7313               BIT(FLOW_DISSECTOR_KEY_BASIC) |
7314               BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
7315               BIT(FLOW_DISSECTOR_KEY_VLAN) |
7316               BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
7317               BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
7318               BIT(FLOW_DISSECTOR_KEY_PORTS))) {
7319                 dev_err(&hdev->pdev->dev, "unsupported key set: %#x\n",
7320                         dissector->used_keys);
7321                 return -EOPNOTSUPP;
7322         }
7323
7324         hclge_get_cls_key_basic(flow, rule);
7325         hclge_get_cls_key_mac(flow, rule);
7326         hclge_get_cls_key_vlan(flow, rule);
7327         hclge_get_cls_key_ip(flow, rule);
7328         hclge_get_cls_key_port(flow, rule);
7329
7330         return 0;
7331 }
7332
7333 static int hclge_check_cls_flower(struct hclge_dev *hdev,
7334                                   struct flow_cls_offload *cls_flower, int tc)
7335 {
7336         u32 prio = cls_flower->common.prio;
7337
7338         if (tc < 0 || tc > hdev->tc_max) {
7339                 dev_err(&hdev->pdev->dev, "invalid traffic class\n");
7340                 return -EINVAL;
7341         }
7342
7343         if (prio == 0 ||
7344             prio > hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) {
7345                 dev_err(&hdev->pdev->dev,
7346                         "prio %u should be in range[1, %u]\n",
7347                         prio, hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]);
7348                 return -EINVAL;
7349         }
7350
7351         if (test_bit(prio - 1, hdev->fd_bmap)) {
7352                 dev_err(&hdev->pdev->dev, "prio %u is already used\n", prio);
7353                 return -EINVAL;
7354         }
7355         return 0;
7356 }
7357
7358 static int hclge_add_cls_flower(struct hnae3_handle *handle,
7359                                 struct flow_cls_offload *cls_flower,
7360                                 int tc)
7361 {
7362         struct hclge_vport *vport = hclge_get_vport(handle);
7363         struct hclge_dev *hdev = vport->back;
7364         struct hclge_fd_rule *rule;
7365         int ret;
7366
7367         if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) {
7368                 dev_err(&hdev->pdev->dev,
7369                         "cls flower is not supported\n");
7370                 return -EOPNOTSUPP;
7371         }
7372
7373         ret = hclge_check_cls_flower(hdev, cls_flower, tc);
7374         if (ret) {
7375                 dev_err(&hdev->pdev->dev,
7376                         "failed to check cls flower params, ret = %d\n", ret);
7377                 return ret;
7378         }
7379
7380         rule = kzalloc(sizeof(*rule), GFP_KERNEL);
7381         if (!rule)
7382                 return -ENOMEM;
7383
7384         ret = hclge_parse_cls_flower(hdev, cls_flower, rule);
7385         if (ret) {
7386                 kfree(rule);
7387                 return ret;
7388         }
7389
7390         rule->action = HCLGE_FD_ACTION_SELECT_TC;
7391         rule->cls_flower.tc = tc;
7392         rule->location = cls_flower->common.prio - 1;
7393         rule->vf_id = 0;
7394         rule->cls_flower.cookie = cls_flower->cookie;
7395         rule->rule_type = HCLGE_FD_TC_FLOWER_ACTIVE;
7396
7397         ret = hclge_add_fd_entry_common(hdev, rule);
7398         if (ret)
7399                 kfree(rule);
7400
7401         return ret;
7402 }
7403
7404 static struct hclge_fd_rule *hclge_find_cls_flower(struct hclge_dev *hdev,
7405                                                    unsigned long cookie)
7406 {
7407         struct hclge_fd_rule *rule;
7408         struct hlist_node *node;
7409
7410         hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
7411                 if (rule->cls_flower.cookie == cookie)
7412                         return rule;
7413         }
7414
7415         return NULL;
7416 }
7417
7418 static int hclge_del_cls_flower(struct hnae3_handle *handle,
7419                                 struct flow_cls_offload *cls_flower)
7420 {
7421         struct hclge_vport *vport = hclge_get_vport(handle);
7422         struct hclge_dev *hdev = vport->back;
7423         struct hclge_fd_rule *rule;
7424         int ret;
7425
7426         if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
7427                 return -EOPNOTSUPP;
7428
7429         spin_lock_bh(&hdev->fd_rule_lock);
7430
7431         rule = hclge_find_cls_flower(hdev, cls_flower->cookie);
7432         if (!rule) {
7433                 spin_unlock_bh(&hdev->fd_rule_lock);
7434                 return -EINVAL;
7435         }
7436
7437         ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, rule->location,
7438                                    NULL, false);
7439         if (ret) {
7440                 spin_unlock_bh(&hdev->fd_rule_lock);
7441                 return ret;
7442         }
7443
7444         hclge_update_fd_list(hdev, HCLGE_FD_DELETED, rule->location, NULL);
7445         spin_unlock_bh(&hdev->fd_rule_lock);
7446
7447         return 0;
7448 }
7449
7450 static void hclge_sync_fd_list(struct hclge_dev *hdev, struct hlist_head *hlist)
7451 {
7452         struct hclge_fd_rule *rule;
7453         struct hlist_node *node;
7454         int ret = 0;
7455
7456         if (!test_and_clear_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state))
7457                 return;
7458
7459         spin_lock_bh(&hdev->fd_rule_lock);
7460
7461         hlist_for_each_entry_safe(rule, node, hlist, rule_node) {
7462                 switch (rule->state) {
7463                 case HCLGE_FD_TO_ADD:
7464                         ret = hclge_fd_config_rule(hdev, rule);
7465                         if (ret)
7466                                 goto out;
7467                         rule->state = HCLGE_FD_ACTIVE;
7468                         break;
7469                 case HCLGE_FD_TO_DEL:
7470                         ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
7471                                                    rule->location, NULL, false);
7472                         if (ret)
7473                                 goto out;
7474                         hclge_fd_dec_rule_cnt(hdev, rule->location);
7475                         hclge_fd_free_node(hdev, rule);
7476                         break;
7477                 default:
7478                         break;
7479                 }
7480         }
7481
7482 out:
7483         if (ret)
7484                 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state);
7485
7486         spin_unlock_bh(&hdev->fd_rule_lock);
7487 }
7488
7489 static void hclge_sync_fd_table(struct hclge_dev *hdev)
7490 {
7491         if (test_and_clear_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state)) {
7492                 bool clear_list = hdev->fd_active_type == HCLGE_FD_ARFS_ACTIVE;
7493
7494                 hclge_clear_fd_rules_in_list(hdev, clear_list);
7495         }
7496
7497         hclge_sync_fd_user_def_cfg(hdev, false);
7498
7499         hclge_sync_fd_list(hdev, &hdev->fd_rule_list);
7500 }
7501
7502 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle)
7503 {
7504         struct hclge_vport *vport = hclge_get_vport(handle);
7505         struct hclge_dev *hdev = vport->back;
7506
7507         return hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) ||
7508                hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING);
7509 }
7510
7511 static bool hclge_get_cmdq_stat(struct hnae3_handle *handle)
7512 {
7513         struct hclge_vport *vport = hclge_get_vport(handle);
7514         struct hclge_dev *hdev = vport->back;
7515
7516         return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
7517 }
7518
7519 static bool hclge_ae_dev_resetting(struct hnae3_handle *handle)
7520 {
7521         struct hclge_vport *vport = hclge_get_vport(handle);
7522         struct hclge_dev *hdev = vport->back;
7523
7524         return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
7525 }
7526
7527 static unsigned long hclge_ae_dev_reset_cnt(struct hnae3_handle *handle)
7528 {
7529         struct hclge_vport *vport = hclge_get_vport(handle);
7530         struct hclge_dev *hdev = vport->back;
7531
7532         return hdev->rst_stats.hw_reset_done_cnt;
7533 }
7534
7535 static void hclge_enable_fd(struct hnae3_handle *handle, bool enable)
7536 {
7537         struct hclge_vport *vport = hclge_get_vport(handle);
7538         struct hclge_dev *hdev = vport->back;
7539
7540         hdev->fd_en = enable;
7541
7542         if (!enable)
7543                 set_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state);
7544         else
7545                 hclge_restore_fd_entries(handle);
7546
7547         hclge_task_schedule(hdev, 0);
7548 }
7549
7550 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
7551 {
7552         struct hclge_desc desc;
7553         struct hclge_config_mac_mode_cmd *req =
7554                 (struct hclge_config_mac_mode_cmd *)desc.data;
7555         u32 loop_en = 0;
7556         int ret;
7557
7558         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
7559
7560         if (enable) {
7561                 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, 1U);
7562                 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, 1U);
7563                 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, 1U);
7564                 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, 1U);
7565                 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, 1U);
7566                 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, 1U);
7567                 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, 1U);
7568                 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, 1U);
7569                 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, 1U);
7570                 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, 1U);
7571         }
7572
7573         req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
7574
7575         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7576         if (ret)
7577                 dev_err(&hdev->pdev->dev,
7578                         "mac enable fail, ret =%d.\n", ret);
7579 }
7580
7581 static int hclge_config_switch_param(struct hclge_dev *hdev, int vfid,
7582                                      u8 switch_param, u8 param_mask)
7583 {
7584         struct hclge_mac_vlan_switch_cmd *req;
7585         struct hclge_desc desc;
7586         u32 func_id;
7587         int ret;
7588
7589         func_id = hclge_get_port_number(HOST_PORT, 0, vfid, 0);
7590         req = (struct hclge_mac_vlan_switch_cmd *)desc.data;
7591
7592         /* read current config parameter */
7593         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_SWITCH_PARAM,
7594                                    true);
7595         req->roce_sel = HCLGE_MAC_VLAN_NIC_SEL;
7596         req->func_id = cpu_to_le32(func_id);
7597
7598         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7599         if (ret) {
7600                 dev_err(&hdev->pdev->dev,
7601                         "read mac vlan switch parameter fail, ret = %d\n", ret);
7602                 return ret;
7603         }
7604
7605         /* modify and write new config parameter */
7606         hclge_comm_cmd_reuse_desc(&desc, false);
7607         req->switch_param = (req->switch_param & param_mask) | switch_param;
7608         req->param_mask = param_mask;
7609
7610         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7611         if (ret)
7612                 dev_err(&hdev->pdev->dev,
7613                         "set mac vlan switch parameter fail, ret = %d\n", ret);
7614         return ret;
7615 }
7616
7617 static void hclge_phy_link_status_wait(struct hclge_dev *hdev,
7618                                        int link_ret)
7619 {
7620 #define HCLGE_PHY_LINK_STATUS_NUM  200
7621
7622         struct phy_device *phydev = hdev->hw.mac.phydev;
7623         int i = 0;
7624         int ret;
7625
7626         do {
7627                 ret = phy_read_status(phydev);
7628                 if (ret) {
7629                         dev_err(&hdev->pdev->dev,
7630                                 "phy update link status fail, ret = %d\n", ret);
7631                         return;
7632                 }
7633
7634                 if (phydev->link == link_ret)
7635                         break;
7636
7637                 msleep(HCLGE_LINK_STATUS_MS);
7638         } while (++i < HCLGE_PHY_LINK_STATUS_NUM);
7639 }
7640
7641 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret)
7642 {
7643 #define HCLGE_MAC_LINK_STATUS_NUM  100
7644
7645         int link_status;
7646         int i = 0;
7647         int ret;
7648
7649         do {
7650                 ret = hclge_get_mac_link_status(hdev, &link_status);
7651                 if (ret)
7652                         return ret;
7653                 if (link_status == link_ret)
7654                         return 0;
7655
7656                 msleep(HCLGE_LINK_STATUS_MS);
7657         } while (++i < HCLGE_MAC_LINK_STATUS_NUM);
7658         return -EBUSY;
7659 }
7660
7661 static int hclge_mac_phy_link_status_wait(struct hclge_dev *hdev, bool en,
7662                                           bool is_phy)
7663 {
7664         int link_ret;
7665
7666         link_ret = en ? HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN;
7667
7668         if (is_phy)
7669                 hclge_phy_link_status_wait(hdev, link_ret);
7670
7671         return hclge_mac_link_status_wait(hdev, link_ret);
7672 }
7673
7674 static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en)
7675 {
7676         struct hclge_config_mac_mode_cmd *req;
7677         struct hclge_desc desc;
7678         u32 loop_en;
7679         int ret;
7680
7681         req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
7682         /* 1 Read out the MAC mode config at first */
7683         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
7684         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7685         if (ret) {
7686                 dev_err(&hdev->pdev->dev,
7687                         "mac loopback get fail, ret =%d.\n", ret);
7688                 return ret;
7689         }
7690
7691         /* 2 Then setup the loopback flag */
7692         loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
7693         hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0);
7694
7695         req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
7696
7697         /* 3 Config mac work mode with loopback flag
7698          * and its original configure parameters
7699          */
7700         hclge_comm_cmd_reuse_desc(&desc, false);
7701         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7702         if (ret)
7703                 dev_err(&hdev->pdev->dev,
7704                         "mac loopback set fail, ret =%d.\n", ret);
7705         return ret;
7706 }
7707
7708 static int hclge_cfg_common_loopback_cmd_send(struct hclge_dev *hdev, bool en,
7709                                               enum hnae3_loop loop_mode)
7710 {
7711         struct hclge_common_lb_cmd *req;
7712         struct hclge_desc desc;
7713         u8 loop_mode_b;
7714         int ret;
7715
7716         req = (struct hclge_common_lb_cmd *)desc.data;
7717         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, false);
7718
7719         switch (loop_mode) {
7720         case HNAE3_LOOP_SERIAL_SERDES:
7721                 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
7722                 break;
7723         case HNAE3_LOOP_PARALLEL_SERDES:
7724                 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B;
7725                 break;
7726         case HNAE3_LOOP_PHY:
7727                 loop_mode_b = HCLGE_CMD_GE_PHY_INNER_LOOP_B;
7728                 break;
7729         default:
7730                 dev_err(&hdev->pdev->dev,
7731                         "unsupported loopback mode %d\n", loop_mode);
7732                 return -ENOTSUPP;
7733         }
7734
7735         req->mask = loop_mode_b;
7736         if (en)
7737                 req->enable = loop_mode_b;
7738
7739         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7740         if (ret)
7741                 dev_err(&hdev->pdev->dev,
7742                         "failed to send loopback cmd, loop_mode = %d, ret = %d\n",
7743                         loop_mode, ret);
7744
7745         return ret;
7746 }
7747
7748 static int hclge_cfg_common_loopback_wait(struct hclge_dev *hdev)
7749 {
7750 #define HCLGE_COMMON_LB_RETRY_MS        10
7751 #define HCLGE_COMMON_LB_RETRY_NUM       100
7752
7753         struct hclge_common_lb_cmd *req;
7754         struct hclge_desc desc;
7755         u32 i = 0;
7756         int ret;
7757
7758         req = (struct hclge_common_lb_cmd *)desc.data;
7759
7760         do {
7761                 msleep(HCLGE_COMMON_LB_RETRY_MS);
7762                 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK,
7763                                            true);
7764                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7765                 if (ret) {
7766                         dev_err(&hdev->pdev->dev,
7767                                 "failed to get loopback done status, ret = %d\n",
7768                                 ret);
7769                         return ret;
7770                 }
7771         } while (++i < HCLGE_COMMON_LB_RETRY_NUM &&
7772                  !(req->result & HCLGE_CMD_COMMON_LB_DONE_B));
7773
7774         if (!(req->result & HCLGE_CMD_COMMON_LB_DONE_B)) {
7775                 dev_err(&hdev->pdev->dev, "wait loopback timeout\n");
7776                 return -EBUSY;
7777         } else if (!(req->result & HCLGE_CMD_COMMON_LB_SUCCESS_B)) {
7778                 dev_err(&hdev->pdev->dev, "failed to do loopback test\n");
7779                 return -EIO;
7780         }
7781
7782         return 0;
7783 }
7784
7785 static int hclge_cfg_common_loopback(struct hclge_dev *hdev, bool en,
7786                                      enum hnae3_loop loop_mode)
7787 {
7788         int ret;
7789
7790         ret = hclge_cfg_common_loopback_cmd_send(hdev, en, loop_mode);
7791         if (ret)
7792                 return ret;
7793
7794         return hclge_cfg_common_loopback_wait(hdev);
7795 }
7796
7797 static int hclge_set_common_loopback(struct hclge_dev *hdev, bool en,
7798                                      enum hnae3_loop loop_mode)
7799 {
7800         int ret;
7801
7802         ret = hclge_cfg_common_loopback(hdev, en, loop_mode);
7803         if (ret)
7804                 return ret;
7805
7806         hclge_cfg_mac_mode(hdev, en);
7807
7808         ret = hclge_mac_phy_link_status_wait(hdev, en, false);
7809         if (ret)
7810                 dev_err(&hdev->pdev->dev,
7811                         "serdes loopback config mac mode timeout\n");
7812
7813         return ret;
7814 }
7815
7816 static int hclge_enable_phy_loopback(struct hclge_dev *hdev,
7817                                      struct phy_device *phydev)
7818 {
7819         int ret;
7820
7821         if (!phydev->suspended) {
7822                 ret = phy_suspend(phydev);
7823                 if (ret)
7824                         return ret;
7825         }
7826
7827         ret = phy_resume(phydev);
7828         if (ret)
7829                 return ret;
7830
7831         return phy_loopback(phydev, true);
7832 }
7833
7834 static int hclge_disable_phy_loopback(struct hclge_dev *hdev,
7835                                       struct phy_device *phydev)
7836 {
7837         int ret;
7838
7839         ret = phy_loopback(phydev, false);
7840         if (ret)
7841                 return ret;
7842
7843         return phy_suspend(phydev);
7844 }
7845
7846 static int hclge_set_phy_loopback(struct hclge_dev *hdev, bool en)
7847 {
7848         struct phy_device *phydev = hdev->hw.mac.phydev;
7849         int ret;
7850
7851         if (!phydev) {
7852                 if (hnae3_dev_phy_imp_supported(hdev))
7853                         return hclge_set_common_loopback(hdev, en,
7854                                                          HNAE3_LOOP_PHY);
7855                 return -ENOTSUPP;
7856         }
7857
7858         if (en)
7859                 ret = hclge_enable_phy_loopback(hdev, phydev);
7860         else
7861                 ret = hclge_disable_phy_loopback(hdev, phydev);
7862         if (ret) {
7863                 dev_err(&hdev->pdev->dev,
7864                         "set phy loopback fail, ret = %d\n", ret);
7865                 return ret;
7866         }
7867
7868         hclge_cfg_mac_mode(hdev, en);
7869
7870         ret = hclge_mac_phy_link_status_wait(hdev, en, true);
7871         if (ret)
7872                 dev_err(&hdev->pdev->dev,
7873                         "phy loopback config mac mode timeout\n");
7874
7875         return ret;
7876 }
7877
7878 static int hclge_tqp_enable_cmd_send(struct hclge_dev *hdev, u16 tqp_id,
7879                                      u16 stream_id, bool enable)
7880 {
7881         struct hclge_desc desc;
7882         struct hclge_cfg_com_tqp_queue_cmd *req =
7883                 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
7884
7885         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
7886         req->tqp_id = cpu_to_le16(tqp_id);
7887         req->stream_id = cpu_to_le16(stream_id);
7888         if (enable)
7889                 req->enable |= 1U << HCLGE_TQP_ENABLE_B;
7890
7891         return hclge_cmd_send(&hdev->hw, &desc, 1);
7892 }
7893
7894 static int hclge_tqp_enable(struct hnae3_handle *handle, bool enable)
7895 {
7896         struct hclge_vport *vport = hclge_get_vport(handle);
7897         struct hclge_dev *hdev = vport->back;
7898         int ret;
7899         u16 i;
7900
7901         for (i = 0; i < handle->kinfo.num_tqps; i++) {
7902                 ret = hclge_tqp_enable_cmd_send(hdev, i, 0, enable);
7903                 if (ret)
7904                         return ret;
7905         }
7906         return 0;
7907 }
7908
7909 static int hclge_set_loopback(struct hnae3_handle *handle,
7910                               enum hnae3_loop loop_mode, bool en)
7911 {
7912         struct hclge_vport *vport = hclge_get_vport(handle);
7913         struct hclge_dev *hdev = vport->back;
7914         int ret = 0;
7915
7916         /* Loopback can be enabled in three places: SSU, MAC, and serdes. By
7917          * default, SSU loopback is enabled, so if the SMAC and the DMAC are
7918          * the same, the packets are looped back in the SSU. If SSU loopback
7919          * is disabled, packets can reach MAC even if SMAC is the same as DMAC.
7920          */
7921         if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
7922                 u8 switch_param = en ? 0 : BIT(HCLGE_SWITCH_ALW_LPBK_B);
7923
7924                 ret = hclge_config_switch_param(hdev, PF_VPORT_ID, switch_param,
7925                                                 HCLGE_SWITCH_ALW_LPBK_MASK);
7926                 if (ret)
7927                         return ret;
7928         }
7929
7930         switch (loop_mode) {
7931         case HNAE3_LOOP_APP:
7932                 ret = hclge_set_app_loopback(hdev, en);
7933                 break;
7934         case HNAE3_LOOP_SERIAL_SERDES:
7935         case HNAE3_LOOP_PARALLEL_SERDES:
7936                 ret = hclge_set_common_loopback(hdev, en, loop_mode);
7937                 break;
7938         case HNAE3_LOOP_PHY:
7939                 ret = hclge_set_phy_loopback(hdev, en);
7940                 break;
7941         case HNAE3_LOOP_EXTERNAL:
7942                 break;
7943         default:
7944                 ret = -ENOTSUPP;
7945                 dev_err(&hdev->pdev->dev,
7946                         "loop_mode %d is not supported\n", loop_mode);
7947                 break;
7948         }
7949
7950         if (ret)
7951                 return ret;
7952
7953         ret = hclge_tqp_enable(handle, en);
7954         if (ret)
7955                 dev_err(&hdev->pdev->dev, "failed to %s tqp in loopback, ret = %d\n",
7956                         en ? "enable" : "disable", ret);
7957
7958         return ret;
7959 }
7960
7961 static int hclge_set_default_loopback(struct hclge_dev *hdev)
7962 {
7963         int ret;
7964
7965         ret = hclge_set_app_loopback(hdev, false);
7966         if (ret)
7967                 return ret;
7968
7969         ret = hclge_cfg_common_loopback(hdev, false, HNAE3_LOOP_SERIAL_SERDES);
7970         if (ret)
7971                 return ret;
7972
7973         return hclge_cfg_common_loopback(hdev, false,
7974                                          HNAE3_LOOP_PARALLEL_SERDES);
7975 }
7976
7977 static void hclge_flush_link_update(struct hclge_dev *hdev)
7978 {
7979 #define HCLGE_FLUSH_LINK_TIMEOUT        100000
7980
7981         unsigned long last = hdev->serv_processed_cnt;
7982         int i = 0;
7983
7984         while (test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state) &&
7985                i++ < HCLGE_FLUSH_LINK_TIMEOUT &&
7986                last == hdev->serv_processed_cnt)
7987                 usleep_range(1, 1);
7988 }
7989
7990 static void hclge_set_timer_task(struct hnae3_handle *handle, bool enable)
7991 {
7992         struct hclge_vport *vport = hclge_get_vport(handle);
7993         struct hclge_dev *hdev = vport->back;
7994
7995         if (enable) {
7996                 hclge_task_schedule(hdev, 0);
7997         } else {
7998                 /* Set the DOWN flag here to disable link updating */
7999                 set_bit(HCLGE_STATE_DOWN, &hdev->state);
8000
8001                 /* flush memory to make sure DOWN is seen by service task */
8002                 smp_mb__before_atomic();
8003                 hclge_flush_link_update(hdev);
8004         }
8005 }
8006
8007 static int hclge_ae_start(struct hnae3_handle *handle)
8008 {
8009         struct hclge_vport *vport = hclge_get_vport(handle);
8010         struct hclge_dev *hdev = vport->back;
8011
8012         /* mac enable */
8013         hclge_cfg_mac_mode(hdev, true);
8014         clear_bit(HCLGE_STATE_DOWN, &hdev->state);
8015         hdev->hw.mac.link = 0;
8016
8017         /* reset tqp stats */
8018         hclge_comm_reset_tqp_stats(handle);
8019
8020         hclge_mac_start_phy(hdev);
8021
8022         return 0;
8023 }
8024
8025 static void hclge_ae_stop(struct hnae3_handle *handle)
8026 {
8027         struct hclge_vport *vport = hclge_get_vport(handle);
8028         struct hclge_dev *hdev = vport->back;
8029
8030         set_bit(HCLGE_STATE_DOWN, &hdev->state);
8031         spin_lock_bh(&hdev->fd_rule_lock);
8032         hclge_clear_arfs_rules(hdev);
8033         spin_unlock_bh(&hdev->fd_rule_lock);
8034
8035         /* If it is not PF reset or FLR, the firmware will disable the MAC,
8036          * so it only need to stop phy here.
8037          */
8038         if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) &&
8039             hdev->reset_type != HNAE3_FUNC_RESET &&
8040             hdev->reset_type != HNAE3_FLR_RESET) {
8041                 hclge_mac_stop_phy(hdev);
8042                 hclge_update_link_status(hdev);
8043                 return;
8044         }
8045
8046         hclge_reset_tqp(handle);
8047
8048         hclge_config_mac_tnl_int(hdev, false);
8049
8050         /* Mac disable */
8051         hclge_cfg_mac_mode(hdev, false);
8052
8053         hclge_mac_stop_phy(hdev);
8054
8055         /* reset tqp stats */
8056         hclge_comm_reset_tqp_stats(handle);
8057         hclge_update_link_status(hdev);
8058 }
8059
8060 int hclge_vport_start(struct hclge_vport *vport)
8061 {
8062         struct hclge_dev *hdev = vport->back;
8063
8064         set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
8065         set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
8066         vport->last_active_jiffies = jiffies;
8067
8068         if (test_bit(vport->vport_id, hdev->vport_config_block)) {
8069                 if (vport->vport_id) {
8070                         hclge_restore_mac_table_common(vport);
8071                         hclge_restore_vport_vlan_table(vport);
8072                 } else {
8073                         hclge_restore_hw_table(hdev);
8074                 }
8075         }
8076
8077         clear_bit(vport->vport_id, hdev->vport_config_block);
8078
8079         return 0;
8080 }
8081
8082 void hclge_vport_stop(struct hclge_vport *vport)
8083 {
8084         clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
8085 }
8086
8087 static int hclge_client_start(struct hnae3_handle *handle)
8088 {
8089         struct hclge_vport *vport = hclge_get_vport(handle);
8090
8091         return hclge_vport_start(vport);
8092 }
8093
8094 static void hclge_client_stop(struct hnae3_handle *handle)
8095 {
8096         struct hclge_vport *vport = hclge_get_vport(handle);
8097
8098         hclge_vport_stop(vport);
8099 }
8100
8101 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
8102                                          u16 cmdq_resp, u8  resp_code,
8103                                          enum hclge_mac_vlan_tbl_opcode op)
8104 {
8105         struct hclge_dev *hdev = vport->back;
8106
8107         if (cmdq_resp) {
8108                 dev_err(&hdev->pdev->dev,
8109                         "cmdq execute failed for get_mac_vlan_cmd_status,status=%u.\n",
8110                         cmdq_resp);
8111                 return -EIO;
8112         }
8113
8114         if (op == HCLGE_MAC_VLAN_ADD) {
8115                 if (!resp_code || resp_code == 1)
8116                         return 0;
8117                 else if (resp_code == HCLGE_ADD_UC_OVERFLOW ||
8118                          resp_code == HCLGE_ADD_MC_OVERFLOW)
8119                         return -ENOSPC;
8120
8121                 dev_err(&hdev->pdev->dev,
8122                         "add mac addr failed for undefined, code=%u.\n",
8123                         resp_code);
8124                 return -EIO;
8125         } else if (op == HCLGE_MAC_VLAN_REMOVE) {
8126                 if (!resp_code) {
8127                         return 0;
8128                 } else if (resp_code == 1) {
8129                         dev_dbg(&hdev->pdev->dev,
8130                                 "remove mac addr failed for miss.\n");
8131                         return -ENOENT;
8132                 }
8133
8134                 dev_err(&hdev->pdev->dev,
8135                         "remove mac addr failed for undefined, code=%u.\n",
8136                         resp_code);
8137                 return -EIO;
8138         } else if (op == HCLGE_MAC_VLAN_LKUP) {
8139                 if (!resp_code) {
8140                         return 0;
8141                 } else if (resp_code == 1) {
8142                         dev_dbg(&hdev->pdev->dev,
8143                                 "lookup mac addr failed for miss.\n");
8144                         return -ENOENT;
8145                 }
8146
8147                 dev_err(&hdev->pdev->dev,
8148                         "lookup mac addr failed for undefined, code=%u.\n",
8149                         resp_code);
8150                 return -EIO;
8151         }
8152
8153         dev_err(&hdev->pdev->dev,
8154                 "unknown opcode for get_mac_vlan_cmd_status, opcode=%d.\n", op);
8155
8156         return -EINVAL;
8157 }
8158
8159 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
8160 {
8161 #define HCLGE_VF_NUM_IN_FIRST_DESC 192
8162
8163         unsigned int word_num;
8164         unsigned int bit_num;
8165
8166         if (vfid > 255 || vfid < 0)
8167                 return -EIO;
8168
8169         if (vfid >= 0 && vfid < HCLGE_VF_NUM_IN_FIRST_DESC) {
8170                 word_num = vfid / 32;
8171                 bit_num  = vfid % 32;
8172                 if (clr)
8173                         desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
8174                 else
8175                         desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
8176         } else {
8177                 word_num = (vfid - HCLGE_VF_NUM_IN_FIRST_DESC) / 32;
8178                 bit_num  = vfid % 32;
8179                 if (clr)
8180                         desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
8181                 else
8182                         desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
8183         }
8184
8185         return 0;
8186 }
8187
8188 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
8189 {
8190 #define HCLGE_DESC_NUMBER 3
8191 #define HCLGE_FUNC_NUMBER_PER_DESC 6
8192         int i, j;
8193
8194         for (i = 1; i < HCLGE_DESC_NUMBER; i++)
8195                 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
8196                         if (desc[i].data[j])
8197                                 return false;
8198
8199         return true;
8200 }
8201
8202 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
8203                                    const u8 *addr, bool is_mc)
8204 {
8205         const unsigned char *mac_addr = addr;
8206         u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
8207                        (mac_addr[0]) | (mac_addr[1] << 8);
8208         u32 low_val  = mac_addr[4] | (mac_addr[5] << 8);
8209
8210         hnae3_set_bit(new_req->flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
8211         if (is_mc) {
8212                 hnae3_set_bit(new_req->entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
8213                 hnae3_set_bit(new_req->mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
8214         }
8215
8216         new_req->mac_addr_hi32 = cpu_to_le32(high_val);
8217         new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
8218 }
8219
8220 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
8221                                      struct hclge_mac_vlan_tbl_entry_cmd *req)
8222 {
8223         struct hclge_dev *hdev = vport->back;
8224         struct hclge_desc desc;
8225         u8 resp_code;
8226         u16 retval;
8227         int ret;
8228
8229         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
8230
8231         memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
8232
8233         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
8234         if (ret) {
8235                 dev_err(&hdev->pdev->dev,
8236                         "del mac addr failed for cmd_send, ret =%d.\n",
8237                         ret);
8238                 return ret;
8239         }
8240         resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
8241         retval = le16_to_cpu(desc.retval);
8242
8243         return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
8244                                              HCLGE_MAC_VLAN_REMOVE);
8245 }
8246
8247 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
8248                                      struct hclge_mac_vlan_tbl_entry_cmd *req,
8249                                      struct hclge_desc *desc,
8250                                      bool is_mc)
8251 {
8252         struct hclge_dev *hdev = vport->back;
8253         u8 resp_code;
8254         u16 retval;
8255         int ret;
8256
8257         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
8258         if (is_mc) {
8259                 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
8260                 memcpy(desc[0].data,
8261                        req,
8262                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
8263                 hclge_cmd_setup_basic_desc(&desc[1],
8264                                            HCLGE_OPC_MAC_VLAN_ADD,
8265                                            true);
8266                 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
8267                 hclge_cmd_setup_basic_desc(&desc[2],
8268                                            HCLGE_OPC_MAC_VLAN_ADD,
8269                                            true);
8270                 ret = hclge_cmd_send(&hdev->hw, desc, 3);
8271         } else {
8272                 memcpy(desc[0].data,
8273                        req,
8274                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
8275                 ret = hclge_cmd_send(&hdev->hw, desc, 1);
8276         }
8277         if (ret) {
8278                 dev_err(&hdev->pdev->dev,
8279                         "lookup mac addr failed for cmd_send, ret =%d.\n",
8280                         ret);
8281                 return ret;
8282         }
8283         resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
8284         retval = le16_to_cpu(desc[0].retval);
8285
8286         return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
8287                                              HCLGE_MAC_VLAN_LKUP);
8288 }
8289
8290 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
8291                                   struct hclge_mac_vlan_tbl_entry_cmd *req,
8292                                   struct hclge_desc *mc_desc)
8293 {
8294         struct hclge_dev *hdev = vport->back;
8295         int cfg_status;
8296         u8 resp_code;
8297         u16 retval;
8298         int ret;
8299
8300         if (!mc_desc) {
8301                 struct hclge_desc desc;
8302
8303                 hclge_cmd_setup_basic_desc(&desc,
8304                                            HCLGE_OPC_MAC_VLAN_ADD,
8305                                            false);
8306                 memcpy(desc.data, req,
8307                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
8308                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
8309                 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
8310                 retval = le16_to_cpu(desc.retval);
8311
8312                 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
8313                                                            resp_code,
8314                                                            HCLGE_MAC_VLAN_ADD);
8315         } else {
8316                 hclge_comm_cmd_reuse_desc(&mc_desc[0], false);
8317                 mc_desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
8318                 hclge_comm_cmd_reuse_desc(&mc_desc[1], false);
8319                 mc_desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
8320                 hclge_comm_cmd_reuse_desc(&mc_desc[2], false);
8321                 mc_desc[2].flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_NEXT);
8322                 memcpy(mc_desc[0].data, req,
8323                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
8324                 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
8325                 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
8326                 retval = le16_to_cpu(mc_desc[0].retval);
8327
8328                 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
8329                                                            resp_code,
8330                                                            HCLGE_MAC_VLAN_ADD);
8331         }
8332
8333         if (ret) {
8334                 dev_err(&hdev->pdev->dev,
8335                         "add mac addr failed for cmd_send, ret =%d.\n",
8336                         ret);
8337                 return ret;
8338         }
8339
8340         return cfg_status;
8341 }
8342
8343 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size,
8344                                u16 *allocated_size)
8345 {
8346         struct hclge_umv_spc_alc_cmd *req;
8347         struct hclge_desc desc;
8348         int ret;
8349
8350         req = (struct hclge_umv_spc_alc_cmd *)desc.data;
8351         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false);
8352
8353         req->space_size = cpu_to_le32(space_size);
8354
8355         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
8356         if (ret) {
8357                 dev_err(&hdev->pdev->dev, "failed to set umv space, ret = %d\n",
8358                         ret);
8359                 return ret;
8360         }
8361
8362         *allocated_size = le32_to_cpu(desc.data[1]);
8363
8364         return 0;
8365 }
8366
8367 static int hclge_init_umv_space(struct hclge_dev *hdev)
8368 {
8369         u16 allocated_size = 0;
8370         int ret;
8371
8372         ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size);
8373         if (ret)
8374                 return ret;
8375
8376         if (allocated_size < hdev->wanted_umv_size)
8377                 dev_warn(&hdev->pdev->dev,
8378                          "failed to alloc umv space, want %u, get %u\n",
8379                          hdev->wanted_umv_size, allocated_size);
8380
8381         hdev->max_umv_size = allocated_size;
8382         hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_alloc_vport + 1);
8383         hdev->share_umv_size = hdev->priv_umv_size +
8384                         hdev->max_umv_size % (hdev->num_alloc_vport + 1);
8385
8386         if (hdev->ae_dev->dev_specs.mc_mac_size)
8387                 set_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, hdev->ae_dev->caps);
8388
8389         return 0;
8390 }
8391
8392 static void hclge_reset_umv_space(struct hclge_dev *hdev)
8393 {
8394         struct hclge_vport *vport;
8395         int i;
8396
8397         for (i = 0; i < hdev->num_alloc_vport; i++) {
8398                 vport = &hdev->vport[i];
8399                 vport->used_umv_num = 0;
8400         }
8401
8402         mutex_lock(&hdev->vport_lock);
8403         hdev->share_umv_size = hdev->priv_umv_size +
8404                         hdev->max_umv_size % (hdev->num_alloc_vport + 1);
8405         mutex_unlock(&hdev->vport_lock);
8406
8407         hdev->used_mc_mac_num = 0;
8408 }
8409
8410 static bool hclge_is_umv_space_full(struct hclge_vport *vport, bool need_lock)
8411 {
8412         struct hclge_dev *hdev = vport->back;
8413         bool is_full;
8414
8415         if (need_lock)
8416                 mutex_lock(&hdev->vport_lock);
8417
8418         is_full = (vport->used_umv_num >= hdev->priv_umv_size &&
8419                    hdev->share_umv_size == 0);
8420
8421         if (need_lock)
8422                 mutex_unlock(&hdev->vport_lock);
8423
8424         return is_full;
8425 }
8426
8427 static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free)
8428 {
8429         struct hclge_dev *hdev = vport->back;
8430
8431         if (is_free) {
8432                 if (vport->used_umv_num > hdev->priv_umv_size)
8433                         hdev->share_umv_size++;
8434
8435                 if (vport->used_umv_num > 0)
8436                         vport->used_umv_num--;
8437         } else {
8438                 if (vport->used_umv_num >= hdev->priv_umv_size &&
8439                     hdev->share_umv_size > 0)
8440                         hdev->share_umv_size--;
8441                 vport->used_umv_num++;
8442         }
8443 }
8444
8445 static struct hclge_mac_node *hclge_find_mac_node(struct list_head *list,
8446                                                   const u8 *mac_addr)
8447 {
8448         struct hclge_mac_node *mac_node, *tmp;
8449
8450         list_for_each_entry_safe(mac_node, tmp, list, node)
8451                 if (ether_addr_equal(mac_addr, mac_node->mac_addr))
8452                         return mac_node;
8453
8454         return NULL;
8455 }
8456
8457 static void hclge_update_mac_node(struct hclge_mac_node *mac_node,
8458                                   enum HCLGE_MAC_NODE_STATE state)
8459 {
8460         switch (state) {
8461         /* from set_rx_mode or tmp_add_list */
8462         case HCLGE_MAC_TO_ADD:
8463                 if (mac_node->state == HCLGE_MAC_TO_DEL)
8464                         mac_node->state = HCLGE_MAC_ACTIVE;
8465                 break;
8466         /* only from set_rx_mode */
8467         case HCLGE_MAC_TO_DEL:
8468                 if (mac_node->state == HCLGE_MAC_TO_ADD) {
8469                         list_del(&mac_node->node);
8470                         kfree(mac_node);
8471                 } else {
8472                         mac_node->state = HCLGE_MAC_TO_DEL;
8473                 }
8474                 break;
8475         /* only from tmp_add_list, the mac_node->state won't be
8476          * ACTIVE.
8477          */
8478         case HCLGE_MAC_ACTIVE:
8479                 if (mac_node->state == HCLGE_MAC_TO_ADD)
8480                         mac_node->state = HCLGE_MAC_ACTIVE;
8481
8482                 break;
8483         }
8484 }
8485
8486 int hclge_update_mac_list(struct hclge_vport *vport,
8487                           enum HCLGE_MAC_NODE_STATE state,
8488                           enum HCLGE_MAC_ADDR_TYPE mac_type,
8489                           const unsigned char *addr)
8490 {
8491         char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
8492         struct hclge_dev *hdev = vport->back;
8493         struct hclge_mac_node *mac_node;
8494         struct list_head *list;
8495
8496         list = (mac_type == HCLGE_MAC_ADDR_UC) ?
8497                 &vport->uc_mac_list : &vport->mc_mac_list;
8498
8499         spin_lock_bh(&vport->mac_list_lock);
8500
8501         /* if the mac addr is already in the mac list, no need to add a new
8502          * one into it, just check the mac addr state, convert it to a new
8503          * state, or just remove it, or do nothing.
8504          */
8505         mac_node = hclge_find_mac_node(list, addr);
8506         if (mac_node) {
8507                 hclge_update_mac_node(mac_node, state);
8508                 spin_unlock_bh(&vport->mac_list_lock);
8509                 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state);
8510                 return 0;
8511         }
8512
8513         /* if this address is never added, unnecessary to delete */
8514         if (state == HCLGE_MAC_TO_DEL) {
8515                 spin_unlock_bh(&vport->mac_list_lock);
8516                 hnae3_format_mac_addr(format_mac_addr, addr);
8517                 dev_err(&hdev->pdev->dev,
8518                         "failed to delete address %s from mac list\n",
8519                         format_mac_addr);
8520                 return -ENOENT;
8521         }
8522
8523         mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC);
8524         if (!mac_node) {
8525                 spin_unlock_bh(&vport->mac_list_lock);
8526                 return -ENOMEM;
8527         }
8528
8529         set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state);
8530
8531         mac_node->state = state;
8532         ether_addr_copy(mac_node->mac_addr, addr);
8533         list_add_tail(&mac_node->node, list);
8534
8535         spin_unlock_bh(&vport->mac_list_lock);
8536
8537         return 0;
8538 }
8539
8540 static int hclge_add_uc_addr(struct hnae3_handle *handle,
8541                              const unsigned char *addr)
8542 {
8543         struct hclge_vport *vport = hclge_get_vport(handle);
8544
8545         return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_UC,
8546                                      addr);
8547 }
8548
8549 int hclge_add_uc_addr_common(struct hclge_vport *vport,
8550                              const unsigned char *addr)
8551 {
8552         char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
8553         struct hclge_dev *hdev = vport->back;
8554         struct hclge_mac_vlan_tbl_entry_cmd req;
8555         struct hclge_desc desc;
8556         u16 egress_port = 0;
8557         int ret;
8558
8559         /* mac addr check */
8560         if (is_zero_ether_addr(addr) ||
8561             is_broadcast_ether_addr(addr) ||
8562             is_multicast_ether_addr(addr)) {
8563                 hnae3_format_mac_addr(format_mac_addr, addr);
8564                 dev_err(&hdev->pdev->dev,
8565                         "Set_uc mac err! invalid mac:%s. is_zero:%d,is_br=%d,is_mul=%d\n",
8566                          format_mac_addr, is_zero_ether_addr(addr),
8567                          is_broadcast_ether_addr(addr),
8568                          is_multicast_ether_addr(addr));
8569                 return -EINVAL;
8570         }
8571
8572         memset(&req, 0, sizeof(req));
8573
8574         hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
8575                         HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
8576
8577         req.egress_port = cpu_to_le16(egress_port);
8578
8579         hclge_prepare_mac_addr(&req, addr, false);
8580
8581         /* Lookup the mac address in the mac_vlan table, and add
8582          * it if the entry is inexistent. Repeated unicast entry
8583          * is not allowed in the mac vlan table.
8584          */
8585         ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false);
8586         if (ret == -ENOENT) {
8587                 mutex_lock(&hdev->vport_lock);
8588                 if (!hclge_is_umv_space_full(vport, false)) {
8589                         ret = hclge_add_mac_vlan_tbl(vport, &req, NULL);
8590                         if (!ret)
8591                                 hclge_update_umv_space(vport, false);
8592                         mutex_unlock(&hdev->vport_lock);
8593                         return ret;
8594                 }
8595                 mutex_unlock(&hdev->vport_lock);
8596
8597                 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE))
8598                         dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n",
8599                                 hdev->priv_umv_size);
8600
8601                 return -ENOSPC;
8602         }
8603
8604         /* check if we just hit the duplicate */
8605         if (!ret)
8606                 return -EEXIST;
8607
8608         return ret;
8609 }
8610
8611 static int hclge_rm_uc_addr(struct hnae3_handle *handle,
8612                             const unsigned char *addr)
8613 {
8614         struct hclge_vport *vport = hclge_get_vport(handle);
8615
8616         return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_UC,
8617                                      addr);
8618 }
8619
8620 int hclge_rm_uc_addr_common(struct hclge_vport *vport,
8621                             const unsigned char *addr)
8622 {
8623         char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
8624         struct hclge_dev *hdev = vport->back;
8625         struct hclge_mac_vlan_tbl_entry_cmd req;
8626         int ret;
8627
8628         /* mac addr check */
8629         if (is_zero_ether_addr(addr) ||
8630             is_broadcast_ether_addr(addr) ||
8631             is_multicast_ether_addr(addr)) {
8632                 hnae3_format_mac_addr(format_mac_addr, addr);
8633                 dev_dbg(&hdev->pdev->dev, "Remove mac err! invalid mac:%s.\n",
8634                         format_mac_addr);
8635                 return -EINVAL;
8636         }
8637
8638         memset(&req, 0, sizeof(req));
8639         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
8640         hclge_prepare_mac_addr(&req, addr, false);
8641         ret = hclge_remove_mac_vlan_tbl(vport, &req);
8642         if (!ret || ret == -ENOENT) {
8643                 mutex_lock(&hdev->vport_lock);
8644                 hclge_update_umv_space(vport, true);
8645                 mutex_unlock(&hdev->vport_lock);
8646                 return 0;
8647         }
8648
8649         return ret;
8650 }
8651
8652 static int hclge_add_mc_addr(struct hnae3_handle *handle,
8653                              const unsigned char *addr)
8654 {
8655         struct hclge_vport *vport = hclge_get_vport(handle);
8656
8657         return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_MC,
8658                                      addr);
8659 }
8660
8661 int hclge_add_mc_addr_common(struct hclge_vport *vport,
8662                              const unsigned char *addr)
8663 {
8664         char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
8665         struct hclge_dev *hdev = vport->back;
8666         struct hclge_mac_vlan_tbl_entry_cmd req;
8667         struct hclge_desc desc[3];
8668         bool is_new_addr = false;
8669         int status;
8670
8671         /* mac addr check */
8672         if (!is_multicast_ether_addr(addr)) {
8673                 hnae3_format_mac_addr(format_mac_addr, addr);
8674                 dev_err(&hdev->pdev->dev,
8675                         "Add mc mac err! invalid mac:%s.\n",
8676                          format_mac_addr);
8677                 return -EINVAL;
8678         }
8679         memset(&req, 0, sizeof(req));
8680         hclge_prepare_mac_addr(&req, addr, true);
8681         status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
8682         if (status) {
8683                 if (hnae3_ae_dev_mc_mac_mng_supported(hdev->ae_dev) &&
8684                     hdev->used_mc_mac_num >=
8685                     hdev->ae_dev->dev_specs.mc_mac_size)
8686                         goto err_no_space;
8687
8688                 is_new_addr = true;
8689
8690                 /* This mac addr do not exist, add new entry for it */
8691                 memset(desc[0].data, 0, sizeof(desc[0].data));
8692                 memset(desc[1].data, 0, sizeof(desc[0].data));
8693                 memset(desc[2].data, 0, sizeof(desc[0].data));
8694         }
8695         status = hclge_update_desc_vfid(desc, vport->vport_id, false);
8696         if (status)
8697                 return status;
8698         status = hclge_add_mac_vlan_tbl(vport, &req, desc);
8699         if (status == -ENOSPC)
8700                 goto err_no_space;
8701         else if (!status && is_new_addr)
8702                 hdev->used_mc_mac_num++;
8703
8704         return status;
8705
8706 err_no_space:
8707         /* if already overflow, not to print each time */
8708         if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE)) {
8709                 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE;
8710                 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n");
8711         }
8712
8713         return -ENOSPC;
8714 }
8715
8716 static int hclge_rm_mc_addr(struct hnae3_handle *handle,
8717                             const unsigned char *addr)
8718 {
8719         struct hclge_vport *vport = hclge_get_vport(handle);
8720
8721         return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_MC,
8722                                      addr);
8723 }
8724
8725 int hclge_rm_mc_addr_common(struct hclge_vport *vport,
8726                             const unsigned char *addr)
8727 {
8728         char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
8729         struct hclge_dev *hdev = vport->back;
8730         struct hclge_mac_vlan_tbl_entry_cmd req;
8731         enum hclge_comm_cmd_status status;
8732         struct hclge_desc desc[3];
8733
8734         /* mac addr check */
8735         if (!is_multicast_ether_addr(addr)) {
8736                 hnae3_format_mac_addr(format_mac_addr, addr);
8737                 dev_dbg(&hdev->pdev->dev,
8738                         "Remove mc mac err! invalid mac:%s.\n",
8739                          format_mac_addr);
8740                 return -EINVAL;
8741         }
8742
8743         memset(&req, 0, sizeof(req));
8744         hclge_prepare_mac_addr(&req, addr, true);
8745         status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
8746         if (!status) {
8747                 /* This mac addr exist, remove this handle's VFID for it */
8748                 status = hclge_update_desc_vfid(desc, vport->vport_id, true);
8749                 if (status)
8750                         return status;
8751
8752                 if (hclge_is_all_function_id_zero(desc)) {
8753                         /* All the vfid is zero, so need to delete this entry */
8754                         status = hclge_remove_mac_vlan_tbl(vport, &req);
8755                         if (!status)
8756                                 hdev->used_mc_mac_num--;
8757                 } else {
8758                         /* Not all the vfid is zero, update the vfid */
8759                         status = hclge_add_mac_vlan_tbl(vport, &req, desc);
8760                 }
8761         } else if (status == -ENOENT) {
8762                 status = 0;
8763         }
8764
8765         return status;
8766 }
8767
8768 static void hclge_sync_vport_mac_list(struct hclge_vport *vport,
8769                                       struct list_head *list,
8770                                       enum HCLGE_MAC_ADDR_TYPE mac_type)
8771 {
8772         int (*sync)(struct hclge_vport *vport, const unsigned char *addr);
8773         struct hclge_mac_node *mac_node, *tmp;
8774         int ret;
8775
8776         if (mac_type == HCLGE_MAC_ADDR_UC)
8777                 sync = hclge_add_uc_addr_common;
8778         else
8779                 sync = hclge_add_mc_addr_common;
8780
8781         list_for_each_entry_safe(mac_node, tmp, list, node) {
8782                 ret = sync(vport, mac_node->mac_addr);
8783                 if (!ret) {
8784                         mac_node->state = HCLGE_MAC_ACTIVE;
8785                 } else {
8786                         set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE,
8787                                 &vport->state);
8788
8789                         /* If one unicast mac address is existing in hardware,
8790                          * we need to try whether other unicast mac addresses
8791                          * are new addresses that can be added.
8792                          * Multicast mac address can be reusable, even though
8793                          * there is no space to add new multicast mac address,
8794                          * we should check whether other mac addresses are
8795                          * existing in hardware for reuse.
8796                          */
8797                         if ((mac_type == HCLGE_MAC_ADDR_UC && ret != -EEXIST) ||
8798                             (mac_type == HCLGE_MAC_ADDR_MC && ret != -ENOSPC))
8799                                 break;
8800                 }
8801         }
8802 }
8803
8804 static void hclge_unsync_vport_mac_list(struct hclge_vport *vport,
8805                                         struct list_head *list,
8806                                         enum HCLGE_MAC_ADDR_TYPE mac_type)
8807 {
8808         int (*unsync)(struct hclge_vport *vport, const unsigned char *addr);
8809         struct hclge_mac_node *mac_node, *tmp;
8810         int ret;
8811
8812         if (mac_type == HCLGE_MAC_ADDR_UC)
8813                 unsync = hclge_rm_uc_addr_common;
8814         else
8815                 unsync = hclge_rm_mc_addr_common;
8816
8817         list_for_each_entry_safe(mac_node, tmp, list, node) {
8818                 ret = unsync(vport, mac_node->mac_addr);
8819                 if (!ret || ret == -ENOENT) {
8820                         list_del(&mac_node->node);
8821                         kfree(mac_node);
8822                 } else {
8823                         set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE,
8824                                 &vport->state);
8825                         break;
8826                 }
8827         }
8828 }
8829
8830 static bool hclge_sync_from_add_list(struct list_head *add_list,
8831                                      struct list_head *mac_list)
8832 {
8833         struct hclge_mac_node *mac_node, *tmp, *new_node;
8834         bool all_added = true;
8835
8836         list_for_each_entry_safe(mac_node, tmp, add_list, node) {
8837                 if (mac_node->state == HCLGE_MAC_TO_ADD)
8838                         all_added = false;
8839
8840                 /* if the mac address from tmp_add_list is not in the
8841                  * uc/mc_mac_list, it means have received a TO_DEL request
8842                  * during the time window of adding the mac address into mac
8843                  * table. if mac_node state is ACTIVE, then change it to TO_DEL,
8844                  * then it will be removed at next time. else it must be TO_ADD,
8845                  * this address hasn't been added into mac table,
8846                  * so just remove the mac node.
8847                  */
8848                 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr);
8849                 if (new_node) {
8850                         hclge_update_mac_node(new_node, mac_node->state);
8851                         list_del(&mac_node->node);
8852                         kfree(mac_node);
8853                 } else if (mac_node->state == HCLGE_MAC_ACTIVE) {
8854                         mac_node->state = HCLGE_MAC_TO_DEL;
8855                         list_move_tail(&mac_node->node, mac_list);
8856                 } else {
8857                         list_del(&mac_node->node);
8858                         kfree(mac_node);
8859                 }
8860         }
8861
8862         return all_added;
8863 }
8864
8865 static void hclge_sync_from_del_list(struct list_head *del_list,
8866                                      struct list_head *mac_list)
8867 {
8868         struct hclge_mac_node *mac_node, *tmp, *new_node;
8869
8870         list_for_each_entry_safe(mac_node, tmp, del_list, node) {
8871                 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr);
8872                 if (new_node) {
8873                         /* If the mac addr exists in the mac list, it means
8874                          * received a new TO_ADD request during the time window
8875                          * of configuring the mac address. For the mac node
8876                          * state is TO_ADD, and the address is already in the
8877                          * in the hardware(due to delete fail), so we just need
8878                          * to change the mac node state to ACTIVE.
8879                          */
8880                         new_node->state = HCLGE_MAC_ACTIVE;
8881                         list_del(&mac_node->node);
8882                         kfree(mac_node);
8883                 } else {
8884                         list_move_tail(&mac_node->node, mac_list);
8885                 }
8886         }
8887 }
8888
8889 static void hclge_update_overflow_flags(struct hclge_vport *vport,
8890                                         enum HCLGE_MAC_ADDR_TYPE mac_type,
8891                                         bool is_all_added)
8892 {
8893         if (mac_type == HCLGE_MAC_ADDR_UC) {
8894                 if (is_all_added)
8895                         vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_UPE;
8896                 else
8897                         vport->overflow_promisc_flags |= HNAE3_OVERFLOW_UPE;
8898         } else {
8899                 if (is_all_added)
8900                         vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_MPE;
8901                 else
8902                         vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE;
8903         }
8904 }
8905
8906 static void hclge_sync_vport_mac_table(struct hclge_vport *vport,
8907                                        enum HCLGE_MAC_ADDR_TYPE mac_type)
8908 {
8909         struct hclge_mac_node *mac_node, *tmp, *new_node;
8910         struct list_head tmp_add_list, tmp_del_list;
8911         struct list_head *list;
8912         bool all_added;
8913
8914         INIT_LIST_HEAD(&tmp_add_list);
8915         INIT_LIST_HEAD(&tmp_del_list);
8916
8917         /* move the mac addr to the tmp_add_list and tmp_del_list, then
8918          * we can add/delete these mac addr outside the spin lock
8919          */
8920         list = (mac_type == HCLGE_MAC_ADDR_UC) ?
8921                 &vport->uc_mac_list : &vport->mc_mac_list;
8922
8923         spin_lock_bh(&vport->mac_list_lock);
8924
8925         list_for_each_entry_safe(mac_node, tmp, list, node) {
8926                 switch (mac_node->state) {
8927                 case HCLGE_MAC_TO_DEL:
8928                         list_move_tail(&mac_node->node, &tmp_del_list);
8929                         break;
8930                 case HCLGE_MAC_TO_ADD:
8931                         new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC);
8932                         if (!new_node)
8933                                 goto stop_traverse;
8934                         ether_addr_copy(new_node->mac_addr, mac_node->mac_addr);
8935                         new_node->state = mac_node->state;
8936                         list_add_tail(&new_node->node, &tmp_add_list);
8937                         break;
8938                 default:
8939                         break;
8940                 }
8941         }
8942
8943 stop_traverse:
8944         spin_unlock_bh(&vport->mac_list_lock);
8945
8946         /* delete first, in order to get max mac table space for adding */
8947         hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type);
8948         hclge_sync_vport_mac_list(vport, &tmp_add_list, mac_type);
8949
8950         /* if some mac addresses were added/deleted fail, move back to the
8951          * mac_list, and retry at next time.
8952          */
8953         spin_lock_bh(&vport->mac_list_lock);
8954
8955         hclge_sync_from_del_list(&tmp_del_list, list);
8956         all_added = hclge_sync_from_add_list(&tmp_add_list, list);
8957
8958         spin_unlock_bh(&vport->mac_list_lock);
8959
8960         hclge_update_overflow_flags(vport, mac_type, all_added);
8961 }
8962
8963 static bool hclge_need_sync_mac_table(struct hclge_vport *vport)
8964 {
8965         struct hclge_dev *hdev = vport->back;
8966
8967         if (test_bit(vport->vport_id, hdev->vport_config_block))
8968                 return false;
8969
8970         if (test_and_clear_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state))
8971                 return true;
8972
8973         return false;
8974 }
8975
8976 static void hclge_sync_mac_table(struct hclge_dev *hdev)
8977 {
8978         int i;
8979
8980         for (i = 0; i < hdev->num_alloc_vport; i++) {
8981                 struct hclge_vport *vport = &hdev->vport[i];
8982
8983                 if (!hclge_need_sync_mac_table(vport))
8984                         continue;
8985
8986                 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_UC);
8987                 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_MC);
8988         }
8989 }
8990
8991 static void hclge_build_del_list(struct list_head *list,
8992                                  bool is_del_list,
8993                                  struct list_head *tmp_del_list)
8994 {
8995         struct hclge_mac_node *mac_cfg, *tmp;
8996
8997         list_for_each_entry_safe(mac_cfg, tmp, list, node) {
8998                 switch (mac_cfg->state) {
8999                 case HCLGE_MAC_TO_DEL:
9000                 case HCLGE_MAC_ACTIVE:
9001                         list_move_tail(&mac_cfg->node, tmp_del_list);
9002                         break;
9003                 case HCLGE_MAC_TO_ADD:
9004                         if (is_del_list) {
9005                                 list_del(&mac_cfg->node);
9006                                 kfree(mac_cfg);
9007                         }
9008                         break;
9009                 }
9010         }
9011 }
9012
9013 static void hclge_unsync_del_list(struct hclge_vport *vport,
9014                                   int (*unsync)(struct hclge_vport *vport,
9015                                                 const unsigned char *addr),
9016                                   bool is_del_list,
9017                                   struct list_head *tmp_del_list)
9018 {
9019         struct hclge_mac_node *mac_cfg, *tmp;
9020         int ret;
9021
9022         list_for_each_entry_safe(mac_cfg, tmp, tmp_del_list, node) {
9023                 ret = unsync(vport, mac_cfg->mac_addr);
9024                 if (!ret || ret == -ENOENT) {
9025                         /* clear all mac addr from hardware, but remain these
9026                          * mac addr in the mac list, and restore them after
9027                          * vf reset finished.
9028                          */
9029                         if (!is_del_list &&
9030                             mac_cfg->state == HCLGE_MAC_ACTIVE) {
9031                                 mac_cfg->state = HCLGE_MAC_TO_ADD;
9032                         } else {
9033                                 list_del(&mac_cfg->node);
9034                                 kfree(mac_cfg);
9035                         }
9036                 } else if (is_del_list) {
9037                         mac_cfg->state = HCLGE_MAC_TO_DEL;
9038                 }
9039         }
9040 }
9041
9042 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list,
9043                                   enum HCLGE_MAC_ADDR_TYPE mac_type)
9044 {
9045         int (*unsync)(struct hclge_vport *vport, const unsigned char *addr);
9046         struct hclge_dev *hdev = vport->back;
9047         struct list_head tmp_del_list, *list;
9048
9049         if (mac_type == HCLGE_MAC_ADDR_UC) {
9050                 list = &vport->uc_mac_list;
9051                 unsync = hclge_rm_uc_addr_common;
9052         } else {
9053                 list = &vport->mc_mac_list;
9054                 unsync = hclge_rm_mc_addr_common;
9055         }
9056
9057         INIT_LIST_HEAD(&tmp_del_list);
9058
9059         if (!is_del_list)
9060                 set_bit(vport->vport_id, hdev->vport_config_block);
9061
9062         spin_lock_bh(&vport->mac_list_lock);
9063
9064         hclge_build_del_list(list, is_del_list, &tmp_del_list);
9065
9066         spin_unlock_bh(&vport->mac_list_lock);
9067
9068         hclge_unsync_del_list(vport, unsync, is_del_list, &tmp_del_list);
9069
9070         spin_lock_bh(&vport->mac_list_lock);
9071
9072         hclge_sync_from_del_list(&tmp_del_list, list);
9073
9074         spin_unlock_bh(&vport->mac_list_lock);
9075 }
9076
9077 /* remove all mac address when uninitailize */
9078 static void hclge_uninit_vport_mac_list(struct hclge_vport *vport,
9079                                         enum HCLGE_MAC_ADDR_TYPE mac_type)
9080 {
9081         struct hclge_mac_node *mac_node, *tmp;
9082         struct hclge_dev *hdev = vport->back;
9083         struct list_head tmp_del_list, *list;
9084
9085         INIT_LIST_HEAD(&tmp_del_list);
9086
9087         list = (mac_type == HCLGE_MAC_ADDR_UC) ?
9088                 &vport->uc_mac_list : &vport->mc_mac_list;
9089
9090         spin_lock_bh(&vport->mac_list_lock);
9091
9092         list_for_each_entry_safe(mac_node, tmp, list, node) {
9093                 switch (mac_node->state) {
9094                 case HCLGE_MAC_TO_DEL:
9095                 case HCLGE_MAC_ACTIVE:
9096                         list_move_tail(&mac_node->node, &tmp_del_list);
9097                         break;
9098                 case HCLGE_MAC_TO_ADD:
9099                         list_del(&mac_node->node);
9100                         kfree(mac_node);
9101                         break;
9102                 }
9103         }
9104
9105         spin_unlock_bh(&vport->mac_list_lock);
9106
9107         hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type);
9108
9109         if (!list_empty(&tmp_del_list))
9110                 dev_warn(&hdev->pdev->dev,
9111                          "uninit %s mac list for vport %u not completely.\n",
9112                          mac_type == HCLGE_MAC_ADDR_UC ? "uc" : "mc",
9113                          vport->vport_id);
9114
9115         list_for_each_entry_safe(mac_node, tmp, &tmp_del_list, node) {
9116                 list_del(&mac_node->node);
9117                 kfree(mac_node);
9118         }
9119 }
9120
9121 static void hclge_uninit_mac_table(struct hclge_dev *hdev)
9122 {
9123         struct hclge_vport *vport;
9124         int i;
9125
9126         for (i = 0; i < hdev->num_alloc_vport; i++) {
9127                 vport = &hdev->vport[i];
9128                 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_UC);
9129                 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_MC);
9130         }
9131 }
9132
9133 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev,
9134                                               u16 cmdq_resp, u8 resp_code)
9135 {
9136 #define HCLGE_ETHERTYPE_SUCCESS_ADD             0
9137 #define HCLGE_ETHERTYPE_ALREADY_ADD             1
9138 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW        2
9139 #define HCLGE_ETHERTYPE_KEY_CONFLICT            3
9140
9141         int return_status;
9142
9143         if (cmdq_resp) {
9144                 dev_err(&hdev->pdev->dev,
9145                         "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
9146                         cmdq_resp);
9147                 return -EIO;
9148         }
9149
9150         switch (resp_code) {
9151         case HCLGE_ETHERTYPE_SUCCESS_ADD:
9152         case HCLGE_ETHERTYPE_ALREADY_ADD:
9153                 return_status = 0;
9154                 break;
9155         case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW:
9156                 dev_err(&hdev->pdev->dev,
9157                         "add mac ethertype failed for manager table overflow.\n");
9158                 return_status = -EIO;
9159                 break;
9160         case HCLGE_ETHERTYPE_KEY_CONFLICT:
9161                 dev_err(&hdev->pdev->dev,
9162                         "add mac ethertype failed for key conflict.\n");
9163                 return_status = -EIO;
9164                 break;
9165         default:
9166                 dev_err(&hdev->pdev->dev,
9167                         "add mac ethertype failed for undefined, code=%u.\n",
9168                         resp_code);
9169                 return_status = -EIO;
9170         }
9171
9172         return return_status;
9173 }
9174
9175 static int hclge_set_vf_mac(struct hnae3_handle *handle, int vf,
9176                             u8 *mac_addr)
9177 {
9178         struct hclge_vport *vport = hclge_get_vport(handle);
9179         char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
9180         struct hclge_dev *hdev = vport->back;
9181
9182         vport = hclge_get_vf_vport(hdev, vf);
9183         if (!vport)
9184                 return -EINVAL;
9185
9186         hnae3_format_mac_addr(format_mac_addr, mac_addr);
9187         if (ether_addr_equal(mac_addr, vport->vf_info.mac)) {
9188                 dev_info(&hdev->pdev->dev,
9189                          "Specified MAC(=%s) is same as before, no change committed!\n",
9190                          format_mac_addr);
9191                 return 0;
9192         }
9193
9194         ether_addr_copy(vport->vf_info.mac, mac_addr);
9195
9196         /* there is a timewindow for PF to know VF unalive, it may
9197          * cause send mailbox fail, but it doesn't matter, VF will
9198          * query it when reinit.
9199          */
9200         if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) {
9201                 dev_info(&hdev->pdev->dev,
9202                          "MAC of VF %d has been set to %s, and it will be reinitialized!\n",
9203                          vf, format_mac_addr);
9204                 (void)hclge_inform_reset_assert_to_vf(vport);
9205                 return 0;
9206         }
9207
9208         dev_info(&hdev->pdev->dev, "MAC of VF %d has been set to %s\n",
9209                  vf, format_mac_addr);
9210         return 0;
9211 }
9212
9213 static int hclge_add_mgr_tbl(struct hclge_dev *hdev,
9214                              const struct hclge_mac_mgr_tbl_entry_cmd *req)
9215 {
9216         struct hclge_desc desc;
9217         u8 resp_code;
9218         u16 retval;
9219         int ret;
9220
9221         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false);
9222         memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd));
9223
9224         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
9225         if (ret) {
9226                 dev_err(&hdev->pdev->dev,
9227                         "add mac ethertype failed for cmd_send, ret =%d.\n",
9228                         ret);
9229                 return ret;
9230         }
9231
9232         resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
9233         retval = le16_to_cpu(desc.retval);
9234
9235         return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code);
9236 }
9237
9238 static int init_mgr_tbl(struct hclge_dev *hdev)
9239 {
9240         int ret;
9241         int i;
9242
9243         for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) {
9244                 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]);
9245                 if (ret) {
9246                         dev_err(&hdev->pdev->dev,
9247                                 "add mac ethertype failed, ret =%d.\n",
9248                                 ret);
9249                         return ret;
9250                 }
9251         }
9252
9253         return 0;
9254 }
9255
9256 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
9257 {
9258         struct hclge_vport *vport = hclge_get_vport(handle);
9259         struct hclge_dev *hdev = vport->back;
9260
9261         ether_addr_copy(p, hdev->hw.mac.mac_addr);
9262 }
9263
9264 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport,
9265                                        const u8 *old_addr, const u8 *new_addr)
9266 {
9267         struct list_head *list = &vport->uc_mac_list;
9268         struct hclge_mac_node *old_node, *new_node;
9269
9270         new_node = hclge_find_mac_node(list, new_addr);
9271         if (!new_node) {
9272                 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC);
9273                 if (!new_node)
9274                         return -ENOMEM;
9275
9276                 new_node->state = HCLGE_MAC_TO_ADD;
9277                 ether_addr_copy(new_node->mac_addr, new_addr);
9278                 list_add(&new_node->node, list);
9279         } else {
9280                 if (new_node->state == HCLGE_MAC_TO_DEL)
9281                         new_node->state = HCLGE_MAC_ACTIVE;
9282
9283                 /* make sure the new addr is in the list head, avoid dev
9284                  * addr may be not re-added into mac table for the umv space
9285                  * limitation after global/imp reset which will clear mac
9286                  * table by hardware.
9287                  */
9288                 list_move(&new_node->node, list);
9289         }
9290
9291         if (old_addr && !ether_addr_equal(old_addr, new_addr)) {
9292                 old_node = hclge_find_mac_node(list, old_addr);
9293                 if (old_node) {
9294                         if (old_node->state == HCLGE_MAC_TO_ADD) {
9295                                 list_del(&old_node->node);
9296                                 kfree(old_node);
9297                         } else {
9298                                 old_node->state = HCLGE_MAC_TO_DEL;
9299                         }
9300                 }
9301         }
9302
9303         set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state);
9304
9305         return 0;
9306 }
9307
9308 static int hclge_set_mac_addr(struct hnae3_handle *handle, const void *p,
9309                               bool is_first)
9310 {
9311         const unsigned char *new_addr = (const unsigned char *)p;
9312         struct hclge_vport *vport = hclge_get_vport(handle);
9313         char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
9314         struct hclge_dev *hdev = vport->back;
9315         unsigned char *old_addr = NULL;
9316         int ret;
9317
9318         /* mac addr check */
9319         if (is_zero_ether_addr(new_addr) ||
9320             is_broadcast_ether_addr(new_addr) ||
9321             is_multicast_ether_addr(new_addr)) {
9322                 hnae3_format_mac_addr(format_mac_addr, new_addr);
9323                 dev_err(&hdev->pdev->dev,
9324                         "change uc mac err! invalid mac: %s.\n",
9325                          format_mac_addr);
9326                 return -EINVAL;
9327         }
9328
9329         ret = hclge_pause_addr_cfg(hdev, new_addr);
9330         if (ret) {
9331                 dev_err(&hdev->pdev->dev,
9332                         "failed to configure mac pause address, ret = %d\n",
9333                         ret);
9334                 return ret;
9335         }
9336
9337         if (!is_first)
9338                 old_addr = hdev->hw.mac.mac_addr;
9339
9340         spin_lock_bh(&vport->mac_list_lock);
9341         ret = hclge_update_mac_node_for_dev_addr(vport, old_addr, new_addr);
9342         if (ret) {
9343                 hnae3_format_mac_addr(format_mac_addr, new_addr);
9344                 dev_err(&hdev->pdev->dev,
9345                         "failed to change the mac addr:%s, ret = %d\n",
9346                         format_mac_addr, ret);
9347                 spin_unlock_bh(&vport->mac_list_lock);
9348
9349                 if (!is_first)
9350                         hclge_pause_addr_cfg(hdev, old_addr);
9351
9352                 return ret;
9353         }
9354         /* we must update dev addr with spin lock protect, preventing dev addr
9355          * being removed by set_rx_mode path.
9356          */
9357         ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
9358         spin_unlock_bh(&vport->mac_list_lock);
9359
9360         hclge_task_schedule(hdev, 0);
9361
9362         return 0;
9363 }
9364
9365 static int hclge_mii_ioctl(struct hclge_dev *hdev, struct ifreq *ifr, int cmd)
9366 {
9367         struct mii_ioctl_data *data = if_mii(ifr);
9368
9369         if (!hnae3_dev_phy_imp_supported(hdev))
9370                 return -EOPNOTSUPP;
9371
9372         switch (cmd) {
9373         case SIOCGMIIPHY:
9374                 data->phy_id = hdev->hw.mac.phy_addr;
9375                 /* this command reads phy id and register at the same time */
9376                 fallthrough;
9377         case SIOCGMIIREG:
9378                 data->val_out = hclge_read_phy_reg(hdev, data->reg_num);
9379                 return 0;
9380
9381         case SIOCSMIIREG:
9382                 return hclge_write_phy_reg(hdev, data->reg_num, data->val_in);
9383         default:
9384                 return -EOPNOTSUPP;
9385         }
9386 }
9387
9388 static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr,
9389                           int cmd)
9390 {
9391         struct hclge_vport *vport = hclge_get_vport(handle);
9392         struct hclge_dev *hdev = vport->back;
9393
9394         switch (cmd) {
9395         case SIOCGHWTSTAMP:
9396                 return hclge_ptp_get_cfg(hdev, ifr);
9397         case SIOCSHWTSTAMP:
9398                 return hclge_ptp_set_cfg(hdev, ifr);
9399         default:
9400                 if (!hdev->hw.mac.phydev)
9401                         return hclge_mii_ioctl(hdev, ifr, cmd);
9402         }
9403
9404         return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd);
9405 }
9406
9407 static int hclge_set_port_vlan_filter_bypass(struct hclge_dev *hdev, u8 vf_id,
9408                                              bool bypass_en)
9409 {
9410         struct hclge_port_vlan_filter_bypass_cmd *req;
9411         struct hclge_desc desc;
9412         int ret;
9413
9414         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PORT_VLAN_BYPASS, false);
9415         req = (struct hclge_port_vlan_filter_bypass_cmd *)desc.data;
9416         req->vf_id = vf_id;
9417         hnae3_set_bit(req->bypass_state, HCLGE_INGRESS_BYPASS_B,
9418                       bypass_en ? 1 : 0);
9419
9420         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
9421         if (ret)
9422                 dev_err(&hdev->pdev->dev,
9423                         "failed to set vport%u port vlan filter bypass state, ret = %d.\n",
9424                         vf_id, ret);
9425
9426         return ret;
9427 }
9428
9429 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
9430                                       u8 fe_type, bool filter_en, u8 vf_id)
9431 {
9432         struct hclge_vlan_filter_ctrl_cmd *req;
9433         struct hclge_desc desc;
9434         int ret;
9435
9436         /* read current vlan filter parameter */
9437         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, true);
9438         req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
9439         req->vlan_type = vlan_type;
9440         req->vf_id = vf_id;
9441
9442         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
9443         if (ret) {
9444                 dev_err(&hdev->pdev->dev, "failed to get vport%u vlan filter config, ret = %d.\n",
9445                         vf_id, ret);
9446                 return ret;
9447         }
9448
9449         /* modify and write new config parameter */
9450         hclge_comm_cmd_reuse_desc(&desc, false);
9451         req->vlan_fe = filter_en ?
9452                         (req->vlan_fe | fe_type) : (req->vlan_fe & ~fe_type);
9453
9454         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
9455         if (ret)
9456                 dev_err(&hdev->pdev->dev, "failed to set vport%u vlan filter, ret = %d.\n",
9457                         vf_id, ret);
9458
9459         return ret;
9460 }
9461
9462 static int hclge_set_vport_vlan_filter(struct hclge_vport *vport, bool enable)
9463 {
9464         struct hclge_dev *hdev = vport->back;
9465         struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
9466         int ret;
9467
9468         if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
9469                 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
9470                                                   HCLGE_FILTER_FE_EGRESS_V1_B,
9471                                                   enable, vport->vport_id);
9472
9473         ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
9474                                          HCLGE_FILTER_FE_EGRESS, enable,
9475                                          vport->vport_id);
9476         if (ret)
9477                 return ret;
9478
9479         if (test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, ae_dev->caps)) {
9480                 ret = hclge_set_port_vlan_filter_bypass(hdev, vport->vport_id,
9481                                                         !enable);
9482         } else if (!vport->vport_id) {
9483                 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps))
9484                         enable = false;
9485
9486                 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT,
9487                                                  HCLGE_FILTER_FE_INGRESS,
9488                                                  enable, 0);
9489         }
9490
9491         return ret;
9492 }
9493
9494 static bool hclge_need_enable_vport_vlan_filter(struct hclge_vport *vport)
9495 {
9496         struct hnae3_handle *handle = &vport->nic;
9497         struct hclge_vport_vlan_cfg *vlan, *tmp;
9498         struct hclge_dev *hdev = vport->back;
9499
9500         if (vport->vport_id) {
9501                 if (vport->port_base_vlan_cfg.state !=
9502                         HNAE3_PORT_BASE_VLAN_DISABLE)
9503                         return true;
9504
9505                 if (vport->vf_info.trusted && vport->vf_info.request_uc_en)
9506                         return false;
9507         } else if (handle->netdev_flags & HNAE3_USER_UPE) {
9508                 return false;
9509         }
9510
9511         if (!vport->req_vlan_fltr_en)
9512                 return false;
9513
9514         /* compatible with former device, always enable vlan filter */
9515         if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps))
9516                 return true;
9517
9518         list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node)
9519                 if (vlan->vlan_id != 0)
9520                         return true;
9521
9522         return false;
9523 }
9524
9525 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en)
9526 {
9527         struct hclge_dev *hdev = vport->back;
9528         bool need_en;
9529         int ret;
9530
9531         mutex_lock(&hdev->vport_lock);
9532
9533         vport->req_vlan_fltr_en = request_en;
9534
9535         need_en = hclge_need_enable_vport_vlan_filter(vport);
9536         if (need_en == vport->cur_vlan_fltr_en) {
9537                 mutex_unlock(&hdev->vport_lock);
9538                 return 0;
9539         }
9540
9541         ret = hclge_set_vport_vlan_filter(vport, need_en);
9542         if (ret) {
9543                 mutex_unlock(&hdev->vport_lock);
9544                 return ret;
9545         }
9546
9547         vport->cur_vlan_fltr_en = need_en;
9548
9549         mutex_unlock(&hdev->vport_lock);
9550
9551         return 0;
9552 }
9553
9554 static int hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
9555 {
9556         struct hclge_vport *vport = hclge_get_vport(handle);
9557
9558         return hclge_enable_vport_vlan_filter(vport, enable);
9559 }
9560
9561 static int hclge_set_vf_vlan_filter_cmd(struct hclge_dev *hdev, u16 vfid,
9562                                         bool is_kill, u16 vlan,
9563                                         struct hclge_desc *desc)
9564 {
9565         struct hclge_vlan_filter_vf_cfg_cmd *req0;
9566         struct hclge_vlan_filter_vf_cfg_cmd *req1;
9567         u8 vf_byte_val;
9568         u8 vf_byte_off;
9569         int ret;
9570
9571         hclge_cmd_setup_basic_desc(&desc[0],
9572                                    HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
9573         hclge_cmd_setup_basic_desc(&desc[1],
9574                                    HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
9575
9576         desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
9577
9578         vf_byte_off = vfid / 8;
9579         vf_byte_val = 1 << (vfid % 8);
9580
9581         req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
9582         req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
9583
9584         req0->vlan_id  = cpu_to_le16(vlan);
9585         req0->vlan_cfg = is_kill;
9586
9587         if (vf_byte_off < HCLGE_MAX_VF_BYTES)
9588                 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
9589         else
9590                 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
9591
9592         ret = hclge_cmd_send(&hdev->hw, desc, 2);
9593         if (ret) {
9594                 dev_err(&hdev->pdev->dev,
9595                         "Send vf vlan command fail, ret =%d.\n",
9596                         ret);
9597                 return ret;
9598         }
9599
9600         return 0;
9601 }
9602
9603 static int hclge_check_vf_vlan_cmd_status(struct hclge_dev *hdev, u16 vfid,
9604                                           bool is_kill, struct hclge_desc *desc)
9605 {
9606         struct hclge_vlan_filter_vf_cfg_cmd *req;
9607
9608         req = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
9609
9610         if (!is_kill) {
9611 #define HCLGE_VF_VLAN_NO_ENTRY  2
9612                 if (!req->resp_code || req->resp_code == 1)
9613                         return 0;
9614
9615                 if (req->resp_code == HCLGE_VF_VLAN_NO_ENTRY) {
9616                         set_bit(vfid, hdev->vf_vlan_full);
9617                         dev_warn(&hdev->pdev->dev,
9618                                  "vf vlan table is full, vf vlan filter is disabled\n");
9619                         return 0;
9620                 }
9621
9622                 dev_err(&hdev->pdev->dev,
9623                         "Add vf vlan filter fail, ret =%u.\n",
9624                         req->resp_code);
9625         } else {
9626 #define HCLGE_VF_VLAN_DEL_NO_FOUND      1
9627                 if (!req->resp_code)
9628                         return 0;
9629
9630                 /* vf vlan filter is disabled when vf vlan table is full,
9631                  * then new vlan id will not be added into vf vlan table.
9632                  * Just return 0 without warning, avoid massive verbose
9633                  * print logs when unload.
9634                  */
9635                 if (req->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND)
9636                         return 0;
9637
9638                 dev_err(&hdev->pdev->dev,
9639                         "Kill vf vlan filter fail, ret =%u.\n",
9640                         req->resp_code);
9641         }
9642
9643         return -EIO;
9644 }
9645
9646 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, u16 vfid,
9647                                     bool is_kill, u16 vlan)
9648 {
9649         struct hclge_vport *vport = &hdev->vport[vfid];
9650         struct hclge_desc desc[2];
9651         int ret;
9652
9653         /* if vf vlan table is full, firmware will close vf vlan filter, it
9654          * is unable and unnecessary to add new vlan id to vf vlan filter.
9655          * If spoof check is enable, and vf vlan is full, it shouldn't add
9656          * new vlan, because tx packets with these vlan id will be dropped.
9657          */
9658         if (test_bit(vfid, hdev->vf_vlan_full) && !is_kill) {
9659                 if (vport->vf_info.spoofchk && vlan) {
9660                         dev_err(&hdev->pdev->dev,
9661                                 "Can't add vlan due to spoof check is on and vf vlan table is full\n");
9662                         return -EPERM;
9663                 }
9664                 return 0;
9665         }
9666
9667         ret = hclge_set_vf_vlan_filter_cmd(hdev, vfid, is_kill, vlan, desc);
9668         if (ret)
9669                 return ret;
9670
9671         return hclge_check_vf_vlan_cmd_status(hdev, vfid, is_kill, desc);
9672 }
9673
9674 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto,
9675                                       u16 vlan_id, bool is_kill)
9676 {
9677         struct hclge_vlan_filter_pf_cfg_cmd *req;
9678         struct hclge_desc desc;
9679         u8 vlan_offset_byte_val;
9680         u8 vlan_offset_byte;
9681         u8 vlan_offset_160;
9682         int ret;
9683
9684         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
9685
9686         vlan_offset_160 = vlan_id / HCLGE_VLAN_ID_OFFSET_STEP;
9687         vlan_offset_byte = (vlan_id % HCLGE_VLAN_ID_OFFSET_STEP) /
9688                            HCLGE_VLAN_BYTE_SIZE;
9689         vlan_offset_byte_val = 1 << (vlan_id % HCLGE_VLAN_BYTE_SIZE);
9690
9691         req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
9692         req->vlan_offset = vlan_offset_160;
9693         req->vlan_cfg = is_kill;
9694         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
9695
9696         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
9697         if (ret)
9698                 dev_err(&hdev->pdev->dev,
9699                         "port vlan command, send fail, ret =%d.\n", ret);
9700         return ret;
9701 }
9702
9703 static bool hclge_need_update_port_vlan(struct hclge_dev *hdev, u16 vport_id,
9704                                         u16 vlan_id, bool is_kill)
9705 {
9706         /* vlan 0 may be added twice when 8021q module is enabled */
9707         if (!is_kill && !vlan_id &&
9708             test_bit(vport_id, hdev->vlan_table[vlan_id]))
9709                 return false;
9710
9711         if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) {
9712                 dev_warn(&hdev->pdev->dev,
9713                          "Add port vlan failed, vport %u is already in vlan %u\n",
9714                          vport_id, vlan_id);
9715                 return false;
9716         }
9717
9718         if (is_kill &&
9719             !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) {
9720                 dev_warn(&hdev->pdev->dev,
9721                          "Delete port vlan failed, vport %u is not in vlan %u\n",
9722                          vport_id, vlan_id);
9723                 return false;
9724         }
9725
9726         return true;
9727 }
9728
9729 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto,
9730                                     u16 vport_id, u16 vlan_id,
9731                                     bool is_kill)
9732 {
9733         u16 vport_idx, vport_num = 0;
9734         int ret;
9735
9736         if (is_kill && !vlan_id)
9737                 return 0;
9738
9739         if (vlan_id >= VLAN_N_VID)
9740                 return -EINVAL;
9741
9742         ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id);
9743         if (ret) {
9744                 dev_err(&hdev->pdev->dev,
9745                         "Set %u vport vlan filter config fail, ret =%d.\n",
9746                         vport_id, ret);
9747                 return ret;
9748         }
9749
9750         if (!hclge_need_update_port_vlan(hdev, vport_id, vlan_id, is_kill))
9751                 return 0;
9752
9753         for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM)
9754                 vport_num++;
9755
9756         if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1))
9757                 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id,
9758                                                  is_kill);
9759
9760         return ret;
9761 }
9762
9763 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
9764 {
9765         struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
9766         struct hclge_vport_vtag_tx_cfg_cmd *req;
9767         struct hclge_dev *hdev = vport->back;
9768         struct hclge_desc desc;
9769         u16 bmap_index;
9770         int status;
9771
9772         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
9773
9774         req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
9775         req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
9776         req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
9777         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B,
9778                       vcfg->accept_tag1 ? 1 : 0);
9779         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B,
9780                       vcfg->accept_untag1 ? 1 : 0);
9781         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B,
9782                       vcfg->accept_tag2 ? 1 : 0);
9783         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B,
9784                       vcfg->accept_untag2 ? 1 : 0);
9785         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
9786                       vcfg->insert_tag1_en ? 1 : 0);
9787         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
9788                       vcfg->insert_tag2_en ? 1 : 0);
9789         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_TAG_SHIFT_MODE_EN_B,
9790                       vcfg->tag_shift_mode_en ? 1 : 0);
9791         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
9792
9793         req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
9794         bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD /
9795                         HCLGE_VF_NUM_PER_BYTE;
9796         req->vf_bitmap[bmap_index] =
9797                 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
9798
9799         status = hclge_cmd_send(&hdev->hw, &desc, 1);
9800         if (status)
9801                 dev_err(&hdev->pdev->dev,
9802                         "Send port txvlan cfg command fail, ret =%d\n",
9803                         status);
9804
9805         return status;
9806 }
9807
9808 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
9809 {
9810         struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
9811         struct hclge_vport_vtag_rx_cfg_cmd *req;
9812         struct hclge_dev *hdev = vport->back;
9813         struct hclge_desc desc;
9814         u16 bmap_index;
9815         int status;
9816
9817         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
9818
9819         req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
9820         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
9821                       vcfg->strip_tag1_en ? 1 : 0);
9822         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
9823                       vcfg->strip_tag2_en ? 1 : 0);
9824         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
9825                       vcfg->vlan1_vlan_prionly ? 1 : 0);
9826         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
9827                       vcfg->vlan2_vlan_prionly ? 1 : 0);
9828         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG1_EN_B,
9829                       vcfg->strip_tag1_discard_en ? 1 : 0);
9830         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG2_EN_B,
9831                       vcfg->strip_tag2_discard_en ? 1 : 0);
9832
9833         req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
9834         bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD /
9835                         HCLGE_VF_NUM_PER_BYTE;
9836         req->vf_bitmap[bmap_index] =
9837                 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
9838
9839         status = hclge_cmd_send(&hdev->hw, &desc, 1);
9840         if (status)
9841                 dev_err(&hdev->pdev->dev,
9842                         "Send port rxvlan cfg command fail, ret =%d\n",
9843                         status);
9844
9845         return status;
9846 }
9847
9848 static int hclge_vlan_offload_cfg(struct hclge_vport *vport,
9849                                   u16 port_base_vlan_state,
9850                                   u16 vlan_tag, u8 qos)
9851 {
9852         int ret;
9853
9854         if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) {
9855                 vport->txvlan_cfg.accept_tag1 = true;
9856                 vport->txvlan_cfg.insert_tag1_en = false;
9857                 vport->txvlan_cfg.default_tag1 = 0;
9858         } else {
9859                 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(vport->nic.pdev);
9860
9861                 vport->txvlan_cfg.accept_tag1 =
9862                         ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3;
9863                 vport->txvlan_cfg.insert_tag1_en = true;
9864                 vport->txvlan_cfg.default_tag1 = (qos << VLAN_PRIO_SHIFT) |
9865                                                  vlan_tag;
9866         }
9867
9868         vport->txvlan_cfg.accept_untag1 = true;
9869
9870         /* accept_tag2 and accept_untag2 are not supported on
9871          * pdev revision(0x20), new revision support them,
9872          * this two fields can not be configured by user.
9873          */
9874         vport->txvlan_cfg.accept_tag2 = true;
9875         vport->txvlan_cfg.accept_untag2 = true;
9876         vport->txvlan_cfg.insert_tag2_en = false;
9877         vport->txvlan_cfg.default_tag2 = 0;
9878         vport->txvlan_cfg.tag_shift_mode_en = true;
9879
9880         if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) {
9881                 vport->rxvlan_cfg.strip_tag1_en = false;
9882                 vport->rxvlan_cfg.strip_tag2_en =
9883                                 vport->rxvlan_cfg.rx_vlan_offload_en;
9884                 vport->rxvlan_cfg.strip_tag2_discard_en = false;
9885         } else {
9886                 vport->rxvlan_cfg.strip_tag1_en =
9887                                 vport->rxvlan_cfg.rx_vlan_offload_en;
9888                 vport->rxvlan_cfg.strip_tag2_en = true;
9889                 vport->rxvlan_cfg.strip_tag2_discard_en = true;
9890         }
9891
9892         vport->rxvlan_cfg.strip_tag1_discard_en = false;
9893         vport->rxvlan_cfg.vlan1_vlan_prionly = false;
9894         vport->rxvlan_cfg.vlan2_vlan_prionly = false;
9895
9896         ret = hclge_set_vlan_tx_offload_cfg(vport);
9897         if (ret)
9898                 return ret;
9899
9900         return hclge_set_vlan_rx_offload_cfg(vport);
9901 }
9902
9903 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
9904 {
9905         struct hclge_rx_vlan_type_cfg_cmd *rx_req;
9906         struct hclge_tx_vlan_type_cfg_cmd *tx_req;
9907         struct hclge_desc desc;
9908         int status;
9909
9910         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
9911         rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
9912         rx_req->ot_fst_vlan_type =
9913                 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
9914         rx_req->ot_sec_vlan_type =
9915                 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
9916         rx_req->in_fst_vlan_type =
9917                 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
9918         rx_req->in_sec_vlan_type =
9919                 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
9920
9921         status = hclge_cmd_send(&hdev->hw, &desc, 1);
9922         if (status) {
9923                 dev_err(&hdev->pdev->dev,
9924                         "Send rxvlan protocol type command fail, ret =%d\n",
9925                         status);
9926                 return status;
9927         }
9928
9929         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
9930
9931         tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data;
9932         tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
9933         tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
9934
9935         status = hclge_cmd_send(&hdev->hw, &desc, 1);
9936         if (status)
9937                 dev_err(&hdev->pdev->dev,
9938                         "Send txvlan protocol type command fail, ret =%d\n",
9939                         status);
9940
9941         return status;
9942 }
9943
9944 static int hclge_init_vlan_filter(struct hclge_dev *hdev)
9945 {
9946         struct hclge_vport *vport;
9947         int ret;
9948         int i;
9949
9950         if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
9951                 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
9952                                                   HCLGE_FILTER_FE_EGRESS_V1_B,
9953                                                   true, 0);
9954
9955         /* for revision 0x21, vf vlan filter is per function */
9956         for (i = 0; i < hdev->num_alloc_vport; i++) {
9957                 vport = &hdev->vport[i];
9958                 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
9959                                                  HCLGE_FILTER_FE_EGRESS, true,
9960                                                  vport->vport_id);
9961                 if (ret)
9962                         return ret;
9963                 vport->cur_vlan_fltr_en = true;
9964         }
9965
9966         return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT,
9967                                           HCLGE_FILTER_FE_INGRESS, true, 0);
9968 }
9969
9970 static int hclge_init_vlan_type(struct hclge_dev *hdev)
9971 {
9972         hdev->vlan_type_cfg.rx_in_fst_vlan_type = ETH_P_8021Q;
9973         hdev->vlan_type_cfg.rx_in_sec_vlan_type = ETH_P_8021Q;
9974         hdev->vlan_type_cfg.rx_ot_fst_vlan_type = ETH_P_8021Q;
9975         hdev->vlan_type_cfg.rx_ot_sec_vlan_type = ETH_P_8021Q;
9976         hdev->vlan_type_cfg.tx_ot_vlan_type = ETH_P_8021Q;
9977         hdev->vlan_type_cfg.tx_in_vlan_type = ETH_P_8021Q;
9978
9979         return hclge_set_vlan_protocol_type(hdev);
9980 }
9981
9982 static int hclge_init_vport_vlan_offload(struct hclge_dev *hdev)
9983 {
9984         struct hclge_port_base_vlan_config *cfg;
9985         struct hclge_vport *vport;
9986         int ret;
9987         int i;
9988
9989         for (i = 0; i < hdev->num_alloc_vport; i++) {
9990                 vport = &hdev->vport[i];
9991                 cfg = &vport->port_base_vlan_cfg;
9992
9993                 ret = hclge_vlan_offload_cfg(vport, cfg->state,
9994                                              cfg->vlan_info.vlan_tag,
9995                                              cfg->vlan_info.qos);
9996                 if (ret)
9997                         return ret;
9998         }
9999         return 0;
10000 }
10001
10002 static int hclge_init_vlan_config(struct hclge_dev *hdev)
10003 {
10004         struct hnae3_handle *handle = &hdev->vport[0].nic;
10005         int ret;
10006
10007         ret = hclge_init_vlan_filter(hdev);
10008         if (ret)
10009                 return ret;
10010
10011         ret = hclge_init_vlan_type(hdev);
10012         if (ret)
10013                 return ret;
10014
10015         ret = hclge_init_vport_vlan_offload(hdev);
10016         if (ret)
10017                 return ret;
10018
10019         return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
10020 }
10021
10022 static void hclge_add_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id,
10023                                        bool writen_to_tbl)
10024 {
10025         struct hclge_vport_vlan_cfg *vlan, *tmp;
10026         struct hclge_dev *hdev = vport->back;
10027
10028         mutex_lock(&hdev->vport_lock);
10029
10030         list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
10031                 if (vlan->vlan_id == vlan_id) {
10032                         mutex_unlock(&hdev->vport_lock);
10033                         return;
10034                 }
10035         }
10036
10037         vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
10038         if (!vlan) {
10039                 mutex_unlock(&hdev->vport_lock);
10040                 return;
10041         }
10042
10043         vlan->hd_tbl_status = writen_to_tbl;
10044         vlan->vlan_id = vlan_id;
10045
10046         list_add_tail(&vlan->node, &vport->vlan_list);
10047         mutex_unlock(&hdev->vport_lock);
10048 }
10049
10050 static int hclge_add_vport_all_vlan_table(struct hclge_vport *vport)
10051 {
10052         struct hclge_vport_vlan_cfg *vlan, *tmp;
10053         struct hclge_dev *hdev = vport->back;
10054         int ret;
10055
10056         mutex_lock(&hdev->vport_lock);
10057
10058         list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
10059                 if (!vlan->hd_tbl_status) {
10060                         ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q),
10061                                                        vport->vport_id,
10062                                                        vlan->vlan_id, false);
10063                         if (ret) {
10064                                 dev_err(&hdev->pdev->dev,
10065                                         "restore vport vlan list failed, ret=%d\n",
10066                                         ret);
10067
10068                                 mutex_unlock(&hdev->vport_lock);
10069                                 return ret;
10070                         }
10071                 }
10072                 vlan->hd_tbl_status = true;
10073         }
10074
10075         mutex_unlock(&hdev->vport_lock);
10076
10077         return 0;
10078 }
10079
10080 static void hclge_rm_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id,
10081                                       bool is_write_tbl)
10082 {
10083         struct hclge_vport_vlan_cfg *vlan, *tmp;
10084         struct hclge_dev *hdev = vport->back;
10085
10086         mutex_lock(&hdev->vport_lock);
10087
10088         list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
10089                 if (vlan->vlan_id == vlan_id) {
10090                         if (is_write_tbl && vlan->hd_tbl_status)
10091                                 hclge_set_vlan_filter_hw(hdev,
10092                                                          htons(ETH_P_8021Q),
10093                                                          vport->vport_id,
10094                                                          vlan_id,
10095                                                          true);
10096
10097                         list_del(&vlan->node);
10098                         kfree(vlan);
10099                         break;
10100                 }
10101         }
10102
10103         mutex_unlock(&hdev->vport_lock);
10104 }
10105
10106 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list)
10107 {
10108         struct hclge_vport_vlan_cfg *vlan, *tmp;
10109         struct hclge_dev *hdev = vport->back;
10110
10111         mutex_lock(&hdev->vport_lock);
10112
10113         list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
10114                 if (vlan->hd_tbl_status)
10115                         hclge_set_vlan_filter_hw(hdev,
10116                                                  htons(ETH_P_8021Q),
10117                                                  vport->vport_id,
10118                                                  vlan->vlan_id,
10119                                                  true);
10120
10121                 vlan->hd_tbl_status = false;
10122                 if (is_del_list) {
10123                         list_del(&vlan->node);
10124                         kfree(vlan);
10125                 }
10126         }
10127         clear_bit(vport->vport_id, hdev->vf_vlan_full);
10128         mutex_unlock(&hdev->vport_lock);
10129 }
10130
10131 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev)
10132 {
10133         struct hclge_vport_vlan_cfg *vlan, *tmp;
10134         struct hclge_vport *vport;
10135         int i;
10136
10137         mutex_lock(&hdev->vport_lock);
10138
10139         for (i = 0; i < hdev->num_alloc_vport; i++) {
10140                 vport = &hdev->vport[i];
10141                 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
10142                         list_del(&vlan->node);
10143                         kfree(vlan);
10144                 }
10145         }
10146
10147         mutex_unlock(&hdev->vport_lock);
10148 }
10149
10150 void hclge_restore_vport_port_base_vlan_config(struct hclge_dev *hdev)
10151 {
10152         struct hclge_vlan_info *vlan_info;
10153         struct hclge_vport *vport;
10154         u16 vlan_proto;
10155         u16 vlan_id;
10156         u16 state;
10157         int vf_id;
10158         int ret;
10159
10160         /* PF should restore all vfs port base vlan */
10161         for (vf_id = 0; vf_id < hdev->num_alloc_vfs; vf_id++) {
10162                 vport = &hdev->vport[vf_id + HCLGE_VF_VPORT_START_NUM];
10163                 vlan_info = vport->port_base_vlan_cfg.tbl_sta ?
10164                             &vport->port_base_vlan_cfg.vlan_info :
10165                             &vport->port_base_vlan_cfg.old_vlan_info;
10166
10167                 vlan_id = vlan_info->vlan_tag;
10168                 vlan_proto = vlan_info->vlan_proto;
10169                 state = vport->port_base_vlan_cfg.state;
10170
10171                 if (state != HNAE3_PORT_BASE_VLAN_DISABLE) {
10172                         clear_bit(vport->vport_id, hdev->vlan_table[vlan_id]);
10173                         ret = hclge_set_vlan_filter_hw(hdev, htons(vlan_proto),
10174                                                        vport->vport_id,
10175                                                        vlan_id, false);
10176                         vport->port_base_vlan_cfg.tbl_sta = ret == 0;
10177                 }
10178         }
10179 }
10180
10181 void hclge_restore_vport_vlan_table(struct hclge_vport *vport)
10182 {
10183         struct hclge_vport_vlan_cfg *vlan, *tmp;
10184         struct hclge_dev *hdev = vport->back;
10185         int ret;
10186
10187         mutex_lock(&hdev->vport_lock);
10188
10189         if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) {
10190                 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
10191                         ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q),
10192                                                        vport->vport_id,
10193                                                        vlan->vlan_id, false);
10194                         if (ret)
10195                                 break;
10196                         vlan->hd_tbl_status = true;
10197                 }
10198         }
10199
10200         mutex_unlock(&hdev->vport_lock);
10201 }
10202
10203 /* For global reset and imp reset, hardware will clear the mac table,
10204  * so we change the mac address state from ACTIVE to TO_ADD, then they
10205  * can be restored in the service task after reset complete. Furtherly,
10206  * the mac addresses with state TO_DEL or DEL_FAIL are unnecessary to
10207  * be restored after reset, so just remove these mac nodes from mac_list.
10208  */
10209 static void hclge_mac_node_convert_for_reset(struct list_head *list)
10210 {
10211         struct hclge_mac_node *mac_node, *tmp;
10212
10213         list_for_each_entry_safe(mac_node, tmp, list, node) {
10214                 if (mac_node->state == HCLGE_MAC_ACTIVE) {
10215                         mac_node->state = HCLGE_MAC_TO_ADD;
10216                 } else if (mac_node->state == HCLGE_MAC_TO_DEL) {
10217                         list_del(&mac_node->node);
10218                         kfree(mac_node);
10219                 }
10220         }
10221 }
10222
10223 void hclge_restore_mac_table_common(struct hclge_vport *vport)
10224 {
10225         spin_lock_bh(&vport->mac_list_lock);
10226
10227         hclge_mac_node_convert_for_reset(&vport->uc_mac_list);
10228         hclge_mac_node_convert_for_reset(&vport->mc_mac_list);
10229         set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state);
10230
10231         spin_unlock_bh(&vport->mac_list_lock);
10232 }
10233
10234 static void hclge_restore_hw_table(struct hclge_dev *hdev)
10235 {
10236         struct hclge_vport *vport = &hdev->vport[0];
10237         struct hnae3_handle *handle = &vport->nic;
10238
10239         hclge_restore_mac_table_common(vport);
10240         hclge_restore_vport_port_base_vlan_config(hdev);
10241         hclge_restore_vport_vlan_table(vport);
10242         set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state);
10243         hclge_restore_fd_entries(handle);
10244 }
10245
10246 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
10247 {
10248         struct hclge_vport *vport = hclge_get_vport(handle);
10249
10250         if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) {
10251                 vport->rxvlan_cfg.strip_tag1_en = false;
10252                 vport->rxvlan_cfg.strip_tag2_en = enable;
10253                 vport->rxvlan_cfg.strip_tag2_discard_en = false;
10254         } else {
10255                 vport->rxvlan_cfg.strip_tag1_en = enable;
10256                 vport->rxvlan_cfg.strip_tag2_en = true;
10257                 vport->rxvlan_cfg.strip_tag2_discard_en = true;
10258         }
10259
10260         vport->rxvlan_cfg.strip_tag1_discard_en = false;
10261         vport->rxvlan_cfg.vlan1_vlan_prionly = false;
10262         vport->rxvlan_cfg.vlan2_vlan_prionly = false;
10263         vport->rxvlan_cfg.rx_vlan_offload_en = enable;
10264
10265         return hclge_set_vlan_rx_offload_cfg(vport);
10266 }
10267
10268 static void hclge_set_vport_vlan_fltr_change(struct hclge_vport *vport)
10269 {
10270         struct hclge_dev *hdev = vport->back;
10271
10272         if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps))
10273                 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, &vport->state);
10274 }
10275
10276 static int hclge_update_vlan_filter_entries(struct hclge_vport *vport,
10277                                             u16 port_base_vlan_state,
10278                                             struct hclge_vlan_info *new_info,
10279                                             struct hclge_vlan_info *old_info)
10280 {
10281         struct hclge_dev *hdev = vport->back;
10282         int ret;
10283
10284         if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_ENABLE) {
10285                 hclge_rm_vport_all_vlan_table(vport, false);
10286                 /* force clear VLAN 0 */
10287                 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, true, 0);
10288                 if (ret)
10289                         return ret;
10290                 return hclge_set_vlan_filter_hw(hdev,
10291                                                  htons(new_info->vlan_proto),
10292                                                  vport->vport_id,
10293                                                  new_info->vlan_tag,
10294                                                  false);
10295         }
10296
10297         vport->port_base_vlan_cfg.tbl_sta = false;
10298
10299         /* force add VLAN 0 */
10300         ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, false, 0);
10301         if (ret)
10302                 return ret;
10303
10304         ret = hclge_set_vlan_filter_hw(hdev, htons(old_info->vlan_proto),
10305                                        vport->vport_id, old_info->vlan_tag,
10306                                        true);
10307         if (ret)
10308                 return ret;
10309
10310         return hclge_add_vport_all_vlan_table(vport);
10311 }
10312
10313 static bool hclge_need_update_vlan_filter(const struct hclge_vlan_info *new_cfg,
10314                                           const struct hclge_vlan_info *old_cfg)
10315 {
10316         if (new_cfg->vlan_tag != old_cfg->vlan_tag)
10317                 return true;
10318
10319         if (new_cfg->vlan_tag == 0 && (new_cfg->qos == 0 || old_cfg->qos == 0))
10320                 return true;
10321
10322         return false;
10323 }
10324
10325 static int hclge_modify_port_base_vlan_tag(struct hclge_vport *vport,
10326                                            struct hclge_vlan_info *new_info,
10327                                            struct hclge_vlan_info *old_info)
10328 {
10329         struct hclge_dev *hdev = vport->back;
10330         int ret;
10331
10332         /* add new VLAN tag */
10333         ret = hclge_set_vlan_filter_hw(hdev, htons(new_info->vlan_proto),
10334                                        vport->vport_id, new_info->vlan_tag,
10335                                        false);
10336         if (ret)
10337                 return ret;
10338
10339         vport->port_base_vlan_cfg.tbl_sta = false;
10340         /* remove old VLAN tag */
10341         if (old_info->vlan_tag == 0)
10342                 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id,
10343                                                true, 0);
10344         else
10345                 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q),
10346                                                vport->vport_id,
10347                                                old_info->vlan_tag, true);
10348         if (ret)
10349                 dev_err(&hdev->pdev->dev,
10350                         "failed to clear vport%u port base vlan %u, ret = %d.\n",
10351                         vport->vport_id, old_info->vlan_tag, ret);
10352
10353         return ret;
10354 }
10355
10356 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state,
10357                                     struct hclge_vlan_info *vlan_info)
10358 {
10359         struct hnae3_handle *nic = &vport->nic;
10360         struct hclge_vlan_info *old_vlan_info;
10361         int ret;
10362
10363         old_vlan_info = &vport->port_base_vlan_cfg.vlan_info;
10364
10365         ret = hclge_vlan_offload_cfg(vport, state, vlan_info->vlan_tag,
10366                                      vlan_info->qos);
10367         if (ret)
10368                 return ret;
10369
10370         if (!hclge_need_update_vlan_filter(vlan_info, old_vlan_info))
10371                 goto out;
10372
10373         if (state == HNAE3_PORT_BASE_VLAN_MODIFY)
10374                 ret = hclge_modify_port_base_vlan_tag(vport, vlan_info,
10375                                                       old_vlan_info);
10376         else
10377                 ret = hclge_update_vlan_filter_entries(vport, state, vlan_info,
10378                                                        old_vlan_info);
10379         if (ret)
10380                 return ret;
10381
10382 out:
10383         vport->port_base_vlan_cfg.state = state;
10384         if (state == HNAE3_PORT_BASE_VLAN_DISABLE)
10385                 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE;
10386         else
10387                 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE;
10388
10389         vport->port_base_vlan_cfg.old_vlan_info = *old_vlan_info;
10390         vport->port_base_vlan_cfg.vlan_info = *vlan_info;
10391         vport->port_base_vlan_cfg.tbl_sta = true;
10392         hclge_set_vport_vlan_fltr_change(vport);
10393
10394         return 0;
10395 }
10396
10397 static u16 hclge_get_port_base_vlan_state(struct hclge_vport *vport,
10398                                           enum hnae3_port_base_vlan_state state,
10399                                           u16 vlan, u8 qos)
10400 {
10401         if (state == HNAE3_PORT_BASE_VLAN_DISABLE) {
10402                 if (!vlan && !qos)
10403                         return HNAE3_PORT_BASE_VLAN_NOCHANGE;
10404
10405                 return HNAE3_PORT_BASE_VLAN_ENABLE;
10406         }
10407
10408         if (!vlan && !qos)
10409                 return HNAE3_PORT_BASE_VLAN_DISABLE;
10410
10411         if (vport->port_base_vlan_cfg.vlan_info.vlan_tag == vlan &&
10412             vport->port_base_vlan_cfg.vlan_info.qos == qos)
10413                 return HNAE3_PORT_BASE_VLAN_NOCHANGE;
10414
10415         return HNAE3_PORT_BASE_VLAN_MODIFY;
10416 }
10417
10418 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
10419                                     u16 vlan, u8 qos, __be16 proto)
10420 {
10421         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
10422         struct hclge_vport *vport = hclge_get_vport(handle);
10423         struct hclge_dev *hdev = vport->back;
10424         struct hclge_vlan_info vlan_info;
10425         u16 state;
10426         int ret;
10427
10428         if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
10429                 return -EOPNOTSUPP;
10430
10431         vport = hclge_get_vf_vport(hdev, vfid);
10432         if (!vport)
10433                 return -EINVAL;
10434
10435         /* qos is a 3 bits value, so can not be bigger than 7 */
10436         if (vlan > VLAN_N_VID - 1 || qos > 7)
10437                 return -EINVAL;
10438         if (proto != htons(ETH_P_8021Q))
10439                 return -EPROTONOSUPPORT;
10440
10441         state = hclge_get_port_base_vlan_state(vport,
10442                                                vport->port_base_vlan_cfg.state,
10443                                                vlan, qos);
10444         if (state == HNAE3_PORT_BASE_VLAN_NOCHANGE)
10445                 return 0;
10446
10447         vlan_info.vlan_tag = vlan;
10448         vlan_info.qos = qos;
10449         vlan_info.vlan_proto = ntohs(proto);
10450
10451         ret = hclge_update_port_base_vlan_cfg(vport, state, &vlan_info);
10452         if (ret) {
10453                 dev_err(&hdev->pdev->dev,
10454                         "failed to update port base vlan for vf %d, ret = %d\n",
10455                         vfid, ret);
10456                 return ret;
10457         }
10458
10459         /* there is a timewindow for PF to know VF unalive, it may
10460          * cause send mailbox fail, but it doesn't matter, VF will
10461          * query it when reinit.
10462          * for DEVICE_VERSION_V3, vf doesn't need to know about the port based
10463          * VLAN state.
10464          */
10465         if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3 &&
10466             test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state))
10467                 (void)hclge_push_vf_port_base_vlan_info(&hdev->vport[0],
10468                                                         vport->vport_id,
10469                                                         state, &vlan_info);
10470
10471         return 0;
10472 }
10473
10474 static void hclge_clear_vf_vlan(struct hclge_dev *hdev)
10475 {
10476         struct hclge_vlan_info *vlan_info;
10477         struct hclge_vport *vport;
10478         int ret;
10479         int vf;
10480
10481         /* clear port base vlan for all vf */
10482         for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) {
10483                 vport = &hdev->vport[vf];
10484                 vlan_info = &vport->port_base_vlan_cfg.vlan_info;
10485
10486                 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q),
10487                                                vport->vport_id,
10488                                                vlan_info->vlan_tag, true);
10489                 if (ret)
10490                         dev_err(&hdev->pdev->dev,
10491                                 "failed to clear vf vlan for vf%d, ret = %d\n",
10492                                 vf - HCLGE_VF_VPORT_START_NUM, ret);
10493         }
10494 }
10495
10496 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
10497                           u16 vlan_id, bool is_kill)
10498 {
10499         struct hclge_vport *vport = hclge_get_vport(handle);
10500         struct hclge_dev *hdev = vport->back;
10501         bool writen_to_tbl = false;
10502         int ret = 0;
10503
10504         /* When device is resetting or reset failed, firmware is unable to
10505          * handle mailbox. Just record the vlan id, and remove it after
10506          * reset finished.
10507          */
10508         if ((test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) ||
10509              test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) && is_kill) {
10510                 set_bit(vlan_id, vport->vlan_del_fail_bmap);
10511                 return -EBUSY;
10512         }
10513
10514         /* when port base vlan enabled, we use port base vlan as the vlan
10515          * filter entry. In this case, we don't update vlan filter table
10516          * when user add new vlan or remove exist vlan, just update the vport
10517          * vlan list. The vlan id in vlan list will be writen in vlan filter
10518          * table until port base vlan disabled
10519          */
10520         if (handle->port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) {
10521                 ret = hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id,
10522                                                vlan_id, is_kill);
10523                 writen_to_tbl = true;
10524         }
10525
10526         if (!ret) {
10527                 if (!is_kill)
10528                         hclge_add_vport_vlan_table(vport, vlan_id,
10529                                                    writen_to_tbl);
10530                 else if (is_kill && vlan_id != 0)
10531                         hclge_rm_vport_vlan_table(vport, vlan_id, false);
10532         } else if (is_kill) {
10533                 /* when remove hw vlan filter failed, record the vlan id,
10534                  * and try to remove it from hw later, to be consistence
10535                  * with stack
10536                  */
10537                 set_bit(vlan_id, vport->vlan_del_fail_bmap);
10538         }
10539
10540         hclge_set_vport_vlan_fltr_change(vport);
10541
10542         return ret;
10543 }
10544
10545 static void hclge_sync_vlan_fltr_state(struct hclge_dev *hdev)
10546 {
10547         struct hclge_vport *vport;
10548         int ret;
10549         u16 i;
10550
10551         for (i = 0; i < hdev->num_alloc_vport; i++) {
10552                 vport = &hdev->vport[i];
10553                 if (!test_and_clear_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE,
10554                                         &vport->state))
10555                         continue;
10556
10557                 ret = hclge_enable_vport_vlan_filter(vport,
10558                                                      vport->req_vlan_fltr_en);
10559                 if (ret) {
10560                         dev_err(&hdev->pdev->dev,
10561                                 "failed to sync vlan filter state for vport%u, ret = %d\n",
10562                                 vport->vport_id, ret);
10563                         set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE,
10564                                 &vport->state);
10565                         return;
10566                 }
10567         }
10568 }
10569
10570 static void hclge_sync_vlan_filter(struct hclge_dev *hdev)
10571 {
10572 #define HCLGE_MAX_SYNC_COUNT    60
10573
10574         int i, ret, sync_cnt = 0;
10575         u16 vlan_id;
10576
10577         /* start from vport 1 for PF is always alive */
10578         for (i = 0; i < hdev->num_alloc_vport; i++) {
10579                 struct hclge_vport *vport = &hdev->vport[i];
10580
10581                 vlan_id = find_first_bit(vport->vlan_del_fail_bmap,
10582                                          VLAN_N_VID);
10583                 while (vlan_id != VLAN_N_VID) {
10584                         ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q),
10585                                                        vport->vport_id, vlan_id,
10586                                                        true);
10587                         if (ret && ret != -EINVAL)
10588                                 return;
10589
10590                         clear_bit(vlan_id, vport->vlan_del_fail_bmap);
10591                         hclge_rm_vport_vlan_table(vport, vlan_id, false);
10592                         hclge_set_vport_vlan_fltr_change(vport);
10593
10594                         sync_cnt++;
10595                         if (sync_cnt >= HCLGE_MAX_SYNC_COUNT)
10596                                 return;
10597
10598                         vlan_id = find_first_bit(vport->vlan_del_fail_bmap,
10599                                                  VLAN_N_VID);
10600                 }
10601         }
10602
10603         hclge_sync_vlan_fltr_state(hdev);
10604 }
10605
10606 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps)
10607 {
10608         struct hclge_config_max_frm_size_cmd *req;
10609         struct hclge_desc desc;
10610
10611         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
10612
10613         req = (struct hclge_config_max_frm_size_cmd *)desc.data;
10614         req->max_frm_size = cpu_to_le16(new_mps);
10615         req->min_frm_size = HCLGE_MAC_MIN_FRAME;
10616
10617         return hclge_cmd_send(&hdev->hw, &desc, 1);
10618 }
10619
10620 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
10621 {
10622         struct hclge_vport *vport = hclge_get_vport(handle);
10623
10624         return hclge_set_vport_mtu(vport, new_mtu);
10625 }
10626
10627 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu)
10628 {
10629         struct hclge_dev *hdev = vport->back;
10630         int i, max_frm_size, ret;
10631
10632         /* HW supprt 2 layer vlan */
10633         max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN;
10634         if (max_frm_size < HCLGE_MAC_MIN_FRAME ||
10635             max_frm_size > hdev->ae_dev->dev_specs.max_frm_size)
10636                 return -EINVAL;
10637
10638         max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
10639         mutex_lock(&hdev->vport_lock);
10640         /* VF's mps must fit within hdev->mps */
10641         if (vport->vport_id && max_frm_size > hdev->mps) {
10642                 mutex_unlock(&hdev->vport_lock);
10643                 return -EINVAL;
10644         } else if (vport->vport_id) {
10645                 vport->mps = max_frm_size;
10646                 mutex_unlock(&hdev->vport_lock);
10647                 return 0;
10648         }
10649
10650         /* PF's mps must be greater then VF's mps */
10651         for (i = 1; i < hdev->num_alloc_vport; i++)
10652                 if (max_frm_size < hdev->vport[i].mps) {
10653                         dev_err(&hdev->pdev->dev,
10654                                 "failed to set pf mtu for less than vport %d, mps = %u.\n",
10655                                 i, hdev->vport[i].mps);
10656                         mutex_unlock(&hdev->vport_lock);
10657                         return -EINVAL;
10658                 }
10659
10660         hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
10661
10662         ret = hclge_set_mac_mtu(hdev, max_frm_size);
10663         if (ret) {
10664                 dev_err(&hdev->pdev->dev,
10665                         "Change mtu fail, ret =%d\n", ret);
10666                 goto out;
10667         }
10668
10669         hdev->mps = max_frm_size;
10670         vport->mps = max_frm_size;
10671
10672         ret = hclge_buffer_alloc(hdev);
10673         if (ret)
10674                 dev_err(&hdev->pdev->dev,
10675                         "Allocate buffer fail, ret =%d\n", ret);
10676
10677 out:
10678         hclge_notify_client(hdev, HNAE3_UP_CLIENT);
10679         mutex_unlock(&hdev->vport_lock);
10680         return ret;
10681 }
10682
10683 static int hclge_reset_tqp_cmd_send(struct hclge_dev *hdev, u16 queue_id,
10684                                     bool enable)
10685 {
10686         struct hclge_reset_tqp_queue_cmd *req;
10687         struct hclge_desc desc;
10688         int ret;
10689
10690         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
10691
10692         req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
10693         req->tqp_id = cpu_to_le16(queue_id);
10694         if (enable)
10695                 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, 1U);
10696
10697         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
10698         if (ret) {
10699                 dev_err(&hdev->pdev->dev,
10700                         "Send tqp reset cmd error, status =%d\n", ret);
10701                 return ret;
10702         }
10703
10704         return 0;
10705 }
10706
10707 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id,
10708                                   u8 *reset_status)
10709 {
10710         struct hclge_reset_tqp_queue_cmd *req;
10711         struct hclge_desc desc;
10712         int ret;
10713
10714         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
10715
10716         req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
10717         req->tqp_id = cpu_to_le16(queue_id);
10718
10719         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
10720         if (ret) {
10721                 dev_err(&hdev->pdev->dev,
10722                         "Get reset status error, status =%d\n", ret);
10723                 return ret;
10724         }
10725
10726         *reset_status = hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
10727
10728         return 0;
10729 }
10730
10731 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id)
10732 {
10733         struct hclge_comm_tqp *tqp;
10734         struct hnae3_queue *queue;
10735
10736         queue = handle->kinfo.tqp[queue_id];
10737         tqp = container_of(queue, struct hclge_comm_tqp, q);
10738
10739         return tqp->index;
10740 }
10741
10742 static int hclge_reset_tqp_cmd(struct hnae3_handle *handle)
10743 {
10744         struct hclge_vport *vport = hclge_get_vport(handle);
10745         struct hclge_dev *hdev = vport->back;
10746         u16 reset_try_times = 0;
10747         u8 reset_status;
10748         u16 queue_gid;
10749         int ret;
10750         u16 i;
10751
10752         for (i = 0; i < handle->kinfo.num_tqps; i++) {
10753                 queue_gid = hclge_covert_handle_qid_global(handle, i);
10754                 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, true);
10755                 if (ret) {
10756                         dev_err(&hdev->pdev->dev,
10757                                 "failed to send reset tqp cmd, ret = %d\n",
10758                                 ret);
10759                         return ret;
10760                 }
10761
10762                 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
10763                         ret = hclge_get_reset_status(hdev, queue_gid,
10764                                                      &reset_status);
10765                         if (ret)
10766                                 return ret;
10767
10768                         if (reset_status)
10769                                 break;
10770
10771                         /* Wait for tqp hw reset */
10772                         usleep_range(1000, 1200);
10773                 }
10774
10775                 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
10776                         dev_err(&hdev->pdev->dev,
10777                                 "wait for tqp hw reset timeout\n");
10778                         return -ETIME;
10779                 }
10780
10781                 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, false);
10782                 if (ret) {
10783                         dev_err(&hdev->pdev->dev,
10784                                 "failed to deassert soft reset, ret = %d\n",
10785                                 ret);
10786                         return ret;
10787                 }
10788                 reset_try_times = 0;
10789         }
10790         return 0;
10791 }
10792
10793 static int hclge_reset_rcb(struct hnae3_handle *handle)
10794 {
10795 #define HCLGE_RESET_RCB_NOT_SUPPORT     0U
10796 #define HCLGE_RESET_RCB_SUCCESS         1U
10797
10798         struct hclge_vport *vport = hclge_get_vport(handle);
10799         struct hclge_dev *hdev = vport->back;
10800         struct hclge_reset_cmd *req;
10801         struct hclge_desc desc;
10802         u8 return_status;
10803         u16 queue_gid;
10804         int ret;
10805
10806         queue_gid = hclge_covert_handle_qid_global(handle, 0);
10807
10808         req = (struct hclge_reset_cmd *)desc.data;
10809         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
10810         hnae3_set_bit(req->fun_reset_rcb, HCLGE_CFG_RESET_RCB_B, 1);
10811         req->fun_reset_rcb_vqid_start = cpu_to_le16(queue_gid);
10812         req->fun_reset_rcb_vqid_num = cpu_to_le16(handle->kinfo.num_tqps);
10813
10814         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
10815         if (ret) {
10816                 dev_err(&hdev->pdev->dev,
10817                         "failed to send rcb reset cmd, ret = %d\n", ret);
10818                 return ret;
10819         }
10820
10821         return_status = req->fun_reset_rcb_return_status;
10822         if (return_status == HCLGE_RESET_RCB_SUCCESS)
10823                 return 0;
10824
10825         if (return_status != HCLGE_RESET_RCB_NOT_SUPPORT) {
10826                 dev_err(&hdev->pdev->dev, "failed to reset rcb, ret = %u\n",
10827                         return_status);
10828                 return -EIO;
10829         }
10830
10831         /* if reset rcb cmd is unsupported, we need to send reset tqp cmd
10832          * again to reset all tqps
10833          */
10834         return hclge_reset_tqp_cmd(handle);
10835 }
10836
10837 int hclge_reset_tqp(struct hnae3_handle *handle)
10838 {
10839         struct hclge_vport *vport = hclge_get_vport(handle);
10840         struct hclge_dev *hdev = vport->back;
10841         int ret;
10842
10843         /* only need to disable PF's tqp */
10844         if (!vport->vport_id) {
10845                 ret = hclge_tqp_enable(handle, false);
10846                 if (ret) {
10847                         dev_err(&hdev->pdev->dev,
10848                                 "failed to disable tqp, ret = %d\n", ret);
10849                         return ret;
10850                 }
10851         }
10852
10853         return hclge_reset_rcb(handle);
10854 }
10855
10856 static u32 hclge_get_fw_version(struct hnae3_handle *handle)
10857 {
10858         struct hclge_vport *vport = hclge_get_vport(handle);
10859         struct hclge_dev *hdev = vport->back;
10860
10861         return hdev->fw_version;
10862 }
10863
10864 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
10865 {
10866         struct phy_device *phydev = hdev->hw.mac.phydev;
10867
10868         if (!phydev)
10869                 return;
10870
10871         phy_set_asym_pause(phydev, rx_en, tx_en);
10872 }
10873
10874 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
10875 {
10876         int ret;
10877
10878         if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
10879                 return 0;
10880
10881         ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
10882         if (ret)
10883                 dev_err(&hdev->pdev->dev,
10884                         "configure pauseparam error, ret = %d.\n", ret);
10885
10886         return ret;
10887 }
10888
10889 int hclge_cfg_flowctrl(struct hclge_dev *hdev)
10890 {
10891         struct phy_device *phydev = hdev->hw.mac.phydev;
10892         u16 remote_advertising = 0;
10893         u16 local_advertising;
10894         u32 rx_pause, tx_pause;
10895         u8 flowctl;
10896
10897         if (!phydev->link || !phydev->autoneg)
10898                 return 0;
10899
10900         local_advertising = linkmode_adv_to_lcl_adv_t(phydev->advertising);
10901
10902         if (phydev->pause)
10903                 remote_advertising = LPA_PAUSE_CAP;
10904
10905         if (phydev->asym_pause)
10906                 remote_advertising |= LPA_PAUSE_ASYM;
10907
10908         flowctl = mii_resolve_flowctrl_fdx(local_advertising,
10909                                            remote_advertising);
10910         tx_pause = flowctl & FLOW_CTRL_TX;
10911         rx_pause = flowctl & FLOW_CTRL_RX;
10912
10913         if (phydev->duplex == HCLGE_MAC_HALF) {
10914                 tx_pause = 0;
10915                 rx_pause = 0;
10916         }
10917
10918         return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
10919 }
10920
10921 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
10922                                  u32 *rx_en, u32 *tx_en)
10923 {
10924         struct hclge_vport *vport = hclge_get_vport(handle);
10925         struct hclge_dev *hdev = vport->back;
10926         u8 media_type = hdev->hw.mac.media_type;
10927
10928         *auto_neg = (media_type == HNAE3_MEDIA_TYPE_COPPER) ?
10929                     hclge_get_autoneg(handle) : 0;
10930
10931         if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
10932                 *rx_en = 0;
10933                 *tx_en = 0;
10934                 return;
10935         }
10936
10937         if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
10938                 *rx_en = 1;
10939                 *tx_en = 0;
10940         } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
10941                 *tx_en = 1;
10942                 *rx_en = 0;
10943         } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
10944                 *rx_en = 1;
10945                 *tx_en = 1;
10946         } else {
10947                 *rx_en = 0;
10948                 *tx_en = 0;
10949         }
10950 }
10951
10952 static void hclge_record_user_pauseparam(struct hclge_dev *hdev,
10953                                          u32 rx_en, u32 tx_en)
10954 {
10955         if (rx_en && tx_en)
10956                 hdev->fc_mode_last_time = HCLGE_FC_FULL;
10957         else if (rx_en && !tx_en)
10958                 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
10959         else if (!rx_en && tx_en)
10960                 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
10961         else
10962                 hdev->fc_mode_last_time = HCLGE_FC_NONE;
10963
10964         hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
10965 }
10966
10967 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
10968                                 u32 rx_en, u32 tx_en)
10969 {
10970         struct hclge_vport *vport = hclge_get_vport(handle);
10971         struct hclge_dev *hdev = vport->back;
10972         struct phy_device *phydev = hdev->hw.mac.phydev;
10973         u32 fc_autoneg;
10974
10975         if (phydev || hnae3_dev_phy_imp_supported(hdev)) {
10976                 fc_autoneg = hclge_get_autoneg(handle);
10977                 if (auto_neg != fc_autoneg) {
10978                         dev_info(&hdev->pdev->dev,
10979                                  "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
10980                         return -EOPNOTSUPP;
10981                 }
10982         }
10983
10984         if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
10985                 dev_info(&hdev->pdev->dev,
10986                          "Priority flow control enabled. Cannot set link flow control.\n");
10987                 return -EOPNOTSUPP;
10988         }
10989
10990         hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
10991
10992         hclge_record_user_pauseparam(hdev, rx_en, tx_en);
10993
10994         if (!auto_neg || hnae3_dev_phy_imp_supported(hdev))
10995                 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
10996
10997         if (phydev)
10998                 return phy_start_aneg(phydev);
10999
11000         return -EOPNOTSUPP;
11001 }
11002
11003 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
11004                                           u8 *auto_neg, u32 *speed, u8 *duplex, u32 *lane_num)
11005 {
11006         struct hclge_vport *vport = hclge_get_vport(handle);
11007         struct hclge_dev *hdev = vport->back;
11008
11009         if (speed)
11010                 *speed = hdev->hw.mac.speed;
11011         if (duplex)
11012                 *duplex = hdev->hw.mac.duplex;
11013         if (auto_neg)
11014                 *auto_neg = hdev->hw.mac.autoneg;
11015         if (lane_num)
11016                 *lane_num = hdev->hw.mac.lane_num;
11017 }
11018
11019 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type,
11020                                  u8 *module_type)
11021 {
11022         struct hclge_vport *vport = hclge_get_vport(handle);
11023         struct hclge_dev *hdev = vport->back;
11024
11025         /* When nic is down, the service task is not running, doesn't update
11026          * the port information per second. Query the port information before
11027          * return the media type, ensure getting the correct media information.
11028          */
11029         hclge_update_port_info(hdev);
11030
11031         if (media_type)
11032                 *media_type = hdev->hw.mac.media_type;
11033
11034         if (module_type)
11035                 *module_type = hdev->hw.mac.module_type;
11036 }
11037
11038 static void hclge_get_mdix_mode(struct hnae3_handle *handle,
11039                                 u8 *tp_mdix_ctrl, u8 *tp_mdix)
11040 {
11041         struct hclge_vport *vport = hclge_get_vport(handle);
11042         struct hclge_dev *hdev = vport->back;
11043         struct phy_device *phydev = hdev->hw.mac.phydev;
11044         int mdix_ctrl, mdix, is_resolved;
11045         unsigned int retval;
11046
11047         if (!phydev) {
11048                 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
11049                 *tp_mdix = ETH_TP_MDI_INVALID;
11050                 return;
11051         }
11052
11053         phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
11054
11055         retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
11056         mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
11057                                     HCLGE_PHY_MDIX_CTRL_S);
11058
11059         retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
11060         mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
11061         is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
11062
11063         phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
11064
11065         switch (mdix_ctrl) {
11066         case 0x0:
11067                 *tp_mdix_ctrl = ETH_TP_MDI;
11068                 break;
11069         case 0x1:
11070                 *tp_mdix_ctrl = ETH_TP_MDI_X;
11071                 break;
11072         case 0x3:
11073                 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
11074                 break;
11075         default:
11076                 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
11077                 break;
11078         }
11079
11080         if (!is_resolved)
11081                 *tp_mdix = ETH_TP_MDI_INVALID;
11082         else if (mdix)
11083                 *tp_mdix = ETH_TP_MDI_X;
11084         else
11085                 *tp_mdix = ETH_TP_MDI;
11086 }
11087
11088 static void hclge_info_show(struct hclge_dev *hdev)
11089 {
11090         struct device *dev = &hdev->pdev->dev;
11091
11092         dev_info(dev, "PF info begin:\n");
11093
11094         dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps);
11095         dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc);
11096         dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc);
11097         dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport);
11098         dev_info(dev, "Numbers of VF for this PF: %u\n", hdev->num_req_vfs);
11099         dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map);
11100         dev_info(dev, "Total buffer size for TX/RX: %u\n", hdev->pkt_buf_size);
11101         dev_info(dev, "TX buffer size for each TC: %u\n", hdev->tx_buf_size);
11102         dev_info(dev, "DV buffer size for each TC: %u\n", hdev->dv_buf_size);
11103         dev_info(dev, "This is %s PF\n",
11104                  hdev->flag & HCLGE_FLAG_MAIN ? "main" : "not main");
11105         dev_info(dev, "DCB %s\n",
11106                  hdev->flag & HCLGE_FLAG_DCB_ENABLE ? "enable" : "disable");
11107         dev_info(dev, "MQPRIO %s\n",
11108                  hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE ? "enable" : "disable");
11109         dev_info(dev, "Default tx spare buffer size: %u\n",
11110                  hdev->tx_spare_buf_size);
11111
11112         dev_info(dev, "PF info end.\n");
11113 }
11114
11115 static int hclge_init_nic_client_instance(struct hnae3_ae_dev *ae_dev,
11116                                           struct hclge_vport *vport)
11117 {
11118         struct hnae3_client *client = vport->nic.client;
11119         struct hclge_dev *hdev = ae_dev->priv;
11120         int rst_cnt = hdev->rst_stats.reset_cnt;
11121         int ret;
11122
11123         ret = client->ops->init_instance(&vport->nic);
11124         if (ret)
11125                 return ret;
11126
11127         set_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state);
11128         if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) ||
11129             rst_cnt != hdev->rst_stats.reset_cnt) {
11130                 ret = -EBUSY;
11131                 goto init_nic_err;
11132         }
11133
11134         /* Enable nic hw error interrupts */
11135         ret = hclge_config_nic_hw_error(hdev, true);
11136         if (ret) {
11137                 dev_err(&ae_dev->pdev->dev,
11138                         "fail(%d) to enable hw error interrupts\n", ret);
11139                 goto init_nic_err;
11140         }
11141
11142         hnae3_set_client_init_flag(client, ae_dev, 1);
11143
11144         if (netif_msg_drv(&hdev->vport->nic))
11145                 hclge_info_show(hdev);
11146
11147         return ret;
11148
11149 init_nic_err:
11150         clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state);
11151         while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
11152                 msleep(HCLGE_WAIT_RESET_DONE);
11153
11154         client->ops->uninit_instance(&vport->nic, 0);
11155
11156         return ret;
11157 }
11158
11159 static int hclge_init_roce_client_instance(struct hnae3_ae_dev *ae_dev,
11160                                            struct hclge_vport *vport)
11161 {
11162         struct hclge_dev *hdev = ae_dev->priv;
11163         struct hnae3_client *client;
11164         int rst_cnt;
11165         int ret;
11166
11167         if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client ||
11168             !hdev->nic_client)
11169                 return 0;
11170
11171         client = hdev->roce_client;
11172         ret = hclge_init_roce_base_info(vport);
11173         if (ret)
11174                 return ret;
11175
11176         rst_cnt = hdev->rst_stats.reset_cnt;
11177         ret = client->ops->init_instance(&vport->roce);
11178         if (ret)
11179                 return ret;
11180
11181         set_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state);
11182         if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) ||
11183             rst_cnt != hdev->rst_stats.reset_cnt) {
11184                 ret = -EBUSY;
11185                 goto init_roce_err;
11186         }
11187
11188         /* Enable roce ras interrupts */
11189         ret = hclge_config_rocee_ras_interrupt(hdev, true);
11190         if (ret) {
11191                 dev_err(&ae_dev->pdev->dev,
11192                         "fail(%d) to enable roce ras interrupts\n", ret);
11193                 goto init_roce_err;
11194         }
11195
11196         hnae3_set_client_init_flag(client, ae_dev, 1);
11197
11198         return 0;
11199
11200 init_roce_err:
11201         clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state);
11202         while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
11203                 msleep(HCLGE_WAIT_RESET_DONE);
11204
11205         hdev->roce_client->ops->uninit_instance(&vport->roce, 0);
11206
11207         return ret;
11208 }
11209
11210 static int hclge_init_client_instance(struct hnae3_client *client,
11211                                       struct hnae3_ae_dev *ae_dev)
11212 {
11213         struct hclge_dev *hdev = ae_dev->priv;
11214         struct hclge_vport *vport = &hdev->vport[0];
11215         int ret;
11216
11217         switch (client->type) {
11218         case HNAE3_CLIENT_KNIC:
11219                 hdev->nic_client = client;
11220                 vport->nic.client = client;
11221                 ret = hclge_init_nic_client_instance(ae_dev, vport);
11222                 if (ret)
11223                         goto clear_nic;
11224
11225                 ret = hclge_init_roce_client_instance(ae_dev, vport);
11226                 if (ret)
11227                         goto clear_roce;
11228
11229                 break;
11230         case HNAE3_CLIENT_ROCE:
11231                 if (hnae3_dev_roce_supported(hdev)) {
11232                         hdev->roce_client = client;
11233                         vport->roce.client = client;
11234                 }
11235
11236                 ret = hclge_init_roce_client_instance(ae_dev, vport);
11237                 if (ret)
11238                         goto clear_roce;
11239
11240                 break;
11241         default:
11242                 return -EINVAL;
11243         }
11244
11245         return 0;
11246
11247 clear_nic:
11248         hdev->nic_client = NULL;
11249         vport->nic.client = NULL;
11250         return ret;
11251 clear_roce:
11252         hdev->roce_client = NULL;
11253         vport->roce.client = NULL;
11254         return ret;
11255 }
11256
11257 static void hclge_uninit_client_instance(struct hnae3_client *client,
11258                                          struct hnae3_ae_dev *ae_dev)
11259 {
11260         struct hclge_dev *hdev = ae_dev->priv;
11261         struct hclge_vport *vport = &hdev->vport[0];
11262
11263         if (hdev->roce_client) {
11264                 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state);
11265                 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
11266                         msleep(HCLGE_WAIT_RESET_DONE);
11267
11268                 hdev->roce_client->ops->uninit_instance(&vport->roce, 0);
11269                 hdev->roce_client = NULL;
11270                 vport->roce.client = NULL;
11271         }
11272         if (client->type == HNAE3_CLIENT_ROCE)
11273                 return;
11274         if (hdev->nic_client && client->ops->uninit_instance) {
11275                 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state);
11276                 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
11277                         msleep(HCLGE_WAIT_RESET_DONE);
11278
11279                 client->ops->uninit_instance(&vport->nic, 0);
11280                 hdev->nic_client = NULL;
11281                 vport->nic.client = NULL;
11282         }
11283 }
11284
11285 static int hclge_dev_mem_map(struct hclge_dev *hdev)
11286 {
11287         struct pci_dev *pdev = hdev->pdev;
11288         struct hclge_hw *hw = &hdev->hw;
11289
11290         /* for device does not have device memory, return directly */
11291         if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGE_MEM_BAR)))
11292                 return 0;
11293
11294         hw->hw.mem_base =
11295                 devm_ioremap_wc(&pdev->dev,
11296                                 pci_resource_start(pdev, HCLGE_MEM_BAR),
11297                                 pci_resource_len(pdev, HCLGE_MEM_BAR));
11298         if (!hw->hw.mem_base) {
11299                 dev_err(&pdev->dev, "failed to map device memory\n");
11300                 return -EFAULT;
11301         }
11302
11303         return 0;
11304 }
11305
11306 static int hclge_pci_init(struct hclge_dev *hdev)
11307 {
11308         struct pci_dev *pdev = hdev->pdev;
11309         struct hclge_hw *hw;
11310         int ret;
11311
11312         ret = pci_enable_device(pdev);
11313         if (ret) {
11314                 dev_err(&pdev->dev, "failed to enable PCI device\n");
11315                 return ret;
11316         }
11317
11318         ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
11319         if (ret) {
11320                 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
11321                 if (ret) {
11322                         dev_err(&pdev->dev,
11323                                 "can't set consistent PCI DMA");
11324                         goto err_disable_device;
11325                 }
11326                 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
11327         }
11328
11329         ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
11330         if (ret) {
11331                 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
11332                 goto err_disable_device;
11333         }
11334
11335         pci_set_master(pdev);
11336         hw = &hdev->hw;
11337         hw->hw.io_base = pcim_iomap(pdev, 2, 0);
11338         if (!hw->hw.io_base) {
11339                 dev_err(&pdev->dev, "Can't map configuration register space\n");
11340                 ret = -ENOMEM;
11341                 goto err_clr_master;
11342         }
11343
11344         ret = hclge_dev_mem_map(hdev);
11345         if (ret)
11346                 goto err_unmap_io_base;
11347
11348         hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
11349
11350         return 0;
11351
11352 err_unmap_io_base:
11353         pcim_iounmap(pdev, hdev->hw.hw.io_base);
11354 err_clr_master:
11355         pci_clear_master(pdev);
11356         pci_release_regions(pdev);
11357 err_disable_device:
11358         pci_disable_device(pdev);
11359
11360         return ret;
11361 }
11362
11363 static void hclge_pci_uninit(struct hclge_dev *hdev)
11364 {
11365         struct pci_dev *pdev = hdev->pdev;
11366
11367         if (hdev->hw.hw.mem_base)
11368                 devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base);
11369
11370         pcim_iounmap(pdev, hdev->hw.hw.io_base);
11371         pci_free_irq_vectors(pdev);
11372         pci_clear_master(pdev);
11373         pci_release_mem_regions(pdev);
11374         pci_disable_device(pdev);
11375 }
11376
11377 static void hclge_state_init(struct hclge_dev *hdev)
11378 {
11379         set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
11380         set_bit(HCLGE_STATE_DOWN, &hdev->state);
11381         clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
11382         clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
11383         clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state);
11384         clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
11385         clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
11386 }
11387
11388 static void hclge_state_uninit(struct hclge_dev *hdev)
11389 {
11390         set_bit(HCLGE_STATE_DOWN, &hdev->state);
11391         set_bit(HCLGE_STATE_REMOVING, &hdev->state);
11392
11393         if (hdev->reset_timer.function)
11394                 del_timer_sync(&hdev->reset_timer);
11395         if (hdev->service_task.work.func)
11396                 cancel_delayed_work_sync(&hdev->service_task);
11397 }
11398
11399 static void hclge_reset_prepare_general(struct hnae3_ae_dev *ae_dev,
11400                                         enum hnae3_reset_type rst_type)
11401 {
11402 #define HCLGE_RESET_RETRY_WAIT_MS       500
11403 #define HCLGE_RESET_RETRY_CNT   5
11404
11405         struct hclge_dev *hdev = ae_dev->priv;
11406         int retry_cnt = 0;
11407         int ret;
11408
11409         while (retry_cnt++ < HCLGE_RESET_RETRY_CNT) {
11410                 down(&hdev->reset_sem);
11411                 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
11412                 hdev->reset_type = rst_type;
11413                 ret = hclge_reset_prepare(hdev);
11414                 if (!ret && !hdev->reset_pending)
11415                         break;
11416
11417                 dev_err(&hdev->pdev->dev,
11418                         "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n",
11419                         ret, hdev->reset_pending, retry_cnt);
11420                 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
11421                 up(&hdev->reset_sem);
11422                 msleep(HCLGE_RESET_RETRY_WAIT_MS);
11423         }
11424
11425         /* disable misc vector before reset done */
11426         hclge_enable_vector(&hdev->misc_vector, false);
11427         set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
11428
11429         if (hdev->reset_type == HNAE3_FLR_RESET)
11430                 hdev->rst_stats.flr_rst_cnt++;
11431 }
11432
11433 static void hclge_reset_done(struct hnae3_ae_dev *ae_dev)
11434 {
11435         struct hclge_dev *hdev = ae_dev->priv;
11436         int ret;
11437
11438         hclge_enable_vector(&hdev->misc_vector, true);
11439
11440         ret = hclge_reset_rebuild(hdev);
11441         if (ret)
11442                 dev_err(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", ret);
11443
11444         hdev->reset_type = HNAE3_NONE_RESET;
11445         clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
11446         up(&hdev->reset_sem);
11447 }
11448
11449 static void hclge_clear_resetting_state(struct hclge_dev *hdev)
11450 {
11451         u16 i;
11452
11453         for (i = 0; i < hdev->num_alloc_vport; i++) {
11454                 struct hclge_vport *vport = &hdev->vport[i];
11455                 int ret;
11456
11457                  /* Send cmd to clear vport's FUNC_RST_ING */
11458                 ret = hclge_set_vf_rst(hdev, vport->vport_id, false);
11459                 if (ret)
11460                         dev_warn(&hdev->pdev->dev,
11461                                  "clear vport(%u) rst failed %d!\n",
11462                                  vport->vport_id, ret);
11463         }
11464 }
11465
11466 static int hclge_clear_hw_resource(struct hclge_dev *hdev)
11467 {
11468         struct hclge_desc desc;
11469         int ret;
11470
11471         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CLEAR_HW_RESOURCE, false);
11472
11473         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
11474         /* This new command is only supported by new firmware, it will
11475          * fail with older firmware. Error value -EOPNOSUPP can only be
11476          * returned by older firmware running this command, to keep code
11477          * backward compatible we will override this value and return
11478          * success.
11479          */
11480         if (ret && ret != -EOPNOTSUPP) {
11481                 dev_err(&hdev->pdev->dev,
11482                         "failed to clear hw resource, ret = %d\n", ret);
11483                 return ret;
11484         }
11485         return 0;
11486 }
11487
11488 static void hclge_init_rxd_adv_layout(struct hclge_dev *hdev)
11489 {
11490         if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev))
11491                 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 1);
11492 }
11493
11494 static void hclge_uninit_rxd_adv_layout(struct hclge_dev *hdev)
11495 {
11496         if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev))
11497                 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 0);
11498 }
11499
11500 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
11501 {
11502         struct pci_dev *pdev = ae_dev->pdev;
11503         struct hclge_dev *hdev;
11504         int ret;
11505
11506         hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
11507         if (!hdev)
11508                 return -ENOMEM;
11509
11510         hdev->pdev = pdev;
11511         hdev->ae_dev = ae_dev;
11512         hdev->reset_type = HNAE3_NONE_RESET;
11513         hdev->reset_level = HNAE3_FUNC_RESET;
11514         ae_dev->priv = hdev;
11515
11516         /* HW supprt 2 layer vlan */
11517         hdev->mps = ETH_FRAME_LEN + ETH_FCS_LEN + 2 * VLAN_HLEN;
11518
11519         mutex_init(&hdev->vport_lock);
11520         spin_lock_init(&hdev->fd_rule_lock);
11521         sema_init(&hdev->reset_sem, 1);
11522
11523         ret = hclge_pci_init(hdev);
11524         if (ret)
11525                 goto out;
11526
11527         ret = hclge_devlink_init(hdev);
11528         if (ret)
11529                 goto err_pci_uninit;
11530
11531         /* Firmware command queue initialize */
11532         ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw);
11533         if (ret)
11534                 goto err_devlink_uninit;
11535
11536         /* Firmware command initialize */
11537         ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version,
11538                                   true, hdev->reset_pending);
11539         if (ret)
11540                 goto err_cmd_uninit;
11541
11542         ret  = hclge_clear_hw_resource(hdev);
11543         if (ret)
11544                 goto err_cmd_uninit;
11545
11546         ret = hclge_get_cap(hdev);
11547         if (ret)
11548                 goto err_cmd_uninit;
11549
11550         ret = hclge_query_dev_specs(hdev);
11551         if (ret) {
11552                 dev_err(&pdev->dev, "failed to query dev specifications, ret = %d.\n",
11553                         ret);
11554                 goto err_cmd_uninit;
11555         }
11556
11557         ret = hclge_configure(hdev);
11558         if (ret) {
11559                 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
11560                 goto err_cmd_uninit;
11561         }
11562
11563         ret = hclge_init_msi(hdev);
11564         if (ret) {
11565                 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
11566                 goto err_cmd_uninit;
11567         }
11568
11569         ret = hclge_misc_irq_init(hdev);
11570         if (ret)
11571                 goto err_msi_uninit;
11572
11573         ret = hclge_alloc_tqps(hdev);
11574         if (ret) {
11575                 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
11576                 goto err_msi_irq_uninit;
11577         }
11578
11579         ret = hclge_alloc_vport(hdev);
11580         if (ret)
11581                 goto err_msi_irq_uninit;
11582
11583         ret = hclge_map_tqp(hdev);
11584         if (ret)
11585                 goto err_msi_irq_uninit;
11586
11587         if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER &&
11588             !hnae3_dev_phy_imp_supported(hdev)) {
11589                 ret = hclge_mac_mdio_config(hdev);
11590                 if (ret)
11591                         goto err_msi_irq_uninit;
11592         }
11593
11594         ret = hclge_init_umv_space(hdev);
11595         if (ret)
11596                 goto err_mdiobus_unreg;
11597
11598         ret = hclge_mac_init(hdev);
11599         if (ret) {
11600                 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
11601                 goto err_mdiobus_unreg;
11602         }
11603
11604         ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
11605         if (ret) {
11606                 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
11607                 goto err_mdiobus_unreg;
11608         }
11609
11610         ret = hclge_config_gro(hdev);
11611         if (ret)
11612                 goto err_mdiobus_unreg;
11613
11614         ret = hclge_init_vlan_config(hdev);
11615         if (ret) {
11616                 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
11617                 goto err_mdiobus_unreg;
11618         }
11619
11620         ret = hclge_tm_schd_init(hdev);
11621         if (ret) {
11622                 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
11623                 goto err_mdiobus_unreg;
11624         }
11625
11626         ret = hclge_comm_rss_init_cfg(&hdev->vport->nic, hdev->ae_dev,
11627                                       &hdev->rss_cfg);
11628         if (ret) {
11629                 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret);
11630                 goto err_mdiobus_unreg;
11631         }
11632
11633         ret = hclge_rss_init_hw(hdev);
11634         if (ret) {
11635                 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
11636                 goto err_mdiobus_unreg;
11637         }
11638
11639         ret = init_mgr_tbl(hdev);
11640         if (ret) {
11641                 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret);
11642                 goto err_mdiobus_unreg;
11643         }
11644
11645         ret = hclge_init_fd_config(hdev);
11646         if (ret) {
11647                 dev_err(&pdev->dev,
11648                         "fd table init fail, ret=%d\n", ret);
11649                 goto err_mdiobus_unreg;
11650         }
11651
11652         ret = hclge_ptp_init(hdev);
11653         if (ret)
11654                 goto err_mdiobus_unreg;
11655
11656         ret = hclge_update_port_info(hdev);
11657         if (ret)
11658                 goto err_mdiobus_unreg;
11659
11660         INIT_KFIFO(hdev->mac_tnl_log);
11661
11662         hclge_dcb_ops_set(hdev);
11663
11664         timer_setup(&hdev->reset_timer, hclge_reset_timer, 0);
11665         INIT_DELAYED_WORK(&hdev->service_task, hclge_service_task);
11666
11667         hclge_clear_all_event_cause(hdev);
11668         hclge_clear_resetting_state(hdev);
11669
11670         /* Log and clear the hw errors those already occurred */
11671         if (hnae3_dev_ras_imp_supported(hdev))
11672                 hclge_handle_occurred_error(hdev);
11673         else
11674                 hclge_handle_all_hns_hw_errors(ae_dev);
11675
11676         /* request delayed reset for the error recovery because an immediate
11677          * global reset on a PF affecting pending initialization of other PFs
11678          */
11679         if (ae_dev->hw_err_reset_req) {
11680                 enum hnae3_reset_type reset_level;
11681
11682                 reset_level = hclge_get_reset_level(ae_dev,
11683                                                     &ae_dev->hw_err_reset_req);
11684                 hclge_set_def_reset_request(ae_dev, reset_level);
11685                 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL);
11686         }
11687
11688         hclge_init_rxd_adv_layout(hdev);
11689
11690         /* Enable MISC vector(vector0) */
11691         hclge_enable_vector(&hdev->misc_vector, true);
11692
11693         hclge_state_init(hdev);
11694         hdev->last_reset_time = jiffies;
11695
11696         dev_info(&hdev->pdev->dev, "%s driver initialization finished.\n",
11697                  HCLGE_DRIVER_NAME);
11698
11699         hclge_task_schedule(hdev, round_jiffies_relative(HZ));
11700
11701         return 0;
11702
11703 err_mdiobus_unreg:
11704         if (hdev->hw.mac.phydev)
11705                 mdiobus_unregister(hdev->hw.mac.mdio_bus);
11706 err_msi_irq_uninit:
11707         hclge_misc_irq_uninit(hdev);
11708 err_msi_uninit:
11709         pci_free_irq_vectors(pdev);
11710 err_cmd_uninit:
11711         hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw);
11712 err_devlink_uninit:
11713         hclge_devlink_uninit(hdev);
11714 err_pci_uninit:
11715         pcim_iounmap(pdev, hdev->hw.hw.io_base);
11716         pci_clear_master(pdev);
11717         pci_release_regions(pdev);
11718         pci_disable_device(pdev);
11719 out:
11720         mutex_destroy(&hdev->vport_lock);
11721         return ret;
11722 }
11723
11724 static void hclge_stats_clear(struct hclge_dev *hdev)
11725 {
11726         memset(&hdev->mac_stats, 0, sizeof(hdev->mac_stats));
11727         memset(&hdev->fec_stats, 0, sizeof(hdev->fec_stats));
11728 }
11729
11730 static int hclge_set_mac_spoofchk(struct hclge_dev *hdev, int vf, bool enable)
11731 {
11732         return hclge_config_switch_param(hdev, vf, enable,
11733                                          HCLGE_SWITCH_ANTI_SPOOF_MASK);
11734 }
11735
11736 static int hclge_set_vlan_spoofchk(struct hclge_dev *hdev, int vf, bool enable)
11737 {
11738         return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
11739                                           HCLGE_FILTER_FE_NIC_INGRESS_B,
11740                                           enable, vf);
11741 }
11742
11743 static int hclge_set_vf_spoofchk_hw(struct hclge_dev *hdev, int vf, bool enable)
11744 {
11745         int ret;
11746
11747         ret = hclge_set_mac_spoofchk(hdev, vf, enable);
11748         if (ret) {
11749                 dev_err(&hdev->pdev->dev,
11750                         "Set vf %d mac spoof check %s failed, ret=%d\n",
11751                         vf, enable ? "on" : "off", ret);
11752                 return ret;
11753         }
11754
11755         ret = hclge_set_vlan_spoofchk(hdev, vf, enable);
11756         if (ret)
11757                 dev_err(&hdev->pdev->dev,
11758                         "Set vf %d vlan spoof check %s failed, ret=%d\n",
11759                         vf, enable ? "on" : "off", ret);
11760
11761         return ret;
11762 }
11763
11764 static int hclge_set_vf_spoofchk(struct hnae3_handle *handle, int vf,
11765                                  bool enable)
11766 {
11767         struct hclge_vport *vport = hclge_get_vport(handle);
11768         struct hclge_dev *hdev = vport->back;
11769         u32 new_spoofchk = enable ? 1 : 0;
11770         int ret;
11771
11772         if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
11773                 return -EOPNOTSUPP;
11774
11775         vport = hclge_get_vf_vport(hdev, vf);
11776         if (!vport)
11777                 return -EINVAL;
11778
11779         if (vport->vf_info.spoofchk == new_spoofchk)
11780                 return 0;
11781
11782         if (enable && test_bit(vport->vport_id, hdev->vf_vlan_full))
11783                 dev_warn(&hdev->pdev->dev,
11784                          "vf %d vlan table is full, enable spoof check may cause its packet send fail\n",
11785                          vf);
11786         else if (enable && hclge_is_umv_space_full(vport, true))
11787                 dev_warn(&hdev->pdev->dev,
11788                          "vf %d mac table is full, enable spoof check may cause its packet send fail\n",
11789                          vf);
11790
11791         ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, enable);
11792         if (ret)
11793                 return ret;
11794
11795         vport->vf_info.spoofchk = new_spoofchk;
11796         return 0;
11797 }
11798
11799 static int hclge_reset_vport_spoofchk(struct hclge_dev *hdev)
11800 {
11801         struct hclge_vport *vport = hdev->vport;
11802         int ret;
11803         int i;
11804
11805         if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
11806                 return 0;
11807
11808         /* resume the vf spoof check state after reset */
11809         for (i = 0; i < hdev->num_alloc_vport; i++) {
11810                 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id,
11811                                                vport->vf_info.spoofchk);
11812                 if (ret)
11813                         return ret;
11814
11815                 vport++;
11816         }
11817
11818         return 0;
11819 }
11820
11821 static int hclge_set_vf_trust(struct hnae3_handle *handle, int vf, bool enable)
11822 {
11823         struct hclge_vport *vport = hclge_get_vport(handle);
11824         struct hclge_dev *hdev = vport->back;
11825         u32 new_trusted = enable ? 1 : 0;
11826
11827         vport = hclge_get_vf_vport(hdev, vf);
11828         if (!vport)
11829                 return -EINVAL;
11830
11831         if (vport->vf_info.trusted == new_trusted)
11832                 return 0;
11833
11834         vport->vf_info.trusted = new_trusted;
11835         set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
11836         hclge_task_schedule(hdev, 0);
11837
11838         return 0;
11839 }
11840
11841 static void hclge_reset_vf_rate(struct hclge_dev *hdev)
11842 {
11843         int ret;
11844         int vf;
11845
11846         /* reset vf rate to default value */
11847         for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) {
11848                 struct hclge_vport *vport = &hdev->vport[vf];
11849
11850                 vport->vf_info.max_tx_rate = 0;
11851                 ret = hclge_tm_qs_shaper_cfg(vport, vport->vf_info.max_tx_rate);
11852                 if (ret)
11853                         dev_err(&hdev->pdev->dev,
11854                                 "vf%d failed to reset to default, ret=%d\n",
11855                                 vf - HCLGE_VF_VPORT_START_NUM, ret);
11856         }
11857 }
11858
11859 static int hclge_vf_rate_param_check(struct hclge_dev *hdev,
11860                                      int min_tx_rate, int max_tx_rate)
11861 {
11862         if (min_tx_rate != 0 ||
11863             max_tx_rate < 0 || max_tx_rate > hdev->hw.mac.max_speed) {
11864                 dev_err(&hdev->pdev->dev,
11865                         "min_tx_rate:%d [0], max_tx_rate:%d [0, %u]\n",
11866                         min_tx_rate, max_tx_rate, hdev->hw.mac.max_speed);
11867                 return -EINVAL;
11868         }
11869
11870         return 0;
11871 }
11872
11873 static int hclge_set_vf_rate(struct hnae3_handle *handle, int vf,
11874                              int min_tx_rate, int max_tx_rate, bool force)
11875 {
11876         struct hclge_vport *vport = hclge_get_vport(handle);
11877         struct hclge_dev *hdev = vport->back;
11878         int ret;
11879
11880         ret = hclge_vf_rate_param_check(hdev, min_tx_rate, max_tx_rate);
11881         if (ret)
11882                 return ret;
11883
11884         vport = hclge_get_vf_vport(hdev, vf);
11885         if (!vport)
11886                 return -EINVAL;
11887
11888         if (!force && max_tx_rate == vport->vf_info.max_tx_rate)
11889                 return 0;
11890
11891         ret = hclge_tm_qs_shaper_cfg(vport, max_tx_rate);
11892         if (ret)
11893                 return ret;
11894
11895         vport->vf_info.max_tx_rate = max_tx_rate;
11896
11897         return 0;
11898 }
11899
11900 static int hclge_resume_vf_rate(struct hclge_dev *hdev)
11901 {
11902         struct hnae3_handle *handle = &hdev->vport->nic;
11903         struct hclge_vport *vport;
11904         int ret;
11905         int vf;
11906
11907         /* resume the vf max_tx_rate after reset */
11908         for (vf = 0; vf < pci_num_vf(hdev->pdev); vf++) {
11909                 vport = hclge_get_vf_vport(hdev, vf);
11910                 if (!vport)
11911                         return -EINVAL;
11912
11913                 /* zero means max rate, after reset, firmware already set it to
11914                  * max rate, so just continue.
11915                  */
11916                 if (!vport->vf_info.max_tx_rate)
11917                         continue;
11918
11919                 ret = hclge_set_vf_rate(handle, vf, 0,
11920                                         vport->vf_info.max_tx_rate, true);
11921                 if (ret) {
11922                         dev_err(&hdev->pdev->dev,
11923                                 "vf%d failed to resume tx_rate:%u, ret=%d\n",
11924                                 vf, vport->vf_info.max_tx_rate, ret);
11925                         return ret;
11926                 }
11927         }
11928
11929         return 0;
11930 }
11931
11932 static void hclge_reset_vport_state(struct hclge_dev *hdev)
11933 {
11934         struct hclge_vport *vport = hdev->vport;
11935         int i;
11936
11937         for (i = 0; i < hdev->num_alloc_vport; i++) {
11938                 hclge_vport_stop(vport);
11939                 vport++;
11940         }
11941 }
11942
11943 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
11944 {
11945         struct hclge_dev *hdev = ae_dev->priv;
11946         struct pci_dev *pdev = ae_dev->pdev;
11947         int ret;
11948
11949         set_bit(HCLGE_STATE_DOWN, &hdev->state);
11950
11951         hclge_stats_clear(hdev);
11952         /* NOTE: pf reset needn't to clear or restore pf and vf table entry.
11953          * so here should not clean table in memory.
11954          */
11955         if (hdev->reset_type == HNAE3_IMP_RESET ||
11956             hdev->reset_type == HNAE3_GLOBAL_RESET) {
11957                 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table));
11958                 memset(hdev->vf_vlan_full, 0, sizeof(hdev->vf_vlan_full));
11959                 bitmap_set(hdev->vport_config_block, 0, hdev->num_alloc_vport);
11960                 hclge_reset_umv_space(hdev);
11961         }
11962
11963         ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version,
11964                                   true, hdev->reset_pending);
11965         if (ret) {
11966                 dev_err(&pdev->dev, "Cmd queue init failed\n");
11967                 return ret;
11968         }
11969
11970         ret = hclge_map_tqp(hdev);
11971         if (ret) {
11972                 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
11973                 return ret;
11974         }
11975
11976         ret = hclge_mac_init(hdev);
11977         if (ret) {
11978                 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
11979                 return ret;
11980         }
11981
11982         ret = hclge_tp_port_init(hdev);
11983         if (ret) {
11984                 dev_err(&pdev->dev, "failed to init tp port, ret = %d\n",
11985                         ret);
11986                 return ret;
11987         }
11988
11989         ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
11990         if (ret) {
11991                 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
11992                 return ret;
11993         }
11994
11995         ret = hclge_config_gro(hdev);
11996         if (ret)
11997                 return ret;
11998
11999         ret = hclge_init_vlan_config(hdev);
12000         if (ret) {
12001                 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
12002                 return ret;
12003         }
12004
12005         ret = hclge_tm_init_hw(hdev, true);
12006         if (ret) {
12007                 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret);
12008                 return ret;
12009         }
12010
12011         ret = hclge_rss_init_hw(hdev);
12012         if (ret) {
12013                 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
12014                 return ret;
12015         }
12016
12017         ret = init_mgr_tbl(hdev);
12018         if (ret) {
12019                 dev_err(&pdev->dev,
12020                         "failed to reinit manager table, ret = %d\n", ret);
12021                 return ret;
12022         }
12023
12024         ret = hclge_init_fd_config(hdev);
12025         if (ret) {
12026                 dev_err(&pdev->dev, "fd table init fail, ret=%d\n", ret);
12027                 return ret;
12028         }
12029
12030         ret = hclge_ptp_init(hdev);
12031         if (ret)
12032                 return ret;
12033
12034         /* Log and clear the hw errors those already occurred */
12035         if (hnae3_dev_ras_imp_supported(hdev))
12036                 hclge_handle_occurred_error(hdev);
12037         else
12038                 hclge_handle_all_hns_hw_errors(ae_dev);
12039
12040         /* Re-enable the hw error interrupts because
12041          * the interrupts get disabled on global reset.
12042          */
12043         ret = hclge_config_nic_hw_error(hdev, true);
12044         if (ret) {
12045                 dev_err(&pdev->dev,
12046                         "fail(%d) to re-enable NIC hw error interrupts\n",
12047                         ret);
12048                 return ret;
12049         }
12050
12051         if (hdev->roce_client) {
12052                 ret = hclge_config_rocee_ras_interrupt(hdev, true);
12053                 if (ret) {
12054                         dev_err(&pdev->dev,
12055                                 "fail(%d) to re-enable roce ras interrupts\n",
12056                                 ret);
12057                         return ret;
12058                 }
12059         }
12060
12061         hclge_reset_vport_state(hdev);
12062         ret = hclge_reset_vport_spoofchk(hdev);
12063         if (ret)
12064                 return ret;
12065
12066         ret = hclge_resume_vf_rate(hdev);
12067         if (ret)
12068                 return ret;
12069
12070         hclge_init_rxd_adv_layout(hdev);
12071
12072         dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
12073                  HCLGE_DRIVER_NAME);
12074
12075         return 0;
12076 }
12077
12078 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
12079 {
12080         struct hclge_dev *hdev = ae_dev->priv;
12081         struct hclge_mac *mac = &hdev->hw.mac;
12082
12083         hclge_reset_vf_rate(hdev);
12084         hclge_clear_vf_vlan(hdev);
12085         hclge_state_uninit(hdev);
12086         hclge_ptp_uninit(hdev);
12087         hclge_uninit_rxd_adv_layout(hdev);
12088         hclge_uninit_mac_table(hdev);
12089         hclge_del_all_fd_entries(hdev);
12090
12091         if (mac->phydev)
12092                 mdiobus_unregister(mac->mdio_bus);
12093
12094         /* Disable MISC vector(vector0) */
12095         hclge_enable_vector(&hdev->misc_vector, false);
12096         synchronize_irq(hdev->misc_vector.vector_irq);
12097
12098         /* Disable all hw interrupts */
12099         hclge_config_mac_tnl_int(hdev, false);
12100         hclge_config_nic_hw_error(hdev, false);
12101         hclge_config_rocee_ras_interrupt(hdev, false);
12102
12103         hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw);
12104         hclge_misc_irq_uninit(hdev);
12105         hclge_devlink_uninit(hdev);
12106         hclge_pci_uninit(hdev);
12107         hclge_uninit_vport_vlan_table(hdev);
12108         mutex_destroy(&hdev->vport_lock);
12109         ae_dev->priv = NULL;
12110 }
12111
12112 static u32 hclge_get_max_channels(struct hnae3_handle *handle)
12113 {
12114         struct hclge_vport *vport = hclge_get_vport(handle);
12115         struct hclge_dev *hdev = vport->back;
12116
12117         return min_t(u32, hdev->pf_rss_size_max, vport->alloc_tqps);
12118 }
12119
12120 static void hclge_get_channels(struct hnae3_handle *handle,
12121                                struct ethtool_channels *ch)
12122 {
12123         ch->max_combined = hclge_get_max_channels(handle);
12124         ch->other_count = 1;
12125         ch->max_other = 1;
12126         ch->combined_count = handle->kinfo.rss_size;
12127 }
12128
12129 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
12130                                         u16 *alloc_tqps, u16 *max_rss_size)
12131 {
12132         struct hclge_vport *vport = hclge_get_vport(handle);
12133         struct hclge_dev *hdev = vport->back;
12134
12135         *alloc_tqps = vport->alloc_tqps;
12136         *max_rss_size = hdev->pf_rss_size_max;
12137 }
12138
12139 static int hclge_set_rss_tc_mode_cfg(struct hnae3_handle *handle)
12140 {
12141         struct hclge_vport *vport = hclge_get_vport(handle);
12142         u16 tc_offset[HCLGE_MAX_TC_NUM] = {0};
12143         struct hclge_dev *hdev = vport->back;
12144         u16 tc_size[HCLGE_MAX_TC_NUM] = {0};
12145         u16 tc_valid[HCLGE_MAX_TC_NUM];
12146         u16 roundup_size;
12147         unsigned int i;
12148
12149         roundup_size = roundup_pow_of_two(vport->nic.kinfo.rss_size);
12150         roundup_size = ilog2(roundup_size);
12151         /* Set the RSS TC mode according to the new RSS size */
12152         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
12153                 tc_valid[i] = 0;
12154
12155                 if (!(hdev->hw_tc_map & BIT(i)))
12156                         continue;
12157
12158                 tc_valid[i] = 1;
12159                 tc_size[i] = roundup_size;
12160                 tc_offset[i] = vport->nic.kinfo.rss_size * i;
12161         }
12162
12163         return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid,
12164                                           tc_size);
12165 }
12166
12167 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num,
12168                               bool rxfh_configured)
12169 {
12170         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
12171         struct hclge_vport *vport = hclge_get_vport(handle);
12172         struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
12173         struct hclge_dev *hdev = vport->back;
12174         u16 cur_rss_size = kinfo->rss_size;
12175         u16 cur_tqps = kinfo->num_tqps;
12176         u32 *rss_indir;
12177         unsigned int i;
12178         int ret;
12179
12180         kinfo->req_rss_size = new_tqps_num;
12181
12182         ret = hclge_tm_vport_map_update(hdev);
12183         if (ret) {
12184                 dev_err(&hdev->pdev->dev, "tm vport map fail, ret =%d\n", ret);
12185                 return ret;
12186         }
12187
12188         ret = hclge_set_rss_tc_mode_cfg(handle);
12189         if (ret)
12190                 return ret;
12191
12192         /* RSS indirection table has been configured by user */
12193         if (rxfh_configured)
12194                 goto out;
12195
12196         /* Reinitializes the rss indirect table according to the new RSS size */
12197         rss_indir = kcalloc(ae_dev->dev_specs.rss_ind_tbl_size, sizeof(u32),
12198                             GFP_KERNEL);
12199         if (!rss_indir)
12200                 return -ENOMEM;
12201
12202         for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++)
12203                 rss_indir[i] = i % kinfo->rss_size;
12204
12205         ret = hclge_set_rss(handle, rss_indir, NULL, 0);
12206         if (ret)
12207                 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
12208                         ret);
12209
12210         kfree(rss_indir);
12211
12212 out:
12213         if (!ret)
12214                 dev_info(&hdev->pdev->dev,
12215                          "Channels changed, rss_size from %u to %u, tqps from %u to %u",
12216                          cur_rss_size, kinfo->rss_size,
12217                          cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc);
12218
12219         return ret;
12220 }
12221
12222 static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit,
12223                               u32 *regs_num_64_bit)
12224 {
12225         struct hclge_desc desc;
12226         u32 total_num;
12227         int ret;
12228
12229         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true);
12230         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
12231         if (ret) {
12232                 dev_err(&hdev->pdev->dev,
12233                         "Query register number cmd failed, ret = %d.\n", ret);
12234                 return ret;
12235         }
12236
12237         *regs_num_32_bit = le32_to_cpu(desc.data[0]);
12238         *regs_num_64_bit = le32_to_cpu(desc.data[1]);
12239
12240         total_num = *regs_num_32_bit + *regs_num_64_bit;
12241         if (!total_num)
12242                 return -EINVAL;
12243
12244         return 0;
12245 }
12246
12247 static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num,
12248                                  void *data)
12249 {
12250 #define HCLGE_32_BIT_REG_RTN_DATANUM 8
12251 #define HCLGE_32_BIT_DESC_NODATA_LEN 2
12252
12253         struct hclge_desc *desc;
12254         u32 *reg_val = data;
12255         __le32 *desc_data;
12256         int nodata_num;
12257         int cmd_num;
12258         int i, k, n;
12259         int ret;
12260
12261         if (regs_num == 0)
12262                 return 0;
12263
12264         nodata_num = HCLGE_32_BIT_DESC_NODATA_LEN;
12265         cmd_num = DIV_ROUND_UP(regs_num + nodata_num,
12266                                HCLGE_32_BIT_REG_RTN_DATANUM);
12267         desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
12268         if (!desc)
12269                 return -ENOMEM;
12270
12271         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true);
12272         ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
12273         if (ret) {
12274                 dev_err(&hdev->pdev->dev,
12275                         "Query 32 bit register cmd failed, ret = %d.\n", ret);
12276                 kfree(desc);
12277                 return ret;
12278         }
12279
12280         for (i = 0; i < cmd_num; i++) {
12281                 if (i == 0) {
12282                         desc_data = (__le32 *)(&desc[i].data[0]);
12283                         n = HCLGE_32_BIT_REG_RTN_DATANUM - nodata_num;
12284                 } else {
12285                         desc_data = (__le32 *)(&desc[i]);
12286                         n = HCLGE_32_BIT_REG_RTN_DATANUM;
12287                 }
12288                 for (k = 0; k < n; k++) {
12289                         *reg_val++ = le32_to_cpu(*desc_data++);
12290
12291                         regs_num--;
12292                         if (!regs_num)
12293                                 break;
12294                 }
12295         }
12296
12297         kfree(desc);
12298         return 0;
12299 }
12300
12301 static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num,
12302                                  void *data)
12303 {
12304 #define HCLGE_64_BIT_REG_RTN_DATANUM 4
12305 #define HCLGE_64_BIT_DESC_NODATA_LEN 1
12306
12307         struct hclge_desc *desc;
12308         u64 *reg_val = data;
12309         __le64 *desc_data;
12310         int nodata_len;
12311         int cmd_num;
12312         int i, k, n;
12313         int ret;
12314
12315         if (regs_num == 0)
12316                 return 0;
12317
12318         nodata_len = HCLGE_64_BIT_DESC_NODATA_LEN;
12319         cmd_num = DIV_ROUND_UP(regs_num + nodata_len,
12320                                HCLGE_64_BIT_REG_RTN_DATANUM);
12321         desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
12322         if (!desc)
12323                 return -ENOMEM;
12324
12325         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true);
12326         ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
12327         if (ret) {
12328                 dev_err(&hdev->pdev->dev,
12329                         "Query 64 bit register cmd failed, ret = %d.\n", ret);
12330                 kfree(desc);
12331                 return ret;
12332         }
12333
12334         for (i = 0; i < cmd_num; i++) {
12335                 if (i == 0) {
12336                         desc_data = (__le64 *)(&desc[i].data[0]);
12337                         n = HCLGE_64_BIT_REG_RTN_DATANUM - nodata_len;
12338                 } else {
12339                         desc_data = (__le64 *)(&desc[i]);
12340                         n = HCLGE_64_BIT_REG_RTN_DATANUM;
12341                 }
12342                 for (k = 0; k < n; k++) {
12343                         *reg_val++ = le64_to_cpu(*desc_data++);
12344
12345                         regs_num--;
12346                         if (!regs_num)
12347                                 break;
12348                 }
12349         }
12350
12351         kfree(desc);
12352         return 0;
12353 }
12354
12355 #define MAX_SEPARATE_NUM        4
12356 #define SEPARATOR_VALUE         0xFDFCFBFA
12357 #define REG_NUM_PER_LINE        4
12358 #define REG_LEN_PER_LINE        (REG_NUM_PER_LINE * sizeof(u32))
12359 #define REG_SEPARATOR_LINE      1
12360 #define REG_NUM_REMAIN_MASK     3
12361
12362 int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev, struct hclge_desc *desc)
12363 {
12364         int i;
12365
12366         /* initialize command BD except the last one */
12367         for (i = 0; i < HCLGE_GET_DFX_REG_TYPE_CNT - 1; i++) {
12368                 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_DFX_BD_NUM,
12369                                            true);
12370                 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
12371         }
12372
12373         /* initialize the last command BD */
12374         hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_DFX_BD_NUM, true);
12375
12376         return hclge_cmd_send(&hdev->hw, desc, HCLGE_GET_DFX_REG_TYPE_CNT);
12377 }
12378
12379 static int hclge_get_dfx_reg_bd_num(struct hclge_dev *hdev,
12380                                     int *bd_num_list,
12381                                     u32 type_num)
12382 {
12383         u32 entries_per_desc, desc_index, index, offset, i;
12384         struct hclge_desc desc[HCLGE_GET_DFX_REG_TYPE_CNT];
12385         int ret;
12386
12387         ret = hclge_query_bd_num_cmd_send(hdev, desc);
12388         if (ret) {
12389                 dev_err(&hdev->pdev->dev,
12390                         "Get dfx bd num fail, status is %d.\n", ret);
12391                 return ret;
12392         }
12393
12394         entries_per_desc = ARRAY_SIZE(desc[0].data);
12395         for (i = 0; i < type_num; i++) {
12396                 offset = hclge_dfx_bd_offset_list[i];
12397                 index = offset % entries_per_desc;
12398                 desc_index = offset / entries_per_desc;
12399                 bd_num_list[i] = le32_to_cpu(desc[desc_index].data[index]);
12400         }
12401
12402         return ret;
12403 }
12404
12405 static int hclge_dfx_reg_cmd_send(struct hclge_dev *hdev,
12406                                   struct hclge_desc *desc_src, int bd_num,
12407                                   enum hclge_opcode_type cmd)
12408 {
12409         struct hclge_desc *desc = desc_src;
12410         int i, ret;
12411
12412         hclge_cmd_setup_basic_desc(desc, cmd, true);
12413         for (i = 0; i < bd_num - 1; i++) {
12414                 desc->flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
12415                 desc++;
12416                 hclge_cmd_setup_basic_desc(desc, cmd, true);
12417         }
12418
12419         desc = desc_src;
12420         ret = hclge_cmd_send(&hdev->hw, desc, bd_num);
12421         if (ret)
12422                 dev_err(&hdev->pdev->dev,
12423                         "Query dfx reg cmd(0x%x) send fail, status is %d.\n",
12424                         cmd, ret);
12425
12426         return ret;
12427 }
12428
12429 static int hclge_dfx_reg_fetch_data(struct hclge_desc *desc_src, int bd_num,
12430                                     void *data)
12431 {
12432         int entries_per_desc, reg_num, separator_num, desc_index, index, i;
12433         struct hclge_desc *desc = desc_src;
12434         u32 *reg = data;
12435
12436         entries_per_desc = ARRAY_SIZE(desc->data);
12437         reg_num = entries_per_desc * bd_num;
12438         separator_num = REG_NUM_PER_LINE - (reg_num & REG_NUM_REMAIN_MASK);
12439         for (i = 0; i < reg_num; i++) {
12440                 index = i % entries_per_desc;
12441                 desc_index = i / entries_per_desc;
12442                 *reg++ = le32_to_cpu(desc[desc_index].data[index]);
12443         }
12444         for (i = 0; i < separator_num; i++)
12445                 *reg++ = SEPARATOR_VALUE;
12446
12447         return reg_num + separator_num;
12448 }
12449
12450 static int hclge_get_dfx_reg_len(struct hclge_dev *hdev, int *len)
12451 {
12452         u32 dfx_reg_type_num = ARRAY_SIZE(hclge_dfx_bd_offset_list);
12453         int data_len_per_desc, bd_num, i;
12454         int *bd_num_list;
12455         u32 data_len;
12456         int ret;
12457
12458         bd_num_list = kcalloc(dfx_reg_type_num, sizeof(int), GFP_KERNEL);
12459         if (!bd_num_list)
12460                 return -ENOMEM;
12461
12462         ret = hclge_get_dfx_reg_bd_num(hdev, bd_num_list, dfx_reg_type_num);
12463         if (ret) {
12464                 dev_err(&hdev->pdev->dev,
12465                         "Get dfx reg bd num fail, status is %d.\n", ret);
12466                 goto out;
12467         }
12468
12469         data_len_per_desc = sizeof_field(struct hclge_desc, data);
12470         *len = 0;
12471         for (i = 0; i < dfx_reg_type_num; i++) {
12472                 bd_num = bd_num_list[i];
12473                 data_len = data_len_per_desc * bd_num;
12474                 *len += (data_len / REG_LEN_PER_LINE + 1) * REG_LEN_PER_LINE;
12475         }
12476
12477 out:
12478         kfree(bd_num_list);
12479         return ret;
12480 }
12481
12482 static int hclge_get_dfx_reg(struct hclge_dev *hdev, void *data)
12483 {
12484         u32 dfx_reg_type_num = ARRAY_SIZE(hclge_dfx_bd_offset_list);
12485         int bd_num, bd_num_max, buf_len, i;
12486         struct hclge_desc *desc_src;
12487         int *bd_num_list;
12488         u32 *reg = data;
12489         int ret;
12490
12491         bd_num_list = kcalloc(dfx_reg_type_num, sizeof(int), GFP_KERNEL);
12492         if (!bd_num_list)
12493                 return -ENOMEM;
12494
12495         ret = hclge_get_dfx_reg_bd_num(hdev, bd_num_list, dfx_reg_type_num);
12496         if (ret) {
12497                 dev_err(&hdev->pdev->dev,
12498                         "Get dfx reg bd num fail, status is %d.\n", ret);
12499                 goto out;
12500         }
12501
12502         bd_num_max = bd_num_list[0];
12503         for (i = 1; i < dfx_reg_type_num; i++)
12504                 bd_num_max = max_t(int, bd_num_max, bd_num_list[i]);
12505
12506         buf_len = sizeof(*desc_src) * bd_num_max;
12507         desc_src = kzalloc(buf_len, GFP_KERNEL);
12508         if (!desc_src) {
12509                 ret = -ENOMEM;
12510                 goto out;
12511         }
12512
12513         for (i = 0; i < dfx_reg_type_num; i++) {
12514                 bd_num = bd_num_list[i];
12515                 ret = hclge_dfx_reg_cmd_send(hdev, desc_src, bd_num,
12516                                              hclge_dfx_reg_opcode_list[i]);
12517                 if (ret) {
12518                         dev_err(&hdev->pdev->dev,
12519                                 "Get dfx reg fail, status is %d.\n", ret);
12520                         break;
12521                 }
12522
12523                 reg += hclge_dfx_reg_fetch_data(desc_src, bd_num, reg);
12524         }
12525
12526         kfree(desc_src);
12527 out:
12528         kfree(bd_num_list);
12529         return ret;
12530 }
12531
12532 static int hclge_fetch_pf_reg(struct hclge_dev *hdev, void *data,
12533                               struct hnae3_knic_private_info *kinfo)
12534 {
12535 #define HCLGE_RING_REG_OFFSET           0x200
12536 #define HCLGE_RING_INT_REG_OFFSET       0x4
12537
12538         int i, j, reg_num, separator_num;
12539         int data_num_sum;
12540         u32 *reg = data;
12541
12542         /* fetching per-PF registers valus from PF PCIe register space */
12543         reg_num = ARRAY_SIZE(cmdq_reg_addr_list);
12544         separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK);
12545         for (i = 0; i < reg_num; i++)
12546                 *reg++ = hclge_read_dev(&hdev->hw, cmdq_reg_addr_list[i]);
12547         for (i = 0; i < separator_num; i++)
12548                 *reg++ = SEPARATOR_VALUE;
12549         data_num_sum = reg_num + separator_num;
12550
12551         reg_num = ARRAY_SIZE(common_reg_addr_list);
12552         separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK);
12553         for (i = 0; i < reg_num; i++)
12554                 *reg++ = hclge_read_dev(&hdev->hw, common_reg_addr_list[i]);
12555         for (i = 0; i < separator_num; i++)
12556                 *reg++ = SEPARATOR_VALUE;
12557         data_num_sum += reg_num + separator_num;
12558
12559         reg_num = ARRAY_SIZE(ring_reg_addr_list);
12560         separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK);
12561         for (j = 0; j < kinfo->num_tqps; j++) {
12562                 for (i = 0; i < reg_num; i++)
12563                         *reg++ = hclge_read_dev(&hdev->hw,
12564                                                 ring_reg_addr_list[i] +
12565                                                 HCLGE_RING_REG_OFFSET * j);
12566                 for (i = 0; i < separator_num; i++)
12567                         *reg++ = SEPARATOR_VALUE;
12568         }
12569         data_num_sum += (reg_num + separator_num) * kinfo->num_tqps;
12570
12571         reg_num = ARRAY_SIZE(tqp_intr_reg_addr_list);
12572         separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK);
12573         for (j = 0; j < hdev->num_msi_used - 1; j++) {
12574                 for (i = 0; i < reg_num; i++)
12575                         *reg++ = hclge_read_dev(&hdev->hw,
12576                                                 tqp_intr_reg_addr_list[i] +
12577                                                 HCLGE_RING_INT_REG_OFFSET * j);
12578                 for (i = 0; i < separator_num; i++)
12579                         *reg++ = SEPARATOR_VALUE;
12580         }
12581         data_num_sum += (reg_num + separator_num) * (hdev->num_msi_used - 1);
12582
12583         return data_num_sum;
12584 }
12585
12586 static int hclge_get_regs_len(struct hnae3_handle *handle)
12587 {
12588         int cmdq_lines, common_lines, ring_lines, tqp_intr_lines;
12589         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
12590         struct hclge_vport *vport = hclge_get_vport(handle);
12591         struct hclge_dev *hdev = vport->back;
12592         int regs_num_32_bit, regs_num_64_bit, dfx_regs_len;
12593         int regs_lines_32_bit, regs_lines_64_bit;
12594         int ret;
12595
12596         ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
12597         if (ret) {
12598                 dev_err(&hdev->pdev->dev,
12599                         "Get register number failed, ret = %d.\n", ret);
12600                 return ret;
12601         }
12602
12603         ret = hclge_get_dfx_reg_len(hdev, &dfx_regs_len);
12604         if (ret) {
12605                 dev_err(&hdev->pdev->dev,
12606                         "Get dfx reg len failed, ret = %d.\n", ret);
12607                 return ret;
12608         }
12609
12610         cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE +
12611                 REG_SEPARATOR_LINE;
12612         common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE +
12613                 REG_SEPARATOR_LINE;
12614         ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE +
12615                 REG_SEPARATOR_LINE;
12616         tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE +
12617                 REG_SEPARATOR_LINE;
12618         regs_lines_32_bit = regs_num_32_bit * sizeof(u32) / REG_LEN_PER_LINE +
12619                 REG_SEPARATOR_LINE;
12620         regs_lines_64_bit = regs_num_64_bit * sizeof(u64) / REG_LEN_PER_LINE +
12621                 REG_SEPARATOR_LINE;
12622
12623         return (cmdq_lines + common_lines + ring_lines * kinfo->num_tqps +
12624                 tqp_intr_lines * (hdev->num_msi_used - 1) + regs_lines_32_bit +
12625                 regs_lines_64_bit) * REG_LEN_PER_LINE + dfx_regs_len;
12626 }
12627
12628 static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
12629                            void *data)
12630 {
12631         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
12632         struct hclge_vport *vport = hclge_get_vport(handle);
12633         struct hclge_dev *hdev = vport->back;
12634         u32 regs_num_32_bit, regs_num_64_bit;
12635         int i, reg_num, separator_num, ret;
12636         u32 *reg = data;
12637
12638         *version = hdev->fw_version;
12639
12640         ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
12641         if (ret) {
12642                 dev_err(&hdev->pdev->dev,
12643                         "Get register number failed, ret = %d.\n", ret);
12644                 return;
12645         }
12646
12647         reg += hclge_fetch_pf_reg(hdev, reg, kinfo);
12648
12649         ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, reg);
12650         if (ret) {
12651                 dev_err(&hdev->pdev->dev,
12652                         "Get 32 bit register failed, ret = %d.\n", ret);
12653                 return;
12654         }
12655         reg_num = regs_num_32_bit;
12656         reg += reg_num;
12657         separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK);
12658         for (i = 0; i < separator_num; i++)
12659                 *reg++ = SEPARATOR_VALUE;
12660
12661         ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit, reg);
12662         if (ret) {
12663                 dev_err(&hdev->pdev->dev,
12664                         "Get 64 bit register failed, ret = %d.\n", ret);
12665                 return;
12666         }
12667         reg_num = regs_num_64_bit * 2;
12668         reg += reg_num;
12669         separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK);
12670         for (i = 0; i < separator_num; i++)
12671                 *reg++ = SEPARATOR_VALUE;
12672
12673         ret = hclge_get_dfx_reg(hdev, reg);
12674         if (ret)
12675                 dev_err(&hdev->pdev->dev,
12676                         "Get dfx register failed, ret = %d.\n", ret);
12677 }
12678
12679 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status)
12680 {
12681         struct hclge_set_led_state_cmd *req;
12682         struct hclge_desc desc;
12683         int ret;
12684
12685         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false);
12686
12687         req = (struct hclge_set_led_state_cmd *)desc.data;
12688         hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M,
12689                         HCLGE_LED_LOCATE_STATE_S, locate_led_status);
12690
12691         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
12692         if (ret)
12693                 dev_err(&hdev->pdev->dev,
12694                         "Send set led state cmd error, ret =%d\n", ret);
12695
12696         return ret;
12697 }
12698
12699 enum hclge_led_status {
12700         HCLGE_LED_OFF,
12701         HCLGE_LED_ON,
12702         HCLGE_LED_NO_CHANGE = 0xFF,
12703 };
12704
12705 static int hclge_set_led_id(struct hnae3_handle *handle,
12706                             enum ethtool_phys_id_state status)
12707 {
12708         struct hclge_vport *vport = hclge_get_vport(handle);
12709         struct hclge_dev *hdev = vport->back;
12710
12711         switch (status) {
12712         case ETHTOOL_ID_ACTIVE:
12713                 return hclge_set_led_status(hdev, HCLGE_LED_ON);
12714         case ETHTOOL_ID_INACTIVE:
12715                 return hclge_set_led_status(hdev, HCLGE_LED_OFF);
12716         default:
12717                 return -EINVAL;
12718         }
12719 }
12720
12721 static void hclge_get_link_mode(struct hnae3_handle *handle,
12722                                 unsigned long *supported,
12723                                 unsigned long *advertising)
12724 {
12725         unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS);
12726         struct hclge_vport *vport = hclge_get_vport(handle);
12727         struct hclge_dev *hdev = vport->back;
12728         unsigned int idx = 0;
12729
12730         for (; idx < size; idx++) {
12731                 supported[idx] = hdev->hw.mac.supported[idx];
12732                 advertising[idx] = hdev->hw.mac.advertising[idx];
12733         }
12734 }
12735
12736 static int hclge_gro_en(struct hnae3_handle *handle, bool enable)
12737 {
12738         struct hclge_vport *vport = hclge_get_vport(handle);
12739         struct hclge_dev *hdev = vport->back;
12740         bool gro_en_old = hdev->gro_en;
12741         int ret;
12742
12743         hdev->gro_en = enable;
12744         ret = hclge_config_gro(hdev);
12745         if (ret)
12746                 hdev->gro_en = gro_en_old;
12747
12748         return ret;
12749 }
12750
12751 static void hclge_sync_promisc_mode(struct hclge_dev *hdev)
12752 {
12753         struct hclge_vport *vport = &hdev->vport[0];
12754         struct hnae3_handle *handle = &vport->nic;
12755         u8 tmp_flags;
12756         int ret;
12757         u16 i;
12758
12759         if (vport->last_promisc_flags != vport->overflow_promisc_flags) {
12760                 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
12761                 vport->last_promisc_flags = vport->overflow_promisc_flags;
12762         }
12763
12764         if (test_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state)) {
12765                 tmp_flags = handle->netdev_flags | vport->last_promisc_flags;
12766                 ret = hclge_set_promisc_mode(handle, tmp_flags & HNAE3_UPE,
12767                                              tmp_flags & HNAE3_MPE);
12768                 if (!ret) {
12769                         clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE,
12770                                   &vport->state);
12771                         set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE,
12772                                 &vport->state);
12773                 }
12774         }
12775
12776         for (i = 1; i < hdev->num_alloc_vport; i++) {
12777                 bool uc_en = false;
12778                 bool mc_en = false;
12779                 bool bc_en;
12780
12781                 vport = &hdev->vport[i];
12782
12783                 if (!test_and_clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE,
12784                                         &vport->state))
12785                         continue;
12786
12787                 if (vport->vf_info.trusted) {
12788                         uc_en = vport->vf_info.request_uc_en > 0 ||
12789                                 vport->overflow_promisc_flags &
12790                                 HNAE3_OVERFLOW_UPE;
12791                         mc_en = vport->vf_info.request_mc_en > 0 ||
12792                                 vport->overflow_promisc_flags &
12793                                 HNAE3_OVERFLOW_MPE;
12794                 }
12795                 bc_en = vport->vf_info.request_bc_en > 0;
12796
12797                 ret = hclge_cmd_set_promisc_mode(hdev, vport->vport_id, uc_en,
12798                                                  mc_en, bc_en);
12799                 if (ret) {
12800                         set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE,
12801                                 &vport->state);
12802                         return;
12803                 }
12804                 hclge_set_vport_vlan_fltr_change(vport);
12805         }
12806 }
12807
12808 static bool hclge_module_existed(struct hclge_dev *hdev)
12809 {
12810         struct hclge_desc desc;
12811         u32 existed;
12812         int ret;
12813
12814         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_EXIST, true);
12815         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
12816         if (ret) {
12817                 dev_err(&hdev->pdev->dev,
12818                         "failed to get SFP exist state, ret = %d\n", ret);
12819                 return false;
12820         }
12821
12822         existed = le32_to_cpu(desc.data[0]);
12823
12824         return existed != 0;
12825 }
12826
12827 /* need 6 bds(total 140 bytes) in one reading
12828  * return the number of bytes actually read, 0 means read failed.
12829  */
12830 static u16 hclge_get_sfp_eeprom_info(struct hclge_dev *hdev, u32 offset,
12831                                      u32 len, u8 *data)
12832 {
12833         struct hclge_desc desc[HCLGE_SFP_INFO_CMD_NUM];
12834         struct hclge_sfp_info_bd0_cmd *sfp_info_bd0;
12835         u16 read_len;
12836         u16 copy_len;
12837         int ret;
12838         int i;
12839
12840         /* setup all 6 bds to read module eeprom info. */
12841         for (i = 0; i < HCLGE_SFP_INFO_CMD_NUM; i++) {
12842                 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_SFP_EEPROM,
12843                                            true);
12844
12845                 /* bd0~bd4 need next flag */
12846                 if (i < HCLGE_SFP_INFO_CMD_NUM - 1)
12847                         desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
12848         }
12849
12850         /* setup bd0, this bd contains offset and read length. */
12851         sfp_info_bd0 = (struct hclge_sfp_info_bd0_cmd *)desc[0].data;
12852         sfp_info_bd0->offset = cpu_to_le16((u16)offset);
12853         read_len = min_t(u16, len, HCLGE_SFP_INFO_MAX_LEN);
12854         sfp_info_bd0->read_len = cpu_to_le16(read_len);
12855
12856         ret = hclge_cmd_send(&hdev->hw, desc, i);
12857         if (ret) {
12858                 dev_err(&hdev->pdev->dev,
12859                         "failed to get SFP eeprom info, ret = %d\n", ret);
12860                 return 0;
12861         }
12862
12863         /* copy sfp info from bd0 to out buffer. */
12864         copy_len = min_t(u16, len, HCLGE_SFP_INFO_BD0_LEN);
12865         memcpy(data, sfp_info_bd0->data, copy_len);
12866         read_len = copy_len;
12867
12868         /* copy sfp info from bd1~bd5 to out buffer if needed. */
12869         for (i = 1; i < HCLGE_SFP_INFO_CMD_NUM; i++) {
12870                 if (read_len >= len)
12871                         return read_len;
12872
12873                 copy_len = min_t(u16, len - read_len, HCLGE_SFP_INFO_BDX_LEN);
12874                 memcpy(data + read_len, desc[i].data, copy_len);
12875                 read_len += copy_len;
12876         }
12877
12878         return read_len;
12879 }
12880
12881 static int hclge_get_module_eeprom(struct hnae3_handle *handle, u32 offset,
12882                                    u32 len, u8 *data)
12883 {
12884         struct hclge_vport *vport = hclge_get_vport(handle);
12885         struct hclge_dev *hdev = vport->back;
12886         u32 read_len = 0;
12887         u16 data_len;
12888
12889         if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER)
12890                 return -EOPNOTSUPP;
12891
12892         if (!hclge_module_existed(hdev))
12893                 return -ENXIO;
12894
12895         while (read_len < len) {
12896                 data_len = hclge_get_sfp_eeprom_info(hdev,
12897                                                      offset + read_len,
12898                                                      len - read_len,
12899                                                      data + read_len);
12900                 if (!data_len)
12901                         return -EIO;
12902
12903                 read_len += data_len;
12904         }
12905
12906         return 0;
12907 }
12908
12909 static int hclge_get_link_diagnosis_info(struct hnae3_handle *handle,
12910                                          u32 *status_code)
12911 {
12912         struct hclge_vport *vport = hclge_get_vport(handle);
12913         struct hclge_dev *hdev = vport->back;
12914         struct hclge_desc desc;
12915         int ret;
12916
12917         if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2)
12918                 return -EOPNOTSUPP;
12919
12920         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_DIAGNOSIS, true);
12921         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
12922         if (ret) {
12923                 dev_err(&hdev->pdev->dev,
12924                         "failed to query link diagnosis info, ret = %d\n", ret);
12925                 return ret;
12926         }
12927
12928         *status_code = le32_to_cpu(desc.data[0]);
12929         return 0;
12930 }
12931
12932 /* After disable sriov, VF still has some config and info need clean,
12933  * which configed by PF.
12934  */
12935 static void hclge_clear_vport_vf_info(struct hclge_vport *vport, int vfid)
12936 {
12937         struct hclge_dev *hdev = vport->back;
12938         struct hclge_vlan_info vlan_info;
12939         int ret;
12940
12941         /* after disable sriov, clean VF rate configured by PF */
12942         ret = hclge_tm_qs_shaper_cfg(vport, 0);
12943         if (ret)
12944                 dev_err(&hdev->pdev->dev,
12945                         "failed to clean vf%d rate config, ret = %d\n",
12946                         vfid, ret);
12947
12948         vlan_info.vlan_tag = 0;
12949         vlan_info.qos = 0;
12950         vlan_info.vlan_proto = ETH_P_8021Q;
12951         ret = hclge_update_port_base_vlan_cfg(vport,
12952                                               HNAE3_PORT_BASE_VLAN_DISABLE,
12953                                               &vlan_info);
12954         if (ret)
12955                 dev_err(&hdev->pdev->dev,
12956                         "failed to clean vf%d port base vlan, ret = %d\n",
12957                         vfid, ret);
12958
12959         ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, false);
12960         if (ret)
12961                 dev_err(&hdev->pdev->dev,
12962                         "failed to clean vf%d spoof config, ret = %d\n",
12963                         vfid, ret);
12964
12965         memset(&vport->vf_info, 0, sizeof(vport->vf_info));
12966 }
12967
12968 static void hclge_clean_vport_config(struct hnae3_ae_dev *ae_dev, int num_vfs)
12969 {
12970         struct hclge_dev *hdev = ae_dev->priv;
12971         struct hclge_vport *vport;
12972         int i;
12973
12974         for (i = 0; i < num_vfs; i++) {
12975                 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM];
12976
12977                 hclge_clear_vport_vf_info(vport, i);
12978         }
12979 }
12980
12981 static int hclge_get_dscp_prio(struct hnae3_handle *h, u8 dscp, u8 *tc_mode,
12982                                u8 *priority)
12983 {
12984         struct hclge_vport *vport = hclge_get_vport(h);
12985         struct hclge_dev *hdev = vport->back;
12986
12987         if (dscp >= HCLGE_MAX_DSCP)
12988                 return -EINVAL;
12989
12990         if (tc_mode)
12991                 *tc_mode = vport->nic.kinfo.tc_map_mode;
12992         if (priority)
12993                 *priority = hdev->tm_info.dscp_prio[dscp] == HCLGE_PRIO_ID_INVALID ? 0 :
12994                             hdev->tm_info.dscp_prio[dscp];
12995
12996         return 0;
12997 }
12998
12999 static const struct hnae3_ae_ops hclge_ops = {
13000         .init_ae_dev = hclge_init_ae_dev,
13001         .uninit_ae_dev = hclge_uninit_ae_dev,
13002         .reset_prepare = hclge_reset_prepare_general,
13003         .reset_done = hclge_reset_done,
13004         .init_client_instance = hclge_init_client_instance,
13005         .uninit_client_instance = hclge_uninit_client_instance,
13006         .map_ring_to_vector = hclge_map_ring_to_vector,
13007         .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
13008         .get_vector = hclge_get_vector,
13009         .put_vector = hclge_put_vector,
13010         .set_promisc_mode = hclge_set_promisc_mode,
13011         .request_update_promisc_mode = hclge_request_update_promisc_mode,
13012         .set_loopback = hclge_set_loopback,
13013         .start = hclge_ae_start,
13014         .stop = hclge_ae_stop,
13015         .client_start = hclge_client_start,
13016         .client_stop = hclge_client_stop,
13017         .get_status = hclge_get_status,
13018         .get_ksettings_an_result = hclge_get_ksettings_an_result,
13019         .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
13020         .get_media_type = hclge_get_media_type,
13021         .check_port_speed = hclge_check_port_speed,
13022         .get_fec_stats = hclge_get_fec_stats,
13023         .get_fec = hclge_get_fec,
13024         .set_fec = hclge_set_fec,
13025         .get_rss_key_size = hclge_comm_get_rss_key_size,
13026         .get_rss = hclge_get_rss,
13027         .set_rss = hclge_set_rss,
13028         .set_rss_tuple = hclge_set_rss_tuple,
13029         .get_rss_tuple = hclge_get_rss_tuple,
13030         .get_tc_size = hclge_get_tc_size,
13031         .get_mac_addr = hclge_get_mac_addr,
13032         .set_mac_addr = hclge_set_mac_addr,
13033         .do_ioctl = hclge_do_ioctl,
13034         .add_uc_addr = hclge_add_uc_addr,
13035         .rm_uc_addr = hclge_rm_uc_addr,
13036         .add_mc_addr = hclge_add_mc_addr,
13037         .rm_mc_addr = hclge_rm_mc_addr,
13038         .set_autoneg = hclge_set_autoneg,
13039         .get_autoneg = hclge_get_autoneg,
13040         .restart_autoneg = hclge_restart_autoneg,
13041         .halt_autoneg = hclge_halt_autoneg,
13042         .get_pauseparam = hclge_get_pauseparam,
13043         .set_pauseparam = hclge_set_pauseparam,
13044         .set_mtu = hclge_set_mtu,
13045         .reset_queue = hclge_reset_tqp,
13046         .get_stats = hclge_get_stats,
13047         .get_mac_stats = hclge_get_mac_stat,
13048         .update_stats = hclge_update_stats,
13049         .get_strings = hclge_get_strings,
13050         .get_sset_count = hclge_get_sset_count,
13051         .get_fw_version = hclge_get_fw_version,
13052         .get_mdix_mode = hclge_get_mdix_mode,
13053         .enable_vlan_filter = hclge_enable_vlan_filter,
13054         .set_vlan_filter = hclge_set_vlan_filter,
13055         .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
13056         .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
13057         .reset_event = hclge_reset_event,
13058         .get_reset_level = hclge_get_reset_level,
13059         .set_default_reset_request = hclge_set_def_reset_request,
13060         .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
13061         .set_channels = hclge_set_channels,
13062         .get_channels = hclge_get_channels,
13063         .get_regs_len = hclge_get_regs_len,
13064         .get_regs = hclge_get_regs,
13065         .set_led_id = hclge_set_led_id,
13066         .get_link_mode = hclge_get_link_mode,
13067         .add_fd_entry = hclge_add_fd_entry,
13068         .del_fd_entry = hclge_del_fd_entry,
13069         .get_fd_rule_cnt = hclge_get_fd_rule_cnt,
13070         .get_fd_rule_info = hclge_get_fd_rule_info,
13071         .get_fd_all_rules = hclge_get_all_rules,
13072         .enable_fd = hclge_enable_fd,
13073         .add_arfs_entry = hclge_add_fd_entry_by_arfs,
13074         .dbg_read_cmd = hclge_dbg_read_cmd,
13075         .handle_hw_ras_error = hclge_handle_hw_ras_error,
13076         .get_hw_reset_stat = hclge_get_hw_reset_stat,
13077         .ae_dev_resetting = hclge_ae_dev_resetting,
13078         .ae_dev_reset_cnt = hclge_ae_dev_reset_cnt,
13079         .set_gro_en = hclge_gro_en,
13080         .get_global_queue_id = hclge_covert_handle_qid_global,
13081         .set_timer_task = hclge_set_timer_task,
13082         .mac_connect_phy = hclge_mac_connect_phy,
13083         .mac_disconnect_phy = hclge_mac_disconnect_phy,
13084         .get_vf_config = hclge_get_vf_config,
13085         .set_vf_link_state = hclge_set_vf_link_state,
13086         .set_vf_spoofchk = hclge_set_vf_spoofchk,
13087         .set_vf_trust = hclge_set_vf_trust,
13088         .set_vf_rate = hclge_set_vf_rate,
13089         .set_vf_mac = hclge_set_vf_mac,
13090         .get_module_eeprom = hclge_get_module_eeprom,
13091         .get_cmdq_stat = hclge_get_cmdq_stat,
13092         .add_cls_flower = hclge_add_cls_flower,
13093         .del_cls_flower = hclge_del_cls_flower,
13094         .cls_flower_active = hclge_is_cls_flower_active,
13095         .get_phy_link_ksettings = hclge_get_phy_link_ksettings,
13096         .set_phy_link_ksettings = hclge_set_phy_link_ksettings,
13097         .set_tx_hwts_info = hclge_ptp_set_tx_info,
13098         .get_rx_hwts = hclge_ptp_get_rx_hwts,
13099         .get_ts_info = hclge_ptp_get_ts_info,
13100         .get_link_diagnosis_info = hclge_get_link_diagnosis_info,
13101         .clean_vf_config = hclge_clean_vport_config,
13102         .get_dscp_prio = hclge_get_dscp_prio,
13103 };
13104
13105 static struct hnae3_ae_algo ae_algo = {
13106         .ops = &hclge_ops,
13107         .pdev_id_table = ae_algo_pci_tbl,
13108 };
13109
13110 static int hclge_init(void)
13111 {
13112         pr_info("%s is initializing\n", HCLGE_NAME);
13113
13114         hclge_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGE_NAME);
13115         if (!hclge_wq) {
13116                 pr_err("%s: failed to create workqueue\n", HCLGE_NAME);
13117                 return -ENOMEM;
13118         }
13119
13120         hnae3_register_ae_algo(&ae_algo);
13121
13122         return 0;
13123 }
13124
13125 static void hclge_exit(void)
13126 {
13127         hnae3_unregister_ae_algo_prepare(&ae_algo);
13128         hnae3_unregister_ae_algo(&ae_algo);
13129         destroy_workqueue(hclge_wq);
13130 }
13131 module_init(hclge_init);
13132 module_exit(hclge_exit);
13133
13134 MODULE_LICENSE("GPL");
13135 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
13136 MODULE_DESCRIPTION("HCLGE Driver");
13137 MODULE_VERSION(HCLGE_MOD_VERSION);