drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4 #include <linux/acpi.h>
   5 #include <linux/device.h>
   6 #include <linux/etherdevice.h>
   7 #include <linux/init.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/netdevice.h>
  12 #include <linux/pci.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/if_vlan.h>
  15 #include <linux/crash_dump.h>
  16 #include <net/ipv6.h>
  17 #include <net/rtnetlink.h>
  18 #include "hclge_cmd.h"
  19 #include "hclge_dcb.h"
  20 #include "hclge_main.h"
  21 #include "hclge_mbx.h"
  22 #include "hclge_mdio.h"
  23 #include "hclge_regs.h"
  24 #include "hclge_tm.h"
  25 #include "hclge_err.h"
  26 #include "hnae3.h"
  27 #include "hclge_devlink.h"
  28 #include "hclge_comm_cmd.h"
  29
  30 #define HCLGE_NAME                      "hclge"
  31
  32 #define HCLGE_BUF_SIZE_UNIT     256U
  33 #define HCLGE_BUF_MUL_BY        2
  34 #define HCLGE_BUF_DIV_BY        2
  35 #define NEED_RESERVE_TC_NUM     2
  36 #define BUF_MAX_PERCENT         100
  37 #define BUF_RESERVE_PERCENT     90
  38
  39 #define HCLGE_RESET_MAX_FAIL_CNT        5
  40 #define HCLGE_RESET_SYNC_TIME           100
  41 #define HCLGE_PF_RESET_SYNC_TIME        20
  42 #define HCLGE_PF_RESET_SYNC_CNT         1500
  43
  44 #define HCLGE_LINK_STATUS_MS    10
  45
  46 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps);
  47 static int hclge_init_vlan_config(struct hclge_dev *hdev);
  48 static void hclge_sync_vlan_filter(struct hclge_dev *hdev);
  49 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
  50 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle);
  51 static void hclge_rfs_filter_expire(struct hclge_dev *hdev);
  52 static int hclge_clear_arfs_rules(struct hclge_dev *hdev);
  53 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev,
  54                                                    unsigned long *addr);
  55 static int hclge_set_default_loopback(struct hclge_dev *hdev);
  56
  57 static void hclge_sync_mac_table(struct hclge_dev *hdev);
  58 static void hclge_restore_hw_table(struct hclge_dev *hdev);
  59 static void hclge_sync_promisc_mode(struct hclge_dev *hdev);
  60 static void hclge_sync_fd_table(struct hclge_dev *hdev);
  61 static void hclge_update_fec_stats(struct hclge_dev *hdev);
  62 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret,
  63                                       int wait_cnt);
  64
  65 static struct hnae3_ae_algo ae_algo;
  66
  67 static struct workqueue_struct *hclge_wq;
  68
  69 static const struct pci_device_id ae_algo_pci_tbl[] = {
  70         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
  71         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
  72         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
  73         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
  74         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
  75         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
  76         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
  77         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0},
  78         /* required last entry */
  79         {0, }
  80 };
  81
  82 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
  83
  84 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
  85         "External Loopback test",
  86         "App      Loopback test",
  87         "Serdes   serial Loopback test",
  88         "Serdes   parallel Loopback test",
  89         "Phy      Loopback test"
  90 };
  91
  92 static const struct hclge_comm_stats_str g_mac_stats_string[] = {
  93         {"mac_tx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1,
  94                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
  95         {"mac_rx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1,
  96                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
  97         {"mac_tx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
  98                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pause_xoff_time)},
  99         {"mac_rx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 100                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pause_xoff_time)},
 101         {"mac_tx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 102                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_ctrl_pkt_num)},
 103         {"mac_rx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 104                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_ctrl_pkt_num)},
 105         {"mac_tx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 106                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pause_pkt_num)},
 107         {"mac_tx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 108                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
 109         {"mac_tx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 110                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
 111         {"mac_tx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 112                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
 113         {"mac_tx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 114                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
 115         {"mac_tx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 116                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
 117         {"mac_tx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 118                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
 119         {"mac_tx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 120                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
 121         {"mac_tx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 122                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
 123         {"mac_tx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 124                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_xoff_time)},
 125         {"mac_tx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 126                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_xoff_time)},
 127         {"mac_tx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 128                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_xoff_time)},
 129         {"mac_tx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 130                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_xoff_time)},
 131         {"mac_tx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 132                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_xoff_time)},
 133         {"mac_tx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 134                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_xoff_time)},
 135         {"mac_tx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 136                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_xoff_time)},
 137         {"mac_tx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 138                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_xoff_time)},
 139         {"mac_rx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 140                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pause_pkt_num)},
 141         {"mac_rx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 142                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
 143         {"mac_rx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 144                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
 145         {"mac_rx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 146                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
 147         {"mac_rx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 148                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
 149         {"mac_rx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 150                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
 151         {"mac_rx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 152                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
 153         {"mac_rx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 154                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
 155         {"mac_rx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 156                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
 157         {"mac_rx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 158                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_xoff_time)},
 159         {"mac_rx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 160                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_xoff_time)},
 161         {"mac_rx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 162                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_xoff_time)},
 163         {"mac_rx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 164                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_xoff_time)},
 165         {"mac_rx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 166                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_xoff_time)},
 167         {"mac_rx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 168                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_xoff_time)},
 169         {"mac_rx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 170                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_xoff_time)},
 171         {"mac_rx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 172                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_xoff_time)},
 173         {"mac_tx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 174                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
 175         {"mac_tx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 176                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
 177         {"mac_tx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 178                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
 179         {"mac_tx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 180                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
 181         {"mac_tx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 182                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
 183         {"mac_tx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 184                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
 185         {"mac_tx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 186                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
 187         {"mac_tx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 188                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
 189         {"mac_tx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 190                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
 191         {"mac_tx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 192                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
 193         {"mac_tx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 194                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
 195         {"mac_tx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 196                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
 197         {"mac_tx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 198                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
 199         {"mac_tx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 200                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
 201         {"mac_tx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 202                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
 203         {"mac_tx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 204                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
 205         {"mac_tx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 206                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
 207         {"mac_tx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 208                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
 209         {"mac_tx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 210                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
 211         {"mac_tx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 212                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
 213         {"mac_tx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 214                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
 215         {"mac_tx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 216                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
 217         {"mac_tx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 218                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
 219         {"mac_tx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 220                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
 221         {"mac_tx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 222                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
 223         {"mac_rx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 224                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
 225         {"mac_rx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 226                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
 227         {"mac_rx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 228                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
 229         {"mac_rx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 230                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
 231         {"mac_rx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 232                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
 233         {"mac_rx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 234                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
 235         {"mac_rx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 236                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
 237         {"mac_rx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 238                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
 239         {"mac_rx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 240                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
 241         {"mac_rx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 242                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
 243         {"mac_rx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 244                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
 245         {"mac_rx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 246                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
 247         {"mac_rx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 248                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
 249         {"mac_rx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 250                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
 251         {"mac_rx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 252                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
 253         {"mac_rx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 254                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
 255         {"mac_rx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 256                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
 257         {"mac_rx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 258                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
 259         {"mac_rx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 260                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
 261         {"mac_rx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 262                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
 263         {"mac_rx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 264                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
 265         {"mac_rx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 266                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
 267         {"mac_rx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 268                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
 269         {"mac_rx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 270                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
 271         {"mac_rx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 272                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
 273
 274         {"mac_tx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 275                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
 276         {"mac_tx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 277                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
 278         {"mac_tx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 279                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
 280         {"mac_tx_err_all_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 281                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
 282         {"mac_tx_from_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 283                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
 284         {"mac_tx_from_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 285                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
 286         {"mac_rx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 287                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
 288         {"mac_rx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 289                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
 290         {"mac_rx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 291                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
 292         {"mac_rx_fcs_err_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 293                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
 294         {"mac_rx_send_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 295                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
 296         {"mac_rx_send_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 297                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
 298 };
 299
 300 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
 301         {
 302                 .flags = HCLGE_MAC_MGR_MASK_VLAN_B,
 303                 .ethter_type = cpu_to_le16(ETH_P_LLDP),
 304                 .mac_addr = {0x01, 0x80, 0xc2, 0x00, 0x00, 0x0e},
 305                 .i_port_bitmap = 0x1,
 306         },
 307 };
 308
 309 static const struct key_info meta_data_key_info[] = {
 310         { PACKET_TYPE_ID, 6 },
 311         { IP_FRAGEMENT, 1 },
 312         { ROCE_TYPE, 1 },
 313         { NEXT_KEY, 5 },
 314         { VLAN_NUMBER, 2 },
 315         { SRC_VPORT, 12 },
 316         { DST_VPORT, 12 },
 317         { TUNNEL_PACKET, 1 },
 318 };
 319
 320 static const struct key_info tuple_key_info[] = {
 321         { OUTER_DST_MAC, 48, KEY_OPT_MAC, -1, -1 },
 322         { OUTER_SRC_MAC, 48, KEY_OPT_MAC, -1, -1 },
 323         { OUTER_VLAN_TAG_FST, 16, KEY_OPT_LE16, -1, -1 },
 324         { OUTER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 },
 325         { OUTER_ETH_TYPE, 16, KEY_OPT_LE16, -1, -1 },
 326         { OUTER_L2_RSV, 16, KEY_OPT_LE16, -1, -1 },
 327         { OUTER_IP_TOS, 8, KEY_OPT_U8, -1, -1 },
 328         { OUTER_IP_PROTO, 8, KEY_OPT_U8, -1, -1 },
 329         { OUTER_SRC_IP, 32, KEY_OPT_IP, -1, -1 },
 330         { OUTER_DST_IP, 32, KEY_OPT_IP, -1, -1 },
 331         { OUTER_L3_RSV, 16, KEY_OPT_LE16, -1, -1 },
 332         { OUTER_SRC_PORT, 16, KEY_OPT_LE16, -1, -1 },
 333         { OUTER_DST_PORT, 16, KEY_OPT_LE16, -1, -1 },
 334         { OUTER_L4_RSV, 32, KEY_OPT_LE32, -1, -1 },
 335         { OUTER_TUN_VNI, 24, KEY_OPT_VNI, -1, -1 },
 336         { OUTER_TUN_FLOW_ID, 8, KEY_OPT_U8, -1, -1 },
 337         { INNER_DST_MAC, 48, KEY_OPT_MAC,
 338           offsetof(struct hclge_fd_rule, tuples.dst_mac),
 339           offsetof(struct hclge_fd_rule, tuples_mask.dst_mac) },
 340         { INNER_SRC_MAC, 48, KEY_OPT_MAC,
 341           offsetof(struct hclge_fd_rule, tuples.src_mac),
 342           offsetof(struct hclge_fd_rule, tuples_mask.src_mac) },
 343         { INNER_VLAN_TAG_FST, 16, KEY_OPT_LE16,
 344           offsetof(struct hclge_fd_rule, tuples.vlan_tag1),
 345           offsetof(struct hclge_fd_rule, tuples_mask.vlan_tag1) },
 346         { INNER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 },
 347         { INNER_ETH_TYPE, 16, KEY_OPT_LE16,
 348           offsetof(struct hclge_fd_rule, tuples.ether_proto),
 349           offsetof(struct hclge_fd_rule, tuples_mask.ether_proto) },
 350         { INNER_L2_RSV, 16, KEY_OPT_LE16,
 351           offsetof(struct hclge_fd_rule, tuples.l2_user_def),
 352           offsetof(struct hclge_fd_rule, tuples_mask.l2_user_def) },
 353         { INNER_IP_TOS, 8, KEY_OPT_U8,
 354           offsetof(struct hclge_fd_rule, tuples.ip_tos),
 355           offsetof(struct hclge_fd_rule, tuples_mask.ip_tos) },
 356         { INNER_IP_PROTO, 8, KEY_OPT_U8,
 357           offsetof(struct hclge_fd_rule, tuples.ip_proto),
 358           offsetof(struct hclge_fd_rule, tuples_mask.ip_proto) },
 359         { INNER_SRC_IP, 32, KEY_OPT_IP,
 360           offsetof(struct hclge_fd_rule, tuples.src_ip),
 361           offsetof(struct hclge_fd_rule, tuples_mask.src_ip) },
 362         { INNER_DST_IP, 32, KEY_OPT_IP,
 363           offsetof(struct hclge_fd_rule, tuples.dst_ip),
 364           offsetof(struct hclge_fd_rule, tuples_mask.dst_ip) },
 365         { INNER_L3_RSV, 16, KEY_OPT_LE16,
 366           offsetof(struct hclge_fd_rule, tuples.l3_user_def),
 367           offsetof(struct hclge_fd_rule, tuples_mask.l3_user_def) },
 368         { INNER_SRC_PORT, 16, KEY_OPT_LE16,
 369           offsetof(struct hclge_fd_rule, tuples.src_port),
 370           offsetof(struct hclge_fd_rule, tuples_mask.src_port) },
 371         { INNER_DST_PORT, 16, KEY_OPT_LE16,
 372           offsetof(struct hclge_fd_rule, tuples.dst_port),
 373           offsetof(struct hclge_fd_rule, tuples_mask.dst_port) },
 374         { INNER_L4_RSV, 32, KEY_OPT_LE32,
 375           offsetof(struct hclge_fd_rule, tuples.l4_user_def),
 376           offsetof(struct hclge_fd_rule, tuples_mask.l4_user_def) },
 377 };
 378
 379 /**
 380  * hclge_cmd_send - send command to command queue
 381  * @hw: pointer to the hw struct
 382  * @desc: prefilled descriptor for describing the command
 383  * @num : the number of descriptors to be sent
 384  *
 385  * This is the main send command for command queue, it
 386  * sends the queue, cleans the queue, etc
 387  **/
 388 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num)
 389 {
 390         return hclge_comm_cmd_send(&hw->hw, desc, num);
 391 }
 392
 393 static int hclge_mac_update_stats_defective(struct hclge_dev *hdev)
 394 {
 395 #define HCLGE_MAC_CMD_NUM 21
 396
 397         u64 *data = (u64 *)(&hdev->mac_stats);
 398         struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
 399         __le64 *desc_data;
 400         u32 data_size;
 401         int ret;
 402         u32 i;
 403
 404         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
 405         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
 406         if (ret) {
 407                 dev_err(&hdev->pdev->dev,
 408                         "Get MAC pkt stats fail, status = %d.\n", ret);
 409
 410                 return ret;
 411         }
 412
 413         /* The first desc has a 64-bit header, so data size need to minus 1 */
 414         data_size = sizeof(desc) / (sizeof(u64)) - 1;
 415
 416         desc_data = (__le64 *)(&desc[0].data[0]);
 417         for (i = 0; i < data_size; i++) {
 418                 /* data memory is continuous becase only the first desc has a
 419                  * header in this command
 420                  */
 421                 *data += le64_to_cpu(*desc_data);
 422                 data++;
 423                 desc_data++;
 424         }
 425
 426         return 0;
 427 }
 428
 429 static int hclge_mac_update_stats_complete(struct hclge_dev *hdev)
 430 {
 431 #define HCLGE_REG_NUM_PER_DESC          4
 432
 433         u32 reg_num = hdev->ae_dev->dev_specs.mac_stats_num;
 434         u64 *data = (u64 *)(&hdev->mac_stats);
 435         struct hclge_desc *desc;
 436         __le64 *desc_data;
 437         u32 data_size;
 438         u32 desc_num;
 439         int ret;
 440         u32 i;
 441
 442         /* The first desc has a 64-bit header, so need to consider it */
 443         desc_num = reg_num / HCLGE_REG_NUM_PER_DESC + 1;
 444
 445         /* This may be called inside atomic sections,
 446          * so GFP_ATOMIC is more suitalbe here
 447          */
 448         desc = kcalloc(desc_num, sizeof(struct hclge_desc), GFP_ATOMIC);
 449         if (!desc)
 450                 return -ENOMEM;
 451
 452         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC_ALL, true);
 453         ret = hclge_cmd_send(&hdev->hw, desc, desc_num);
 454         if (ret) {
 455                 kfree(desc);
 456                 return ret;
 457         }
 458
 459         data_size = min_t(u32, sizeof(hdev->mac_stats) / sizeof(u64), reg_num);
 460
 461         desc_data = (__le64 *)(&desc[0].data[0]);
 462         for (i = 0; i < data_size; i++) {
 463                 /* data memory is continuous becase only the first desc has a
 464                  * header in this command
 465                  */
 466                 *data += le64_to_cpu(*desc_data);
 467                 data++;
 468                 desc_data++;
 469         }
 470
 471         kfree(desc);
 472
 473         return 0;
 474 }
 475
 476 static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *reg_num)
 477 {
 478         struct hclge_desc desc;
 479         int ret;
 480
 481         /* Driver needs total register number of both valid registers and
 482          * reserved registers, but the old firmware only returns number
 483          * of valid registers in device V2. To be compatible with these
 484          * devices, driver uses a fixed value.
 485          */
 486         if (hdev->ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) {
 487                 *reg_num = HCLGE_MAC_STATS_MAX_NUM_V1;
 488                 return 0;
 489         }
 490
 491         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_REG_NUM, true);
 492         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 493         if (ret) {
 494                 dev_err(&hdev->pdev->dev,
 495                         "failed to query mac statistic reg number, ret = %d\n",
 496                         ret);
 497                 return ret;
 498         }
 499
 500         *reg_num = le32_to_cpu(desc.data[0]);
 501         if (*reg_num == 0) {
 502                 dev_err(&hdev->pdev->dev,
 503                         "mac statistic reg number is invalid!\n");
 504                 return -ENODATA;
 505         }
 506
 507         return 0;
 508 }
 509
 510 int hclge_mac_update_stats(struct hclge_dev *hdev)
 511 {
 512         /* The firmware supports the new statistics acquisition method */
 513         if (hdev->ae_dev->dev_specs.mac_stats_num)
 514                 return hclge_mac_update_stats_complete(hdev);
 515         else
 516                 return hclge_mac_update_stats_defective(hdev);
 517 }
 518
 519 static int hclge_comm_get_count(struct hclge_dev *hdev,
 520                                 const struct hclge_comm_stats_str strs[],
 521                                 u32 size)
 522 {
 523         int count = 0;
 524         u32 i;
 525
 526         for (i = 0; i < size; i++)
 527                 if (strs[i].stats_num <= hdev->ae_dev->dev_specs.mac_stats_num)
 528                         count++;
 529
 530         return count;
 531 }
 532
 533 static u64 *hclge_comm_get_stats(struct hclge_dev *hdev,
 534                                  const struct hclge_comm_stats_str strs[],
 535                                  int size, u64 *data)
 536 {
 537         u64 *buf = data;
 538         u32 i;
 539
 540         for (i = 0; i < size; i++) {
 541                 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num)
 542                         continue;
 543
 544                 *buf = HCLGE_STATS_READ(&hdev->mac_stats, strs[i].offset);
 545                 buf++;
 546         }
 547
 548         return buf;
 549 }
 550
 551 static u8 *hclge_comm_get_strings(struct hclge_dev *hdev, u32 stringset,
 552                                   const struct hclge_comm_stats_str strs[],
 553                                   int size, u8 *data)
 554 {
 555         char *buff = (char *)data;
 556         u32 i;
 557
 558         if (stringset != ETH_SS_STATS)
 559                 return buff;
 560
 561         for (i = 0; i < size; i++) {
 562                 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num)
 563                         continue;
 564
 565                 snprintf(buff, ETH_GSTRING_LEN, "%s", strs[i].desc);
 566                 buff = buff + ETH_GSTRING_LEN;
 567         }
 568
 569         return (u8 *)buff;
 570 }
 571
 572 static void hclge_update_stats_for_all(struct hclge_dev *hdev)
 573 {
 574         struct hnae3_handle *handle;
 575         int status;
 576
 577         handle = &hdev->vport[0].nic;
 578         if (handle->client) {
 579                 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw);
 580                 if (status) {
 581                         dev_err(&hdev->pdev->dev,
 582                                 "Update TQPS stats fail, status = %d.\n",
 583                                 status);
 584                 }
 585         }
 586
 587         hclge_update_fec_stats(hdev);
 588
 589         status = hclge_mac_update_stats(hdev);
 590         if (status)
 591                 dev_err(&hdev->pdev->dev,
 592                         "Update MAC stats fail, status = %d.\n", status);
 593 }
 594
 595 static void hclge_update_stats(struct hnae3_handle *handle)
 596 {
 597         struct hclge_vport *vport = hclge_get_vport(handle);
 598         struct hclge_dev *hdev = vport->back;
 599         int status;
 600
 601         if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
 602                 return;
 603
 604         status = hclge_mac_update_stats(hdev);
 605         if (status)
 606                 dev_err(&hdev->pdev->dev,
 607                         "Update MAC stats fail, status = %d.\n",
 608                         status);
 609
 610         status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw);
 611         if (status)
 612                 dev_err(&hdev->pdev->dev,
 613                         "Update TQPS stats fail, status = %d.\n",
 614                         status);
 615
 616         clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
 617 }
 618
 619 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
 620 {
 621 #define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK | \
 622                 HNAE3_SUPPORT_PHY_LOOPBACK | \
 623                 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK | \
 624                 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK | \
 625                 HNAE3_SUPPORT_EXTERNAL_LOOPBACK)
 626
 627         struct hclge_vport *vport = hclge_get_vport(handle);
 628         struct hclge_dev *hdev = vport->back;
 629         int count = 0;
 630
 631         /* Loopback test support rules:
 632          * mac: only GE mode support
 633          * serdes: all mac mode will support include GE/XGE/LGE/CGE
 634          * phy: only support when phy device exist on board
 635          */
 636         if (stringset == ETH_SS_TEST) {
 637                 /* clear loopback bit flags at first */
 638                 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
 639                 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 ||
 640                     hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
 641                     hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
 642                     hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
 643                         count += 1;
 644                         handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK;
 645                 }
 646
 647                 count += 1;
 648                 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK;
 649                 count += 1;
 650                 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK;
 651                 count += 1;
 652                 handle->flags |= HNAE3_SUPPORT_EXTERNAL_LOOPBACK;
 653
 654                 if ((hdev->hw.mac.phydev && hdev->hw.mac.phydev->drv &&
 655                      hdev->hw.mac.phydev->drv->set_loopback) ||
 656                     hnae3_dev_phy_imp_supported(hdev)) {
 657                         count += 1;
 658                         handle->flags |= HNAE3_SUPPORT_PHY_LOOPBACK;
 659                 }
 660         } else if (stringset == ETH_SS_STATS) {
 661                 count = hclge_comm_get_count(hdev, g_mac_stats_string,
 662                                              ARRAY_SIZE(g_mac_stats_string)) +
 663                         hclge_comm_tqps_get_sset_count(handle);
 664         }
 665
 666         return count;
 667 }
 668
 669 static void hclge_get_strings(struct hnae3_handle *handle, u32 stringset,
 670                               u8 *data)
 671 {
 672         struct hclge_vport *vport = hclge_get_vport(handle);
 673         struct hclge_dev *hdev = vport->back;
 674         u8 *p = (char *)data;
 675         int size;
 676
 677         if (stringset == ETH_SS_STATS) {
 678                 size = ARRAY_SIZE(g_mac_stats_string);
 679                 p = hclge_comm_get_strings(hdev, stringset, g_mac_stats_string,
 680                                            size, p);
 681                 p = hclge_comm_tqps_get_strings(handle, p);
 682         } else if (stringset == ETH_SS_TEST) {
 683                 if (handle->flags & HNAE3_SUPPORT_EXTERNAL_LOOPBACK) {
 684                         memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_EXTERNAL],
 685                                ETH_GSTRING_LEN);
 686                         p += ETH_GSTRING_LEN;
 687                 }
 688                 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) {
 689                         memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_APP],
 690                                ETH_GSTRING_LEN);
 691                         p += ETH_GSTRING_LEN;
 692                 }
 693                 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) {
 694                         memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES],
 695                                ETH_GSTRING_LEN);
 696                         p += ETH_GSTRING_LEN;
 697                 }
 698                 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) {
 699                         memcpy(p,
 700                                hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES],
 701                                ETH_GSTRING_LEN);
 702                         p += ETH_GSTRING_LEN;
 703                 }
 704                 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
 705                         memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_PHY],
 706                                ETH_GSTRING_LEN);
 707                         p += ETH_GSTRING_LEN;
 708                 }
 709         }
 710 }
 711
 712 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
 713 {
 714         struct hclge_vport *vport = hclge_get_vport(handle);
 715         struct hclge_dev *hdev = vport->back;
 716         u64 *p;
 717
 718         p = hclge_comm_get_stats(hdev, g_mac_stats_string,
 719                                  ARRAY_SIZE(g_mac_stats_string), data);
 720         p = hclge_comm_tqps_get_stats(handle, p);
 721 }
 722
 723 static void hclge_get_mac_stat(struct hnae3_handle *handle,
 724                                struct hns3_mac_stats *mac_stats)
 725 {
 726         struct hclge_vport *vport = hclge_get_vport(handle);
 727         struct hclge_dev *hdev = vport->back;
 728
 729         hclge_update_stats(handle);
 730
 731         mac_stats->tx_pause_cnt = hdev->mac_stats.mac_tx_mac_pause_num;
 732         mac_stats->rx_pause_cnt = hdev->mac_stats.mac_rx_mac_pause_num;
 733 }
 734
 735 static int hclge_parse_func_status(struct hclge_dev *hdev,
 736                                    struct hclge_func_status_cmd *status)
 737 {
 738 #define HCLGE_MAC_ID_MASK       0xF
 739
 740         if (!(status->pf_state & HCLGE_PF_STATE_DONE))
 741                 return -EINVAL;
 742
 743         /* Set the pf to main pf */
 744         if (status->pf_state & HCLGE_PF_STATE_MAIN)
 745                 hdev->flag |= HCLGE_FLAG_MAIN;
 746         else
 747                 hdev->flag &= ~HCLGE_FLAG_MAIN;
 748
 749         hdev->hw.mac.mac_id = status->mac_id & HCLGE_MAC_ID_MASK;
 750         return 0;
 751 }
 752
 753 static int hclge_query_function_status(struct hclge_dev *hdev)
 754 {
 755 #define HCLGE_QUERY_MAX_CNT     5
 756
 757         struct hclge_func_status_cmd *req;
 758         struct hclge_desc desc;
 759         int timeout = 0;
 760         int ret;
 761
 762         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
 763         req = (struct hclge_func_status_cmd *)desc.data;
 764
 765         do {
 766                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 767                 if (ret) {
 768                         dev_err(&hdev->pdev->dev,
 769                                 "query function status failed %d.\n", ret);
 770                         return ret;
 771                 }
 772
 773                 /* Check pf reset is done */
 774                 if (req->pf_state)
 775                         break;
 776                 usleep_range(1000, 2000);
 777         } while (timeout++ < HCLGE_QUERY_MAX_CNT);
 778
 779         return hclge_parse_func_status(hdev, req);
 780 }
 781
 782 static int hclge_query_pf_resource(struct hclge_dev *hdev)
 783 {
 784         struct hclge_pf_res_cmd *req;
 785         struct hclge_desc desc;
 786         int ret;
 787
 788         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
 789         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 790         if (ret) {
 791                 dev_err(&hdev->pdev->dev,
 792                         "query pf resource failed %d.\n", ret);
 793                 return ret;
 794         }
 795
 796         req = (struct hclge_pf_res_cmd *)desc.data;
 797         hdev->num_tqps = le16_to_cpu(req->tqp_num) +
 798                          le16_to_cpu(req->ext_tqp_num);
 799         hdev->pkt_buf_size = le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
 800
 801         if (req->tx_buf_size)
 802                 hdev->tx_buf_size =
 803                         le16_to_cpu(req->tx_buf_size) << HCLGE_BUF_UNIT_S;
 804         else
 805                 hdev->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
 806
 807         hdev->tx_buf_size = roundup(hdev->tx_buf_size, HCLGE_BUF_SIZE_UNIT);
 808
 809         if (req->dv_buf_size)
 810                 hdev->dv_buf_size =
 811                         le16_to_cpu(req->dv_buf_size) << HCLGE_BUF_UNIT_S;
 812         else
 813                 hdev->dv_buf_size = HCLGE_DEFAULT_DV;
 814
 815         hdev->dv_buf_size = roundup(hdev->dv_buf_size, HCLGE_BUF_SIZE_UNIT);
 816
 817         hdev->num_nic_msi = le16_to_cpu(req->msixcap_localid_number_nic);
 818         if (hdev->num_nic_msi < HNAE3_MIN_VECTOR_NUM) {
 819                 dev_err(&hdev->pdev->dev,
 820                         "only %u msi resources available, not enough for pf(min:2).\n",
 821                         hdev->num_nic_msi);
 822                 return -EINVAL;
 823         }
 824
 825         if (hnae3_dev_roce_supported(hdev)) {
 826                 hdev->num_roce_msi =
 827                         le16_to_cpu(req->pf_intr_vector_number_roce);
 828
 829                 /* PF should have NIC vectors and Roce vectors,
 830                  * NIC vectors are queued before Roce vectors.
 831                  */
 832                 hdev->num_msi = hdev->num_nic_msi + hdev->num_roce_msi;
 833         } else {
 834                 hdev->num_msi = hdev->num_nic_msi;
 835         }
 836
 837         return 0;
 838 }
 839
 840 static int hclge_parse_speed(u8 speed_cmd, u32 *speed)
 841 {
 842         switch (speed_cmd) {
 843         case HCLGE_FW_MAC_SPEED_10M:
 844                 *speed = HCLGE_MAC_SPEED_10M;
 845                 break;
 846         case HCLGE_FW_MAC_SPEED_100M:
 847                 *speed = HCLGE_MAC_SPEED_100M;
 848                 break;
 849         case HCLGE_FW_MAC_SPEED_1G:
 850                 *speed = HCLGE_MAC_SPEED_1G;
 851                 break;
 852         case HCLGE_FW_MAC_SPEED_10G:
 853                 *speed = HCLGE_MAC_SPEED_10G;
 854                 break;
 855         case HCLGE_FW_MAC_SPEED_25G:
 856                 *speed = HCLGE_MAC_SPEED_25G;
 857                 break;
 858         case HCLGE_FW_MAC_SPEED_40G:
 859                 *speed = HCLGE_MAC_SPEED_40G;
 860                 break;
 861         case HCLGE_FW_MAC_SPEED_50G:
 862                 *speed = HCLGE_MAC_SPEED_50G;
 863                 break;
 864         case HCLGE_FW_MAC_SPEED_100G:
 865                 *speed = HCLGE_MAC_SPEED_100G;
 866                 break;
 867         case HCLGE_FW_MAC_SPEED_200G:
 868                 *speed = HCLGE_MAC_SPEED_200G;
 869                 break;
 870         default:
 871                 return -EINVAL;
 872         }
 873
 874         return 0;
 875 }
 876
 877 static const struct hclge_speed_bit_map speed_bit_map[] = {
 878         {HCLGE_MAC_SPEED_10M, HCLGE_SUPPORT_10M_BIT},
 879         {HCLGE_MAC_SPEED_100M, HCLGE_SUPPORT_100M_BIT},
 880         {HCLGE_MAC_SPEED_1G, HCLGE_SUPPORT_1G_BIT},
 881         {HCLGE_MAC_SPEED_10G, HCLGE_SUPPORT_10G_BIT},
 882         {HCLGE_MAC_SPEED_25G, HCLGE_SUPPORT_25G_BIT},
 883         {HCLGE_MAC_SPEED_40G, HCLGE_SUPPORT_40G_BIT},
 884         {HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BIT},
 885         {HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BIT},
 886         {HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BIT},
 887 };
 888
 889 static int hclge_get_speed_bit(u32 speed, u32 *speed_bit)
 890 {
 891         u16 i;
 892
 893         for (i = 0; i < ARRAY_SIZE(speed_bit_map); i++) {
 894                 if (speed == speed_bit_map[i].speed) {
 895                         *speed_bit = speed_bit_map[i].speed_bit;
 896                         return 0;
 897                 }
 898         }
 899
 900         return -EINVAL;
 901 }
 902
 903 static int hclge_check_port_speed(struct hnae3_handle *handle, u32 speed)
 904 {
 905         struct hclge_vport *vport = hclge_get_vport(handle);
 906         struct hclge_dev *hdev = vport->back;
 907         u32 speed_ability = hdev->hw.mac.speed_ability;
 908         u32 speed_bit = 0;
 909         int ret;
 910
 911         ret = hclge_get_speed_bit(speed, &speed_bit);
 912         if (ret)
 913                 return ret;
 914
 915         if (speed_bit & speed_ability)
 916                 return 0;
 917
 918         return -EINVAL;
 919 }
 920
 921 static void hclge_update_fec_support(struct hclge_mac *mac)
 922 {
 923         linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, mac->supported);
 924         linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mac->supported);
 925         linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, mac->supported);
 926         linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported);
 927
 928         if (mac->fec_ability & BIT(HNAE3_FEC_BASER))
 929                 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
 930                                  mac->supported);
 931         if (mac->fec_ability & BIT(HNAE3_FEC_RS))
 932                 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
 933                                  mac->supported);
 934         if (mac->fec_ability & BIT(HNAE3_FEC_LLRS))
 935                 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
 936                                  mac->supported);
 937         if (mac->fec_ability & BIT(HNAE3_FEC_NONE))
 938                 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
 939                                  mac->supported);
 940 }
 941
 942 static void hclge_convert_setting_sr(u16 speed_ability,
 943                                      unsigned long *link_mode)
 944 {
 945         if (speed_ability & HCLGE_SUPPORT_10G_BIT)
 946                 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
 947                                  link_mode);
 948         if (speed_ability & HCLGE_SUPPORT_25G_BIT)
 949                 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
 950                                  link_mode);
 951         if (speed_ability & HCLGE_SUPPORT_40G_BIT)
 952                 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
 953                                  link_mode);
 954         if (speed_ability & HCLGE_SUPPORT_50G_BIT)
 955                 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
 956                                  link_mode);
 957         if (speed_ability & HCLGE_SUPPORT_100G_BIT)
 958                 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
 959                                  link_mode);
 960         if (speed_ability & HCLGE_SUPPORT_200G_BIT)
 961                 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
 962                                  link_mode);
 963 }
 964
 965 static void hclge_convert_setting_lr(u16 speed_ability,
 966                                      unsigned long *link_mode)
 967 {
 968         if (speed_ability & HCLGE_SUPPORT_10G_BIT)
 969                 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
 970                                  link_mode);
 971         if (speed_ability & HCLGE_SUPPORT_25G_BIT)
 972                 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
 973                                  link_mode);
 974         if (speed_ability & HCLGE_SUPPORT_50G_BIT)
 975                 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
 976                                  link_mode);
 977         if (speed_ability & HCLGE_SUPPORT_40G_BIT)
 978                 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
 979                                  link_mode);
 980         if (speed_ability & HCLGE_SUPPORT_100G_BIT)
 981                 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
 982                                  link_mode);
 983         if (speed_ability & HCLGE_SUPPORT_200G_BIT)
 984                 linkmode_set_bit(
 985                         ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
 986                         link_mode);
 987 }
 988
 989 static void hclge_convert_setting_cr(u16 speed_ability,
 990                                      unsigned long *link_mode)
 991 {
 992         if (speed_ability & HCLGE_SUPPORT_10G_BIT)
 993                 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
 994                                  link_mode);
 995         if (speed_ability & HCLGE_SUPPORT_25G_BIT)
 996                 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
 997                                  link_mode);
 998         if (speed_ability & HCLGE_SUPPORT_40G_BIT)
 999                 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
1000                                  link_mode);
1001         if (speed_ability & HCLGE_SUPPORT_50G_BIT)
1002                 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
1003                                  link_mode);
1004         if (speed_ability & HCLGE_SUPPORT_100G_BIT)
1005                 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
1006                                  link_mode);
1007         if (speed_ability & HCLGE_SUPPORT_200G_BIT)
1008                 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT,
1009                                  link_mode);
1010 }
1011
1012 static void hclge_convert_setting_kr(u16 speed_ability,
1013                                      unsigned long *link_mode)
1014 {
1015         if (speed_ability & HCLGE_SUPPORT_1G_BIT)
1016                 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
1017                                  link_mode);
1018         if (speed_ability & HCLGE_SUPPORT_10G_BIT)
1019                 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
1020                                  link_mode);
1021         if (speed_ability & HCLGE_SUPPORT_25G_BIT)
1022                 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
1023                                  link_mode);
1024         if (speed_ability & HCLGE_SUPPORT_40G_BIT)
1025                 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
1026                                  link_mode);
1027         if (speed_ability & HCLGE_SUPPORT_50G_BIT)
1028                 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
1029                                  link_mode);
1030         if (speed_ability & HCLGE_SUPPORT_100G_BIT)
1031                 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
1032                                  link_mode);
1033         if (speed_ability & HCLGE_SUPPORT_200G_BIT)
1034                 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
1035                                  link_mode);
1036 }
1037
1038 static void hclge_convert_setting_fec(struct hclge_mac *mac)
1039 {
1040         /* If firmware has reported fec_ability, don't need to convert by speed */
1041         if (mac->fec_ability)
1042                 goto out;
1043
1044         switch (mac->speed) {
1045         case HCLGE_MAC_SPEED_10G:
1046         case HCLGE_MAC_SPEED_40G:
1047                 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_AUTO) |
1048                                    BIT(HNAE3_FEC_NONE);
1049                 break;
1050         case HCLGE_MAC_SPEED_25G:
1051         case HCLGE_MAC_SPEED_50G:
1052                 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_RS) |
1053                                    BIT(HNAE3_FEC_AUTO) | BIT(HNAE3_FEC_NONE);
1054                 break;
1055         case HCLGE_MAC_SPEED_100G:
1056                 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) |
1057                                    BIT(HNAE3_FEC_NONE);
1058                 break;
1059         case HCLGE_MAC_SPEED_200G:
1060                 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) |
1061                                    BIT(HNAE3_FEC_LLRS);
1062                 break;
1063         default:
1064                 mac->fec_ability = 0;
1065                 break;
1066         }
1067
1068 out:
1069         hclge_update_fec_support(mac);
1070 }
1071
1072 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
1073                                         u16 speed_ability)
1074 {
1075         struct hclge_mac *mac = &hdev->hw.mac;
1076
1077         if (speed_ability & HCLGE_SUPPORT_1G_BIT)
1078                 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
1079                                  mac->supported);
1080
1081         hclge_convert_setting_sr(speed_ability, mac->supported);
1082         hclge_convert_setting_lr(speed_ability, mac->supported);
1083         hclge_convert_setting_cr(speed_ability, mac->supported);
1084         if (hnae3_dev_fec_supported(hdev))
1085                 hclge_convert_setting_fec(mac);
1086
1087         if (hnae3_dev_pause_supported(hdev))
1088                 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported);
1089
1090         linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mac->supported);
1091         linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported);
1092 }
1093
1094 static void hclge_parse_backplane_link_mode(struct hclge_dev *hdev,
1095                                             u16 speed_ability)
1096 {
1097         struct hclge_mac *mac = &hdev->hw.mac;
1098
1099         hclge_convert_setting_kr(speed_ability, mac->supported);
1100         if (hnae3_dev_fec_supported(hdev))
1101                 hclge_convert_setting_fec(mac);
1102
1103         if (hnae3_dev_pause_supported(hdev))
1104                 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported);
1105
1106         linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mac->supported);
1107         linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported);
1108 }
1109
1110 static void hclge_parse_copper_link_mode(struct hclge_dev *hdev,
1111                                          u16 speed_ability)
1112 {
1113         unsigned long *supported = hdev->hw.mac.supported;
1114
1115         /* default to support all speed for GE port */
1116         if (!speed_ability)
1117                 speed_ability = HCLGE_SUPPORT_GE;
1118
1119         if (speed_ability & HCLGE_SUPPORT_1G_BIT)
1120                 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1121                                  supported);
1122
1123         if (speed_ability & HCLGE_SUPPORT_100M_BIT) {
1124                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
1125                                  supported);
1126                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
1127                                  supported);
1128         }
1129
1130         if (speed_ability & HCLGE_SUPPORT_10M_BIT) {
1131                 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, supported);
1132                 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, supported);
1133         }
1134
1135         if (hnae3_dev_pause_supported(hdev)) {
1136                 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
1137                 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported);
1138         }
1139
1140         linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported);
1141         linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported);
1142 }
1143
1144 static void hclge_parse_link_mode(struct hclge_dev *hdev, u16 speed_ability)
1145 {
1146         u8 media_type = hdev->hw.mac.media_type;
1147
1148         if (media_type == HNAE3_MEDIA_TYPE_FIBER)
1149                 hclge_parse_fiber_link_mode(hdev, speed_ability);
1150         else if (media_type == HNAE3_MEDIA_TYPE_COPPER)
1151                 hclge_parse_copper_link_mode(hdev, speed_ability);
1152         else if (media_type == HNAE3_MEDIA_TYPE_BACKPLANE)
1153                 hclge_parse_backplane_link_mode(hdev, speed_ability);
1154 }
1155
1156 static u32 hclge_get_max_speed(u16 speed_ability)
1157 {
1158         if (speed_ability & HCLGE_SUPPORT_200G_BIT)
1159                 return HCLGE_MAC_SPEED_200G;
1160
1161         if (speed_ability & HCLGE_SUPPORT_100G_BIT)
1162                 return HCLGE_MAC_SPEED_100G;
1163
1164         if (speed_ability & HCLGE_SUPPORT_50G_BIT)
1165                 return HCLGE_MAC_SPEED_50G;
1166
1167         if (speed_ability & HCLGE_SUPPORT_40G_BIT)
1168                 return HCLGE_MAC_SPEED_40G;
1169
1170         if (speed_ability & HCLGE_SUPPORT_25G_BIT)
1171                 return HCLGE_MAC_SPEED_25G;
1172
1173         if (speed_ability & HCLGE_SUPPORT_10G_BIT)
1174                 return HCLGE_MAC_SPEED_10G;
1175
1176         if (speed_ability & HCLGE_SUPPORT_1G_BIT)
1177                 return HCLGE_MAC_SPEED_1G;
1178
1179         if (speed_ability & HCLGE_SUPPORT_100M_BIT)
1180                 return HCLGE_MAC_SPEED_100M;
1181
1182         if (speed_ability & HCLGE_SUPPORT_10M_BIT)
1183                 return HCLGE_MAC_SPEED_10M;
1184
1185         return HCLGE_MAC_SPEED_1G;
1186 }
1187
1188 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
1189 {
1190 #define HCLGE_TX_SPARE_SIZE_UNIT                4096
1191 #define SPEED_ABILITY_EXT_SHIFT                 8
1192
1193         struct hclge_cfg_param_cmd *req;
1194         u64 mac_addr_tmp_high;
1195         u16 speed_ability_ext;
1196         u64 mac_addr_tmp;
1197         unsigned int i;
1198
1199         req = (struct hclge_cfg_param_cmd *)desc[0].data;
1200
1201         /* get the configuration */
1202         cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1203                                       HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
1204         cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1205                                             HCLGE_CFG_TQP_DESC_N_M,
1206                                             HCLGE_CFG_TQP_DESC_N_S);
1207
1208         cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]),
1209                                         HCLGE_CFG_PHY_ADDR_M,
1210                                         HCLGE_CFG_PHY_ADDR_S);
1211         cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]),
1212                                           HCLGE_CFG_MEDIA_TP_M,
1213                                           HCLGE_CFG_MEDIA_TP_S);
1214         cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]),
1215                                           HCLGE_CFG_RX_BUF_LEN_M,
1216                                           HCLGE_CFG_RX_BUF_LEN_S);
1217         /* get mac_address */
1218         mac_addr_tmp = __le32_to_cpu(req->param[2]);
1219         mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]),
1220                                             HCLGE_CFG_MAC_ADDR_H_M,
1221                                             HCLGE_CFG_MAC_ADDR_H_S);
1222
1223         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
1224
1225         cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]),
1226                                              HCLGE_CFG_DEFAULT_SPEED_M,
1227                                              HCLGE_CFG_DEFAULT_SPEED_S);
1228         cfg->vf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]),
1229                                                HCLGE_CFG_RSS_SIZE_M,
1230                                                HCLGE_CFG_RSS_SIZE_S);
1231
1232         for (i = 0; i < ETH_ALEN; i++)
1233                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
1234
1235         req = (struct hclge_cfg_param_cmd *)desc[1].data;
1236         cfg->numa_node_map = __le32_to_cpu(req->param[0]);
1237
1238         cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]),
1239                                              HCLGE_CFG_SPEED_ABILITY_M,
1240                                              HCLGE_CFG_SPEED_ABILITY_S);
1241         speed_ability_ext = hnae3_get_field(__le32_to_cpu(req->param[1]),
1242                                             HCLGE_CFG_SPEED_ABILITY_EXT_M,
1243                                             HCLGE_CFG_SPEED_ABILITY_EXT_S);
1244         cfg->speed_ability |= speed_ability_ext << SPEED_ABILITY_EXT_SHIFT;
1245
1246         cfg->vlan_fliter_cap = hnae3_get_field(__le32_to_cpu(req->param[1]),
1247                                                HCLGE_CFG_VLAN_FLTR_CAP_M,
1248                                                HCLGE_CFG_VLAN_FLTR_CAP_S);
1249
1250         cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]),
1251                                          HCLGE_CFG_UMV_TBL_SPACE_M,
1252                                          HCLGE_CFG_UMV_TBL_SPACE_S);
1253
1254         cfg->pf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[2]),
1255                                                HCLGE_CFG_PF_RSS_SIZE_M,
1256                                                HCLGE_CFG_PF_RSS_SIZE_S);
1257
1258         /* HCLGE_CFG_PF_RSS_SIZE_M is the PF max rss size, which is a
1259          * power of 2, instead of reading out directly. This would
1260          * be more flexible for future changes and expansions.
1261          * When VF max  rss size field is HCLGE_CFG_RSS_SIZE_S,
1262          * it does not make sense if PF's field is 0. In this case, PF and VF
1263          * has the same max rss size filed: HCLGE_CFG_RSS_SIZE_S.
1264          */
1265         cfg->pf_rss_size_max = cfg->pf_rss_size_max ?
1266                                1U << cfg->pf_rss_size_max :
1267                                cfg->vf_rss_size_max;
1268
1269         /* The unit of the tx spare buffer size queried from configuration
1270          * file is HCLGE_TX_SPARE_SIZE_UNIT(4096) bytes, so a conversion is
1271          * needed here.
1272          */
1273         cfg->tx_spare_buf_size = hnae3_get_field(__le32_to_cpu(req->param[2]),
1274                                                  HCLGE_CFG_TX_SPARE_BUF_SIZE_M,
1275                                                  HCLGE_CFG_TX_SPARE_BUF_SIZE_S);
1276         cfg->tx_spare_buf_size *= HCLGE_TX_SPARE_SIZE_UNIT;
1277 }
1278
1279 /* hclge_get_cfg: query the static parameter from flash
1280  * @hdev: pointer to struct hclge_dev
1281  * @hcfg: the config structure to be getted
1282  */
1283 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
1284 {
1285         struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
1286         struct hclge_cfg_param_cmd *req;
1287         unsigned int i;
1288         int ret;
1289
1290         for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
1291                 u32 offset = 0;
1292
1293                 req = (struct hclge_cfg_param_cmd *)desc[i].data;
1294                 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
1295                                            true);
1296                 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M,
1297                                 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
1298                 /* Len should be united by 4 bytes when send to hardware */
1299                 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
1300                                 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
1301                 req->offset = cpu_to_le32(offset);
1302         }
1303
1304         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1305         if (ret) {
1306                 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret);
1307                 return ret;
1308         }
1309
1310         hclge_parse_cfg(hcfg, desc);
1311
1312         return 0;
1313 }
1314
1315 static void hclge_set_default_dev_specs(struct hclge_dev *hdev)
1316 {
1317 #define HCLGE_MAX_NON_TSO_BD_NUM                        8U
1318
1319         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
1320
1321         ae_dev->dev_specs.max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM;
1322         ae_dev->dev_specs.rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE;
1323         ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE;
1324         ae_dev->dev_specs.max_tm_rate = HCLGE_ETHER_MAX_RATE;
1325         ae_dev->dev_specs.max_int_gl = HCLGE_DEF_MAX_INT_GL;
1326         ae_dev->dev_specs.max_frm_size = HCLGE_MAC_MAX_FRAME;
1327         ae_dev->dev_specs.max_qset_num = HCLGE_MAX_QSET_NUM;
1328         ae_dev->dev_specs.umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF;
1329         ae_dev->dev_specs.tnl_num = 0;
1330 }
1331
1332 static void hclge_parse_dev_specs(struct hclge_dev *hdev,
1333                                   struct hclge_desc *desc)
1334 {
1335         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
1336         struct hclge_dev_specs_0_cmd *req0;
1337         struct hclge_dev_specs_1_cmd *req1;
1338
1339         req0 = (struct hclge_dev_specs_0_cmd *)desc[0].data;
1340         req1 = (struct hclge_dev_specs_1_cmd *)desc[1].data;
1341
1342         ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num;
1343         ae_dev->dev_specs.rss_ind_tbl_size =
1344                 le16_to_cpu(req0->rss_ind_tbl_size);
1345         ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max);
1346         ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size);
1347         ae_dev->dev_specs.max_tm_rate = le32_to_cpu(req0->max_tm_rate);
1348         ae_dev->dev_specs.max_qset_num = le16_to_cpu(req1->max_qset_num);
1349         ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl);
1350         ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size);
1351         ae_dev->dev_specs.umv_size = le16_to_cpu(req1->umv_size);
1352         ae_dev->dev_specs.mc_mac_size = le16_to_cpu(req1->mc_mac_size);
1353         ae_dev->dev_specs.tnl_num = req1->tnl_num;
1354 }
1355
1356 static void hclge_check_dev_specs(struct hclge_dev *hdev)
1357 {
1358         struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs;
1359
1360         if (!dev_specs->max_non_tso_bd_num)
1361                 dev_specs->max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM;
1362         if (!dev_specs->rss_ind_tbl_size)
1363                 dev_specs->rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE;
1364         if (!dev_specs->rss_key_size)
1365                 dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE;
1366         if (!dev_specs->max_tm_rate)
1367                 dev_specs->max_tm_rate = HCLGE_ETHER_MAX_RATE;
1368         if (!dev_specs->max_qset_num)
1369                 dev_specs->max_qset_num = HCLGE_MAX_QSET_NUM;
1370         if (!dev_specs->max_int_gl)
1371                 dev_specs->max_int_gl = HCLGE_DEF_MAX_INT_GL;
1372         if (!dev_specs->max_frm_size)
1373                 dev_specs->max_frm_size = HCLGE_MAC_MAX_FRAME;
1374         if (!dev_specs->umv_size)
1375                 dev_specs->umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF;
1376 }
1377
1378 static int hclge_query_mac_stats_num(struct hclge_dev *hdev)
1379 {
1380         u32 reg_num = 0;
1381         int ret;
1382
1383         ret = hclge_mac_query_reg_num(hdev, &reg_num);
1384         if (ret && ret != -EOPNOTSUPP)
1385                 return ret;
1386
1387         hdev->ae_dev->dev_specs.mac_stats_num = reg_num;
1388         return 0;
1389 }
1390
1391 static int hclge_query_dev_specs(struct hclge_dev *hdev)
1392 {
1393         struct hclge_desc desc[HCLGE_QUERY_DEV_SPECS_BD_NUM];
1394         int ret;
1395         int i;
1396
1397         ret = hclge_query_mac_stats_num(hdev);
1398         if (ret)
1399                 return ret;
1400
1401         /* set default specifications as devices lower than version V3 do not
1402          * support querying specifications from firmware.
1403          */
1404         if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) {
1405                 hclge_set_default_dev_specs(hdev);
1406                 return 0;
1407         }
1408
1409         for (i = 0; i < HCLGE_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1410                 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS,
1411                                            true);
1412                 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
1413         }
1414         hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true);
1415
1416         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_QUERY_DEV_SPECS_BD_NUM);
1417         if (ret)
1418                 return ret;
1419
1420         hclge_parse_dev_specs(hdev, desc);
1421         hclge_check_dev_specs(hdev);
1422
1423         return 0;
1424 }
1425
1426 static int hclge_get_cap(struct hclge_dev *hdev)
1427 {
1428         int ret;
1429
1430         ret = hclge_query_function_status(hdev);
1431         if (ret) {
1432                 dev_err(&hdev->pdev->dev,
1433                         "query function status error %d.\n", ret);
1434                 return ret;
1435         }
1436
1437         /* get pf resource */
1438         return hclge_query_pf_resource(hdev);
1439 }
1440
1441 static void hclge_init_kdump_kernel_config(struct hclge_dev *hdev)
1442 {
1443 #define HCLGE_MIN_TX_DESC       64
1444 #define HCLGE_MIN_RX_DESC       64
1445
1446         if (!is_kdump_kernel())
1447                 return;
1448
1449         dev_info(&hdev->pdev->dev,
1450                  "Running kdump kernel. Using minimal resources\n");
1451
1452         /* minimal queue pairs equals to the number of vports */
1453         hdev->num_tqps = hdev->num_req_vfs + 1;
1454         hdev->num_tx_desc = HCLGE_MIN_TX_DESC;
1455         hdev->num_rx_desc = HCLGE_MIN_RX_DESC;
1456 }
1457
1458 static void hclge_init_tc_config(struct hclge_dev *hdev)
1459 {
1460         unsigned int i;
1461
1462         if (hdev->tc_max > HNAE3_MAX_TC ||
1463             hdev->tc_max < 1) {
1464                 dev_warn(&hdev->pdev->dev, "TC num = %u.\n",
1465                          hdev->tc_max);
1466                 hdev->tc_max = 1;
1467         }
1468
1469         /* Dev does not support DCB */
1470         if (!hnae3_dev_dcb_supported(hdev)) {
1471                 hdev->tc_max = 1;
1472                 hdev->pfc_max = 0;
1473         } else {
1474                 hdev->pfc_max = hdev->tc_max;
1475         }
1476
1477         hdev->tm_info.num_tc = 1;
1478
1479         /* Currently not support uncontiuous tc */
1480         for (i = 0; i < hdev->tm_info.num_tc; i++)
1481                 hnae3_set_bit(hdev->hw_tc_map, i, 1);
1482
1483         hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
1484 }
1485
1486 static int hclge_configure(struct hclge_dev *hdev)
1487 {
1488         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
1489         struct hclge_cfg cfg;
1490         int ret;
1491
1492         ret = hclge_get_cfg(hdev, &cfg);
1493         if (ret)
1494                 return ret;
1495
1496         hdev->base_tqp_pid = 0;
1497         hdev->vf_rss_size_max = cfg.vf_rss_size_max;
1498         hdev->pf_rss_size_max = cfg.pf_rss_size_max;
1499         hdev->rx_buf_len = cfg.rx_buf_len;
1500         ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
1501         hdev->hw.mac.media_type = cfg.media_type;
1502         hdev->hw.mac.phy_addr = cfg.phy_addr;
1503         hdev->num_tx_desc = cfg.tqp_desc_num;
1504         hdev->num_rx_desc = cfg.tqp_desc_num;
1505         hdev->tm_info.num_pg = 1;
1506         hdev->tc_max = cfg.tc_num;
1507         hdev->tm_info.hw_pfc_map = 0;
1508         if (cfg.umv_space)
1509                 hdev->wanted_umv_size = cfg.umv_space;
1510         else
1511                 hdev->wanted_umv_size = hdev->ae_dev->dev_specs.umv_size;
1512         hdev->tx_spare_buf_size = cfg.tx_spare_buf_size;
1513         hdev->gro_en = true;
1514         if (cfg.vlan_fliter_cap == HCLGE_VLAN_FLTR_CAN_MDF)
1515                 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps);
1516
1517         if (hnae3_ae_dev_fd_supported(hdev->ae_dev)) {
1518                 hdev->fd_en = true;
1519                 hdev->fd_active_type = HCLGE_FD_RULE_NONE;
1520         }
1521
1522         ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1523         if (ret) {
1524                 dev_err(&hdev->pdev->dev, "failed to parse speed %u, ret = %d\n",
1525                         cfg.default_speed, ret);
1526                 return ret;
1527         }
1528
1529         hclge_parse_link_mode(hdev, cfg.speed_ability);
1530
1531         hdev->hw.mac.max_speed = hclge_get_max_speed(cfg.speed_ability);
1532
1533         hclge_init_tc_config(hdev);
1534         hclge_init_kdump_kernel_config(hdev);
1535
1536         return ret;
1537 }
1538
1539 static int hclge_config_tso(struct hclge_dev *hdev, u16 tso_mss_min,
1540                             u16 tso_mss_max)
1541 {
1542         struct hclge_cfg_tso_status_cmd *req;
1543         struct hclge_desc desc;
1544
1545         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1546
1547         req = (struct hclge_cfg_tso_status_cmd *)desc.data;
1548         req->tso_mss_min = cpu_to_le16(tso_mss_min);
1549         req->tso_mss_max = cpu_to_le16(tso_mss_max);
1550
1551         return hclge_cmd_send(&hdev->hw, &desc, 1);
1552 }
1553
1554 static int hclge_config_gro(struct hclge_dev *hdev)
1555 {
1556         struct hclge_cfg_gro_status_cmd *req;
1557         struct hclge_desc desc;
1558         int ret;
1559
1560         if (!hnae3_ae_dev_gro_supported(hdev->ae_dev))
1561                 return 0;
1562
1563         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, false);
1564         req = (struct hclge_cfg_gro_status_cmd *)desc.data;
1565
1566         req->gro_en = hdev->gro_en ? 1 : 0;
1567
1568         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1569         if (ret)
1570                 dev_err(&hdev->pdev->dev,
1571                         "GRO hardware config cmd failed, ret = %d\n", ret);
1572
1573         return ret;
1574 }
1575
1576 static int hclge_alloc_tqps(struct hclge_dev *hdev)
1577 {
1578         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
1579         struct hclge_comm_tqp *tqp;
1580         int i;
1581
1582         hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1583                                   sizeof(struct hclge_comm_tqp), GFP_KERNEL);
1584         if (!hdev->htqp)
1585                 return -ENOMEM;
1586
1587         tqp = hdev->htqp;
1588
1589         for (i = 0; i < hdev->num_tqps; i++) {
1590                 tqp->dev = &hdev->pdev->dev;
1591                 tqp->index = i;
1592
1593                 tqp->q.ae_algo = &ae_algo;
1594                 tqp->q.buf_size = hdev->rx_buf_len;
1595                 tqp->q.tx_desc_num = hdev->num_tx_desc;
1596                 tqp->q.rx_desc_num = hdev->num_rx_desc;
1597
1598                 /* need an extended offset to configure queues >=
1599                  * HCLGE_TQP_MAX_SIZE_DEV_V2
1600                  */
1601                 if (i < HCLGE_TQP_MAX_SIZE_DEV_V2)
1602                         tqp->q.io_base = hdev->hw.hw.io_base +
1603                                          HCLGE_TQP_REG_OFFSET +
1604                                          i * HCLGE_TQP_REG_SIZE;
1605                 else
1606                         tqp->q.io_base = hdev->hw.hw.io_base +
1607                                          HCLGE_TQP_REG_OFFSET +
1608                                          HCLGE_TQP_EXT_REG_OFFSET +
1609                                          (i - HCLGE_TQP_MAX_SIZE_DEV_V2) *
1610                                          HCLGE_TQP_REG_SIZE;
1611
1612                 /* when device supports tx push and has device memory,
1613                  * the queue can execute push mode or doorbell mode on
1614                  * device memory.
1615                  */
1616                 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps))
1617                         tqp->q.mem_base = hdev->hw.hw.mem_base +
1618                                           HCLGE_TQP_MEM_OFFSET(hdev, i);
1619
1620                 tqp++;
1621         }
1622
1623         return 0;
1624 }
1625
1626 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1627                                   u16 tqp_pid, u16 tqp_vid, bool is_pf)
1628 {
1629         struct hclge_tqp_map_cmd *req;
1630         struct hclge_desc desc;
1631         int ret;
1632
1633         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1634
1635         req = (struct hclge_tqp_map_cmd *)desc.data;
1636         req->tqp_id = cpu_to_le16(tqp_pid);
1637         req->tqp_vf = func_id;
1638         req->tqp_flag = 1U << HCLGE_TQP_MAP_EN_B;
1639         if (!is_pf)
1640                 req->tqp_flag |= 1U << HCLGE_TQP_MAP_TYPE_B;
1641         req->tqp_vid = cpu_to_le16(tqp_vid);
1642
1643         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1644         if (ret)
1645                 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret);
1646
1647         return ret;
1648 }
1649
1650 static int  hclge_assign_tqp(struct hclge_vport *vport, u16 num_tqps)
1651 {
1652         struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
1653         struct hclge_dev *hdev = vport->back;
1654         int i, alloced;
1655
1656         for (i = 0, alloced = 0; i < hdev->num_tqps &&
1657              alloced < num_tqps; i++) {
1658                 if (!hdev->htqp[i].alloced) {
1659                         hdev->htqp[i].q.handle = &vport->nic;
1660                         hdev->htqp[i].q.tqp_index = alloced;
1661                         hdev->htqp[i].q.tx_desc_num = kinfo->num_tx_desc;
1662                         hdev->htqp[i].q.rx_desc_num = kinfo->num_rx_desc;
1663                         kinfo->tqp[alloced] = &hdev->htqp[i].q;
1664                         hdev->htqp[i].alloced = true;
1665                         alloced++;
1666                 }
1667         }
1668         vport->alloc_tqps = alloced;
1669         kinfo->rss_size = min_t(u16, hdev->pf_rss_size_max,
1670                                 vport->alloc_tqps / hdev->tm_info.num_tc);
1671
1672         /* ensure one to one mapping between irq and queue at default */
1673         kinfo->rss_size = min_t(u16, kinfo->rss_size,
1674                                 (hdev->num_nic_msi - 1) / hdev->tm_info.num_tc);
1675
1676         return 0;
1677 }
1678
1679 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps,
1680                             u16 num_tx_desc, u16 num_rx_desc)
1681
1682 {
1683         struct hnae3_handle *nic = &vport->nic;
1684         struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1685         struct hclge_dev *hdev = vport->back;
1686         int ret;
1687
1688         kinfo->num_tx_desc = num_tx_desc;
1689         kinfo->num_rx_desc = num_rx_desc;
1690
1691         kinfo->rx_buf_len = hdev->rx_buf_len;
1692         kinfo->tx_spare_buf_size = hdev->tx_spare_buf_size;
1693
1694         kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, num_tqps,
1695                                   sizeof(struct hnae3_queue *), GFP_KERNEL);
1696         if (!kinfo->tqp)
1697                 return -ENOMEM;
1698
1699         ret = hclge_assign_tqp(vport, num_tqps);
1700         if (ret)
1701                 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1702
1703         return ret;
1704 }
1705
1706 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1707                                   struct hclge_vport *vport)
1708 {
1709         struct hnae3_handle *nic = &vport->nic;
1710         struct hnae3_knic_private_info *kinfo;
1711         u16 i;
1712
1713         kinfo = &nic->kinfo;
1714         for (i = 0; i < vport->alloc_tqps; i++) {
1715                 struct hclge_comm_tqp *q =
1716                         container_of(kinfo->tqp[i], struct hclge_comm_tqp, q);
1717                 bool is_pf;
1718                 int ret;
1719
1720                 is_pf = !(vport->vport_id);
1721                 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1722                                              i, is_pf);
1723                 if (ret)
1724                         return ret;
1725         }
1726
1727         return 0;
1728 }
1729
1730 static int hclge_map_tqp(struct hclge_dev *hdev)
1731 {
1732         struct hclge_vport *vport = hdev->vport;
1733         u16 i, num_vport;
1734
1735         num_vport = hdev->num_req_vfs + 1;
1736         for (i = 0; i < num_vport; i++) {
1737                 int ret;
1738
1739                 ret = hclge_map_tqp_to_vport(hdev, vport);
1740                 if (ret)
1741                         return ret;
1742
1743                 vport++;
1744         }
1745
1746         return 0;
1747 }
1748
1749 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1750 {
1751         struct hnae3_handle *nic = &vport->nic;
1752         struct hclge_dev *hdev = vport->back;
1753         int ret;
1754
1755         nic->pdev = hdev->pdev;
1756         nic->ae_algo = &ae_algo;
1757         nic->numa_node_mask = hdev->numa_node_mask;
1758         nic->kinfo.io_base = hdev->hw.hw.io_base;
1759
1760         ret = hclge_knic_setup(vport, num_tqps,
1761                                hdev->num_tx_desc, hdev->num_rx_desc);
1762         if (ret)
1763                 dev_err(&hdev->pdev->dev, "knic setup failed %d\n", ret);
1764
1765         return ret;
1766 }
1767
1768 static int hclge_alloc_vport(struct hclge_dev *hdev)
1769 {
1770         struct pci_dev *pdev = hdev->pdev;
1771         struct hclge_vport *vport;
1772         u32 tqp_main_vport;
1773         u32 tqp_per_vport;
1774         int num_vport, i;
1775         int ret;
1776
1777         /* We need to alloc a vport for main NIC of PF */
1778         num_vport = hdev->num_req_vfs + 1;
1779
1780         if (hdev->num_tqps < num_vport) {
1781                 dev_err(&hdev->pdev->dev, "tqps(%u) is less than vports(%d)",
1782                         hdev->num_tqps, num_vport);
1783                 return -EINVAL;
1784         }
1785
1786         /* Alloc the same number of TQPs for every vport */
1787         tqp_per_vport = hdev->num_tqps / num_vport;
1788         tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1789
1790         vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1791                              GFP_KERNEL);
1792         if (!vport)
1793                 return -ENOMEM;
1794
1795         hdev->vport = vport;
1796         hdev->num_alloc_vport = num_vport;
1797
1798         if (IS_ENABLED(CONFIG_PCI_IOV))
1799                 hdev->num_alloc_vfs = hdev->num_req_vfs;
1800
1801         for (i = 0; i < num_vport; i++) {
1802                 vport->back = hdev;
1803                 vport->vport_id = i;
1804                 vport->vf_info.link_state = IFLA_VF_LINK_STATE_AUTO;
1805                 vport->mps = HCLGE_MAC_DEFAULT_FRAME;
1806                 vport->port_base_vlan_cfg.state = HNAE3_PORT_BASE_VLAN_DISABLE;
1807                 vport->port_base_vlan_cfg.tbl_sta = true;
1808                 vport->rxvlan_cfg.rx_vlan_offload_en = true;
1809                 vport->req_vlan_fltr_en = true;
1810                 INIT_LIST_HEAD(&vport->vlan_list);
1811                 INIT_LIST_HEAD(&vport->uc_mac_list);
1812                 INIT_LIST_HEAD(&vport->mc_mac_list);
1813                 spin_lock_init(&vport->mac_list_lock);
1814
1815                 if (i == 0)
1816                         ret = hclge_vport_setup(vport, tqp_main_vport);
1817                 else
1818                         ret = hclge_vport_setup(vport, tqp_per_vport);
1819                 if (ret) {
1820                         dev_err(&pdev->dev,
1821                                 "vport setup failed for vport %d, %d\n",
1822                                 i, ret);
1823                         return ret;
1824                 }
1825
1826                 vport++;
1827         }
1828
1829         return 0;
1830 }
1831
1832 static int  hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1833                                     struct hclge_pkt_buf_alloc *buf_alloc)
1834 {
1835 /* TX buffer size is unit by 128 byte */
1836 #define HCLGE_BUF_SIZE_UNIT_SHIFT       7
1837 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK    BIT(15)
1838         struct hclge_tx_buff_alloc_cmd *req;
1839         struct hclge_desc desc;
1840         int ret;
1841         u8 i;
1842
1843         req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
1844
1845         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
1846         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1847                 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
1848
1849                 req->tx_pkt_buff[i] =
1850                         cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1851                                      HCLGE_BUF_SIZE_UPDATE_EN_MSK);
1852         }
1853
1854         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1855         if (ret)
1856                 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1857                         ret);
1858
1859         return ret;
1860 }
1861
1862 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1863                                  struct hclge_pkt_buf_alloc *buf_alloc)
1864 {
1865         int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
1866
1867         if (ret)
1868                 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret);
1869
1870         return ret;
1871 }
1872
1873 static u32 hclge_get_tc_num(struct hclge_dev *hdev)
1874 {
1875         unsigned int i;
1876         u32 cnt = 0;
1877
1878         for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1879                 if (hdev->hw_tc_map & BIT(i))
1880                         cnt++;
1881         return cnt;
1882 }
1883
1884 /* Get the number of pfc enabled TCs, which have private buffer */
1885 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1886                                   struct hclge_pkt_buf_alloc *buf_alloc)
1887 {
1888         struct hclge_priv_buf *priv;
1889         unsigned int i;
1890         int cnt = 0;
1891
1892         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1893                 priv = &buf_alloc->priv_buf[i];
1894                 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1895                     priv->enable)
1896                         cnt++;
1897         }
1898
1899         return cnt;
1900 }
1901
1902 /* Get the number of pfc disabled TCs, which have private buffer */
1903 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1904                                      struct hclge_pkt_buf_alloc *buf_alloc)
1905 {
1906         struct hclge_priv_buf *priv;
1907         unsigned int i;
1908         int cnt = 0;
1909
1910         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1911                 priv = &buf_alloc->priv_buf[i];
1912                 if (hdev->hw_tc_map & BIT(i) &&
1913                     !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1914                     priv->enable)
1915                         cnt++;
1916         }
1917
1918         return cnt;
1919 }
1920
1921 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1922 {
1923         struct hclge_priv_buf *priv;
1924         u32 rx_priv = 0;
1925         int i;
1926
1927         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1928                 priv = &buf_alloc->priv_buf[i];
1929                 if (priv->enable)
1930                         rx_priv += priv->buf_size;
1931         }
1932         return rx_priv;
1933 }
1934
1935 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1936 {
1937         u32 i, total_tx_size = 0;
1938
1939         for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1940                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
1941
1942         return total_tx_size;
1943 }
1944
1945 static bool  hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1946                                 struct hclge_pkt_buf_alloc *buf_alloc,
1947                                 u32 rx_all)
1948 {
1949         u32 shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
1950         u32 tc_num = hclge_get_tc_num(hdev);
1951         u32 shared_buf, aligned_mps;
1952         u32 rx_priv;
1953         int i;
1954
1955         aligned_mps = roundup(hdev->mps, HCLGE_BUF_SIZE_UNIT);
1956
1957         if (hnae3_dev_dcb_supported(hdev))
1958                 shared_buf_min = HCLGE_BUF_MUL_BY * aligned_mps +
1959                                         hdev->dv_buf_size;
1960         else
1961                 shared_buf_min = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF
1962                                         + hdev->dv_buf_size;
1963
1964         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
1965         shared_std = roundup(max_t(u32, shared_buf_min, shared_buf_tc),
1966                              HCLGE_BUF_SIZE_UNIT);
1967
1968         rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
1969         if (rx_all < rx_priv + shared_std)
1970                 return false;
1971
1972         shared_buf = rounddown(rx_all - rx_priv, HCLGE_BUF_SIZE_UNIT);
1973         buf_alloc->s_buf.buf_size = shared_buf;
1974         if (hnae3_dev_dcb_supported(hdev)) {
1975                 buf_alloc->s_buf.self.high = shared_buf - hdev->dv_buf_size;
1976                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
1977                         - roundup(aligned_mps / HCLGE_BUF_DIV_BY,
1978                                   HCLGE_BUF_SIZE_UNIT);
1979         } else {
1980                 buf_alloc->s_buf.self.high = aligned_mps +
1981                                                 HCLGE_NON_DCB_ADDITIONAL_BUF;
1982                 buf_alloc->s_buf.self.low = aligned_mps;
1983         }
1984
1985         if (hnae3_dev_dcb_supported(hdev)) {
1986                 hi_thrd = shared_buf - hdev->dv_buf_size;
1987
1988                 if (tc_num <= NEED_RESERVE_TC_NUM)
1989                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
1990                                         / BUF_MAX_PERCENT;
1991
1992                 if (tc_num)
1993                         hi_thrd = hi_thrd / tc_num;
1994
1995                 hi_thrd = max_t(u32, hi_thrd, HCLGE_BUF_MUL_BY * aligned_mps);
1996                 hi_thrd = rounddown(hi_thrd, HCLGE_BUF_SIZE_UNIT);
1997                 lo_thrd = hi_thrd - aligned_mps / HCLGE_BUF_DIV_BY;
1998         } else {
1999                 hi_thrd = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF;
2000                 lo_thrd = aligned_mps;
2001         }
2002
2003         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2004                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
2005                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
2006         }
2007
2008         return true;
2009 }
2010
2011 static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
2012                                 struct hclge_pkt_buf_alloc *buf_alloc)
2013 {
2014         u32 i, total_size;
2015
2016         total_size = hdev->pkt_buf_size;
2017
2018         /* alloc tx buffer for all enabled tc */
2019         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2020                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
2021
2022                 if (hdev->hw_tc_map & BIT(i)) {
2023                         if (total_size < hdev->tx_buf_size)
2024                                 return -ENOMEM;
2025
2026                         priv->tx_buf_size = hdev->tx_buf_size;
2027                 } else {
2028                         priv->tx_buf_size = 0;
2029                 }
2030
2031                 total_size -= priv->tx_buf_size;
2032         }
2033
2034         return 0;
2035 }
2036
2037 static bool hclge_rx_buf_calc_all(struct hclge_dev *hdev, bool max,
2038                                   struct hclge_pkt_buf_alloc *buf_alloc)
2039 {
2040         u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc);
2041         u32 aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT);
2042         unsigned int i;
2043
2044         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2045                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
2046
2047                 priv->enable = 0;
2048                 priv->wl.low = 0;
2049                 priv->wl.high = 0;
2050                 priv->buf_size = 0;
2051
2052                 if (!(hdev->hw_tc_map & BIT(i)))
2053                         continue;
2054
2055                 priv->enable = 1;
2056
2057                 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
2058                         priv->wl.low = max ? aligned_mps : HCLGE_BUF_SIZE_UNIT;
2059                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
2060                                                 HCLGE_BUF_SIZE_UNIT);
2061                 } else {
2062                         priv->wl.low = 0;
2063                         priv->wl.high = max ? (aligned_mps * HCLGE_BUF_MUL_BY) :
2064                                         aligned_mps;
2065                 }
2066
2067                 priv->buf_size = priv->wl.high + hdev->dv_buf_size;
2068         }
2069
2070         return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all);
2071 }
2072
2073 static bool hclge_drop_nopfc_buf_till_fit(struct hclge_dev *hdev,
2074                                           struct hclge_pkt_buf_alloc *buf_alloc)
2075 {
2076         u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc);
2077         int no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
2078         int i;
2079
2080         /* let the last to be cleared first */
2081         for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
2082                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
2083                 unsigned int mask = BIT((unsigned int)i);
2084
2085                 if (hdev->hw_tc_map & mask &&
2086                     !(hdev->tm_info.hw_pfc_map & mask)) {
2087                         /* Clear the no pfc TC private buffer */
2088                         priv->wl.low = 0;
2089                         priv->wl.high = 0;
2090                         priv->buf_size = 0;
2091                         priv->enable = 0;
2092                         no_pfc_priv_num--;
2093                 }
2094
2095                 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
2096                     no_pfc_priv_num == 0)
2097                         break;
2098         }
2099
2100         return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all);
2101 }
2102
2103 static bool hclge_drop_pfc_buf_till_fit(struct hclge_dev *hdev,
2104                                         struct hclge_pkt_buf_alloc *buf_alloc)
2105 {
2106         u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc);
2107         int pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
2108         int i;
2109
2110         /* let the last to be cleared first */
2111         for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
2112                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
2113                 unsigned int mask = BIT((unsigned int)i);
2114
2115                 if (hdev->hw_tc_map & mask &&
2116                     hdev->tm_info.hw_pfc_map & mask) {
2117                         /* Reduce the number of pfc TC with private buffer */
2118                         priv->wl.low = 0;
2119                         priv->enable = 0;
2120                         priv->wl.high = 0;
2121                         priv->buf_size = 0;
2122                         pfc_priv_num--;
2123                 }
2124
2125                 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
2126                     pfc_priv_num == 0)
2127                         break;
2128         }
2129
2130         return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all);
2131 }
2132
2133 static int hclge_only_alloc_priv_buff(struct hclge_dev *hdev,
2134                                       struct hclge_pkt_buf_alloc *buf_alloc)
2135 {
2136 #define COMPENSATE_BUFFER       0x3C00
2137 #define COMPENSATE_HALF_MPS_NUM 5
2138 #define PRIV_WL_GAP             0x1800
2139
2140         u32 rx_priv = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc);
2141         u32 tc_num = hclge_get_tc_num(hdev);
2142         u32 half_mps = hdev->mps >> 1;
2143         u32 min_rx_priv;
2144         unsigned int i;
2145
2146         if (tc_num)
2147                 rx_priv = rx_priv / tc_num;
2148
2149         if (tc_num <= NEED_RESERVE_TC_NUM)
2150                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
2151
2152         min_rx_priv = hdev->dv_buf_size + COMPENSATE_BUFFER +
2153                         COMPENSATE_HALF_MPS_NUM * half_mps;
2154         min_rx_priv = round_up(min_rx_priv, HCLGE_BUF_SIZE_UNIT);
2155         rx_priv = round_down(rx_priv, HCLGE_BUF_SIZE_UNIT);
2156         if (rx_priv < min_rx_priv)
2157                 return false;
2158
2159         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2160                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
2161
2162                 priv->enable = 0;
2163                 priv->wl.low = 0;
2164                 priv->wl.high = 0;
2165                 priv->buf_size = 0;
2166
2167                 if (!(hdev->hw_tc_map & BIT(i)))
2168                         continue;
2169
2170                 priv->enable = 1;
2171                 priv->buf_size = rx_priv;
2172                 priv->wl.high = rx_priv - hdev->dv_buf_size;
2173                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
2174         }
2175
2176         buf_alloc->s_buf.buf_size = 0;
2177
2178         return true;
2179 }
2180
2181 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
2182  * @hdev: pointer to struct hclge_dev
2183  * @buf_alloc: pointer to buffer calculation data
2184  * @return: 0: calculate successful, negative: fail
2185  */
2186 static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
2187                                 struct hclge_pkt_buf_alloc *buf_alloc)
2188 {
2189         /* When DCB is not supported, rx private buffer is not allocated. */
2190         if (!hnae3_dev_dcb_supported(hdev)) {
2191                 u32 rx_all = hdev->pkt_buf_size;
2192
2193                 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
2194                 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
2195                         return -ENOMEM;
2196
2197                 return 0;
2198         }
2199
2200         if (hclge_only_alloc_priv_buff(hdev, buf_alloc))
2201                 return 0;
2202
2203         if (hclge_rx_buf_calc_all(hdev, true, buf_alloc))
2204                 return 0;
2205
2206         /* try to decrease the buffer size */
2207         if (hclge_rx_buf_calc_all(hdev, false, buf_alloc))
2208                 return 0;
2209
2210         if (hclge_drop_nopfc_buf_till_fit(hdev, buf_alloc))
2211                 return 0;
2212
2213         if (hclge_drop_pfc_buf_till_fit(hdev, buf_alloc))
2214                 return 0;
2215
2216         return -ENOMEM;
2217 }
2218
2219 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
2220                                    struct hclge_pkt_buf_alloc *buf_alloc)
2221 {
2222         struct hclge_rx_priv_buff_cmd *req;
2223         struct hclge_desc desc;
2224         int ret;
2225         int i;
2226
2227         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
2228         req = (struct hclge_rx_priv_buff_cmd *)desc.data;
2229
2230         /* Alloc private buffer TCs */
2231         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2232                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
2233
2234                 req->buf_num[i] =
2235                         cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
2236                 req->buf_num[i] |=
2237                         cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
2238         }
2239
2240         req->shared_buf =
2241                 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
2242                             (1 << HCLGE_TC0_PRI_BUF_EN_B));
2243
2244         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2245         if (ret)
2246                 dev_err(&hdev->pdev->dev,
2247                         "rx private buffer alloc cmd failed %d\n", ret);
2248
2249         return ret;
2250 }
2251
2252 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
2253                                    struct hclge_pkt_buf_alloc *buf_alloc)
2254 {
2255         struct hclge_rx_priv_wl_buf *req;
2256         struct hclge_priv_buf *priv;
2257         struct hclge_desc desc[2];
2258         int i, j;
2259         int ret;
2260
2261         for (i = 0; i < 2; i++) {
2262                 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
2263                                            false);
2264                 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
2265
2266                 /* The first descriptor set the NEXT bit to 1 */
2267                 if (i == 0)
2268                         desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2269                 else
2270                         desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2271
2272                 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
2273                         u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
2274
2275                         priv = &buf_alloc->priv_buf[idx];
2276                         req->tc_wl[j].high =
2277                                 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
2278                         req->tc_wl[j].high |=
2279                                 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
2280                         req->tc_wl[j].low =
2281                                 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
2282                         req->tc_wl[j].low |=
2283                                  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
2284                 }
2285         }
2286
2287         /* Send 2 descriptor at one time */
2288         ret = hclge_cmd_send(&hdev->hw, desc, 2);
2289         if (ret)
2290                 dev_err(&hdev->pdev->dev,
2291                         "rx private waterline config cmd failed %d\n",
2292                         ret);
2293         return ret;
2294 }
2295
2296 static int hclge_common_thrd_config(struct hclge_dev *hdev,
2297                                     struct hclge_pkt_buf_alloc *buf_alloc)
2298 {
2299         struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
2300         struct hclge_rx_com_thrd *req;
2301         struct hclge_desc desc[2];
2302         struct hclge_tc_thrd *tc;
2303         int i, j;
2304         int ret;
2305
2306         for (i = 0; i < 2; i++) {
2307                 hclge_cmd_setup_basic_desc(&desc[i],
2308                                            HCLGE_OPC_RX_COM_THRD_ALLOC, false);
2309                 req = (struct hclge_rx_com_thrd *)&desc[i].data;
2310
2311                 /* The first descriptor set the NEXT bit to 1 */
2312                 if (i == 0)
2313                         desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2314                 else
2315                         desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2316
2317                 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
2318                         tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
2319
2320                         req->com_thrd[j].high =
2321                                 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
2322                         req->com_thrd[j].high |=
2323                                  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
2324                         req->com_thrd[j].low =
2325                                 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
2326                         req->com_thrd[j].low |=
2327                                  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
2328                 }
2329         }
2330
2331         /* Send 2 descriptors at one time */
2332         ret = hclge_cmd_send(&hdev->hw, desc, 2);
2333         if (ret)
2334                 dev_err(&hdev->pdev->dev,
2335                         "common threshold config cmd failed %d\n", ret);
2336         return ret;
2337 }
2338
2339 static int hclge_common_wl_config(struct hclge_dev *hdev,
2340                                   struct hclge_pkt_buf_alloc *buf_alloc)
2341 {
2342         struct hclge_shared_buf *buf = &buf_alloc->s_buf;
2343         struct hclge_rx_com_wl *req;
2344         struct hclge_desc desc;
2345         int ret;
2346
2347         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
2348
2349         req = (struct hclge_rx_com_wl *)desc.data;
2350         req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
2351         req->com_wl.high |=  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
2352
2353         req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
2354         req->com_wl.low |=  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
2355
2356         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2357         if (ret)
2358                 dev_err(&hdev->pdev->dev,
2359                         "common waterline config cmd failed %d\n", ret);
2360
2361         return ret;
2362 }
2363
2364 int hclge_buffer_alloc(struct hclge_dev *hdev)
2365 {
2366         struct hclge_pkt_buf_alloc *pkt_buf;
2367         int ret;
2368
2369         pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
2370         if (!pkt_buf)
2371                 return -ENOMEM;
2372
2373         ret = hclge_tx_buffer_calc(hdev, pkt_buf);
2374         if (ret) {
2375                 dev_err(&hdev->pdev->dev,
2376                         "could not calc tx buffer size for all TCs %d\n", ret);
2377                 goto out;
2378         }
2379
2380         ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
2381         if (ret) {
2382                 dev_err(&hdev->pdev->dev,
2383                         "could not alloc tx buffers %d\n", ret);
2384                 goto out;
2385         }
2386
2387         ret = hclge_rx_buffer_calc(hdev, pkt_buf);
2388         if (ret) {
2389                 dev_err(&hdev->pdev->dev,
2390                         "could not calc rx priv buffer size for all TCs %d\n",
2391                         ret);
2392                 goto out;
2393         }
2394
2395         ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
2396         if (ret) {
2397                 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
2398                         ret);
2399                 goto out;
2400         }
2401
2402         if (hnae3_dev_dcb_supported(hdev)) {
2403                 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
2404                 if (ret) {
2405                         dev_err(&hdev->pdev->dev,
2406                                 "could not configure rx private waterline %d\n",
2407                                 ret);
2408                         goto out;
2409                 }
2410
2411                 ret = hclge_common_thrd_config(hdev, pkt_buf);
2412                 if (ret) {
2413                         dev_err(&hdev->pdev->dev,
2414                                 "could not configure common threshold %d\n",
2415                                 ret);
2416                         goto out;
2417                 }
2418         }
2419
2420         ret = hclge_common_wl_config(hdev, pkt_buf);
2421         if (ret)
2422                 dev_err(&hdev->pdev->dev,
2423                         "could not configure common waterline %d\n", ret);
2424
2425 out:
2426         kfree(pkt_buf);
2427         return ret;
2428 }
2429
2430 static int hclge_init_roce_base_info(struct hclge_vport *vport)
2431 {
2432         struct hnae3_handle *roce = &vport->roce;
2433         struct hnae3_handle *nic = &vport->nic;
2434         struct hclge_dev *hdev = vport->back;
2435
2436         roce->rinfo.num_vectors = vport->back->num_roce_msi;
2437
2438         if (hdev->num_msi < hdev->num_nic_msi + hdev->num_roce_msi)
2439                 return -EINVAL;
2440
2441         roce->rinfo.base_vector = hdev->num_nic_msi;
2442
2443         roce->rinfo.netdev = nic->kinfo.netdev;
2444         roce->rinfo.roce_io_base = hdev->hw.hw.io_base;
2445         roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base;
2446
2447         roce->pdev = nic->pdev;
2448         roce->ae_algo = nic->ae_algo;
2449         roce->numa_node_mask = nic->numa_node_mask;
2450
2451         return 0;
2452 }
2453
2454 static int hclge_init_msi(struct hclge_dev *hdev)
2455 {
2456         struct pci_dev *pdev = hdev->pdev;
2457         int vectors;
2458         int i;
2459
2460         vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM,
2461                                         hdev->num_msi,
2462                                         PCI_IRQ_MSI | PCI_IRQ_MSIX);
2463         if (vectors < 0) {
2464                 dev_err(&pdev->dev,
2465                         "failed(%d) to allocate MSI/MSI-X vectors\n",
2466                         vectors);
2467                 return vectors;
2468         }
2469         if (vectors < hdev->num_msi)
2470                 dev_warn(&hdev->pdev->dev,
2471                          "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2472                          hdev->num_msi, vectors);
2473
2474         hdev->num_msi = vectors;
2475         hdev->num_msi_left = vectors;
2476
2477         hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2478                                            sizeof(u16), GFP_KERNEL);
2479         if (!hdev->vector_status) {
2480                 pci_free_irq_vectors(pdev);
2481                 return -ENOMEM;
2482         }
2483
2484         for (i = 0; i < hdev->num_msi; i++)
2485                 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
2486
2487         hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2488                                         sizeof(int), GFP_KERNEL);
2489         if (!hdev->vector_irq) {
2490                 pci_free_irq_vectors(pdev);
2491                 return -ENOMEM;
2492         }
2493
2494         return 0;
2495 }
2496
2497 static u8 hclge_check_speed_dup(u8 duplex, int speed)
2498 {
2499         if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M))
2500                 duplex = HCLGE_MAC_FULL;
2501
2502         return duplex;
2503 }
2504
2505 static struct hclge_mac_speed_map hclge_mac_speed_map_to_fw[] = {
2506         {HCLGE_MAC_SPEED_10M, HCLGE_FW_MAC_SPEED_10M},
2507         {HCLGE_MAC_SPEED_100M, HCLGE_FW_MAC_SPEED_100M},
2508         {HCLGE_MAC_SPEED_1G, HCLGE_FW_MAC_SPEED_1G},
2509         {HCLGE_MAC_SPEED_10G, HCLGE_FW_MAC_SPEED_10G},
2510         {HCLGE_MAC_SPEED_25G, HCLGE_FW_MAC_SPEED_25G},
2511         {HCLGE_MAC_SPEED_40G, HCLGE_FW_MAC_SPEED_40G},
2512         {HCLGE_MAC_SPEED_50G, HCLGE_FW_MAC_SPEED_50G},
2513         {HCLGE_MAC_SPEED_100G, HCLGE_FW_MAC_SPEED_100G},
2514         {HCLGE_MAC_SPEED_200G, HCLGE_FW_MAC_SPEED_200G},
2515 };
2516
2517 static int hclge_convert_to_fw_speed(u32 speed_drv, u32 *speed_fw)
2518 {
2519         u16 i;
2520
2521         for (i = 0; i < ARRAY_SIZE(hclge_mac_speed_map_to_fw); i++) {
2522                 if (hclge_mac_speed_map_to_fw[i].speed_drv == speed_drv) {
2523                         *speed_fw = hclge_mac_speed_map_to_fw[i].speed_fw;
2524                         return 0;
2525                 }
2526         }
2527
2528         return -EINVAL;
2529 }
2530
2531 static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed,
2532                                       u8 duplex, u8 lane_num)
2533 {
2534         struct hclge_config_mac_speed_dup_cmd *req;
2535         struct hclge_desc desc;
2536         u32 speed_fw;
2537         int ret;
2538
2539         req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
2540
2541         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
2542
2543         if (duplex)
2544                 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, 1);
2545
2546         ret = hclge_convert_to_fw_speed(speed, &speed_fw);
2547         if (ret) {
2548                 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
2549                 return ret;
2550         }
2551
2552         hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, HCLGE_CFG_SPEED_S,
2553                         speed_fw);
2554         hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
2555                       1);
2556         req->lane_num = lane_num;
2557
2558         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2559         if (ret) {
2560                 dev_err(&hdev->pdev->dev,
2561                         "mac speed/duplex config cmd failed %d.\n", ret);
2562                 return ret;
2563         }
2564
2565         return 0;
2566 }
2567
2568 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex, u8 lane_num)
2569 {
2570         struct hclge_mac *mac = &hdev->hw.mac;
2571         int ret;
2572
2573         duplex = hclge_check_speed_dup(duplex, speed);
2574         if (!mac->support_autoneg && mac->speed == speed &&
2575             mac->duplex == duplex && (mac->lane_num == lane_num || lane_num == 0))
2576                 return 0;
2577
2578         ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex, lane_num);
2579         if (ret)
2580                 return ret;
2581
2582         hdev->hw.mac.speed = speed;
2583         hdev->hw.mac.duplex = duplex;
2584         if (!lane_num)
2585                 hdev->hw.mac.lane_num = lane_num;
2586
2587         return 0;
2588 }
2589
2590 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2591                                      u8 duplex, u8 lane_num)
2592 {
2593         struct hclge_vport *vport = hclge_get_vport(handle);
2594         struct hclge_dev *hdev = vport->back;
2595
2596         return hclge_cfg_mac_speed_dup(hdev, speed, duplex, lane_num);
2597 }
2598
2599 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2600 {
2601         struct hclge_config_auto_neg_cmd *req;
2602         struct hclge_desc desc;
2603         u32 flag = 0;
2604         int ret;
2605
2606         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2607
2608         req = (struct hclge_config_auto_neg_cmd *)desc.data;
2609         if (enable)
2610                 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, 1U);
2611         req->cfg_an_cmd_flag = cpu_to_le32(flag);
2612
2613         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2614         if (ret)
2615                 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2616                         ret);
2617
2618         return ret;
2619 }
2620
2621 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2622 {
2623         struct hclge_vport *vport = hclge_get_vport(handle);
2624         struct hclge_dev *hdev = vport->back;
2625
2626         if (!hdev->hw.mac.support_autoneg) {
2627                 if (enable) {
2628                         dev_err(&hdev->pdev->dev,
2629                                 "autoneg is not supported by current port\n");
2630                         return -EOPNOTSUPP;
2631                 } else {
2632                         return 0;
2633                 }
2634         }
2635
2636         return hclge_set_autoneg_en(hdev, enable);
2637 }
2638
2639 static int hclge_get_autoneg(struct hnae3_handle *handle)
2640 {
2641         struct hclge_vport *vport = hclge_get_vport(handle);
2642         struct hclge_dev *hdev = vport->back;
2643         struct phy_device *phydev = hdev->hw.mac.phydev;
2644
2645         if (phydev)
2646                 return phydev->autoneg;
2647
2648         return hdev->hw.mac.autoneg;
2649 }
2650
2651 static int hclge_restart_autoneg(struct hnae3_handle *handle)
2652 {
2653         struct hclge_vport *vport = hclge_get_vport(handle);
2654         struct hclge_dev *hdev = vport->back;
2655         int ret;
2656
2657         dev_dbg(&hdev->pdev->dev, "restart autoneg\n");
2658
2659         ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2660         if (ret)
2661                 return ret;
2662         return hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2663 }
2664
2665 static int hclge_halt_autoneg(struct hnae3_handle *handle, bool halt)
2666 {
2667         struct hclge_vport *vport = hclge_get_vport(handle);
2668         struct hclge_dev *hdev = vport->back;
2669
2670         if (hdev->hw.mac.support_autoneg && hdev->hw.mac.autoneg)
2671                 return hclge_set_autoneg_en(hdev, !halt);
2672
2673         return 0;
2674 }
2675
2676 static void hclge_parse_fec_stats_lanes(struct hclge_dev *hdev,
2677                                         struct hclge_desc *desc, u32 desc_len)
2678 {
2679         u32 lane_size = HCLGE_FEC_STATS_MAX_LANES * 2;
2680         u32 desc_index = 0;
2681         u32 data_index = 0;
2682         u32 i;
2683
2684         for (i = 0; i < lane_size; i++) {
2685                 if (data_index >= HCLGE_DESC_DATA_LEN) {
2686                         desc_index++;
2687                         data_index = 0;
2688                 }
2689
2690                 if (desc_index >= desc_len)
2691                         return;
2692
2693                 hdev->fec_stats.per_lanes[i] +=
2694                         le32_to_cpu(desc[desc_index].data[data_index]);
2695                 data_index++;
2696         }
2697 }
2698
2699 static void hclge_parse_fec_stats(struct hclge_dev *hdev,
2700                                   struct hclge_desc *desc, u32 desc_len)
2701 {
2702         struct hclge_query_fec_stats_cmd *req;
2703
2704         req = (struct hclge_query_fec_stats_cmd *)desc[0].data;
2705
2706         hdev->fec_stats.base_r_lane_num = req->base_r_lane_num;
2707         hdev->fec_stats.rs_corr_blocks +=
2708                 le32_to_cpu(req->rs_fec_corr_blocks);
2709         hdev->fec_stats.rs_uncorr_blocks +=
2710                 le32_to_cpu(req->rs_fec_uncorr_blocks);
2711         hdev->fec_stats.rs_error_blocks +=
2712                 le32_to_cpu(req->rs_fec_error_blocks);
2713         hdev->fec_stats.base_r_corr_blocks +=
2714                 le32_to_cpu(req->base_r_fec_corr_blocks);
2715         hdev->fec_stats.base_r_uncorr_blocks +=
2716                 le32_to_cpu(req->base_r_fec_uncorr_blocks);
2717
2718         hclge_parse_fec_stats_lanes(hdev, &desc[1], desc_len - 1);
2719 }
2720
2721 static int hclge_update_fec_stats_hw(struct hclge_dev *hdev)
2722 {
2723         struct hclge_desc desc[HCLGE_FEC_STATS_CMD_NUM];
2724         int ret;
2725         u32 i;
2726
2727         for (i = 0; i < HCLGE_FEC_STATS_CMD_NUM; i++) {
2728                 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_FEC_STATS,
2729                                            true);
2730                 if (i != (HCLGE_FEC_STATS_CMD_NUM - 1))
2731                         desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2732         }
2733
2734         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_FEC_STATS_CMD_NUM);
2735         if (ret)
2736                 return ret;
2737
2738         hclge_parse_fec_stats(hdev, desc, HCLGE_FEC_STATS_CMD_NUM);
2739
2740         return 0;
2741 }
2742
2743 static void hclge_update_fec_stats(struct hclge_dev *hdev)
2744 {
2745         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
2746         int ret;
2747
2748         if (!hnae3_ae_dev_fec_stats_supported(ae_dev) ||
2749             test_and_set_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state))
2750                 return;
2751
2752         ret = hclge_update_fec_stats_hw(hdev);
2753         if (ret)
2754                 dev_err(&hdev->pdev->dev,
2755                         "failed to update fec stats, ret = %d\n", ret);
2756
2757         clear_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state);
2758 }
2759
2760 static void hclge_get_fec_stats_total(struct hclge_dev *hdev,
2761                                       struct ethtool_fec_stats *fec_stats)
2762 {
2763         fec_stats->corrected_blocks.total = hdev->fec_stats.rs_corr_blocks;
2764         fec_stats->uncorrectable_blocks.total =
2765                 hdev->fec_stats.rs_uncorr_blocks;
2766 }
2767
2768 static void hclge_get_fec_stats_lanes(struct hclge_dev *hdev,
2769                                       struct ethtool_fec_stats *fec_stats)
2770 {
2771         u32 i;
2772
2773         if (hdev->fec_stats.base_r_lane_num == 0 ||
2774             hdev->fec_stats.base_r_lane_num > HCLGE_FEC_STATS_MAX_LANES) {
2775                 dev_err(&hdev->pdev->dev,
2776                         "fec stats lane number(%llu) is invalid\n",
2777                         hdev->fec_stats.base_r_lane_num);
2778                 return;
2779         }
2780
2781         for (i = 0; i < hdev->fec_stats.base_r_lane_num; i++) {
2782                 fec_stats->corrected_blocks.lanes[i] =
2783                         hdev->fec_stats.base_r_corr_per_lanes[i];
2784                 fec_stats->uncorrectable_blocks.lanes[i] =
2785                         hdev->fec_stats.base_r_uncorr_per_lanes[i];
2786         }
2787 }
2788
2789 static void hclge_comm_get_fec_stats(struct hclge_dev *hdev,
2790                                      struct ethtool_fec_stats *fec_stats)
2791 {
2792         u32 fec_mode = hdev->hw.mac.fec_mode;
2793
2794         switch (fec_mode) {
2795         case BIT(HNAE3_FEC_RS):
2796         case BIT(HNAE3_FEC_LLRS):
2797                 hclge_get_fec_stats_total(hdev, fec_stats);
2798                 break;
2799         case BIT(HNAE3_FEC_BASER):
2800                 hclge_get_fec_stats_lanes(hdev, fec_stats);
2801                 break;
2802         default:
2803                 dev_err(&hdev->pdev->dev,
2804                         "fec stats is not supported by current fec mode(0x%x)\n",
2805                         fec_mode);
2806                 break;
2807         }
2808 }
2809
2810 static void hclge_get_fec_stats(struct hnae3_handle *handle,
2811                                 struct ethtool_fec_stats *fec_stats)
2812 {
2813         struct hclge_vport *vport = hclge_get_vport(handle);
2814         struct hclge_dev *hdev = vport->back;
2815         u32 fec_mode = hdev->hw.mac.fec_mode;
2816
2817         if (fec_mode == BIT(HNAE3_FEC_NONE) ||
2818             fec_mode == BIT(HNAE3_FEC_AUTO) ||
2819             fec_mode == BIT(HNAE3_FEC_USER_DEF))
2820                 return;
2821
2822         hclge_update_fec_stats(hdev);
2823
2824         hclge_comm_get_fec_stats(hdev, fec_stats);
2825 }
2826
2827 static int hclge_set_fec_hw(struct hclge_dev *hdev, u32 fec_mode)
2828 {
2829         struct hclge_config_fec_cmd *req;
2830         struct hclge_desc desc;
2831         int ret;
2832
2833         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_FEC_MODE, false);
2834
2835         req = (struct hclge_config_fec_cmd *)desc.data;
2836         if (fec_mode & BIT(HNAE3_FEC_AUTO))
2837                 hnae3_set_bit(req->fec_mode, HCLGE_MAC_CFG_FEC_AUTO_EN_B, 1);
2838         if (fec_mode & BIT(HNAE3_FEC_RS))
2839                 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M,
2840                                 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_RS);
2841         if (fec_mode & BIT(HNAE3_FEC_LLRS))
2842                 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M,
2843                                 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_LLRS);
2844         if (fec_mode & BIT(HNAE3_FEC_BASER))
2845                 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M,
2846                                 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_BASER);
2847
2848         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2849         if (ret)
2850                 dev_err(&hdev->pdev->dev, "set fec mode failed %d.\n", ret);
2851
2852         return ret;
2853 }
2854
2855 static int hclge_set_fec(struct hnae3_handle *handle, u32 fec_mode)
2856 {
2857         struct hclge_vport *vport = hclge_get_vport(handle);
2858         struct hclge_dev *hdev = vport->back;
2859         struct hclge_mac *mac = &hdev->hw.mac;
2860         int ret;
2861
2862         if (fec_mode && !(mac->fec_ability & fec_mode)) {
2863                 dev_err(&hdev->pdev->dev, "unsupported fec mode\n");
2864                 return -EINVAL;
2865         }
2866
2867         ret = hclge_set_fec_hw(hdev, fec_mode);
2868         if (ret)
2869                 return ret;
2870
2871         mac->user_fec_mode = fec_mode | BIT(HNAE3_FEC_USER_DEF);
2872         return 0;
2873 }
2874
2875 static void hclge_get_fec(struct hnae3_handle *handle, u8 *fec_ability,
2876                           u8 *fec_mode)
2877 {
2878         struct hclge_vport *vport = hclge_get_vport(handle);
2879         struct hclge_dev *hdev = vport->back;
2880         struct hclge_mac *mac = &hdev->hw.mac;
2881
2882         if (fec_ability)
2883                 *fec_ability = mac->fec_ability;
2884         if (fec_mode)
2885                 *fec_mode = mac->fec_mode;
2886 }
2887
2888 static int hclge_mac_init(struct hclge_dev *hdev)
2889 {
2890         struct hclge_mac *mac = &hdev->hw.mac;
2891         int ret;
2892
2893         hdev->support_sfp_query = true;
2894         hdev->hw.mac.duplex = HCLGE_MAC_FULL;
2895         ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed,
2896                                          hdev->hw.mac.duplex, hdev->hw.mac.lane_num);
2897         if (ret)
2898                 return ret;
2899
2900         if (hdev->hw.mac.support_autoneg) {
2901                 ret = hclge_set_autoneg_en(hdev, hdev->hw.mac.autoneg);
2902                 if (ret)
2903                         return ret;
2904         }
2905
2906         mac->link = 0;
2907
2908         if (mac->user_fec_mode & BIT(HNAE3_FEC_USER_DEF)) {
2909                 ret = hclge_set_fec_hw(hdev, mac->user_fec_mode);
2910                 if (ret)
2911                         return ret;
2912         }
2913
2914         ret = hclge_set_mac_mtu(hdev, hdev->mps);
2915         if (ret) {
2916                 dev_err(&hdev->pdev->dev, "set mtu failed ret=%d\n", ret);
2917                 return ret;
2918         }
2919
2920         ret = hclge_set_default_loopback(hdev);
2921         if (ret)
2922                 return ret;
2923
2924         ret = hclge_buffer_alloc(hdev);
2925         if (ret)
2926                 dev_err(&hdev->pdev->dev,
2927                         "allocate buffer fail, ret=%d\n", ret);
2928
2929         return ret;
2930 }
2931
2932 static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
2933 {
2934         if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2935             !test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) {
2936                 hdev->last_mbx_scheduled = jiffies;
2937                 mod_delayed_work(hclge_wq, &hdev->service_task, 0);
2938         }
2939 }
2940
2941 static void hclge_reset_task_schedule(struct hclge_dev *hdev)
2942 {
2943         if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2944             test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state) &&
2945             !test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) {
2946                 hdev->last_rst_scheduled = jiffies;
2947                 mod_delayed_work(hclge_wq, &hdev->service_task, 0);
2948         }
2949 }
2950
2951 static void hclge_errhand_task_schedule(struct hclge_dev *hdev)
2952 {
2953         if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2954             !test_and_set_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state))
2955                 mod_delayed_work(hclge_wq, &hdev->service_task, 0);
2956 }
2957
2958 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time)
2959 {
2960         if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2961             !test_bit(HCLGE_STATE_RST_FAIL, &hdev->state))
2962                 mod_delayed_work(hclge_wq, &hdev->service_task, delay_time);
2963 }
2964
2965 static int hclge_get_mac_link_status(struct hclge_dev *hdev, int *link_status)
2966 {
2967         struct hclge_link_status_cmd *req;
2968         struct hclge_desc desc;
2969         int ret;
2970
2971         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2972         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2973         if (ret) {
2974                 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2975                         ret);
2976                 return ret;
2977         }
2978
2979         req = (struct hclge_link_status_cmd *)desc.data;
2980         *link_status = (req->status & HCLGE_LINK_STATUS_UP_M) > 0 ?
2981                 HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN;
2982
2983         return 0;
2984 }
2985
2986 static int hclge_get_mac_phy_link(struct hclge_dev *hdev, int *link_status)
2987 {
2988         struct phy_device *phydev = hdev->hw.mac.phydev;
2989
2990         *link_status = HCLGE_LINK_STATUS_DOWN;
2991
2992         if (test_bit(HCLGE_STATE_DOWN, &hdev->state))
2993                 return 0;
2994
2995         if (phydev && (phydev->state != PHY_RUNNING || !phydev->link))
2996                 return 0;
2997
2998         return hclge_get_mac_link_status(hdev, link_status);
2999 }
3000
3001 static void hclge_push_link_status(struct hclge_dev *hdev)
3002 {
3003         struct hclge_vport *vport;
3004         int ret;
3005         u16 i;
3006
3007         for (i = 0; i < pci_num_vf(hdev->pdev); i++) {
3008                 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM];
3009
3010                 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) ||
3011                     vport->vf_info.link_state != IFLA_VF_LINK_STATE_AUTO)
3012                         continue;
3013
3014                 ret = hclge_push_vf_link_status(vport);
3015                 if (ret) {
3016                         dev_err(&hdev->pdev->dev,
3017                                 "failed to push link status to vf%u, ret = %d\n",
3018                                 i, ret);
3019                 }
3020         }
3021 }
3022
3023 static void hclge_update_link_status(struct hclge_dev *hdev)
3024 {
3025         struct hnae3_handle *rhandle = &hdev->vport[0].roce;
3026         struct hnae3_handle *handle = &hdev->vport[0].nic;
3027         struct hnae3_client *rclient = hdev->roce_client;
3028         struct hnae3_client *client = hdev->nic_client;
3029         int state;
3030         int ret;
3031
3032         if (!client)
3033                 return;
3034
3035         if (test_and_set_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state))
3036                 return;
3037
3038         ret = hclge_get_mac_phy_link(hdev, &state);
3039         if (ret) {
3040                 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state);
3041                 return;
3042         }
3043
3044         if (state != hdev->hw.mac.link) {
3045                 hdev->hw.mac.link = state;
3046                 client->ops->link_status_change(handle, state);
3047                 hclge_config_mac_tnl_int(hdev, state);
3048                 if (rclient && rclient->ops->link_status_change)
3049                         rclient->ops->link_status_change(rhandle, state);
3050
3051                 hclge_push_link_status(hdev);
3052         }
3053
3054         clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state);
3055 }
3056
3057 static void hclge_update_speed_advertising(struct hclge_mac *mac)
3058 {
3059         u32 speed_ability;
3060
3061         if (hclge_get_speed_bit(mac->speed, &speed_ability))
3062                 return;
3063
3064         switch (mac->module_type) {
3065         case HNAE3_MODULE_TYPE_FIBRE_LR:
3066                 hclge_convert_setting_lr(speed_ability, mac->advertising);
3067                 break;
3068         case HNAE3_MODULE_TYPE_FIBRE_SR:
3069         case HNAE3_MODULE_TYPE_AOC:
3070                 hclge_convert_setting_sr(speed_ability, mac->advertising);
3071                 break;
3072         case HNAE3_MODULE_TYPE_CR:
3073                 hclge_convert_setting_cr(speed_ability, mac->advertising);
3074                 break;
3075         case HNAE3_MODULE_TYPE_KR:
3076                 hclge_convert_setting_kr(speed_ability, mac->advertising);
3077                 break;
3078         default:
3079                 break;
3080         }
3081 }
3082
3083 static void hclge_update_fec_advertising(struct hclge_mac *mac)
3084 {
3085         if (mac->fec_mode & BIT(HNAE3_FEC_RS))
3086                 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
3087                                  mac->advertising);
3088         else if (mac->fec_mode & BIT(HNAE3_FEC_LLRS))
3089                 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
3090                                  mac->advertising);
3091         else if (mac->fec_mode & BIT(HNAE3_FEC_BASER))
3092                 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
3093                                  mac->advertising);
3094         else
3095                 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
3096                                  mac->advertising);
3097 }
3098
3099 static void hclge_update_pause_advertising(struct hclge_dev *hdev)
3100 {
3101         struct hclge_mac *mac = &hdev->hw.mac;
3102         bool rx_en, tx_en;
3103
3104         switch (hdev->fc_mode_last_time) {
3105         case HCLGE_FC_RX_PAUSE:
3106                 rx_en = true;
3107                 tx_en = false;
3108                 break;
3109         case HCLGE_FC_TX_PAUSE:
3110                 rx_en = false;
3111                 tx_en = true;
3112                 break;
3113         case HCLGE_FC_FULL:
3114                 rx_en = true;
3115                 tx_en = true;
3116                 break;
3117         default:
3118                 rx_en = false;
3119                 tx_en = false;
3120                 break;
3121         }
3122
3123         linkmode_set_pause(mac->advertising, tx_en, rx_en);
3124 }
3125
3126 static void hclge_update_advertising(struct hclge_dev *hdev)
3127 {
3128         struct hclge_mac *mac = &hdev->hw.mac;
3129
3130         linkmode_zero(mac->advertising);
3131         hclge_update_speed_advertising(mac);
3132         hclge_update_fec_advertising(mac);
3133         hclge_update_pause_advertising(hdev);
3134 }
3135
3136 static void hclge_update_port_capability(struct hclge_dev *hdev,
3137                                          struct hclge_mac *mac)
3138 {
3139         if (hnae3_dev_fec_supported(hdev))
3140                 hclge_convert_setting_fec(mac);
3141
3142         /* firmware can not identify back plane type, the media type
3143          * read from configuration can help deal it
3144          */
3145         if (mac->media_type == HNAE3_MEDIA_TYPE_BACKPLANE &&
3146             mac->module_type == HNAE3_MODULE_TYPE_UNKNOWN)
3147                 mac->module_type = HNAE3_MODULE_TYPE_KR;
3148         else if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER)
3149                 mac->module_type = HNAE3_MODULE_TYPE_TP;
3150
3151         if (mac->support_autoneg) {
3152                 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mac->supported);
3153                 linkmode_copy(mac->advertising, mac->supported);
3154         } else {
3155                 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
3156                                    mac->supported);
3157                 hclge_update_advertising(hdev);
3158         }
3159 }
3160
3161 static int hclge_get_sfp_speed(struct hclge_dev *hdev, u32 *speed)
3162 {
3163         struct hclge_sfp_info_cmd *resp;
3164         struct hclge_desc desc;
3165         int ret;
3166
3167         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true);
3168         resp = (struct hclge_sfp_info_cmd *)desc.data;
3169         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3170         if (ret == -EOPNOTSUPP) {
3171                 dev_warn(&hdev->pdev->dev,
3172                          "IMP do not support get SFP speed %d\n", ret);
3173                 return ret;
3174         } else if (ret) {
3175                 dev_err(&hdev->pdev->dev, "get sfp speed failed %d\n", ret);
3176                 return ret;
3177         }
3178
3179         *speed = le32_to_cpu(resp->speed);
3180
3181         return 0;
3182 }
3183
3184 static int hclge_get_sfp_info(struct hclge_dev *hdev, struct hclge_mac *mac)
3185 {
3186         struct hclge_sfp_info_cmd *resp;
3187         struct hclge_desc desc;
3188         int ret;
3189
3190         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true);
3191         resp = (struct hclge_sfp_info_cmd *)desc.data;
3192
3193         resp->query_type = QUERY_ACTIVE_SPEED;
3194
3195         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3196         if (ret == -EOPNOTSUPP) {
3197                 dev_warn(&hdev->pdev->dev,
3198                          "IMP does not support get SFP info %d\n", ret);
3199                 return ret;
3200         } else if (ret) {
3201                 dev_err(&hdev->pdev->dev, "get sfp info failed %d\n", ret);
3202                 return ret;
3203         }
3204
3205         /* In some case, mac speed get from IMP may be 0, it shouldn't be
3206          * set to mac->speed.
3207          */
3208         if (!le32_to_cpu(resp->speed))
3209                 return 0;
3210
3211         mac->speed = le32_to_cpu(resp->speed);
3212         /* if resp->speed_ability is 0, it means it's an old version
3213          * firmware, do not update these params
3214          */
3215         if (resp->speed_ability) {
3216                 mac->module_type = le32_to_cpu(resp->module_type);
3217                 mac->speed_ability = le32_to_cpu(resp->speed_ability);
3218                 mac->autoneg = resp->autoneg;
3219                 mac->support_autoneg = resp->autoneg_ability;
3220                 mac->speed_type = QUERY_ACTIVE_SPEED;
3221                 mac->lane_num = resp->lane_num;
3222                 if (!resp->active_fec)
3223                         mac->fec_mode = 0;
3224                 else
3225                         mac->fec_mode = BIT(resp->active_fec);
3226                 mac->fec_ability = resp->fec_ability;
3227         } else {
3228                 mac->speed_type = QUERY_SFP_SPEED;
3229         }
3230
3231         return 0;
3232 }
3233
3234 static int hclge_get_phy_link_ksettings(struct hnae3_handle *handle,
3235                                         struct ethtool_link_ksettings *cmd)
3236 {
3237         struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM];
3238         struct hclge_vport *vport = hclge_get_vport(handle);
3239         struct hclge_phy_link_ksetting_0_cmd *req0;
3240         struct hclge_phy_link_ksetting_1_cmd *req1;
3241         u32 supported, advertising, lp_advertising;
3242         struct hclge_dev *hdev = vport->back;
3243         int ret;
3244
3245         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING,
3246                                    true);
3247         desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
3248         hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING,
3249                                    true);
3250
3251         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM);
3252         if (ret) {
3253                 dev_err(&hdev->pdev->dev,
3254                         "failed to get phy link ksetting, ret = %d.\n", ret);
3255                 return ret;
3256         }
3257
3258         req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data;
3259         cmd->base.autoneg = req0->autoneg;
3260         cmd->base.speed = le32_to_cpu(req0->speed);
3261         cmd->base.duplex = req0->duplex;
3262         cmd->base.port = req0->port;
3263         cmd->base.transceiver = req0->transceiver;
3264         cmd->base.phy_address = req0->phy_address;
3265         cmd->base.eth_tp_mdix = req0->eth_tp_mdix;
3266         cmd->base.eth_tp_mdix_ctrl = req0->eth_tp_mdix_ctrl;
3267         supported = le32_to_cpu(req0->supported);
3268         advertising = le32_to_cpu(req0->advertising);
3269         lp_advertising = le32_to_cpu(req0->lp_advertising);
3270         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
3271                                                 supported);
3272         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
3273                                                 advertising);
3274         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising,
3275                                                 lp_advertising);
3276
3277         req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data;
3278         cmd->base.master_slave_cfg = req1->master_slave_cfg;
3279         cmd->base.master_slave_state = req1->master_slave_state;
3280
3281         return 0;
3282 }
3283
3284 static int
3285 hclge_set_phy_link_ksettings(struct hnae3_handle *handle,
3286                              const struct ethtool_link_ksettings *cmd)
3287 {
3288         struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM];
3289         struct hclge_vport *vport = hclge_get_vport(handle);
3290         struct hclge_phy_link_ksetting_0_cmd *req0;
3291         struct hclge_phy_link_ksetting_1_cmd *req1;
3292         struct hclge_dev *hdev = vport->back;
3293         u32 advertising;
3294         int ret;
3295
3296         if (cmd->base.autoneg == AUTONEG_DISABLE &&
3297             ((cmd->base.speed != SPEED_100 && cmd->base.speed != SPEED_10) ||
3298              (cmd->base.duplex != DUPLEX_HALF &&
3299               cmd->base.duplex != DUPLEX_FULL)))
3300                 return -EINVAL;
3301
3302         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING,
3303                                    false);
3304         desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
3305         hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING,
3306                                    false);
3307
3308         req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data;
3309         req0->autoneg = cmd->base.autoneg;
3310         req0->speed = cpu_to_le32(cmd->base.speed);
3311         req0->duplex = cmd->base.duplex;
3312         ethtool_convert_link_mode_to_legacy_u32(&advertising,
3313                                                 cmd->link_modes.advertising);
3314         req0->advertising = cpu_to_le32(advertising);
3315         req0->eth_tp_mdix_ctrl = cmd->base.eth_tp_mdix_ctrl;
3316
3317         req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data;
3318         req1->master_slave_cfg = cmd->base.master_slave_cfg;
3319
3320         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM);
3321         if (ret) {
3322                 dev_err(&hdev->pdev->dev,
3323                         "failed to set phy link ksettings, ret = %d.\n", ret);
3324                 return ret;
3325         }
3326
3327         hdev->hw.mac.autoneg = cmd->base.autoneg;
3328         hdev->hw.mac.speed = cmd->base.speed;
3329         hdev->hw.mac.duplex = cmd->base.duplex;
3330         linkmode_copy(hdev->hw.mac.advertising, cmd->link_modes.advertising);
3331
3332         return 0;
3333 }
3334
3335 static int hclge_update_tp_port_info(struct hclge_dev *hdev)
3336 {
3337         struct ethtool_link_ksettings cmd;
3338         int ret;
3339
3340         if (!hnae3_dev_phy_imp_supported(hdev))
3341                 return 0;
3342
3343         ret = hclge_get_phy_link_ksettings(&hdev->vport->nic, &cmd);
3344         if (ret)
3345                 return ret;
3346
3347         hdev->hw.mac.autoneg = cmd.base.autoneg;
3348         hdev->hw.mac.speed = cmd.base.speed;
3349         hdev->hw.mac.duplex = cmd.base.duplex;
3350         linkmode_copy(hdev->hw.mac.advertising, cmd.link_modes.advertising);
3351
3352         return 0;
3353 }
3354
3355 static int hclge_tp_port_init(struct hclge_dev *hdev)
3356 {
3357         struct ethtool_link_ksettings cmd;
3358
3359         if (!hnae3_dev_phy_imp_supported(hdev))
3360                 return 0;
3361
3362         cmd.base.autoneg = hdev->hw.mac.autoneg;
3363         cmd.base.speed = hdev->hw.mac.speed;
3364         cmd.base.duplex = hdev->hw.mac.duplex;
3365         linkmode_copy(cmd.link_modes.advertising, hdev->hw.mac.advertising);
3366
3367         return hclge_set_phy_link_ksettings(&hdev->vport->nic, &cmd);
3368 }
3369
3370 static int hclge_update_port_info(struct hclge_dev *hdev)
3371 {
3372         struct hclge_mac *mac = &hdev->hw.mac;
3373         int speed;
3374         int ret;
3375
3376         /* get the port info from SFP cmd if not copper port */
3377         if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER)
3378                 return hclge_update_tp_port_info(hdev);
3379
3380         /* if IMP does not support get SFP/qSFP info, return directly */
3381         if (!hdev->support_sfp_query)
3382                 return 0;
3383
3384         if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
3385                 speed = mac->speed;
3386                 ret = hclge_get_sfp_info(hdev, mac);
3387         } else {
3388                 speed = HCLGE_MAC_SPEED_UNKNOWN;
3389                 ret = hclge_get_sfp_speed(hdev, &speed);
3390         }
3391
3392         if (ret == -EOPNOTSUPP) {
3393                 hdev->support_sfp_query = false;
3394                 return ret;
3395         } else if (ret) {
3396                 return ret;
3397         }
3398
3399         if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
3400                 if (mac->speed_type == QUERY_ACTIVE_SPEED) {
3401                         hclge_update_port_capability(hdev, mac);
3402                         if (mac->speed != speed)
3403                                 (void)hclge_tm_port_shaper_cfg(hdev);
3404                         return 0;
3405                 }
3406                 return hclge_cfg_mac_speed_dup(hdev, mac->speed,
3407                                                HCLGE_MAC_FULL, mac->lane_num);
3408         } else {
3409                 if (speed == HCLGE_MAC_SPEED_UNKNOWN)
3410                         return 0; /* do nothing if no SFP */
3411
3412                 /* must config full duplex for SFP */
3413                 return hclge_cfg_mac_speed_dup(hdev, speed, HCLGE_MAC_FULL, 0);
3414         }
3415 }
3416
3417 static int hclge_get_status(struct hnae3_handle *handle)
3418 {
3419         struct hclge_vport *vport = hclge_get_vport(handle);
3420         struct hclge_dev *hdev = vport->back;
3421
3422         hclge_update_link_status(hdev);
3423
3424         return hdev->hw.mac.link;
3425 }
3426
3427 static struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf)
3428 {
3429         if (!pci_num_vf(hdev->pdev)) {
3430                 dev_err(&hdev->pdev->dev,
3431                         "SRIOV is disabled, can not get vport(%d) info.\n", vf);
3432                 return NULL;
3433         }
3434
3435         if (vf < 0 || vf >= pci_num_vf(hdev->pdev)) {
3436                 dev_err(&hdev->pdev->dev,
3437                         "vf id(%d) is out of range(0 <= vfid < %d)\n",
3438                         vf, pci_num_vf(hdev->pdev));
3439                 return NULL;
3440         }
3441
3442         /* VF start from 1 in vport */
3443         vf += HCLGE_VF_VPORT_START_NUM;
3444         return &hdev->vport[vf];
3445 }
3446
3447 static int hclge_get_vf_config(struct hnae3_handle *handle, int vf,
3448                                struct ifla_vf_info *ivf)
3449 {
3450         struct hclge_vport *vport = hclge_get_vport(handle);
3451         struct hclge_dev *hdev = vport->back;
3452
3453         vport = hclge_get_vf_vport(hdev, vf);
3454         if (!vport)
3455                 return -EINVAL;
3456
3457         ivf->vf = vf;
3458         ivf->linkstate = vport->vf_info.link_state;
3459         ivf->spoofchk = vport->vf_info.spoofchk;
3460         ivf->trusted = vport->vf_info.trusted;
3461         ivf->min_tx_rate = 0;
3462         ivf->max_tx_rate = vport->vf_info.max_tx_rate;
3463         ivf->vlan = vport->port_base_vlan_cfg.vlan_info.vlan_tag;
3464         ivf->vlan_proto = htons(vport->port_base_vlan_cfg.vlan_info.vlan_proto);
3465         ivf->qos = vport->port_base_vlan_cfg.vlan_info.qos;
3466         ether_addr_copy(ivf->mac, vport->vf_info.mac);
3467
3468         return 0;
3469 }
3470
3471 static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf,
3472                                    int link_state)
3473 {
3474         struct hclge_vport *vport = hclge_get_vport(handle);
3475         struct hclge_dev *hdev = vport->back;
3476         int link_state_old;
3477         int ret;
3478
3479         vport = hclge_get_vf_vport(hdev, vf);
3480         if (!vport)
3481                 return -EINVAL;
3482
3483         link_state_old = vport->vf_info.link_state;
3484         vport->vf_info.link_state = link_state;
3485
3486         /* return success directly if the VF is unalive, VF will
3487          * query link state itself when it starts work.
3488          */
3489         if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state))
3490                 return 0;
3491
3492         ret = hclge_push_vf_link_status(vport);
3493         if (ret) {
3494                 vport->vf_info.link_state = link_state_old;
3495                 dev_err(&hdev->pdev->dev,
3496                         "failed to push vf%d link status, ret = %d\n", vf, ret);
3497         }
3498
3499         return ret;
3500 }
3501
3502 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
3503 {
3504         u32 cmdq_src_reg, msix_src_reg, hw_err_src_reg;
3505
3506         /* fetch the events from their corresponding regs */
3507         cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
3508         msix_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
3509         hw_err_src_reg = hclge_read_dev(&hdev->hw,
3510                                         HCLGE_RAS_PF_OTHER_INT_STS_REG);
3511
3512         /* Assumption: If by any chance reset and mailbox events are reported
3513          * together then we will only process reset event in this go and will
3514          * defer the processing of the mailbox events. Since, we would have not
3515          * cleared RX CMDQ event this time we would receive again another
3516          * interrupt from H/W just for the mailbox.
3517          *
3518          * check for vector0 reset event sources
3519          */
3520         if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) {
3521                 dev_info(&hdev->pdev->dev, "IMP reset interrupt\n");
3522                 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
3523                 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
3524                 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
3525                 hdev->rst_stats.imp_rst_cnt++;
3526                 return HCLGE_VECTOR0_EVENT_RST;
3527         }
3528
3529         if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & msix_src_reg) {
3530                 dev_info(&hdev->pdev->dev, "global reset interrupt\n");
3531                 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
3532                 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
3533                 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
3534                 hdev->rst_stats.global_rst_cnt++;
3535                 return HCLGE_VECTOR0_EVENT_RST;
3536         }
3537
3538         /* check for vector0 msix event and hardware error event source */
3539         if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK ||
3540             hw_err_src_reg & HCLGE_RAS_REG_ERR_MASK)
3541                 return HCLGE_VECTOR0_EVENT_ERR;
3542
3543         /* check for vector0 ptp event source */
3544         if (BIT(HCLGE_VECTOR0_REG_PTP_INT_B) & msix_src_reg) {
3545                 *clearval = msix_src_reg;
3546                 return HCLGE_VECTOR0_EVENT_PTP;
3547         }
3548
3549         /* check for vector0 mailbox(=CMDQ RX) event source */
3550         if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
3551                 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
3552                 *clearval = cmdq_src_reg;
3553                 return HCLGE_VECTOR0_EVENT_MBX;
3554         }
3555
3556         /* print other vector0 event source */
3557         dev_info(&hdev->pdev->dev,
3558                  "INT status: CMDQ(%#x) HW errors(%#x) other(%#x)\n",
3559                  cmdq_src_reg, hw_err_src_reg, msix_src_reg);
3560
3561         return HCLGE_VECTOR0_EVENT_OTHER;
3562 }
3563
3564 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
3565                                     u32 regclr)
3566 {
3567 #define HCLGE_IMP_RESET_DELAY           5
3568
3569         switch (event_type) {
3570         case HCLGE_VECTOR0_EVENT_PTP:
3571         case HCLGE_VECTOR0_EVENT_RST:
3572                 if (regclr == BIT(HCLGE_VECTOR0_IMPRESET_INT_B))
3573                         mdelay(HCLGE_IMP_RESET_DELAY);
3574
3575                 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
3576                 break;
3577         case HCLGE_VECTOR0_EVENT_MBX:
3578                 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
3579                 break;
3580         default:
3581                 break;
3582         }
3583 }
3584
3585 static void hclge_clear_all_event_cause(struct hclge_dev *hdev)
3586 {
3587         hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST,
3588                                 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) |
3589                                 BIT(HCLGE_VECTOR0_CORERESET_INT_B) |
3590                                 BIT(HCLGE_VECTOR0_IMPRESET_INT_B));
3591         hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0);
3592 }
3593
3594 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
3595 {
3596         writel(enable ? 1 : 0, vector->addr);
3597 }
3598
3599 static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
3600 {
3601         struct hclge_dev *hdev = data;
3602         unsigned long flags;
3603         u32 clearval = 0;
3604         u32 event_cause;
3605
3606         hclge_enable_vector(&hdev->misc_vector, false);
3607         event_cause = hclge_check_event_cause(hdev, &clearval);
3608
3609         /* vector 0 interrupt is shared with reset and mailbox source events. */
3610         switch (event_cause) {
3611         case HCLGE_VECTOR0_EVENT_ERR:
3612                 hclge_errhand_task_schedule(hdev);
3613                 break;
3614         case HCLGE_VECTOR0_EVENT_RST:
3615                 hclge_reset_task_schedule(hdev);
3616                 break;
3617         case HCLGE_VECTOR0_EVENT_PTP:
3618                 spin_lock_irqsave(&hdev->ptp->lock, flags);
3619                 hclge_ptp_clean_tx_hwts(hdev);
3620                 spin_unlock_irqrestore(&hdev->ptp->lock, flags);
3621                 break;
3622         case HCLGE_VECTOR0_EVENT_MBX:
3623                 /* If we are here then,
3624                  * 1. Either we are not handling any mbx task and we are not
3625                  *    scheduled as well
3626                  *                        OR
3627                  * 2. We could be handling a mbx task but nothing more is
3628                  *    scheduled.
3629                  * In both cases, we should schedule mbx task as there are more
3630                  * mbx messages reported by this interrupt.
3631                  */
3632                 hclge_mbx_task_schedule(hdev);
3633                 break;
3634         default:
3635                 dev_warn(&hdev->pdev->dev,
3636                          "received unknown or unhandled event of vector0\n");
3637                 break;
3638         }
3639
3640         hclge_clear_event_cause(hdev, event_cause, clearval);
3641
3642         /* Enable interrupt if it is not caused by reset event or error event */
3643         if (event_cause == HCLGE_VECTOR0_EVENT_PTP ||
3644             event_cause == HCLGE_VECTOR0_EVENT_MBX ||
3645             event_cause == HCLGE_VECTOR0_EVENT_OTHER)
3646                 hclge_enable_vector(&hdev->misc_vector, true);
3647
3648         return IRQ_HANDLED;
3649 }
3650
3651 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
3652 {
3653         if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) {
3654                 dev_warn(&hdev->pdev->dev,
3655                          "vector(vector_id %d) has been freed.\n", vector_id);
3656                 return;
3657         }
3658
3659         hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
3660         hdev->num_msi_left += 1;
3661         hdev->num_msi_used -= 1;
3662 }
3663
3664 static void hclge_get_misc_vector(struct hclge_dev *hdev)
3665 {
3666         struct hclge_misc_vector *vector = &hdev->misc_vector;
3667
3668         vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
3669
3670         vector->addr = hdev->hw.hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
3671         hdev->vector_status[0] = 0;
3672
3673         hdev->num_msi_left -= 1;
3674         hdev->num_msi_used += 1;
3675 }
3676
3677 static int hclge_misc_irq_init(struct hclge_dev *hdev)
3678 {
3679         int ret;
3680
3681         hclge_get_misc_vector(hdev);
3682
3683         /* this would be explicitly freed in the end */
3684         snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s",
3685                  HCLGE_NAME, pci_name(hdev->pdev));
3686         ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
3687                           0, hdev->misc_vector.name, hdev);
3688         if (ret) {
3689                 hclge_free_vector(hdev, 0);
3690                 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
3691                         hdev->misc_vector.vector_irq);
3692         }
3693
3694         return ret;
3695 }
3696
3697 static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
3698 {
3699         free_irq(hdev->misc_vector.vector_irq, hdev);
3700         hclge_free_vector(hdev, 0);
3701 }
3702
3703 int hclge_notify_client(struct hclge_dev *hdev,
3704                         enum hnae3_reset_notify_type type)
3705 {
3706         struct hnae3_handle *handle = &hdev->vport[0].nic;
3707         struct hnae3_client *client = hdev->nic_client;
3708         int ret;
3709
3710         if (!test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state) || !client)
3711                 return 0;
3712
3713         if (!client->ops->reset_notify)
3714                 return -EOPNOTSUPP;
3715
3716         ret = client->ops->reset_notify(handle, type);
3717         if (ret)
3718                 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n",
3719                         type, ret);
3720
3721         return ret;
3722 }
3723
3724 static int hclge_notify_roce_client(struct hclge_dev *hdev,
3725                                     enum hnae3_reset_notify_type type)
3726 {
3727         struct hnae3_handle *handle = &hdev->vport[0].roce;
3728         struct hnae3_client *client = hdev->roce_client;
3729         int ret;
3730
3731         if (!test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state) || !client)
3732                 return 0;
3733
3734         if (!client->ops->reset_notify)
3735                 return -EOPNOTSUPP;
3736
3737         ret = client->ops->reset_notify(handle, type);
3738         if (ret)
3739                 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)",
3740                         type, ret);
3741
3742         return ret;
3743 }
3744
3745 static int hclge_reset_wait(struct hclge_dev *hdev)
3746 {
3747 #define HCLGE_RESET_WATI_MS     100
3748 #define HCLGE_RESET_WAIT_CNT    350
3749
3750         u32 val, reg, reg_bit;
3751         u32 cnt = 0;
3752
3753         switch (hdev->reset_type) {
3754         case HNAE3_IMP_RESET:
3755                 reg = HCLGE_GLOBAL_RESET_REG;
3756                 reg_bit = HCLGE_IMP_RESET_BIT;
3757                 break;
3758         case HNAE3_GLOBAL_RESET:
3759                 reg = HCLGE_GLOBAL_RESET_REG;
3760                 reg_bit = HCLGE_GLOBAL_RESET_BIT;
3761                 break;
3762         case HNAE3_FUNC_RESET:
3763                 reg = HCLGE_FUN_RST_ING;
3764                 reg_bit = HCLGE_FUN_RST_ING_B;
3765                 break;
3766         default:
3767                 dev_err(&hdev->pdev->dev,
3768                         "Wait for unsupported reset type: %d\n",
3769                         hdev->reset_type);
3770                 return -EINVAL;
3771         }
3772
3773         val = hclge_read_dev(&hdev->hw, reg);
3774         while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
3775                 msleep(HCLGE_RESET_WATI_MS);
3776                 val = hclge_read_dev(&hdev->hw, reg);
3777                 cnt++;
3778         }
3779
3780         if (cnt >= HCLGE_RESET_WAIT_CNT) {
3781                 dev_warn(&hdev->pdev->dev,
3782                          "Wait for reset timeout: %d\n", hdev->reset_type);
3783                 return -EBUSY;
3784         }
3785
3786         return 0;
3787 }
3788
3789 static int hclge_set_vf_rst(struct hclge_dev *hdev, int func_id, bool reset)
3790 {
3791         struct hclge_vf_rst_cmd *req;
3792         struct hclge_desc desc;
3793
3794         req = (struct hclge_vf_rst_cmd *)desc.data;
3795         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GBL_RST_STATUS, false);
3796         req->dest_vfid = func_id;
3797
3798         if (reset)
3799                 req->vf_rst = 0x1;
3800
3801         return hclge_cmd_send(&hdev->hw, &desc, 1);
3802 }
3803
3804 static int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset)
3805 {
3806         int i;
3807
3808         for (i = HCLGE_VF_VPORT_START_NUM; i < hdev->num_alloc_vport; i++) {
3809                 struct hclge_vport *vport = &hdev->vport[i];
3810                 int ret;
3811
3812                 /* Send cmd to set/clear VF's FUNC_RST_ING */
3813                 ret = hclge_set_vf_rst(hdev, vport->vport_id, reset);
3814                 if (ret) {
3815                         dev_err(&hdev->pdev->dev,
3816                                 "set vf(%u) rst failed %d!\n",
3817                                 vport->vport_id - HCLGE_VF_VPORT_START_NUM,
3818                                 ret);
3819                         return ret;
3820                 }
3821
3822                 if (!reset ||
3823                     !test_bit(HCLGE_VPORT_STATE_INITED, &vport->state))
3824                         continue;
3825
3826                 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) &&
3827                     hdev->reset_type == HNAE3_FUNC_RESET) {
3828                         set_bit(HCLGE_VPORT_NEED_NOTIFY_RESET,
3829                                 &vport->need_notify);
3830                         continue;
3831                 }
3832
3833                 /* Inform VF to process the reset.
3834                  * hclge_inform_reset_assert_to_vf may fail if VF
3835                  * driver is not loaded.
3836                  */
3837                 ret = hclge_inform_reset_assert_to_vf(vport);
3838                 if (ret)
3839                         dev_warn(&hdev->pdev->dev,
3840                                  "inform reset to vf(%u) failed %d!\n",
3841                                  vport->vport_id - HCLGE_VF_VPORT_START_NUM,
3842                                  ret);
3843         }
3844
3845         return 0;
3846 }
3847
3848 static void hclge_mailbox_service_task(struct hclge_dev *hdev)
3849 {
3850         if (!test_and_clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state) ||
3851             test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state) ||
3852             test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
3853                 return;
3854
3855         if (time_is_before_jiffies(hdev->last_mbx_scheduled +
3856                                    HCLGE_MBX_SCHED_TIMEOUT))
3857                 dev_warn(&hdev->pdev->dev,
3858                          "mbx service task is scheduled after %ums on cpu%u!\n",
3859                          jiffies_to_msecs(jiffies - hdev->last_mbx_scheduled),
3860                          smp_processor_id());
3861
3862         hclge_mbx_handler(hdev);
3863
3864         clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
3865 }
3866
3867 static void hclge_func_reset_sync_vf(struct hclge_dev *hdev)
3868 {
3869         struct hclge_pf_rst_sync_cmd *req;
3870         struct hclge_desc desc;
3871         int cnt = 0;
3872         int ret;
3873
3874         req = (struct hclge_pf_rst_sync_cmd *)desc.data;
3875         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RST_RDY, true);
3876
3877         do {
3878                 /* vf need to down netdev by mbx during PF or FLR reset */
3879                 hclge_mailbox_service_task(hdev);
3880
3881                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3882                 /* for compatible with old firmware, wait
3883                  * 100 ms for VF to stop IO
3884                  */
3885                 if (ret == -EOPNOTSUPP) {
3886                         msleep(HCLGE_RESET_SYNC_TIME);
3887                         return;
3888                 } else if (ret) {
3889                         dev_warn(&hdev->pdev->dev, "sync with VF fail %d!\n",
3890                                  ret);
3891                         return;
3892                 } else if (req->all_vf_ready) {
3893                         return;
3894                 }
3895                 msleep(HCLGE_PF_RESET_SYNC_TIME);
3896                 hclge_comm_cmd_reuse_desc(&desc, true);
3897         } while (cnt++ < HCLGE_PF_RESET_SYNC_CNT);
3898
3899         dev_warn(&hdev->pdev->dev, "sync with VF timeout!\n");
3900 }
3901
3902 void hclge_report_hw_error(struct hclge_dev *hdev,
3903                            enum hnae3_hw_error_type type)
3904 {
3905         struct hnae3_client *client = hdev->nic_client;
3906
3907         if (!client || !client->ops->process_hw_error ||
3908             !test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state))
3909                 return;
3910
3911         client->ops->process_hw_error(&hdev->vport[0].nic, type);
3912 }
3913
3914 static void hclge_handle_imp_error(struct hclge_dev *hdev)
3915 {
3916         u32 reg_val;
3917
3918         reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);
3919         if (reg_val & BIT(HCLGE_VECTOR0_IMP_RD_POISON_B)) {
3920                 hclge_report_hw_error(hdev, HNAE3_IMP_RD_POISON_ERROR);
3921                 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_RD_POISON_B);
3922                 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val);
3923         }
3924
3925         if (reg_val & BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B)) {
3926                 hclge_report_hw_error(hdev, HNAE3_CMDQ_ECC_ERROR);
3927                 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B);
3928                 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val);
3929         }
3930 }
3931
3932 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
3933 {
3934         struct hclge_desc desc;
3935         struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
3936         int ret;
3937
3938         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
3939         hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
3940         req->fun_reset_vfid = func_id;
3941
3942         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3943         if (ret)
3944                 dev_err(&hdev->pdev->dev,
3945                         "send function reset cmd fail, status =%d\n", ret);
3946
3947         return ret;
3948 }
3949
3950 static void hclge_do_reset(struct hclge_dev *hdev)
3951 {
3952         struct hnae3_handle *handle = &hdev->vport[0].nic;
3953         struct pci_dev *pdev = hdev->pdev;
3954         u32 val;
3955
3956         if (hclge_get_hw_reset_stat(handle)) {
3957                 dev_info(&pdev->dev, "hardware reset not finish\n");
3958                 dev_info(&pdev->dev, "func_rst_reg:0x%x, global_rst_reg:0x%x\n",
3959                          hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING),
3960                          hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG));
3961                 return;
3962         }
3963
3964         switch (hdev->reset_type) {
3965         case HNAE3_IMP_RESET:
3966                 dev_info(&pdev->dev, "IMP reset requested\n");
3967                 val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);
3968                 hnae3_set_bit(val, HCLGE_TRIGGER_IMP_RESET_B, 1);
3969                 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, val);
3970                 break;
3971         case HNAE3_GLOBAL_RESET:
3972                 dev_info(&pdev->dev, "global reset requested\n");
3973                 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
3974                 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
3975                 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
3976                 break;
3977         case HNAE3_FUNC_RESET:
3978                 dev_info(&pdev->dev, "PF reset requested\n");
3979                 /* schedule again to check later */
3980                 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
3981                 hclge_reset_task_schedule(hdev);
3982                 break;
3983         default:
3984                 dev_warn(&pdev->dev,
3985                          "unsupported reset type: %d\n", hdev->reset_type);
3986                 break;
3987         }
3988 }
3989
3990 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev,
3991                                                    unsigned long *addr)
3992 {
3993         enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
3994         struct hclge_dev *hdev = ae_dev->priv;
3995
3996         /* return the highest priority reset level amongst all */
3997         if (test_bit(HNAE3_IMP_RESET, addr)) {
3998                 rst_level = HNAE3_IMP_RESET;
3999                 clear_bit(HNAE3_IMP_RESET, addr);
4000                 clear_bit(HNAE3_GLOBAL_RESET, addr);
4001                 clear_bit(HNAE3_FUNC_RESET, addr);
4002         } else if (test_bit(HNAE3_GLOBAL_RESET, addr)) {
4003                 rst_level = HNAE3_GLOBAL_RESET;
4004                 clear_bit(HNAE3_GLOBAL_RESET, addr);
4005                 clear_bit(HNAE3_FUNC_RESET, addr);
4006         } else if (test_bit(HNAE3_FUNC_RESET, addr)) {
4007                 rst_level = HNAE3_FUNC_RESET;
4008                 clear_bit(HNAE3_FUNC_RESET, addr);
4009         } else if (test_bit(HNAE3_FLR_RESET, addr)) {
4010                 rst_level = HNAE3_FLR_RESET;
4011                 clear_bit(HNAE3_FLR_RESET, addr);
4012         }
4013
4014         if (hdev->reset_type != HNAE3_NONE_RESET &&
4015             rst_level < hdev->reset_type)
4016                 return HNAE3_NONE_RESET;
4017
4018         return rst_level;
4019 }
4020
4021 static void hclge_clear_reset_cause(struct hclge_dev *hdev)
4022 {
4023         u32 clearval = 0;
4024
4025         switch (hdev->reset_type) {
4026         case HNAE3_IMP_RESET:
4027                 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
4028                 break;
4029         case HNAE3_GLOBAL_RESET:
4030                 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
4031                 break;
4032         default:
4033                 break;
4034         }
4035
4036         if (!clearval)
4037                 return;
4038
4039         /* For revision 0x20, the reset interrupt source
4040          * can only be cleared after hardware reset done
4041          */
4042         if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
4043                 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG,
4044                                 clearval);
4045
4046         hclge_enable_vector(&hdev->misc_vector, true);
4047 }
4048
4049 static void hclge_reset_handshake(struct hclge_dev *hdev, bool enable)
4050 {
4051         u32 reg_val;
4052
4053         reg_val = hclge_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG);
4054         if (enable)
4055                 reg_val |= HCLGE_COMM_NIC_SW_RST_RDY;
4056         else
4057                 reg_val &= ~HCLGE_COMM_NIC_SW_RST_RDY;
4058
4059         hclge_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, reg_val);
4060 }
4061
4062 static int hclge_func_reset_notify_vf(struct hclge_dev *hdev)
4063 {
4064         int ret;
4065
4066         ret = hclge_set_all_vf_rst(hdev, true);
4067         if (ret)
4068                 return ret;
4069
4070         hclge_func_reset_sync_vf(hdev);
4071
4072         return 0;
4073 }
4074
4075 static int hclge_reset_prepare_wait(struct hclge_dev *hdev)
4076 {
4077         u32 reg_val;
4078         int ret = 0;
4079
4080         switch (hdev->reset_type) {
4081         case HNAE3_FUNC_RESET:
4082                 ret = hclge_func_reset_notify_vf(hdev);
4083                 if (ret)
4084                         return ret;
4085
4086                 ret = hclge_func_reset_cmd(hdev, 0);
4087                 if (ret) {
4088                         dev_err(&hdev->pdev->dev,
4089                                 "asserting function reset fail %d!\n", ret);
4090                         return ret;
4091                 }
4092
4093                 /* After performaning pf reset, it is not necessary to do the
4094                  * mailbox handling or send any command to firmware, because
4095                  * any mailbox handling or command to firmware is only valid
4096                  * after hclge_comm_cmd_init is called.
4097                  */
4098                 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
4099                 hdev->rst_stats.pf_rst_cnt++;
4100                 break;
4101         case HNAE3_FLR_RESET:
4102                 ret = hclge_func_reset_notify_vf(hdev);
4103                 if (ret)
4104                         return ret;
4105                 break;
4106         case HNAE3_IMP_RESET:
4107                 hclge_handle_imp_error(hdev);
4108                 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);
4109                 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG,
4110                                 BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val);
4111                 break;
4112         default:
4113                 break;
4114         }
4115
4116         /* inform hardware that preparatory work is done */
4117         msleep(HCLGE_RESET_SYNC_TIME);
4118         hclge_reset_handshake(hdev, true);
4119         dev_info(&hdev->pdev->dev, "prepare wait ok\n");
4120
4121         return ret;
4122 }
4123
4124 static void hclge_show_rst_info(struct hclge_dev *hdev)
4125 {
4126         char *buf;
4127
4128         buf = kzalloc(HCLGE_DBG_RESET_INFO_LEN, GFP_KERNEL);
4129         if (!buf)
4130                 return;
4131
4132         hclge_dbg_dump_rst_info(hdev, buf, HCLGE_DBG_RESET_INFO_LEN);
4133
4134         dev_info(&hdev->pdev->dev, "dump reset info:\n%s", buf);
4135
4136         kfree(buf);
4137 }
4138
4139 static bool hclge_reset_err_handle(struct hclge_dev *hdev)
4140 {
4141 #define MAX_RESET_FAIL_CNT 5
4142
4143         if (hdev->reset_pending) {
4144                 dev_info(&hdev->pdev->dev, "Reset pending %lu\n",
4145                          hdev->reset_pending);
4146                 return true;
4147         } else if (hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) &
4148                    HCLGE_RESET_INT_M) {
4149                 dev_info(&hdev->pdev->dev,
4150                          "reset failed because new reset interrupt\n");
4151                 hclge_clear_reset_cause(hdev);
4152                 return false;
4153         } else if (hdev->rst_stats.reset_fail_cnt < MAX_RESET_FAIL_CNT) {
4154                 hdev->rst_stats.reset_fail_cnt++;
4155                 set_bit(hdev->reset_type, &hdev->reset_pending);
4156                 dev_info(&hdev->pdev->dev,
4157                          "re-schedule reset task(%u)\n",
4158                          hdev->rst_stats.reset_fail_cnt);
4159                 return true;
4160         }
4161
4162         hclge_clear_reset_cause(hdev);
4163
4164         /* recover the handshake status when reset fail */
4165         hclge_reset_handshake(hdev, true);
4166
4167         dev_err(&hdev->pdev->dev, "Reset fail!\n");
4168
4169         hclge_show_rst_info(hdev);
4170
4171         set_bit(HCLGE_STATE_RST_FAIL, &hdev->state);
4172
4173         return false;
4174 }
4175
4176 static void hclge_update_reset_level(struct hclge_dev *hdev)
4177 {
4178         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
4179         enum hnae3_reset_type reset_level;
4180
4181         /* reset request will not be set during reset, so clear
4182          * pending reset request to avoid unnecessary reset
4183          * caused by the same reason.
4184          */
4185         hclge_get_reset_level(ae_dev, &hdev->reset_request);
4186
4187         /* if default_reset_request has a higher level reset request,
4188          * it should be handled as soon as possible. since some errors
4189          * need this kind of reset to fix.
4190          */
4191         reset_level = hclge_get_reset_level(ae_dev,
4192                                             &hdev->default_reset_request);
4193         if (reset_level != HNAE3_NONE_RESET)
4194                 set_bit(reset_level, &hdev->reset_request);
4195 }
4196
4197 static int hclge_set_rst_done(struct hclge_dev *hdev)
4198 {
4199         struct hclge_pf_rst_done_cmd *req;
4200         struct hclge_desc desc;
4201         int ret;
4202
4203         req = (struct hclge_pf_rst_done_cmd *)desc.data;
4204         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PF_RST_DONE, false);
4205         req->pf_rst_done |= HCLGE_PF_RESET_DONE_BIT;
4206
4207         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4208         /* To be compatible with the old firmware, which does not support
4209          * command HCLGE_OPC_PF_RST_DONE, just print a warning and
4210          * return success
4211          */
4212         if (ret == -EOPNOTSUPP) {
4213                 dev_warn(&hdev->pdev->dev,
4214                          "current firmware does not support command(0x%x)!\n",
4215                          HCLGE_OPC_PF_RST_DONE);
4216                 return 0;
4217         } else if (ret) {
4218                 dev_err(&hdev->pdev->dev, "assert PF reset done fail %d!\n",
4219                         ret);
4220         }
4221
4222         return ret;
4223 }
4224
4225 static int hclge_reset_prepare_up(struct hclge_dev *hdev)
4226 {
4227         int ret = 0;
4228
4229         switch (hdev->reset_type) {
4230         case HNAE3_FUNC_RESET:
4231         case HNAE3_FLR_RESET:
4232                 ret = hclge_set_all_vf_rst(hdev, false);
4233                 break;
4234         case HNAE3_GLOBAL_RESET:
4235         case HNAE3_IMP_RESET:
4236                 ret = hclge_set_rst_done(hdev);
4237                 break;
4238         default:
4239                 break;
4240         }
4241
4242         /* clear up the handshake status after re-initialize done */
4243         hclge_reset_handshake(hdev, false);
4244
4245         return ret;
4246 }
4247
4248 static int hclge_reset_stack(struct hclge_dev *hdev)
4249 {
4250         int ret;
4251
4252         ret = hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
4253         if (ret)
4254                 return ret;
4255
4256         ret = hclge_reset_ae_dev(hdev->ae_dev);
4257         if (ret)
4258                 return ret;
4259
4260         return hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
4261 }
4262
4263 static int hclge_reset_prepare(struct hclge_dev *hdev)
4264 {
4265         int ret;
4266
4267         hdev->rst_stats.reset_cnt++;
4268         /* perform reset of the stack & ae device for a client */
4269         ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT);
4270         if (ret)
4271                 return ret;
4272
4273         rtnl_lock();
4274         ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
4275         rtnl_unlock();
4276         if (ret)
4277                 return ret;
4278
4279         return hclge_reset_prepare_wait(hdev);
4280 }
4281
4282 static int hclge_reset_rebuild(struct hclge_dev *hdev)
4283 {
4284         int ret;
4285
4286         hdev->rst_stats.hw_reset_done_cnt++;
4287
4288         ret = hclge_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT);
4289         if (ret)
4290                 return ret;
4291
4292         rtnl_lock();
4293         ret = hclge_reset_stack(hdev);
4294         rtnl_unlock();
4295         if (ret)
4296                 return ret;
4297
4298         hclge_clear_reset_cause(hdev);
4299
4300         ret = hclge_notify_roce_client(hdev, HNAE3_INIT_CLIENT);
4301         /* ignore RoCE notify error if it fails HCLGE_RESET_MAX_FAIL_CNT - 1
4302          * times
4303          */
4304         if (ret &&
4305             hdev->rst_stats.reset_fail_cnt < HCLGE_RESET_MAX_FAIL_CNT - 1)
4306                 return ret;
4307
4308         ret = hclge_reset_prepare_up(hdev);
4309         if (ret)
4310                 return ret;
4311
4312         rtnl_lock();
4313         ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT);
4314         rtnl_unlock();
4315         if (ret)
4316                 return ret;
4317
4318         ret = hclge_notify_roce_client(hdev, HNAE3_UP_CLIENT);
4319         if (ret)
4320                 return ret;
4321
4322         hdev->last_reset_time = jiffies;
4323         hdev->rst_stats.reset_fail_cnt = 0;
4324         hdev->rst_stats.reset_done_cnt++;
4325         clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state);
4326
4327         hclge_update_reset_level(hdev);
4328
4329         return 0;
4330 }
4331
4332 static void hclge_reset(struct hclge_dev *hdev)
4333 {
4334         if (hclge_reset_prepare(hdev))
4335                 goto err_reset;
4336
4337         if (hclge_reset_wait(hdev))
4338                 goto err_reset;
4339
4340         if (hclge_reset_rebuild(hdev))
4341                 goto err_reset;
4342
4343         return;
4344
4345 err_reset:
4346         if (hclge_reset_err_handle(hdev))
4347                 hclge_reset_task_schedule(hdev);
4348 }
4349
4350 static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle)
4351 {
4352         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
4353         struct hclge_dev *hdev = ae_dev->priv;
4354
4355         /* We might end up getting called broadly because of 2 below cases:
4356          * 1. Recoverable error was conveyed through APEI and only way to bring
4357          *    normalcy is to reset.
4358          * 2. A new reset request from the stack due to timeout
4359          *
4360          * check if this is a new reset request and we are not here just because
4361          * last reset attempt did not succeed and watchdog hit us again. We will
4362          * know this if last reset request did not occur very recently (watchdog
4363          * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
4364          * In case of new request we reset the "reset level" to PF reset.
4365          * And if it is a repeat reset request of the most recent one then we
4366          * want to make sure we throttle the reset request. Therefore, we will
4367          * not allow it again before 3*HZ times.
4368          */
4369
4370         if (time_before(jiffies, (hdev->last_reset_time +
4371                                   HCLGE_RESET_INTERVAL))) {
4372                 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL);
4373                 return;
4374         }
4375
4376         if (hdev->default_reset_request) {
4377                 hdev->reset_level =
4378                         hclge_get_reset_level(ae_dev,
4379                                               &hdev->default_reset_request);
4380         } else if (time_after(jiffies, (hdev->last_reset_time + 4 * 5 * HZ))) {
4381                 hdev->reset_level = HNAE3_FUNC_RESET;
4382         }
4383
4384         dev_info(&hdev->pdev->dev, "received reset event, reset type is %d\n",
4385                  hdev->reset_level);
4386
4387         /* request reset & schedule reset task */
4388         set_bit(hdev->reset_level, &hdev->reset_request);
4389         hclge_reset_task_schedule(hdev);
4390
4391         if (hdev->reset_level < HNAE3_GLOBAL_RESET)
4392                 hdev->reset_level++;
4393 }
4394
4395 static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
4396                                         enum hnae3_reset_type rst_type)
4397 {
4398         struct hclge_dev *hdev = ae_dev->priv;
4399
4400         set_bit(rst_type, &hdev->default_reset_request);
4401 }
4402
4403 static void hclge_reset_timer(struct timer_list *t)
4404 {
4405         struct hclge_dev *hdev = from_timer(hdev, t, reset_timer);
4406
4407         /* if default_reset_request has no value, it means that this reset
4408          * request has already be handled, so just return here
4409          */
4410         if (!hdev->default_reset_request)
4411                 return;
4412
4413         dev_info(&hdev->pdev->dev,
4414                  "triggering reset in reset timer\n");
4415         hclge_reset_event(hdev->pdev, NULL);
4416 }
4417
4418 static void hclge_reset_subtask(struct hclge_dev *hdev)
4419 {
4420         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
4421
4422         /* check if there is any ongoing reset in the hardware. This status can
4423          * be checked from reset_pending. If there is then, we need to wait for
4424          * hardware to complete reset.
4425          *    a. If we are able to figure out in reasonable time that hardware
4426          *       has fully resetted then, we can proceed with driver, client
4427          *       reset.
4428          *    b. else, we can come back later to check this status so re-sched
4429          *       now.
4430          */
4431         hdev->last_reset_time = jiffies;
4432         hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_pending);
4433         if (hdev->reset_type != HNAE3_NONE_RESET)
4434                 hclge_reset(hdev);
4435
4436         /* check if we got any *new* reset requests to be honored */
4437         hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_request);
4438         if (hdev->reset_type != HNAE3_NONE_RESET)
4439                 hclge_do_reset(hdev);
4440
4441         hdev->reset_type = HNAE3_NONE_RESET;
4442 }
4443
4444 static void hclge_handle_err_reset_request(struct hclge_dev *hdev)
4445 {
4446         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
4447         enum hnae3_reset_type reset_type;
4448
4449         if (ae_dev->hw_err_reset_req) {
4450                 reset_type = hclge_get_reset_level(ae_dev,
4451                                                    &ae_dev->hw_err_reset_req);
4452                 hclge_set_def_reset_request(ae_dev, reset_type);
4453         }
4454
4455         if (hdev->default_reset_request && ae_dev->ops->reset_event)
4456                 ae_dev->ops->reset_event(hdev->pdev, NULL);
4457
4458         /* enable interrupt after error handling complete */
4459         hclge_enable_vector(&hdev->misc_vector, true);
4460 }
4461
4462 static void hclge_handle_err_recovery(struct hclge_dev *hdev)
4463 {
4464         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
4465
4466         ae_dev->hw_err_reset_req = 0;
4467
4468         if (hclge_find_error_source(hdev)) {
4469                 hclge_handle_error_info_log(ae_dev);
4470                 hclge_handle_mac_tnl(hdev);
4471         }
4472
4473         hclge_handle_err_reset_request(hdev);
4474 }
4475
4476 static void hclge_misc_err_recovery(struct hclge_dev *hdev)
4477 {
4478         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
4479         struct device *dev = &hdev->pdev->dev;
4480         u32 msix_sts_reg;
4481
4482         msix_sts_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
4483         if (msix_sts_reg & HCLGE_VECTOR0_REG_MSIX_MASK) {
4484                 if (hclge_handle_hw_msix_error
4485                                 (hdev, &hdev->default_reset_request))
4486                         dev_info(dev, "received msix interrupt 0x%x\n",
4487                                  msix_sts_reg);
4488         }
4489
4490         hclge_handle_hw_ras_error(ae_dev);
4491
4492         hclge_handle_err_reset_request(hdev);
4493 }
4494
4495 static void hclge_errhand_service_task(struct hclge_dev *hdev)
4496 {
4497         if (!test_and_clear_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state))
4498                 return;
4499
4500         if (hnae3_dev_ras_imp_supported(hdev))
4501                 hclge_handle_err_recovery(hdev);
4502         else
4503                 hclge_misc_err_recovery(hdev);
4504 }
4505
4506 static void hclge_reset_service_task(struct hclge_dev *hdev)
4507 {
4508         if (!test_and_clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
4509                 return;
4510
4511         if (time_is_before_jiffies(hdev->last_rst_scheduled +
4512                                    HCLGE_RESET_SCHED_TIMEOUT))
4513                 dev_warn(&hdev->pdev->dev,
4514                          "reset service task is scheduled after %ums on cpu%u!\n",
4515                          jiffies_to_msecs(jiffies - hdev->last_rst_scheduled),
4516                          smp_processor_id());
4517
4518         down(&hdev->reset_sem);
4519         set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
4520
4521         hclge_reset_subtask(hdev);
4522
4523         clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
4524         up(&hdev->reset_sem);
4525 }
4526
4527 static void hclge_update_vport_alive(struct hclge_dev *hdev)
4528 {
4529 #define HCLGE_ALIVE_SECONDS_NORMAL              8
4530
4531         unsigned long alive_time = HCLGE_ALIVE_SECONDS_NORMAL * HZ;
4532         int i;
4533
4534         /* start from vport 1 for PF is always alive */
4535         for (i = 1; i < hdev->num_alloc_vport; i++) {
4536                 struct hclge_vport *vport = &hdev->vport[i];
4537
4538                 if (!test_bit(HCLGE_VPORT_STATE_INITED, &vport->state) ||
4539                     !test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state))
4540                         continue;
4541                 if (time_after(jiffies, vport->last_active_jiffies +
4542                                alive_time)) {
4543                         clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
4544                         dev_warn(&hdev->pdev->dev,
4545                                  "VF %u heartbeat timeout\n",
4546                                  i - HCLGE_VF_VPORT_START_NUM);
4547                 }
4548         }
4549 }
4550
4551 static void hclge_periodic_service_task(struct hclge_dev *hdev)
4552 {
4553         unsigned long delta = round_jiffies_relative(HZ);
4554
4555         if (test_bit(HCLGE_STATE_RST_FAIL, &hdev->state))
4556                 return;
4557
4558         /* Always handle the link updating to make sure link state is
4559          * updated when it is triggered by mbx.
4560          */
4561         hclge_update_link_status(hdev);
4562         hclge_sync_mac_table(hdev);
4563         hclge_sync_promisc_mode(hdev);
4564         hclge_sync_fd_table(hdev);
4565
4566         if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) {
4567                 delta = jiffies - hdev->last_serv_processed;
4568
4569                 if (delta < round_jiffies_relative(HZ)) {
4570                         delta = round_jiffies_relative(HZ) - delta;
4571                         goto out;
4572                 }
4573         }
4574
4575         hdev->serv_processed_cnt++;
4576         hclge_update_vport_alive(hdev);
4577
4578         if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) {
4579                 hdev->last_serv_processed = jiffies;
4580                 goto out;
4581         }
4582
4583         if (!(hdev->serv_processed_cnt % HCLGE_STATS_TIMER_INTERVAL))
4584                 hclge_update_stats_for_all(hdev);
4585
4586         hclge_update_port_info(hdev);
4587         hclge_sync_vlan_filter(hdev);
4588
4589         if (!(hdev->serv_processed_cnt % HCLGE_ARFS_EXPIRE_INTERVAL))
4590                 hclge_rfs_filter_expire(hdev);
4591
4592         hdev->last_serv_processed = jiffies;
4593
4594 out:
4595         hclge_task_schedule(hdev, delta);
4596 }
4597
4598 static void hclge_ptp_service_task(struct hclge_dev *hdev)
4599 {
4600         unsigned long flags;
4601
4602         if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state) ||
4603             !test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state) ||
4604             !time_is_before_jiffies(hdev->ptp->tx_start + HZ))
4605                 return;
4606
4607         /* to prevent concurrence with the irq handler */
4608         spin_lock_irqsave(&hdev->ptp->lock, flags);
4609
4610         /* check HCLGE_STATE_PTP_TX_HANDLING here again, since the irq
4611          * handler may handle it just before spin_lock_irqsave().
4612          */
4613         if (test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state))
4614                 hclge_ptp_clean_tx_hwts(hdev);
4615
4616         spin_unlock_irqrestore(&hdev->ptp->lock, flags);
4617 }
4618
4619 static void hclge_service_task(struct work_struct *work)
4620 {
4621         struct hclge_dev *hdev =
4622                 container_of(work, struct hclge_dev, service_task.work);
4623
4624         hclge_errhand_service_task(hdev);
4625         hclge_reset_service_task(hdev);
4626         hclge_ptp_service_task(hdev);
4627         hclge_mailbox_service_task(hdev);
4628         hclge_periodic_service_task(hdev);
4629
4630         /* Handle error recovery, reset and mbx again in case periodical task
4631          * delays the handling by calling hclge_task_schedule() in
4632          * hclge_periodic_service_task().
4633          */
4634         hclge_errhand_service_task(hdev);
4635         hclge_reset_service_task(hdev);
4636         hclge_mailbox_service_task(hdev);
4637 }
4638
4639 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
4640 {
4641         /* VF handle has no client */
4642         if (!handle->client)
4643                 return container_of(handle, struct hclge_vport, nic);
4644         else if (handle->client->type == HNAE3_CLIENT_ROCE)
4645                 return container_of(handle, struct hclge_vport, roce);
4646         else
4647                 return container_of(handle, struct hclge_vport, nic);
4648 }
4649
4650 static void hclge_get_vector_info(struct hclge_dev *hdev, u16 idx,
4651                                   struct hnae3_vector_info *vector_info)
4652 {
4653 #define HCLGE_PF_MAX_VECTOR_NUM_DEV_V2  64
4654
4655         vector_info->vector = pci_irq_vector(hdev->pdev, idx);
4656
4657         /* need an extend offset to config vector >= 64 */
4658         if (idx - 1 < HCLGE_PF_MAX_VECTOR_NUM_DEV_V2)
4659                 vector_info->io_addr = hdev->hw.hw.io_base +
4660                                 HCLGE_VECTOR_REG_BASE +
4661                                 (idx - 1) * HCLGE_VECTOR_REG_OFFSET;
4662         else
4663                 vector_info->io_addr = hdev->hw.hw.io_base +
4664                                 HCLGE_VECTOR_EXT_REG_BASE +
4665                                 (idx - 1) / HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 *
4666                                 HCLGE_VECTOR_REG_OFFSET_H +
4667                                 (idx - 1) % HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 *
4668                                 HCLGE_VECTOR_REG_OFFSET;
4669
4670         hdev->vector_status[idx] = hdev->vport[0].vport_id;
4671         hdev->vector_irq[idx] = vector_info->vector;
4672 }
4673
4674 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
4675                             struct hnae3_vector_info *vector_info)
4676 {
4677         struct hclge_vport *vport = hclge_get_vport(handle);
4678         struct hnae3_vector_info *vector = vector_info;
4679         struct hclge_dev *hdev = vport->back;
4680         int alloc = 0;
4681         u16 i = 0;
4682         u16 j;
4683
4684         vector_num = min_t(u16, hdev->num_nic_msi - 1, vector_num);
4685         vector_num = min(hdev->num_msi_left, vector_num);
4686
4687         for (j = 0; j < vector_num; j++) {
4688                 while (++i < hdev->num_nic_msi) {
4689                         if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
4690                                 hclge_get_vector_info(hdev, i, vector);
4691                                 vector++;
4692                                 alloc++;
4693
4694                                 break;
4695                         }
4696                 }
4697         }
4698         hdev->num_msi_left -= alloc;
4699         hdev->num_msi_used += alloc;
4700
4701         return alloc;
4702 }
4703
4704 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
4705 {
4706         int i;
4707
4708         for (i = 0; i < hdev->num_msi; i++)
4709                 if (vector == hdev->vector_irq[i])
4710                         return i;
4711
4712         return -EINVAL;
4713 }
4714
4715 static int hclge_put_vector(struct hnae3_handle *handle, int vector)
4716 {
4717         struct hclge_vport *vport = hclge_get_vport(handle);
4718         struct hclge_dev *hdev = vport->back;
4719         int vector_id;
4720
4721         vector_id = hclge_get_vector_index(hdev, vector);
4722         if (vector_id < 0) {
4723                 dev_err(&hdev->pdev->dev,
4724                         "Get vector index fail. vector = %d\n", vector);
4725                 return vector_id;
4726         }
4727
4728         hclge_free_vector(hdev, vector_id);
4729
4730         return 0;
4731 }
4732
4733 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
4734                          u8 *key, u8 *hfunc)
4735 {
4736         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
4737         struct hclge_vport *vport = hclge_get_vport(handle);
4738         struct hclge_comm_rss_cfg *rss_cfg = &vport->back->rss_cfg;
4739
4740         hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc);
4741
4742         hclge_comm_get_rss_indir_tbl(rss_cfg, indir,
4743                                      ae_dev->dev_specs.rss_ind_tbl_size);
4744
4745         return 0;
4746 }
4747
4748 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
4749                          const  u8 *key, const  u8 hfunc)
4750 {
4751         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
4752         struct hclge_vport *vport = hclge_get_vport(handle);
4753         struct hclge_dev *hdev = vport->back;
4754         struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg;
4755         int ret, i;
4756
4757         ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, hfunc);
4758         if (ret) {
4759                 dev_err(&hdev->pdev->dev, "invalid hfunc type %u\n", hfunc);
4760                 return ret;
4761         }
4762
4763         /* Update the shadow RSS table with user specified qids */
4764         for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++)
4765                 rss_cfg->rss_indirection_tbl[i] = indir[i];
4766
4767         /* Update the hardware */
4768         return hclge_comm_set_rss_indir_table(ae_dev, &hdev->hw.hw,
4769                                               rss_cfg->rss_indirection_tbl);
4770 }
4771
4772 static int hclge_set_rss_tuple(struct hnae3_handle *handle,
4773                                struct ethtool_rxnfc *nfc)
4774 {
4775         struct hclge_vport *vport = hclge_get_vport(handle);
4776         struct hclge_dev *hdev = vport->back;
4777         int ret;
4778
4779         ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw,
4780                                        &hdev->rss_cfg, nfc);
4781         if (ret) {
4782                 dev_err(&hdev->pdev->dev,
4783                         "failed to set rss tuple, ret = %d.\n", ret);
4784                 return ret;
4785         }
4786
4787         return 0;
4788 }
4789
4790 static int hclge_get_rss_tuple(struct hnae3_handle *handle,
4791                                struct ethtool_rxnfc *nfc)
4792 {
4793         struct hclge_vport *vport = hclge_get_vport(handle);
4794         u8 tuple_sets;
4795         int ret;
4796
4797         nfc->data = 0;
4798
4799         ret = hclge_comm_get_rss_tuple(&vport->back->rss_cfg, nfc->flow_type,
4800                                        &tuple_sets);
4801         if (ret || !tuple_sets)
4802                 return ret;
4803
4804         nfc->data = hclge_comm_convert_rss_tuple(tuple_sets);
4805
4806         return 0;
4807 }
4808
4809 static int hclge_get_tc_size(struct hnae3_handle *handle)
4810 {
4811         struct hclge_vport *vport = hclge_get_vport(handle);
4812         struct hclge_dev *hdev = vport->back;
4813
4814         return hdev->pf_rss_size_max;
4815 }
4816
4817 static int hclge_init_rss_tc_mode(struct hclge_dev *hdev)
4818 {
4819         struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
4820         struct hclge_vport *vport = hdev->vport;
4821         u16 tc_offset[HCLGE_MAX_TC_NUM] = {0};
4822         u16 tc_valid[HCLGE_MAX_TC_NUM] = {0};
4823         u16 tc_size[HCLGE_MAX_TC_NUM] = {0};
4824         struct hnae3_tc_info *tc_info;
4825         u16 roundup_size;
4826         u16 rss_size;
4827         int i;
4828
4829         tc_info = &vport->nic.kinfo.tc_info;
4830         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
4831                 rss_size = tc_info->tqp_count[i];
4832                 tc_valid[i] = 0;
4833
4834                 if (!(hdev->hw_tc_map & BIT(i)))
4835                         continue;
4836
4837                 /* tc_size set to hardware is the log2 of roundup power of two
4838                  * of rss_size, the acutal queue size is limited by indirection
4839                  * table.
4840                  */
4841                 if (rss_size > ae_dev->dev_specs.rss_ind_tbl_size ||
4842                     rss_size == 0) {
4843                         dev_err(&hdev->pdev->dev,
4844                                 "Configure rss tc size failed, invalid TC_SIZE = %u\n",
4845                                 rss_size);
4846                         return -EINVAL;
4847                 }
4848
4849                 roundup_size = roundup_pow_of_two(rss_size);
4850                 roundup_size = ilog2(roundup_size);
4851
4852                 tc_valid[i] = 1;
4853                 tc_size[i] = roundup_size;
4854                 tc_offset[i] = tc_info->tqp_offset[i];
4855         }
4856
4857         return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid,
4858                                           tc_size);
4859 }
4860
4861 int hclge_rss_init_hw(struct hclge_dev *hdev)
4862 {
4863         u16 *rss_indir = hdev->rss_cfg.rss_indirection_tbl;
4864         u8 *key = hdev->rss_cfg.rss_hash_key;
4865         u8 hfunc = hdev->rss_cfg.rss_algo;
4866         int ret;
4867
4868         ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw,
4869                                              rss_indir);
4870         if (ret)
4871                 return ret;
4872
4873         ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, hfunc, key);
4874         if (ret)
4875                 return ret;
4876
4877         ret = hclge_comm_set_rss_input_tuple(&hdev->hw.hw, &hdev->rss_cfg);
4878         if (ret)
4879                 return ret;
4880
4881         return hclge_init_rss_tc_mode(hdev);
4882 }
4883
4884 int hclge_bind_ring_with_vector(struct hclge_vport *vport,
4885                                 int vector_id, bool en,
4886                                 struct hnae3_ring_chain_node *ring_chain)
4887 {
4888         struct hclge_dev *hdev = vport->back;
4889         struct hnae3_ring_chain_node *node;
4890         struct hclge_desc desc;
4891         struct hclge_ctrl_vector_chain_cmd *req =
4892                 (struct hclge_ctrl_vector_chain_cmd *)desc.data;
4893         enum hclge_comm_cmd_status status;
4894         enum hclge_opcode_type op;
4895         u16 tqp_type_and_id;
4896         int i;
4897
4898         op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
4899         hclge_cmd_setup_basic_desc(&desc, op, false);
4900         req->int_vector_id_l = hnae3_get_field(vector_id,
4901                                                HCLGE_VECTOR_ID_L_M,
4902                                                HCLGE_VECTOR_ID_L_S);
4903         req->int_vector_id_h = hnae3_get_field(vector_id,
4904                                                HCLGE_VECTOR_ID_H_M,
4905                                                HCLGE_VECTOR_ID_H_S);
4906
4907         i = 0;
4908         for (node = ring_chain; node; node = node->next) {
4909                 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
4910                 hnae3_set_field(tqp_type_and_id,  HCLGE_INT_TYPE_M,
4911                                 HCLGE_INT_TYPE_S,
4912                                 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B));
4913                 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
4914                                 HCLGE_TQP_ID_S, node->tqp_index);
4915                 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
4916                                 HCLGE_INT_GL_IDX_S,
4917                                 hnae3_get_field(node->int_gl_idx,
4918                                                 HNAE3_RING_GL_IDX_M,
4919                                                 HNAE3_RING_GL_IDX_S));
4920                 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
4921                 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
4922                         req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
4923                         req->vfid = vport->vport_id;
4924
4925                         status = hclge_cmd_send(&hdev->hw, &desc, 1);
4926                         if (status) {
4927                                 dev_err(&hdev->pdev->dev,
4928                                         "Map TQP fail, status is %d.\n",
4929                                         status);
4930                                 return -EIO;
4931                         }
4932                         i = 0;
4933
4934                         hclge_cmd_setup_basic_desc(&desc,
4935                                                    op,
4936                                                    false);
4937                         req->int_vector_id_l =
4938                                 hnae3_get_field(vector_id,
4939                                                 HCLGE_VECTOR_ID_L_M,
4940                                                 HCLGE_VECTOR_ID_L_S);
4941                         req->int_vector_id_h =
4942                                 hnae3_get_field(vector_id,
4943                                                 HCLGE_VECTOR_ID_H_M,
4944                                                 HCLGE_VECTOR_ID_H_S);
4945                 }
4946         }
4947
4948         if (i > 0) {
4949                 req->int_cause_num = i;
4950                 req->vfid = vport->vport_id;
4951                 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4952                 if (status) {
4953                         dev_err(&hdev->pdev->dev,
4954                                 "Map TQP fail, status is %d.\n", status);
4955                         return -EIO;
4956                 }
4957         }
4958
4959         return 0;
4960 }
4961
4962 static int hclge_map_ring_to_vector(struct hnae3_handle *handle, int vector,
4963                                     struct hnae3_ring_chain_node *ring_chain)
4964 {
4965         struct hclge_vport *vport = hclge_get_vport(handle);
4966         struct hclge_dev *hdev = vport->back;
4967         int vector_id;
4968
4969         vector_id = hclge_get_vector_index(hdev, vector);
4970         if (vector_id < 0) {
4971                 dev_err(&hdev->pdev->dev,
4972                         "failed to get vector index. vector=%d\n", vector);
4973                 return vector_id;
4974         }
4975
4976         return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
4977 }
4978
4979 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, int vector,
4980                                        struct hnae3_ring_chain_node *ring_chain)
4981 {
4982         struct hclge_vport *vport = hclge_get_vport(handle);
4983         struct hclge_dev *hdev = vport->back;
4984         int vector_id, ret;
4985
4986         if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
4987                 return 0;
4988
4989         vector_id = hclge_get_vector_index(hdev, vector);
4990         if (vector_id < 0) {
4991                 dev_err(&handle->pdev->dev,
4992                         "Get vector index fail. ret =%d\n", vector_id);
4993                 return vector_id;
4994         }
4995
4996         ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
4997         if (ret)
4998                 dev_err(&handle->pdev->dev,
4999                         "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
5000                         vector_id, ret);
5001
5002         return ret;
5003 }
5004
5005 static int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, u8 vf_id,
5006                                       bool en_uc, bool en_mc, bool en_bc)
5007 {
5008         struct hclge_vport *vport = &hdev->vport[vf_id];
5009         struct hnae3_handle *handle = &vport->nic;
5010         struct hclge_promisc_cfg_cmd *req;
5011         struct hclge_desc desc;
5012         bool uc_tx_en = en_uc;
5013         u8 promisc_cfg = 0;
5014         int ret;
5015
5016         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
5017
5018         req = (struct hclge_promisc_cfg_cmd *)desc.data;
5019         req->vf_id = vf_id;
5020
5021         if (test_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->priv_flags))
5022                 uc_tx_en = false;
5023
5024         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_RX_EN, en_uc ? 1 : 0);
5025         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_RX_EN, en_mc ? 1 : 0);
5026         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_RX_EN, en_bc ? 1 : 0);
5027         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_TX_EN, uc_tx_en ? 1 : 0);
5028         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_TX_EN, en_mc ? 1 : 0);
5029         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_TX_EN, en_bc ? 1 : 0);
5030         req->extend_promisc = promisc_cfg;
5031
5032         /* to be compatible with DEVICE_VERSION_V1/2 */
5033         promisc_cfg = 0;
5034         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_UC, en_uc ? 1 : 0);
5035         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_MC, en_mc ? 1 : 0);
5036         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_BC, en_bc ? 1 : 0);
5037         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_TX_EN, 1);
5038         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_RX_EN, 1);
5039         req->promisc = promisc_cfg;
5040
5041         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5042         if (ret)
5043                 dev_err(&hdev->pdev->dev,
5044                         "failed to set vport %u promisc mode, ret = %d.\n",
5045                         vf_id, ret);
5046
5047         return ret;
5048 }
5049
5050 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc,
5051                                  bool en_mc_pmc, bool en_bc_pmc)
5052 {
5053         return hclge_cmd_set_promisc_mode(vport->back, vport->vport_id,
5054                                           en_uc_pmc, en_mc_pmc, en_bc_pmc);
5055 }
5056
5057 static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
5058                                   bool en_mc_pmc)
5059 {
5060         struct hclge_vport *vport = hclge_get_vport(handle);
5061         struct hclge_dev *hdev = vport->back;
5062         bool en_bc_pmc = true;
5063
5064         /* For device whose version below V2, if broadcast promisc enabled,
5065          * vlan filter is always bypassed. So broadcast promisc should be
5066          * disabled until user enable promisc mode
5067          */
5068         if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
5069                 en_bc_pmc = handle->netdev_flags & HNAE3_BPE ? true : false;
5070
5071         return hclge_set_vport_promisc_mode(vport, en_uc_pmc, en_mc_pmc,
5072                                             en_bc_pmc);
5073 }
5074
5075 static void hclge_request_update_promisc_mode(struct hnae3_handle *handle)
5076 {
5077         struct hclge_vport *vport = hclge_get_vport(handle);
5078
5079         set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
5080 }
5081
5082 static void hclge_sync_fd_state(struct hclge_dev *hdev)
5083 {
5084         if (hlist_empty(&hdev->fd_rule_list))
5085                 hdev->fd_active_type = HCLGE_FD_RULE_NONE;
5086 }
5087
5088 static void hclge_fd_inc_rule_cnt(struct hclge_dev *hdev, u16 location)
5089 {
5090         if (!test_bit(location, hdev->fd_bmap)) {
5091                 set_bit(location, hdev->fd_bmap);
5092                 hdev->hclge_fd_rule_num++;
5093         }
5094 }
5095
5096 static void hclge_fd_dec_rule_cnt(struct hclge_dev *hdev, u16 location)
5097 {
5098         if (test_bit(location, hdev->fd_bmap)) {
5099                 clear_bit(location, hdev->fd_bmap);
5100                 hdev->hclge_fd_rule_num--;
5101         }
5102 }
5103
5104 static void hclge_fd_free_node(struct hclge_dev *hdev,
5105                                struct hclge_fd_rule *rule)
5106 {
5107         hlist_del(&rule->rule_node);
5108         kfree(rule);
5109         hclge_sync_fd_state(hdev);
5110 }
5111
5112 static void hclge_update_fd_rule_node(struct hclge_dev *hdev,
5113                                       struct hclge_fd_rule *old_rule,
5114                                       struct hclge_fd_rule *new_rule,
5115                                       enum HCLGE_FD_NODE_STATE state)
5116 {
5117         switch (state) {
5118         case HCLGE_FD_TO_ADD:
5119         case HCLGE_FD_ACTIVE:
5120                 /* 1) if the new state is TO_ADD, just replace the old rule
5121                  * with the same location, no matter its state, because the
5122                  * new rule will be configured to the hardware.
5123                  * 2) if the new state is ACTIVE, it means the new rule
5124                  * has been configured to the hardware, so just replace
5125                  * the old rule node with the same location.
5126                  * 3) for it doesn't add a new node to the list, so it's
5127                  * unnecessary to update the rule number and fd_bmap.
5128                  */
5129                 new_rule->rule_node.next = old_rule->rule_node.next;
5130                 new_rule->rule_node.pprev = old_rule->rule_node.pprev;
5131                 memcpy(old_rule, new_rule, sizeof(*old_rule));
5132                 kfree(new_rule);
5133                 break;
5134         case HCLGE_FD_DELETED:
5135                 hclge_fd_dec_rule_cnt(hdev, old_rule->location);
5136                 hclge_fd_free_node(hdev, old_rule);
5137                 break;
5138         case HCLGE_FD_TO_DEL:
5139                 /* if new request is TO_DEL, and old rule is existent
5140                  * 1) the state of old rule is TO_DEL, we need do nothing,
5141                  * because we delete rule by location, other rule content
5142                  * is unncessary.
5143                  * 2) the state of old rule is ACTIVE, we need to change its
5144                  * state to TO_DEL, so the rule will be deleted when periodic
5145                  * task being scheduled.
5146                  * 3) the state of old rule is TO_ADD, it means the rule hasn't
5147                  * been added to hardware, so we just delete the rule node from
5148                  * fd_rule_list directly.
5149                  */
5150                 if (old_rule->state == HCLGE_FD_TO_ADD) {
5151                         hclge_fd_dec_rule_cnt(hdev, old_rule->location);
5152                         hclge_fd_free_node(hdev, old_rule);
5153                         return;
5154                 }
5155                 old_rule->state = HCLGE_FD_TO_DEL;
5156                 break;
5157         }
5158 }
5159
5160 static struct hclge_fd_rule *hclge_find_fd_rule(struct hlist_head *hlist,
5161                                                 u16 location,
5162                                                 struct hclge_fd_rule **parent)
5163 {
5164         struct hclge_fd_rule *rule;
5165         struct hlist_node *node;
5166
5167         hlist_for_each_entry_safe(rule, node, hlist, rule_node) {
5168                 if (rule->location == location)
5169                         return rule;
5170                 else if (rule->location > location)
5171                         return NULL;
5172                 /* record the parent node, use to keep the nodes in fd_rule_list
5173                  * in ascend order.
5174                  */
5175                 *parent = rule;
5176         }
5177
5178         return NULL;
5179 }
5180
5181 /* insert fd rule node in ascend order according to rule->location */
5182 static void hclge_fd_insert_rule_node(struct hlist_head *hlist,
5183                                       struct hclge_fd_rule *rule,
5184                                       struct hclge_fd_rule *parent)
5185 {
5186         INIT_HLIST_NODE(&rule->rule_node);
5187
5188         if (parent)
5189                 hlist_add_behind(&rule->rule_node, &parent->rule_node);
5190         else
5191                 hlist_add_head(&rule->rule_node, hlist);
5192 }
5193
5194 static int hclge_fd_set_user_def_cmd(struct hclge_dev *hdev,
5195                                      struct hclge_fd_user_def_cfg *cfg)
5196 {
5197         struct hclge_fd_user_def_cfg_cmd *req;
5198         struct hclge_desc desc;
5199         u16 data = 0;
5200         int ret;
5201
5202         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_USER_DEF_OP, false);
5203
5204         req = (struct hclge_fd_user_def_cfg_cmd *)desc.data;
5205
5206         hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[0].ref_cnt > 0);
5207         hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M,
5208                         HCLGE_FD_USER_DEF_OFT_S, cfg[0].offset);
5209         req->ol2_cfg = cpu_to_le16(data);
5210
5211         data = 0;
5212         hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[1].ref_cnt > 0);
5213         hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M,
5214                         HCLGE_FD_USER_DEF_OFT_S, cfg[1].offset);
5215         req->ol3_cfg = cpu_to_le16(data);
5216
5217         data = 0;
5218         hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[2].ref_cnt > 0);
5219         hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M,
5220                         HCLGE_FD_USER_DEF_OFT_S, cfg[2].offset);
5221         req->ol4_cfg = cpu_to_le16(data);
5222
5223         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5224         if (ret)
5225                 dev_err(&hdev->pdev->dev,
5226                         "failed to set fd user def data, ret= %d\n", ret);
5227         return ret;
5228 }
5229
5230 static void hclge_sync_fd_user_def_cfg(struct hclge_dev *hdev, bool locked)
5231 {
5232         int ret;
5233
5234         if (!test_and_clear_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state))
5235                 return;
5236
5237         if (!locked)
5238                 spin_lock_bh(&hdev->fd_rule_lock);
5239
5240         ret = hclge_fd_set_user_def_cmd(hdev, hdev->fd_cfg.user_def_cfg);
5241         if (ret)
5242                 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state);
5243
5244         if (!locked)
5245                 spin_unlock_bh(&hdev->fd_rule_lock);
5246 }
5247
5248 static int hclge_fd_check_user_def_refcnt(struct hclge_dev *hdev,
5249                                           struct hclge_fd_rule *rule)
5250 {
5251         struct hlist_head *hlist = &hdev->fd_rule_list;
5252         struct hclge_fd_rule *fd_rule, *parent = NULL;
5253         struct hclge_fd_user_def_info *info, *old_info;
5254         struct hclge_fd_user_def_cfg *cfg;
5255
5256         if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE ||
5257             rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE)
5258                 return 0;
5259
5260         /* for valid layer is start from 1, so need minus 1 to get the cfg */
5261         cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1];
5262         info = &rule->ep.user_def;
5263
5264         if (!cfg->ref_cnt || cfg->offset == info->offset)
5265                 return 0;
5266
5267         if (cfg->ref_cnt > 1)
5268                 goto error;
5269
5270         fd_rule = hclge_find_fd_rule(hlist, rule->location, &parent);
5271         if (fd_rule) {
5272                 old_info = &fd_rule->ep.user_def;
5273                 if (info->layer == old_info->layer)
5274                         return 0;
5275         }
5276
5277 error:
5278         dev_err(&hdev->pdev->dev,
5279                 "No available offset for layer%d fd rule, each layer only support one user def offset.\n",
5280                 info->layer + 1);
5281         return -ENOSPC;
5282 }
5283
5284 static void hclge_fd_inc_user_def_refcnt(struct hclge_dev *hdev,
5285                                          struct hclge_fd_rule *rule)
5286 {
5287         struct hclge_fd_user_def_cfg *cfg;
5288
5289         if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE ||
5290             rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE)
5291                 return;
5292
5293         cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1];
5294         if (!cfg->ref_cnt) {
5295                 cfg->offset = rule->ep.user_def.offset;
5296                 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state);
5297         }
5298         cfg->ref_cnt++;
5299 }
5300
5301 static void hclge_fd_dec_user_def_refcnt(struct hclge_dev *hdev,
5302                                          struct hclge_fd_rule *rule)
5303 {
5304         struct hclge_fd_user_def_cfg *cfg;
5305
5306         if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE ||
5307             rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE)
5308                 return;
5309
5310         cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1];
5311         if (!cfg->ref_cnt)
5312                 return;
5313
5314         cfg->ref_cnt--;
5315         if (!cfg->ref_cnt) {
5316                 cfg->offset = 0;
5317                 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state);
5318         }
5319 }
5320
5321 static void hclge_update_fd_list(struct hclge_dev *hdev,
5322                                  enum HCLGE_FD_NODE_STATE state, u16 location,
5323                                  struct hclge_fd_rule *new_rule)
5324 {
5325         struct hlist_head *hlist = &hdev->fd_rule_list;
5326         struct hclge_fd_rule *fd_rule, *parent = NULL;
5327
5328         fd_rule = hclge_find_fd_rule(hlist, location, &parent);
5329         if (fd_rule) {
5330                 hclge_fd_dec_user_def_refcnt(hdev, fd_rule);
5331                 if (state == HCLGE_FD_ACTIVE)
5332                         hclge_fd_inc_user_def_refcnt(hdev, new_rule);
5333                 hclge_sync_fd_user_def_cfg(hdev, true);
5334
5335                 hclge_update_fd_rule_node(hdev, fd_rule, new_rule, state);
5336                 return;
5337         }
5338
5339         /* it's unlikely to fail here, because we have checked the rule
5340          * exist before.
5341          */
5342         if (unlikely(state == HCLGE_FD_TO_DEL || state == HCLGE_FD_DELETED)) {
5343                 dev_warn(&hdev->pdev->dev,
5344                          "failed to delete fd rule %u, it's inexistent\n",
5345                          location);
5346                 return;
5347         }
5348
5349         hclge_fd_inc_user_def_refcnt(hdev, new_rule);
5350         hclge_sync_fd_user_def_cfg(hdev, true);
5351
5352         hclge_fd_insert_rule_node(hlist, new_rule, parent);
5353         hclge_fd_inc_rule_cnt(hdev, new_rule->location);
5354
5355         if (state == HCLGE_FD_TO_ADD) {
5356                 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state);
5357                 hclge_task_schedule(hdev, 0);
5358         }
5359 }
5360
5361 static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode)
5362 {
5363         struct hclge_get_fd_mode_cmd *req;
5364         struct hclge_desc desc;
5365         int ret;
5366
5367         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_MODE_CTRL, true);
5368
5369         req = (struct hclge_get_fd_mode_cmd *)desc.data;
5370
5371         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5372         if (ret) {
5373                 dev_err(&hdev->pdev->dev, "get fd mode fail, ret=%d\n", ret);
5374                 return ret;
5375         }
5376
5377         *fd_mode = req->mode;
5378
5379         return ret;
5380 }
5381
5382 static int hclge_get_fd_allocation(struct hclge_dev *hdev,
5383                                    u32 *stage1_entry_num,
5384                                    u32 *stage2_entry_num,
5385                                    u16 *stage1_counter_num,
5386                                    u16 *stage2_counter_num)
5387 {
5388         struct hclge_get_fd_allocation_cmd *req;
5389         struct hclge_desc desc;
5390         int ret;
5391
5392         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_GET_ALLOCATION, true);
5393
5394         req = (struct hclge_get_fd_allocation_cmd *)desc.data;
5395
5396         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5397         if (ret) {
5398                 dev_err(&hdev->pdev->dev, "query fd allocation fail, ret=%d\n",
5399                         ret);
5400                 return ret;
5401         }
5402
5403         *stage1_entry_num = le32_to_cpu(req->stage1_entry_num);
5404         *stage2_entry_num = le32_to_cpu(req->stage2_entry_num);
5405         *stage1_counter_num = le16_to_cpu(req->stage1_counter_num);
5406         *stage2_counter_num = le16_to_cpu(req->stage2_counter_num);
5407
5408         return ret;
5409 }
5410
5411 static int hclge_set_fd_key_config(struct hclge_dev *hdev,
5412                                    enum HCLGE_FD_STAGE stage_num)
5413 {
5414         struct hclge_set_fd_key_config_cmd *req;
5415         struct hclge_fd_key_cfg *stage;
5416         struct hclge_desc desc;
5417         int ret;
5418
5419         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_KEY_CONFIG, false);
5420
5421         req = (struct hclge_set_fd_key_config_cmd *)desc.data;
5422         stage = &hdev->fd_cfg.key_cfg[stage_num];
5423         req->stage = stage_num;
5424         req->key_select = stage->key_sel;
5425         req->inner_sipv6_word_en = stage->inner_sipv6_word_en;
5426         req->inner_dipv6_word_en = stage->inner_dipv6_word_en;
5427         req->outer_sipv6_word_en = stage->outer_sipv6_word_en;
5428         req->outer_dipv6_word_en = stage->outer_dipv6_word_en;
5429         req->tuple_mask = cpu_to_le32(~stage->tuple_active);
5430         req->meta_data_mask = cpu_to_le32(~stage->meta_data_active);
5431
5432         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5433         if (ret)
5434                 dev_err(&hdev->pdev->dev, "set fd key fail, ret=%d\n", ret);
5435
5436         return ret;
5437 }
5438
5439 static void hclge_fd_disable_user_def(struct hclge_dev *hdev)
5440 {
5441         struct hclge_fd_user_def_cfg *cfg = hdev->fd_cfg.user_def_cfg;
5442
5443         spin_lock_bh(&hdev->fd_rule_lock);
5444         memset(cfg, 0, sizeof(hdev->fd_cfg.user_def_cfg));
5445         spin_unlock_bh(&hdev->fd_rule_lock);
5446
5447         hclge_fd_set_user_def_cmd(hdev, cfg);
5448 }
5449
5450 static int hclge_init_fd_config(struct hclge_dev *hdev)
5451 {
5452 #define LOW_2_WORDS             0x03
5453         struct hclge_fd_key_cfg *key_cfg;
5454         int ret;
5455
5456         if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
5457                 return 0;
5458
5459         ret = hclge_get_fd_mode(hdev, &hdev->fd_cfg.fd_mode);
5460         if (ret)
5461                 return ret;
5462
5463         switch (hdev->fd_cfg.fd_mode) {
5464         case HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1:
5465                 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH;
5466                 break;
5467         case HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1:
5468                 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH / 2;
5469                 break;
5470         default:
5471                 dev_err(&hdev->pdev->dev,
5472                         "Unsupported flow director mode %u\n",
5473                         hdev->fd_cfg.fd_mode);
5474                 return -EOPNOTSUPP;
5475         }
5476
5477         key_cfg = &hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1];
5478         key_cfg->key_sel = HCLGE_FD_KEY_BASE_ON_TUPLE;
5479         key_cfg->inner_sipv6_word_en = LOW_2_WORDS;
5480         key_cfg->inner_dipv6_word_en = LOW_2_WORDS;
5481         key_cfg->outer_sipv6_word_en = 0;
5482         key_cfg->outer_dipv6_word_en = 0;
5483
5484         key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) |
5485                                 BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) |
5486                                 BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) |
5487                                 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
5488
5489         /* If use max 400bit key, we can support tuples for ether type */
5490         if (hdev->fd_cfg.fd_mode == HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) {
5491                 key_cfg->tuple_active |=
5492                                 BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC);
5493                 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
5494                         key_cfg->tuple_active |= HCLGE_FD_TUPLE_USER_DEF_TUPLES;
5495         }
5496
5497         /* roce_type is used to filter roce frames
5498          * dst_vport is used to specify the rule
5499          */
5500         key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT);
5501
5502         ret = hclge_get_fd_allocation(hdev,
5503                                       &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1],
5504                                       &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2],
5505                                       &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1],
5506                                       &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]);
5507         if (ret)
5508                 return ret;
5509
5510         return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1);
5511 }
5512
5513 static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x,
5514                                 int loc, u8 *key, bool is_add)
5515 {
5516         struct hclge_fd_tcam_config_1_cmd *req1;
5517         struct hclge_fd_tcam_config_2_cmd *req2;
5518         struct hclge_fd_tcam_config_3_cmd *req3;
5519         struct hclge_desc desc[3];
5520         int ret;
5521
5522         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false);
5523         desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
5524         hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false);
5525         desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
5526         hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false);
5527
5528         req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data;
5529         req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data;
5530         req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data;
5531
5532         req1->stage = stage;
5533         req1->xy_sel = sel_x ? 1 : 0;
5534         hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0);
5535         req1->index = cpu_to_le32(loc);
5536         req1->entry_vld = sel_x ? is_add : 0;
5537
5538         if (key) {
5539                 memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data));
5540                 memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)],
5541                        sizeof(req2->tcam_data));
5542                 memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) +
5543                        sizeof(req2->tcam_data)], sizeof(req3->tcam_data));
5544         }
5545
5546         ret = hclge_cmd_send(&hdev->hw, desc, 3);
5547         if (ret)
5548                 dev_err(&hdev->pdev->dev,
5549                         "config tcam key fail, ret=%d\n",
5550                         ret);
5551
5552         return ret;
5553 }
5554
5555 static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc,
5556                               struct hclge_fd_ad_data *action)
5557 {
5558         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
5559         struct hclge_fd_ad_config_cmd *req;
5560         struct hclge_desc desc;
5561         u64 ad_data = 0;
5562         int ret;
5563
5564         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false);
5565
5566         req = (struct hclge_fd_ad_config_cmd *)desc.data;
5567         req->index = cpu_to_le32(loc);
5568         req->stage = stage;
5569
5570         hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B,
5571                       action->write_rule_id_to_bd);
5572         hnae3_set_field(ad_data, HCLGE_FD_AD_RULE_ID_M, HCLGE_FD_AD_RULE_ID_S,
5573                         action->rule_id);
5574         if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps)) {
5575                 hnae3_set_bit(ad_data, HCLGE_FD_AD_TC_OVRD_B,
5576                               action->override_tc);
5577                 hnae3_set_field(ad_data, HCLGE_FD_AD_TC_SIZE_M,
5578                                 HCLGE_FD_AD_TC_SIZE_S, (u32)action->tc_size);
5579         }
5580         ad_data <<= 32;
5581         hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet);
5582         hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B,
5583                       action->forward_to_direct_queue);
5584         hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S,
5585                         action->queue_id);
5586         hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter);
5587         hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M,
5588                         HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id);
5589         hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage);
5590         hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S,
5591                         action->counter_id);
5592
5593         req->ad_data = cpu_to_le64(ad_data);
5594         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5595         if (ret)
5596                 dev_err(&hdev->pdev->dev, "fd ad config fail, ret=%d\n", ret);
5597
5598         return ret;
5599 }
5600
5601 static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y,
5602                                    struct hclge_fd_rule *rule)
5603 {
5604         int offset, moffset, ip_offset;
5605         enum HCLGE_FD_KEY_OPT key_opt;
5606         u16 tmp_x_s, tmp_y_s;
5607         u32 tmp_x_l, tmp_y_l;
5608         u8 *p = (u8 *)rule;
5609         int i;
5610
5611         if (rule->unused_tuple & BIT(tuple_bit))
5612                 return true;
5613
5614         key_opt = tuple_key_info[tuple_bit].key_opt;
5615         offset = tuple_key_info[tuple_bit].offset;
5616         moffset = tuple_key_info[tuple_bit].moffset;
5617
5618         switch (key_opt) {
5619         case KEY_OPT_U8:
5620                 calc_x(*key_x, p[offset], p[moffset]);
5621                 calc_y(*key_y, p[offset], p[moffset]);
5622
5623                 return true;
5624         case KEY_OPT_LE16:
5625                 calc_x(tmp_x_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset]));
5626                 calc_y(tmp_y_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset]));
5627                 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
5628                 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
5629
5630                 return true;
5631         case KEY_OPT_LE32:
5632                 calc_x(tmp_x_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset]));
5633                 calc_y(tmp_y_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset]));
5634                 *(__le32 *)key_x = cpu_to_le32(tmp_x_l);
5635                 *(__le32 *)key_y = cpu_to_le32(tmp_y_l);
5636
5637                 return true;
5638         case KEY_OPT_MAC:
5639                 for (i = 0; i < ETH_ALEN; i++) {
5640                         calc_x(key_x[ETH_ALEN - 1 - i], p[offset + i],
5641                                p[moffset + i]);
5642                         calc_y(key_y[ETH_ALEN - 1 - i], p[offset + i],
5643                                p[moffset + i]);
5644                 }
5645
5646                 return true;
5647         case KEY_OPT_IP:
5648                 ip_offset = IPV4_INDEX * sizeof(u32);
5649                 calc_x(tmp_x_l, *(u32 *)(&p[offset + ip_offset]),
5650                        *(u32 *)(&p[moffset + ip_offset]));
5651                 calc_y(tmp_y_l, *(u32 *)(&p[offset + ip_offset]),
5652                        *(u32 *)(&p[moffset + ip_offset]));
5653                 *(__le32 *)key_x = cpu_to_le32(tmp_x_l);
5654                 *(__le32 *)key_y = cpu_to_le32(tmp_y_l);
5655
5656                 return true;
5657         default:
5658                 return false;
5659         }
5660 }
5661
5662 static u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id,
5663                                  u8 vf_id, u8 network_port_id)
5664 {
5665         u32 port_number = 0;
5666
5667         if (port_type == HOST_PORT) {
5668                 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S,
5669                                 pf_id);
5670                 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S,
5671                                 vf_id);
5672                 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT);
5673         } else {
5674                 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M,
5675                                 HCLGE_NETWORK_PORT_ID_S, network_port_id);
5676                 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT);
5677         }
5678
5679         return port_number;
5680 }
5681
5682 static void hclge_fd_convert_meta_data(struct hclge_fd_key_cfg *key_cfg,
5683                                        __le32 *key_x, __le32 *key_y,
5684                                        struct hclge_fd_rule *rule)
5685 {
5686         u32 tuple_bit, meta_data = 0, tmp_x, tmp_y, port_number;
5687         u8 cur_pos = 0, tuple_size, shift_bits;
5688         unsigned int i;
5689
5690         for (i = 0; i < MAX_META_DATA; i++) {
5691                 tuple_size = meta_data_key_info[i].key_length;
5692                 tuple_bit = key_cfg->meta_data_active & BIT(i);
5693
5694                 switch (tuple_bit) {
5695                 case BIT(ROCE_TYPE):
5696                         hnae3_set_bit(meta_data, cur_pos, NIC_PACKET);
5697                         cur_pos += tuple_size;
5698                         break;
5699                 case BIT(DST_VPORT):
5700                         port_number = hclge_get_port_number(HOST_PORT, 0,
5701                                                             rule->vf_id, 0);
5702                         hnae3_set_field(meta_data,
5703                                         GENMASK(cur_pos + tuple_size, cur_pos),
5704                                         cur_pos, port_number);
5705                         cur_pos += tuple_size;
5706                         break;
5707                 default:
5708                         break;
5709                 }
5710         }
5711
5712         calc_x(tmp_x, meta_data, 0xFFFFFFFF);
5713         calc_y(tmp_y, meta_data, 0xFFFFFFFF);
5714         shift_bits = sizeof(meta_data) * 8 - cur_pos;
5715
5716         *key_x = cpu_to_le32(tmp_x << shift_bits);
5717         *key_y = cpu_to_le32(tmp_y << shift_bits);
5718 }
5719
5720 /* A complete key is combined with meta data key and tuple key.
5721  * Meta data key is stored at the MSB region, and tuple key is stored at
5722  * the LSB region, unused bits will be filled 0.
5723  */
5724 static int hclge_config_key(struct hclge_dev *hdev, u8 stage,
5725                             struct hclge_fd_rule *rule)
5726 {
5727         struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage];
5728         u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES];
5729         u8 *cur_key_x, *cur_key_y;
5730         u8 meta_data_region;
5731         u8 tuple_size;
5732         int ret;
5733         u32 i;
5734
5735         memset(key_x, 0, sizeof(key_x));
5736         memset(key_y, 0, sizeof(key_y));
5737         cur_key_x = key_x;
5738         cur_key_y = key_y;
5739
5740         for (i = 0; i < MAX_TUPLE; i++) {
5741                 bool tuple_valid;
5742
5743                 tuple_size = tuple_key_info[i].key_length / 8;
5744                 if (!(key_cfg->tuple_active & BIT(i)))
5745                         continue;
5746
5747                 tuple_valid = hclge_fd_convert_tuple(i, cur_key_x,
5748                                                      cur_key_y, rule);
5749                 if (tuple_valid) {
5750                         cur_key_x += tuple_size;
5751                         cur_key_y += tuple_size;
5752                 }
5753         }
5754
5755         meta_data_region = hdev->fd_cfg.max_key_length / 8 -
5756                         MAX_META_DATA_LENGTH / 8;
5757
5758         hclge_fd_convert_meta_data(key_cfg,
5759                                    (__le32 *)(key_x + meta_data_region),
5760                                    (__le32 *)(key_y + meta_data_region),
5761                                    rule);
5762
5763         ret = hclge_fd_tcam_config(hdev, stage, false, rule->location, key_y,
5764                                    true);
5765         if (ret) {
5766                 dev_err(&hdev->pdev->dev,
5767                         "fd key_y config fail, loc=%u, ret=%d\n",
5768                         rule->queue_id, ret);
5769                 return ret;
5770         }
5771
5772         ret = hclge_fd_tcam_config(hdev, stage, true, rule->location, key_x,
5773                                    true);
5774         if (ret)
5775                 dev_err(&hdev->pdev->dev,
5776                         "fd key_x config fail, loc=%u, ret=%d\n",
5777                         rule->queue_id, ret);
5778         return ret;
5779 }
5780
5781 static int hclge_config_action(struct hclge_dev *hdev, u8 stage,
5782                                struct hclge_fd_rule *rule)
5783 {
5784         struct hclge_vport *vport = hdev->vport;
5785         struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5786         struct hclge_fd_ad_data ad_data;
5787
5788         memset(&ad_data, 0, sizeof(struct hclge_fd_ad_data));
5789         ad_data.ad_id = rule->location;
5790
5791         if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) {
5792                 ad_data.drop_packet = true;
5793         } else if (rule->action == HCLGE_FD_ACTION_SELECT_TC) {
5794                 ad_data.override_tc = true;
5795                 ad_data.queue_id =
5796                         kinfo->tc_info.tqp_offset[rule->cls_flower.tc];
5797                 ad_data.tc_size =
5798                         ilog2(kinfo->tc_info.tqp_count[rule->cls_flower.tc]);
5799         } else {
5800                 ad_data.forward_to_direct_queue = true;
5801                 ad_data.queue_id = rule->queue_id;
5802         }
5803
5804         if (hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]) {
5805                 ad_data.use_counter = true;
5806                 ad_data.counter_id = rule->vf_id %
5807                                      hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1];
5808         } else {
5809                 ad_data.use_counter = false;
5810                 ad_data.counter_id = 0;
5811         }
5812
5813         ad_data.use_next_stage = false;
5814         ad_data.next_input_key = 0;
5815
5816         ad_data.write_rule_id_to_bd = true;
5817         ad_data.rule_id = rule->location;
5818
5819         return hclge_fd_ad_config(hdev, stage, ad_data.ad_id, &ad_data);
5820 }
5821
5822 static int hclge_fd_check_tcpip4_tuple(struct ethtool_tcpip4_spec *spec,
5823                                        u32 *unused_tuple)
5824 {
5825         if (!spec || !unused_tuple)
5826                 return -EINVAL;
5827
5828         *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC);
5829
5830         if (!spec->ip4src)
5831                 *unused_tuple |= BIT(INNER_SRC_IP);
5832
5833         if (!spec->ip4dst)
5834                 *unused_tuple |= BIT(INNER_DST_IP);
5835
5836         if (!spec->psrc)
5837                 *unused_tuple |= BIT(INNER_SRC_PORT);
5838
5839         if (!spec->pdst)
5840                 *unused_tuple |= BIT(INNER_DST_PORT);
5841
5842         if (!spec->tos)
5843                 *unused_tuple |= BIT(INNER_IP_TOS);
5844
5845         return 0;
5846 }
5847
5848 static int hclge_fd_check_ip4_tuple(struct ethtool_usrip4_spec *spec,
5849                                     u32 *unused_tuple)
5850 {
5851         if (!spec || !unused_tuple)
5852                 return -EINVAL;
5853
5854         *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
5855                 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
5856
5857         if (!spec->ip4src)
5858                 *unused_tuple |= BIT(INNER_SRC_IP);
5859
5860         if (!spec->ip4dst)
5861                 *unused_tuple |= BIT(INNER_DST_IP);
5862
5863         if (!spec->tos)
5864                 *unused_tuple |= BIT(INNER_IP_TOS);
5865
5866         if (!spec->proto)
5867                 *unused_tuple |= BIT(INNER_IP_PROTO);
5868
5869         if (spec->l4_4_bytes)
5870                 return -EOPNOTSUPP;
5871
5872         if (spec->ip_ver != ETH_RX_NFC_IP4)
5873                 return -EOPNOTSUPP;
5874
5875         return 0;
5876 }
5877
5878 static int hclge_fd_check_tcpip6_tuple(struct ethtool_tcpip6_spec *spec,
5879                                        u32 *unused_tuple)
5880 {
5881         if (!spec || !unused_tuple)
5882                 return -EINVAL;
5883
5884         *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC);
5885
5886         /* check whether src/dst ip address used */
5887         if (ipv6_addr_any((struct in6_addr *)spec->ip6src))
5888                 *unused_tuple |= BIT(INNER_SRC_IP);
5889
5890         if (ipv6_addr_any((struct in6_addr *)spec->ip6dst))
5891                 *unused_tuple |= BIT(INNER_DST_IP);
5892
5893         if (!spec->psrc)
5894                 *unused_tuple |= BIT(INNER_SRC_PORT);
5895
5896         if (!spec->pdst)
5897                 *unused_tuple |= BIT(INNER_DST_PORT);
5898
5899         if (!spec->tclass)
5900                 *unused_tuple |= BIT(INNER_IP_TOS);
5901
5902         return 0;
5903 }
5904
5905 static int hclge_fd_check_ip6_tuple(struct ethtool_usrip6_spec *spec,
5906                                     u32 *unused_tuple)
5907 {
5908         if (!spec || !unused_tuple)
5909                 return -EINVAL;
5910
5911         *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
5912                         BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
5913
5914         /* check whether src/dst ip address used */
5915         if (ipv6_addr_any((struct in6_addr *)spec->ip6src))
5916                 *unused_tuple |= BIT(INNER_SRC_IP);
5917
5918         if (ipv6_addr_any((struct in6_addr *)spec->ip6dst))
5919                 *unused_tuple |= BIT(INNER_DST_IP);
5920
5921         if (!spec->l4_proto)
5922                 *unused_tuple |= BIT(INNER_IP_PROTO);
5923
5924         if (!spec->tclass)
5925                 *unused_tuple |= BIT(INNER_IP_TOS);
5926
5927         if (spec->l4_4_bytes)
5928                 return -EOPNOTSUPP;
5929
5930         return 0;
5931 }
5932
5933 static int hclge_fd_check_ether_tuple(struct ethhdr *spec, u32 *unused_tuple)
5934 {
5935         if (!spec || !unused_tuple)
5936                 return -EINVAL;
5937
5938         *unused_tuple |= BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) |
5939                 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT) |
5940                 BIT(INNER_IP_TOS) | BIT(INNER_IP_PROTO);
5941
5942         if (is_zero_ether_addr(spec->h_source))
5943                 *unused_tuple |= BIT(INNER_SRC_MAC);
5944
5945         if (is_zero_ether_addr(spec->h_dest))
5946                 *unused_tuple |= BIT(INNER_DST_MAC);
5947
5948         if (!spec->h_proto)
5949                 *unused_tuple |= BIT(INNER_ETH_TYPE);
5950
5951         return 0;
5952 }
5953
5954 static int hclge_fd_check_ext_tuple(struct hclge_dev *hdev,
5955                                     struct ethtool_rx_flow_spec *fs,
5956                                     u32 *unused_tuple)
5957 {
5958         if (fs->flow_type & FLOW_EXT) {
5959                 if (fs->h_ext.vlan_etype) {
5960                         dev_err(&hdev->pdev->dev, "vlan-etype is not supported!\n");
5961                         return -EOPNOTSUPP;
5962                 }
5963
5964                 if (!fs->h_ext.vlan_tci)
5965                         *unused_tuple |= BIT(INNER_VLAN_TAG_FST);
5966
5967                 if (fs->m_ext.vlan_tci &&
5968                     be16_to_cpu(fs->h_ext.vlan_tci) >= VLAN_N_VID) {
5969                         dev_err(&hdev->pdev->dev,
5970                                 "failed to config vlan_tci, invalid vlan_tci: %u, max is %d.\n",
5971                                 ntohs(fs->h_ext.vlan_tci), VLAN_N_VID - 1);
5972                         return -EINVAL;
5973                 }
5974         } else {
5975                 *unused_tuple |= BIT(INNER_VLAN_TAG_FST);
5976         }
5977
5978         if (fs->flow_type & FLOW_MAC_EXT) {
5979                 if (hdev->fd_cfg.fd_mode !=
5980                     HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) {
5981                         dev_err(&hdev->pdev->dev,
5982                                 "FLOW_MAC_EXT is not supported in current fd mode!\n");
5983                         return -EOPNOTSUPP;
5984                 }
5985
5986                 if (is_zero_ether_addr(fs->h_ext.h_dest))
5987                         *unused_tuple |= BIT(INNER_DST_MAC);
5988                 else
5989                         *unused_tuple &= ~BIT(INNER_DST_MAC);
5990         }
5991
5992         return 0;
5993 }
5994
5995 static int hclge_fd_get_user_def_layer(u32 flow_type, u32 *unused_tuple,
5996                                        struct hclge_fd_user_def_info *info)
5997 {
5998         switch (flow_type) {
5999         case ETHER_FLOW:
6000                 info->layer = HCLGE_FD_USER_DEF_L2;
6001                 *unused_tuple &= ~BIT(INNER_L2_RSV);
6002                 break;
6003         case IP_USER_FLOW:
6004         case IPV6_USER_FLOW:
6005                 info->layer = HCLGE_FD_USER_DEF_L3;
6006                 *unused_tuple &= ~BIT(INNER_L3_RSV);
6007                 break;
6008         case TCP_V4_FLOW:
6009         case UDP_V4_FLOW:
6010         case TCP_V6_FLOW:
6011         case UDP_V6_FLOW:
6012                 info->layer = HCLGE_FD_USER_DEF_L4;
6013                 *unused_tuple &= ~BIT(INNER_L4_RSV);
6014                 break;
6015         default:
6016                 return -EOPNOTSUPP;
6017         }
6018
6019         return 0;
6020 }
6021
6022 static bool hclge_fd_is_user_def_all_masked(struct ethtool_rx_flow_spec *fs)
6023 {
6024         return be32_to_cpu(fs->m_ext.data[1] | fs->m_ext.data[0]) == 0;
6025 }
6026
6027 static int hclge_fd_parse_user_def_field(struct hclge_dev *hdev,
6028                                          struct ethtool_rx_flow_spec *fs,
6029                                          u32 *unused_tuple,
6030                                          struct hclge_fd_user_def_info *info)
6031 {
6032         u32 tuple_active = hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1].tuple_active;
6033         u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT);
6034         u16 data, offset, data_mask, offset_mask;
6035         int ret;
6036
6037         info->layer = HCLGE_FD_USER_DEF_NONE;
6038         *unused_tuple |= HCLGE_FD_TUPLE_USER_DEF_TUPLES;
6039
6040         if (!(fs->flow_type & FLOW_EXT) || hclge_fd_is_user_def_all_masked(fs))
6041                 return 0;
6042
6043         /* user-def data from ethtool is 64 bit value, the bit0~15 is used
6044          * for data, and bit32~47 is used for offset.
6045          */
6046         data = be32_to_cpu(fs->h_ext.data[1]) & HCLGE_FD_USER_DEF_DATA;
6047         data_mask = be32_to_cpu(fs->m_ext.data[1]) & HCLGE_FD_USER_DEF_DATA;
6048         offset = be32_to_cpu(fs->h_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET;
6049         offset_mask = be32_to_cpu(fs->m_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET;
6050
6051         if (!(tuple_active & HCLGE_FD_TUPLE_USER_DEF_TUPLES)) {
6052                 dev_err(&hdev->pdev->dev, "user-def bytes are not supported\n");
6053                 return -EOPNOTSUPP;
6054         }
6055
6056         if (offset > HCLGE_FD_MAX_USER_DEF_OFFSET) {
6057                 dev_err(&hdev->pdev->dev,
6058                         "user-def offset[%u] should be no more than %u\n",
6059                         offset, HCLGE_FD_MAX_USER_DEF_OFFSET);
6060                 return -EINVAL;
6061         }
6062
6063         if (offset_mask != HCLGE_FD_USER_DEF_OFFSET_UNMASK) {
6064                 dev_err(&hdev->pdev->dev, "user-def offset can't be masked\n");
6065                 return -EINVAL;
6066         }
6067
6068         ret = hclge_fd_get_user_def_layer(flow_type, unused_tuple, info);
6069         if (ret) {
6070                 dev_err(&hdev->pdev->dev,
6071                         "unsupported flow type for user-def bytes, ret = %d\n",
6072                         ret);
6073                 return ret;
6074         }
6075
6076         info->data = data;
6077         info->data_mask = data_mask;
6078         info->offset = offset;
6079
6080         return 0;
6081 }
6082
6083 static int hclge_fd_check_spec(struct hclge_dev *hdev,
6084                                struct ethtool_rx_flow_spec *fs,
6085                                u32 *unused_tuple,
6086                                struct hclge_fd_user_def_info *info)
6087 {
6088         u32 flow_type;
6089         int ret;
6090
6091         if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) {
6092                 dev_err(&hdev->pdev->dev,
6093                         "failed to config fd rules, invalid rule location: %u, max is %u\n.",
6094                         fs->location,
6095                         hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1] - 1);
6096                 return -EINVAL;
6097         }
6098
6099         ret = hclge_fd_parse_user_def_field(hdev, fs, unused_tuple, info);
6100         if (ret)
6101                 return ret;
6102
6103         flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT);
6104         switch (flow_type) {
6105         case SCTP_V4_FLOW:
6106         case TCP_V4_FLOW:
6107         case UDP_V4_FLOW:
6108                 ret = hclge_fd_check_tcpip4_tuple(&fs->h_u.tcp_ip4_spec,
6109                                                   unused_tuple);
6110                 break;
6111         case IP_USER_FLOW:
6112                 ret = hclge_fd_check_ip4_tuple(&fs->h_u.usr_ip4_spec,
6113                                                unused_tuple);
6114                 break;
6115         case SCTP_V6_FLOW:
6116         case TCP_V6_FLOW:
6117         case UDP_V6_FLOW:
6118                 ret = hclge_fd_check_tcpip6_tuple(&fs->h_u.tcp_ip6_spec,
6119                                                   unused_tuple);
6120                 break;
6121         case IPV6_USER_FLOW:
6122                 ret = hclge_fd_check_ip6_tuple(&fs->h_u.usr_ip6_spec,
6123                                                unused_tuple);
6124                 break;
6125         case ETHER_FLOW:
6126                 if (hdev->fd_cfg.fd_mode !=
6127                         HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) {
6128                         dev_err(&hdev->pdev->dev,
6129                                 "ETHER_FLOW is not supported in current fd mode!\n");
6130                         return -EOPNOTSUPP;
6131                 }
6132
6133                 ret = hclge_fd_check_ether_tuple(&fs->h_u.ether_spec,
6134                                                  unused_tuple);
6135                 break;
6136         default:
6137                 dev_err(&hdev->pdev->dev,
6138                         "unsupported protocol type, protocol type = %#x\n",
6139                         flow_type);
6140                 return -EOPNOTSUPP;
6141         }
6142
6143         if (ret) {
6144                 dev_err(&hdev->pdev->dev,
6145                         "failed to check flow union tuple, ret = %d\n",
6146                         ret);
6147                 return ret;
6148         }
6149
6150         return hclge_fd_check_ext_tuple(hdev, fs, unused_tuple);
6151 }
6152
6153 static void hclge_fd_get_tcpip4_tuple(struct ethtool_rx_flow_spec *fs,
6154                                       struct hclge_fd_rule *rule, u8 ip_proto)
6155 {
6156         rule->tuples.src_ip[IPV4_INDEX] =
6157                         be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4src);
6158         rule->tuples_mask.src_ip[IPV4_INDEX] =
6159                         be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4src);
6160
6161         rule->tuples.dst_ip[IPV4_INDEX] =
6162                         be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4dst);
6163         rule->tuples_mask.dst_ip[IPV4_INDEX] =
6164                         be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4dst);
6165
6166         rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc);
6167         rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.psrc);
6168
6169         rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst);
6170         rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.pdst);
6171
6172         rule->tuples.ip_tos = fs->h_u.tcp_ip4_spec.tos;
6173         rule->tuples_mask.ip_tos = fs->m_u.tcp_ip4_spec.tos;
6174
6175         rule->tuples.ether_proto = ETH_P_IP;
6176         rule->tuples_mask.ether_proto = 0xFFFF;
6177
6178         rule->tuples.ip_proto = ip_proto;
6179         rule->tuples_mask.ip_proto = 0xFF;
6180 }
6181
6182 static void hclge_fd_get_ip4_tuple(struct ethtool_rx_flow_spec *fs,
6183                                    struct hclge_fd_rule *rule)
6184 {
6185         rule->tuples.src_ip[IPV4_INDEX] =
6186                         be32_to_cpu(fs->h_u.usr_ip4_spec.ip4src);
6187         rule->tuples_mask.src_ip[IPV4_INDEX] =
6188                         be32_to_cpu(fs->m_u.usr_ip4_spec.ip4src);
6189
6190         rule->tuples.dst_ip[IPV4_INDEX] =
6191                         be32_to_cpu(fs->h_u.usr_ip4_spec.ip4dst);
6192         rule->tuples_mask.dst_ip[IPV4_INDEX] =
6193                         be32_to_cpu(fs->m_u.usr_ip4_spec.ip4dst);
6194
6195         rule->tuples.ip_tos = fs->h_u.usr_ip4_spec.tos;
6196         rule->tuples_mask.ip_tos = fs->m_u.usr_ip4_spec.tos;
6197
6198         rule->tuples.ip_proto = fs->h_u.usr_ip4_spec.proto;
6199         rule->tuples_mask.ip_proto = fs->m_u.usr_ip4_spec.proto;
6200
6201         rule->tuples.ether_proto = ETH_P_IP;
6202         rule->tuples_mask.ether_proto = 0xFFFF;
6203 }
6204
6205 static void hclge_fd_get_tcpip6_tuple(struct ethtool_rx_flow_spec *fs,
6206                                       struct hclge_fd_rule *rule, u8 ip_proto)
6207 {
6208         be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.tcp_ip6_spec.ip6src,
6209                           IPV6_SIZE);
6210         be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.tcp_ip6_spec.ip6src,
6211                           IPV6_SIZE);
6212
6213         be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.tcp_ip6_spec.ip6dst,
6214                           IPV6_SIZE);
6215         be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.tcp_ip6_spec.ip6dst,
6216                           IPV6_SIZE);
6217
6218         rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.psrc);
6219         rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.psrc);
6220
6221         rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.pdst);
6222         rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.pdst);
6223
6224         rule->tuples.ether_proto = ETH_P_IPV6;
6225         rule->tuples_mask.ether_proto = 0xFFFF;
6226
6227         rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass;
6228         rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass;
6229
6230         rule->tuples.ip_proto = ip_proto;
6231         rule->tuples_mask.ip_proto = 0xFF;
6232 }
6233
6234 static void hclge_fd_get_ip6_tuple(struct ethtool_rx_flow_spec *fs,
6235                                    struct hclge_fd_rule *rule)
6236 {
6237         be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.usr_ip6_spec.ip6src,
6238                           IPV6_SIZE);
6239         be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.usr_ip6_spec.ip6src,
6240                           IPV6_SIZE);
6241
6242         be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.usr_ip6_spec.ip6dst,
6243                           IPV6_SIZE);
6244         be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.usr_ip6_spec.ip6dst,
6245                           IPV6_SIZE);
6246
6247         rule->tuples.ip_proto = fs->h_u.usr_ip6_spec.l4_proto;
6248         rule->tuples_mask.ip_proto = fs->m_u.usr_ip6_spec.l4_proto;
6249
6250         rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass;
6251         rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass;
6252
6253         rule->tuples.ether_proto = ETH_P_IPV6;
6254         rule->tuples_mask.ether_proto = 0xFFFF;
6255 }
6256
6257 static void hclge_fd_get_ether_tuple(struct ethtool_rx_flow_spec *fs,
6258                                      struct hclge_fd_rule *rule)
6259 {
6260         ether_addr_copy(rule->tuples.src_mac, fs->h_u.ether_spec.h_source);
6261         ether_addr_copy(rule->tuples_mask.src_mac, fs->m_u.ether_spec.h_source);
6262
6263         ether_addr_copy(rule->tuples.dst_mac, fs->h_u.ether_spec.h_dest);
6264         ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_u.ether_spec.h_dest);
6265
6266         rule->tuples.ether_proto = be16_to_cpu(fs->h_u.ether_spec.h_proto);
6267         rule->tuples_mask.ether_proto = be16_to_cpu(fs->m_u.ether_spec.h_proto);
6268 }
6269
6270 static void hclge_fd_get_user_def_tuple(struct hclge_fd_user_def_info *info,
6271                                         struct hclge_fd_rule *rule)
6272 {
6273         switch (info->layer) {
6274         case HCLGE_FD_USER_DEF_L2:
6275                 rule->tuples.l2_user_def = info->data;
6276                 rule->tuples_mask.l2_user_def = info->data_mask;
6277                 break;
6278         case HCLGE_FD_USER_DEF_L3:
6279                 rule->tuples.l3_user_def = info->data;
6280                 rule->tuples_mask.l3_user_def = info->data_mask;
6281                 break;
6282         case HCLGE_FD_USER_DEF_L4:
6283                 rule->tuples.l4_user_def = (u32)info->data << 16;
6284                 rule->tuples_mask.l4_user_def = (u32)info->data_mask << 16;
6285                 break;
6286         default:
6287                 break;
6288         }
6289
6290         rule->ep.user_def = *info;
6291 }
6292
6293 static int hclge_fd_get_tuple(struct ethtool_rx_flow_spec *fs,
6294                               struct hclge_fd_rule *rule,
6295                               struct hclge_fd_user_def_info *info)
6296 {
6297         u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT);
6298
6299         switch (flow_type) {
6300         case SCTP_V4_FLOW:
6301                 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_SCTP);
6302                 break;
6303         case TCP_V4_FLOW:
6304                 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_TCP);
6305                 break;
6306         case UDP_V4_FLOW:
6307                 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_UDP);
6308                 break;
6309         case IP_USER_FLOW:
6310                 hclge_fd_get_ip4_tuple(fs, rule);
6311                 break;
6312         case SCTP_V6_FLOW:
6313                 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_SCTP);
6314                 break;
6315         case TCP_V6_FLOW:
6316                 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_TCP);
6317                 break;
6318         case UDP_V6_FLOW:
6319                 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_UDP);
6320                 break;
6321         case IPV6_USER_FLOW:
6322                 hclge_fd_get_ip6_tuple(fs, rule);
6323                 break;
6324         case ETHER_FLOW:
6325                 hclge_fd_get_ether_tuple(fs, rule);
6326                 break;
6327         default:
6328                 return -EOPNOTSUPP;
6329         }
6330
6331         if (fs->flow_type & FLOW_EXT) {
6332                 rule->tuples.vlan_tag1 = be16_to_cpu(fs->h_ext.vlan_tci);
6333                 rule->tuples_mask.vlan_tag1 = be16_to_cpu(fs->m_ext.vlan_tci);
6334                 hclge_fd_get_user_def_tuple(info, rule);
6335         }
6336
6337         if (fs->flow_type & FLOW_MAC_EXT) {
6338                 ether_addr_copy(rule->tuples.dst_mac, fs->h_ext.h_dest);
6339                 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_ext.h_dest);
6340         }
6341
6342         return 0;
6343 }
6344
6345 static int hclge_fd_config_rule(struct hclge_dev *hdev,
6346                                 struct hclge_fd_rule *rule)
6347 {
6348         int ret;
6349
6350         ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule);
6351         if (ret)
6352                 return ret;
6353
6354         return hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule);
6355 }
6356
6357 static int hclge_add_fd_entry_common(struct hclge_dev *hdev,
6358                                      struct hclge_fd_rule *rule)
6359 {
6360         int ret;
6361
6362         spin_lock_bh(&hdev->fd_rule_lock);
6363
6364         if (hdev->fd_active_type != rule->rule_type &&
6365             (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE ||
6366              hdev->fd_active_type == HCLGE_FD_EP_ACTIVE)) {
6367                 dev_err(&hdev->pdev->dev,
6368                         "mode conflict(new type %d, active type %d), please delete existent rules first\n",
6369                         rule->rule_type, hdev->fd_active_type);
6370                 spin_unlock_bh(&hdev->fd_rule_lock);
6371                 return -EINVAL;
6372         }
6373
6374         ret = hclge_fd_check_user_def_refcnt(hdev, rule);
6375         if (ret)
6376                 goto out;
6377
6378         ret = hclge_clear_arfs_rules(hdev);
6379         if (ret)
6380                 goto out;
6381
6382         ret = hclge_fd_config_rule(hdev, rule);
6383         if (ret)
6384                 goto out;
6385
6386         rule->state = HCLGE_FD_ACTIVE;
6387         hdev->fd_active_type = rule->rule_type;
6388         hclge_update_fd_list(hdev, rule->state, rule->location, rule);
6389
6390 out:
6391         spin_unlock_bh(&hdev->fd_rule_lock);
6392         return ret;
6393 }
6394
6395 static bool hclge_is_cls_flower_active(struct hnae3_handle *handle)
6396 {
6397         struct hclge_vport *vport = hclge_get_vport(handle);
6398         struct hclge_dev *hdev = vport->back;
6399
6400         return hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE;
6401 }
6402
6403 static int hclge_fd_parse_ring_cookie(struct hclge_dev *hdev, u64 ring_cookie,
6404                                       u16 *vport_id, u8 *action, u16 *queue_id)
6405 {
6406         struct hclge_vport *vport = hdev->vport;
6407
6408         if (ring_cookie == RX_CLS_FLOW_DISC) {
6409                 *action = HCLGE_FD_ACTION_DROP_PACKET;
6410         } else {
6411                 u32 ring = ethtool_get_flow_spec_ring(ring_cookie);
6412                 u8 vf = ethtool_get_flow_spec_ring_vf(ring_cookie);
6413                 u16 tqps;
6414
6415                 /* To keep consistent with user's configuration, minus 1 when
6416                  * printing 'vf', because vf id from ethtool is added 1 for vf.
6417                  */
6418                 if (vf > hdev->num_req_vfs) {
6419                         dev_err(&hdev->pdev->dev,
6420                                 "Error: vf id (%u) should be less than %u\n",
6421                                 vf - 1U, hdev->num_req_vfs);
6422                         return -EINVAL;
6423                 }
6424
6425                 *vport_id = vf ? hdev->vport[vf].vport_id : vport->vport_id;
6426                 tqps = hdev->vport[vf].nic.kinfo.num_tqps;
6427
6428                 if (ring >= tqps) {
6429                         dev_err(&hdev->pdev->dev,
6430                                 "Error: queue id (%u) > max tqp num (%u)\n",
6431                                 ring, tqps - 1U);
6432                         return -EINVAL;
6433                 }
6434
6435                 *action = HCLGE_FD_ACTION_SELECT_QUEUE;
6436                 *queue_id = ring;
6437         }
6438
6439         return 0;
6440 }
6441
6442 static int hclge_add_fd_entry(struct hnae3_handle *handle,
6443                               struct ethtool_rxnfc *cmd)
6444 {
6445         struct hclge_vport *vport = hclge_get_vport(handle);
6446         struct hclge_dev *hdev = vport->back;
6447         struct hclge_fd_user_def_info info;
6448         u16 dst_vport_id = 0, q_index = 0;
6449         struct ethtool_rx_flow_spec *fs;
6450         struct hclge_fd_rule *rule;
6451         u32 unused = 0;
6452         u8 action;
6453         int ret;
6454
6455         if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) {
6456                 dev_err(&hdev->pdev->dev,
6457                         "flow table director is not supported\n");
6458                 return -EOPNOTSUPP;
6459         }
6460
6461         if (!hdev->fd_en) {
6462                 dev_err(&hdev->pdev->dev,
6463                         "please enable flow director first\n");
6464                 return -EOPNOTSUPP;
6465         }
6466
6467         fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
6468
6469         ret = hclge_fd_check_spec(hdev, fs, &unused, &info);
6470         if (ret)
6471                 return ret;
6472
6473         ret = hclge_fd_parse_ring_cookie(hdev, fs->ring_cookie, &dst_vport_id,
6474                                          &action, &q_index);
6475         if (ret)
6476                 return ret;
6477
6478         rule = kzalloc(sizeof(*rule), GFP_KERNEL);
6479         if (!rule)
6480                 return -ENOMEM;
6481
6482         ret = hclge_fd_get_tuple(fs, rule, &info);
6483         if (ret) {
6484                 kfree(rule);
6485                 return ret;
6486         }
6487
6488         rule->flow_type = fs->flow_type;
6489         rule->location = fs->location;
6490         rule->unused_tuple = unused;
6491         rule->vf_id = dst_vport_id;
6492         rule->queue_id = q_index;
6493         rule->action = action;
6494         rule->rule_type = HCLGE_FD_EP_ACTIVE;
6495
6496         ret = hclge_add_fd_entry_common(hdev, rule);
6497         if (ret)
6498                 kfree(rule);
6499
6500         return ret;
6501 }
6502
6503 static int hclge_del_fd_entry(struct hnae3_handle *handle,
6504                               struct ethtool_rxnfc *cmd)
6505 {
6506         struct hclge_vport *vport = hclge_get_vport(handle);
6507         struct hclge_dev *hdev = vport->back;
6508         struct ethtool_rx_flow_spec *fs;
6509         int ret;
6510
6511         if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
6512                 return -EOPNOTSUPP;
6513
6514         fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
6515
6516         if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1])
6517                 return -EINVAL;
6518
6519         spin_lock_bh(&hdev->fd_rule_lock);
6520         if (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE ||
6521             !test_bit(fs->location, hdev->fd_bmap)) {
6522                 dev_err(&hdev->pdev->dev,
6523                         "Delete fail, rule %u is inexistent\n", fs->location);
6524                 spin_unlock_bh(&hdev->fd_rule_lock);
6525                 return -ENOENT;
6526         }
6527
6528         ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, fs->location,
6529                                    NULL, false);
6530         if (ret)
6531                 goto out;
6532
6533         hclge_update_fd_list(hdev, HCLGE_FD_DELETED, fs->location, NULL);
6534
6535 out:
6536         spin_unlock_bh(&hdev->fd_rule_lock);
6537         return ret;
6538 }
6539
6540 static void hclge_clear_fd_rules_in_list(struct hclge_dev *hdev,
6541                                          bool clear_list)
6542 {
6543         struct hclge_fd_rule *rule;
6544         struct hlist_node *node;
6545         u16 location;
6546
6547         spin_lock_bh(&hdev->fd_rule_lock);
6548
6549         for_each_set_bit(location, hdev->fd_bmap,
6550                          hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1])
6551                 hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, location,
6552                                      NULL, false);
6553
6554         if (clear_list) {
6555                 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list,
6556                                           rule_node) {
6557                         hlist_del(&rule->rule_node);
6558                         kfree(rule);
6559                 }
6560                 hdev->fd_active_type = HCLGE_FD_RULE_NONE;
6561                 hdev->hclge_fd_rule_num = 0;
6562                 bitmap_zero(hdev->fd_bmap,
6563                             hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]);
6564         }
6565
6566         spin_unlock_bh(&hdev->fd_rule_lock);
6567 }
6568
6569 static void hclge_del_all_fd_entries(struct hclge_dev *hdev)
6570 {
6571         if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
6572                 return;
6573
6574         hclge_clear_fd_rules_in_list(hdev, true);
6575         hclge_fd_disable_user_def(hdev);
6576 }
6577
6578 static int hclge_restore_fd_entries(struct hnae3_handle *handle)
6579 {
6580         struct hclge_vport *vport = hclge_get_vport(handle);
6581         struct hclge_dev *hdev = vport->back;
6582         struct hclge_fd_rule *rule;
6583         struct hlist_node *node;
6584
6585         /* Return ok here, because reset error handling will check this
6586          * return value. If error is returned here, the reset process will
6587          * fail.
6588          */
6589         if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
6590                 return 0;
6591
6592         /* if fd is disabled, should not restore it when reset */
6593         if (!hdev->fd_en)
6594                 return 0;
6595
6596         spin_lock_bh(&hdev->fd_rule_lock);
6597         hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
6598                 if (rule->state == HCLGE_FD_ACTIVE)
6599                         rule->state = HCLGE_FD_TO_ADD;
6600         }
6601         spin_unlock_bh(&hdev->fd_rule_lock);
6602         set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state);
6603
6604         return 0;
6605 }
6606
6607 static int hclge_get_fd_rule_cnt(struct hnae3_handle *handle,
6608                                  struct ethtool_rxnfc *cmd)
6609 {
6610         struct hclge_vport *vport = hclge_get_vport(handle);
6611         struct hclge_dev *hdev = vport->back;
6612
6613         if (!hnae3_ae_dev_fd_supported(hdev->ae_dev) || hclge_is_cls_flower_active(handle))
6614                 return -EOPNOTSUPP;
6615
6616         cmd->rule_cnt = hdev->hclge_fd_rule_num;
6617         cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1];
6618
6619         return 0;
6620 }
6621
6622 static void hclge_fd_get_tcpip4_info(struct hclge_fd_rule *rule,
6623                                      struct ethtool_tcpip4_spec *spec,
6624                                      struct ethtool_tcpip4_spec *spec_mask)
6625 {
6626         spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]);
6627         spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ?
6628                         0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]);
6629
6630         spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]);
6631         spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ?
6632                         0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]);
6633
6634         spec->psrc = cpu_to_be16(rule->tuples.src_port);
6635         spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ?
6636                         0 : cpu_to_be16(rule->tuples_mask.src_port);
6637
6638         spec->pdst = cpu_to_be16(rule->tuples.dst_port);
6639         spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ?
6640                         0 : cpu_to_be16(rule->tuples_mask.dst_port);
6641
6642         spec->tos = rule->tuples.ip_tos;
6643         spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ?
6644                         0 : rule->tuples_mask.ip_tos;
6645 }
6646
6647 static void hclge_fd_get_ip4_info(struct hclge_fd_rule *rule,
6648                                   struct ethtool_usrip4_spec *spec,
6649                                   struct ethtool_usrip4_spec *spec_mask)
6650 {
6651         spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]);
6652         spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ?
6653                         0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]);
6654
6655         spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]);
6656         spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ?
6657                         0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]);
6658
6659         spec->tos = rule->tuples.ip_tos;
6660         spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ?
6661                         0 : rule->tuples_mask.ip_tos;
6662
6663         spec->proto = rule->tuples.ip_proto;
6664         spec_mask->proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ?
6665                         0 : rule->tuples_mask.ip_proto;
6666
6667         spec->ip_ver = ETH_RX_NFC_IP4;
6668 }
6669
6670 static void hclge_fd_get_tcpip6_info(struct hclge_fd_rule *rule,
6671                                      struct ethtool_tcpip6_spec *spec,
6672                                      struct ethtool_tcpip6_spec *spec_mask)
6673 {
6674         cpu_to_be32_array(spec->ip6src,
6675                           rule->tuples.src_ip, IPV6_SIZE);
6676         cpu_to_be32_array(spec->ip6dst,
6677                           rule->tuples.dst_ip, IPV6_SIZE);
6678         if (rule->unused_tuple & BIT(INNER_SRC_IP))
6679                 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src));
6680         else
6681                 cpu_to_be32_array(spec_mask->ip6src, rule->tuples_mask.src_ip,
6682                                   IPV6_SIZE);
6683
6684         if (rule->unused_tuple & BIT(INNER_DST_IP))
6685                 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst));
6686         else
6687                 cpu_to_be32_array(spec_mask->ip6dst, rule->tuples_mask.dst_ip,
6688                                   IPV6_SIZE);
6689
6690         spec->tclass = rule->tuples.ip_tos;
6691         spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ?
6692                         0 : rule->tuples_mask.ip_tos;
6693
6694         spec->psrc = cpu_to_be16(rule->tuples.src_port);
6695         spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ?
6696                         0 : cpu_to_be16(rule->tuples_mask.src_port);
6697
6698         spec->pdst = cpu_to_be16(rule->tuples.dst_port);
6699         spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ?
6700                         0 : cpu_to_be16(rule->tuples_mask.dst_port);
6701 }
6702
6703 static void hclge_fd_get_ip6_info(struct hclge_fd_rule *rule,
6704                                   struct ethtool_usrip6_spec *spec,
6705                                   struct ethtool_usrip6_spec *spec_mask)
6706 {
6707         cpu_to_be32_array(spec->ip6src, rule->tuples.src_ip, IPV6_SIZE);
6708         cpu_to_be32_array(spec->ip6dst, rule->tuples.dst_ip, IPV6_SIZE);
6709         if (rule->unused_tuple & BIT(INNER_SRC_IP))
6710                 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src));
6711         else
6712                 cpu_to_be32_array(spec_mask->ip6src,
6713                                   rule->tuples_mask.src_ip, IPV6_SIZE);
6714
6715         if (rule->unused_tuple & BIT(INNER_DST_IP))
6716                 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst));
6717         else
6718                 cpu_to_be32_array(spec_mask->ip6dst,
6719                                   rule->tuples_mask.dst_ip, IPV6_SIZE);
6720
6721         spec->tclass = rule->tuples.ip_tos;
6722         spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ?
6723                         0 : rule->tuples_mask.ip_tos;
6724
6725         spec->l4_proto = rule->tuples.ip_proto;
6726         spec_mask->l4_proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ?
6727                         0 : rule->tuples_mask.ip_proto;
6728 }
6729
6730 static void hclge_fd_get_ether_info(struct hclge_fd_rule *rule,
6731                                     struct ethhdr *spec,
6732                                     struct ethhdr *spec_mask)
6733 {
6734         ether_addr_copy(spec->h_source, rule->tuples.src_mac);
6735         ether_addr_copy(spec->h_dest, rule->tuples.dst_mac);
6736
6737         if (rule->unused_tuple & BIT(INNER_SRC_MAC))
6738                 eth_zero_addr(spec_mask->h_source);
6739         else
6740                 ether_addr_copy(spec_mask->h_source, rule->tuples_mask.src_mac);
6741
6742         if (rule->unused_tuple & BIT(INNER_DST_MAC))
6743                 eth_zero_addr(spec_mask->h_dest);
6744         else
6745                 ether_addr_copy(spec_mask->h_dest, rule->tuples_mask.dst_mac);
6746
6747         spec->h_proto = cpu_to_be16(rule->tuples.ether_proto);
6748         spec_mask->h_proto = rule->unused_tuple & BIT(INNER_ETH_TYPE) ?
6749                         0 : cpu_to_be16(rule->tuples_mask.ether_proto);
6750 }
6751
6752 static void hclge_fd_get_user_def_info(struct ethtool_rx_flow_spec *fs,
6753                                        struct hclge_fd_rule *rule)
6754 {
6755         if ((rule->unused_tuple & HCLGE_FD_TUPLE_USER_DEF_TUPLES) ==
6756             HCLGE_FD_TUPLE_USER_DEF_TUPLES) {
6757                 fs->h_ext.data[0] = 0;
6758                 fs->h_ext.data[1] = 0;
6759                 fs->m_ext.data[0] = 0;
6760                 fs->m_ext.data[1] = 0;
6761         } else {
6762                 fs->h_ext.data[0] = cpu_to_be32(rule->ep.user_def.offset);
6763                 fs->h_ext.data[1] = cpu_to_be32(rule->ep.user_def.data);
6764                 fs->m_ext.data[0] =
6765                                 cpu_to_be32(HCLGE_FD_USER_DEF_OFFSET_UNMASK);
6766                 fs->m_ext.data[1] = cpu_to_be32(rule->ep.user_def.data_mask);
6767         }
6768 }
6769
6770 static void hclge_fd_get_ext_info(struct ethtool_rx_flow_spec *fs,
6771                                   struct hclge_fd_rule *rule)
6772 {
6773         if (fs->flow_type & FLOW_EXT) {
6774                 fs->h_ext.vlan_tci = cpu_to_be16(rule->tuples.vlan_tag1);
6775                 fs->m_ext.vlan_tci =
6776                                 rule->unused_tuple & BIT(INNER_VLAN_TAG_FST) ?
6777                                 0 : cpu_to_be16(rule->tuples_mask.vlan_tag1);
6778
6779                 hclge_fd_get_user_def_info(fs, rule);
6780         }
6781
6782         if (fs->flow_type & FLOW_MAC_EXT) {
6783                 ether_addr_copy(fs->h_ext.h_dest, rule->tuples.dst_mac);
6784                 if (rule->unused_tuple & BIT(INNER_DST_MAC))
6785                         eth_zero_addr(fs->m_u.ether_spec.h_dest);
6786                 else
6787                         ether_addr_copy(fs->m_u.ether_spec.h_dest,
6788                                         rule->tuples_mask.dst_mac);
6789         }
6790 }
6791
6792 static struct hclge_fd_rule *hclge_get_fd_rule(struct hclge_dev *hdev,
6793                                                u16 location)
6794 {
6795         struct hclge_fd_rule *rule = NULL;
6796         struct hlist_node *node2;
6797
6798         hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) {
6799                 if (rule->location == location)
6800                         return rule;
6801                 else if (rule->location > location)
6802                         return NULL;
6803         }
6804
6805         return NULL;
6806 }
6807
6808 static void hclge_fd_get_ring_cookie(struct ethtool_rx_flow_spec *fs,
6809                                      struct hclge_fd_rule *rule)
6810 {
6811         if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) {
6812                 fs->ring_cookie = RX_CLS_FLOW_DISC;
6813         } else {
6814                 u64 vf_id;
6815
6816                 fs->ring_cookie = rule->queue_id;
6817                 vf_id = rule->vf_id;
6818                 vf_id <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
6819                 fs->ring_cookie |= vf_id;
6820         }
6821 }
6822
6823 static int hclge_get_fd_rule_info(struct hnae3_handle *handle,
6824                                   struct ethtool_rxnfc *cmd)
6825 {
6826         struct hclge_vport *vport = hclge_get_vport(handle);
6827         struct hclge_fd_rule *rule = NULL;
6828         struct hclge_dev *hdev = vport->back;
6829         struct ethtool_rx_flow_spec *fs;
6830
6831         if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
6832                 return -EOPNOTSUPP;
6833
6834         fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
6835
6836         spin_lock_bh(&hdev->fd_rule_lock);
6837
6838         rule = hclge_get_fd_rule(hdev, fs->location);
6839         if (!rule) {
6840                 spin_unlock_bh(&hdev->fd_rule_lock);
6841                 return -ENOENT;
6842         }
6843
6844         fs->flow_type = rule->flow_type;
6845         switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
6846         case SCTP_V4_FLOW:
6847         case TCP_V4_FLOW:
6848         case UDP_V4_FLOW:
6849                 hclge_fd_get_tcpip4_info(rule, &fs->h_u.tcp_ip4_spec,
6850                                          &fs->m_u.tcp_ip4_spec);
6851                 break;
6852         case IP_USER_FLOW:
6853                 hclge_fd_get_ip4_info(rule, &fs->h_u.usr_ip4_spec,
6854                                       &fs->m_u.usr_ip4_spec);
6855                 break;
6856         case SCTP_V6_FLOW:
6857         case TCP_V6_FLOW:
6858         case UDP_V6_FLOW:
6859                 hclge_fd_get_tcpip6_info(rule, &fs->h_u.tcp_ip6_spec,
6860                                          &fs->m_u.tcp_ip6_spec);
6861                 break;
6862         case IPV6_USER_FLOW:
6863                 hclge_fd_get_ip6_info(rule, &fs->h_u.usr_ip6_spec,
6864                                       &fs->m_u.usr_ip6_spec);
6865                 break;
6866         /* The flow type of fd rule has been checked before adding in to rule
6867          * list. As other flow types have been handled, it must be ETHER_FLOW
6868          * for the default case
6869          */
6870         default:
6871                 hclge_fd_get_ether_info(rule, &fs->h_u.ether_spec,
6872                                         &fs->m_u.ether_spec);
6873                 break;
6874         }
6875
6876         hclge_fd_get_ext_info(fs, rule);
6877
6878         hclge_fd_get_ring_cookie(fs, rule);
6879
6880         spin_unlock_bh(&hdev->fd_rule_lock);
6881
6882         return 0;
6883 }
6884
6885 static int hclge_get_all_rules(struct hnae3_handle *handle,
6886                                struct ethtool_rxnfc *cmd, u32 *rule_locs)
6887 {
6888         struct hclge_vport *vport = hclge_get_vport(handle);
6889         struct hclge_dev *hdev = vport->back;
6890         struct hclge_fd_rule *rule;
6891         struct hlist_node *node2;
6892         int cnt = 0;
6893
6894         if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
6895                 return -EOPNOTSUPP;
6896
6897         cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1];
6898
6899         spin_lock_bh(&hdev->fd_rule_lock);
6900         hlist_for_each_entry_safe(rule, node2,
6901                                   &hdev->fd_rule_list, rule_node) {
6902                 if (cnt == cmd->rule_cnt) {
6903                         spin_unlock_bh(&hdev->fd_rule_lock);
6904                         return -EMSGSIZE;
6905                 }
6906
6907                 if (rule->state == HCLGE_FD_TO_DEL)
6908                         continue;
6909
6910                 rule_locs[cnt] = rule->location;
6911                 cnt++;
6912         }
6913
6914         spin_unlock_bh(&hdev->fd_rule_lock);
6915
6916         cmd->rule_cnt = cnt;
6917
6918         return 0;
6919 }
6920
6921 static void hclge_fd_get_flow_tuples(const struct flow_keys *fkeys,
6922                                      struct hclge_fd_rule_tuples *tuples)
6923 {
6924 #define flow_ip6_src fkeys->addrs.v6addrs.src.in6_u.u6_addr32
6925 #define flow_ip6_dst fkeys->addrs.v6addrs.dst.in6_u.u6_addr32
6926
6927         tuples->ether_proto = be16_to_cpu(fkeys->basic.n_proto);
6928         tuples->ip_proto = fkeys->basic.ip_proto;
6929         tuples->dst_port = be16_to_cpu(fkeys->ports.dst);
6930
6931         if (fkeys->basic.n_proto == htons(ETH_P_IP)) {
6932                 tuples->src_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.src);
6933                 tuples->dst_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.dst);
6934         } else {
6935                 int i;
6936
6937                 for (i = 0; i < IPV6_SIZE; i++) {
6938                         tuples->src_ip[i] = be32_to_cpu(flow_ip6_src[i]);
6939                         tuples->dst_ip[i] = be32_to_cpu(flow_ip6_dst[i]);
6940                 }
6941         }
6942 }
6943
6944 /* traverse all rules, check whether an existed rule has the same tuples */
6945 static struct hclge_fd_rule *
6946 hclge_fd_search_flow_keys(struct hclge_dev *hdev,
6947                           const struct hclge_fd_rule_tuples *tuples)
6948 {
6949         struct hclge_fd_rule *rule = NULL;
6950         struct hlist_node *node;
6951
6952         hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
6953                 if (!memcmp(tuples, &rule->tuples, sizeof(*tuples)))
6954                         return rule;
6955         }
6956
6957         return NULL;
6958 }
6959
6960 static void hclge_fd_build_arfs_rule(const struct hclge_fd_rule_tuples *tuples,
6961                                      struct hclge_fd_rule *rule)
6962 {
6963         rule->unused_tuple = BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
6964                              BIT(INNER_VLAN_TAG_FST) | BIT(INNER_IP_TOS) |
6965                              BIT(INNER_SRC_PORT);
6966         rule->action = 0;
6967         rule->vf_id = 0;
6968         rule->rule_type = HCLGE_FD_ARFS_ACTIVE;
6969         rule->state = HCLGE_FD_TO_ADD;
6970         if (tuples->ether_proto == ETH_P_IP) {
6971                 if (tuples->ip_proto == IPPROTO_TCP)
6972                         rule->flow_type = TCP_V4_FLOW;
6973                 else
6974                         rule->flow_type = UDP_V4_FLOW;
6975         } else {
6976                 if (tuples->ip_proto == IPPROTO_TCP)
6977                         rule->flow_type = TCP_V6_FLOW;
6978                 else
6979                         rule->flow_type = UDP_V6_FLOW;
6980         }
6981         memcpy(&rule->tuples, tuples, sizeof(rule->tuples));
6982         memset(&rule->tuples_mask, 0xFF, sizeof(rule->tuples_mask));
6983 }
6984
6985 static int hclge_add_fd_entry_by_arfs(struct hnae3_handle *handle, u16 queue_id,
6986                                       u16 flow_id, struct flow_keys *fkeys)
6987 {
6988         struct hclge_vport *vport = hclge_get_vport(handle);
6989         struct hclge_fd_rule_tuples new_tuples = {};
6990         struct hclge_dev *hdev = vport->back;
6991         struct hclge_fd_rule *rule;
6992         u16 bit_id;
6993
6994         if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
6995                 return -EOPNOTSUPP;
6996
6997         /* when there is already fd rule existed add by user,
6998          * arfs should not work
6999          */
7000         spin_lock_bh(&hdev->fd_rule_lock);
7001         if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE &&
7002             hdev->fd_active_type != HCLGE_FD_RULE_NONE) {
7003                 spin_unlock_bh(&hdev->fd_rule_lock);
7004                 return -EOPNOTSUPP;
7005         }
7006
7007         hclge_fd_get_flow_tuples(fkeys, &new_tuples);
7008
7009         /* check is there flow director filter existed for this flow,
7010          * if not, create a new filter for it;
7011          * if filter exist with different queue id, modify the filter;
7012          * if filter exist with same queue id, do nothing
7013          */
7014         rule = hclge_fd_search_flow_keys(hdev, &new_tuples);
7015         if (!rule) {
7016                 bit_id = find_first_zero_bit(hdev->fd_bmap, MAX_FD_FILTER_NUM);
7017                 if (bit_id >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) {
7018                         spin_unlock_bh(&hdev->fd_rule_lock);
7019                         return -ENOSPC;
7020                 }
7021
7022                 rule = kzalloc(sizeof(*rule), GFP_ATOMIC);
7023                 if (!rule) {
7024                         spin_unlock_bh(&hdev->fd_rule_lock);
7025                         return -ENOMEM;
7026                 }
7027
7028                 rule->location = bit_id;
7029                 rule->arfs.flow_id = flow_id;
7030                 rule->queue_id = queue_id;
7031                 hclge_fd_build_arfs_rule(&new_tuples, rule);
7032                 hclge_update_fd_list(hdev, rule->state, rule->location, rule);
7033                 hdev->fd_active_type = HCLGE_FD_ARFS_ACTIVE;
7034         } else if (rule->queue_id != queue_id) {
7035                 rule->queue_id = queue_id;
7036                 rule->state = HCLGE_FD_TO_ADD;
7037                 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state);
7038                 hclge_task_schedule(hdev, 0);
7039         }
7040         spin_unlock_bh(&hdev->fd_rule_lock);
7041         return rule->location;
7042 }
7043
7044 static void hclge_rfs_filter_expire(struct hclge_dev *hdev)
7045 {
7046 #ifdef CONFIG_RFS_ACCEL
7047         struct hnae3_handle *handle = &hdev->vport[0].nic;
7048         struct hclge_fd_rule *rule;
7049         struct hlist_node *node;
7050
7051         spin_lock_bh(&hdev->fd_rule_lock);
7052         if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) {
7053                 spin_unlock_bh(&hdev->fd_rule_lock);
7054                 return;
7055         }
7056         hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
7057                 if (rule->state != HCLGE_FD_ACTIVE)
7058                         continue;
7059                 if (rps_may_expire_flow(handle->netdev, rule->queue_id,
7060                                         rule->arfs.flow_id, rule->location)) {
7061                         rule->state = HCLGE_FD_TO_DEL;
7062                         set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state);
7063                 }
7064         }
7065         spin_unlock_bh(&hdev->fd_rule_lock);
7066 #endif
7067 }
7068
7069 /* make sure being called after lock up with fd_rule_lock */
7070 static int hclge_clear_arfs_rules(struct hclge_dev *hdev)
7071 {
7072 #ifdef CONFIG_RFS_ACCEL
7073         struct hclge_fd_rule *rule;
7074         struct hlist_node *node;
7075         int ret;
7076
7077         if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE)
7078                 return 0;
7079
7080         hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
7081                 switch (rule->state) {
7082                 case HCLGE_FD_TO_DEL:
7083                 case HCLGE_FD_ACTIVE:
7084                         ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
7085                                                    rule->location, NULL, false);
7086                         if (ret)
7087                                 return ret;
7088                         fallthrough;
7089                 case HCLGE_FD_TO_ADD:
7090                         hclge_fd_dec_rule_cnt(hdev, rule->location);
7091                         hlist_del(&rule->rule_node);
7092                         kfree(rule);
7093                         break;
7094                 default:
7095                         break;
7096                 }
7097         }
7098         hclge_sync_fd_state(hdev);
7099
7100 #endif
7101         return 0;
7102 }
7103
7104 static void hclge_get_cls_key_basic(const struct flow_rule *flow,
7105                                     struct hclge_fd_rule *rule)
7106 {
7107         if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_BASIC)) {
7108                 struct flow_match_basic match;
7109                 u16 ethtype_key, ethtype_mask;
7110
7111                 flow_rule_match_basic(flow, &match);
7112                 ethtype_key = ntohs(match.key->n_proto);
7113                 ethtype_mask = ntohs(match.mask->n_proto);
7114
7115                 if (ethtype_key == ETH_P_ALL) {
7116                         ethtype_key = 0;
7117                         ethtype_mask = 0;
7118                 }
7119                 rule->tuples.ether_proto = ethtype_key;
7120                 rule->tuples_mask.ether_proto = ethtype_mask;
7121                 rule->tuples.ip_proto = match.key->ip_proto;
7122                 rule->tuples_mask.ip_proto = match.mask->ip_proto;
7123         } else {
7124                 rule->unused_tuple |= BIT(INNER_IP_PROTO);
7125                 rule->unused_tuple |= BIT(INNER_ETH_TYPE);
7126         }
7127 }
7128
7129 static void hclge_get_cls_key_mac(const struct flow_rule *flow,
7130                                   struct hclge_fd_rule *rule)
7131 {
7132         if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
7133                 struct flow_match_eth_addrs match;
7134
7135                 flow_rule_match_eth_addrs(flow, &match);
7136                 ether_addr_copy(rule->tuples.dst_mac, match.key->dst);
7137                 ether_addr_copy(rule->tuples_mask.dst_mac, match.mask->dst);
7138                 ether_addr_copy(rule->tuples.src_mac, match.key->src);
7139                 ether_addr_copy(rule->tuples_mask.src_mac, match.mask->src);
7140         } else {
7141                 rule->unused_tuple |= BIT(INNER_DST_MAC);
7142                 rule->unused_tuple |= BIT(INNER_SRC_MAC);
7143         }
7144 }
7145
7146 static void hclge_get_cls_key_vlan(const struct flow_rule *flow,
7147                                    struct hclge_fd_rule *rule)
7148 {
7149         if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_VLAN)) {
7150                 struct flow_match_vlan match;
7151
7152                 flow_rule_match_vlan(flow, &match);
7153                 rule->tuples.vlan_tag1 = match.key->vlan_id |
7154                                 (match.key->vlan_priority << VLAN_PRIO_SHIFT);
7155                 rule->tuples_mask.vlan_tag1 = match.mask->vlan_id |
7156                                 (match.mask->vlan_priority << VLAN_PRIO_SHIFT);
7157         } else {
7158                 rule->unused_tuple |= BIT(INNER_VLAN_TAG_FST);
7159         }
7160 }
7161
7162 static void hclge_get_cls_key_ip(const struct flow_rule *flow,
7163                                  struct hclge_fd_rule *rule)
7164 {
7165         u16 addr_type = 0;
7166
7167         if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_CONTROL)) {
7168                 struct flow_match_control match;
7169
7170                 flow_rule_match_control(flow, &match);
7171                 addr_type = match.key->addr_type;
7172         }
7173
7174         if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
7175                 struct flow_match_ipv4_addrs match;
7176
7177                 flow_rule_match_ipv4_addrs(flow, &match);
7178                 rule->tuples.src_ip[IPV4_INDEX] = be32_to_cpu(match.key->src);
7179                 rule->tuples_mask.src_ip[IPV4_INDEX] =
7180                                                 be32_to_cpu(match.mask->src);
7181                 rule->tuples.dst_ip[IPV4_INDEX] = be32_to_cpu(match.key->dst);
7182                 rule->tuples_mask.dst_ip[IPV4_INDEX] =
7183                                                 be32_to_cpu(match.mask->dst);
7184         } else if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
7185                 struct flow_match_ipv6_addrs match;
7186
7187                 flow_rule_match_ipv6_addrs(flow, &match);
7188                 be32_to_cpu_array(rule->tuples.src_ip, match.key->src.s6_addr32,
7189                                   IPV6_SIZE);
7190                 be32_to_cpu_array(rule->tuples_mask.src_ip,
7191                                   match.mask->src.s6_addr32, IPV6_SIZE);
7192                 be32_to_cpu_array(rule->tuples.dst_ip, match.key->dst.s6_addr32,
7193                                   IPV6_SIZE);
7194                 be32_to_cpu_array(rule->tuples_mask.dst_ip,
7195                                   match.mask->dst.s6_addr32, IPV6_SIZE);
7196         } else {
7197                 rule->unused_tuple |= BIT(INNER_SRC_IP);
7198                 rule->unused_tuple |= BIT(INNER_DST_IP);
7199         }
7200 }
7201
7202 static void hclge_get_cls_key_port(const struct flow_rule *flow,
7203                                    struct hclge_fd_rule *rule)
7204 {
7205         if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_PORTS)) {
7206                 struct flow_match_ports match;
7207
7208                 flow_rule_match_ports(flow, &match);
7209
7210                 rule->tuples.src_port = be16_to_cpu(match.key->src);
7211                 rule->tuples_mask.src_port = be16_to_cpu(match.mask->src);
7212                 rule->tuples.dst_port = be16_to_cpu(match.key->dst);
7213                 rule->tuples_mask.dst_port = be16_to_cpu(match.mask->dst);
7214         } else {
7215                 rule->unused_tuple |= BIT(INNER_SRC_PORT);
7216                 rule->unused_tuple |= BIT(INNER_DST_PORT);
7217         }
7218 }
7219
7220 static int hclge_parse_cls_flower(struct hclge_dev *hdev,
7221                                   struct flow_cls_offload *cls_flower,
7222                                   struct hclge_fd_rule *rule)
7223 {
7224         struct flow_rule *flow = flow_cls_offload_flow_rule(cls_flower);
7225         struct flow_dissector *dissector = flow->match.dissector;
7226
7227         if (dissector->used_keys &
7228             ~(BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
7229               BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
7230               BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
7231               BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) |
7232               BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
7233               BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
7234               BIT_ULL(FLOW_DISSECTOR_KEY_PORTS))) {
7235                 dev_err(&hdev->pdev->dev, "unsupported key set: %#llx\n",
7236                         dissector->used_keys);
7237                 return -EOPNOTSUPP;
7238         }
7239
7240         hclge_get_cls_key_basic(flow, rule);
7241         hclge_get_cls_key_mac(flow, rule);
7242         hclge_get_cls_key_vlan(flow, rule);
7243         hclge_get_cls_key_ip(flow, rule);
7244         hclge_get_cls_key_port(flow, rule);
7245
7246         return 0;
7247 }
7248
7249 static int hclge_check_cls_flower(struct hclge_dev *hdev,
7250                                   struct flow_cls_offload *cls_flower, int tc)
7251 {
7252         u32 prio = cls_flower->common.prio;
7253
7254         if (tc < 0 || tc > hdev->tc_max) {
7255                 dev_err(&hdev->pdev->dev, "invalid traffic class\n");
7256                 return -EINVAL;
7257         }
7258
7259         if (prio == 0 ||
7260             prio > hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) {
7261                 dev_err(&hdev->pdev->dev,
7262                         "prio %u should be in range[1, %u]\n",
7263                         prio, hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]);
7264                 return -EINVAL;
7265         }
7266
7267         if (test_bit(prio - 1, hdev->fd_bmap)) {
7268                 dev_err(&hdev->pdev->dev, "prio %u is already used\n", prio);
7269                 return -EINVAL;
7270         }
7271         return 0;
7272 }
7273
7274 static int hclge_add_cls_flower(struct hnae3_handle *handle,
7275                                 struct flow_cls_offload *cls_flower,
7276                                 int tc)
7277 {
7278         struct hclge_vport *vport = hclge_get_vport(handle);
7279         struct hclge_dev *hdev = vport->back;
7280         struct hclge_fd_rule *rule;
7281         int ret;
7282
7283         if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) {
7284                 dev_err(&hdev->pdev->dev,
7285                         "cls flower is not supported\n");
7286                 return -EOPNOTSUPP;
7287         }
7288
7289         ret = hclge_check_cls_flower(hdev, cls_flower, tc);
7290         if (ret) {
7291                 dev_err(&hdev->pdev->dev,
7292                         "failed to check cls flower params, ret = %d\n", ret);
7293                 return ret;
7294         }
7295
7296         rule = kzalloc(sizeof(*rule), GFP_KERNEL);
7297         if (!rule)
7298                 return -ENOMEM;
7299
7300         ret = hclge_parse_cls_flower(hdev, cls_flower, rule);
7301         if (ret) {
7302                 kfree(rule);
7303                 return ret;
7304         }
7305
7306         rule->action = HCLGE_FD_ACTION_SELECT_TC;
7307         rule->cls_flower.tc = tc;
7308         rule->location = cls_flower->common.prio - 1;
7309         rule->vf_id = 0;
7310         rule->cls_flower.cookie = cls_flower->cookie;
7311         rule->rule_type = HCLGE_FD_TC_FLOWER_ACTIVE;
7312
7313         ret = hclge_add_fd_entry_common(hdev, rule);
7314         if (ret)
7315                 kfree(rule);
7316
7317         return ret;
7318 }
7319
7320 static struct hclge_fd_rule *hclge_find_cls_flower(struct hclge_dev *hdev,
7321                                                    unsigned long cookie)
7322 {
7323         struct hclge_fd_rule *rule;
7324         struct hlist_node *node;
7325
7326         hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
7327                 if (rule->cls_flower.cookie == cookie)
7328                         return rule;
7329         }
7330
7331         return NULL;
7332 }
7333
7334 static int hclge_del_cls_flower(struct hnae3_handle *handle,
7335                                 struct flow_cls_offload *cls_flower)
7336 {
7337         struct hclge_vport *vport = hclge_get_vport(handle);
7338         struct hclge_dev *hdev = vport->back;
7339         struct hclge_fd_rule *rule;
7340         int ret;
7341
7342         if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
7343                 return -EOPNOTSUPP;
7344
7345         spin_lock_bh(&hdev->fd_rule_lock);
7346
7347         rule = hclge_find_cls_flower(hdev, cls_flower->cookie);
7348         if (!rule) {
7349                 spin_unlock_bh(&hdev->fd_rule_lock);
7350                 return -EINVAL;
7351         }
7352
7353         ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, rule->location,
7354                                    NULL, false);
7355         if (ret) {
7356                 /* if tcam config fail, set rule state to TO_DEL,
7357                  * so the rule will be deleted when periodic
7358                  * task being scheduled.
7359                  */
7360                 hclge_update_fd_list(hdev, HCLGE_FD_TO_DEL, rule->location, NULL);
7361                 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state);
7362                 spin_unlock_bh(&hdev->fd_rule_lock);
7363                 return ret;
7364         }
7365
7366         hclge_update_fd_list(hdev, HCLGE_FD_DELETED, rule->location, NULL);
7367         spin_unlock_bh(&hdev->fd_rule_lock);
7368
7369         return 0;
7370 }
7371
7372 static void hclge_sync_fd_list(struct hclge_dev *hdev, struct hlist_head *hlist)
7373 {
7374         struct hclge_fd_rule *rule;
7375         struct hlist_node *node;
7376         int ret = 0;
7377
7378         if (!test_and_clear_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state))
7379                 return;
7380
7381         spin_lock_bh(&hdev->fd_rule_lock);
7382
7383         hlist_for_each_entry_safe(rule, node, hlist, rule_node) {
7384                 switch (rule->state) {
7385                 case HCLGE_FD_TO_ADD:
7386                         ret = hclge_fd_config_rule(hdev, rule);
7387                         if (ret)
7388                                 goto out;
7389                         rule->state = HCLGE_FD_ACTIVE;
7390                         break;
7391                 case HCLGE_FD_TO_DEL:
7392                         ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
7393                                                    rule->location, NULL, false);
7394                         if (ret)
7395                                 goto out;
7396                         hclge_fd_dec_rule_cnt(hdev, rule->location);
7397                         hclge_fd_free_node(hdev, rule);
7398                         break;
7399                 default:
7400                         break;
7401                 }
7402         }
7403
7404 out:
7405         if (ret)
7406                 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state);
7407
7408         spin_unlock_bh(&hdev->fd_rule_lock);
7409 }
7410
7411 static void hclge_sync_fd_table(struct hclge_dev *hdev)
7412 {
7413         if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
7414                 return;
7415
7416         if (test_and_clear_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state)) {
7417                 bool clear_list = hdev->fd_active_type == HCLGE_FD_ARFS_ACTIVE;
7418
7419                 hclge_clear_fd_rules_in_list(hdev, clear_list);
7420         }
7421
7422         hclge_sync_fd_user_def_cfg(hdev, false);
7423
7424         hclge_sync_fd_list(hdev, &hdev->fd_rule_list);
7425 }
7426
7427 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle)
7428 {
7429         struct hclge_vport *vport = hclge_get_vport(handle);
7430         struct hclge_dev *hdev = vport->back;
7431
7432         return hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) ||
7433                hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING);
7434 }
7435
7436 static bool hclge_get_cmdq_stat(struct hnae3_handle *handle)
7437 {
7438         struct hclge_vport *vport = hclge_get_vport(handle);
7439         struct hclge_dev *hdev = vport->back;
7440
7441         return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
7442 }
7443
7444 static bool hclge_ae_dev_resetting(struct hnae3_handle *handle)
7445 {
7446         struct hclge_vport *vport = hclge_get_vport(handle);
7447         struct hclge_dev *hdev = vport->back;
7448
7449         return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
7450 }
7451
7452 static unsigned long hclge_ae_dev_reset_cnt(struct hnae3_handle *handle)
7453 {
7454         struct hclge_vport *vport = hclge_get_vport(handle);
7455         struct hclge_dev *hdev = vport->back;
7456
7457         return hdev->rst_stats.hw_reset_done_cnt;
7458 }
7459
7460 static void hclge_enable_fd(struct hnae3_handle *handle, bool enable)
7461 {
7462         struct hclge_vport *vport = hclge_get_vport(handle);
7463         struct hclge_dev *hdev = vport->back;
7464
7465         hdev->fd_en = enable;
7466
7467         if (!enable)
7468                 set_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state);
7469         else
7470                 hclge_restore_fd_entries(handle);
7471
7472         hclge_task_schedule(hdev, 0);
7473 }
7474
7475 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
7476 {
7477 #define HCLGE_LINK_STATUS_WAIT_CNT  3
7478
7479         struct hclge_desc desc;
7480         struct hclge_config_mac_mode_cmd *req =
7481                 (struct hclge_config_mac_mode_cmd *)desc.data;
7482         u32 loop_en = 0;
7483         int ret;
7484
7485         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
7486
7487         if (enable) {
7488                 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, 1U);
7489                 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, 1U);
7490                 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, 1U);
7491                 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, 1U);
7492                 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, 1U);
7493                 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, 1U);
7494                 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, 1U);
7495                 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, 1U);
7496                 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, 1U);
7497                 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, 1U);
7498         }
7499
7500         req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
7501
7502         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7503         if (ret) {
7504                 dev_err(&hdev->pdev->dev,
7505                         "mac enable fail, ret =%d.\n", ret);
7506                 return;
7507         }
7508
7509         if (!enable)
7510                 hclge_mac_link_status_wait(hdev, HCLGE_LINK_STATUS_DOWN,
7511                                            HCLGE_LINK_STATUS_WAIT_CNT);
7512 }
7513
7514 static int hclge_config_switch_param(struct hclge_dev *hdev, int vfid,
7515                                      u8 switch_param, u8 param_mask)
7516 {
7517         struct hclge_mac_vlan_switch_cmd *req;
7518         struct hclge_desc desc;
7519         u32 func_id;
7520         int ret;
7521
7522         func_id = hclge_get_port_number(HOST_PORT, 0, vfid, 0);
7523         req = (struct hclge_mac_vlan_switch_cmd *)desc.data;
7524
7525         /* read current config parameter */
7526         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_SWITCH_PARAM,
7527                                    true);
7528         req->roce_sel = HCLGE_MAC_VLAN_NIC_SEL;
7529         req->func_id = cpu_to_le32(func_id);
7530
7531         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7532         if (ret) {
7533                 dev_err(&hdev->pdev->dev,
7534                         "read mac vlan switch parameter fail, ret = %d\n", ret);
7535                 return ret;
7536         }
7537
7538         /* modify and write new config parameter */
7539         hclge_comm_cmd_reuse_desc(&desc, false);
7540         req->switch_param = (req->switch_param & param_mask) | switch_param;
7541         req->param_mask = param_mask;
7542
7543         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7544         if (ret)
7545                 dev_err(&hdev->pdev->dev,
7546                         "set mac vlan switch parameter fail, ret = %d\n", ret);
7547         return ret;
7548 }
7549
7550 static void hclge_phy_link_status_wait(struct hclge_dev *hdev,
7551                                        int link_ret)
7552 {
7553 #define HCLGE_PHY_LINK_STATUS_NUM  200
7554
7555         struct phy_device *phydev = hdev->hw.mac.phydev;
7556         int i = 0;
7557         int ret;
7558
7559         do {
7560                 ret = phy_read_status(phydev);
7561                 if (ret) {
7562                         dev_err(&hdev->pdev->dev,
7563                                 "phy update link status fail, ret = %d\n", ret);
7564                         return;
7565                 }
7566
7567                 if (phydev->link == link_ret)
7568                         break;
7569
7570                 msleep(HCLGE_LINK_STATUS_MS);
7571         } while (++i < HCLGE_PHY_LINK_STATUS_NUM);
7572 }
7573
7574 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret,
7575                                       int wait_cnt)
7576 {
7577         int link_status;
7578         int i = 0;
7579         int ret;
7580
7581         do {
7582                 ret = hclge_get_mac_link_status(hdev, &link_status);
7583                 if (ret)
7584                         return ret;
7585                 if (link_status == link_ret)
7586                         return 0;
7587
7588                 msleep(HCLGE_LINK_STATUS_MS);
7589         } while (++i < wait_cnt);
7590         return -EBUSY;
7591 }
7592
7593 static int hclge_mac_phy_link_status_wait(struct hclge_dev *hdev, bool en,
7594                                           bool is_phy)
7595 {
7596 #define HCLGE_MAC_LINK_STATUS_NUM  100
7597
7598         int link_ret;
7599
7600         link_ret = en ? HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN;
7601
7602         if (is_phy)
7603                 hclge_phy_link_status_wait(hdev, link_ret);
7604
7605         return hclge_mac_link_status_wait(hdev, link_ret,
7606                                           HCLGE_MAC_LINK_STATUS_NUM);
7607 }
7608
7609 static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en)
7610 {
7611         struct hclge_config_mac_mode_cmd *req;
7612         struct hclge_desc desc;
7613         u32 loop_en;
7614         int ret;
7615
7616         req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
7617         /* 1 Read out the MAC mode config at first */
7618         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
7619         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7620         if (ret) {
7621                 dev_err(&hdev->pdev->dev,
7622                         "mac loopback get fail, ret =%d.\n", ret);
7623                 return ret;
7624         }
7625
7626         /* 2 Then setup the loopback flag */
7627         loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
7628         hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0);
7629
7630         req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
7631
7632         /* 3 Config mac work mode with loopback flag
7633          * and its original configure parameters
7634          */
7635         hclge_comm_cmd_reuse_desc(&desc, false);
7636         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7637         if (ret)
7638                 dev_err(&hdev->pdev->dev,
7639                         "mac loopback set fail, ret =%d.\n", ret);
7640         return ret;
7641 }
7642
7643 static int hclge_cfg_common_loopback_cmd_send(struct hclge_dev *hdev, bool en,
7644                                               enum hnae3_loop loop_mode)
7645 {
7646         struct hclge_common_lb_cmd *req;
7647         struct hclge_desc desc;
7648         u8 loop_mode_b;
7649         int ret;
7650
7651         req = (struct hclge_common_lb_cmd *)desc.data;
7652         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, false);
7653
7654         switch (loop_mode) {
7655         case HNAE3_LOOP_SERIAL_SERDES:
7656                 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
7657                 break;
7658         case HNAE3_LOOP_PARALLEL_SERDES:
7659                 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B;
7660                 break;
7661         case HNAE3_LOOP_PHY:
7662                 loop_mode_b = HCLGE_CMD_GE_PHY_INNER_LOOP_B;
7663                 break;
7664         default:
7665                 dev_err(&hdev->pdev->dev,
7666                         "unsupported loopback mode %d\n", loop_mode);
7667                 return -ENOTSUPP;
7668         }
7669
7670         req->mask = loop_mode_b;
7671         if (en)
7672                 req->enable = loop_mode_b;
7673
7674         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7675         if (ret)
7676                 dev_err(&hdev->pdev->dev,
7677                         "failed to send loopback cmd, loop_mode = %d, ret = %d\n",
7678                         loop_mode, ret);
7679
7680         return ret;
7681 }
7682
7683 static int hclge_cfg_common_loopback_wait(struct hclge_dev *hdev)
7684 {
7685 #define HCLGE_COMMON_LB_RETRY_MS        10
7686 #define HCLGE_COMMON_LB_RETRY_NUM       100
7687
7688         struct hclge_common_lb_cmd *req;
7689         struct hclge_desc desc;
7690         u32 i = 0;
7691         int ret;
7692
7693         req = (struct hclge_common_lb_cmd *)desc.data;
7694
7695         do {
7696                 msleep(HCLGE_COMMON_LB_RETRY_MS);
7697                 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK,
7698                                            true);
7699                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7700                 if (ret) {
7701                         dev_err(&hdev->pdev->dev,
7702                                 "failed to get loopback done status, ret = %d\n",
7703                                 ret);
7704                         return ret;
7705                 }
7706         } while (++i < HCLGE_COMMON_LB_RETRY_NUM &&
7707                  !(req->result & HCLGE_CMD_COMMON_LB_DONE_B));
7708
7709         if (!(req->result & HCLGE_CMD_COMMON_LB_DONE_B)) {
7710                 dev_err(&hdev->pdev->dev, "wait loopback timeout\n");
7711                 return -EBUSY;
7712         } else if (!(req->result & HCLGE_CMD_COMMON_LB_SUCCESS_B)) {
7713                 dev_err(&hdev->pdev->dev, "failed to do loopback test\n");
7714                 return -EIO;
7715         }
7716
7717         return 0;
7718 }
7719
7720 static int hclge_cfg_common_loopback(struct hclge_dev *hdev, bool en,
7721                                      enum hnae3_loop loop_mode)
7722 {
7723         int ret;
7724
7725         ret = hclge_cfg_common_loopback_cmd_send(hdev, en, loop_mode);
7726         if (ret)
7727                 return ret;
7728
7729         return hclge_cfg_common_loopback_wait(hdev);
7730 }
7731
7732 static int hclge_set_common_loopback(struct hclge_dev *hdev, bool en,
7733                                      enum hnae3_loop loop_mode)
7734 {
7735         int ret;
7736
7737         ret = hclge_cfg_common_loopback(hdev, en, loop_mode);
7738         if (ret)
7739                 return ret;
7740
7741         hclge_cfg_mac_mode(hdev, en);
7742
7743         ret = hclge_mac_phy_link_status_wait(hdev, en, false);
7744         if (ret)
7745                 dev_err(&hdev->pdev->dev,
7746                         "serdes loopback config mac mode timeout\n");
7747
7748         return ret;
7749 }
7750
7751 static int hclge_enable_phy_loopback(struct hclge_dev *hdev,
7752                                      struct phy_device *phydev)
7753 {
7754         int ret;
7755
7756         if (!phydev->suspended) {
7757                 ret = phy_suspend(phydev);
7758                 if (ret)
7759                         return ret;
7760         }
7761
7762         ret = phy_resume(phydev);
7763         if (ret)
7764                 return ret;
7765
7766         return phy_loopback(phydev, true);
7767 }
7768
7769 static int hclge_disable_phy_loopback(struct hclge_dev *hdev,
7770                                       struct phy_device *phydev)
7771 {
7772         int ret;
7773
7774         ret = phy_loopback(phydev, false);
7775         if (ret)
7776                 return ret;
7777
7778         return phy_suspend(phydev);
7779 }
7780
7781 static int hclge_set_phy_loopback(struct hclge_dev *hdev, bool en)
7782 {
7783         struct phy_device *phydev = hdev->hw.mac.phydev;
7784         int ret;
7785
7786         if (!phydev) {
7787                 if (hnae3_dev_phy_imp_supported(hdev))
7788                         return hclge_set_common_loopback(hdev, en,
7789                                                          HNAE3_LOOP_PHY);
7790                 return -ENOTSUPP;
7791         }
7792
7793         if (en)
7794                 ret = hclge_enable_phy_loopback(hdev, phydev);
7795         else
7796                 ret = hclge_disable_phy_loopback(hdev, phydev);
7797         if (ret) {
7798                 dev_err(&hdev->pdev->dev,
7799                         "set phy loopback fail, ret = %d\n", ret);
7800                 return ret;
7801         }
7802
7803         hclge_cfg_mac_mode(hdev, en);
7804
7805         ret = hclge_mac_phy_link_status_wait(hdev, en, true);
7806         if (ret)
7807                 dev_err(&hdev->pdev->dev,
7808                         "phy loopback config mac mode timeout\n");
7809
7810         return ret;
7811 }
7812
7813 static int hclge_tqp_enable_cmd_send(struct hclge_dev *hdev, u16 tqp_id,
7814                                      u16 stream_id, bool enable)
7815 {
7816         struct hclge_desc desc;
7817         struct hclge_cfg_com_tqp_queue_cmd *req =
7818                 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
7819
7820         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
7821         req->tqp_id = cpu_to_le16(tqp_id);
7822         req->stream_id = cpu_to_le16(stream_id);
7823         if (enable)
7824                 req->enable |= 1U << HCLGE_TQP_ENABLE_B;
7825
7826         return hclge_cmd_send(&hdev->hw, &desc, 1);
7827 }
7828
7829 static int hclge_tqp_enable(struct hnae3_handle *handle, bool enable)
7830 {
7831         struct hclge_vport *vport = hclge_get_vport(handle);
7832         struct hclge_dev *hdev = vport->back;
7833         int ret;
7834         u16 i;
7835
7836         for (i = 0; i < handle->kinfo.num_tqps; i++) {
7837                 ret = hclge_tqp_enable_cmd_send(hdev, i, 0, enable);
7838                 if (ret)
7839                         return ret;
7840         }
7841         return 0;
7842 }
7843
7844 static int hclge_set_loopback(struct hnae3_handle *handle,
7845                               enum hnae3_loop loop_mode, bool en)
7846 {
7847         struct hclge_vport *vport = hclge_get_vport(handle);
7848         struct hclge_dev *hdev = vport->back;
7849         int ret = 0;
7850
7851         /* Loopback can be enabled in three places: SSU, MAC, and serdes. By
7852          * default, SSU loopback is enabled, so if the SMAC and the DMAC are
7853          * the same, the packets are looped back in the SSU. If SSU loopback
7854          * is disabled, packets can reach MAC even if SMAC is the same as DMAC.
7855          */
7856         if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
7857                 u8 switch_param = en ? 0 : BIT(HCLGE_SWITCH_ALW_LPBK_B);
7858
7859                 ret = hclge_config_switch_param(hdev, PF_VPORT_ID, switch_param,
7860                                                 HCLGE_SWITCH_ALW_LPBK_MASK);
7861                 if (ret)
7862                         return ret;
7863         }
7864
7865         switch (loop_mode) {
7866         case HNAE3_LOOP_APP:
7867                 ret = hclge_set_app_loopback(hdev, en);
7868                 break;
7869         case HNAE3_LOOP_SERIAL_SERDES:
7870         case HNAE3_LOOP_PARALLEL_SERDES:
7871                 ret = hclge_set_common_loopback(hdev, en, loop_mode);
7872                 break;
7873         case HNAE3_LOOP_PHY:
7874                 ret = hclge_set_phy_loopback(hdev, en);
7875                 break;
7876         case HNAE3_LOOP_EXTERNAL:
7877                 break;
7878         default:
7879                 ret = -ENOTSUPP;
7880                 dev_err(&hdev->pdev->dev,
7881                         "loop_mode %d is not supported\n", loop_mode);
7882                 break;
7883         }
7884
7885         if (ret)
7886                 return ret;
7887
7888         ret = hclge_tqp_enable(handle, en);
7889         if (ret)
7890                 dev_err(&hdev->pdev->dev, "failed to %s tqp in loopback, ret = %d\n",
7891                         en ? "enable" : "disable", ret);
7892
7893         return ret;
7894 }
7895
7896 static int hclge_set_default_loopback(struct hclge_dev *hdev)
7897 {
7898         int ret;
7899
7900         ret = hclge_set_app_loopback(hdev, false);
7901         if (ret)
7902                 return ret;
7903
7904         ret = hclge_cfg_common_loopback(hdev, false, HNAE3_LOOP_SERIAL_SERDES);
7905         if (ret)
7906                 return ret;
7907
7908         return hclge_cfg_common_loopback(hdev, false,
7909                                          HNAE3_LOOP_PARALLEL_SERDES);
7910 }
7911
7912 static void hclge_flush_link_update(struct hclge_dev *hdev)
7913 {
7914 #define HCLGE_FLUSH_LINK_TIMEOUT        100000
7915
7916         unsigned long last = hdev->serv_processed_cnt;
7917         int i = 0;
7918
7919         while (test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state) &&
7920                i++ < HCLGE_FLUSH_LINK_TIMEOUT &&
7921                last == hdev->serv_processed_cnt)
7922                 usleep_range(1, 1);
7923 }
7924
7925 static void hclge_set_timer_task(struct hnae3_handle *handle, bool enable)
7926 {
7927         struct hclge_vport *vport = hclge_get_vport(handle);
7928         struct hclge_dev *hdev = vport->back;
7929
7930         if (enable) {
7931                 hclge_task_schedule(hdev, 0);
7932         } else {
7933                 /* Set the DOWN flag here to disable link updating */
7934                 set_bit(HCLGE_STATE_DOWN, &hdev->state);
7935
7936                 /* flush memory to make sure DOWN is seen by service task */
7937                 smp_mb__before_atomic();
7938                 hclge_flush_link_update(hdev);
7939         }
7940 }
7941
7942 static int hclge_ae_start(struct hnae3_handle *handle)
7943 {
7944         struct hclge_vport *vport = hclge_get_vport(handle);
7945         struct hclge_dev *hdev = vport->back;
7946
7947         /* mac enable */
7948         hclge_cfg_mac_mode(hdev, true);
7949         clear_bit(HCLGE_STATE_DOWN, &hdev->state);
7950         hdev->hw.mac.link = 0;
7951
7952         /* reset tqp stats */
7953         hclge_comm_reset_tqp_stats(handle);
7954
7955         hclge_mac_start_phy(hdev);
7956
7957         return 0;
7958 }
7959
7960 static void hclge_ae_stop(struct hnae3_handle *handle)
7961 {
7962         struct hclge_vport *vport = hclge_get_vport(handle);
7963         struct hclge_dev *hdev = vport->back;
7964
7965         set_bit(HCLGE_STATE_DOWN, &hdev->state);
7966         spin_lock_bh(&hdev->fd_rule_lock);
7967         hclge_clear_arfs_rules(hdev);
7968         spin_unlock_bh(&hdev->fd_rule_lock);
7969
7970         /* If it is not PF reset or FLR, the firmware will disable the MAC,
7971          * so it only need to stop phy here.
7972          */
7973         if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) {
7974                 hclge_pfc_pause_en_cfg(hdev, HCLGE_PFC_TX_RX_DISABLE,
7975                                        HCLGE_PFC_DISABLE);
7976                 if (hdev->reset_type != HNAE3_FUNC_RESET &&
7977                     hdev->reset_type != HNAE3_FLR_RESET) {
7978                         hclge_mac_stop_phy(hdev);
7979                         hclge_update_link_status(hdev);
7980                         return;
7981                 }
7982         }
7983
7984         hclge_reset_tqp(handle);
7985
7986         hclge_config_mac_tnl_int(hdev, false);
7987
7988         /* Mac disable */
7989         hclge_cfg_mac_mode(hdev, false);
7990
7991         hclge_mac_stop_phy(hdev);
7992
7993         /* reset tqp stats */
7994         hclge_comm_reset_tqp_stats(handle);
7995         hclge_update_link_status(hdev);
7996 }
7997
7998 int hclge_vport_start(struct hclge_vport *vport)
7999 {
8000         struct hclge_dev *hdev = vport->back;
8001
8002         set_bit(HCLGE_VPORT_STATE_INITED, &vport->state);
8003         set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
8004         set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
8005         vport->last_active_jiffies = jiffies;
8006         vport->need_notify = 0;
8007
8008         if (test_bit(vport->vport_id, hdev->vport_config_block)) {
8009                 if (vport->vport_id) {
8010                         hclge_restore_mac_table_common(vport);
8011                         hclge_restore_vport_vlan_table(vport);
8012                 } else {
8013                         hclge_restore_hw_table(hdev);
8014                 }
8015         }
8016
8017         clear_bit(vport->vport_id, hdev->vport_config_block);
8018
8019         return 0;
8020 }
8021
8022 void hclge_vport_stop(struct hclge_vport *vport)
8023 {
8024         clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state);
8025         clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
8026         vport->need_notify = 0;
8027 }
8028
8029 static int hclge_client_start(struct hnae3_handle *handle)
8030 {
8031         struct hclge_vport *vport = hclge_get_vport(handle);
8032
8033         return hclge_vport_start(vport);
8034 }
8035
8036 static void hclge_client_stop(struct hnae3_handle *handle)
8037 {
8038         struct hclge_vport *vport = hclge_get_vport(handle);
8039
8040         hclge_vport_stop(vport);
8041 }
8042
8043 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
8044                                          u16 cmdq_resp, u8  resp_code,
8045                                          enum hclge_mac_vlan_tbl_opcode op)
8046 {
8047         struct hclge_dev *hdev = vport->back;
8048
8049         if (cmdq_resp) {
8050                 dev_err(&hdev->pdev->dev,
8051                         "cmdq execute failed for get_mac_vlan_cmd_status,status=%u.\n",
8052                         cmdq_resp);
8053                 return -EIO;
8054         }
8055
8056         if (op == HCLGE_MAC_VLAN_ADD) {
8057                 if (!resp_code || resp_code == 1)
8058                         return 0;
8059                 else if (resp_code == HCLGE_ADD_UC_OVERFLOW ||
8060                          resp_code == HCLGE_ADD_MC_OVERFLOW)
8061                         return -ENOSPC;
8062
8063                 dev_err(&hdev->pdev->dev,
8064                         "add mac addr failed for undefined, code=%u.\n",
8065                         resp_code);
8066                 return -EIO;
8067         } else if (op == HCLGE_MAC_VLAN_REMOVE) {
8068                 if (!resp_code) {
8069                         return 0;
8070                 } else if (resp_code == 1) {
8071                         dev_dbg(&hdev->pdev->dev,
8072                                 "remove mac addr failed for miss.\n");
8073                         return -ENOENT;
8074                 }
8075
8076                 dev_err(&hdev->pdev->dev,
8077                         "remove mac addr failed for undefined, code=%u.\n",
8078                         resp_code);
8079                 return -EIO;
8080         } else if (op == HCLGE_MAC_VLAN_LKUP) {
8081                 if (!resp_code) {
8082                         return 0;
8083                 } else if (resp_code == 1) {
8084                         dev_dbg(&hdev->pdev->dev,
8085                                 "lookup mac addr failed for miss.\n");
8086                         return -ENOENT;
8087                 }
8088
8089                 dev_err(&hdev->pdev->dev,
8090                         "lookup mac addr failed for undefined, code=%u.\n",
8091                         resp_code);
8092                 return -EIO;
8093         }
8094
8095         dev_err(&hdev->pdev->dev,
8096                 "unknown opcode for get_mac_vlan_cmd_status, opcode=%d.\n", op);
8097
8098         return -EINVAL;
8099 }
8100
8101 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
8102 {
8103 #define HCLGE_VF_NUM_IN_FIRST_DESC 192
8104
8105         unsigned int word_num;
8106         unsigned int bit_num;
8107
8108         if (vfid > 255 || vfid < 0)
8109                 return -EIO;
8110
8111         if (vfid >= 0 && vfid < HCLGE_VF_NUM_IN_FIRST_DESC) {
8112                 word_num = vfid / 32;
8113                 bit_num  = vfid % 32;
8114                 if (clr)
8115                         desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
8116                 else
8117                         desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
8118         } else {
8119                 word_num = (vfid - HCLGE_VF_NUM_IN_FIRST_DESC) / 32;
8120                 bit_num  = vfid % 32;
8121                 if (clr)
8122                         desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
8123                 else
8124                         desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
8125         }
8126
8127         return 0;
8128 }
8129
8130 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
8131 {
8132 #define HCLGE_DESC_NUMBER 3
8133 #define HCLGE_FUNC_NUMBER_PER_DESC 6
8134         int i, j;
8135
8136         for (i = 1; i < HCLGE_DESC_NUMBER; i++)
8137                 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
8138                         if (desc[i].data[j])
8139                                 return false;
8140
8141         return true;
8142 }
8143
8144 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
8145                                    const u8 *addr, bool is_mc)
8146 {
8147         const unsigned char *mac_addr = addr;
8148         u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
8149                        (mac_addr[0]) | (mac_addr[1] << 8);
8150         u32 low_val  = mac_addr[4] | (mac_addr[5] << 8);
8151
8152         hnae3_set_bit(new_req->flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
8153         if (is_mc) {
8154                 hnae3_set_bit(new_req->entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
8155                 hnae3_set_bit(new_req->mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
8156         }
8157
8158         new_req->mac_addr_hi32 = cpu_to_le32(high_val);
8159         new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
8160 }
8161
8162 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
8163                                      struct hclge_mac_vlan_tbl_entry_cmd *req)
8164 {
8165         struct hclge_dev *hdev = vport->back;
8166         struct hclge_desc desc;
8167         u8 resp_code;
8168         u16 retval;
8169         int ret;
8170
8171         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
8172
8173         memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
8174
8175         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
8176         if (ret) {
8177                 dev_err(&hdev->pdev->dev,
8178                         "del mac addr failed for cmd_send, ret =%d.\n",
8179                         ret);
8180                 return ret;
8181         }
8182         resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
8183         retval = le16_to_cpu(desc.retval);
8184
8185         return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
8186                                              HCLGE_MAC_VLAN_REMOVE);
8187 }
8188
8189 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
8190                                      struct hclge_mac_vlan_tbl_entry_cmd *req,
8191                                      struct hclge_desc *desc,
8192                                      bool is_mc)
8193 {
8194         struct hclge_dev *hdev = vport->back;
8195         u8 resp_code;
8196         u16 retval;
8197         int ret;
8198
8199         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
8200         if (is_mc) {
8201                 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
8202                 memcpy(desc[0].data,
8203                        req,
8204                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
8205                 hclge_cmd_setup_basic_desc(&desc[1],
8206                                            HCLGE_OPC_MAC_VLAN_ADD,
8207                                            true);
8208                 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
8209                 hclge_cmd_setup_basic_desc(&desc[2],
8210                                            HCLGE_OPC_MAC_VLAN_ADD,
8211                                            true);
8212                 ret = hclge_cmd_send(&hdev->hw, desc, 3);
8213         } else {
8214                 memcpy(desc[0].data,
8215                        req,
8216                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
8217                 ret = hclge_cmd_send(&hdev->hw, desc, 1);
8218         }
8219         if (ret) {
8220                 dev_err(&hdev->pdev->dev,
8221                         "lookup mac addr failed for cmd_send, ret =%d.\n",
8222                         ret);
8223                 return ret;
8224         }
8225         resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
8226         retval = le16_to_cpu(desc[0].retval);
8227
8228         return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
8229                                              HCLGE_MAC_VLAN_LKUP);
8230 }
8231
8232 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
8233                                   struct hclge_mac_vlan_tbl_entry_cmd *req,
8234                                   struct hclge_desc *mc_desc)
8235 {
8236         struct hclge_dev *hdev = vport->back;
8237         int cfg_status;
8238         u8 resp_code;
8239         u16 retval;
8240         int ret;
8241
8242         if (!mc_desc) {
8243                 struct hclge_desc desc;
8244
8245                 hclge_cmd_setup_basic_desc(&desc,
8246                                            HCLGE_OPC_MAC_VLAN_ADD,
8247                                            false);
8248                 memcpy(desc.data, req,
8249                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
8250                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
8251                 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
8252                 retval = le16_to_cpu(desc.retval);
8253
8254                 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
8255                                                            resp_code,
8256                                                            HCLGE_MAC_VLAN_ADD);
8257         } else {
8258                 hclge_comm_cmd_reuse_desc(&mc_desc[0], false);
8259                 mc_desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
8260                 hclge_comm_cmd_reuse_desc(&mc_desc[1], false);
8261                 mc_desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
8262                 hclge_comm_cmd_reuse_desc(&mc_desc[2], false);
8263                 mc_desc[2].flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_NEXT);
8264                 memcpy(mc_desc[0].data, req,
8265                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
8266                 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
8267                 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
8268                 retval = le16_to_cpu(mc_desc[0].retval);
8269
8270                 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
8271                                                            resp_code,
8272                                                            HCLGE_MAC_VLAN_ADD);
8273         }
8274
8275         if (ret) {
8276                 dev_err(&hdev->pdev->dev,
8277                         "add mac addr failed for cmd_send, ret =%d.\n",
8278                         ret);
8279                 return ret;
8280         }
8281
8282         return cfg_status;
8283 }
8284
8285 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size,
8286                                u16 *allocated_size)
8287 {
8288         struct hclge_umv_spc_alc_cmd *req;
8289         struct hclge_desc desc;
8290         int ret;
8291
8292         req = (struct hclge_umv_spc_alc_cmd *)desc.data;
8293         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false);
8294
8295         req->space_size = cpu_to_le32(space_size);
8296
8297         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
8298         if (ret) {
8299                 dev_err(&hdev->pdev->dev, "failed to set umv space, ret = %d\n",
8300                         ret);
8301                 return ret;
8302         }
8303
8304         *allocated_size = le32_to_cpu(desc.data[1]);
8305
8306         return 0;
8307 }
8308
8309 static int hclge_init_umv_space(struct hclge_dev *hdev)
8310 {
8311         u16 allocated_size = 0;
8312         int ret;
8313
8314         ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size);
8315         if (ret)
8316                 return ret;
8317
8318         if (allocated_size < hdev->wanted_umv_size)
8319                 dev_warn(&hdev->pdev->dev,
8320                          "failed to alloc umv space, want %u, get %u\n",
8321                          hdev->wanted_umv_size, allocated_size);
8322
8323         hdev->max_umv_size = allocated_size;
8324         hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_alloc_vport + 1);
8325         hdev->share_umv_size = hdev->priv_umv_size +
8326                         hdev->max_umv_size % (hdev->num_alloc_vport + 1);
8327
8328         if (hdev->ae_dev->dev_specs.mc_mac_size)
8329                 set_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, hdev->ae_dev->caps);
8330
8331         return 0;
8332 }
8333
8334 static void hclge_reset_umv_space(struct hclge_dev *hdev)
8335 {
8336         struct hclge_vport *vport;
8337         int i;
8338
8339         for (i = 0; i < hdev->num_alloc_vport; i++) {
8340                 vport = &hdev->vport[i];
8341                 vport->used_umv_num = 0;
8342         }
8343
8344         mutex_lock(&hdev->vport_lock);
8345         hdev->share_umv_size = hdev->priv_umv_size +
8346                         hdev->max_umv_size % (hdev->num_alloc_vport + 1);
8347         mutex_unlock(&hdev->vport_lock);
8348
8349         hdev->used_mc_mac_num = 0;
8350 }
8351
8352 static bool hclge_is_umv_space_full(struct hclge_vport *vport, bool need_lock)
8353 {
8354         struct hclge_dev *hdev = vport->back;
8355         bool is_full;
8356
8357         if (need_lock)
8358                 mutex_lock(&hdev->vport_lock);
8359
8360         is_full = (vport->used_umv_num >= hdev->priv_umv_size &&
8361                    hdev->share_umv_size == 0);
8362
8363         if (need_lock)
8364                 mutex_unlock(&hdev->vport_lock);
8365
8366         return is_full;
8367 }
8368
8369 static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free)
8370 {
8371         struct hclge_dev *hdev = vport->back;
8372
8373         if (is_free) {
8374                 if (vport->used_umv_num > hdev->priv_umv_size)
8375                         hdev->share_umv_size++;
8376
8377                 if (vport->used_umv_num > 0)
8378                         vport->used_umv_num--;
8379         } else {
8380                 if (vport->used_umv_num >= hdev->priv_umv_size &&
8381                     hdev->share_umv_size > 0)
8382                         hdev->share_umv_size--;
8383                 vport->used_umv_num++;
8384         }
8385 }
8386
8387 static struct hclge_mac_node *hclge_find_mac_node(struct list_head *list,
8388                                                   const u8 *mac_addr)
8389 {
8390         struct hclge_mac_node *mac_node, *tmp;
8391
8392         list_for_each_entry_safe(mac_node, tmp, list, node)
8393                 if (ether_addr_equal(mac_addr, mac_node->mac_addr))
8394                         return mac_node;
8395
8396         return NULL;
8397 }
8398
8399 static void hclge_update_mac_node(struct hclge_mac_node *mac_node,
8400                                   enum HCLGE_MAC_NODE_STATE state)
8401 {
8402         switch (state) {
8403         /* from set_rx_mode or tmp_add_list */
8404         case HCLGE_MAC_TO_ADD:
8405                 if (mac_node->state == HCLGE_MAC_TO_DEL)
8406                         mac_node->state = HCLGE_MAC_ACTIVE;
8407                 break;
8408         /* only from set_rx_mode */
8409         case HCLGE_MAC_TO_DEL:
8410                 if (mac_node->state == HCLGE_MAC_TO_ADD) {
8411                         list_del(&mac_node->node);
8412                         kfree(mac_node);
8413                 } else {
8414                         mac_node->state = HCLGE_MAC_TO_DEL;
8415                 }
8416                 break;
8417         /* only from tmp_add_list, the mac_node->state won't be
8418          * ACTIVE.
8419          */
8420         case HCLGE_MAC_ACTIVE:
8421                 if (mac_node->state == HCLGE_MAC_TO_ADD)
8422                         mac_node->state = HCLGE_MAC_ACTIVE;
8423
8424                 break;
8425         }
8426 }
8427
8428 int hclge_update_mac_list(struct hclge_vport *vport,
8429                           enum HCLGE_MAC_NODE_STATE state,
8430                           enum HCLGE_MAC_ADDR_TYPE mac_type,
8431                           const unsigned char *addr)
8432 {
8433         char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
8434         struct hclge_dev *hdev = vport->back;
8435         struct hclge_mac_node *mac_node;
8436         struct list_head *list;
8437
8438         list = (mac_type == HCLGE_MAC_ADDR_UC) ?
8439                 &vport->uc_mac_list : &vport->mc_mac_list;
8440
8441         spin_lock_bh(&vport->mac_list_lock);
8442
8443         /* if the mac addr is already in the mac list, no need to add a new
8444          * one into it, just check the mac addr state, convert it to a new
8445          * state, or just remove it, or do nothing.
8446          */
8447         mac_node = hclge_find_mac_node(list, addr);
8448         if (mac_node) {
8449                 hclge_update_mac_node(mac_node, state);
8450                 spin_unlock_bh(&vport->mac_list_lock);
8451                 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state);
8452                 return 0;
8453         }
8454
8455         /* if this address is never added, unnecessary to delete */
8456         if (state == HCLGE_MAC_TO_DEL) {
8457                 spin_unlock_bh(&vport->mac_list_lock);
8458                 hnae3_format_mac_addr(format_mac_addr, addr);
8459                 dev_err(&hdev->pdev->dev,
8460                         "failed to delete address %s from mac list\n",
8461                         format_mac_addr);
8462                 return -ENOENT;
8463         }
8464
8465         mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC);
8466         if (!mac_node) {
8467                 spin_unlock_bh(&vport->mac_list_lock);
8468                 return -ENOMEM;
8469         }
8470
8471         set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state);
8472
8473         mac_node->state = state;
8474         ether_addr_copy(mac_node->mac_addr, addr);
8475         list_add_tail(&mac_node->node, list);
8476
8477         spin_unlock_bh(&vport->mac_list_lock);
8478
8479         return 0;
8480 }
8481
8482 static int hclge_add_uc_addr(struct hnae3_handle *handle,
8483                              const unsigned char *addr)
8484 {
8485         struct hclge_vport *vport = hclge_get_vport(handle);
8486
8487         return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_UC,
8488                                      addr);
8489 }
8490
8491 int hclge_add_uc_addr_common(struct hclge_vport *vport,
8492                              const unsigned char *addr)
8493 {
8494         char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
8495         struct hclge_dev *hdev = vport->back;
8496         struct hclge_mac_vlan_tbl_entry_cmd req;
8497         struct hclge_desc desc;
8498         u16 egress_port = 0;
8499         int ret;
8500
8501         /* mac addr check */
8502         if (is_zero_ether_addr(addr) ||
8503             is_broadcast_ether_addr(addr) ||
8504             is_multicast_ether_addr(addr)) {
8505                 hnae3_format_mac_addr(format_mac_addr, addr);
8506                 dev_err(&hdev->pdev->dev,
8507                         "Set_uc mac err! invalid mac:%s. is_zero:%d,is_br=%d,is_mul=%d\n",
8508                          format_mac_addr, is_zero_ether_addr(addr),
8509                          is_broadcast_ether_addr(addr),
8510                          is_multicast_ether_addr(addr));
8511                 return -EINVAL;
8512         }
8513
8514         memset(&req, 0, sizeof(req));
8515
8516         hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
8517                         HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
8518
8519         req.egress_port = cpu_to_le16(egress_port);
8520
8521         hclge_prepare_mac_addr(&req, addr, false);
8522
8523         /* Lookup the mac address in the mac_vlan table, and add
8524          * it if the entry is inexistent. Repeated unicast entry
8525          * is not allowed in the mac vlan table.
8526          */
8527         ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false);
8528         if (ret == -ENOENT) {
8529                 mutex_lock(&hdev->vport_lock);
8530                 if (!hclge_is_umv_space_full(vport, false)) {
8531                         ret = hclge_add_mac_vlan_tbl(vport, &req, NULL);
8532                         if (!ret)
8533                                 hclge_update_umv_space(vport, false);
8534                         mutex_unlock(&hdev->vport_lock);
8535                         return ret;
8536                 }
8537                 mutex_unlock(&hdev->vport_lock);
8538
8539                 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE))
8540                         dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n",
8541                                 hdev->priv_umv_size);
8542
8543                 return -ENOSPC;
8544         }
8545
8546         /* check if we just hit the duplicate */
8547         if (!ret)
8548                 return -EEXIST;
8549
8550         return ret;
8551 }
8552
8553 static int hclge_rm_uc_addr(struct hnae3_handle *handle,
8554                             const unsigned char *addr)
8555 {
8556         struct hclge_vport *vport = hclge_get_vport(handle);
8557
8558         return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_UC,
8559                                      addr);
8560 }
8561
8562 int hclge_rm_uc_addr_common(struct hclge_vport *vport,
8563                             const unsigned char *addr)
8564 {
8565         char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
8566         struct hclge_dev *hdev = vport->back;
8567         struct hclge_mac_vlan_tbl_entry_cmd req;
8568         int ret;
8569
8570         /* mac addr check */
8571         if (is_zero_ether_addr(addr) ||
8572             is_broadcast_ether_addr(addr) ||
8573             is_multicast_ether_addr(addr)) {
8574                 hnae3_format_mac_addr(format_mac_addr, addr);
8575                 dev_dbg(&hdev->pdev->dev, "Remove mac err! invalid mac:%s.\n",
8576                         format_mac_addr);
8577                 return -EINVAL;
8578         }
8579
8580         memset(&req, 0, sizeof(req));
8581         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
8582         hclge_prepare_mac_addr(&req, addr, false);
8583         ret = hclge_remove_mac_vlan_tbl(vport, &req);
8584         if (!ret || ret == -ENOENT) {
8585                 mutex_lock(&hdev->vport_lock);
8586                 hclge_update_umv_space(vport, true);
8587                 mutex_unlock(&hdev->vport_lock);
8588                 return 0;
8589         }
8590
8591         return ret;
8592 }
8593
8594 static int hclge_add_mc_addr(struct hnae3_handle *handle,
8595                              const unsigned char *addr)
8596 {
8597         struct hclge_vport *vport = hclge_get_vport(handle);
8598
8599         return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_MC,
8600                                      addr);
8601 }
8602
8603 int hclge_add_mc_addr_common(struct hclge_vport *vport,
8604                              const unsigned char *addr)
8605 {
8606         char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
8607         struct hclge_dev *hdev = vport->back;
8608         struct hclge_mac_vlan_tbl_entry_cmd req;
8609         struct hclge_desc desc[3];
8610         bool is_new_addr = false;
8611         int status;
8612
8613         /* mac addr check */
8614         if (!is_multicast_ether_addr(addr)) {
8615                 hnae3_format_mac_addr(format_mac_addr, addr);
8616                 dev_err(&hdev->pdev->dev,
8617                         "Add mc mac err! invalid mac:%s.\n",
8618                          format_mac_addr);
8619                 return -EINVAL;
8620         }
8621         memset(&req, 0, sizeof(req));
8622         hclge_prepare_mac_addr(&req, addr, true);
8623         status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
8624         if (status) {
8625                 if (hnae3_ae_dev_mc_mac_mng_supported(hdev->ae_dev) &&
8626                     hdev->used_mc_mac_num >=
8627                     hdev->ae_dev->dev_specs.mc_mac_size)
8628                         goto err_no_space;
8629
8630                 is_new_addr = true;
8631
8632                 /* This mac addr do not exist, add new entry for it */
8633                 memset(desc[0].data, 0, sizeof(desc[0].data));
8634                 memset(desc[1].data, 0, sizeof(desc[0].data));
8635                 memset(desc[2].data, 0, sizeof(desc[0].data));
8636         }
8637         status = hclge_update_desc_vfid(desc, vport->vport_id, false);
8638         if (status)
8639                 return status;
8640         status = hclge_add_mac_vlan_tbl(vport, &req, desc);
8641         if (status == -ENOSPC)
8642                 goto err_no_space;
8643         else if (!status && is_new_addr)
8644                 hdev->used_mc_mac_num++;
8645
8646         return status;
8647
8648 err_no_space:
8649         /* if already overflow, not to print each time */
8650         if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE)) {
8651                 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE;
8652                 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n");
8653         }
8654
8655         return -ENOSPC;
8656 }
8657
8658 static int hclge_rm_mc_addr(struct hnae3_handle *handle,
8659                             const unsigned char *addr)
8660 {
8661         struct hclge_vport *vport = hclge_get_vport(handle);
8662
8663         return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_MC,
8664                                      addr);
8665 }
8666
8667 int hclge_rm_mc_addr_common(struct hclge_vport *vport,
8668                             const unsigned char *addr)
8669 {
8670         char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
8671         struct hclge_dev *hdev = vport->back;
8672         struct hclge_mac_vlan_tbl_entry_cmd req;
8673         enum hclge_comm_cmd_status status;
8674         struct hclge_desc desc[3];
8675
8676         /* mac addr check */
8677         if (!is_multicast_ether_addr(addr)) {
8678                 hnae3_format_mac_addr(format_mac_addr, addr);
8679                 dev_dbg(&hdev->pdev->dev,
8680                         "Remove mc mac err! invalid mac:%s.\n",
8681                          format_mac_addr);
8682                 return -EINVAL;
8683         }
8684
8685         memset(&req, 0, sizeof(req));
8686         hclge_prepare_mac_addr(&req, addr, true);
8687         status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
8688         if (!status) {
8689                 /* This mac addr exist, remove this handle's VFID for it */
8690                 status = hclge_update_desc_vfid(desc, vport->vport_id, true);
8691                 if (status)
8692                         return status;
8693
8694                 if (hclge_is_all_function_id_zero(desc)) {
8695                         /* All the vfid is zero, so need to delete this entry */
8696                         status = hclge_remove_mac_vlan_tbl(vport, &req);
8697                         if (!status)
8698                                 hdev->used_mc_mac_num--;
8699                 } else {
8700                         /* Not all the vfid is zero, update the vfid */
8701                         status = hclge_add_mac_vlan_tbl(vport, &req, desc);
8702                 }
8703         } else if (status == -ENOENT) {
8704                 status = 0;
8705         }
8706
8707         return status;
8708 }
8709
8710 static void hclge_sync_vport_mac_list(struct hclge_vport *vport,
8711                                       struct list_head *list,
8712                                       enum HCLGE_MAC_ADDR_TYPE mac_type)
8713 {
8714         int (*sync)(struct hclge_vport *vport, const unsigned char *addr);
8715         struct hclge_mac_node *mac_node, *tmp;
8716         int ret;
8717
8718         if (mac_type == HCLGE_MAC_ADDR_UC)
8719                 sync = hclge_add_uc_addr_common;
8720         else
8721                 sync = hclge_add_mc_addr_common;
8722
8723         list_for_each_entry_safe(mac_node, tmp, list, node) {
8724                 ret = sync(vport, mac_node->mac_addr);
8725                 if (!ret) {
8726                         mac_node->state = HCLGE_MAC_ACTIVE;
8727                 } else {
8728                         set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE,
8729                                 &vport->state);
8730
8731                         /* If one unicast mac address is existing in hardware,
8732                          * we need to try whether other unicast mac addresses
8733                          * are new addresses that can be added.
8734                          * Multicast mac address can be reusable, even though
8735                          * there is no space to add new multicast mac address,
8736                          * we should check whether other mac addresses are
8737                          * existing in hardware for reuse.
8738                          */
8739                         if ((mac_type == HCLGE_MAC_ADDR_UC && ret != -EEXIST) ||
8740                             (mac_type == HCLGE_MAC_ADDR_MC && ret != -ENOSPC))
8741                                 break;
8742                 }
8743         }
8744 }
8745
8746 static void hclge_unsync_vport_mac_list(struct hclge_vport *vport,
8747                                         struct list_head *list,
8748                                         enum HCLGE_MAC_ADDR_TYPE mac_type)
8749 {
8750         int (*unsync)(struct hclge_vport *vport, const unsigned char *addr);
8751         struct hclge_mac_node *mac_node, *tmp;
8752         int ret;
8753
8754         if (mac_type == HCLGE_MAC_ADDR_UC)
8755                 unsync = hclge_rm_uc_addr_common;
8756         else
8757                 unsync = hclge_rm_mc_addr_common;
8758
8759         list_for_each_entry_safe(mac_node, tmp, list, node) {
8760                 ret = unsync(vport, mac_node->mac_addr);
8761                 if (!ret || ret == -ENOENT) {
8762                         list_del(&mac_node->node);
8763                         kfree(mac_node);
8764                 } else {
8765                         set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE,
8766                                 &vport->state);
8767                         break;
8768                 }
8769         }
8770 }
8771
8772 static bool hclge_sync_from_add_list(struct list_head *add_list,
8773                                      struct list_head *mac_list)
8774 {
8775         struct hclge_mac_node *mac_node, *tmp, *new_node;
8776         bool all_added = true;
8777
8778         list_for_each_entry_safe(mac_node, tmp, add_list, node) {
8779                 if (mac_node->state == HCLGE_MAC_TO_ADD)
8780                         all_added = false;
8781
8782                 /* if the mac address from tmp_add_list is not in the
8783                  * uc/mc_mac_list, it means have received a TO_DEL request
8784                  * during the time window of adding the mac address into mac
8785                  * table. if mac_node state is ACTIVE, then change it to TO_DEL,
8786                  * then it will be removed at next time. else it must be TO_ADD,
8787                  * this address hasn't been added into mac table,
8788                  * so just remove the mac node.
8789                  */
8790                 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr);
8791                 if (new_node) {
8792                         hclge_update_mac_node(new_node, mac_node->state);
8793                         list_del(&mac_node->node);
8794                         kfree(mac_node);
8795                 } else if (mac_node->state == HCLGE_MAC_ACTIVE) {
8796                         mac_node->state = HCLGE_MAC_TO_DEL;
8797                         list_move_tail(&mac_node->node, mac_list);
8798                 } else {
8799                         list_del(&mac_node->node);
8800                         kfree(mac_node);
8801                 }
8802         }
8803
8804         return all_added;
8805 }
8806
8807 static void hclge_sync_from_del_list(struct list_head *del_list,
8808                                      struct list_head *mac_list)
8809 {
8810         struct hclge_mac_node *mac_node, *tmp, *new_node;
8811
8812         list_for_each_entry_safe(mac_node, tmp, del_list, node) {
8813                 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr);
8814                 if (new_node) {
8815                         /* If the mac addr exists in the mac list, it means
8816                          * received a new TO_ADD request during the time window
8817                          * of configuring the mac address. For the mac node
8818                          * state is TO_ADD, and the address is already in the
8819                          * in the hardware(due to delete fail), so we just need
8820                          * to change the mac node state to ACTIVE.
8821                          */
8822                         new_node->state = HCLGE_MAC_ACTIVE;
8823                         list_del(&mac_node->node);
8824                         kfree(mac_node);
8825                 } else {
8826                         list_move_tail(&mac_node->node, mac_list);
8827                 }
8828         }
8829 }
8830
8831 static void hclge_update_overflow_flags(struct hclge_vport *vport,
8832                                         enum HCLGE_MAC_ADDR_TYPE mac_type,
8833                                         bool is_all_added)
8834 {
8835         if (mac_type == HCLGE_MAC_ADDR_UC) {
8836                 if (is_all_added)
8837                         vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_UPE;
8838                 else if (hclge_is_umv_space_full(vport, true))
8839                         vport->overflow_promisc_flags |= HNAE3_OVERFLOW_UPE;
8840         } else {
8841                 if (is_all_added)
8842                         vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_MPE;
8843                 else
8844                         vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE;
8845         }
8846 }
8847
8848 static void hclge_sync_vport_mac_table(struct hclge_vport *vport,
8849                                        enum HCLGE_MAC_ADDR_TYPE mac_type)
8850 {
8851         struct hclge_mac_node *mac_node, *tmp, *new_node;
8852         struct list_head tmp_add_list, tmp_del_list;
8853         struct list_head *list;
8854         bool all_added;
8855
8856         INIT_LIST_HEAD(&tmp_add_list);
8857         INIT_LIST_HEAD(&tmp_del_list);
8858
8859         /* move the mac addr to the tmp_add_list and tmp_del_list, then
8860          * we can add/delete these mac addr outside the spin lock
8861          */
8862         list = (mac_type == HCLGE_MAC_ADDR_UC) ?
8863                 &vport->uc_mac_list : &vport->mc_mac_list;
8864
8865         spin_lock_bh(&vport->mac_list_lock);
8866
8867         list_for_each_entry_safe(mac_node, tmp, list, node) {
8868                 switch (mac_node->state) {
8869                 case HCLGE_MAC_TO_DEL:
8870                         list_move_tail(&mac_node->node, &tmp_del_list);
8871                         break;
8872                 case HCLGE_MAC_TO_ADD:
8873                         new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC);
8874                         if (!new_node)
8875                                 goto stop_traverse;
8876                         ether_addr_copy(new_node->mac_addr, mac_node->mac_addr);
8877                         new_node->state = mac_node->state;
8878                         list_add_tail(&new_node->node, &tmp_add_list);
8879                         break;
8880                 default:
8881                         break;
8882                 }
8883         }
8884
8885 stop_traverse:
8886         spin_unlock_bh(&vport->mac_list_lock);
8887
8888         /* delete first, in order to get max mac table space for adding */
8889         hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type);
8890         hclge_sync_vport_mac_list(vport, &tmp_add_list, mac_type);
8891
8892         /* if some mac addresses were added/deleted fail, move back to the
8893          * mac_list, and retry at next time.
8894          */
8895         spin_lock_bh(&vport->mac_list_lock);
8896
8897         hclge_sync_from_del_list(&tmp_del_list, list);
8898         all_added = hclge_sync_from_add_list(&tmp_add_list, list);
8899
8900         spin_unlock_bh(&vport->mac_list_lock);
8901
8902         hclge_update_overflow_flags(vport, mac_type, all_added);
8903 }
8904
8905 static bool hclge_need_sync_mac_table(struct hclge_vport *vport)
8906 {
8907         struct hclge_dev *hdev = vport->back;
8908
8909         if (test_bit(vport->vport_id, hdev->vport_config_block))
8910                 return false;
8911
8912         if (test_and_clear_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state))
8913                 return true;
8914
8915         return false;
8916 }
8917
8918 static void hclge_sync_mac_table(struct hclge_dev *hdev)
8919 {
8920         int i;
8921
8922         for (i = 0; i < hdev->num_alloc_vport; i++) {
8923                 struct hclge_vport *vport = &hdev->vport[i];
8924
8925                 if (!hclge_need_sync_mac_table(vport))
8926                         continue;
8927
8928                 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_UC);
8929                 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_MC);
8930         }
8931 }
8932
8933 static void hclge_build_del_list(struct list_head *list,
8934                                  bool is_del_list,
8935                                  struct list_head *tmp_del_list)
8936 {
8937         struct hclge_mac_node *mac_cfg, *tmp;
8938
8939         list_for_each_entry_safe(mac_cfg, tmp, list, node) {
8940                 switch (mac_cfg->state) {
8941                 case HCLGE_MAC_TO_DEL:
8942                 case HCLGE_MAC_ACTIVE:
8943                         list_move_tail(&mac_cfg->node, tmp_del_list);
8944                         break;
8945                 case HCLGE_MAC_TO_ADD:
8946                         if (is_del_list) {
8947                                 list_del(&mac_cfg->node);
8948                                 kfree(mac_cfg);
8949                         }
8950                         break;
8951                 }
8952         }
8953 }
8954
8955 static void hclge_unsync_del_list(struct hclge_vport *vport,
8956                                   int (*unsync)(struct hclge_vport *vport,
8957                                                 const unsigned char *addr),
8958                                   bool is_del_list,
8959                                   struct list_head *tmp_del_list)
8960 {
8961         struct hclge_mac_node *mac_cfg, *tmp;
8962         int ret;
8963
8964         list_for_each_entry_safe(mac_cfg, tmp, tmp_del_list, node) {
8965                 ret = unsync(vport, mac_cfg->mac_addr);
8966                 if (!ret || ret == -ENOENT) {
8967                         /* clear all mac addr from hardware, but remain these
8968                          * mac addr in the mac list, and restore them after
8969                          * vf reset finished.
8970                          */
8971                         if (!is_del_list &&
8972                             mac_cfg->state == HCLGE_MAC_ACTIVE) {
8973                                 mac_cfg->state = HCLGE_MAC_TO_ADD;
8974                         } else {
8975                                 list_del(&mac_cfg->node);
8976                                 kfree(mac_cfg);
8977                         }
8978                 } else if (is_del_list) {
8979                         mac_cfg->state = HCLGE_MAC_TO_DEL;
8980                 }
8981         }
8982 }
8983
8984 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list,
8985                                   enum HCLGE_MAC_ADDR_TYPE mac_type)
8986 {
8987         int (*unsync)(struct hclge_vport *vport, const unsigned char *addr);
8988         struct hclge_dev *hdev = vport->back;
8989         struct list_head tmp_del_list, *list;
8990
8991         if (mac_type == HCLGE_MAC_ADDR_UC) {
8992                 list = &vport->uc_mac_list;
8993                 unsync = hclge_rm_uc_addr_common;
8994         } else {
8995                 list = &vport->mc_mac_list;
8996                 unsync = hclge_rm_mc_addr_common;
8997         }
8998
8999         INIT_LIST_HEAD(&tmp_del_list);
9000
9001         if (!is_del_list)
9002                 set_bit(vport->vport_id, hdev->vport_config_block);
9003
9004         spin_lock_bh(&vport->mac_list_lock);
9005
9006         hclge_build_del_list(list, is_del_list, &tmp_del_list);
9007
9008         spin_unlock_bh(&vport->mac_list_lock);
9009
9010         hclge_unsync_del_list(vport, unsync, is_del_list, &tmp_del_list);
9011
9012         spin_lock_bh(&vport->mac_list_lock);
9013
9014         hclge_sync_from_del_list(&tmp_del_list, list);
9015
9016         spin_unlock_bh(&vport->mac_list_lock);
9017 }
9018
9019 /* remove all mac address when uninitailize */
9020 static void hclge_uninit_vport_mac_list(struct hclge_vport *vport,
9021                                         enum HCLGE_MAC_ADDR_TYPE mac_type)
9022 {
9023         struct hclge_mac_node *mac_node, *tmp;
9024         struct hclge_dev *hdev = vport->back;
9025         struct list_head tmp_del_list, *list;
9026
9027         INIT_LIST_HEAD(&tmp_del_list);
9028
9029         list = (mac_type == HCLGE_MAC_ADDR_UC) ?
9030                 &vport->uc_mac_list : &vport->mc_mac_list;
9031
9032         spin_lock_bh(&vport->mac_list_lock);
9033
9034         list_for_each_entry_safe(mac_node, tmp, list, node) {
9035                 switch (mac_node->state) {
9036                 case HCLGE_MAC_TO_DEL:
9037                 case HCLGE_MAC_ACTIVE:
9038                         list_move_tail(&mac_node->node, &tmp_del_list);
9039                         break;
9040                 case HCLGE_MAC_TO_ADD:
9041                         list_del(&mac_node->node);
9042                         kfree(mac_node);
9043                         break;
9044                 }
9045         }
9046
9047         spin_unlock_bh(&vport->mac_list_lock);
9048
9049         hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type);
9050
9051         if (!list_empty(&tmp_del_list))
9052                 dev_warn(&hdev->pdev->dev,
9053                          "uninit %s mac list for vport %u not completely.\n",
9054                          mac_type == HCLGE_MAC_ADDR_UC ? "uc" : "mc",
9055                          vport->vport_id);
9056
9057         list_for_each_entry_safe(mac_node, tmp, &tmp_del_list, node) {
9058                 list_del(&mac_node->node);
9059                 kfree(mac_node);
9060         }
9061 }
9062
9063 static void hclge_uninit_mac_table(struct hclge_dev *hdev)
9064 {
9065         struct hclge_vport *vport;
9066         int i;
9067
9068         for (i = 0; i < hdev->num_alloc_vport; i++) {
9069                 vport = &hdev->vport[i];
9070                 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_UC);
9071                 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_MC);
9072         }
9073 }
9074
9075 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev,
9076                                               u16 cmdq_resp, u8 resp_code)
9077 {
9078 #define HCLGE_ETHERTYPE_SUCCESS_ADD             0
9079 #define HCLGE_ETHERTYPE_ALREADY_ADD             1
9080 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW        2
9081 #define HCLGE_ETHERTYPE_KEY_CONFLICT            3
9082
9083         int return_status;
9084
9085         if (cmdq_resp) {
9086                 dev_err(&hdev->pdev->dev,
9087                         "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
9088                         cmdq_resp);
9089                 return -EIO;
9090         }
9091
9092         switch (resp_code) {
9093         case HCLGE_ETHERTYPE_SUCCESS_ADD:
9094         case HCLGE_ETHERTYPE_ALREADY_ADD:
9095                 return_status = 0;
9096                 break;
9097         case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW:
9098                 dev_err(&hdev->pdev->dev,
9099                         "add mac ethertype failed for manager table overflow.\n");
9100                 return_status = -EIO;
9101                 break;
9102         case HCLGE_ETHERTYPE_KEY_CONFLICT:
9103                 dev_err(&hdev->pdev->dev,
9104                         "add mac ethertype failed for key conflict.\n");
9105                 return_status = -EIO;
9106                 break;
9107         default:
9108                 dev_err(&hdev->pdev->dev,
9109                         "add mac ethertype failed for undefined, code=%u.\n",
9110                         resp_code);
9111                 return_status = -EIO;
9112         }
9113
9114         return return_status;
9115 }
9116
9117 static int hclge_set_vf_mac(struct hnae3_handle *handle, int vf,
9118                             u8 *mac_addr)
9119 {
9120         struct hclge_vport *vport = hclge_get_vport(handle);
9121         char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
9122         struct hclge_dev *hdev = vport->back;
9123
9124         vport = hclge_get_vf_vport(hdev, vf);
9125         if (!vport)
9126                 return -EINVAL;
9127
9128         hnae3_format_mac_addr(format_mac_addr, mac_addr);
9129         if (ether_addr_equal(mac_addr, vport->vf_info.mac)) {
9130                 dev_info(&hdev->pdev->dev,
9131                          "Specified MAC(=%s) is same as before, no change committed!\n",
9132                          format_mac_addr);
9133                 return 0;
9134         }
9135
9136         ether_addr_copy(vport->vf_info.mac, mac_addr);
9137
9138         /* there is a timewindow for PF to know VF unalive, it may
9139          * cause send mailbox fail, but it doesn't matter, VF will
9140          * query it when reinit.
9141          */
9142         if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) {
9143                 dev_info(&hdev->pdev->dev,
9144                          "MAC of VF %d has been set to %s, and it will be reinitialized!\n",
9145                          vf, format_mac_addr);
9146                 (void)hclge_inform_reset_assert_to_vf(vport);
9147                 return 0;
9148         }
9149
9150         dev_info(&hdev->pdev->dev,
9151                  "MAC of VF %d has been set to %s, will be active after VF reset\n",
9152                  vf, format_mac_addr);
9153         return 0;
9154 }
9155
9156 static int hclge_add_mgr_tbl(struct hclge_dev *hdev,
9157                              const struct hclge_mac_mgr_tbl_entry_cmd *req)
9158 {
9159         struct hclge_desc desc;
9160         u8 resp_code;
9161         u16 retval;
9162         int ret;
9163
9164         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false);
9165         memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd));
9166
9167         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
9168         if (ret) {
9169                 dev_err(&hdev->pdev->dev,
9170                         "add mac ethertype failed for cmd_send, ret =%d.\n",
9171                         ret);
9172                 return ret;
9173         }
9174
9175         resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
9176         retval = le16_to_cpu(desc.retval);
9177
9178         return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code);
9179 }
9180
9181 static int init_mgr_tbl(struct hclge_dev *hdev)
9182 {
9183         int ret;
9184         int i;
9185
9186         for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) {
9187                 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]);
9188                 if (ret) {
9189                         dev_err(&hdev->pdev->dev,
9190                                 "add mac ethertype failed, ret =%d.\n",
9191                                 ret);
9192                         return ret;
9193                 }
9194         }
9195
9196         return 0;
9197 }
9198
9199 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
9200 {
9201         struct hclge_vport *vport = hclge_get_vport(handle);
9202         struct hclge_dev *hdev = vport->back;
9203
9204         ether_addr_copy(p, hdev->hw.mac.mac_addr);
9205 }
9206
9207 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport,
9208                                        const u8 *old_addr, const u8 *new_addr)
9209 {
9210         struct list_head *list = &vport->uc_mac_list;
9211         struct hclge_mac_node *old_node, *new_node;
9212
9213         new_node = hclge_find_mac_node(list, new_addr);
9214         if (!new_node) {
9215                 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC);
9216                 if (!new_node)
9217                         return -ENOMEM;
9218
9219                 new_node->state = HCLGE_MAC_TO_ADD;
9220                 ether_addr_copy(new_node->mac_addr, new_addr);
9221                 list_add(&new_node->node, list);
9222         } else {
9223                 if (new_node->state == HCLGE_MAC_TO_DEL)
9224                         new_node->state = HCLGE_MAC_ACTIVE;
9225
9226                 /* make sure the new addr is in the list head, avoid dev
9227                  * addr may be not re-added into mac table for the umv space
9228                  * limitation after global/imp reset which will clear mac
9229                  * table by hardware.
9230                  */
9231                 list_move(&new_node->node, list);
9232         }
9233
9234         if (old_addr && !ether_addr_equal(old_addr, new_addr)) {
9235                 old_node = hclge_find_mac_node(list, old_addr);
9236                 if (old_node) {
9237                         if (old_node->state == HCLGE_MAC_TO_ADD) {
9238                                 list_del(&old_node->node);
9239                                 kfree(old_node);
9240                         } else {
9241                                 old_node->state = HCLGE_MAC_TO_DEL;
9242                         }
9243                 }
9244         }
9245
9246         set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state);
9247
9248         return 0;
9249 }
9250
9251 static int hclge_set_mac_addr(struct hnae3_handle *handle, const void *p,
9252                               bool is_first)
9253 {
9254         const unsigned char *new_addr = (const unsigned char *)p;
9255         struct hclge_vport *vport = hclge_get_vport(handle);
9256         char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
9257         struct hclge_dev *hdev = vport->back;
9258         unsigned char *old_addr = NULL;
9259         int ret;
9260
9261         /* mac addr check */
9262         if (is_zero_ether_addr(new_addr) ||
9263             is_broadcast_ether_addr(new_addr) ||
9264             is_multicast_ether_addr(new_addr)) {
9265                 hnae3_format_mac_addr(format_mac_addr, new_addr);
9266                 dev_err(&hdev->pdev->dev,
9267                         "change uc mac err! invalid mac: %s.\n",
9268                          format_mac_addr);
9269                 return -EINVAL;
9270         }
9271
9272         ret = hclge_pause_addr_cfg(hdev, new_addr);
9273         if (ret) {
9274                 dev_err(&hdev->pdev->dev,
9275                         "failed to configure mac pause address, ret = %d\n",
9276                         ret);
9277                 return ret;
9278         }
9279
9280         if (!is_first)
9281                 old_addr = hdev->hw.mac.mac_addr;
9282
9283         spin_lock_bh(&vport->mac_list_lock);
9284         ret = hclge_update_mac_node_for_dev_addr(vport, old_addr, new_addr);
9285         if (ret) {
9286                 hnae3_format_mac_addr(format_mac_addr, new_addr);
9287                 dev_err(&hdev->pdev->dev,
9288                         "failed to change the mac addr:%s, ret = %d\n",
9289                         format_mac_addr, ret);
9290                 spin_unlock_bh(&vport->mac_list_lock);
9291
9292                 if (!is_first)
9293                         hclge_pause_addr_cfg(hdev, old_addr);
9294
9295                 return ret;
9296         }
9297         /* we must update dev addr with spin lock protect, preventing dev addr
9298          * being removed by set_rx_mode path.
9299          */
9300         ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
9301         spin_unlock_bh(&vport->mac_list_lock);
9302
9303         hclge_task_schedule(hdev, 0);
9304
9305         return 0;
9306 }
9307
9308 static int hclge_mii_ioctl(struct hclge_dev *hdev, struct ifreq *ifr, int cmd)
9309 {
9310         struct mii_ioctl_data *data = if_mii(ifr);
9311
9312         if (!hnae3_dev_phy_imp_supported(hdev))
9313                 return -EOPNOTSUPP;
9314
9315         switch (cmd) {
9316         case SIOCGMIIPHY:
9317                 data->phy_id = hdev->hw.mac.phy_addr;
9318                 /* this command reads phy id and register at the same time */
9319                 fallthrough;
9320         case SIOCGMIIREG:
9321                 data->val_out = hclge_read_phy_reg(hdev, data->reg_num);
9322                 return 0;
9323
9324         case SIOCSMIIREG:
9325                 return hclge_write_phy_reg(hdev, data->reg_num, data->val_in);
9326         default:
9327                 return -EOPNOTSUPP;
9328         }
9329 }
9330
9331 static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr,
9332                           int cmd)
9333 {
9334         struct hclge_vport *vport = hclge_get_vport(handle);
9335         struct hclge_dev *hdev = vport->back;
9336
9337         switch (cmd) {
9338         case SIOCGHWTSTAMP:
9339                 return hclge_ptp_get_cfg(hdev, ifr);
9340         case SIOCSHWTSTAMP:
9341                 return hclge_ptp_set_cfg(hdev, ifr);
9342         default:
9343                 if (!hdev->hw.mac.phydev)
9344                         return hclge_mii_ioctl(hdev, ifr, cmd);
9345         }
9346
9347         return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd);
9348 }
9349
9350 static int hclge_set_port_vlan_filter_bypass(struct hclge_dev *hdev, u8 vf_id,
9351                                              bool bypass_en)
9352 {
9353         struct hclge_port_vlan_filter_bypass_cmd *req;
9354         struct hclge_desc desc;
9355         int ret;
9356
9357         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PORT_VLAN_BYPASS, false);
9358         req = (struct hclge_port_vlan_filter_bypass_cmd *)desc.data;
9359         req->vf_id = vf_id;
9360         hnae3_set_bit(req->bypass_state, HCLGE_INGRESS_BYPASS_B,
9361                       bypass_en ? 1 : 0);
9362
9363         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
9364         if (ret)
9365                 dev_err(&hdev->pdev->dev,
9366                         "failed to set vport%u port vlan filter bypass state, ret = %d.\n",
9367                         vf_id, ret);
9368
9369         return ret;
9370 }
9371
9372 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
9373                                       u8 fe_type, bool filter_en, u8 vf_id)
9374 {
9375         struct hclge_vlan_filter_ctrl_cmd *req;
9376         struct hclge_desc desc;
9377         int ret;
9378
9379         /* read current vlan filter parameter */
9380         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, true);
9381         req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
9382         req->vlan_type = vlan_type;
9383         req->vf_id = vf_id;
9384
9385         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
9386         if (ret) {
9387                 dev_err(&hdev->pdev->dev, "failed to get vport%u vlan filter config, ret = %d.\n",
9388                         vf_id, ret);
9389                 return ret;
9390         }
9391
9392         /* modify and write new config parameter */
9393         hclge_comm_cmd_reuse_desc(&desc, false);
9394         req->vlan_fe = filter_en ?
9395                         (req->vlan_fe | fe_type) : (req->vlan_fe & ~fe_type);
9396
9397         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
9398         if (ret)
9399                 dev_err(&hdev->pdev->dev, "failed to set vport%u vlan filter, ret = %d.\n",
9400                         vf_id, ret);
9401
9402         return ret;
9403 }
9404
9405 static int hclge_set_vport_vlan_filter(struct hclge_vport *vport, bool enable)
9406 {
9407         struct hclge_dev *hdev = vport->back;
9408         struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
9409         int ret;
9410
9411         if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
9412                 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
9413                                                   HCLGE_FILTER_FE_EGRESS_V1_B,
9414                                                   enable, vport->vport_id);
9415
9416         ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
9417                                          HCLGE_FILTER_FE_EGRESS, enable,
9418                                          vport->vport_id);
9419         if (ret)
9420                 return ret;
9421
9422         if (test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, ae_dev->caps)) {
9423                 ret = hclge_set_port_vlan_filter_bypass(hdev, vport->vport_id,
9424                                                         !enable);
9425         } else if (!vport->vport_id) {
9426                 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps))
9427                         enable = false;
9428
9429                 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT,
9430                                                  HCLGE_FILTER_FE_INGRESS,
9431                                                  enable, 0);
9432         }
9433
9434         return ret;
9435 }
9436
9437 static bool hclge_need_enable_vport_vlan_filter(struct hclge_vport *vport)
9438 {
9439         struct hnae3_handle *handle = &vport->nic;
9440         struct hclge_vport_vlan_cfg *vlan, *tmp;
9441         struct hclge_dev *hdev = vport->back;
9442
9443         if (vport->vport_id) {
9444                 if (vport->port_base_vlan_cfg.state !=
9445                         HNAE3_PORT_BASE_VLAN_DISABLE)
9446                         return true;
9447
9448                 if (vport->vf_info.trusted && vport->vf_info.request_uc_en)
9449                         return false;
9450         } else if (handle->netdev_flags & HNAE3_USER_UPE) {
9451                 return false;
9452         }
9453
9454         if (!vport->req_vlan_fltr_en)
9455                 return false;
9456
9457         /* compatible with former device, always enable vlan filter */
9458         if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps))
9459                 return true;
9460
9461         list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node)
9462                 if (vlan->vlan_id != 0)
9463                         return true;
9464
9465         return false;
9466 }
9467
9468 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en)
9469 {
9470         struct hclge_dev *hdev = vport->back;
9471         bool need_en;
9472         int ret;
9473
9474         mutex_lock(&hdev->vport_lock);
9475
9476         vport->req_vlan_fltr_en = request_en;
9477
9478         need_en = hclge_need_enable_vport_vlan_filter(vport);
9479         if (need_en == vport->cur_vlan_fltr_en) {
9480                 mutex_unlock(&hdev->vport_lock);
9481                 return 0;
9482         }
9483
9484         ret = hclge_set_vport_vlan_filter(vport, need_en);
9485         if (ret) {
9486                 mutex_unlock(&hdev->vport_lock);
9487                 return ret;
9488         }
9489
9490         vport->cur_vlan_fltr_en = need_en;
9491
9492         mutex_unlock(&hdev->vport_lock);
9493
9494         return 0;
9495 }
9496
9497 static int hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
9498 {
9499         struct hclge_vport *vport = hclge_get_vport(handle);
9500
9501         return hclge_enable_vport_vlan_filter(vport, enable);
9502 }
9503
9504 static int hclge_set_vf_vlan_filter_cmd(struct hclge_dev *hdev, u16 vfid,
9505                                         bool is_kill, u16 vlan,
9506                                         struct hclge_desc *desc)
9507 {
9508         struct hclge_vlan_filter_vf_cfg_cmd *req0;
9509         struct hclge_vlan_filter_vf_cfg_cmd *req1;
9510         u8 vf_byte_val;
9511         u8 vf_byte_off;
9512         int ret;
9513
9514         hclge_cmd_setup_basic_desc(&desc[0],
9515                                    HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
9516         hclge_cmd_setup_basic_desc(&desc[1],
9517                                    HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
9518
9519         desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
9520
9521         vf_byte_off = vfid / 8;
9522         vf_byte_val = 1 << (vfid % 8);
9523
9524         req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
9525         req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
9526
9527         req0->vlan_id  = cpu_to_le16(vlan);
9528         req0->vlan_cfg = is_kill;
9529
9530         if (vf_byte_off < HCLGE_MAX_VF_BYTES)
9531                 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
9532         else
9533                 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
9534
9535         ret = hclge_cmd_send(&hdev->hw, desc, 2);
9536         if (ret) {
9537                 dev_err(&hdev->pdev->dev,
9538                         "Send vf vlan command fail, ret =%d.\n",
9539                         ret);
9540                 return ret;
9541         }
9542
9543         return 0;
9544 }
9545
9546 static int hclge_check_vf_vlan_cmd_status(struct hclge_dev *hdev, u16 vfid,
9547                                           bool is_kill, struct hclge_desc *desc)
9548 {
9549         struct hclge_vlan_filter_vf_cfg_cmd *req;
9550
9551         req = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
9552
9553         if (!is_kill) {
9554 #define HCLGE_VF_VLAN_NO_ENTRY  2
9555                 if (!req->resp_code || req->resp_code == 1)
9556                         return 0;
9557
9558                 if (req->resp_code == HCLGE_VF_VLAN_NO_ENTRY) {
9559                         set_bit(vfid, hdev->vf_vlan_full);
9560                         dev_warn(&hdev->pdev->dev,
9561                                  "vf vlan table is full, vf vlan filter is disabled\n");
9562                         return 0;
9563                 }
9564
9565                 dev_err(&hdev->pdev->dev,
9566                         "Add vf vlan filter fail, ret =%u.\n",
9567                         req->resp_code);
9568         } else {
9569 #define HCLGE_VF_VLAN_DEL_NO_FOUND      1
9570                 if (!req->resp_code)
9571                         return 0;
9572
9573                 /* vf vlan filter is disabled when vf vlan table is full,
9574                  * then new vlan id will not be added into vf vlan table.
9575                  * Just return 0 without warning, avoid massive verbose
9576                  * print logs when unload.
9577                  */
9578                 if (req->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND)
9579                         return 0;
9580
9581                 dev_err(&hdev->pdev->dev,
9582                         "Kill vf vlan filter fail, ret =%u.\n",
9583                         req->resp_code);
9584         }
9585
9586         return -EIO;
9587 }
9588
9589 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, u16 vfid,
9590                                     bool is_kill, u16 vlan)
9591 {
9592         struct hclge_vport *vport = &hdev->vport[vfid];
9593         struct hclge_desc desc[2];
9594         int ret;
9595
9596         /* if vf vlan table is full, firmware will close vf vlan filter, it
9597          * is unable and unnecessary to add new vlan id to vf vlan filter.
9598          * If spoof check is enable, and vf vlan is full, it shouldn't add
9599          * new vlan, because tx packets with these vlan id will be dropped.
9600          */
9601         if (test_bit(vfid, hdev->vf_vlan_full) && !is_kill) {
9602                 if (vport->vf_info.spoofchk && vlan) {
9603                         dev_err(&hdev->pdev->dev,
9604                                 "Can't add vlan due to spoof check is on and vf vlan table is full\n");
9605                         return -EPERM;
9606                 }
9607                 return 0;
9608         }
9609
9610         ret = hclge_set_vf_vlan_filter_cmd(hdev, vfid, is_kill, vlan, desc);
9611         if (ret)
9612                 return ret;
9613
9614         return hclge_check_vf_vlan_cmd_status(hdev, vfid, is_kill, desc);
9615 }
9616
9617 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto,
9618                                       u16 vlan_id, bool is_kill)
9619 {
9620         struct hclge_vlan_filter_pf_cfg_cmd *req;
9621         struct hclge_desc desc;
9622         u8 vlan_offset_byte_val;
9623         u8 vlan_offset_byte;
9624         u8 vlan_offset_160;
9625         int ret;
9626
9627         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
9628
9629         vlan_offset_160 = vlan_id / HCLGE_VLAN_ID_OFFSET_STEP;
9630         vlan_offset_byte = (vlan_id % HCLGE_VLAN_ID_OFFSET_STEP) /
9631                            HCLGE_VLAN_BYTE_SIZE;
9632         vlan_offset_byte_val = 1 << (vlan_id % HCLGE_VLAN_BYTE_SIZE);
9633
9634         req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
9635         req->vlan_offset = vlan_offset_160;
9636         req->vlan_cfg = is_kill;
9637         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
9638
9639         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
9640         if (ret)
9641                 dev_err(&hdev->pdev->dev,
9642                         "port vlan command, send fail, ret =%d.\n", ret);
9643         return ret;
9644 }
9645
9646 static bool hclge_need_update_port_vlan(struct hclge_dev *hdev, u16 vport_id,
9647                                         u16 vlan_id, bool is_kill)
9648 {
9649         /* vlan 0 may be added twice when 8021q module is enabled */
9650         if (!is_kill && !vlan_id &&
9651             test_bit(vport_id, hdev->vlan_table[vlan_id]))
9652                 return false;
9653
9654         if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) {
9655                 dev_warn(&hdev->pdev->dev,
9656                          "Add port vlan failed, vport %u is already in vlan %u\n",
9657                          vport_id, vlan_id);
9658                 return false;
9659         }
9660
9661         if (is_kill &&
9662             !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) {
9663                 dev_warn(&hdev->pdev->dev,
9664                          "Delete port vlan failed, vport %u is not in vlan %u\n",
9665                          vport_id, vlan_id);
9666                 return false;
9667         }
9668
9669         return true;
9670 }
9671
9672 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto,
9673                                     u16 vport_id, u16 vlan_id,
9674                                     bool is_kill)
9675 {
9676         u16 vport_idx, vport_num = 0;
9677         int ret;
9678
9679         if (is_kill && !vlan_id)
9680                 return 0;
9681
9682         if (vlan_id >= VLAN_N_VID)
9683                 return -EINVAL;
9684
9685         ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id);
9686         if (ret) {
9687                 dev_err(&hdev->pdev->dev,
9688                         "Set %u vport vlan filter config fail, ret =%d.\n",
9689                         vport_id, ret);
9690                 return ret;
9691         }
9692
9693         if (!hclge_need_update_port_vlan(hdev, vport_id, vlan_id, is_kill))
9694                 return 0;
9695
9696         for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM)
9697                 vport_num++;
9698
9699         if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1))
9700                 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id,
9701                                                  is_kill);
9702
9703         return ret;
9704 }
9705
9706 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
9707 {
9708         struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
9709         struct hclge_vport_vtag_tx_cfg_cmd *req;
9710         struct hclge_dev *hdev = vport->back;
9711         struct hclge_desc desc;
9712         u16 bmap_index;
9713         int status;
9714
9715         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
9716
9717         req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
9718         req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
9719         req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
9720         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B,
9721                       vcfg->accept_tag1 ? 1 : 0);
9722         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B,
9723                       vcfg->accept_untag1 ? 1 : 0);
9724         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B,
9725                       vcfg->accept_tag2 ? 1 : 0);
9726         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B,
9727                       vcfg->accept_untag2 ? 1 : 0);
9728         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
9729                       vcfg->insert_tag1_en ? 1 : 0);
9730         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
9731                       vcfg->insert_tag2_en ? 1 : 0);
9732         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_TAG_SHIFT_MODE_EN_B,
9733                       vcfg->tag_shift_mode_en ? 1 : 0);
9734         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
9735
9736         req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
9737         bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD /
9738                         HCLGE_VF_NUM_PER_BYTE;
9739         req->vf_bitmap[bmap_index] =
9740                 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
9741
9742         status = hclge_cmd_send(&hdev->hw, &desc, 1);
9743         if (status)
9744                 dev_err(&hdev->pdev->dev,
9745                         "Send port txvlan cfg command fail, ret =%d\n",
9746                         status);
9747
9748         return status;
9749 }
9750
9751 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
9752 {
9753         struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
9754         struct hclge_vport_vtag_rx_cfg_cmd *req;
9755         struct hclge_dev *hdev = vport->back;
9756         struct hclge_desc desc;
9757         u16 bmap_index;
9758         int status;
9759
9760         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
9761
9762         req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
9763         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
9764                       vcfg->strip_tag1_en ? 1 : 0);
9765         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
9766                       vcfg->strip_tag2_en ? 1 : 0);
9767         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
9768                       vcfg->vlan1_vlan_prionly ? 1 : 0);
9769         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
9770                       vcfg->vlan2_vlan_prionly ? 1 : 0);
9771         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG1_EN_B,
9772                       vcfg->strip_tag1_discard_en ? 1 : 0);
9773         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG2_EN_B,
9774                       vcfg->strip_tag2_discard_en ? 1 : 0);
9775
9776         req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
9777         bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD /
9778                         HCLGE_VF_NUM_PER_BYTE;
9779         req->vf_bitmap[bmap_index] =
9780                 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
9781
9782         status = hclge_cmd_send(&hdev->hw, &desc, 1);
9783         if (status)
9784                 dev_err(&hdev->pdev->dev,
9785                         "Send port rxvlan cfg command fail, ret =%d\n",
9786                         status);
9787
9788         return status;
9789 }
9790
9791 static int hclge_vlan_offload_cfg(struct hclge_vport *vport,
9792                                   u16 port_base_vlan_state,
9793                                   u16 vlan_tag, u8 qos)
9794 {
9795         int ret;
9796
9797         if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) {
9798                 vport->txvlan_cfg.accept_tag1 = true;
9799                 vport->txvlan_cfg.insert_tag1_en = false;
9800                 vport->txvlan_cfg.default_tag1 = 0;
9801         } else {
9802                 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(vport->nic.pdev);
9803
9804                 vport->txvlan_cfg.accept_tag1 =
9805                         ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3;
9806                 vport->txvlan_cfg.insert_tag1_en = true;
9807                 vport->txvlan_cfg.default_tag1 = (qos << VLAN_PRIO_SHIFT) |
9808                                                  vlan_tag;
9809         }
9810
9811         vport->txvlan_cfg.accept_untag1 = true;
9812
9813         /* accept_tag2 and accept_untag2 are not supported on
9814          * pdev revision(0x20), new revision support them,
9815          * this two fields can not be configured by user.
9816          */
9817         vport->txvlan_cfg.accept_tag2 = true;
9818         vport->txvlan_cfg.accept_untag2 = true;
9819         vport->txvlan_cfg.insert_tag2_en = false;
9820         vport->txvlan_cfg.default_tag2 = 0;
9821         vport->txvlan_cfg.tag_shift_mode_en = true;
9822
9823         if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) {
9824                 vport->rxvlan_cfg.strip_tag1_en = false;
9825                 vport->rxvlan_cfg.strip_tag2_en =
9826                                 vport->rxvlan_cfg.rx_vlan_offload_en;
9827                 vport->rxvlan_cfg.strip_tag2_discard_en = false;
9828         } else {
9829                 vport->rxvlan_cfg.strip_tag1_en =
9830                                 vport->rxvlan_cfg.rx_vlan_offload_en;
9831                 vport->rxvlan_cfg.strip_tag2_en = true;
9832                 vport->rxvlan_cfg.strip_tag2_discard_en = true;
9833         }
9834
9835         vport->rxvlan_cfg.strip_tag1_discard_en = false;
9836         vport->rxvlan_cfg.vlan1_vlan_prionly = false;
9837         vport->rxvlan_cfg.vlan2_vlan_prionly = false;
9838
9839         ret = hclge_set_vlan_tx_offload_cfg(vport);
9840         if (ret)
9841                 return ret;
9842
9843         return hclge_set_vlan_rx_offload_cfg(vport);
9844 }
9845
9846 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
9847 {
9848         struct hclge_rx_vlan_type_cfg_cmd *rx_req;
9849         struct hclge_tx_vlan_type_cfg_cmd *tx_req;
9850         struct hclge_desc desc;
9851         int status;
9852
9853         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
9854         rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
9855         rx_req->ot_fst_vlan_type =
9856                 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
9857         rx_req->ot_sec_vlan_type =
9858                 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
9859         rx_req->in_fst_vlan_type =
9860                 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
9861         rx_req->in_sec_vlan_type =
9862                 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
9863
9864         status = hclge_cmd_send(&hdev->hw, &desc, 1);
9865         if (status) {
9866                 dev_err(&hdev->pdev->dev,
9867                         "Send rxvlan protocol type command fail, ret =%d\n",
9868                         status);
9869                 return status;
9870         }
9871
9872         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
9873
9874         tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data;
9875         tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
9876         tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
9877
9878         status = hclge_cmd_send(&hdev->hw, &desc, 1);
9879         if (status)
9880                 dev_err(&hdev->pdev->dev,
9881                         "Send txvlan protocol type command fail, ret =%d\n",
9882                         status);
9883
9884         return status;
9885 }
9886
9887 static int hclge_init_vlan_filter(struct hclge_dev *hdev)
9888 {
9889         struct hclge_vport *vport;
9890         int ret;
9891         int i;
9892
9893         if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
9894                 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
9895                                                   HCLGE_FILTER_FE_EGRESS_V1_B,
9896                                                   true, 0);
9897
9898         /* for revision 0x21, vf vlan filter is per function */
9899         for (i = 0; i < hdev->num_alloc_vport; i++) {
9900                 vport = &hdev->vport[i];
9901                 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
9902                                                  HCLGE_FILTER_FE_EGRESS, true,
9903                                                  vport->vport_id);
9904                 if (ret)
9905                         return ret;
9906                 vport->cur_vlan_fltr_en = true;
9907         }
9908
9909         return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT,
9910                                           HCLGE_FILTER_FE_INGRESS, true, 0);
9911 }
9912
9913 static int hclge_init_vlan_type(struct hclge_dev *hdev)
9914 {
9915         hdev->vlan_type_cfg.rx_in_fst_vlan_type = ETH_P_8021Q;
9916         hdev->vlan_type_cfg.rx_in_sec_vlan_type = ETH_P_8021Q;
9917         hdev->vlan_type_cfg.rx_ot_fst_vlan_type = ETH_P_8021Q;
9918         hdev->vlan_type_cfg.rx_ot_sec_vlan_type = ETH_P_8021Q;
9919         hdev->vlan_type_cfg.tx_ot_vlan_type = ETH_P_8021Q;
9920         hdev->vlan_type_cfg.tx_in_vlan_type = ETH_P_8021Q;
9921
9922         return hclge_set_vlan_protocol_type(hdev);
9923 }
9924
9925 static int hclge_init_vport_vlan_offload(struct hclge_dev *hdev)
9926 {
9927         struct hclge_port_base_vlan_config *cfg;
9928         struct hclge_vport *vport;
9929         int ret;
9930         int i;
9931
9932         for (i = 0; i < hdev->num_alloc_vport; i++) {
9933                 vport = &hdev->vport[i];
9934                 cfg = &vport->port_base_vlan_cfg;
9935
9936                 ret = hclge_vlan_offload_cfg(vport, cfg->state,
9937                                              cfg->vlan_info.vlan_tag,
9938                                              cfg->vlan_info.qos);
9939                 if (ret)
9940                         return ret;
9941         }
9942         return 0;
9943 }
9944
9945 static int hclge_init_vlan_config(struct hclge_dev *hdev)
9946 {
9947         struct hnae3_handle *handle = &hdev->vport[0].nic;
9948         int ret;
9949
9950         ret = hclge_init_vlan_filter(hdev);
9951         if (ret)
9952                 return ret;
9953
9954         ret = hclge_init_vlan_type(hdev);
9955         if (ret)
9956                 return ret;
9957
9958         ret = hclge_init_vport_vlan_offload(hdev);
9959         if (ret)
9960                 return ret;
9961
9962         return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
9963 }
9964
9965 static void hclge_add_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id,
9966                                        bool writen_to_tbl)
9967 {
9968         struct hclge_vport_vlan_cfg *vlan, *tmp;
9969         struct hclge_dev *hdev = vport->back;
9970
9971         mutex_lock(&hdev->vport_lock);
9972
9973         list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
9974                 if (vlan->vlan_id == vlan_id) {
9975                         mutex_unlock(&hdev->vport_lock);
9976                         return;
9977                 }
9978         }
9979
9980         vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
9981         if (!vlan) {
9982                 mutex_unlock(&hdev->vport_lock);
9983                 return;
9984         }
9985
9986         vlan->hd_tbl_status = writen_to_tbl;
9987         vlan->vlan_id = vlan_id;
9988
9989         list_add_tail(&vlan->node, &vport->vlan_list);
9990         mutex_unlock(&hdev->vport_lock);
9991 }
9992
9993 static int hclge_add_vport_all_vlan_table(struct hclge_vport *vport)
9994 {
9995         struct hclge_vport_vlan_cfg *vlan, *tmp;
9996         struct hclge_dev *hdev = vport->back;
9997         int ret;
9998
9999         mutex_lock(&hdev->vport_lock);
10000
10001         list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
10002                 if (!vlan->hd_tbl_status) {
10003                         ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q),
10004                                                        vport->vport_id,
10005                                                        vlan->vlan_id, false);
10006                         if (ret) {
10007                                 dev_err(&hdev->pdev->dev,
10008                                         "restore vport vlan list failed, ret=%d\n",
10009                                         ret);
10010
10011                                 mutex_unlock(&hdev->vport_lock);
10012                                 return ret;
10013                         }
10014                 }
10015                 vlan->hd_tbl_status = true;
10016         }
10017
10018         mutex_unlock(&hdev->vport_lock);
10019
10020         return 0;
10021 }
10022
10023 static void hclge_rm_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id,
10024                                       bool is_write_tbl)
10025 {
10026         struct hclge_vport_vlan_cfg *vlan, *tmp;
10027         struct hclge_dev *hdev = vport->back;
10028
10029         mutex_lock(&hdev->vport_lock);
10030
10031         list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
10032                 if (vlan->vlan_id == vlan_id) {
10033                         if (is_write_tbl && vlan->hd_tbl_status)
10034                                 hclge_set_vlan_filter_hw(hdev,
10035                                                          htons(ETH_P_8021Q),
10036                                                          vport->vport_id,
10037                                                          vlan_id,
10038                                                          true);
10039
10040                         list_del(&vlan->node);
10041                         kfree(vlan);
10042                         break;
10043                 }
10044         }
10045
10046         mutex_unlock(&hdev->vport_lock);
10047 }
10048
10049 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list)
10050 {
10051         struct hclge_vport_vlan_cfg *vlan, *tmp;
10052         struct hclge_dev *hdev = vport->back;
10053
10054         mutex_lock(&hdev->vport_lock);
10055
10056         list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
10057                 if (vlan->hd_tbl_status)
10058                         hclge_set_vlan_filter_hw(hdev,
10059                                                  htons(ETH_P_8021Q),
10060                                                  vport->vport_id,
10061                                                  vlan->vlan_id,
10062                                                  true);
10063
10064                 vlan->hd_tbl_status = false;
10065                 if (is_del_list) {
10066                         list_del(&vlan->node);
10067                         kfree(vlan);
10068                 }
10069         }
10070         clear_bit(vport->vport_id, hdev->vf_vlan_full);
10071         mutex_unlock(&hdev->vport_lock);
10072 }
10073
10074 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev)
10075 {
10076         struct hclge_vport_vlan_cfg *vlan, *tmp;
10077         struct hclge_vport *vport;
10078         int i;
10079
10080         mutex_lock(&hdev->vport_lock);
10081
10082         for (i = 0; i < hdev->num_alloc_vport; i++) {
10083                 vport = &hdev->vport[i];
10084                 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
10085                         list_del(&vlan->node);
10086                         kfree(vlan);
10087                 }
10088         }
10089
10090         mutex_unlock(&hdev->vport_lock);
10091 }
10092
10093 void hclge_restore_vport_port_base_vlan_config(struct hclge_dev *hdev)
10094 {
10095         struct hclge_vlan_info *vlan_info;
10096         struct hclge_vport *vport;
10097         u16 vlan_proto;
10098         u16 vlan_id;
10099         u16 state;
10100         int vf_id;
10101         int ret;
10102
10103         /* PF should restore all vfs port base vlan */
10104         for (vf_id = 0; vf_id < hdev->num_alloc_vfs; vf_id++) {
10105                 vport = &hdev->vport[vf_id + HCLGE_VF_VPORT_START_NUM];
10106                 vlan_info = vport->port_base_vlan_cfg.tbl_sta ?
10107                             &vport->port_base_vlan_cfg.vlan_info :
10108                             &vport->port_base_vlan_cfg.old_vlan_info;
10109
10110                 vlan_id = vlan_info->vlan_tag;
10111                 vlan_proto = vlan_info->vlan_proto;
10112                 state = vport->port_base_vlan_cfg.state;
10113
10114                 if (state != HNAE3_PORT_BASE_VLAN_DISABLE) {
10115                         clear_bit(vport->vport_id, hdev->vlan_table[vlan_id]);
10116                         ret = hclge_set_vlan_filter_hw(hdev, htons(vlan_proto),
10117                                                        vport->vport_id,
10118                                                        vlan_id, false);
10119                         vport->port_base_vlan_cfg.tbl_sta = ret == 0;
10120                 }
10121         }
10122 }
10123
10124 void hclge_restore_vport_vlan_table(struct hclge_vport *vport)
10125 {
10126         struct hclge_vport_vlan_cfg *vlan, *tmp;
10127         struct hclge_dev *hdev = vport->back;
10128         int ret;
10129
10130         mutex_lock(&hdev->vport_lock);
10131
10132         if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) {
10133                 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
10134                         ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q),
10135                                                        vport->vport_id,
10136                                                        vlan->vlan_id, false);
10137                         if (ret)
10138                                 break;
10139                         vlan->hd_tbl_status = true;
10140                 }
10141         }
10142
10143         mutex_unlock(&hdev->vport_lock);
10144 }
10145
10146 /* For global reset and imp reset, hardware will clear the mac table,
10147  * so we change the mac address state from ACTIVE to TO_ADD, then they
10148  * can be restored in the service task after reset complete. Furtherly,
10149  * the mac addresses with state TO_DEL or DEL_FAIL are unnecessary to
10150  * be restored after reset, so just remove these mac nodes from mac_list.
10151  */
10152 static void hclge_mac_node_convert_for_reset(struct list_head *list)
10153 {
10154         struct hclge_mac_node *mac_node, *tmp;
10155
10156         list_for_each_entry_safe(mac_node, tmp, list, node) {
10157                 if (mac_node->state == HCLGE_MAC_ACTIVE) {
10158                         mac_node->state = HCLGE_MAC_TO_ADD;
10159                 } else if (mac_node->state == HCLGE_MAC_TO_DEL) {
10160                         list_del(&mac_node->node);
10161                         kfree(mac_node);
10162                 }
10163         }
10164 }
10165
10166 void hclge_restore_mac_table_common(struct hclge_vport *vport)
10167 {
10168         spin_lock_bh(&vport->mac_list_lock);
10169
10170         hclge_mac_node_convert_for_reset(&vport->uc_mac_list);
10171         hclge_mac_node_convert_for_reset(&vport->mc_mac_list);
10172         set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state);
10173
10174         spin_unlock_bh(&vport->mac_list_lock);
10175 }
10176
10177 static void hclge_restore_hw_table(struct hclge_dev *hdev)
10178 {
10179         struct hclge_vport *vport = &hdev->vport[0];
10180         struct hnae3_handle *handle = &vport->nic;
10181
10182         hclge_restore_mac_table_common(vport);
10183         hclge_restore_vport_port_base_vlan_config(hdev);
10184         hclge_restore_vport_vlan_table(vport);
10185         set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state);
10186         hclge_restore_fd_entries(handle);
10187 }
10188
10189 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
10190 {
10191         struct hclge_vport *vport = hclge_get_vport(handle);
10192
10193         if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) {
10194                 vport->rxvlan_cfg.strip_tag1_en = false;
10195                 vport->rxvlan_cfg.strip_tag2_en = enable;
10196                 vport->rxvlan_cfg.strip_tag2_discard_en = false;
10197         } else {
10198                 vport->rxvlan_cfg.strip_tag1_en = enable;
10199                 vport->rxvlan_cfg.strip_tag2_en = true;
10200                 vport->rxvlan_cfg.strip_tag2_discard_en = true;
10201         }
10202
10203         vport->rxvlan_cfg.strip_tag1_discard_en = false;
10204         vport->rxvlan_cfg.vlan1_vlan_prionly = false;
10205         vport->rxvlan_cfg.vlan2_vlan_prionly = false;
10206         vport->rxvlan_cfg.rx_vlan_offload_en = enable;
10207
10208         return hclge_set_vlan_rx_offload_cfg(vport);
10209 }
10210
10211 static void hclge_set_vport_vlan_fltr_change(struct hclge_vport *vport)
10212 {
10213         struct hclge_dev *hdev = vport->back;
10214
10215         if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps))
10216                 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, &vport->state);
10217 }
10218
10219 static int hclge_update_vlan_filter_entries(struct hclge_vport *vport,
10220                                             u16 port_base_vlan_state,
10221                                             struct hclge_vlan_info *new_info,
10222                                             struct hclge_vlan_info *old_info)
10223 {
10224         struct hclge_dev *hdev = vport->back;
10225         int ret;
10226
10227         if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_ENABLE) {
10228                 hclge_rm_vport_all_vlan_table(vport, false);
10229                 /* force clear VLAN 0 */
10230                 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, true, 0);
10231                 if (ret)
10232                         return ret;
10233                 return hclge_set_vlan_filter_hw(hdev,
10234                                                  htons(new_info->vlan_proto),
10235                                                  vport->vport_id,
10236                                                  new_info->vlan_tag,
10237                                                  false);
10238         }
10239
10240         vport->port_base_vlan_cfg.tbl_sta = false;
10241
10242         /* force add VLAN 0 */
10243         ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, false, 0);
10244         if (ret)
10245                 return ret;
10246
10247         ret = hclge_set_vlan_filter_hw(hdev, htons(old_info->vlan_proto),
10248                                        vport->vport_id, old_info->vlan_tag,
10249                                        true);
10250         if (ret)
10251                 return ret;
10252
10253         return hclge_add_vport_all_vlan_table(vport);
10254 }
10255
10256 static bool hclge_need_update_vlan_filter(const struct hclge_vlan_info *new_cfg,
10257                                           const struct hclge_vlan_info *old_cfg)
10258 {
10259         if (new_cfg->vlan_tag != old_cfg->vlan_tag)
10260                 return true;
10261
10262         if (new_cfg->vlan_tag == 0 && (new_cfg->qos == 0 || old_cfg->qos == 0))
10263                 return true;
10264
10265         return false;
10266 }
10267
10268 static int hclge_modify_port_base_vlan_tag(struct hclge_vport *vport,
10269                                            struct hclge_vlan_info *new_info,
10270                                            struct hclge_vlan_info *old_info)
10271 {
10272         struct hclge_dev *hdev = vport->back;
10273         int ret;
10274
10275         /* add new VLAN tag */
10276         ret = hclge_set_vlan_filter_hw(hdev, htons(new_info->vlan_proto),
10277                                        vport->vport_id, new_info->vlan_tag,
10278                                        false);
10279         if (ret)
10280                 return ret;
10281
10282         vport->port_base_vlan_cfg.tbl_sta = false;
10283         /* remove old VLAN tag */
10284         if (old_info->vlan_tag == 0)
10285                 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id,
10286                                                true, 0);
10287         else
10288                 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q),
10289                                                vport->vport_id,
10290                                                old_info->vlan_tag, true);
10291         if (ret)
10292                 dev_err(&hdev->pdev->dev,
10293                         "failed to clear vport%u port base vlan %u, ret = %d.\n",
10294                         vport->vport_id, old_info->vlan_tag, ret);
10295
10296         return ret;
10297 }
10298
10299 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state,
10300                                     struct hclge_vlan_info *vlan_info)
10301 {
10302         struct hnae3_handle *nic = &vport->nic;
10303         struct hclge_vlan_info *old_vlan_info;
10304         int ret;
10305
10306         old_vlan_info = &vport->port_base_vlan_cfg.vlan_info;
10307
10308         ret = hclge_vlan_offload_cfg(vport, state, vlan_info->vlan_tag,
10309                                      vlan_info->qos);
10310         if (ret)
10311                 return ret;
10312
10313         if (!hclge_need_update_vlan_filter(vlan_info, old_vlan_info))
10314                 goto out;
10315
10316         if (state == HNAE3_PORT_BASE_VLAN_MODIFY)
10317                 ret = hclge_modify_port_base_vlan_tag(vport, vlan_info,
10318                                                       old_vlan_info);
10319         else
10320                 ret = hclge_update_vlan_filter_entries(vport, state, vlan_info,
10321                                                        old_vlan_info);
10322         if (ret)
10323                 return ret;
10324
10325 out:
10326         vport->port_base_vlan_cfg.state = state;
10327         if (state == HNAE3_PORT_BASE_VLAN_DISABLE)
10328                 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE;
10329         else
10330                 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE;
10331
10332         vport->port_base_vlan_cfg.old_vlan_info = *old_vlan_info;
10333         vport->port_base_vlan_cfg.vlan_info = *vlan_info;
10334         vport->port_base_vlan_cfg.tbl_sta = true;
10335         hclge_set_vport_vlan_fltr_change(vport);
10336
10337         return 0;
10338 }
10339
10340 static u16 hclge_get_port_base_vlan_state(struct hclge_vport *vport,
10341                                           enum hnae3_port_base_vlan_state state,
10342                                           u16 vlan, u8 qos)
10343 {
10344         if (state == HNAE3_PORT_BASE_VLAN_DISABLE) {
10345                 if (!vlan && !qos)
10346                         return HNAE3_PORT_BASE_VLAN_NOCHANGE;
10347
10348                 return HNAE3_PORT_BASE_VLAN_ENABLE;
10349         }
10350
10351         if (!vlan && !qos)
10352                 return HNAE3_PORT_BASE_VLAN_DISABLE;
10353
10354         if (vport->port_base_vlan_cfg.vlan_info.vlan_tag == vlan &&
10355             vport->port_base_vlan_cfg.vlan_info.qos == qos)
10356                 return HNAE3_PORT_BASE_VLAN_NOCHANGE;
10357
10358         return HNAE3_PORT_BASE_VLAN_MODIFY;
10359 }
10360
10361 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
10362                                     u16 vlan, u8 qos, __be16 proto)
10363 {
10364         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
10365         struct hclge_vport *vport = hclge_get_vport(handle);
10366         struct hclge_dev *hdev = vport->back;
10367         struct hclge_vlan_info vlan_info;
10368         u16 state;
10369         int ret;
10370
10371         if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
10372                 return -EOPNOTSUPP;
10373
10374         vport = hclge_get_vf_vport(hdev, vfid);
10375         if (!vport)
10376                 return -EINVAL;
10377
10378         /* qos is a 3 bits value, so can not be bigger than 7 */
10379         if (vlan > VLAN_N_VID - 1 || qos > 7)
10380                 return -EINVAL;
10381         if (proto != htons(ETH_P_8021Q))
10382                 return -EPROTONOSUPPORT;
10383
10384         state = hclge_get_port_base_vlan_state(vport,
10385                                                vport->port_base_vlan_cfg.state,
10386                                                vlan, qos);
10387         if (state == HNAE3_PORT_BASE_VLAN_NOCHANGE)
10388                 return 0;
10389
10390         vlan_info.vlan_tag = vlan;
10391         vlan_info.qos = qos;
10392         vlan_info.vlan_proto = ntohs(proto);
10393
10394         ret = hclge_update_port_base_vlan_cfg(vport, state, &vlan_info);
10395         if (ret) {
10396                 dev_err(&hdev->pdev->dev,
10397                         "failed to update port base vlan for vf %d, ret = %d\n",
10398                         vfid, ret);
10399                 return ret;
10400         }
10401
10402         /* there is a timewindow for PF to know VF unalive, it may
10403          * cause send mailbox fail, but it doesn't matter, VF will
10404          * query it when reinit.
10405          * for DEVICE_VERSION_V3, vf doesn't need to know about the port based
10406          * VLAN state.
10407          */
10408         if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) {
10409                 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state))
10410                         (void)hclge_push_vf_port_base_vlan_info(&hdev->vport[0],
10411                                                                 vport->vport_id,
10412                                                                 state,
10413                                                                 &vlan_info);
10414                 else
10415                         set_bit(HCLGE_VPORT_NEED_NOTIFY_VF_VLAN,
10416                                 &vport->need_notify);
10417         }
10418         return 0;
10419 }
10420
10421 static void hclge_clear_vf_vlan(struct hclge_dev *hdev)
10422 {
10423         struct hclge_vlan_info *vlan_info;
10424         struct hclge_vport *vport;
10425         int ret;
10426         int vf;
10427
10428         /* clear port base vlan for all vf */
10429         for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) {
10430                 vport = &hdev->vport[vf];
10431                 vlan_info = &vport->port_base_vlan_cfg.vlan_info;
10432
10433                 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q),
10434                                                vport->vport_id,
10435                                                vlan_info->vlan_tag, true);
10436                 if (ret)
10437                         dev_err(&hdev->pdev->dev,
10438                                 "failed to clear vf vlan for vf%d, ret = %d\n",
10439                                 vf - HCLGE_VF_VPORT_START_NUM, ret);
10440         }
10441 }
10442
10443 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
10444                           u16 vlan_id, bool is_kill)
10445 {
10446         struct hclge_vport *vport = hclge_get_vport(handle);
10447         struct hclge_dev *hdev = vport->back;
10448         bool writen_to_tbl = false;
10449         int ret = 0;
10450
10451         /* When device is resetting or reset failed, firmware is unable to
10452          * handle mailbox. Just record the vlan id, and remove it after
10453          * reset finished.
10454          */
10455         if ((test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) ||
10456              test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) && is_kill) {
10457                 set_bit(vlan_id, vport->vlan_del_fail_bmap);
10458                 return -EBUSY;
10459         }
10460
10461         /* when port base vlan enabled, we use port base vlan as the vlan
10462          * filter entry. In this case, we don't update vlan filter table
10463          * when user add new vlan or remove exist vlan, just update the vport
10464          * vlan list. The vlan id in vlan list will be writen in vlan filter
10465          * table until port base vlan disabled
10466          */
10467         if (handle->port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) {
10468                 ret = hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id,
10469                                                vlan_id, is_kill);
10470                 writen_to_tbl = true;
10471         }
10472
10473         if (!ret) {
10474                 if (!is_kill)
10475                         hclge_add_vport_vlan_table(vport, vlan_id,
10476                                                    writen_to_tbl);
10477                 else if (is_kill && vlan_id != 0)
10478                         hclge_rm_vport_vlan_table(vport, vlan_id, false);
10479         } else if (is_kill) {
10480                 /* when remove hw vlan filter failed, record the vlan id,
10481                  * and try to remove it from hw later, to be consistence
10482                  * with stack
10483                  */
10484                 set_bit(vlan_id, vport->vlan_del_fail_bmap);
10485         }
10486
10487         hclge_set_vport_vlan_fltr_change(vport);
10488
10489         return ret;
10490 }
10491
10492 static void hclge_sync_vlan_fltr_state(struct hclge_dev *hdev)
10493 {
10494         struct hclge_vport *vport;
10495         int ret;
10496         u16 i;
10497
10498         for (i = 0; i < hdev->num_alloc_vport; i++) {
10499                 vport = &hdev->vport[i];
10500                 if (!test_and_clear_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE,
10501                                         &vport->state))
10502                         continue;
10503
10504                 ret = hclge_enable_vport_vlan_filter(vport,
10505                                                      vport->req_vlan_fltr_en);
10506                 if (ret) {
10507                         dev_err(&hdev->pdev->dev,
10508                                 "failed to sync vlan filter state for vport%u, ret = %d\n",
10509                                 vport->vport_id, ret);
10510                         set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE,
10511                                 &vport->state);
10512                         return;
10513                 }
10514         }
10515 }
10516
10517 static void hclge_sync_vlan_filter(struct hclge_dev *hdev)
10518 {
10519 #define HCLGE_MAX_SYNC_COUNT    60
10520
10521         int i, ret, sync_cnt = 0;
10522         u16 vlan_id;
10523
10524         /* start from vport 1 for PF is always alive */
10525         for (i = 0; i < hdev->num_alloc_vport; i++) {
10526                 struct hclge_vport *vport = &hdev->vport[i];
10527
10528                 vlan_id = find_first_bit(vport->vlan_del_fail_bmap,
10529                                          VLAN_N_VID);
10530                 while (vlan_id != VLAN_N_VID) {
10531                         ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q),
10532                                                        vport->vport_id, vlan_id,
10533                                                        true);
10534                         if (ret && ret != -EINVAL)
10535                                 return;
10536
10537                         clear_bit(vlan_id, vport->vlan_del_fail_bmap);
10538                         hclge_rm_vport_vlan_table(vport, vlan_id, false);
10539                         hclge_set_vport_vlan_fltr_change(vport);
10540
10541                         sync_cnt++;
10542                         if (sync_cnt >= HCLGE_MAX_SYNC_COUNT)
10543                                 return;
10544
10545                         vlan_id = find_first_bit(vport->vlan_del_fail_bmap,
10546                                                  VLAN_N_VID);
10547                 }
10548         }
10549
10550         hclge_sync_vlan_fltr_state(hdev);
10551 }
10552
10553 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps)
10554 {
10555         struct hclge_config_max_frm_size_cmd *req;
10556         struct hclge_desc desc;
10557
10558         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
10559
10560         req = (struct hclge_config_max_frm_size_cmd *)desc.data;
10561         req->max_frm_size = cpu_to_le16(new_mps);
10562         req->min_frm_size = HCLGE_MAC_MIN_FRAME;
10563
10564         return hclge_cmd_send(&hdev->hw, &desc, 1);
10565 }
10566
10567 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
10568 {
10569         struct hclge_vport *vport = hclge_get_vport(handle);
10570
10571         return hclge_set_vport_mtu(vport, new_mtu);
10572 }
10573
10574 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu)
10575 {
10576         struct hclge_dev *hdev = vport->back;
10577         int i, max_frm_size, ret;
10578
10579         /* HW supprt 2 layer vlan */
10580         max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN;
10581         if (max_frm_size < HCLGE_MAC_MIN_FRAME ||
10582             max_frm_size > hdev->ae_dev->dev_specs.max_frm_size)
10583                 return -EINVAL;
10584
10585         max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
10586         mutex_lock(&hdev->vport_lock);
10587         /* VF's mps must fit within hdev->mps */
10588         if (vport->vport_id && max_frm_size > hdev->mps) {
10589                 mutex_unlock(&hdev->vport_lock);
10590                 return -EINVAL;
10591         } else if (vport->vport_id) {
10592                 vport->mps = max_frm_size;
10593                 mutex_unlock(&hdev->vport_lock);
10594                 return 0;
10595         }
10596
10597         /* PF's mps must be greater then VF's mps */
10598         for (i = 1; i < hdev->num_alloc_vport; i++)
10599                 if (max_frm_size < hdev->vport[i].mps) {
10600                         dev_err(&hdev->pdev->dev,
10601                                 "failed to set pf mtu for less than vport %d, mps = %u.\n",
10602                                 i, hdev->vport[i].mps);
10603                         mutex_unlock(&hdev->vport_lock);
10604                         return -EINVAL;
10605                 }
10606
10607         hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
10608
10609         ret = hclge_set_mac_mtu(hdev, max_frm_size);
10610         if (ret) {
10611                 dev_err(&hdev->pdev->dev,
10612                         "Change mtu fail, ret =%d\n", ret);
10613                 goto out;
10614         }
10615
10616         hdev->mps = max_frm_size;
10617         vport->mps = max_frm_size;
10618
10619         ret = hclge_buffer_alloc(hdev);
10620         if (ret)
10621                 dev_err(&hdev->pdev->dev,
10622                         "Allocate buffer fail, ret =%d\n", ret);
10623
10624 out:
10625         hclge_notify_client(hdev, HNAE3_UP_CLIENT);
10626         mutex_unlock(&hdev->vport_lock);
10627         return ret;
10628 }
10629
10630 static int hclge_reset_tqp_cmd_send(struct hclge_dev *hdev, u16 queue_id,
10631                                     bool enable)
10632 {
10633         struct hclge_reset_tqp_queue_cmd *req;
10634         struct hclge_desc desc;
10635         int ret;
10636
10637         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
10638
10639         req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
10640         req->tqp_id = cpu_to_le16(queue_id);
10641         if (enable)
10642                 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, 1U);
10643
10644         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
10645         if (ret) {
10646                 dev_err(&hdev->pdev->dev,
10647                         "Send tqp reset cmd error, status =%d\n", ret);
10648                 return ret;
10649         }
10650
10651         return 0;
10652 }
10653
10654 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id,
10655                                   u8 *reset_status)
10656 {
10657         struct hclge_reset_tqp_queue_cmd *req;
10658         struct hclge_desc desc;
10659         int ret;
10660
10661         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
10662
10663         req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
10664         req->tqp_id = cpu_to_le16(queue_id);
10665
10666         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
10667         if (ret) {
10668                 dev_err(&hdev->pdev->dev,
10669                         "Get reset status error, status =%d\n", ret);
10670                 return ret;
10671         }
10672
10673         *reset_status = hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
10674
10675         return 0;
10676 }
10677
10678 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id)
10679 {
10680         struct hclge_comm_tqp *tqp;
10681         struct hnae3_queue *queue;
10682
10683         queue = handle->kinfo.tqp[queue_id];
10684         tqp = container_of(queue, struct hclge_comm_tqp, q);
10685
10686         return tqp->index;
10687 }
10688
10689 static int hclge_reset_tqp_cmd(struct hnae3_handle *handle)
10690 {
10691         struct hclge_vport *vport = hclge_get_vport(handle);
10692         struct hclge_dev *hdev = vport->back;
10693         u16 reset_try_times = 0;
10694         u8 reset_status;
10695         u16 queue_gid;
10696         int ret;
10697         u16 i;
10698
10699         for (i = 0; i < handle->kinfo.num_tqps; i++) {
10700                 queue_gid = hclge_covert_handle_qid_global(handle, i);
10701                 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, true);
10702                 if (ret) {
10703                         dev_err(&hdev->pdev->dev,
10704                                 "failed to send reset tqp cmd, ret = %d\n",
10705                                 ret);
10706                         return ret;
10707                 }
10708
10709                 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
10710                         ret = hclge_get_reset_status(hdev, queue_gid,
10711                                                      &reset_status);
10712                         if (ret)
10713                                 return ret;
10714
10715                         if (reset_status)
10716                                 break;
10717
10718                         /* Wait for tqp hw reset */
10719                         usleep_range(1000, 1200);
10720                 }
10721
10722                 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
10723                         dev_err(&hdev->pdev->dev,
10724                                 "wait for tqp hw reset timeout\n");
10725                         return -ETIME;
10726                 }
10727
10728                 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, false);
10729                 if (ret) {
10730                         dev_err(&hdev->pdev->dev,
10731                                 "failed to deassert soft reset, ret = %d\n",
10732                                 ret);
10733                         return ret;
10734                 }
10735                 reset_try_times = 0;
10736         }
10737         return 0;
10738 }
10739
10740 static int hclge_reset_rcb(struct hnae3_handle *handle)
10741 {
10742 #define HCLGE_RESET_RCB_NOT_SUPPORT     0U
10743 #define HCLGE_RESET_RCB_SUCCESS         1U
10744
10745         struct hclge_vport *vport = hclge_get_vport(handle);
10746         struct hclge_dev *hdev = vport->back;
10747         struct hclge_reset_cmd *req;
10748         struct hclge_desc desc;
10749         u8 return_status;
10750         u16 queue_gid;
10751         int ret;
10752
10753         queue_gid = hclge_covert_handle_qid_global(handle, 0);
10754
10755         req = (struct hclge_reset_cmd *)desc.data;
10756         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
10757         hnae3_set_bit(req->fun_reset_rcb, HCLGE_CFG_RESET_RCB_B, 1);
10758         req->fun_reset_rcb_vqid_start = cpu_to_le16(queue_gid);
10759         req->fun_reset_rcb_vqid_num = cpu_to_le16(handle->kinfo.num_tqps);
10760
10761         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
10762         if (ret) {
10763                 dev_err(&hdev->pdev->dev,
10764                         "failed to send rcb reset cmd, ret = %d\n", ret);
10765                 return ret;
10766         }
10767
10768         return_status = req->fun_reset_rcb_return_status;
10769         if (return_status == HCLGE_RESET_RCB_SUCCESS)
10770                 return 0;
10771
10772         if (return_status != HCLGE_RESET_RCB_NOT_SUPPORT) {
10773                 dev_err(&hdev->pdev->dev, "failed to reset rcb, ret = %u\n",
10774                         return_status);
10775                 return -EIO;
10776         }
10777
10778         /* if reset rcb cmd is unsupported, we need to send reset tqp cmd
10779          * again to reset all tqps
10780          */
10781         return hclge_reset_tqp_cmd(handle);
10782 }
10783
10784 int hclge_reset_tqp(struct hnae3_handle *handle)
10785 {
10786         struct hclge_vport *vport = hclge_get_vport(handle);
10787         struct hclge_dev *hdev = vport->back;
10788         int ret;
10789
10790         /* only need to disable PF's tqp */
10791         if (!vport->vport_id) {
10792                 ret = hclge_tqp_enable(handle, false);
10793                 if (ret) {
10794                         dev_err(&hdev->pdev->dev,
10795                                 "failed to disable tqp, ret = %d\n", ret);
10796                         return ret;
10797                 }
10798         }
10799
10800         return hclge_reset_rcb(handle);
10801 }
10802
10803 static u32 hclge_get_fw_version(struct hnae3_handle *handle)
10804 {
10805         struct hclge_vport *vport = hclge_get_vport(handle);
10806         struct hclge_dev *hdev = vport->back;
10807
10808         return hdev->fw_version;
10809 }
10810
10811 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
10812 {
10813         struct phy_device *phydev = hdev->hw.mac.phydev;
10814
10815         if (!phydev)
10816                 return;
10817
10818         phy_set_asym_pause(phydev, rx_en, tx_en);
10819 }
10820
10821 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
10822 {
10823         int ret;
10824
10825         if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
10826                 return 0;
10827
10828         ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
10829         if (ret)
10830                 dev_err(&hdev->pdev->dev,
10831                         "configure pauseparam error, ret = %d.\n", ret);
10832
10833         return ret;
10834 }
10835
10836 int hclge_cfg_flowctrl(struct hclge_dev *hdev)
10837 {
10838         struct phy_device *phydev = hdev->hw.mac.phydev;
10839         u16 remote_advertising = 0;
10840         u16 local_advertising;
10841         u32 rx_pause, tx_pause;
10842         u8 flowctl;
10843
10844         if (!phydev->link)
10845                 return 0;
10846
10847         if (!phydev->autoneg)
10848                 return hclge_mac_pause_setup_hw(hdev);
10849
10850         local_advertising = linkmode_adv_to_lcl_adv_t(phydev->advertising);
10851
10852         if (phydev->pause)
10853                 remote_advertising = LPA_PAUSE_CAP;
10854
10855         if (phydev->asym_pause)
10856                 remote_advertising |= LPA_PAUSE_ASYM;
10857
10858         flowctl = mii_resolve_flowctrl_fdx(local_advertising,
10859                                            remote_advertising);
10860         tx_pause = flowctl & FLOW_CTRL_TX;
10861         rx_pause = flowctl & FLOW_CTRL_RX;
10862
10863         if (phydev->duplex == HCLGE_MAC_HALF) {
10864                 tx_pause = 0;
10865                 rx_pause = 0;
10866         }
10867
10868         return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
10869 }
10870
10871 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
10872                                  u32 *rx_en, u32 *tx_en)
10873 {
10874         struct hclge_vport *vport = hclge_get_vport(handle);
10875         struct hclge_dev *hdev = vport->back;
10876         u8 media_type = hdev->hw.mac.media_type;
10877
10878         *auto_neg = (media_type == HNAE3_MEDIA_TYPE_COPPER) ?
10879                     hclge_get_autoneg(handle) : 0;
10880
10881         if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
10882                 *rx_en = 0;
10883                 *tx_en = 0;
10884                 return;
10885         }
10886
10887         if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
10888                 *rx_en = 1;
10889                 *tx_en = 0;
10890         } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
10891                 *tx_en = 1;
10892                 *rx_en = 0;
10893         } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
10894                 *rx_en = 1;
10895                 *tx_en = 1;
10896         } else {
10897                 *rx_en = 0;
10898                 *tx_en = 0;
10899         }
10900 }
10901
10902 static void hclge_record_user_pauseparam(struct hclge_dev *hdev,
10903                                          u32 rx_en, u32 tx_en)
10904 {
10905         if (rx_en && tx_en)
10906                 hdev->fc_mode_last_time = HCLGE_FC_FULL;
10907         else if (rx_en && !tx_en)
10908                 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
10909         else if (!rx_en && tx_en)
10910                 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
10911         else
10912                 hdev->fc_mode_last_time = HCLGE_FC_NONE;
10913
10914         hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
10915 }
10916
10917 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
10918                                 u32 rx_en, u32 tx_en)
10919 {
10920         struct hclge_vport *vport = hclge_get_vport(handle);
10921         struct hclge_dev *hdev = vport->back;
10922         struct phy_device *phydev = hdev->hw.mac.phydev;
10923         u32 fc_autoneg;
10924
10925         if (phydev || hnae3_dev_phy_imp_supported(hdev)) {
10926                 fc_autoneg = hclge_get_autoneg(handle);
10927                 if (auto_neg != fc_autoneg) {
10928                         dev_info(&hdev->pdev->dev,
10929                                  "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
10930                         return -EOPNOTSUPP;
10931                 }
10932         }
10933
10934         if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
10935                 dev_info(&hdev->pdev->dev,
10936                          "Priority flow control enabled. Cannot set link flow control.\n");
10937                 return -EOPNOTSUPP;
10938         }
10939
10940         hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
10941
10942         hclge_record_user_pauseparam(hdev, rx_en, tx_en);
10943
10944         if (!auto_neg || hnae3_dev_phy_imp_supported(hdev))
10945                 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
10946
10947         if (phydev)
10948                 return phy_start_aneg(phydev);
10949
10950         return -EOPNOTSUPP;
10951 }
10952
10953 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
10954                                           u8 *auto_neg, u32 *speed, u8 *duplex, u32 *lane_num)
10955 {
10956         struct hclge_vport *vport = hclge_get_vport(handle);
10957         struct hclge_dev *hdev = vport->back;
10958
10959         if (speed)
10960                 *speed = hdev->hw.mac.speed;
10961         if (duplex)
10962                 *duplex = hdev->hw.mac.duplex;
10963         if (auto_neg)
10964                 *auto_neg = hdev->hw.mac.autoneg;
10965         if (lane_num)
10966                 *lane_num = hdev->hw.mac.lane_num;
10967 }
10968
10969 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type,
10970                                  u8 *module_type)
10971 {
10972         struct hclge_vport *vport = hclge_get_vport(handle);
10973         struct hclge_dev *hdev = vport->back;
10974
10975         /* When nic is down, the service task is not running, doesn't update
10976          * the port information per second. Query the port information before
10977          * return the media type, ensure getting the correct media information.
10978          */
10979         hclge_update_port_info(hdev);
10980
10981         if (media_type)
10982                 *media_type = hdev->hw.mac.media_type;
10983
10984         if (module_type)
10985                 *module_type = hdev->hw.mac.module_type;
10986 }
10987
10988 static void hclge_get_mdix_mode(struct hnae3_handle *handle,
10989                                 u8 *tp_mdix_ctrl, u8 *tp_mdix)
10990 {
10991         struct hclge_vport *vport = hclge_get_vport(handle);
10992         struct hclge_dev *hdev = vport->back;
10993         struct phy_device *phydev = hdev->hw.mac.phydev;
10994         int mdix_ctrl, mdix, is_resolved;
10995         unsigned int retval;
10996
10997         if (!phydev) {
10998                 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
10999                 *tp_mdix = ETH_TP_MDI_INVALID;
11000                 return;
11001         }
11002
11003         phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
11004
11005         retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
11006         mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
11007                                     HCLGE_PHY_MDIX_CTRL_S);
11008
11009         retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
11010         mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
11011         is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
11012
11013         phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
11014
11015         switch (mdix_ctrl) {
11016         case 0x0:
11017                 *tp_mdix_ctrl = ETH_TP_MDI;
11018                 break;
11019         case 0x1:
11020                 *tp_mdix_ctrl = ETH_TP_MDI_X;
11021                 break;
11022         case 0x3:
11023                 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
11024                 break;
11025         default:
11026                 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
11027                 break;
11028         }
11029
11030         if (!is_resolved)
11031                 *tp_mdix = ETH_TP_MDI_INVALID;
11032         else if (mdix)
11033                 *tp_mdix = ETH_TP_MDI_X;
11034         else
11035                 *tp_mdix = ETH_TP_MDI;
11036 }
11037
11038 static void hclge_info_show(struct hclge_dev *hdev)
11039 {
11040         struct hnae3_handle *handle = &hdev->vport->nic;
11041         struct device *dev = &hdev->pdev->dev;
11042
11043         dev_info(dev, "PF info begin:\n");
11044
11045         dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps);
11046         dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc);
11047         dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc);
11048         dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport);
11049         dev_info(dev, "Numbers of VF for this PF: %u\n", hdev->num_req_vfs);
11050         dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map);
11051         dev_info(dev, "Total buffer size for TX/RX: %u\n", hdev->pkt_buf_size);
11052         dev_info(dev, "TX buffer size for each TC: %u\n", hdev->tx_buf_size);
11053         dev_info(dev, "DV buffer size for each TC: %u\n", hdev->dv_buf_size);
11054         dev_info(dev, "This is %s PF\n",
11055                  hdev->flag & HCLGE_FLAG_MAIN ? "main" : "not main");
11056         dev_info(dev, "DCB %s\n",
11057                  handle->kinfo.tc_info.dcb_ets_active ? "enable" : "disable");
11058         dev_info(dev, "MQPRIO %s\n",
11059                  handle->kinfo.tc_info.mqprio_active ? "enable" : "disable");
11060         dev_info(dev, "Default tx spare buffer size: %u\n",
11061                  hdev->tx_spare_buf_size);
11062
11063         dev_info(dev, "PF info end.\n");
11064 }
11065
11066 static int hclge_init_nic_client_instance(struct hnae3_ae_dev *ae_dev,
11067                                           struct hclge_vport *vport)
11068 {
11069         struct hnae3_client *client = vport->nic.client;
11070         struct hclge_dev *hdev = ae_dev->priv;
11071         int rst_cnt = hdev->rst_stats.reset_cnt;
11072         int ret;
11073
11074         ret = client->ops->init_instance(&vport->nic);
11075         if (ret)
11076                 return ret;
11077
11078         set_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state);
11079         if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) ||
11080             rst_cnt != hdev->rst_stats.reset_cnt) {
11081                 ret = -EBUSY;
11082                 goto init_nic_err;
11083         }
11084
11085         /* Enable nic hw error interrupts */
11086         ret = hclge_config_nic_hw_error(hdev, true);
11087         if (ret) {
11088                 dev_err(&ae_dev->pdev->dev,
11089                         "fail(%d) to enable hw error interrupts\n", ret);
11090                 goto init_nic_err;
11091         }
11092
11093         hnae3_set_client_init_flag(client, ae_dev, 1);
11094
11095         if (netif_msg_drv(&hdev->vport->nic))
11096                 hclge_info_show(hdev);
11097
11098         return ret;
11099
11100 init_nic_err:
11101         clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state);
11102         while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
11103                 msleep(HCLGE_WAIT_RESET_DONE);
11104
11105         client->ops->uninit_instance(&vport->nic, 0);
11106
11107         return ret;
11108 }
11109
11110 static int hclge_init_roce_client_instance(struct hnae3_ae_dev *ae_dev,
11111                                            struct hclge_vport *vport)
11112 {
11113         struct hclge_dev *hdev = ae_dev->priv;
11114         struct hnae3_client *client;
11115         int rst_cnt;
11116         int ret;
11117
11118         if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client ||
11119             !hdev->nic_client)
11120                 return 0;
11121
11122         client = hdev->roce_client;
11123         ret = hclge_init_roce_base_info(vport);
11124         if (ret)
11125                 return ret;
11126
11127         rst_cnt = hdev->rst_stats.reset_cnt;
11128         ret = client->ops->init_instance(&vport->roce);
11129         if (ret)
11130                 return ret;
11131
11132         set_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state);
11133         if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) ||
11134             rst_cnt != hdev->rst_stats.reset_cnt) {
11135                 ret = -EBUSY;
11136                 goto init_roce_err;
11137         }
11138
11139         /* Enable roce ras interrupts */
11140         ret = hclge_config_rocee_ras_interrupt(hdev, true);
11141         if (ret) {
11142                 dev_err(&ae_dev->pdev->dev,
11143                         "fail(%d) to enable roce ras interrupts\n", ret);
11144                 goto init_roce_err;
11145         }
11146
11147         hnae3_set_client_init_flag(client, ae_dev, 1);
11148
11149         return 0;
11150
11151 init_roce_err:
11152         clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state);
11153         while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
11154                 msleep(HCLGE_WAIT_RESET_DONE);
11155
11156         hdev->roce_client->ops->uninit_instance(&vport->roce, 0);
11157
11158         return ret;
11159 }
11160
11161 static int hclge_init_client_instance(struct hnae3_client *client,
11162                                       struct hnae3_ae_dev *ae_dev)
11163 {
11164         struct hclge_dev *hdev = ae_dev->priv;
11165         struct hclge_vport *vport = &hdev->vport[0];
11166         int ret;
11167
11168         switch (client->type) {
11169         case HNAE3_CLIENT_KNIC:
11170                 hdev->nic_client = client;
11171                 vport->nic.client = client;
11172                 ret = hclge_init_nic_client_instance(ae_dev, vport);
11173                 if (ret)
11174                         goto clear_nic;
11175
11176                 ret = hclge_init_roce_client_instance(ae_dev, vport);
11177                 if (ret)
11178                         goto clear_roce;
11179
11180                 break;
11181         case HNAE3_CLIENT_ROCE:
11182                 if (hnae3_dev_roce_supported(hdev)) {
11183                         hdev->roce_client = client;
11184                         vport->roce.client = client;
11185                 }
11186
11187                 ret = hclge_init_roce_client_instance(ae_dev, vport);
11188                 if (ret)
11189                         goto clear_roce;
11190
11191                 break;
11192         default:
11193                 return -EINVAL;
11194         }
11195
11196         return 0;
11197
11198 clear_nic:
11199         hdev->nic_client = NULL;
11200         vport->nic.client = NULL;
11201         return ret;
11202 clear_roce:
11203         hdev->roce_client = NULL;
11204         vport->roce.client = NULL;
11205         return ret;
11206 }
11207
11208 static void hclge_uninit_client_instance(struct hnae3_client *client,
11209                                          struct hnae3_ae_dev *ae_dev)
11210 {
11211         struct hclge_dev *hdev = ae_dev->priv;
11212         struct hclge_vport *vport = &hdev->vport[0];
11213
11214         if (hdev->roce_client) {
11215                 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state);
11216                 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
11217                         msleep(HCLGE_WAIT_RESET_DONE);
11218
11219                 hdev->roce_client->ops->uninit_instance(&vport->roce, 0);
11220                 hdev->roce_client = NULL;
11221                 vport->roce.client = NULL;
11222         }
11223         if (client->type == HNAE3_CLIENT_ROCE)
11224                 return;
11225         if (hdev->nic_client && client->ops->uninit_instance) {
11226                 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state);
11227                 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
11228                         msleep(HCLGE_WAIT_RESET_DONE);
11229
11230                 client->ops->uninit_instance(&vport->nic, 0);
11231                 hdev->nic_client = NULL;
11232                 vport->nic.client = NULL;
11233         }
11234 }
11235
11236 static int hclge_dev_mem_map(struct hclge_dev *hdev)
11237 {
11238         struct pci_dev *pdev = hdev->pdev;
11239         struct hclge_hw *hw = &hdev->hw;
11240
11241         /* for device does not have device memory, return directly */
11242         if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGE_MEM_BAR)))
11243                 return 0;
11244
11245         hw->hw.mem_base =
11246                 devm_ioremap_wc(&pdev->dev,
11247                                 pci_resource_start(pdev, HCLGE_MEM_BAR),
11248                                 pci_resource_len(pdev, HCLGE_MEM_BAR));
11249         if (!hw->hw.mem_base) {
11250                 dev_err(&pdev->dev, "failed to map device memory\n");
11251                 return -EFAULT;
11252         }
11253
11254         return 0;
11255 }
11256
11257 static int hclge_pci_init(struct hclge_dev *hdev)
11258 {
11259         struct pci_dev *pdev = hdev->pdev;
11260         struct hclge_hw *hw;
11261         int ret;
11262
11263         ret = pci_enable_device(pdev);
11264         if (ret) {
11265                 dev_err(&pdev->dev, "failed to enable PCI device\n");
11266                 return ret;
11267         }
11268
11269         ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
11270         if (ret) {
11271                 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
11272                 if (ret) {
11273                         dev_err(&pdev->dev,
11274                                 "can't set consistent PCI DMA");
11275                         goto err_disable_device;
11276                 }
11277                 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
11278         }
11279
11280         ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
11281         if (ret) {
11282                 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
11283                 goto err_disable_device;
11284         }
11285
11286         pci_set_master(pdev);
11287         hw = &hdev->hw;
11288         hw->hw.io_base = pcim_iomap(pdev, 2, 0);
11289         if (!hw->hw.io_base) {
11290                 dev_err(&pdev->dev, "Can't map configuration register space\n");
11291                 ret = -ENOMEM;
11292                 goto err_release_regions;
11293         }
11294
11295         ret = hclge_dev_mem_map(hdev);
11296         if (ret)
11297                 goto err_unmap_io_base;
11298
11299         hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
11300
11301         return 0;
11302
11303 err_unmap_io_base:
11304         pcim_iounmap(pdev, hdev->hw.hw.io_base);
11305 err_release_regions:
11306         pci_release_regions(pdev);
11307 err_disable_device:
11308         pci_disable_device(pdev);
11309
11310         return ret;
11311 }
11312
11313 static void hclge_pci_uninit(struct hclge_dev *hdev)
11314 {
11315         struct pci_dev *pdev = hdev->pdev;
11316
11317         if (hdev->hw.hw.mem_base)
11318                 devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base);
11319
11320         pcim_iounmap(pdev, hdev->hw.hw.io_base);
11321         pci_free_irq_vectors(pdev);
11322         pci_release_mem_regions(pdev);
11323         pci_disable_device(pdev);
11324 }
11325
11326 static void hclge_state_init(struct hclge_dev *hdev)
11327 {
11328         set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
11329         set_bit(HCLGE_STATE_DOWN, &hdev->state);
11330         clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
11331         clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
11332         clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state);
11333         clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
11334         clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
11335 }
11336
11337 static void hclge_state_uninit(struct hclge_dev *hdev)
11338 {
11339         set_bit(HCLGE_STATE_DOWN, &hdev->state);
11340         set_bit(HCLGE_STATE_REMOVING, &hdev->state);
11341
11342         if (hdev->reset_timer.function)
11343                 del_timer_sync(&hdev->reset_timer);
11344         if (hdev->service_task.work.func)
11345                 cancel_delayed_work_sync(&hdev->service_task);
11346 }
11347
11348 static void hclge_reset_prepare_general(struct hnae3_ae_dev *ae_dev,
11349                                         enum hnae3_reset_type rst_type)
11350 {
11351 #define HCLGE_RESET_RETRY_WAIT_MS       500
11352 #define HCLGE_RESET_RETRY_CNT   5
11353
11354         struct hclge_dev *hdev = ae_dev->priv;
11355         int retry_cnt = 0;
11356         int ret;
11357
11358         while (retry_cnt++ < HCLGE_RESET_RETRY_CNT) {
11359                 down(&hdev->reset_sem);
11360                 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
11361                 hdev->reset_type = rst_type;
11362                 ret = hclge_reset_prepare(hdev);
11363                 if (!ret && !hdev->reset_pending)
11364                         break;
11365
11366                 dev_err(&hdev->pdev->dev,
11367                         "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n",
11368                         ret, hdev->reset_pending, retry_cnt);
11369                 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
11370                 up(&hdev->reset_sem);
11371                 msleep(HCLGE_RESET_RETRY_WAIT_MS);
11372         }
11373
11374         /* disable misc vector before reset done */
11375         hclge_enable_vector(&hdev->misc_vector, false);
11376         set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
11377
11378         if (hdev->reset_type == HNAE3_FLR_RESET)
11379                 hdev->rst_stats.flr_rst_cnt++;
11380 }
11381
11382 static void hclge_reset_done(struct hnae3_ae_dev *ae_dev)
11383 {
11384         struct hclge_dev *hdev = ae_dev->priv;
11385         int ret;
11386
11387         hclge_enable_vector(&hdev->misc_vector, true);
11388
11389         ret = hclge_reset_rebuild(hdev);
11390         if (ret)
11391                 dev_err(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", ret);
11392
11393         hdev->reset_type = HNAE3_NONE_RESET;
11394         clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
11395         up(&hdev->reset_sem);
11396 }
11397
11398 static void hclge_clear_resetting_state(struct hclge_dev *hdev)
11399 {
11400         u16 i;
11401
11402         for (i = 0; i < hdev->num_alloc_vport; i++) {
11403                 struct hclge_vport *vport = &hdev->vport[i];
11404                 int ret;
11405
11406                  /* Send cmd to clear vport's FUNC_RST_ING */
11407                 ret = hclge_set_vf_rst(hdev, vport->vport_id, false);
11408                 if (ret)
11409                         dev_warn(&hdev->pdev->dev,
11410                                  "clear vport(%u) rst failed %d!\n",
11411                                  vport->vport_id, ret);
11412         }
11413 }
11414
11415 static int hclge_clear_hw_resource(struct hclge_dev *hdev)
11416 {
11417         struct hclge_desc desc;
11418         int ret;
11419
11420         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CLEAR_HW_RESOURCE, false);
11421
11422         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
11423         /* This new command is only supported by new firmware, it will
11424          * fail with older firmware. Error value -EOPNOSUPP can only be
11425          * returned by older firmware running this command, to keep code
11426          * backward compatible we will override this value and return
11427          * success.
11428          */
11429         if (ret && ret != -EOPNOTSUPP) {
11430                 dev_err(&hdev->pdev->dev,
11431                         "failed to clear hw resource, ret = %d\n", ret);
11432                 return ret;
11433         }
11434         return 0;
11435 }
11436
11437 static void hclge_init_rxd_adv_layout(struct hclge_dev *hdev)
11438 {
11439         if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev))
11440                 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 1);
11441 }
11442
11443 static void hclge_uninit_rxd_adv_layout(struct hclge_dev *hdev)
11444 {
11445         if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev))
11446                 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 0);
11447 }
11448
11449 static struct hclge_wol_info *hclge_get_wol_info(struct hnae3_handle *handle)
11450 {
11451         struct hclge_vport *vport = hclge_get_vport(handle);
11452
11453         return &vport->back->hw.mac.wol;
11454 }
11455
11456 static int hclge_get_wol_supported_mode(struct hclge_dev *hdev,
11457                                         u32 *wol_supported)
11458 {
11459         struct hclge_query_wol_supported_cmd *wol_supported_cmd;
11460         struct hclge_desc desc;
11461         int ret;
11462
11463         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_GET_SUPPORTED_MODE,
11464                                    true);
11465         wol_supported_cmd = (struct hclge_query_wol_supported_cmd *)desc.data;
11466
11467         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
11468         if (ret) {
11469                 dev_err(&hdev->pdev->dev,
11470                         "failed to query wol supported, ret = %d\n", ret);
11471                 return ret;
11472         }
11473
11474         *wol_supported = le32_to_cpu(wol_supported_cmd->supported_wake_mode);
11475
11476         return 0;
11477 }
11478
11479 static int hclge_set_wol_cfg(struct hclge_dev *hdev,
11480                              struct hclge_wol_info *wol_info)
11481 {
11482         struct hclge_wol_cfg_cmd *wol_cfg_cmd;
11483         struct hclge_desc desc;
11484         int ret;
11485
11486         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_CFG, false);
11487         wol_cfg_cmd = (struct hclge_wol_cfg_cmd *)desc.data;
11488         wol_cfg_cmd->wake_on_lan_mode = cpu_to_le32(wol_info->wol_current_mode);
11489         wol_cfg_cmd->sopass_size = wol_info->wol_sopass_size;
11490         memcpy(wol_cfg_cmd->sopass, wol_info->wol_sopass, SOPASS_MAX);
11491
11492         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
11493         if (ret)
11494                 dev_err(&hdev->pdev->dev,
11495                         "failed to set wol config, ret = %d\n", ret);
11496
11497         return ret;
11498 }
11499
11500 static int hclge_update_wol(struct hclge_dev *hdev)
11501 {
11502         struct hclge_wol_info *wol_info = &hdev->hw.mac.wol;
11503
11504         if (!hnae3_ae_dev_wol_supported(hdev->ae_dev))
11505                 return 0;
11506
11507         return hclge_set_wol_cfg(hdev, wol_info);
11508 }
11509
11510 static int hclge_init_wol(struct hclge_dev *hdev)
11511 {
11512         struct hclge_wol_info *wol_info = &hdev->hw.mac.wol;
11513         int ret;
11514
11515         if (!hnae3_ae_dev_wol_supported(hdev->ae_dev))
11516                 return 0;
11517
11518         memset(wol_info, 0, sizeof(struct hclge_wol_info));
11519         ret = hclge_get_wol_supported_mode(hdev,
11520                                            &wol_info->wol_support_mode);
11521         if (ret) {
11522                 wol_info->wol_support_mode = 0;
11523                 return ret;
11524         }
11525
11526         return hclge_update_wol(hdev);
11527 }
11528
11529 static void hclge_get_wol(struct hnae3_handle *handle,
11530                           struct ethtool_wolinfo *wol)
11531 {
11532         struct hclge_wol_info *wol_info = hclge_get_wol_info(handle);
11533
11534         wol->supported = wol_info->wol_support_mode;
11535         wol->wolopts = wol_info->wol_current_mode;
11536         if (wol_info->wol_current_mode & WAKE_MAGICSECURE)
11537                 memcpy(wol->sopass, wol_info->wol_sopass, SOPASS_MAX);
11538 }
11539
11540 static int hclge_set_wol(struct hnae3_handle *handle,
11541                          struct ethtool_wolinfo *wol)
11542 {
11543         struct hclge_wol_info *wol_info = hclge_get_wol_info(handle);
11544         struct hclge_vport *vport = hclge_get_vport(handle);
11545         u32 wol_mode;
11546         int ret;
11547
11548         wol_mode = wol->wolopts;
11549         if (wol_mode & ~wol_info->wol_support_mode)
11550                 return -EINVAL;
11551
11552         wol_info->wol_current_mode = wol_mode;
11553         if (wol_mode & WAKE_MAGICSECURE) {
11554                 memcpy(wol_info->wol_sopass, wol->sopass, SOPASS_MAX);
11555                 wol_info->wol_sopass_size = SOPASS_MAX;
11556         } else {
11557                 wol_info->wol_sopass_size = 0;
11558         }
11559
11560         ret = hclge_set_wol_cfg(vport->back, wol_info);
11561         if (ret)
11562                 wol_info->wol_current_mode = 0;
11563
11564         return ret;
11565 }
11566
11567 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
11568 {
11569         struct pci_dev *pdev = ae_dev->pdev;
11570         struct hclge_dev *hdev;
11571         int ret;
11572
11573         hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
11574         if (!hdev)
11575                 return -ENOMEM;
11576
11577         hdev->pdev = pdev;
11578         hdev->ae_dev = ae_dev;
11579         hdev->reset_type = HNAE3_NONE_RESET;
11580         hdev->reset_level = HNAE3_FUNC_RESET;
11581         ae_dev->priv = hdev;
11582
11583         /* HW supprt 2 layer vlan */
11584         hdev->mps = ETH_FRAME_LEN + ETH_FCS_LEN + 2 * VLAN_HLEN;
11585
11586         mutex_init(&hdev->vport_lock);
11587         spin_lock_init(&hdev->fd_rule_lock);
11588         sema_init(&hdev->reset_sem, 1);
11589
11590         ret = hclge_pci_init(hdev);
11591         if (ret)
11592                 goto out;
11593
11594         ret = hclge_devlink_init(hdev);
11595         if (ret)
11596                 goto err_pci_uninit;
11597
11598         /* Firmware command queue initialize */
11599         ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw);
11600         if (ret)
11601                 goto err_devlink_uninit;
11602
11603         /* Firmware command initialize */
11604         ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version,
11605                                   true, hdev->reset_pending);
11606         if (ret)
11607                 goto err_cmd_uninit;
11608
11609         ret  = hclge_clear_hw_resource(hdev);
11610         if (ret)
11611                 goto err_cmd_uninit;
11612
11613         ret = hclge_get_cap(hdev);
11614         if (ret)
11615                 goto err_cmd_uninit;
11616
11617         ret = hclge_query_dev_specs(hdev);
11618         if (ret) {
11619                 dev_err(&pdev->dev, "failed to query dev specifications, ret = %d.\n",
11620                         ret);
11621                 goto err_cmd_uninit;
11622         }
11623
11624         ret = hclge_configure(hdev);
11625         if (ret) {
11626                 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
11627                 goto err_cmd_uninit;
11628         }
11629
11630         ret = hclge_init_msi(hdev);
11631         if (ret) {
11632                 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
11633                 goto err_cmd_uninit;
11634         }
11635
11636         ret = hclge_misc_irq_init(hdev);
11637         if (ret)
11638                 goto err_msi_uninit;
11639
11640         ret = hclge_alloc_tqps(hdev);
11641         if (ret) {
11642                 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
11643                 goto err_msi_irq_uninit;
11644         }
11645
11646         ret = hclge_alloc_vport(hdev);
11647         if (ret)
11648                 goto err_msi_irq_uninit;
11649
11650         ret = hclge_map_tqp(hdev);
11651         if (ret)
11652                 goto err_msi_irq_uninit;
11653
11654         if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) {
11655                 if (hnae3_dev_phy_imp_supported(hdev))
11656                         ret = hclge_update_tp_port_info(hdev);
11657                 else
11658                         ret = hclge_mac_mdio_config(hdev);
11659
11660                 if (ret)
11661                         goto err_msi_irq_uninit;
11662         }
11663
11664         ret = hclge_init_umv_space(hdev);
11665         if (ret)
11666                 goto err_mdiobus_unreg;
11667
11668         ret = hclge_mac_init(hdev);
11669         if (ret) {
11670                 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
11671                 goto err_mdiobus_unreg;
11672         }
11673
11674         ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
11675         if (ret) {
11676                 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
11677                 goto err_mdiobus_unreg;
11678         }
11679
11680         ret = hclge_config_gro(hdev);
11681         if (ret)
11682                 goto err_mdiobus_unreg;
11683
11684         ret = hclge_init_vlan_config(hdev);
11685         if (ret) {
11686                 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
11687                 goto err_mdiobus_unreg;
11688         }
11689
11690         ret = hclge_tm_schd_init(hdev);
11691         if (ret) {
11692                 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
11693                 goto err_mdiobus_unreg;
11694         }
11695
11696         ret = hclge_comm_rss_init_cfg(&hdev->vport->nic, hdev->ae_dev,
11697                                       &hdev->rss_cfg);
11698         if (ret) {
11699                 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret);
11700                 goto err_mdiobus_unreg;
11701         }
11702
11703         ret = hclge_rss_init_hw(hdev);
11704         if (ret) {
11705                 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
11706                 goto err_mdiobus_unreg;
11707         }
11708
11709         ret = init_mgr_tbl(hdev);
11710         if (ret) {
11711                 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret);
11712                 goto err_mdiobus_unreg;
11713         }
11714
11715         ret = hclge_init_fd_config(hdev);
11716         if (ret) {
11717                 dev_err(&pdev->dev,
11718                         "fd table init fail, ret=%d\n", ret);
11719                 goto err_mdiobus_unreg;
11720         }
11721
11722         ret = hclge_ptp_init(hdev);
11723         if (ret)
11724                 goto err_mdiobus_unreg;
11725
11726         ret = hclge_update_port_info(hdev);
11727         if (ret)
11728                 goto err_mdiobus_unreg;
11729
11730         INIT_KFIFO(hdev->mac_tnl_log);
11731
11732         hclge_dcb_ops_set(hdev);
11733
11734         timer_setup(&hdev->reset_timer, hclge_reset_timer, 0);
11735         INIT_DELAYED_WORK(&hdev->service_task, hclge_service_task);
11736
11737         hclge_clear_all_event_cause(hdev);
11738         hclge_clear_resetting_state(hdev);
11739
11740         /* Log and clear the hw errors those already occurred */
11741         if (hnae3_dev_ras_imp_supported(hdev))
11742                 hclge_handle_occurred_error(hdev);
11743         else
11744                 hclge_handle_all_hns_hw_errors(ae_dev);
11745
11746         /* request delayed reset for the error recovery because an immediate
11747          * global reset on a PF affecting pending initialization of other PFs
11748          */
11749         if (ae_dev->hw_err_reset_req) {
11750                 enum hnae3_reset_type reset_level;
11751
11752                 reset_level = hclge_get_reset_level(ae_dev,
11753                                                     &ae_dev->hw_err_reset_req);
11754                 hclge_set_def_reset_request(ae_dev, reset_level);
11755                 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL);
11756         }
11757
11758         hclge_init_rxd_adv_layout(hdev);
11759
11760         /* Enable MISC vector(vector0) */
11761         hclge_enable_vector(&hdev->misc_vector, true);
11762
11763         ret = hclge_init_wol(hdev);
11764         if (ret)
11765                 dev_warn(&pdev->dev,
11766                          "failed to wake on lan init, ret = %d\n", ret);
11767
11768         hclge_state_init(hdev);
11769         hdev->last_reset_time = jiffies;
11770
11771         dev_info(&hdev->pdev->dev, "%s driver initialization finished.\n",
11772                  HCLGE_DRIVER_NAME);
11773
11774         hclge_task_schedule(hdev, round_jiffies_relative(HZ));
11775
11776         return 0;
11777
11778 err_mdiobus_unreg:
11779         if (hdev->hw.mac.phydev)
11780                 mdiobus_unregister(hdev->hw.mac.mdio_bus);
11781 err_msi_irq_uninit:
11782         hclge_misc_irq_uninit(hdev);
11783 err_msi_uninit:
11784         pci_free_irq_vectors(pdev);
11785 err_cmd_uninit:
11786         hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw);
11787 err_devlink_uninit:
11788         hclge_devlink_uninit(hdev);
11789 err_pci_uninit:
11790         pcim_iounmap(pdev, hdev->hw.hw.io_base);
11791         pci_release_regions(pdev);
11792         pci_disable_device(pdev);
11793 out:
11794         mutex_destroy(&hdev->vport_lock);
11795         return ret;
11796 }
11797
11798 static void hclge_stats_clear(struct hclge_dev *hdev)
11799 {
11800         memset(&hdev->mac_stats, 0, sizeof(hdev->mac_stats));
11801         memset(&hdev->fec_stats, 0, sizeof(hdev->fec_stats));
11802 }
11803
11804 static int hclge_set_mac_spoofchk(struct hclge_dev *hdev, int vf, bool enable)
11805 {
11806         return hclge_config_switch_param(hdev, vf, enable,
11807                                          HCLGE_SWITCH_ANTI_SPOOF_MASK);
11808 }
11809
11810 static int hclge_set_vlan_spoofchk(struct hclge_dev *hdev, int vf, bool enable)
11811 {
11812         return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
11813                                           HCLGE_FILTER_FE_NIC_INGRESS_B,
11814                                           enable, vf);
11815 }
11816
11817 static int hclge_set_vf_spoofchk_hw(struct hclge_dev *hdev, int vf, bool enable)
11818 {
11819         int ret;
11820
11821         ret = hclge_set_mac_spoofchk(hdev, vf, enable);
11822         if (ret) {
11823                 dev_err(&hdev->pdev->dev,
11824                         "Set vf %d mac spoof check %s failed, ret=%d\n",
11825                         vf, enable ? "on" : "off", ret);
11826                 return ret;
11827         }
11828
11829         ret = hclge_set_vlan_spoofchk(hdev, vf, enable);
11830         if (ret)
11831                 dev_err(&hdev->pdev->dev,
11832                         "Set vf %d vlan spoof check %s failed, ret=%d\n",
11833                         vf, enable ? "on" : "off", ret);
11834
11835         return ret;
11836 }
11837
11838 static int hclge_set_vf_spoofchk(struct hnae3_handle *handle, int vf,
11839                                  bool enable)
11840 {
11841         struct hclge_vport *vport = hclge_get_vport(handle);
11842         struct hclge_dev *hdev = vport->back;
11843         u32 new_spoofchk = enable ? 1 : 0;
11844         int ret;
11845
11846         if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
11847                 return -EOPNOTSUPP;
11848
11849         vport = hclge_get_vf_vport(hdev, vf);
11850         if (!vport)
11851                 return -EINVAL;
11852
11853         if (vport->vf_info.spoofchk == new_spoofchk)
11854                 return 0;
11855
11856         if (enable && test_bit(vport->vport_id, hdev->vf_vlan_full))
11857                 dev_warn(&hdev->pdev->dev,
11858                          "vf %d vlan table is full, enable spoof check may cause its packet send fail\n",
11859                          vf);
11860         else if (enable && hclge_is_umv_space_full(vport, true))
11861                 dev_warn(&hdev->pdev->dev,
11862                          "vf %d mac table is full, enable spoof check may cause its packet send fail\n",
11863                          vf);
11864
11865         ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, enable);
11866         if (ret)
11867                 return ret;
11868
11869         vport->vf_info.spoofchk = new_spoofchk;
11870         return 0;
11871 }
11872
11873 static int hclge_reset_vport_spoofchk(struct hclge_dev *hdev)
11874 {
11875         struct hclge_vport *vport = hdev->vport;
11876         int ret;
11877         int i;
11878
11879         if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
11880                 return 0;
11881
11882         /* resume the vf spoof check state after reset */
11883         for (i = 0; i < hdev->num_alloc_vport; i++) {
11884                 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id,
11885                                                vport->vf_info.spoofchk);
11886                 if (ret)
11887                         return ret;
11888
11889                 vport++;
11890         }
11891
11892         return 0;
11893 }
11894
11895 static int hclge_set_vf_trust(struct hnae3_handle *handle, int vf, bool enable)
11896 {
11897         struct hclge_vport *vport = hclge_get_vport(handle);
11898         struct hclge_dev *hdev = vport->back;
11899         u32 new_trusted = enable ? 1 : 0;
11900
11901         vport = hclge_get_vf_vport(hdev, vf);
11902         if (!vport)
11903                 return -EINVAL;
11904
11905         if (vport->vf_info.trusted == new_trusted)
11906                 return 0;
11907
11908         vport->vf_info.trusted = new_trusted;
11909         set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
11910         hclge_task_schedule(hdev, 0);
11911
11912         return 0;
11913 }
11914
11915 static void hclge_reset_vf_rate(struct hclge_dev *hdev)
11916 {
11917         int ret;
11918         int vf;
11919
11920         /* reset vf rate to default value */
11921         for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) {
11922                 struct hclge_vport *vport = &hdev->vport[vf];
11923
11924                 vport->vf_info.max_tx_rate = 0;
11925                 ret = hclge_tm_qs_shaper_cfg(vport, vport->vf_info.max_tx_rate);
11926                 if (ret)
11927                         dev_err(&hdev->pdev->dev,
11928                                 "vf%d failed to reset to default, ret=%d\n",
11929                                 vf - HCLGE_VF_VPORT_START_NUM, ret);
11930         }
11931 }
11932
11933 static int hclge_vf_rate_param_check(struct hclge_dev *hdev,
11934                                      int min_tx_rate, int max_tx_rate)
11935 {
11936         if (min_tx_rate != 0 ||
11937             max_tx_rate < 0 || max_tx_rate > hdev->hw.mac.max_speed) {
11938                 dev_err(&hdev->pdev->dev,
11939                         "min_tx_rate:%d [0], max_tx_rate:%d [0, %u]\n",
11940                         min_tx_rate, max_tx_rate, hdev->hw.mac.max_speed);
11941                 return -EINVAL;
11942         }
11943
11944         return 0;
11945 }
11946
11947 static int hclge_set_vf_rate(struct hnae3_handle *handle, int vf,
11948                              int min_tx_rate, int max_tx_rate, bool force)
11949 {
11950         struct hclge_vport *vport = hclge_get_vport(handle);
11951         struct hclge_dev *hdev = vport->back;
11952         int ret;
11953
11954         ret = hclge_vf_rate_param_check(hdev, min_tx_rate, max_tx_rate);
11955         if (ret)
11956                 return ret;
11957
11958         vport = hclge_get_vf_vport(hdev, vf);
11959         if (!vport)
11960                 return -EINVAL;
11961
11962         if (!force && max_tx_rate == vport->vf_info.max_tx_rate)
11963                 return 0;
11964
11965         ret = hclge_tm_qs_shaper_cfg(vport, max_tx_rate);
11966         if (ret)
11967                 return ret;
11968
11969         vport->vf_info.max_tx_rate = max_tx_rate;
11970
11971         return 0;
11972 }
11973
11974 static int hclge_resume_vf_rate(struct hclge_dev *hdev)
11975 {
11976         struct hnae3_handle *handle = &hdev->vport->nic;
11977         struct hclge_vport *vport;
11978         int ret;
11979         int vf;
11980
11981         /* resume the vf max_tx_rate after reset */
11982         for (vf = 0; vf < pci_num_vf(hdev->pdev); vf++) {
11983                 vport = hclge_get_vf_vport(hdev, vf);
11984                 if (!vport)
11985                         return -EINVAL;
11986
11987                 /* zero means max rate, after reset, firmware already set it to
11988                  * max rate, so just continue.
11989                  */
11990                 if (!vport->vf_info.max_tx_rate)
11991                         continue;
11992
11993                 ret = hclge_set_vf_rate(handle, vf, 0,
11994                                         vport->vf_info.max_tx_rate, true);
11995                 if (ret) {
11996                         dev_err(&hdev->pdev->dev,
11997                                 "vf%d failed to resume tx_rate:%u, ret=%d\n",
11998                                 vf, vport->vf_info.max_tx_rate, ret);
11999                         return ret;
12000                 }
12001         }
12002
12003         return 0;
12004 }
12005
12006 static void hclge_reset_vport_state(struct hclge_dev *hdev)
12007 {
12008         struct hclge_vport *vport = hdev->vport;
12009         int i;
12010
12011         for (i = 0; i < hdev->num_alloc_vport; i++) {
12012                 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
12013                 vport++;
12014         }
12015 }
12016
12017 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
12018 {
12019         struct hclge_dev *hdev = ae_dev->priv;
12020         struct pci_dev *pdev = ae_dev->pdev;
12021         int ret;
12022
12023         set_bit(HCLGE_STATE_DOWN, &hdev->state);
12024
12025         hclge_stats_clear(hdev);
12026         /* NOTE: pf reset needn't to clear or restore pf and vf table entry.
12027          * so here should not clean table in memory.
12028          */
12029         if (hdev->reset_type == HNAE3_IMP_RESET ||
12030             hdev->reset_type == HNAE3_GLOBAL_RESET) {
12031                 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table));
12032                 memset(hdev->vf_vlan_full, 0, sizeof(hdev->vf_vlan_full));
12033                 bitmap_set(hdev->vport_config_block, 0, hdev->num_alloc_vport);
12034                 hclge_reset_umv_space(hdev);
12035         }
12036
12037         ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version,
12038                                   true, hdev->reset_pending);
12039         if (ret) {
12040                 dev_err(&pdev->dev, "Cmd queue init failed\n");
12041                 return ret;
12042         }
12043
12044         ret = hclge_map_tqp(hdev);
12045         if (ret) {
12046                 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
12047                 return ret;
12048         }
12049
12050         ret = hclge_mac_init(hdev);
12051         if (ret) {
12052                 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
12053                 return ret;
12054         }
12055
12056         ret = hclge_tp_port_init(hdev);
12057         if (ret) {
12058                 dev_err(&pdev->dev, "failed to init tp port, ret = %d\n",
12059                         ret);
12060                 return ret;
12061         }
12062
12063         ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
12064         if (ret) {
12065                 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
12066                 return ret;
12067         }
12068
12069         ret = hclge_config_gro(hdev);
12070         if (ret)
12071                 return ret;
12072
12073         ret = hclge_init_vlan_config(hdev);
12074         if (ret) {
12075                 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
12076                 return ret;
12077         }
12078
12079         ret = hclge_tm_init_hw(hdev, true);
12080         if (ret) {
12081                 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret);
12082                 return ret;
12083         }
12084
12085         ret = hclge_rss_init_hw(hdev);
12086         if (ret) {
12087                 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
12088                 return ret;
12089         }
12090
12091         ret = init_mgr_tbl(hdev);
12092         if (ret) {
12093                 dev_err(&pdev->dev,
12094                         "failed to reinit manager table, ret = %d\n", ret);
12095                 return ret;
12096         }
12097
12098         ret = hclge_init_fd_config(hdev);
12099         if (ret) {
12100                 dev_err(&pdev->dev, "fd table init fail, ret=%d\n", ret);
12101                 return ret;
12102         }
12103
12104         ret = hclge_ptp_init(hdev);
12105         if (ret)
12106                 return ret;
12107
12108         /* Log and clear the hw errors those already occurred */
12109         if (hnae3_dev_ras_imp_supported(hdev))
12110                 hclge_handle_occurred_error(hdev);
12111         else
12112                 hclge_handle_all_hns_hw_errors(ae_dev);
12113
12114         /* Re-enable the hw error interrupts because
12115          * the interrupts get disabled on global reset.
12116          */
12117         ret = hclge_config_nic_hw_error(hdev, true);
12118         if (ret) {
12119                 dev_err(&pdev->dev,
12120                         "fail(%d) to re-enable NIC hw error interrupts\n",
12121                         ret);
12122                 return ret;
12123         }
12124
12125         if (hdev->roce_client) {
12126                 ret = hclge_config_rocee_ras_interrupt(hdev, true);
12127                 if (ret) {
12128                         dev_err(&pdev->dev,
12129                                 "fail(%d) to re-enable roce ras interrupts\n",
12130                                 ret);
12131                         return ret;
12132                 }
12133         }
12134
12135         hclge_reset_vport_state(hdev);
12136         ret = hclge_reset_vport_spoofchk(hdev);
12137         if (ret)
12138                 return ret;
12139
12140         ret = hclge_resume_vf_rate(hdev);
12141         if (ret)
12142                 return ret;
12143
12144         hclge_init_rxd_adv_layout(hdev);
12145
12146         ret = hclge_update_wol(hdev);
12147         if (ret)
12148                 dev_warn(&pdev->dev,
12149                          "failed to update wol config, ret = %d\n", ret);
12150
12151         dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
12152                  HCLGE_DRIVER_NAME);
12153
12154         return 0;
12155 }
12156
12157 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
12158 {
12159         struct hclge_dev *hdev = ae_dev->priv;
12160         struct hclge_mac *mac = &hdev->hw.mac;
12161
12162         hclge_reset_vf_rate(hdev);
12163         hclge_clear_vf_vlan(hdev);
12164         hclge_state_uninit(hdev);
12165         hclge_ptp_uninit(hdev);
12166         hclge_uninit_rxd_adv_layout(hdev);
12167         hclge_uninit_mac_table(hdev);
12168         hclge_del_all_fd_entries(hdev);
12169
12170         if (mac->phydev)
12171                 mdiobus_unregister(mac->mdio_bus);
12172
12173         /* Disable MISC vector(vector0) */
12174         hclge_enable_vector(&hdev->misc_vector, false);
12175         synchronize_irq(hdev->misc_vector.vector_irq);
12176
12177         /* Disable all hw interrupts */
12178         hclge_config_mac_tnl_int(hdev, false);
12179         hclge_config_nic_hw_error(hdev, false);
12180         hclge_config_rocee_ras_interrupt(hdev, false);
12181
12182         hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw);
12183         hclge_misc_irq_uninit(hdev);
12184         hclge_devlink_uninit(hdev);
12185         hclge_pci_uninit(hdev);
12186         hclge_uninit_vport_vlan_table(hdev);
12187         mutex_destroy(&hdev->vport_lock);
12188         ae_dev->priv = NULL;
12189 }
12190
12191 static u32 hclge_get_max_channels(struct hnae3_handle *handle)
12192 {
12193         struct hclge_vport *vport = hclge_get_vport(handle);
12194         struct hclge_dev *hdev = vport->back;
12195
12196         return min_t(u32, hdev->pf_rss_size_max, vport->alloc_tqps);
12197 }
12198
12199 static void hclge_get_channels(struct hnae3_handle *handle,
12200                                struct ethtool_channels *ch)
12201 {
12202         ch->max_combined = hclge_get_max_channels(handle);
12203         ch->other_count = 1;
12204         ch->max_other = 1;
12205         ch->combined_count = handle->kinfo.rss_size;
12206 }
12207
12208 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
12209                                         u16 *alloc_tqps, u16 *max_rss_size)
12210 {
12211         struct hclge_vport *vport = hclge_get_vport(handle);
12212         struct hclge_dev *hdev = vport->back;
12213
12214         *alloc_tqps = vport->alloc_tqps;
12215         *max_rss_size = hdev->pf_rss_size_max;
12216 }
12217
12218 static int hclge_set_rss_tc_mode_cfg(struct hnae3_handle *handle)
12219 {
12220         struct hclge_vport *vport = hclge_get_vport(handle);
12221         u16 tc_offset[HCLGE_MAX_TC_NUM] = {0};
12222         struct hclge_dev *hdev = vport->back;
12223         u16 tc_size[HCLGE_MAX_TC_NUM] = {0};
12224         u16 tc_valid[HCLGE_MAX_TC_NUM];
12225         u16 roundup_size;
12226         unsigned int i;
12227
12228         roundup_size = roundup_pow_of_two(vport->nic.kinfo.rss_size);
12229         roundup_size = ilog2(roundup_size);
12230         /* Set the RSS TC mode according to the new RSS size */
12231         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
12232                 tc_valid[i] = 0;
12233
12234                 if (!(hdev->hw_tc_map & BIT(i)))
12235                         continue;
12236
12237                 tc_valid[i] = 1;
12238                 tc_size[i] = roundup_size;
12239                 tc_offset[i] = vport->nic.kinfo.rss_size * i;
12240         }
12241
12242         return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid,
12243                                           tc_size);
12244 }
12245
12246 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num,
12247                               bool rxfh_configured)
12248 {
12249         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
12250         struct hclge_vport *vport = hclge_get_vport(handle);
12251         struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
12252         struct hclge_dev *hdev = vport->back;
12253         u16 cur_rss_size = kinfo->rss_size;
12254         u16 cur_tqps = kinfo->num_tqps;
12255         u32 *rss_indir;
12256         unsigned int i;
12257         int ret;
12258
12259         kinfo->req_rss_size = new_tqps_num;
12260
12261         ret = hclge_tm_vport_map_update(hdev);
12262         if (ret) {
12263                 dev_err(&hdev->pdev->dev, "tm vport map fail, ret =%d\n", ret);
12264                 return ret;
12265         }
12266
12267         ret = hclge_set_rss_tc_mode_cfg(handle);
12268         if (ret)
12269                 return ret;
12270
12271         /* RSS indirection table has been configured by user */
12272         if (rxfh_configured)
12273                 goto out;
12274
12275         /* Reinitializes the rss indirect table according to the new RSS size */
12276         rss_indir = kcalloc(ae_dev->dev_specs.rss_ind_tbl_size, sizeof(u32),
12277                             GFP_KERNEL);
12278         if (!rss_indir)
12279                 return -ENOMEM;
12280
12281         for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++)
12282                 rss_indir[i] = i % kinfo->rss_size;
12283
12284         ret = hclge_set_rss(handle, rss_indir, NULL, 0);
12285         if (ret)
12286                 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
12287                         ret);
12288
12289         kfree(rss_indir);
12290
12291 out:
12292         if (!ret)
12293                 dev_info(&hdev->pdev->dev,
12294                          "Channels changed, rss_size from %u to %u, tqps from %u to %u",
12295                          cur_rss_size, kinfo->rss_size,
12296                          cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc);
12297
12298         return ret;
12299 }
12300
12301 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status)
12302 {
12303         struct hclge_set_led_state_cmd *req;
12304         struct hclge_desc desc;
12305         int ret;
12306
12307         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false);
12308
12309         req = (struct hclge_set_led_state_cmd *)desc.data;
12310         hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M,
12311                         HCLGE_LED_LOCATE_STATE_S, locate_led_status);
12312
12313         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
12314         if (ret)
12315                 dev_err(&hdev->pdev->dev,
12316                         "Send set led state cmd error, ret =%d\n", ret);
12317
12318         return ret;
12319 }
12320
12321 enum hclge_led_status {
12322         HCLGE_LED_OFF,
12323         HCLGE_LED_ON,
12324         HCLGE_LED_NO_CHANGE = 0xFF,
12325 };
12326
12327 static int hclge_set_led_id(struct hnae3_handle *handle,
12328                             enum ethtool_phys_id_state status)
12329 {
12330         struct hclge_vport *vport = hclge_get_vport(handle);
12331         struct hclge_dev *hdev = vport->back;
12332
12333         switch (status) {
12334         case ETHTOOL_ID_ACTIVE:
12335                 return hclge_set_led_status(hdev, HCLGE_LED_ON);
12336         case ETHTOOL_ID_INACTIVE:
12337                 return hclge_set_led_status(hdev, HCLGE_LED_OFF);
12338         default:
12339                 return -EINVAL;
12340         }
12341 }
12342
12343 static void hclge_get_link_mode(struct hnae3_handle *handle,
12344                                 unsigned long *supported,
12345                                 unsigned long *advertising)
12346 {
12347         unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS);
12348         struct hclge_vport *vport = hclge_get_vport(handle);
12349         struct hclge_dev *hdev = vport->back;
12350         unsigned int idx = 0;
12351
12352         for (; idx < size; idx++) {
12353                 supported[idx] = hdev->hw.mac.supported[idx];
12354                 advertising[idx] = hdev->hw.mac.advertising[idx];
12355         }
12356 }
12357
12358 static int hclge_gro_en(struct hnae3_handle *handle, bool enable)
12359 {
12360         struct hclge_vport *vport = hclge_get_vport(handle);
12361         struct hclge_dev *hdev = vport->back;
12362         bool gro_en_old = hdev->gro_en;
12363         int ret;
12364
12365         hdev->gro_en = enable;
12366         ret = hclge_config_gro(hdev);
12367         if (ret)
12368                 hdev->gro_en = gro_en_old;
12369
12370         return ret;
12371 }
12372
12373 static int hclge_sync_vport_promisc_mode(struct hclge_vport *vport)
12374 {
12375         struct hnae3_handle *handle = &vport->nic;
12376         struct hclge_dev *hdev = vport->back;
12377         bool uc_en = false;
12378         bool mc_en = false;
12379         u8 tmp_flags;
12380         bool bc_en;
12381         int ret;
12382
12383         if (vport->last_promisc_flags != vport->overflow_promisc_flags) {
12384                 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
12385                 vport->last_promisc_flags = vport->overflow_promisc_flags;
12386         }
12387
12388         if (!test_and_clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE,
12389                                 &vport->state))
12390                 return 0;
12391
12392         /* for PF */
12393         if (!vport->vport_id) {
12394                 tmp_flags = handle->netdev_flags | vport->last_promisc_flags;
12395                 ret = hclge_set_promisc_mode(handle, tmp_flags & HNAE3_UPE,
12396                                              tmp_flags & HNAE3_MPE);
12397                 if (!ret)
12398                         set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE,
12399                                 &vport->state);
12400                 else
12401                         set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE,
12402                                 &vport->state);
12403                 return ret;
12404         }
12405
12406         /* for VF */
12407         if (vport->vf_info.trusted) {
12408                 uc_en = vport->vf_info.request_uc_en > 0 ||
12409                         vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE;
12410                 mc_en = vport->vf_info.request_mc_en > 0 ||
12411                         vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE;
12412         }
12413         bc_en = vport->vf_info.request_bc_en > 0;
12414
12415         ret = hclge_cmd_set_promisc_mode(hdev, vport->vport_id, uc_en,
12416                                          mc_en, bc_en);
12417         if (ret) {
12418                 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
12419                 return ret;
12420         }
12421         hclge_set_vport_vlan_fltr_change(vport);
12422
12423         return 0;
12424 }
12425
12426 static void hclge_sync_promisc_mode(struct hclge_dev *hdev)
12427 {
12428         struct hclge_vport *vport;
12429         int ret;
12430         u16 i;
12431
12432         for (i = 0; i < hdev->num_alloc_vport; i++) {
12433                 vport = &hdev->vport[i];
12434
12435                 ret = hclge_sync_vport_promisc_mode(vport);
12436                 if (ret)
12437                         return;
12438         }
12439 }
12440
12441 static bool hclge_module_existed(struct hclge_dev *hdev)
12442 {
12443         struct hclge_desc desc;
12444         u32 existed;
12445         int ret;
12446
12447         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_EXIST, true);
12448         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
12449         if (ret) {
12450                 dev_err(&hdev->pdev->dev,
12451                         "failed to get SFP exist state, ret = %d\n", ret);
12452                 return false;
12453         }
12454
12455         existed = le32_to_cpu(desc.data[0]);
12456
12457         return existed != 0;
12458 }
12459
12460 /* need 6 bds(total 140 bytes) in one reading
12461  * return the number of bytes actually read, 0 means read failed.
12462  */
12463 static u16 hclge_get_sfp_eeprom_info(struct hclge_dev *hdev, u32 offset,
12464                                      u32 len, u8 *data)
12465 {
12466         struct hclge_desc desc[HCLGE_SFP_INFO_CMD_NUM];
12467         struct hclge_sfp_info_bd0_cmd *sfp_info_bd0;
12468         u16 read_len;
12469         u16 copy_len;
12470         int ret;
12471         int i;
12472
12473         /* setup all 6 bds to read module eeprom info. */
12474         for (i = 0; i < HCLGE_SFP_INFO_CMD_NUM; i++) {
12475                 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_SFP_EEPROM,
12476                                            true);
12477
12478                 /* bd0~bd4 need next flag */
12479                 if (i < HCLGE_SFP_INFO_CMD_NUM - 1)
12480                         desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
12481         }
12482
12483         /* setup bd0, this bd contains offset and read length. */
12484         sfp_info_bd0 = (struct hclge_sfp_info_bd0_cmd *)desc[0].data;
12485         sfp_info_bd0->offset = cpu_to_le16((u16)offset);
12486         read_len = min_t(u16, len, HCLGE_SFP_INFO_MAX_LEN);
12487         sfp_info_bd0->read_len = cpu_to_le16(read_len);
12488
12489         ret = hclge_cmd_send(&hdev->hw, desc, i);
12490         if (ret) {
12491                 dev_err(&hdev->pdev->dev,
12492                         "failed to get SFP eeprom info, ret = %d\n", ret);
12493                 return 0;
12494         }
12495
12496         /* copy sfp info from bd0 to out buffer. */
12497         copy_len = min_t(u16, len, HCLGE_SFP_INFO_BD0_LEN);
12498         memcpy(data, sfp_info_bd0->data, copy_len);
12499         read_len = copy_len;
12500
12501         /* copy sfp info from bd1~bd5 to out buffer if needed. */
12502         for (i = 1; i < HCLGE_SFP_INFO_CMD_NUM; i++) {
12503                 if (read_len >= len)
12504                         return read_len;
12505
12506                 copy_len = min_t(u16, len - read_len, HCLGE_SFP_INFO_BDX_LEN);
12507                 memcpy(data + read_len, desc[i].data, copy_len);
12508                 read_len += copy_len;
12509         }
12510
12511         return read_len;
12512 }
12513
12514 static int hclge_get_module_eeprom(struct hnae3_handle *handle, u32 offset,
12515                                    u32 len, u8 *data)
12516 {
12517         struct hclge_vport *vport = hclge_get_vport(handle);
12518         struct hclge_dev *hdev = vport->back;
12519         u32 read_len = 0;
12520         u16 data_len;
12521
12522         if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER)
12523                 return -EOPNOTSUPP;
12524
12525         if (!hclge_module_existed(hdev))
12526                 return -ENXIO;
12527
12528         while (read_len < len) {
12529                 data_len = hclge_get_sfp_eeprom_info(hdev,
12530                                                      offset + read_len,
12531                                                      len - read_len,
12532                                                      data + read_len);
12533                 if (!data_len)
12534                         return -EIO;
12535
12536                 read_len += data_len;
12537         }
12538
12539         return 0;
12540 }
12541
12542 static int hclge_get_link_diagnosis_info(struct hnae3_handle *handle,
12543                                          u32 *status_code)
12544 {
12545         struct hclge_vport *vport = hclge_get_vport(handle);
12546         struct hclge_dev *hdev = vport->back;
12547         struct hclge_desc desc;
12548         int ret;
12549
12550         if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2)
12551                 return -EOPNOTSUPP;
12552
12553         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_DIAGNOSIS, true);
12554         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
12555         if (ret) {
12556                 dev_err(&hdev->pdev->dev,
12557                         "failed to query link diagnosis info, ret = %d\n", ret);
12558                 return ret;
12559         }
12560
12561         *status_code = le32_to_cpu(desc.data[0]);
12562         return 0;
12563 }
12564
12565 /* After disable sriov, VF still has some config and info need clean,
12566  * which configed by PF.
12567  */
12568 static void hclge_clear_vport_vf_info(struct hclge_vport *vport, int vfid)
12569 {
12570         struct hclge_dev *hdev = vport->back;
12571         struct hclge_vlan_info vlan_info;
12572         int ret;
12573
12574         clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state);
12575         clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
12576         vport->need_notify = 0;
12577         vport->mps = 0;
12578
12579         /* after disable sriov, clean VF rate configured by PF */
12580         ret = hclge_tm_qs_shaper_cfg(vport, 0);
12581         if (ret)
12582                 dev_err(&hdev->pdev->dev,
12583                         "failed to clean vf%d rate config, ret = %d\n",
12584                         vfid, ret);
12585
12586         vlan_info.vlan_tag = 0;
12587         vlan_info.qos = 0;
12588         vlan_info.vlan_proto = ETH_P_8021Q;
12589         ret = hclge_update_port_base_vlan_cfg(vport,
12590                                               HNAE3_PORT_BASE_VLAN_DISABLE,
12591                                               &vlan_info);
12592         if (ret)
12593                 dev_err(&hdev->pdev->dev,
12594                         "failed to clean vf%d port base vlan, ret = %d\n",
12595                         vfid, ret);
12596
12597         ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, false);
12598         if (ret)
12599                 dev_err(&hdev->pdev->dev,
12600                         "failed to clean vf%d spoof config, ret = %d\n",
12601                         vfid, ret);
12602
12603         memset(&vport->vf_info, 0, sizeof(vport->vf_info));
12604 }
12605
12606 static void hclge_clean_vport_config(struct hnae3_ae_dev *ae_dev, int num_vfs)
12607 {
12608         struct hclge_dev *hdev = ae_dev->priv;
12609         struct hclge_vport *vport;
12610         int i;
12611
12612         for (i = 0; i < num_vfs; i++) {
12613                 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM];
12614
12615                 hclge_clear_vport_vf_info(vport, i);
12616         }
12617 }
12618
12619 static int hclge_get_dscp_prio(struct hnae3_handle *h, u8 dscp, u8 *tc_mode,
12620                                u8 *priority)
12621 {
12622         struct hclge_vport *vport = hclge_get_vport(h);
12623
12624         if (dscp >= HNAE3_MAX_DSCP)
12625                 return -EINVAL;
12626
12627         if (tc_mode)
12628                 *tc_mode = vport->nic.kinfo.tc_map_mode;
12629         if (priority)
12630                 *priority = vport->nic.kinfo.dscp_prio[dscp] == HNAE3_PRIO_ID_INVALID ? 0 :
12631                             vport->nic.kinfo.dscp_prio[dscp];
12632
12633         return 0;
12634 }
12635
12636 static const struct hnae3_ae_ops hclge_ops = {
12637         .init_ae_dev = hclge_init_ae_dev,
12638         .uninit_ae_dev = hclge_uninit_ae_dev,
12639         .reset_prepare = hclge_reset_prepare_general,
12640         .reset_done = hclge_reset_done,
12641         .init_client_instance = hclge_init_client_instance,
12642         .uninit_client_instance = hclge_uninit_client_instance,
12643         .map_ring_to_vector = hclge_map_ring_to_vector,
12644         .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
12645         .get_vector = hclge_get_vector,
12646         .put_vector = hclge_put_vector,
12647         .set_promisc_mode = hclge_set_promisc_mode,
12648         .request_update_promisc_mode = hclge_request_update_promisc_mode,
12649         .set_loopback = hclge_set_loopback,
12650         .start = hclge_ae_start,
12651         .stop = hclge_ae_stop,
12652         .client_start = hclge_client_start,
12653         .client_stop = hclge_client_stop,
12654         .get_status = hclge_get_status,
12655         .get_ksettings_an_result = hclge_get_ksettings_an_result,
12656         .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
12657         .get_media_type = hclge_get_media_type,
12658         .check_port_speed = hclge_check_port_speed,
12659         .get_fec_stats = hclge_get_fec_stats,
12660         .get_fec = hclge_get_fec,
12661         .set_fec = hclge_set_fec,
12662         .get_rss_key_size = hclge_comm_get_rss_key_size,
12663         .get_rss = hclge_get_rss,
12664         .set_rss = hclge_set_rss,
12665         .set_rss_tuple = hclge_set_rss_tuple,
12666         .get_rss_tuple = hclge_get_rss_tuple,
12667         .get_tc_size = hclge_get_tc_size,
12668         .get_mac_addr = hclge_get_mac_addr,
12669         .set_mac_addr = hclge_set_mac_addr,
12670         .do_ioctl = hclge_do_ioctl,
12671         .add_uc_addr = hclge_add_uc_addr,
12672         .rm_uc_addr = hclge_rm_uc_addr,
12673         .add_mc_addr = hclge_add_mc_addr,
12674         .rm_mc_addr = hclge_rm_mc_addr,
12675         .set_autoneg = hclge_set_autoneg,
12676         .get_autoneg = hclge_get_autoneg,
12677         .restart_autoneg = hclge_restart_autoneg,
12678         .halt_autoneg = hclge_halt_autoneg,
12679         .get_pauseparam = hclge_get_pauseparam,
12680         .set_pauseparam = hclge_set_pauseparam,
12681         .set_mtu = hclge_set_mtu,
12682         .reset_queue = hclge_reset_tqp,
12683         .get_stats = hclge_get_stats,
12684         .get_mac_stats = hclge_get_mac_stat,
12685         .update_stats = hclge_update_stats,
12686         .get_strings = hclge_get_strings,
12687         .get_sset_count = hclge_get_sset_count,
12688         .get_fw_version = hclge_get_fw_version,
12689         .get_mdix_mode = hclge_get_mdix_mode,
12690         .enable_vlan_filter = hclge_enable_vlan_filter,
12691         .set_vlan_filter = hclge_set_vlan_filter,
12692         .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
12693         .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
12694         .reset_event = hclge_reset_event,
12695         .get_reset_level = hclge_get_reset_level,
12696         .set_default_reset_request = hclge_set_def_reset_request,
12697         .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
12698         .set_channels = hclge_set_channels,
12699         .get_channels = hclge_get_channels,
12700         .get_regs_len = hclge_get_regs_len,
12701         .get_regs = hclge_get_regs,
12702         .set_led_id = hclge_set_led_id,
12703         .get_link_mode = hclge_get_link_mode,
12704         .add_fd_entry = hclge_add_fd_entry,
12705         .del_fd_entry = hclge_del_fd_entry,
12706         .get_fd_rule_cnt = hclge_get_fd_rule_cnt,
12707         .get_fd_rule_info = hclge_get_fd_rule_info,
12708         .get_fd_all_rules = hclge_get_all_rules,
12709         .enable_fd = hclge_enable_fd,
12710         .add_arfs_entry = hclge_add_fd_entry_by_arfs,
12711         .dbg_read_cmd = hclge_dbg_read_cmd,
12712         .handle_hw_ras_error = hclge_handle_hw_ras_error,
12713         .get_hw_reset_stat = hclge_get_hw_reset_stat,
12714         .ae_dev_resetting = hclge_ae_dev_resetting,
12715         .ae_dev_reset_cnt = hclge_ae_dev_reset_cnt,
12716         .set_gro_en = hclge_gro_en,
12717         .get_global_queue_id = hclge_covert_handle_qid_global,
12718         .set_timer_task = hclge_set_timer_task,
12719         .mac_connect_phy = hclge_mac_connect_phy,
12720         .mac_disconnect_phy = hclge_mac_disconnect_phy,
12721         .get_vf_config = hclge_get_vf_config,
12722         .set_vf_link_state = hclge_set_vf_link_state,
12723         .set_vf_spoofchk = hclge_set_vf_spoofchk,
12724         .set_vf_trust = hclge_set_vf_trust,
12725         .set_vf_rate = hclge_set_vf_rate,
12726         .set_vf_mac = hclge_set_vf_mac,
12727         .get_module_eeprom = hclge_get_module_eeprom,
12728         .get_cmdq_stat = hclge_get_cmdq_stat,
12729         .add_cls_flower = hclge_add_cls_flower,
12730         .del_cls_flower = hclge_del_cls_flower,
12731         .cls_flower_active = hclge_is_cls_flower_active,
12732         .get_phy_link_ksettings = hclge_get_phy_link_ksettings,
12733         .set_phy_link_ksettings = hclge_set_phy_link_ksettings,
12734         .set_tx_hwts_info = hclge_ptp_set_tx_info,
12735         .get_rx_hwts = hclge_ptp_get_rx_hwts,
12736         .get_ts_info = hclge_ptp_get_ts_info,
12737         .get_link_diagnosis_info = hclge_get_link_diagnosis_info,
12738         .clean_vf_config = hclge_clean_vport_config,
12739         .get_dscp_prio = hclge_get_dscp_prio,
12740         .get_wol = hclge_get_wol,
12741         .set_wol = hclge_set_wol,
12742 };
12743
12744 static struct hnae3_ae_algo ae_algo = {
12745         .ops = &hclge_ops,
12746         .pdev_id_table = ae_algo_pci_tbl,
12747 };
12748
12749 static int __init hclge_init(void)
12750 {
12751         pr_info("%s is initializing\n", HCLGE_NAME);
12752
12753         hclge_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGE_NAME);
12754         if (!hclge_wq) {
12755                 pr_err("%s: failed to create workqueue\n", HCLGE_NAME);
12756                 return -ENOMEM;
12757         }
12758
12759         hnae3_register_ae_algo(&ae_algo);
12760
12761         return 0;
12762 }
12763
12764 static void __exit hclge_exit(void)
12765 {
12766         hnae3_unregister_ae_algo_prepare(&ae_algo);
12767         hnae3_unregister_ae_algo(&ae_algo);
12768         destroy_workqueue(hclge_wq);
12769 }
12770 module_init(hclge_init);
12771 module_exit(hclge_exit);
12772
12773 MODULE_LICENSE("GPL");
12774 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
12775 MODULE_DESCRIPTION("HCLGE Driver");
12776 MODULE_VERSION(HCLGE_MOD_VERSION);