drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4 #include <linux/acpi.h>
   5 #include <linux/device.h>
   6 #include <linux/etherdevice.h>
   7 #include <linux/init.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/netdevice.h>
  12 #include <linux/pci.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/if_vlan.h>
  15 #include <linux/crash_dump.h>
  16 #include <net/ipv6.h>
  17 #include <net/rtnetlink.h>
  18 #include "hclge_cmd.h"
  19 #include "hclge_dcb.h"
  20 #include "hclge_main.h"
  21 #include "hclge_mbx.h"
  22 #include "hclge_mdio.h"
  23 #include "hclge_tm.h"
  24 #include "hclge_err.h"
  25 #include "hnae3.h"
  26 #include "hclge_devlink.h"
  27 #include "hclge_comm_cmd.h"
  28
  29 #define HCLGE_NAME                      "hclge"
  30
  31 #define HCLGE_BUF_SIZE_UNIT     256U
  32 #define HCLGE_BUF_MUL_BY        2
  33 #define HCLGE_BUF_DIV_BY        2
  34 #define NEED_RESERVE_TC_NUM     2
  35 #define BUF_MAX_PERCENT         100
  36 #define BUF_RESERVE_PERCENT     90
  37
  38 #define HCLGE_RESET_MAX_FAIL_CNT        5
  39 #define HCLGE_RESET_SYNC_TIME           100
  40 #define HCLGE_PF_RESET_SYNC_TIME        20
  41 #define HCLGE_PF_RESET_SYNC_CNT         1500
  42
  43 /* Get DFX BD number offset */
  44 #define HCLGE_DFX_BIOS_BD_OFFSET        1
  45 #define HCLGE_DFX_SSU_0_BD_OFFSET       2
  46 #define HCLGE_DFX_SSU_1_BD_OFFSET       3
  47 #define HCLGE_DFX_IGU_BD_OFFSET         4
  48 #define HCLGE_DFX_RPU_0_BD_OFFSET       5
  49 #define HCLGE_DFX_RPU_1_BD_OFFSET       6
  50 #define HCLGE_DFX_NCSI_BD_OFFSET        7
  51 #define HCLGE_DFX_RTC_BD_OFFSET         8
  52 #define HCLGE_DFX_PPP_BD_OFFSET         9
  53 #define HCLGE_DFX_RCB_BD_OFFSET         10
  54 #define HCLGE_DFX_TQP_BD_OFFSET         11
  55 #define HCLGE_DFX_SSU_2_BD_OFFSET       12
  56
  57 #define HCLGE_LINK_STATUS_MS    10
  58
  59 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps);
  60 static int hclge_init_vlan_config(struct hclge_dev *hdev);
  61 static void hclge_sync_vlan_filter(struct hclge_dev *hdev);
  62 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
  63 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle);
  64 static void hclge_rfs_filter_expire(struct hclge_dev *hdev);
  65 static int hclge_clear_arfs_rules(struct hclge_dev *hdev);
  66 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev,
  67                                                    unsigned long *addr);
  68 static int hclge_set_default_loopback(struct hclge_dev *hdev);
  69
  70 static void hclge_sync_mac_table(struct hclge_dev *hdev);
  71 static void hclge_restore_hw_table(struct hclge_dev *hdev);
  72 static void hclge_sync_promisc_mode(struct hclge_dev *hdev);
  73 static void hclge_sync_fd_table(struct hclge_dev *hdev);
  74
  75 static struct hnae3_ae_algo ae_algo;
  76
  77 static struct workqueue_struct *hclge_wq;
  78
  79 static const struct pci_device_id ae_algo_pci_tbl[] = {
  80         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
  81         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
  82         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
  83         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
  84         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
  85         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
  86         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
  87         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0},
  88         /* required last entry */
  89         {0, }
  90 };
  91
  92 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
  93
  94 static const u32 cmdq_reg_addr_list[] = {HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG,
  95                                          HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG,
  96                                          HCLGE_COMM_NIC_CSQ_DEPTH_REG,
  97                                          HCLGE_COMM_NIC_CSQ_TAIL_REG,
  98                                          HCLGE_COMM_NIC_CSQ_HEAD_REG,
  99                                          HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG,
 100                                          HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG,
 101                                          HCLGE_COMM_NIC_CRQ_DEPTH_REG,
 102                                          HCLGE_COMM_NIC_CRQ_TAIL_REG,
 103                                          HCLGE_COMM_NIC_CRQ_HEAD_REG,
 104                                          HCLGE_COMM_VECTOR0_CMDQ_SRC_REG,
 105                                          HCLGE_COMM_CMDQ_INTR_STS_REG,
 106                                          HCLGE_COMM_CMDQ_INTR_EN_REG,
 107                                          HCLGE_COMM_CMDQ_INTR_GEN_REG};
 108
 109 static const u32 common_reg_addr_list[] = {HCLGE_MISC_VECTOR_REG_BASE,
 110                                            HCLGE_PF_OTHER_INT_REG,
 111                                            HCLGE_MISC_RESET_STS_REG,
 112                                            HCLGE_MISC_VECTOR_INT_STS,
 113                                            HCLGE_GLOBAL_RESET_REG,
 114                                            HCLGE_FUN_RST_ING,
 115                                            HCLGE_GRO_EN_REG};
 116
 117 static const u32 ring_reg_addr_list[] = {HCLGE_RING_RX_ADDR_L_REG,
 118                                          HCLGE_RING_RX_ADDR_H_REG,
 119                                          HCLGE_RING_RX_BD_NUM_REG,
 120                                          HCLGE_RING_RX_BD_LENGTH_REG,
 121                                          HCLGE_RING_RX_MERGE_EN_REG,
 122                                          HCLGE_RING_RX_TAIL_REG,
 123                                          HCLGE_RING_RX_HEAD_REG,
 124                                          HCLGE_RING_RX_FBD_NUM_REG,
 125                                          HCLGE_RING_RX_OFFSET_REG,
 126                                          HCLGE_RING_RX_FBD_OFFSET_REG,
 127                                          HCLGE_RING_RX_STASH_REG,
 128                                          HCLGE_RING_RX_BD_ERR_REG,
 129                                          HCLGE_RING_TX_ADDR_L_REG,
 130                                          HCLGE_RING_TX_ADDR_H_REG,
 131                                          HCLGE_RING_TX_BD_NUM_REG,
 132                                          HCLGE_RING_TX_PRIORITY_REG,
 133                                          HCLGE_RING_TX_TC_REG,
 134                                          HCLGE_RING_TX_MERGE_EN_REG,
 135                                          HCLGE_RING_TX_TAIL_REG,
 136                                          HCLGE_RING_TX_HEAD_REG,
 137                                          HCLGE_RING_TX_FBD_NUM_REG,
 138                                          HCLGE_RING_TX_OFFSET_REG,
 139                                          HCLGE_RING_TX_EBD_NUM_REG,
 140                                          HCLGE_RING_TX_EBD_OFFSET_REG,
 141                                          HCLGE_RING_TX_BD_ERR_REG,
 142                                          HCLGE_RING_EN_REG};
 143
 144 static const u32 tqp_intr_reg_addr_list[] = {HCLGE_TQP_INTR_CTRL_REG,
 145                                              HCLGE_TQP_INTR_GL0_REG,
 146                                              HCLGE_TQP_INTR_GL1_REG,
 147                                              HCLGE_TQP_INTR_GL2_REG,
 148                                              HCLGE_TQP_INTR_RL_REG};
 149
 150 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
 151         "App    Loopback test",
 152         "Serdes serial Loopback test",
 153         "Serdes parallel Loopback test",
 154         "Phy    Loopback test"
 155 };
 156
 157 static const struct hclge_comm_stats_str g_mac_stats_string[] = {
 158         {"mac_tx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 159                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
 160         {"mac_rx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 161                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
 162         {"mac_tx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 163                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pause_xoff_time)},
 164         {"mac_rx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 165                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pause_xoff_time)},
 166         {"mac_tx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 167                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_ctrl_pkt_num)},
 168         {"mac_rx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 169                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_ctrl_pkt_num)},
 170         {"mac_tx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 171                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pause_pkt_num)},
 172         {"mac_tx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 173                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
 174         {"mac_tx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 175                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
 176         {"mac_tx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 177                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
 178         {"mac_tx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 179                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
 180         {"mac_tx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 181                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
 182         {"mac_tx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 183                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
 184         {"mac_tx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 185                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
 186         {"mac_tx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 187                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
 188         {"mac_tx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 189                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_xoff_time)},
 190         {"mac_tx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 191                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_xoff_time)},
 192         {"mac_tx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 193                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_xoff_time)},
 194         {"mac_tx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 195                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_xoff_time)},
 196         {"mac_tx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 197                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_xoff_time)},
 198         {"mac_tx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 199                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_xoff_time)},
 200         {"mac_tx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 201                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_xoff_time)},
 202         {"mac_tx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 203                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_xoff_time)},
 204         {"mac_rx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 205                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pause_pkt_num)},
 206         {"mac_rx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 207                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
 208         {"mac_rx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 209                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
 210         {"mac_rx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 211                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
 212         {"mac_rx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 213                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
 214         {"mac_rx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 215                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
 216         {"mac_rx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 217                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
 218         {"mac_rx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 219                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
 220         {"mac_rx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 221                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
 222         {"mac_rx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 223                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_xoff_time)},
 224         {"mac_rx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 225                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_xoff_time)},
 226         {"mac_rx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 227                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_xoff_time)},
 228         {"mac_rx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 229                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_xoff_time)},
 230         {"mac_rx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 231                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_xoff_time)},
 232         {"mac_rx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 233                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_xoff_time)},
 234         {"mac_rx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 235                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_xoff_time)},
 236         {"mac_rx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
 237                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_xoff_time)},
 238         {"mac_tx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 239                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
 240         {"mac_tx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 241                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
 242         {"mac_tx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 243                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
 244         {"mac_tx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 245                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
 246         {"mac_tx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 247                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
 248         {"mac_tx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 249                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
 250         {"mac_tx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 251                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
 252         {"mac_tx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 253                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
 254         {"mac_tx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 255                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
 256         {"mac_tx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 257                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
 258         {"mac_tx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 259                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
 260         {"mac_tx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 261                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
 262         {"mac_tx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 263                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
 264         {"mac_tx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 265                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
 266         {"mac_tx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 267                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
 268         {"mac_tx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 269                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
 270         {"mac_tx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 271                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
 272         {"mac_tx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 273                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
 274         {"mac_tx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 275                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
 276         {"mac_tx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 277                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
 278         {"mac_tx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 279                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
 280         {"mac_tx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 281                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
 282         {"mac_tx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 283                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
 284         {"mac_tx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 285                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
 286         {"mac_tx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 287                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
 288         {"mac_rx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 289                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
 290         {"mac_rx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 291                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
 292         {"mac_rx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 293                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
 294         {"mac_rx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 295                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
 296         {"mac_rx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 297                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
 298         {"mac_rx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 299                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
 300         {"mac_rx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 301                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
 302         {"mac_rx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 303                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
 304         {"mac_rx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 305                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
 306         {"mac_rx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 307                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
 308         {"mac_rx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 309                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
 310         {"mac_rx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 311                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
 312         {"mac_rx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 313                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
 314         {"mac_rx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 315                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
 316         {"mac_rx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 317                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
 318         {"mac_rx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 319                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
 320         {"mac_rx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 321                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
 322         {"mac_rx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 323                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
 324         {"mac_rx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 325                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
 326         {"mac_rx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 327                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
 328         {"mac_rx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 329                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
 330         {"mac_rx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 331                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
 332         {"mac_rx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 333                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
 334         {"mac_rx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 335                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
 336         {"mac_rx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 337                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
 338
 339         {"mac_tx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 340                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
 341         {"mac_tx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 342                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
 343         {"mac_tx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 344                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
 345         {"mac_tx_err_all_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 346                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
 347         {"mac_tx_from_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 348                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
 349         {"mac_tx_from_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 350                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
 351         {"mac_rx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 352                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
 353         {"mac_rx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 354                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
 355         {"mac_rx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 356                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
 357         {"mac_rx_fcs_err_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 358                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
 359         {"mac_rx_send_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 360                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
 361         {"mac_rx_send_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
 362                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
 363 };
 364
 365 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
 366         {
 367                 .flags = HCLGE_MAC_MGR_MASK_VLAN_B,
 368                 .ethter_type = cpu_to_le16(ETH_P_LLDP),
 369                 .mac_addr = {0x01, 0x80, 0xc2, 0x00, 0x00, 0x0e},
 370                 .i_port_bitmap = 0x1,
 371         },
 372 };
 373
 374 static const u32 hclge_dfx_bd_offset_list[] = {
 375         HCLGE_DFX_BIOS_BD_OFFSET,
 376         HCLGE_DFX_SSU_0_BD_OFFSET,
 377         HCLGE_DFX_SSU_1_BD_OFFSET,
 378         HCLGE_DFX_IGU_BD_OFFSET,
 379         HCLGE_DFX_RPU_0_BD_OFFSET,
 380         HCLGE_DFX_RPU_1_BD_OFFSET,
 381         HCLGE_DFX_NCSI_BD_OFFSET,
 382         HCLGE_DFX_RTC_BD_OFFSET,
 383         HCLGE_DFX_PPP_BD_OFFSET,
 384         HCLGE_DFX_RCB_BD_OFFSET,
 385         HCLGE_DFX_TQP_BD_OFFSET,
 386         HCLGE_DFX_SSU_2_BD_OFFSET
 387 };
 388
 389 static const enum hclge_opcode_type hclge_dfx_reg_opcode_list[] = {
 390         HCLGE_OPC_DFX_BIOS_COMMON_REG,
 391         HCLGE_OPC_DFX_SSU_REG_0,
 392         HCLGE_OPC_DFX_SSU_REG_1,
 393         HCLGE_OPC_DFX_IGU_EGU_REG,
 394         HCLGE_OPC_DFX_RPU_REG_0,
 395         HCLGE_OPC_DFX_RPU_REG_1,
 396         HCLGE_OPC_DFX_NCSI_REG,
 397         HCLGE_OPC_DFX_RTC_REG,
 398         HCLGE_OPC_DFX_PPP_REG,
 399         HCLGE_OPC_DFX_RCB_REG,
 400         HCLGE_OPC_DFX_TQP_REG,
 401         HCLGE_OPC_DFX_SSU_REG_2
 402 };
 403
 404 static const struct key_info meta_data_key_info[] = {
 405         { PACKET_TYPE_ID, 6 },
 406         { IP_FRAGEMENT, 1 },
 407         { ROCE_TYPE, 1 },
 408         { NEXT_KEY, 5 },
 409         { VLAN_NUMBER, 2 },
 410         { SRC_VPORT, 12 },
 411         { DST_VPORT, 12 },
 412         { TUNNEL_PACKET, 1 },
 413 };
 414
 415 static const struct key_info tuple_key_info[] = {
 416         { OUTER_DST_MAC, 48, KEY_OPT_MAC, -1, -1 },
 417         { OUTER_SRC_MAC, 48, KEY_OPT_MAC, -1, -1 },
 418         { OUTER_VLAN_TAG_FST, 16, KEY_OPT_LE16, -1, -1 },
 419         { OUTER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 },
 420         { OUTER_ETH_TYPE, 16, KEY_OPT_LE16, -1, -1 },
 421         { OUTER_L2_RSV, 16, KEY_OPT_LE16, -1, -1 },
 422         { OUTER_IP_TOS, 8, KEY_OPT_U8, -1, -1 },
 423         { OUTER_IP_PROTO, 8, KEY_OPT_U8, -1, -1 },
 424         { OUTER_SRC_IP, 32, KEY_OPT_IP, -1, -1 },
 425         { OUTER_DST_IP, 32, KEY_OPT_IP, -1, -1 },
 426         { OUTER_L3_RSV, 16, KEY_OPT_LE16, -1, -1 },
 427         { OUTER_SRC_PORT, 16, KEY_OPT_LE16, -1, -1 },
 428         { OUTER_DST_PORT, 16, KEY_OPT_LE16, -1, -1 },
 429         { OUTER_L4_RSV, 32, KEY_OPT_LE32, -1, -1 },
 430         { OUTER_TUN_VNI, 24, KEY_OPT_VNI, -1, -1 },
 431         { OUTER_TUN_FLOW_ID, 8, KEY_OPT_U8, -1, -1 },
 432         { INNER_DST_MAC, 48, KEY_OPT_MAC,
 433           offsetof(struct hclge_fd_rule, tuples.dst_mac),
 434           offsetof(struct hclge_fd_rule, tuples_mask.dst_mac) },
 435         { INNER_SRC_MAC, 48, KEY_OPT_MAC,
 436           offsetof(struct hclge_fd_rule, tuples.src_mac),
 437           offsetof(struct hclge_fd_rule, tuples_mask.src_mac) },
 438         { INNER_VLAN_TAG_FST, 16, KEY_OPT_LE16,
 439           offsetof(struct hclge_fd_rule, tuples.vlan_tag1),
 440           offsetof(struct hclge_fd_rule, tuples_mask.vlan_tag1) },
 441         { INNER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 },
 442         { INNER_ETH_TYPE, 16, KEY_OPT_LE16,
 443           offsetof(struct hclge_fd_rule, tuples.ether_proto),
 444           offsetof(struct hclge_fd_rule, tuples_mask.ether_proto) },
 445         { INNER_L2_RSV, 16, KEY_OPT_LE16,
 446           offsetof(struct hclge_fd_rule, tuples.l2_user_def),
 447           offsetof(struct hclge_fd_rule, tuples_mask.l2_user_def) },
 448         { INNER_IP_TOS, 8, KEY_OPT_U8,
 449           offsetof(struct hclge_fd_rule, tuples.ip_tos),
 450           offsetof(struct hclge_fd_rule, tuples_mask.ip_tos) },
 451         { INNER_IP_PROTO, 8, KEY_OPT_U8,
 452           offsetof(struct hclge_fd_rule, tuples.ip_proto),
 453           offsetof(struct hclge_fd_rule, tuples_mask.ip_proto) },
 454         { INNER_SRC_IP, 32, KEY_OPT_IP,
 455           offsetof(struct hclge_fd_rule, tuples.src_ip),
 456           offsetof(struct hclge_fd_rule, tuples_mask.src_ip) },
 457         { INNER_DST_IP, 32, KEY_OPT_IP,
 458           offsetof(struct hclge_fd_rule, tuples.dst_ip),
 459           offsetof(struct hclge_fd_rule, tuples_mask.dst_ip) },
 460         { INNER_L3_RSV, 16, KEY_OPT_LE16,
 461           offsetof(struct hclge_fd_rule, tuples.l3_user_def),
 462           offsetof(struct hclge_fd_rule, tuples_mask.l3_user_def) },
 463         { INNER_SRC_PORT, 16, KEY_OPT_LE16,
 464           offsetof(struct hclge_fd_rule, tuples.src_port),
 465           offsetof(struct hclge_fd_rule, tuples_mask.src_port) },
 466         { INNER_DST_PORT, 16, KEY_OPT_LE16,
 467           offsetof(struct hclge_fd_rule, tuples.dst_port),
 468           offsetof(struct hclge_fd_rule, tuples_mask.dst_port) },
 469         { INNER_L4_RSV, 32, KEY_OPT_LE32,
 470           offsetof(struct hclge_fd_rule, tuples.l4_user_def),
 471           offsetof(struct hclge_fd_rule, tuples_mask.l4_user_def) },
 472 };
 473
 474 /**
 475  * hclge_cmd_send - send command to command queue
 476  * @hw: pointer to the hw struct
 477  * @desc: prefilled descriptor for describing the command
 478  * @num : the number of descriptors to be sent
 479  *
 480  * This is the main send command for command queue, it
 481  * sends the queue, cleans the queue, etc
 482  **/
 483 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num)
 484 {
 485         return hclge_comm_cmd_send(&hw->hw, desc, num);
 486 }
 487
 488 static int hclge_mac_update_stats_defective(struct hclge_dev *hdev)
 489 {
 490 #define HCLGE_MAC_CMD_NUM 21
 491
 492         u64 *data = (u64 *)(&hdev->mac_stats);
 493         struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
 494         __le64 *desc_data;
 495         u32 data_size;
 496         int ret;
 497         u32 i;
 498
 499         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
 500         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
 501         if (ret) {
 502                 dev_err(&hdev->pdev->dev,
 503                         "Get MAC pkt stats fail, status = %d.\n", ret);
 504
 505                 return ret;
 506         }
 507
 508         /* The first desc has a 64-bit header, so data size need to minus 1 */
 509         data_size = sizeof(desc) / (sizeof(u64)) - 1;
 510
 511         desc_data = (__le64 *)(&desc[0].data[0]);
 512         for (i = 0; i < data_size; i++) {
 513                 /* data memory is continuous becase only the first desc has a
 514                  * header in this command
 515                  */
 516                 *data += le64_to_cpu(*desc_data);
 517                 data++;
 518                 desc_data++;
 519         }
 520
 521         return 0;
 522 }
 523
 524 static int hclge_mac_update_stats_complete(struct hclge_dev *hdev)
 525 {
 526 #define HCLGE_REG_NUM_PER_DESC          4
 527
 528         u32 reg_num = hdev->ae_dev->dev_specs.mac_stats_num;
 529         u64 *data = (u64 *)(&hdev->mac_stats);
 530         struct hclge_desc *desc;
 531         __le64 *desc_data;
 532         u32 data_size;
 533         u32 desc_num;
 534         int ret;
 535         u32 i;
 536
 537         /* The first desc has a 64-bit header, so need to consider it */
 538         desc_num = reg_num / HCLGE_REG_NUM_PER_DESC + 1;
 539
 540         /* This may be called inside atomic sections,
 541          * so GFP_ATOMIC is more suitalbe here
 542          */
 543         desc = kcalloc(desc_num, sizeof(struct hclge_desc), GFP_ATOMIC);
 544         if (!desc)
 545                 return -ENOMEM;
 546
 547         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC_ALL, true);
 548         ret = hclge_cmd_send(&hdev->hw, desc, desc_num);
 549         if (ret) {
 550                 kfree(desc);
 551                 return ret;
 552         }
 553
 554         data_size = min_t(u32, sizeof(hdev->mac_stats) / sizeof(u64), reg_num);
 555
 556         desc_data = (__le64 *)(&desc[0].data[0]);
 557         for (i = 0; i < data_size; i++) {
 558                 /* data memory is continuous becase only the first desc has a
 559                  * header in this command
 560                  */
 561                 *data += le64_to_cpu(*desc_data);
 562                 data++;
 563                 desc_data++;
 564         }
 565
 566         kfree(desc);
 567
 568         return 0;
 569 }
 570
 571 static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *reg_num)
 572 {
 573         struct hclge_desc desc;
 574         int ret;
 575
 576         /* Driver needs total register number of both valid registers and
 577          * reserved registers, but the old firmware only returns number
 578          * of valid registers in device V2. To be compatible with these
 579          * devices, driver uses a fixed value.
 580          */
 581         if (hdev->ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) {
 582                 *reg_num = HCLGE_MAC_STATS_MAX_NUM_V1;
 583                 return 0;
 584         }
 585
 586         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_REG_NUM, true);
 587         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 588         if (ret) {
 589                 dev_err(&hdev->pdev->dev,
 590                         "failed to query mac statistic reg number, ret = %d\n",
 591                         ret);
 592                 return ret;
 593         }
 594
 595         *reg_num = le32_to_cpu(desc.data[0]);
 596         if (*reg_num == 0) {
 597                 dev_err(&hdev->pdev->dev,
 598                         "mac statistic reg number is invalid!\n");
 599                 return -ENODATA;
 600         }
 601
 602         return 0;
 603 }
 604
 605 int hclge_mac_update_stats(struct hclge_dev *hdev)
 606 {
 607         /* The firmware supports the new statistics acquisition method */
 608         if (hdev->ae_dev->dev_specs.mac_stats_num)
 609                 return hclge_mac_update_stats_complete(hdev);
 610         else
 611                 return hclge_mac_update_stats_defective(hdev);
 612 }
 613
 614 static int hclge_comm_get_count(struct hclge_dev *hdev,
 615                                 const struct hclge_comm_stats_str strs[],
 616                                 u32 size)
 617 {
 618         int count = 0;
 619         u32 i;
 620
 621         for (i = 0; i < size; i++)
 622                 if (strs[i].stats_num <= hdev->ae_dev->dev_specs.mac_stats_num)
 623                         count++;
 624
 625         return count;
 626 }
 627
 628 static u64 *hclge_comm_get_stats(struct hclge_dev *hdev,
 629                                  const struct hclge_comm_stats_str strs[],
 630                                  int size, u64 *data)
 631 {
 632         u64 *buf = data;
 633         u32 i;
 634
 635         for (i = 0; i < size; i++) {
 636                 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num)
 637                         continue;
 638
 639                 *buf = HCLGE_STATS_READ(&hdev->mac_stats, strs[i].offset);
 640                 buf++;
 641         }
 642
 643         return buf;
 644 }
 645
 646 static u8 *hclge_comm_get_strings(struct hclge_dev *hdev, u32 stringset,
 647                                   const struct hclge_comm_stats_str strs[],
 648                                   int size, u8 *data)
 649 {
 650         char *buff = (char *)data;
 651         u32 i;
 652
 653         if (stringset != ETH_SS_STATS)
 654                 return buff;
 655
 656         for (i = 0; i < size; i++) {
 657                 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num)
 658                         continue;
 659
 660                 snprintf(buff, ETH_GSTRING_LEN, "%s", strs[i].desc);
 661                 buff = buff + ETH_GSTRING_LEN;
 662         }
 663
 664         return (u8 *)buff;
 665 }
 666
 667 static void hclge_update_stats_for_all(struct hclge_dev *hdev)
 668 {
 669         struct hnae3_handle *handle;
 670         int status;
 671
 672         handle = &hdev->vport[0].nic;
 673         if (handle->client) {
 674                 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw);
 675                 if (status) {
 676                         dev_err(&hdev->pdev->dev,
 677                                 "Update TQPS stats fail, status = %d.\n",
 678                                 status);
 679                 }
 680         }
 681
 682         status = hclge_mac_update_stats(hdev);
 683         if (status)
 684                 dev_err(&hdev->pdev->dev,
 685                         "Update MAC stats fail, status = %d.\n", status);
 686 }
 687
 688 static void hclge_update_stats(struct hnae3_handle *handle,
 689                                struct net_device_stats *net_stats)
 690 {
 691         struct hclge_vport *vport = hclge_get_vport(handle);
 692         struct hclge_dev *hdev = vport->back;
 693         int status;
 694
 695         if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
 696                 return;
 697
 698         status = hclge_mac_update_stats(hdev);
 699         if (status)
 700                 dev_err(&hdev->pdev->dev,
 701                         "Update MAC stats fail, status = %d.\n",
 702                         status);
 703
 704         status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw);
 705         if (status)
 706                 dev_err(&hdev->pdev->dev,
 707                         "Update TQPS stats fail, status = %d.\n",
 708                         status);
 709
 710         clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
 711 }
 712
 713 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
 714 {
 715 #define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK | \
 716                 HNAE3_SUPPORT_PHY_LOOPBACK | \
 717                 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK | \
 718                 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK)
 719
 720         struct hclge_vport *vport = hclge_get_vport(handle);
 721         struct hclge_dev *hdev = vport->back;
 722         int count = 0;
 723
 724         /* Loopback test support rules:
 725          * mac: only GE mode support
 726          * serdes: all mac mode will support include GE/XGE/LGE/CGE
 727          * phy: only support when phy device exist on board
 728          */
 729         if (stringset == ETH_SS_TEST) {
 730                 /* clear loopback bit flags at first */
 731                 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
 732                 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 ||
 733                     hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
 734                     hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
 735                     hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
 736                         count += 1;
 737                         handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK;
 738                 }
 739
 740                 count += 2;
 741                 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK;
 742                 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK;
 743
 744                 if ((hdev->hw.mac.phydev && hdev->hw.mac.phydev->drv &&
 745                      hdev->hw.mac.phydev->drv->set_loopback) ||
 746                     hnae3_dev_phy_imp_supported(hdev)) {
 747                         count += 1;
 748                         handle->flags |= HNAE3_SUPPORT_PHY_LOOPBACK;
 749                 }
 750         } else if (stringset == ETH_SS_STATS) {
 751                 count = hclge_comm_get_count(hdev, g_mac_stats_string,
 752                                              ARRAY_SIZE(g_mac_stats_string)) +
 753                         hclge_comm_tqps_get_sset_count(handle);
 754         }
 755
 756         return count;
 757 }
 758
 759 static void hclge_get_strings(struct hnae3_handle *handle, u32 stringset,
 760                               u8 *data)
 761 {
 762         struct hclge_vport *vport = hclge_get_vport(handle);
 763         struct hclge_dev *hdev = vport->back;
 764         u8 *p = (char *)data;
 765         int size;
 766
 767         if (stringset == ETH_SS_STATS) {
 768                 size = ARRAY_SIZE(g_mac_stats_string);
 769                 p = hclge_comm_get_strings(hdev, stringset, g_mac_stats_string,
 770                                            size, p);
 771                 p = hclge_comm_tqps_get_strings(handle, p);
 772         } else if (stringset == ETH_SS_TEST) {
 773                 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) {
 774                         memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_APP],
 775                                ETH_GSTRING_LEN);
 776                         p += ETH_GSTRING_LEN;
 777                 }
 778                 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) {
 779                         memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES],
 780                                ETH_GSTRING_LEN);
 781                         p += ETH_GSTRING_LEN;
 782                 }
 783                 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) {
 784                         memcpy(p,
 785                                hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES],
 786                                ETH_GSTRING_LEN);
 787                         p += ETH_GSTRING_LEN;
 788                 }
 789                 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
 790                         memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_PHY],
 791                                ETH_GSTRING_LEN);
 792                         p += ETH_GSTRING_LEN;
 793                 }
 794         }
 795 }
 796
 797 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
 798 {
 799         struct hclge_vport *vport = hclge_get_vport(handle);
 800         struct hclge_dev *hdev = vport->back;
 801         u64 *p;
 802
 803         p = hclge_comm_get_stats(hdev, g_mac_stats_string,
 804                                  ARRAY_SIZE(g_mac_stats_string), data);
 805         p = hclge_comm_tqps_get_stats(handle, p);
 806 }
 807
 808 static void hclge_get_mac_stat(struct hnae3_handle *handle,
 809                                struct hns3_mac_stats *mac_stats)
 810 {
 811         struct hclge_vport *vport = hclge_get_vport(handle);
 812         struct hclge_dev *hdev = vport->back;
 813
 814         hclge_update_stats(handle, NULL);
 815
 816         mac_stats->tx_pause_cnt = hdev->mac_stats.mac_tx_mac_pause_num;
 817         mac_stats->rx_pause_cnt = hdev->mac_stats.mac_rx_mac_pause_num;
 818 }
 819
 820 static int hclge_parse_func_status(struct hclge_dev *hdev,
 821                                    struct hclge_func_status_cmd *status)
 822 {
 823 #define HCLGE_MAC_ID_MASK       0xF
 824
 825         if (!(status->pf_state & HCLGE_PF_STATE_DONE))
 826                 return -EINVAL;
 827
 828         /* Set the pf to main pf */
 829         if (status->pf_state & HCLGE_PF_STATE_MAIN)
 830                 hdev->flag |= HCLGE_FLAG_MAIN;
 831         else
 832                 hdev->flag &= ~HCLGE_FLAG_MAIN;
 833
 834         hdev->hw.mac.mac_id = status->mac_id & HCLGE_MAC_ID_MASK;
 835         return 0;
 836 }
 837
 838 static int hclge_query_function_status(struct hclge_dev *hdev)
 839 {
 840 #define HCLGE_QUERY_MAX_CNT     5
 841
 842         struct hclge_func_status_cmd *req;
 843         struct hclge_desc desc;
 844         int timeout = 0;
 845         int ret;
 846
 847         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
 848         req = (struct hclge_func_status_cmd *)desc.data;
 849
 850         do {
 851                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 852                 if (ret) {
 853                         dev_err(&hdev->pdev->dev,
 854                                 "query function status failed %d.\n", ret);
 855                         return ret;
 856                 }
 857
 858                 /* Check pf reset is done */
 859                 if (req->pf_state)
 860                         break;
 861                 usleep_range(1000, 2000);
 862         } while (timeout++ < HCLGE_QUERY_MAX_CNT);
 863
 864         return hclge_parse_func_status(hdev, req);
 865 }
 866
 867 static int hclge_query_pf_resource(struct hclge_dev *hdev)
 868 {
 869         struct hclge_pf_res_cmd *req;
 870         struct hclge_desc desc;
 871         int ret;
 872
 873         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
 874         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 875         if (ret) {
 876                 dev_err(&hdev->pdev->dev,
 877                         "query pf resource failed %d.\n", ret);
 878                 return ret;
 879         }
 880
 881         req = (struct hclge_pf_res_cmd *)desc.data;
 882         hdev->num_tqps = le16_to_cpu(req->tqp_num) +
 883                          le16_to_cpu(req->ext_tqp_num);
 884         hdev->pkt_buf_size = le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
 885
 886         if (req->tx_buf_size)
 887                 hdev->tx_buf_size =
 888                         le16_to_cpu(req->tx_buf_size) << HCLGE_BUF_UNIT_S;
 889         else
 890                 hdev->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
 891
 892         hdev->tx_buf_size = roundup(hdev->tx_buf_size, HCLGE_BUF_SIZE_UNIT);
 893
 894         if (req->dv_buf_size)
 895                 hdev->dv_buf_size =
 896                         le16_to_cpu(req->dv_buf_size) << HCLGE_BUF_UNIT_S;
 897         else
 898                 hdev->dv_buf_size = HCLGE_DEFAULT_DV;
 899
 900         hdev->dv_buf_size = roundup(hdev->dv_buf_size, HCLGE_BUF_SIZE_UNIT);
 901
 902         hdev->num_nic_msi = le16_to_cpu(req->msixcap_localid_number_nic);
 903         if (hdev->num_nic_msi < HNAE3_MIN_VECTOR_NUM) {
 904                 dev_err(&hdev->pdev->dev,
 905                         "only %u msi resources available, not enough for pf(min:2).\n",
 906                         hdev->num_nic_msi);
 907                 return -EINVAL;
 908         }
 909
 910         if (hnae3_dev_roce_supported(hdev)) {
 911                 hdev->num_roce_msi =
 912                         le16_to_cpu(req->pf_intr_vector_number_roce);
 913
 914                 /* PF should have NIC vectors and Roce vectors,
 915                  * NIC vectors are queued before Roce vectors.
 916                  */
 917                 hdev->num_msi = hdev->num_nic_msi + hdev->num_roce_msi;
 918         } else {
 919                 hdev->num_msi = hdev->num_nic_msi;
 920         }
 921
 922         return 0;
 923 }
 924
 925 static int hclge_parse_speed(u8 speed_cmd, u32 *speed)
 926 {
 927         switch (speed_cmd) {
 928         case HCLGE_FW_MAC_SPEED_10M:
 929                 *speed = HCLGE_MAC_SPEED_10M;
 930                 break;
 931         case HCLGE_FW_MAC_SPEED_100M:
 932                 *speed = HCLGE_MAC_SPEED_100M;
 933                 break;
 934         case HCLGE_FW_MAC_SPEED_1G:
 935                 *speed = HCLGE_MAC_SPEED_1G;
 936                 break;
 937         case HCLGE_FW_MAC_SPEED_10G:
 938                 *speed = HCLGE_MAC_SPEED_10G;
 939                 break;
 940         case HCLGE_FW_MAC_SPEED_25G:
 941                 *speed = HCLGE_MAC_SPEED_25G;
 942                 break;
 943         case HCLGE_FW_MAC_SPEED_40G:
 944                 *speed = HCLGE_MAC_SPEED_40G;
 945                 break;
 946         case HCLGE_FW_MAC_SPEED_50G:
 947                 *speed = HCLGE_MAC_SPEED_50G;
 948                 break;
 949         case HCLGE_FW_MAC_SPEED_100G:
 950                 *speed = HCLGE_MAC_SPEED_100G;
 951                 break;
 952         case HCLGE_FW_MAC_SPEED_200G:
 953                 *speed = HCLGE_MAC_SPEED_200G;
 954                 break;
 955         default:
 956                 return -EINVAL;
 957         }
 958
 959         return 0;
 960 }
 961
 962 static const struct hclge_speed_bit_map speed_bit_map[] = {
 963         {HCLGE_MAC_SPEED_10M, HCLGE_SUPPORT_10M_BIT},
 964         {HCLGE_MAC_SPEED_100M, HCLGE_SUPPORT_100M_BIT},
 965         {HCLGE_MAC_SPEED_1G, HCLGE_SUPPORT_1G_BIT},
 966         {HCLGE_MAC_SPEED_10G, HCLGE_SUPPORT_10G_BIT},
 967         {HCLGE_MAC_SPEED_25G, HCLGE_SUPPORT_25G_BIT},
 968         {HCLGE_MAC_SPEED_40G, HCLGE_SUPPORT_40G_BIT},
 969         {HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BIT},
 970         {HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BIT},
 971         {HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BIT},
 972 };
 973
 974 static int hclge_get_speed_bit(u32 speed, u32 *speed_bit)
 975 {
 976         u16 i;
 977
 978         for (i = 0; i < ARRAY_SIZE(speed_bit_map); i++) {
 979                 if (speed == speed_bit_map[i].speed) {
 980                         *speed_bit = speed_bit_map[i].speed_bit;
 981                         return 0;
 982                 }
 983         }
 984
 985         return -EINVAL;
 986 }
 987
 988 static int hclge_check_port_speed(struct hnae3_handle *handle, u32 speed)
 989 {
 990         struct hclge_vport *vport = hclge_get_vport(handle);
 991         struct hclge_dev *hdev = vport->back;
 992         u32 speed_ability = hdev->hw.mac.speed_ability;
 993         u32 speed_bit = 0;
 994         int ret;
 995
 996         ret = hclge_get_speed_bit(speed, &speed_bit);
 997         if (ret)
 998                 return ret;
 999
1000         if (speed_bit & speed_ability)
1001                 return 0;
1002
1003         return -EINVAL;
1004 }
1005
1006 static void hclge_convert_setting_sr(u16 speed_ability,
1007                                      unsigned long *link_mode)
1008 {
1009         if (speed_ability & HCLGE_SUPPORT_10G_BIT)
1010                 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
1011                                  link_mode);
1012         if (speed_ability & HCLGE_SUPPORT_25G_BIT)
1013                 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
1014                                  link_mode);
1015         if (speed_ability & HCLGE_SUPPORT_40G_BIT)
1016                 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
1017                                  link_mode);
1018         if (speed_ability & HCLGE_SUPPORT_50G_BIT)
1019                 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
1020                                  link_mode);
1021         if (speed_ability & HCLGE_SUPPORT_100G_BIT)
1022                 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
1023                                  link_mode);
1024         if (speed_ability & HCLGE_SUPPORT_200G_BIT)
1025                 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
1026                                  link_mode);
1027 }
1028
1029 static void hclge_convert_setting_lr(u16 speed_ability,
1030                                      unsigned long *link_mode)
1031 {
1032         if (speed_ability & HCLGE_SUPPORT_10G_BIT)
1033                 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
1034                                  link_mode);
1035         if (speed_ability & HCLGE_SUPPORT_25G_BIT)
1036                 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
1037                                  link_mode);
1038         if (speed_ability & HCLGE_SUPPORT_50G_BIT)
1039                 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
1040                                  link_mode);
1041         if (speed_ability & HCLGE_SUPPORT_40G_BIT)
1042                 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
1043                                  link_mode);
1044         if (speed_ability & HCLGE_SUPPORT_100G_BIT)
1045                 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
1046                                  link_mode);
1047         if (speed_ability & HCLGE_SUPPORT_200G_BIT)
1048                 linkmode_set_bit(
1049                         ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
1050                         link_mode);
1051 }
1052
1053 static void hclge_convert_setting_cr(u16 speed_ability,
1054                                      unsigned long *link_mode)
1055 {
1056         if (speed_ability & HCLGE_SUPPORT_10G_BIT)
1057                 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
1058                                  link_mode);
1059         if (speed_ability & HCLGE_SUPPORT_25G_BIT)
1060                 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
1061                                  link_mode);
1062         if (speed_ability & HCLGE_SUPPORT_40G_BIT)
1063                 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
1064                                  link_mode);
1065         if (speed_ability & HCLGE_SUPPORT_50G_BIT)
1066                 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
1067                                  link_mode);
1068         if (speed_ability & HCLGE_SUPPORT_100G_BIT)
1069                 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
1070                                  link_mode);
1071         if (speed_ability & HCLGE_SUPPORT_200G_BIT)
1072                 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT,
1073                                  link_mode);
1074 }
1075
1076 static void hclge_convert_setting_kr(u16 speed_ability,
1077                                      unsigned long *link_mode)
1078 {
1079         if (speed_ability & HCLGE_SUPPORT_1G_BIT)
1080                 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
1081                                  link_mode);
1082         if (speed_ability & HCLGE_SUPPORT_10G_BIT)
1083                 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
1084                                  link_mode);
1085         if (speed_ability & HCLGE_SUPPORT_25G_BIT)
1086                 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
1087                                  link_mode);
1088         if (speed_ability & HCLGE_SUPPORT_40G_BIT)
1089                 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
1090                                  link_mode);
1091         if (speed_ability & HCLGE_SUPPORT_50G_BIT)
1092                 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
1093                                  link_mode);
1094         if (speed_ability & HCLGE_SUPPORT_100G_BIT)
1095                 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
1096                                  link_mode);
1097         if (speed_ability & HCLGE_SUPPORT_200G_BIT)
1098                 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
1099                                  link_mode);
1100 }
1101
1102 static void hclge_convert_setting_fec(struct hclge_mac *mac)
1103 {
1104         linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, mac->supported);
1105         linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mac->supported);
1106
1107         switch (mac->speed) {
1108         case HCLGE_MAC_SPEED_10G:
1109         case HCLGE_MAC_SPEED_40G:
1110                 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
1111                                  mac->supported);
1112                 mac->fec_ability =
1113                         BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_AUTO);
1114                 break;
1115         case HCLGE_MAC_SPEED_25G:
1116         case HCLGE_MAC_SPEED_50G:
1117                 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
1118                                  mac->supported);
1119                 mac->fec_ability =
1120                         BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_RS) |
1121                         BIT(HNAE3_FEC_AUTO);
1122                 break;
1123         case HCLGE_MAC_SPEED_100G:
1124         case HCLGE_MAC_SPEED_200G:
1125                 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mac->supported);
1126                 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO);
1127                 break;
1128         default:
1129                 mac->fec_ability = 0;
1130                 break;
1131         }
1132 }
1133
1134 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
1135                                         u16 speed_ability)
1136 {
1137         struct hclge_mac *mac = &hdev->hw.mac;
1138
1139         if (speed_ability & HCLGE_SUPPORT_1G_BIT)
1140                 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
1141                                  mac->supported);
1142
1143         hclge_convert_setting_sr(speed_ability, mac->supported);
1144         hclge_convert_setting_lr(speed_ability, mac->supported);
1145         hclge_convert_setting_cr(speed_ability, mac->supported);
1146         if (hnae3_dev_fec_supported(hdev))
1147                 hclge_convert_setting_fec(mac);
1148
1149         if (hnae3_dev_pause_supported(hdev))
1150                 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported);
1151
1152         linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mac->supported);
1153         linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported);
1154 }
1155
1156 static void hclge_parse_backplane_link_mode(struct hclge_dev *hdev,
1157                                             u16 speed_ability)
1158 {
1159         struct hclge_mac *mac = &hdev->hw.mac;
1160
1161         hclge_convert_setting_kr(speed_ability, mac->supported);
1162         if (hnae3_dev_fec_supported(hdev))
1163                 hclge_convert_setting_fec(mac);
1164
1165         if (hnae3_dev_pause_supported(hdev))
1166                 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported);
1167
1168         linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mac->supported);
1169         linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported);
1170 }
1171
1172 static void hclge_parse_copper_link_mode(struct hclge_dev *hdev,
1173                                          u16 speed_ability)
1174 {
1175         unsigned long *supported = hdev->hw.mac.supported;
1176
1177         /* default to support all speed for GE port */
1178         if (!speed_ability)
1179                 speed_ability = HCLGE_SUPPORT_GE;
1180
1181         if (speed_ability & HCLGE_SUPPORT_1G_BIT)
1182                 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1183                                  supported);
1184
1185         if (speed_ability & HCLGE_SUPPORT_100M_BIT) {
1186                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
1187                                  supported);
1188                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
1189                                  supported);
1190         }
1191
1192         if (speed_ability & HCLGE_SUPPORT_10M_BIT) {
1193                 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, supported);
1194                 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, supported);
1195         }
1196
1197         if (hnae3_dev_pause_supported(hdev)) {
1198                 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
1199                 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported);
1200         }
1201
1202         linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported);
1203         linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported);
1204 }
1205
1206 static void hclge_parse_link_mode(struct hclge_dev *hdev, u16 speed_ability)
1207 {
1208         u8 media_type = hdev->hw.mac.media_type;
1209
1210         if (media_type == HNAE3_MEDIA_TYPE_FIBER)
1211                 hclge_parse_fiber_link_mode(hdev, speed_ability);
1212         else if (media_type == HNAE3_MEDIA_TYPE_COPPER)
1213                 hclge_parse_copper_link_mode(hdev, speed_ability);
1214         else if (media_type == HNAE3_MEDIA_TYPE_BACKPLANE)
1215                 hclge_parse_backplane_link_mode(hdev, speed_ability);
1216 }
1217
1218 static u32 hclge_get_max_speed(u16 speed_ability)
1219 {
1220         if (speed_ability & HCLGE_SUPPORT_200G_BIT)
1221                 return HCLGE_MAC_SPEED_200G;
1222
1223         if (speed_ability & HCLGE_SUPPORT_100G_BIT)
1224                 return HCLGE_MAC_SPEED_100G;
1225
1226         if (speed_ability & HCLGE_SUPPORT_50G_BIT)
1227                 return HCLGE_MAC_SPEED_50G;
1228
1229         if (speed_ability & HCLGE_SUPPORT_40G_BIT)
1230                 return HCLGE_MAC_SPEED_40G;
1231
1232         if (speed_ability & HCLGE_SUPPORT_25G_BIT)
1233                 return HCLGE_MAC_SPEED_25G;
1234
1235         if (speed_ability & HCLGE_SUPPORT_10G_BIT)
1236                 return HCLGE_MAC_SPEED_10G;
1237
1238         if (speed_ability & HCLGE_SUPPORT_1G_BIT)
1239                 return HCLGE_MAC_SPEED_1G;
1240
1241         if (speed_ability & HCLGE_SUPPORT_100M_BIT)
1242                 return HCLGE_MAC_SPEED_100M;
1243
1244         if (speed_ability & HCLGE_SUPPORT_10M_BIT)
1245                 return HCLGE_MAC_SPEED_10M;
1246
1247         return HCLGE_MAC_SPEED_1G;
1248 }
1249
1250 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
1251 {
1252 #define HCLGE_TX_SPARE_SIZE_UNIT                4096
1253 #define SPEED_ABILITY_EXT_SHIFT                 8
1254
1255         struct hclge_cfg_param_cmd *req;
1256         u64 mac_addr_tmp_high;
1257         u16 speed_ability_ext;
1258         u64 mac_addr_tmp;
1259         unsigned int i;
1260
1261         req = (struct hclge_cfg_param_cmd *)desc[0].data;
1262
1263         /* get the configuration */
1264         cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1265                                       HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
1266         cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1267                                             HCLGE_CFG_TQP_DESC_N_M,
1268                                             HCLGE_CFG_TQP_DESC_N_S);
1269
1270         cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]),
1271                                         HCLGE_CFG_PHY_ADDR_M,
1272                                         HCLGE_CFG_PHY_ADDR_S);
1273         cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]),
1274                                           HCLGE_CFG_MEDIA_TP_M,
1275                                           HCLGE_CFG_MEDIA_TP_S);
1276         cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]),
1277                                           HCLGE_CFG_RX_BUF_LEN_M,
1278                                           HCLGE_CFG_RX_BUF_LEN_S);
1279         /* get mac_address */
1280         mac_addr_tmp = __le32_to_cpu(req->param[2]);
1281         mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]),
1282                                             HCLGE_CFG_MAC_ADDR_H_M,
1283                                             HCLGE_CFG_MAC_ADDR_H_S);
1284
1285         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
1286
1287         cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]),
1288                                              HCLGE_CFG_DEFAULT_SPEED_M,
1289                                              HCLGE_CFG_DEFAULT_SPEED_S);
1290         cfg->vf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]),
1291                                                HCLGE_CFG_RSS_SIZE_M,
1292                                                HCLGE_CFG_RSS_SIZE_S);
1293
1294         for (i = 0; i < ETH_ALEN; i++)
1295                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
1296
1297         req = (struct hclge_cfg_param_cmd *)desc[1].data;
1298         cfg->numa_node_map = __le32_to_cpu(req->param[0]);
1299
1300         cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]),
1301                                              HCLGE_CFG_SPEED_ABILITY_M,
1302                                              HCLGE_CFG_SPEED_ABILITY_S);
1303         speed_ability_ext = hnae3_get_field(__le32_to_cpu(req->param[1]),
1304                                             HCLGE_CFG_SPEED_ABILITY_EXT_M,
1305                                             HCLGE_CFG_SPEED_ABILITY_EXT_S);
1306         cfg->speed_ability |= speed_ability_ext << SPEED_ABILITY_EXT_SHIFT;
1307
1308         cfg->vlan_fliter_cap = hnae3_get_field(__le32_to_cpu(req->param[1]),
1309                                                HCLGE_CFG_VLAN_FLTR_CAP_M,
1310                                                HCLGE_CFG_VLAN_FLTR_CAP_S);
1311
1312         cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]),
1313                                          HCLGE_CFG_UMV_TBL_SPACE_M,
1314                                          HCLGE_CFG_UMV_TBL_SPACE_S);
1315
1316         cfg->pf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[2]),
1317                                                HCLGE_CFG_PF_RSS_SIZE_M,
1318                                                HCLGE_CFG_PF_RSS_SIZE_S);
1319
1320         /* HCLGE_CFG_PF_RSS_SIZE_M is the PF max rss size, which is a
1321          * power of 2, instead of reading out directly. This would
1322          * be more flexible for future changes and expansions.
1323          * When VF max  rss size field is HCLGE_CFG_RSS_SIZE_S,
1324          * it does not make sense if PF's field is 0. In this case, PF and VF
1325          * has the same max rss size filed: HCLGE_CFG_RSS_SIZE_S.
1326          */
1327         cfg->pf_rss_size_max = cfg->pf_rss_size_max ?
1328                                1U << cfg->pf_rss_size_max :
1329                                cfg->vf_rss_size_max;
1330
1331         /* The unit of the tx spare buffer size queried from configuration
1332          * file is HCLGE_TX_SPARE_SIZE_UNIT(4096) bytes, so a conversion is
1333          * needed here.
1334          */
1335         cfg->tx_spare_buf_size = hnae3_get_field(__le32_to_cpu(req->param[2]),
1336                                                  HCLGE_CFG_TX_SPARE_BUF_SIZE_M,
1337                                                  HCLGE_CFG_TX_SPARE_BUF_SIZE_S);
1338         cfg->tx_spare_buf_size *= HCLGE_TX_SPARE_SIZE_UNIT;
1339 }
1340
1341 /* hclge_get_cfg: query the static parameter from flash
1342  * @hdev: pointer to struct hclge_dev
1343  * @hcfg: the config structure to be getted
1344  */
1345 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
1346 {
1347         struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
1348         struct hclge_cfg_param_cmd *req;
1349         unsigned int i;
1350         int ret;
1351
1352         for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
1353                 u32 offset = 0;
1354
1355                 req = (struct hclge_cfg_param_cmd *)desc[i].data;
1356                 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
1357                                            true);
1358                 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M,
1359                                 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
1360                 /* Len should be united by 4 bytes when send to hardware */
1361                 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
1362                                 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
1363                 req->offset = cpu_to_le32(offset);
1364         }
1365
1366         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1367         if (ret) {
1368                 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret);
1369                 return ret;
1370         }
1371
1372         hclge_parse_cfg(hcfg, desc);
1373
1374         return 0;
1375 }
1376
1377 static void hclge_set_default_dev_specs(struct hclge_dev *hdev)
1378 {
1379 #define HCLGE_MAX_NON_TSO_BD_NUM                        8U
1380
1381         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
1382
1383         ae_dev->dev_specs.max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM;
1384         ae_dev->dev_specs.rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE;
1385         ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE;
1386         ae_dev->dev_specs.max_tm_rate = HCLGE_ETHER_MAX_RATE;
1387         ae_dev->dev_specs.max_int_gl = HCLGE_DEF_MAX_INT_GL;
1388         ae_dev->dev_specs.max_frm_size = HCLGE_MAC_MAX_FRAME;
1389         ae_dev->dev_specs.max_qset_num = HCLGE_MAX_QSET_NUM;
1390         ae_dev->dev_specs.umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF;
1391 }
1392
1393 static void hclge_parse_dev_specs(struct hclge_dev *hdev,
1394                                   struct hclge_desc *desc)
1395 {
1396         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
1397         struct hclge_dev_specs_0_cmd *req0;
1398         struct hclge_dev_specs_1_cmd *req1;
1399
1400         req0 = (struct hclge_dev_specs_0_cmd *)desc[0].data;
1401         req1 = (struct hclge_dev_specs_1_cmd *)desc[1].data;
1402
1403         ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num;
1404         ae_dev->dev_specs.rss_ind_tbl_size =
1405                 le16_to_cpu(req0->rss_ind_tbl_size);
1406         ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max);
1407         ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size);
1408         ae_dev->dev_specs.max_tm_rate = le32_to_cpu(req0->max_tm_rate);
1409         ae_dev->dev_specs.max_qset_num = le16_to_cpu(req1->max_qset_num);
1410         ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl);
1411         ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size);
1412         ae_dev->dev_specs.umv_size = le16_to_cpu(req1->umv_size);
1413         ae_dev->dev_specs.mc_mac_size = le16_to_cpu(req1->mc_mac_size);
1414 }
1415
1416 static void hclge_check_dev_specs(struct hclge_dev *hdev)
1417 {
1418         struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs;
1419
1420         if (!dev_specs->max_non_tso_bd_num)
1421                 dev_specs->max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM;
1422         if (!dev_specs->rss_ind_tbl_size)
1423                 dev_specs->rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE;
1424         if (!dev_specs->rss_key_size)
1425                 dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE;
1426         if (!dev_specs->max_tm_rate)
1427                 dev_specs->max_tm_rate = HCLGE_ETHER_MAX_RATE;
1428         if (!dev_specs->max_qset_num)
1429                 dev_specs->max_qset_num = HCLGE_MAX_QSET_NUM;
1430         if (!dev_specs->max_int_gl)
1431                 dev_specs->max_int_gl = HCLGE_DEF_MAX_INT_GL;
1432         if (!dev_specs->max_frm_size)
1433                 dev_specs->max_frm_size = HCLGE_MAC_MAX_FRAME;
1434         if (!dev_specs->umv_size)
1435                 dev_specs->umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF;
1436 }
1437
1438 static int hclge_query_mac_stats_num(struct hclge_dev *hdev)
1439 {
1440         u32 reg_num = 0;
1441         int ret;
1442
1443         ret = hclge_mac_query_reg_num(hdev, &reg_num);
1444         if (ret && ret != -EOPNOTSUPP)
1445                 return ret;
1446
1447         hdev->ae_dev->dev_specs.mac_stats_num = reg_num;
1448         return 0;
1449 }
1450
1451 static int hclge_query_dev_specs(struct hclge_dev *hdev)
1452 {
1453         struct hclge_desc desc[HCLGE_QUERY_DEV_SPECS_BD_NUM];
1454         int ret;
1455         int i;
1456
1457         ret = hclge_query_mac_stats_num(hdev);
1458         if (ret)
1459                 return ret;
1460
1461         /* set default specifications as devices lower than version V3 do not
1462          * support querying specifications from firmware.
1463          */
1464         if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) {
1465                 hclge_set_default_dev_specs(hdev);
1466                 return 0;
1467         }
1468
1469         for (i = 0; i < HCLGE_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1470                 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS,
1471                                            true);
1472                 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
1473         }
1474         hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true);
1475
1476         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_QUERY_DEV_SPECS_BD_NUM);
1477         if (ret)
1478                 return ret;
1479
1480         hclge_parse_dev_specs(hdev, desc);
1481         hclge_check_dev_specs(hdev);
1482
1483         return 0;
1484 }
1485
1486 static int hclge_get_cap(struct hclge_dev *hdev)
1487 {
1488         int ret;
1489
1490         ret = hclge_query_function_status(hdev);
1491         if (ret) {
1492                 dev_err(&hdev->pdev->dev,
1493                         "query function status error %d.\n", ret);
1494                 return ret;
1495         }
1496
1497         /* get pf resource */
1498         return hclge_query_pf_resource(hdev);
1499 }
1500
1501 static void hclge_init_kdump_kernel_config(struct hclge_dev *hdev)
1502 {
1503 #define HCLGE_MIN_TX_DESC       64
1504 #define HCLGE_MIN_RX_DESC       64
1505
1506         if (!is_kdump_kernel())
1507                 return;
1508
1509         dev_info(&hdev->pdev->dev,
1510                  "Running kdump kernel. Using minimal resources\n");
1511
1512         /* minimal queue pairs equals to the number of vports */
1513         hdev->num_tqps = hdev->num_req_vfs + 1;
1514         hdev->num_tx_desc = HCLGE_MIN_TX_DESC;
1515         hdev->num_rx_desc = HCLGE_MIN_RX_DESC;
1516 }
1517
1518 static void hclge_init_tc_config(struct hclge_dev *hdev)
1519 {
1520         unsigned int i;
1521
1522         if (hdev->tc_max > HNAE3_MAX_TC ||
1523             hdev->tc_max < 1) {
1524                 dev_warn(&hdev->pdev->dev, "TC num = %u.\n",
1525                          hdev->tc_max);
1526                 hdev->tc_max = 1;
1527         }
1528
1529         /* Dev does not support DCB */
1530         if (!hnae3_dev_dcb_supported(hdev)) {
1531                 hdev->tc_max = 1;
1532                 hdev->pfc_max = 0;
1533         } else {
1534                 hdev->pfc_max = hdev->tc_max;
1535         }
1536
1537         hdev->tm_info.num_tc = 1;
1538
1539         /* Currently not support uncontiuous tc */
1540         for (i = 0; i < hdev->tm_info.num_tc; i++)
1541                 hnae3_set_bit(hdev->hw_tc_map, i, 1);
1542
1543         hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
1544 }
1545
1546 static int hclge_configure(struct hclge_dev *hdev)
1547 {
1548         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
1549         struct hclge_cfg cfg;
1550         int ret;
1551
1552         ret = hclge_get_cfg(hdev, &cfg);
1553         if (ret)
1554                 return ret;
1555
1556         hdev->base_tqp_pid = 0;
1557         hdev->vf_rss_size_max = cfg.vf_rss_size_max;
1558         hdev->pf_rss_size_max = cfg.pf_rss_size_max;
1559         hdev->rx_buf_len = cfg.rx_buf_len;
1560         ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
1561         hdev->hw.mac.media_type = cfg.media_type;
1562         hdev->hw.mac.phy_addr = cfg.phy_addr;
1563         hdev->num_tx_desc = cfg.tqp_desc_num;
1564         hdev->num_rx_desc = cfg.tqp_desc_num;
1565         hdev->tm_info.num_pg = 1;
1566         hdev->tc_max = cfg.tc_num;
1567         hdev->tm_info.hw_pfc_map = 0;
1568         if (cfg.umv_space)
1569                 hdev->wanted_umv_size = cfg.umv_space;
1570         else
1571                 hdev->wanted_umv_size = hdev->ae_dev->dev_specs.umv_size;
1572         hdev->tx_spare_buf_size = cfg.tx_spare_buf_size;
1573         hdev->gro_en = true;
1574         if (cfg.vlan_fliter_cap == HCLGE_VLAN_FLTR_CAN_MDF)
1575                 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps);
1576
1577         if (hnae3_dev_fd_supported(hdev)) {
1578                 hdev->fd_en = true;
1579                 hdev->fd_active_type = HCLGE_FD_RULE_NONE;
1580         }
1581
1582         ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1583         if (ret) {
1584                 dev_err(&hdev->pdev->dev, "failed to parse speed %u, ret = %d\n",
1585                         cfg.default_speed, ret);
1586                 return ret;
1587         }
1588
1589         hclge_parse_link_mode(hdev, cfg.speed_ability);
1590
1591         hdev->hw.mac.max_speed = hclge_get_max_speed(cfg.speed_ability);
1592
1593         hclge_init_tc_config(hdev);
1594         hclge_init_kdump_kernel_config(hdev);
1595
1596         return ret;
1597 }
1598
1599 static int hclge_config_tso(struct hclge_dev *hdev, u16 tso_mss_min,
1600                             u16 tso_mss_max)
1601 {
1602         struct hclge_cfg_tso_status_cmd *req;
1603         struct hclge_desc desc;
1604
1605         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1606
1607         req = (struct hclge_cfg_tso_status_cmd *)desc.data;
1608         req->tso_mss_min = cpu_to_le16(tso_mss_min);
1609         req->tso_mss_max = cpu_to_le16(tso_mss_max);
1610
1611         return hclge_cmd_send(&hdev->hw, &desc, 1);
1612 }
1613
1614 static int hclge_config_gro(struct hclge_dev *hdev)
1615 {
1616         struct hclge_cfg_gro_status_cmd *req;
1617         struct hclge_desc desc;
1618         int ret;
1619
1620         if (!hnae3_dev_gro_supported(hdev))
1621                 return 0;
1622
1623         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, false);
1624         req = (struct hclge_cfg_gro_status_cmd *)desc.data;
1625
1626         req->gro_en = hdev->gro_en ? 1 : 0;
1627
1628         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1629         if (ret)
1630                 dev_err(&hdev->pdev->dev,
1631                         "GRO hardware config cmd failed, ret = %d\n", ret);
1632
1633         return ret;
1634 }
1635
1636 static int hclge_alloc_tqps(struct hclge_dev *hdev)
1637 {
1638         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
1639         struct hclge_comm_tqp *tqp;
1640         int i;
1641
1642         hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1643                                   sizeof(struct hclge_comm_tqp), GFP_KERNEL);
1644         if (!hdev->htqp)
1645                 return -ENOMEM;
1646
1647         tqp = hdev->htqp;
1648
1649         for (i = 0; i < hdev->num_tqps; i++) {
1650                 tqp->dev = &hdev->pdev->dev;
1651                 tqp->index = i;
1652
1653                 tqp->q.ae_algo = &ae_algo;
1654                 tqp->q.buf_size = hdev->rx_buf_len;
1655                 tqp->q.tx_desc_num = hdev->num_tx_desc;
1656                 tqp->q.rx_desc_num = hdev->num_rx_desc;
1657
1658                 /* need an extended offset to configure queues >=
1659                  * HCLGE_TQP_MAX_SIZE_DEV_V2
1660                  */
1661                 if (i < HCLGE_TQP_MAX_SIZE_DEV_V2)
1662                         tqp->q.io_base = hdev->hw.hw.io_base +
1663                                          HCLGE_TQP_REG_OFFSET +
1664                                          i * HCLGE_TQP_REG_SIZE;
1665                 else
1666                         tqp->q.io_base = hdev->hw.hw.io_base +
1667                                          HCLGE_TQP_REG_OFFSET +
1668                                          HCLGE_TQP_EXT_REG_OFFSET +
1669                                          (i - HCLGE_TQP_MAX_SIZE_DEV_V2) *
1670                                          HCLGE_TQP_REG_SIZE;
1671
1672                 /* when device supports tx push and has device memory,
1673                  * the queue can execute push mode or doorbell mode on
1674                  * device memory.
1675                  */
1676                 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps))
1677                         tqp->q.mem_base = hdev->hw.hw.mem_base +
1678                                           HCLGE_TQP_MEM_OFFSET(hdev, i);
1679
1680                 tqp++;
1681         }
1682
1683         return 0;
1684 }
1685
1686 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1687                                   u16 tqp_pid, u16 tqp_vid, bool is_pf)
1688 {
1689         struct hclge_tqp_map_cmd *req;
1690         struct hclge_desc desc;
1691         int ret;
1692
1693         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1694
1695         req = (struct hclge_tqp_map_cmd *)desc.data;
1696         req->tqp_id = cpu_to_le16(tqp_pid);
1697         req->tqp_vf = func_id;
1698         req->tqp_flag = 1U << HCLGE_TQP_MAP_EN_B;
1699         if (!is_pf)
1700                 req->tqp_flag |= 1U << HCLGE_TQP_MAP_TYPE_B;
1701         req->tqp_vid = cpu_to_le16(tqp_vid);
1702
1703         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1704         if (ret)
1705                 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret);
1706
1707         return ret;
1708 }
1709
1710 static int  hclge_assign_tqp(struct hclge_vport *vport, u16 num_tqps)
1711 {
1712         struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
1713         struct hclge_dev *hdev = vport->back;
1714         int i, alloced;
1715
1716         for (i = 0, alloced = 0; i < hdev->num_tqps &&
1717              alloced < num_tqps; i++) {
1718                 if (!hdev->htqp[i].alloced) {
1719                         hdev->htqp[i].q.handle = &vport->nic;
1720                         hdev->htqp[i].q.tqp_index = alloced;
1721                         hdev->htqp[i].q.tx_desc_num = kinfo->num_tx_desc;
1722                         hdev->htqp[i].q.rx_desc_num = kinfo->num_rx_desc;
1723                         kinfo->tqp[alloced] = &hdev->htqp[i].q;
1724                         hdev->htqp[i].alloced = true;
1725                         alloced++;
1726                 }
1727         }
1728         vport->alloc_tqps = alloced;
1729         kinfo->rss_size = min_t(u16, hdev->pf_rss_size_max,
1730                                 vport->alloc_tqps / hdev->tm_info.num_tc);
1731
1732         /* ensure one to one mapping between irq and queue at default */
1733         kinfo->rss_size = min_t(u16, kinfo->rss_size,
1734                                 (hdev->num_nic_msi - 1) / hdev->tm_info.num_tc);
1735
1736         return 0;
1737 }
1738
1739 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps,
1740                             u16 num_tx_desc, u16 num_rx_desc)
1741
1742 {
1743         struct hnae3_handle *nic = &vport->nic;
1744         struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1745         struct hclge_dev *hdev = vport->back;
1746         int ret;
1747
1748         kinfo->num_tx_desc = num_tx_desc;
1749         kinfo->num_rx_desc = num_rx_desc;
1750
1751         kinfo->rx_buf_len = hdev->rx_buf_len;
1752         kinfo->tx_spare_buf_size = hdev->tx_spare_buf_size;
1753
1754         kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, num_tqps,
1755                                   sizeof(struct hnae3_queue *), GFP_KERNEL);
1756         if (!kinfo->tqp)
1757                 return -ENOMEM;
1758
1759         ret = hclge_assign_tqp(vport, num_tqps);
1760         if (ret)
1761                 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1762
1763         return ret;
1764 }
1765
1766 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1767                                   struct hclge_vport *vport)
1768 {
1769         struct hnae3_handle *nic = &vport->nic;
1770         struct hnae3_knic_private_info *kinfo;
1771         u16 i;
1772
1773         kinfo = &nic->kinfo;
1774         for (i = 0; i < vport->alloc_tqps; i++) {
1775                 struct hclge_comm_tqp *q =
1776                         container_of(kinfo->tqp[i], struct hclge_comm_tqp, q);
1777                 bool is_pf;
1778                 int ret;
1779
1780                 is_pf = !(vport->vport_id);
1781                 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1782                                              i, is_pf);
1783                 if (ret)
1784                         return ret;
1785         }
1786
1787         return 0;
1788 }
1789
1790 static int hclge_map_tqp(struct hclge_dev *hdev)
1791 {
1792         struct hclge_vport *vport = hdev->vport;
1793         u16 i, num_vport;
1794
1795         num_vport = hdev->num_req_vfs + 1;
1796         for (i = 0; i < num_vport; i++) {
1797                 int ret;
1798
1799                 ret = hclge_map_tqp_to_vport(hdev, vport);
1800                 if (ret)
1801                         return ret;
1802
1803                 vport++;
1804         }
1805
1806         return 0;
1807 }
1808
1809 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1810 {
1811         struct hnae3_handle *nic = &vport->nic;
1812         struct hclge_dev *hdev = vport->back;
1813         int ret;
1814
1815         nic->pdev = hdev->pdev;
1816         nic->ae_algo = &ae_algo;
1817         nic->numa_node_mask = hdev->numa_node_mask;
1818         nic->kinfo.io_base = hdev->hw.hw.io_base;
1819
1820         ret = hclge_knic_setup(vport, num_tqps,
1821                                hdev->num_tx_desc, hdev->num_rx_desc);
1822         if (ret)
1823                 dev_err(&hdev->pdev->dev, "knic setup failed %d\n", ret);
1824
1825         return ret;
1826 }
1827
1828 static int hclge_alloc_vport(struct hclge_dev *hdev)
1829 {
1830         struct pci_dev *pdev = hdev->pdev;
1831         struct hclge_vport *vport;
1832         u32 tqp_main_vport;
1833         u32 tqp_per_vport;
1834         int num_vport, i;
1835         int ret;
1836
1837         /* We need to alloc a vport for main NIC of PF */
1838         num_vport = hdev->num_req_vfs + 1;
1839
1840         if (hdev->num_tqps < num_vport) {
1841                 dev_err(&hdev->pdev->dev, "tqps(%u) is less than vports(%d)",
1842                         hdev->num_tqps, num_vport);
1843                 return -EINVAL;
1844         }
1845
1846         /* Alloc the same number of TQPs for every vport */
1847         tqp_per_vport = hdev->num_tqps / num_vport;
1848         tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1849
1850         vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1851                              GFP_KERNEL);
1852         if (!vport)
1853                 return -ENOMEM;
1854
1855         hdev->vport = vport;
1856         hdev->num_alloc_vport = num_vport;
1857
1858         if (IS_ENABLED(CONFIG_PCI_IOV))
1859                 hdev->num_alloc_vfs = hdev->num_req_vfs;
1860
1861         for (i = 0; i < num_vport; i++) {
1862                 vport->back = hdev;
1863                 vport->vport_id = i;
1864                 vport->vf_info.link_state = IFLA_VF_LINK_STATE_AUTO;
1865                 vport->mps = HCLGE_MAC_DEFAULT_FRAME;
1866                 vport->port_base_vlan_cfg.state = HNAE3_PORT_BASE_VLAN_DISABLE;
1867                 vport->port_base_vlan_cfg.tbl_sta = true;
1868                 vport->rxvlan_cfg.rx_vlan_offload_en = true;
1869                 vport->req_vlan_fltr_en = true;
1870                 INIT_LIST_HEAD(&vport->vlan_list);
1871                 INIT_LIST_HEAD(&vport->uc_mac_list);
1872                 INIT_LIST_HEAD(&vport->mc_mac_list);
1873                 spin_lock_init(&vport->mac_list_lock);
1874
1875                 if (i == 0)
1876                         ret = hclge_vport_setup(vport, tqp_main_vport);
1877                 else
1878                         ret = hclge_vport_setup(vport, tqp_per_vport);
1879                 if (ret) {
1880                         dev_err(&pdev->dev,
1881                                 "vport setup failed for vport %d, %d\n",
1882                                 i, ret);
1883                         return ret;
1884                 }
1885
1886                 vport++;
1887         }
1888
1889         return 0;
1890 }
1891
1892 static int  hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1893                                     struct hclge_pkt_buf_alloc *buf_alloc)
1894 {
1895 /* TX buffer size is unit by 128 byte */
1896 #define HCLGE_BUF_SIZE_UNIT_SHIFT       7
1897 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK    BIT(15)
1898         struct hclge_tx_buff_alloc_cmd *req;
1899         struct hclge_desc desc;
1900         int ret;
1901         u8 i;
1902
1903         req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
1904
1905         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
1906         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1907                 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
1908
1909                 req->tx_pkt_buff[i] =
1910                         cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1911                                      HCLGE_BUF_SIZE_UPDATE_EN_MSK);
1912         }
1913
1914         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1915         if (ret)
1916                 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1917                         ret);
1918
1919         return ret;
1920 }
1921
1922 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1923                                  struct hclge_pkt_buf_alloc *buf_alloc)
1924 {
1925         int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
1926
1927         if (ret)
1928                 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret);
1929
1930         return ret;
1931 }
1932
1933 static u32 hclge_get_tc_num(struct hclge_dev *hdev)
1934 {
1935         unsigned int i;
1936         u32 cnt = 0;
1937
1938         for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1939                 if (hdev->hw_tc_map & BIT(i))
1940                         cnt++;
1941         return cnt;
1942 }
1943
1944 /* Get the number of pfc enabled TCs, which have private buffer */
1945 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1946                                   struct hclge_pkt_buf_alloc *buf_alloc)
1947 {
1948         struct hclge_priv_buf *priv;
1949         unsigned int i;
1950         int cnt = 0;
1951
1952         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1953                 priv = &buf_alloc->priv_buf[i];
1954                 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1955                     priv->enable)
1956                         cnt++;
1957         }
1958
1959         return cnt;
1960 }
1961
1962 /* Get the number of pfc disabled TCs, which have private buffer */
1963 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1964                                      struct hclge_pkt_buf_alloc *buf_alloc)
1965 {
1966         struct hclge_priv_buf *priv;
1967         unsigned int i;
1968         int cnt = 0;
1969
1970         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1971                 priv = &buf_alloc->priv_buf[i];
1972                 if (hdev->hw_tc_map & BIT(i) &&
1973                     !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1974                     priv->enable)
1975                         cnt++;
1976         }
1977
1978         return cnt;
1979 }
1980
1981 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1982 {
1983         struct hclge_priv_buf *priv;
1984         u32 rx_priv = 0;
1985         int i;
1986
1987         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1988                 priv = &buf_alloc->priv_buf[i];
1989                 if (priv->enable)
1990                         rx_priv += priv->buf_size;
1991         }
1992         return rx_priv;
1993 }
1994
1995 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1996 {
1997         u32 i, total_tx_size = 0;
1998
1999         for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
2000                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
2001
2002         return total_tx_size;
2003 }
2004
2005 static bool  hclge_is_rx_buf_ok(struct hclge_dev *hdev,
2006                                 struct hclge_pkt_buf_alloc *buf_alloc,
2007                                 u32 rx_all)
2008 {
2009         u32 shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
2010         u32 tc_num = hclge_get_tc_num(hdev);
2011         u32 shared_buf, aligned_mps;
2012         u32 rx_priv;
2013         int i;
2014
2015         aligned_mps = roundup(hdev->mps, HCLGE_BUF_SIZE_UNIT);
2016
2017         if (hnae3_dev_dcb_supported(hdev))
2018                 shared_buf_min = HCLGE_BUF_MUL_BY * aligned_mps +
2019                                         hdev->dv_buf_size;
2020         else
2021                 shared_buf_min = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF
2022                                         + hdev->dv_buf_size;
2023
2024         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
2025         shared_std = roundup(max_t(u32, shared_buf_min, shared_buf_tc),
2026                              HCLGE_BUF_SIZE_UNIT);
2027
2028         rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
2029         if (rx_all < rx_priv + shared_std)
2030                 return false;
2031
2032         shared_buf = rounddown(rx_all - rx_priv, HCLGE_BUF_SIZE_UNIT);
2033         buf_alloc->s_buf.buf_size = shared_buf;
2034         if (hnae3_dev_dcb_supported(hdev)) {
2035                 buf_alloc->s_buf.self.high = shared_buf - hdev->dv_buf_size;
2036                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
2037                         - roundup(aligned_mps / HCLGE_BUF_DIV_BY,
2038                                   HCLGE_BUF_SIZE_UNIT);
2039         } else {
2040                 buf_alloc->s_buf.self.high = aligned_mps +
2041                                                 HCLGE_NON_DCB_ADDITIONAL_BUF;
2042                 buf_alloc->s_buf.self.low = aligned_mps;
2043         }
2044
2045         if (hnae3_dev_dcb_supported(hdev)) {
2046                 hi_thrd = shared_buf - hdev->dv_buf_size;
2047
2048                 if (tc_num <= NEED_RESERVE_TC_NUM)
2049                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
2050                                         / BUF_MAX_PERCENT;
2051
2052                 if (tc_num)
2053                         hi_thrd = hi_thrd / tc_num;
2054
2055                 hi_thrd = max_t(u32, hi_thrd, HCLGE_BUF_MUL_BY * aligned_mps);
2056                 hi_thrd = rounddown(hi_thrd, HCLGE_BUF_SIZE_UNIT);
2057                 lo_thrd = hi_thrd - aligned_mps / HCLGE_BUF_DIV_BY;
2058         } else {
2059                 hi_thrd = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF;
2060                 lo_thrd = aligned_mps;
2061         }
2062
2063         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2064                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
2065                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
2066         }
2067
2068         return true;
2069 }
2070
2071 static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
2072                                 struct hclge_pkt_buf_alloc *buf_alloc)
2073 {
2074         u32 i, total_size;
2075
2076         total_size = hdev->pkt_buf_size;
2077
2078         /* alloc tx buffer for all enabled tc */
2079         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2080                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
2081
2082                 if (hdev->hw_tc_map & BIT(i)) {
2083                         if (total_size < hdev->tx_buf_size)
2084                                 return -ENOMEM;
2085
2086                         priv->tx_buf_size = hdev->tx_buf_size;
2087                 } else {
2088                         priv->tx_buf_size = 0;
2089                 }
2090
2091                 total_size -= priv->tx_buf_size;
2092         }
2093
2094         return 0;
2095 }
2096
2097 static bool hclge_rx_buf_calc_all(struct hclge_dev *hdev, bool max,
2098                                   struct hclge_pkt_buf_alloc *buf_alloc)
2099 {
2100         u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc);
2101         u32 aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT);
2102         unsigned int i;
2103
2104         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2105                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
2106
2107                 priv->enable = 0;
2108                 priv->wl.low = 0;
2109                 priv->wl.high = 0;
2110                 priv->buf_size = 0;
2111
2112                 if (!(hdev->hw_tc_map & BIT(i)))
2113                         continue;
2114
2115                 priv->enable = 1;
2116
2117                 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
2118                         priv->wl.low = max ? aligned_mps : HCLGE_BUF_SIZE_UNIT;
2119                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
2120                                                 HCLGE_BUF_SIZE_UNIT);
2121                 } else {
2122                         priv->wl.low = 0;
2123                         priv->wl.high = max ? (aligned_mps * HCLGE_BUF_MUL_BY) :
2124                                         aligned_mps;
2125                 }
2126
2127                 priv->buf_size = priv->wl.high + hdev->dv_buf_size;
2128         }
2129
2130         return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all);
2131 }
2132
2133 static bool hclge_drop_nopfc_buf_till_fit(struct hclge_dev *hdev,
2134                                           struct hclge_pkt_buf_alloc *buf_alloc)
2135 {
2136         u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc);
2137         int no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
2138         int i;
2139
2140         /* let the last to be cleared first */
2141         for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
2142                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
2143                 unsigned int mask = BIT((unsigned int)i);
2144
2145                 if (hdev->hw_tc_map & mask &&
2146                     !(hdev->tm_info.hw_pfc_map & mask)) {
2147                         /* Clear the no pfc TC private buffer */
2148                         priv->wl.low = 0;
2149                         priv->wl.high = 0;
2150                         priv->buf_size = 0;
2151                         priv->enable = 0;
2152                         no_pfc_priv_num--;
2153                 }
2154
2155                 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
2156                     no_pfc_priv_num == 0)
2157                         break;
2158         }
2159
2160         return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all);
2161 }
2162
2163 static bool hclge_drop_pfc_buf_till_fit(struct hclge_dev *hdev,
2164                                         struct hclge_pkt_buf_alloc *buf_alloc)
2165 {
2166         u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc);
2167         int pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
2168         int i;
2169
2170         /* let the last to be cleared first */
2171         for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
2172                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
2173                 unsigned int mask = BIT((unsigned int)i);
2174
2175                 if (hdev->hw_tc_map & mask &&
2176                     hdev->tm_info.hw_pfc_map & mask) {
2177                         /* Reduce the number of pfc TC with private buffer */
2178                         priv->wl.low = 0;
2179                         priv->enable = 0;
2180                         priv->wl.high = 0;
2181                         priv->buf_size = 0;
2182                         pfc_priv_num--;
2183                 }
2184
2185                 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
2186                     pfc_priv_num == 0)
2187                         break;
2188         }
2189
2190         return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all);
2191 }
2192
2193 static int hclge_only_alloc_priv_buff(struct hclge_dev *hdev,
2194                                       struct hclge_pkt_buf_alloc *buf_alloc)
2195 {
2196 #define COMPENSATE_BUFFER       0x3C00
2197 #define COMPENSATE_HALF_MPS_NUM 5
2198 #define PRIV_WL_GAP             0x1800
2199
2200         u32 rx_priv = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc);
2201         u32 tc_num = hclge_get_tc_num(hdev);
2202         u32 half_mps = hdev->mps >> 1;
2203         u32 min_rx_priv;
2204         unsigned int i;
2205
2206         if (tc_num)
2207                 rx_priv = rx_priv / tc_num;
2208
2209         if (tc_num <= NEED_RESERVE_TC_NUM)
2210                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
2211
2212         min_rx_priv = hdev->dv_buf_size + COMPENSATE_BUFFER +
2213                         COMPENSATE_HALF_MPS_NUM * half_mps;
2214         min_rx_priv = round_up(min_rx_priv, HCLGE_BUF_SIZE_UNIT);
2215         rx_priv = round_down(rx_priv, HCLGE_BUF_SIZE_UNIT);
2216         if (rx_priv < min_rx_priv)
2217                 return false;
2218
2219         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2220                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
2221
2222                 priv->enable = 0;
2223                 priv->wl.low = 0;
2224                 priv->wl.high = 0;
2225                 priv->buf_size = 0;
2226
2227                 if (!(hdev->hw_tc_map & BIT(i)))
2228                         continue;
2229
2230                 priv->enable = 1;
2231                 priv->buf_size = rx_priv;
2232                 priv->wl.high = rx_priv - hdev->dv_buf_size;
2233                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
2234         }
2235
2236         buf_alloc->s_buf.buf_size = 0;
2237
2238         return true;
2239 }
2240
2241 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
2242  * @hdev: pointer to struct hclge_dev
2243  * @buf_alloc: pointer to buffer calculation data
2244  * @return: 0: calculate successful, negative: fail
2245  */
2246 static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
2247                                 struct hclge_pkt_buf_alloc *buf_alloc)
2248 {
2249         /* When DCB is not supported, rx private buffer is not allocated. */
2250         if (!hnae3_dev_dcb_supported(hdev)) {
2251                 u32 rx_all = hdev->pkt_buf_size;
2252
2253                 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
2254                 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
2255                         return -ENOMEM;
2256
2257                 return 0;
2258         }
2259
2260         if (hclge_only_alloc_priv_buff(hdev, buf_alloc))
2261                 return 0;
2262
2263         if (hclge_rx_buf_calc_all(hdev, true, buf_alloc))
2264                 return 0;
2265
2266         /* try to decrease the buffer size */
2267         if (hclge_rx_buf_calc_all(hdev, false, buf_alloc))
2268                 return 0;
2269
2270         if (hclge_drop_nopfc_buf_till_fit(hdev, buf_alloc))
2271                 return 0;
2272
2273         if (hclge_drop_pfc_buf_till_fit(hdev, buf_alloc))
2274                 return 0;
2275
2276         return -ENOMEM;
2277 }
2278
2279 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
2280                                    struct hclge_pkt_buf_alloc *buf_alloc)
2281 {
2282         struct hclge_rx_priv_buff_cmd *req;
2283         struct hclge_desc desc;
2284         int ret;
2285         int i;
2286
2287         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
2288         req = (struct hclge_rx_priv_buff_cmd *)desc.data;
2289
2290         /* Alloc private buffer TCs */
2291         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2292                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
2293
2294                 req->buf_num[i] =
2295                         cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
2296                 req->buf_num[i] |=
2297                         cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
2298         }
2299
2300         req->shared_buf =
2301                 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
2302                             (1 << HCLGE_TC0_PRI_BUF_EN_B));
2303
2304         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2305         if (ret)
2306                 dev_err(&hdev->pdev->dev,
2307                         "rx private buffer alloc cmd failed %d\n", ret);
2308
2309         return ret;
2310 }
2311
2312 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
2313                                    struct hclge_pkt_buf_alloc *buf_alloc)
2314 {
2315         struct hclge_rx_priv_wl_buf *req;
2316         struct hclge_priv_buf *priv;
2317         struct hclge_desc desc[2];
2318         int i, j;
2319         int ret;
2320
2321         for (i = 0; i < 2; i++) {
2322                 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
2323                                            false);
2324                 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
2325
2326                 /* The first descriptor set the NEXT bit to 1 */
2327                 if (i == 0)
2328                         desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2329                 else
2330                         desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2331
2332                 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
2333                         u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
2334
2335                         priv = &buf_alloc->priv_buf[idx];
2336                         req->tc_wl[j].high =
2337                                 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
2338                         req->tc_wl[j].high |=
2339                                 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
2340                         req->tc_wl[j].low =
2341                                 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
2342                         req->tc_wl[j].low |=
2343                                  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
2344                 }
2345         }
2346
2347         /* Send 2 descriptor at one time */
2348         ret = hclge_cmd_send(&hdev->hw, desc, 2);
2349         if (ret)
2350                 dev_err(&hdev->pdev->dev,
2351                         "rx private waterline config cmd failed %d\n",
2352                         ret);
2353         return ret;
2354 }
2355
2356 static int hclge_common_thrd_config(struct hclge_dev *hdev,
2357                                     struct hclge_pkt_buf_alloc *buf_alloc)
2358 {
2359         struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
2360         struct hclge_rx_com_thrd *req;
2361         struct hclge_desc desc[2];
2362         struct hclge_tc_thrd *tc;
2363         int i, j;
2364         int ret;
2365
2366         for (i = 0; i < 2; i++) {
2367                 hclge_cmd_setup_basic_desc(&desc[i],
2368                                            HCLGE_OPC_RX_COM_THRD_ALLOC, false);
2369                 req = (struct hclge_rx_com_thrd *)&desc[i].data;
2370
2371                 /* The first descriptor set the NEXT bit to 1 */
2372                 if (i == 0)
2373                         desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2374                 else
2375                         desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2376
2377                 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
2378                         tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
2379
2380                         req->com_thrd[j].high =
2381                                 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
2382                         req->com_thrd[j].high |=
2383                                  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
2384                         req->com_thrd[j].low =
2385                                 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
2386                         req->com_thrd[j].low |=
2387                                  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
2388                 }
2389         }
2390
2391         /* Send 2 descriptors at one time */
2392         ret = hclge_cmd_send(&hdev->hw, desc, 2);
2393         if (ret)
2394                 dev_err(&hdev->pdev->dev,
2395                         "common threshold config cmd failed %d\n", ret);
2396         return ret;
2397 }
2398
2399 static int hclge_common_wl_config(struct hclge_dev *hdev,
2400                                   struct hclge_pkt_buf_alloc *buf_alloc)
2401 {
2402         struct hclge_shared_buf *buf = &buf_alloc->s_buf;
2403         struct hclge_rx_com_wl *req;
2404         struct hclge_desc desc;
2405         int ret;
2406
2407         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
2408
2409         req = (struct hclge_rx_com_wl *)desc.data;
2410         req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
2411         req->com_wl.high |=  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
2412
2413         req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
2414         req->com_wl.low |=  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
2415
2416         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2417         if (ret)
2418                 dev_err(&hdev->pdev->dev,
2419                         "common waterline config cmd failed %d\n", ret);
2420
2421         return ret;
2422 }
2423
2424 int hclge_buffer_alloc(struct hclge_dev *hdev)
2425 {
2426         struct hclge_pkt_buf_alloc *pkt_buf;
2427         int ret;
2428
2429         pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
2430         if (!pkt_buf)
2431                 return -ENOMEM;
2432
2433         ret = hclge_tx_buffer_calc(hdev, pkt_buf);
2434         if (ret) {
2435                 dev_err(&hdev->pdev->dev,
2436                         "could not calc tx buffer size for all TCs %d\n", ret);
2437                 goto out;
2438         }
2439
2440         ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
2441         if (ret) {
2442                 dev_err(&hdev->pdev->dev,
2443                         "could not alloc tx buffers %d\n", ret);
2444                 goto out;
2445         }
2446
2447         ret = hclge_rx_buffer_calc(hdev, pkt_buf);
2448         if (ret) {
2449                 dev_err(&hdev->pdev->dev,
2450                         "could not calc rx priv buffer size for all TCs %d\n",
2451                         ret);
2452                 goto out;
2453         }
2454
2455         ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
2456         if (ret) {
2457                 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
2458                         ret);
2459                 goto out;
2460         }
2461
2462         if (hnae3_dev_dcb_supported(hdev)) {
2463                 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
2464                 if (ret) {
2465                         dev_err(&hdev->pdev->dev,
2466                                 "could not configure rx private waterline %d\n",
2467                                 ret);
2468                         goto out;
2469                 }
2470
2471                 ret = hclge_common_thrd_config(hdev, pkt_buf);
2472                 if (ret) {
2473                         dev_err(&hdev->pdev->dev,
2474                                 "could not configure common threshold %d\n",
2475                                 ret);
2476                         goto out;
2477                 }
2478         }
2479
2480         ret = hclge_common_wl_config(hdev, pkt_buf);
2481         if (ret)
2482                 dev_err(&hdev->pdev->dev,
2483                         "could not configure common waterline %d\n", ret);
2484
2485 out:
2486         kfree(pkt_buf);
2487         return ret;
2488 }
2489
2490 static int hclge_init_roce_base_info(struct hclge_vport *vport)
2491 {
2492         struct hnae3_handle *roce = &vport->roce;
2493         struct hnae3_handle *nic = &vport->nic;
2494         struct hclge_dev *hdev = vport->back;
2495
2496         roce->rinfo.num_vectors = vport->back->num_roce_msi;
2497
2498         if (hdev->num_msi < hdev->num_nic_msi + hdev->num_roce_msi)
2499                 return -EINVAL;
2500
2501         roce->rinfo.base_vector = hdev->num_nic_msi;
2502
2503         roce->rinfo.netdev = nic->kinfo.netdev;
2504         roce->rinfo.roce_io_base = hdev->hw.hw.io_base;
2505         roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base;
2506
2507         roce->pdev = nic->pdev;
2508         roce->ae_algo = nic->ae_algo;
2509         roce->numa_node_mask = nic->numa_node_mask;
2510
2511         return 0;
2512 }
2513
2514 static int hclge_init_msi(struct hclge_dev *hdev)
2515 {
2516         struct pci_dev *pdev = hdev->pdev;
2517         int vectors;
2518         int i;
2519
2520         vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM,
2521                                         hdev->num_msi,
2522                                         PCI_IRQ_MSI | PCI_IRQ_MSIX);
2523         if (vectors < 0) {
2524                 dev_err(&pdev->dev,
2525                         "failed(%d) to allocate MSI/MSI-X vectors\n",
2526                         vectors);
2527                 return vectors;
2528         }
2529         if (vectors < hdev->num_msi)
2530                 dev_warn(&hdev->pdev->dev,
2531                          "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2532                          hdev->num_msi, vectors);
2533
2534         hdev->num_msi = vectors;
2535         hdev->num_msi_left = vectors;
2536
2537         hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2538                                            sizeof(u16), GFP_KERNEL);
2539         if (!hdev->vector_status) {
2540                 pci_free_irq_vectors(pdev);
2541                 return -ENOMEM;
2542         }
2543
2544         for (i = 0; i < hdev->num_msi; i++)
2545                 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
2546
2547         hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2548                                         sizeof(int), GFP_KERNEL);
2549         if (!hdev->vector_irq) {
2550                 pci_free_irq_vectors(pdev);
2551                 return -ENOMEM;
2552         }
2553
2554         return 0;
2555 }
2556
2557 static u8 hclge_check_speed_dup(u8 duplex, int speed)
2558 {
2559         if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M))
2560                 duplex = HCLGE_MAC_FULL;
2561
2562         return duplex;
2563 }
2564
2565 static struct hclge_mac_speed_map hclge_mac_speed_map_to_fw[] = {
2566         {HCLGE_MAC_SPEED_10M, HCLGE_FW_MAC_SPEED_10M},
2567         {HCLGE_MAC_SPEED_100M, HCLGE_FW_MAC_SPEED_100M},
2568         {HCLGE_MAC_SPEED_1G, HCLGE_FW_MAC_SPEED_1G},
2569         {HCLGE_MAC_SPEED_10G, HCLGE_FW_MAC_SPEED_10G},
2570         {HCLGE_MAC_SPEED_25G, HCLGE_FW_MAC_SPEED_25G},
2571         {HCLGE_MAC_SPEED_40G, HCLGE_FW_MAC_SPEED_40G},
2572         {HCLGE_MAC_SPEED_50G, HCLGE_FW_MAC_SPEED_50G},
2573         {HCLGE_MAC_SPEED_100G, HCLGE_FW_MAC_SPEED_100G},
2574         {HCLGE_MAC_SPEED_200G, HCLGE_FW_MAC_SPEED_200G},
2575 };
2576
2577 static int hclge_convert_to_fw_speed(u32 speed_drv, u32 *speed_fw)
2578 {
2579         u16 i;
2580
2581         for (i = 0; i < ARRAY_SIZE(hclge_mac_speed_map_to_fw); i++) {
2582                 if (hclge_mac_speed_map_to_fw[i].speed_drv == speed_drv) {
2583                         *speed_fw = hclge_mac_speed_map_to_fw[i].speed_fw;
2584                         return 0;
2585                 }
2586         }
2587
2588         return -EINVAL;
2589 }
2590
2591 static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed,
2592                                       u8 duplex)
2593 {
2594         struct hclge_config_mac_speed_dup_cmd *req;
2595         struct hclge_desc desc;
2596         u32 speed_fw;
2597         int ret;
2598
2599         req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
2600
2601         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
2602
2603         if (duplex)
2604                 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, 1);
2605
2606         ret = hclge_convert_to_fw_speed(speed, &speed_fw);
2607         if (ret) {
2608                 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
2609                 return ret;
2610         }
2611
2612         hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, HCLGE_CFG_SPEED_S,
2613                         speed_fw);
2614         hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
2615                       1);
2616
2617         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2618         if (ret) {
2619                 dev_err(&hdev->pdev->dev,
2620                         "mac speed/duplex config cmd failed %d.\n", ret);
2621                 return ret;
2622         }
2623
2624         return 0;
2625 }
2626
2627 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
2628 {
2629         struct hclge_mac *mac = &hdev->hw.mac;
2630         int ret;
2631
2632         duplex = hclge_check_speed_dup(duplex, speed);
2633         if (!mac->support_autoneg && mac->speed == speed &&
2634             mac->duplex == duplex)
2635                 return 0;
2636
2637         ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex);
2638         if (ret)
2639                 return ret;
2640
2641         hdev->hw.mac.speed = speed;
2642         hdev->hw.mac.duplex = duplex;
2643
2644         return 0;
2645 }
2646
2647 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2648                                      u8 duplex)
2649 {
2650         struct hclge_vport *vport = hclge_get_vport(handle);
2651         struct hclge_dev *hdev = vport->back;
2652
2653         return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2654 }
2655
2656 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2657 {
2658         struct hclge_config_auto_neg_cmd *req;
2659         struct hclge_desc desc;
2660         u32 flag = 0;
2661         int ret;
2662
2663         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2664
2665         req = (struct hclge_config_auto_neg_cmd *)desc.data;
2666         if (enable)
2667                 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, 1U);
2668         req->cfg_an_cmd_flag = cpu_to_le32(flag);
2669
2670         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2671         if (ret)
2672                 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2673                         ret);
2674
2675         return ret;
2676 }
2677
2678 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2679 {
2680         struct hclge_vport *vport = hclge_get_vport(handle);
2681         struct hclge_dev *hdev = vport->back;
2682
2683         if (!hdev->hw.mac.support_autoneg) {
2684                 if (enable) {
2685                         dev_err(&hdev->pdev->dev,
2686                                 "autoneg is not supported by current port\n");
2687                         return -EOPNOTSUPP;
2688                 } else {
2689                         return 0;
2690                 }
2691         }
2692
2693         return hclge_set_autoneg_en(hdev, enable);
2694 }
2695
2696 static int hclge_get_autoneg(struct hnae3_handle *handle)
2697 {
2698         struct hclge_vport *vport = hclge_get_vport(handle);
2699         struct hclge_dev *hdev = vport->back;
2700         struct phy_device *phydev = hdev->hw.mac.phydev;
2701
2702         if (phydev)
2703                 return phydev->autoneg;
2704
2705         return hdev->hw.mac.autoneg;
2706 }
2707
2708 static int hclge_restart_autoneg(struct hnae3_handle *handle)
2709 {
2710         struct hclge_vport *vport = hclge_get_vport(handle);
2711         struct hclge_dev *hdev = vport->back;
2712         int ret;
2713
2714         dev_dbg(&hdev->pdev->dev, "restart autoneg\n");
2715
2716         ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2717         if (ret)
2718                 return ret;
2719         return hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2720 }
2721
2722 static int hclge_halt_autoneg(struct hnae3_handle *handle, bool halt)
2723 {
2724         struct hclge_vport *vport = hclge_get_vport(handle);
2725         struct hclge_dev *hdev = vport->back;
2726
2727         if (hdev->hw.mac.support_autoneg && hdev->hw.mac.autoneg)
2728                 return hclge_set_autoneg_en(hdev, !halt);
2729
2730         return 0;
2731 }
2732
2733 static int hclge_set_fec_hw(struct hclge_dev *hdev, u32 fec_mode)
2734 {
2735         struct hclge_config_fec_cmd *req;
2736         struct hclge_desc desc;
2737         int ret;
2738
2739         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_FEC_MODE, false);
2740
2741         req = (struct hclge_config_fec_cmd *)desc.data;
2742         if (fec_mode & BIT(HNAE3_FEC_AUTO))
2743                 hnae3_set_bit(req->fec_mode, HCLGE_MAC_CFG_FEC_AUTO_EN_B, 1);
2744         if (fec_mode & BIT(HNAE3_FEC_RS))
2745                 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M,
2746                                 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_RS);
2747         if (fec_mode & BIT(HNAE3_FEC_BASER))
2748                 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M,
2749                                 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_BASER);
2750
2751         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2752         if (ret)
2753                 dev_err(&hdev->pdev->dev, "set fec mode failed %d.\n", ret);
2754
2755         return ret;
2756 }
2757
2758 static int hclge_set_fec(struct hnae3_handle *handle, u32 fec_mode)
2759 {
2760         struct hclge_vport *vport = hclge_get_vport(handle);
2761         struct hclge_dev *hdev = vport->back;
2762         struct hclge_mac *mac = &hdev->hw.mac;
2763         int ret;
2764
2765         if (fec_mode && !(mac->fec_ability & fec_mode)) {
2766                 dev_err(&hdev->pdev->dev, "unsupported fec mode\n");
2767                 return -EINVAL;
2768         }
2769
2770         ret = hclge_set_fec_hw(hdev, fec_mode);
2771         if (ret)
2772                 return ret;
2773
2774         mac->user_fec_mode = fec_mode | BIT(HNAE3_FEC_USER_DEF);
2775         return 0;
2776 }
2777
2778 static void hclge_get_fec(struct hnae3_handle *handle, u8 *fec_ability,
2779                           u8 *fec_mode)
2780 {
2781         struct hclge_vport *vport = hclge_get_vport(handle);
2782         struct hclge_dev *hdev = vport->back;
2783         struct hclge_mac *mac = &hdev->hw.mac;
2784
2785         if (fec_ability)
2786                 *fec_ability = mac->fec_ability;
2787         if (fec_mode)
2788                 *fec_mode = mac->fec_mode;
2789 }
2790
2791 static int hclge_mac_init(struct hclge_dev *hdev)
2792 {
2793         struct hclge_mac *mac = &hdev->hw.mac;
2794         int ret;
2795
2796         hdev->support_sfp_query = true;
2797         hdev->hw.mac.duplex = HCLGE_MAC_FULL;
2798         ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed,
2799                                          hdev->hw.mac.duplex);
2800         if (ret)
2801                 return ret;
2802
2803         if (hdev->hw.mac.support_autoneg) {
2804                 ret = hclge_set_autoneg_en(hdev, hdev->hw.mac.autoneg);
2805                 if (ret)
2806                         return ret;
2807         }
2808
2809         mac->link = 0;
2810
2811         if (mac->user_fec_mode & BIT(HNAE3_FEC_USER_DEF)) {
2812                 ret = hclge_set_fec_hw(hdev, mac->user_fec_mode);
2813                 if (ret)
2814                         return ret;
2815         }
2816
2817         ret = hclge_set_mac_mtu(hdev, hdev->mps);
2818         if (ret) {
2819                 dev_err(&hdev->pdev->dev, "set mtu failed ret=%d\n", ret);
2820                 return ret;
2821         }
2822
2823         ret = hclge_set_default_loopback(hdev);
2824         if (ret)
2825                 return ret;
2826
2827         ret = hclge_buffer_alloc(hdev);
2828         if (ret)
2829                 dev_err(&hdev->pdev->dev,
2830                         "allocate buffer fail, ret=%d\n", ret);
2831
2832         return ret;
2833 }
2834
2835 static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
2836 {
2837         if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2838             !test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) {
2839                 hdev->last_mbx_scheduled = jiffies;
2840                 mod_delayed_work(hclge_wq, &hdev->service_task, 0);
2841         }
2842 }
2843
2844 static void hclge_reset_task_schedule(struct hclge_dev *hdev)
2845 {
2846         if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2847             test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state) &&
2848             !test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) {
2849                 hdev->last_rst_scheduled = jiffies;
2850                 mod_delayed_work(hclge_wq, &hdev->service_task, 0);
2851         }
2852 }
2853
2854 static void hclge_errhand_task_schedule(struct hclge_dev *hdev)
2855 {
2856         if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2857             !test_and_set_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state))
2858                 mod_delayed_work(hclge_wq, &hdev->service_task, 0);
2859 }
2860
2861 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time)
2862 {
2863         if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2864             !test_bit(HCLGE_STATE_RST_FAIL, &hdev->state))
2865                 mod_delayed_work(hclge_wq, &hdev->service_task, delay_time);
2866 }
2867
2868 static int hclge_get_mac_link_status(struct hclge_dev *hdev, int *link_status)
2869 {
2870         struct hclge_link_status_cmd *req;
2871         struct hclge_desc desc;
2872         int ret;
2873
2874         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2875         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2876         if (ret) {
2877                 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2878                         ret);
2879                 return ret;
2880         }
2881
2882         req = (struct hclge_link_status_cmd *)desc.data;
2883         *link_status = (req->status & HCLGE_LINK_STATUS_UP_M) > 0 ?
2884                 HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN;
2885
2886         return 0;
2887 }
2888
2889 static int hclge_get_mac_phy_link(struct hclge_dev *hdev, int *link_status)
2890 {
2891         struct phy_device *phydev = hdev->hw.mac.phydev;
2892
2893         *link_status = HCLGE_LINK_STATUS_DOWN;
2894
2895         if (test_bit(HCLGE_STATE_DOWN, &hdev->state))
2896                 return 0;
2897
2898         if (phydev && (phydev->state != PHY_RUNNING || !phydev->link))
2899                 return 0;
2900
2901         return hclge_get_mac_link_status(hdev, link_status);
2902 }
2903
2904 static void hclge_push_link_status(struct hclge_dev *hdev)
2905 {
2906         struct hclge_vport *vport;
2907         int ret;
2908         u16 i;
2909
2910         for (i = 0; i < pci_num_vf(hdev->pdev); i++) {
2911                 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM];
2912
2913                 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) ||
2914                     vport->vf_info.link_state != IFLA_VF_LINK_STATE_AUTO)
2915                         continue;
2916
2917                 ret = hclge_push_vf_link_status(vport);
2918                 if (ret) {
2919                         dev_err(&hdev->pdev->dev,
2920                                 "failed to push link status to vf%u, ret = %d\n",
2921                                 i, ret);
2922                 }
2923         }
2924 }
2925
2926 static void hclge_update_link_status(struct hclge_dev *hdev)
2927 {
2928         struct hnae3_handle *rhandle = &hdev->vport[0].roce;
2929         struct hnae3_handle *handle = &hdev->vport[0].nic;
2930         struct hnae3_client *rclient = hdev->roce_client;
2931         struct hnae3_client *client = hdev->nic_client;
2932         int state;
2933         int ret;
2934
2935         if (!client)
2936                 return;
2937
2938         if (test_and_set_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state))
2939                 return;
2940
2941         ret = hclge_get_mac_phy_link(hdev, &state);
2942         if (ret) {
2943                 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state);
2944                 return;
2945         }
2946
2947         if (state != hdev->hw.mac.link) {
2948                 hdev->hw.mac.link = state;
2949                 client->ops->link_status_change(handle, state);
2950                 hclge_config_mac_tnl_int(hdev, state);
2951                 if (rclient && rclient->ops->link_status_change)
2952                         rclient->ops->link_status_change(rhandle, state);
2953
2954                 hclge_push_link_status(hdev);
2955         }
2956
2957         clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state);
2958 }
2959
2960 static void hclge_update_speed_advertising(struct hclge_mac *mac)
2961 {
2962         u32 speed_ability;
2963
2964         if (hclge_get_speed_bit(mac->speed, &speed_ability))
2965                 return;
2966
2967         switch (mac->module_type) {
2968         case HNAE3_MODULE_TYPE_FIBRE_LR:
2969                 hclge_convert_setting_lr(speed_ability, mac->advertising);
2970                 break;
2971         case HNAE3_MODULE_TYPE_FIBRE_SR:
2972         case HNAE3_MODULE_TYPE_AOC:
2973                 hclge_convert_setting_sr(speed_ability, mac->advertising);
2974                 break;
2975         case HNAE3_MODULE_TYPE_CR:
2976                 hclge_convert_setting_cr(speed_ability, mac->advertising);
2977                 break;
2978         case HNAE3_MODULE_TYPE_KR:
2979                 hclge_convert_setting_kr(speed_ability, mac->advertising);
2980                 break;
2981         default:
2982                 break;
2983         }
2984 }
2985
2986 static void hclge_update_fec_advertising(struct hclge_mac *mac)
2987 {
2988         if (mac->fec_mode & BIT(HNAE3_FEC_RS))
2989                 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
2990                                  mac->advertising);
2991         else if (mac->fec_mode & BIT(HNAE3_FEC_BASER))
2992                 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
2993                                  mac->advertising);
2994         else
2995                 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
2996                                  mac->advertising);
2997 }
2998
2999 static void hclge_update_pause_advertising(struct hclge_dev *hdev)
3000 {
3001         struct hclge_mac *mac = &hdev->hw.mac;
3002         bool rx_en, tx_en;
3003
3004         switch (hdev->fc_mode_last_time) {
3005         case HCLGE_FC_RX_PAUSE:
3006                 rx_en = true;
3007                 tx_en = false;
3008                 break;
3009         case HCLGE_FC_TX_PAUSE:
3010                 rx_en = false;
3011                 tx_en = true;
3012                 break;
3013         case HCLGE_FC_FULL:
3014                 rx_en = true;
3015                 tx_en = true;
3016                 break;
3017         default:
3018                 rx_en = false;
3019                 tx_en = false;
3020                 break;
3021         }
3022
3023         linkmode_set_pause(mac->advertising, tx_en, rx_en);
3024 }
3025
3026 static void hclge_update_advertising(struct hclge_dev *hdev)
3027 {
3028         struct hclge_mac *mac = &hdev->hw.mac;
3029
3030         linkmode_zero(mac->advertising);
3031         hclge_update_speed_advertising(mac);
3032         hclge_update_fec_advertising(mac);
3033         hclge_update_pause_advertising(hdev);
3034 }
3035
3036 static void hclge_update_port_capability(struct hclge_dev *hdev,
3037                                          struct hclge_mac *mac)
3038 {
3039         if (hnae3_dev_fec_supported(hdev))
3040                 /* update fec ability by speed */
3041                 hclge_convert_setting_fec(mac);
3042
3043         /* firmware can not identify back plane type, the media type
3044          * read from configuration can help deal it
3045          */
3046         if (mac->media_type == HNAE3_MEDIA_TYPE_BACKPLANE &&
3047             mac->module_type == HNAE3_MODULE_TYPE_UNKNOWN)
3048                 mac->module_type = HNAE3_MODULE_TYPE_KR;
3049         else if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER)
3050                 mac->module_type = HNAE3_MODULE_TYPE_TP;
3051
3052         if (mac->support_autoneg) {
3053                 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mac->supported);
3054                 linkmode_copy(mac->advertising, mac->supported);
3055         } else {
3056                 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
3057                                    mac->supported);
3058                 hclge_update_advertising(hdev);
3059         }
3060 }
3061
3062 static int hclge_get_sfp_speed(struct hclge_dev *hdev, u32 *speed)
3063 {
3064         struct hclge_sfp_info_cmd *resp;
3065         struct hclge_desc desc;
3066         int ret;
3067
3068         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true);
3069         resp = (struct hclge_sfp_info_cmd *)desc.data;
3070         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3071         if (ret == -EOPNOTSUPP) {
3072                 dev_warn(&hdev->pdev->dev,
3073                          "IMP do not support get SFP speed %d\n", ret);
3074                 return ret;
3075         } else if (ret) {
3076                 dev_err(&hdev->pdev->dev, "get sfp speed failed %d\n", ret);
3077                 return ret;
3078         }
3079
3080         *speed = le32_to_cpu(resp->speed);
3081
3082         return 0;
3083 }
3084
3085 static int hclge_get_sfp_info(struct hclge_dev *hdev, struct hclge_mac *mac)
3086 {
3087         struct hclge_sfp_info_cmd *resp;
3088         struct hclge_desc desc;
3089         int ret;
3090
3091         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true);
3092         resp = (struct hclge_sfp_info_cmd *)desc.data;
3093
3094         resp->query_type = QUERY_ACTIVE_SPEED;
3095
3096         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3097         if (ret == -EOPNOTSUPP) {
3098                 dev_warn(&hdev->pdev->dev,
3099                          "IMP does not support get SFP info %d\n", ret);
3100                 return ret;
3101         } else if (ret) {
3102                 dev_err(&hdev->pdev->dev, "get sfp info failed %d\n", ret);
3103                 return ret;
3104         }
3105
3106         /* In some case, mac speed get from IMP may be 0, it shouldn't be
3107          * set to mac->speed.
3108          */
3109         if (!le32_to_cpu(resp->speed))
3110                 return 0;
3111
3112         mac->speed = le32_to_cpu(resp->speed);
3113         /* if resp->speed_ability is 0, it means it's an old version
3114          * firmware, do not update these params
3115          */
3116         if (resp->speed_ability) {
3117                 mac->module_type = le32_to_cpu(resp->module_type);
3118                 mac->speed_ability = le32_to_cpu(resp->speed_ability);
3119                 mac->autoneg = resp->autoneg;
3120                 mac->support_autoneg = resp->autoneg_ability;
3121                 mac->speed_type = QUERY_ACTIVE_SPEED;
3122                 if (!resp->active_fec)
3123                         mac->fec_mode = 0;
3124                 else
3125                         mac->fec_mode = BIT(resp->active_fec);
3126         } else {
3127                 mac->speed_type = QUERY_SFP_SPEED;
3128         }
3129
3130         return 0;
3131 }
3132
3133 static int hclge_get_phy_link_ksettings(struct hnae3_handle *handle,
3134                                         struct ethtool_link_ksettings *cmd)
3135 {
3136         struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM];
3137         struct hclge_vport *vport = hclge_get_vport(handle);
3138         struct hclge_phy_link_ksetting_0_cmd *req0;
3139         struct hclge_phy_link_ksetting_1_cmd *req1;
3140         u32 supported, advertising, lp_advertising;
3141         struct hclge_dev *hdev = vport->back;
3142         int ret;
3143
3144         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING,
3145                                    true);
3146         desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
3147         hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING,
3148                                    true);
3149
3150         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM);
3151         if (ret) {
3152                 dev_err(&hdev->pdev->dev,
3153                         "failed to get phy link ksetting, ret = %d.\n", ret);
3154                 return ret;
3155         }
3156
3157         req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data;
3158         cmd->base.autoneg = req0->autoneg;
3159         cmd->base.speed = le32_to_cpu(req0->speed);
3160         cmd->base.duplex = req0->duplex;
3161         cmd->base.port = req0->port;
3162         cmd->base.transceiver = req0->transceiver;
3163         cmd->base.phy_address = req0->phy_address;
3164         cmd->base.eth_tp_mdix = req0->eth_tp_mdix;
3165         cmd->base.eth_tp_mdix_ctrl = req0->eth_tp_mdix_ctrl;
3166         supported = le32_to_cpu(req0->supported);
3167         advertising = le32_to_cpu(req0->advertising);
3168         lp_advertising = le32_to_cpu(req0->lp_advertising);
3169         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
3170                                                 supported);
3171         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
3172                                                 advertising);
3173         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising,
3174                                                 lp_advertising);
3175
3176         req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data;
3177         cmd->base.master_slave_cfg = req1->master_slave_cfg;
3178         cmd->base.master_slave_state = req1->master_slave_state;
3179
3180         return 0;
3181 }
3182
3183 static int
3184 hclge_set_phy_link_ksettings(struct hnae3_handle *handle,
3185                              const struct ethtool_link_ksettings *cmd)
3186 {
3187         struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM];
3188         struct hclge_vport *vport = hclge_get_vport(handle);
3189         struct hclge_phy_link_ksetting_0_cmd *req0;
3190         struct hclge_phy_link_ksetting_1_cmd *req1;
3191         struct hclge_dev *hdev = vport->back;
3192         u32 advertising;
3193         int ret;
3194
3195         if (cmd->base.autoneg == AUTONEG_DISABLE &&
3196             ((cmd->base.speed != SPEED_100 && cmd->base.speed != SPEED_10) ||
3197              (cmd->base.duplex != DUPLEX_HALF &&
3198               cmd->base.duplex != DUPLEX_FULL)))
3199                 return -EINVAL;
3200
3201         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING,
3202                                    false);
3203         desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
3204         hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING,
3205                                    false);
3206
3207         req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data;
3208         req0->autoneg = cmd->base.autoneg;
3209         req0->speed = cpu_to_le32(cmd->base.speed);
3210         req0->duplex = cmd->base.duplex;
3211         ethtool_convert_link_mode_to_legacy_u32(&advertising,
3212                                                 cmd->link_modes.advertising);
3213         req0->advertising = cpu_to_le32(advertising);
3214         req0->eth_tp_mdix_ctrl = cmd->base.eth_tp_mdix_ctrl;
3215
3216         req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data;
3217         req1->master_slave_cfg = cmd->base.master_slave_cfg;
3218
3219         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM);
3220         if (ret) {
3221                 dev_err(&hdev->pdev->dev,
3222                         "failed to set phy link ksettings, ret = %d.\n", ret);
3223                 return ret;
3224         }
3225
3226         hdev->hw.mac.autoneg = cmd->base.autoneg;
3227         hdev->hw.mac.speed = cmd->base.speed;
3228         hdev->hw.mac.duplex = cmd->base.duplex;
3229         linkmode_copy(hdev->hw.mac.advertising, cmd->link_modes.advertising);
3230
3231         return 0;
3232 }
3233
3234 static int hclge_update_tp_port_info(struct hclge_dev *hdev)
3235 {
3236         struct ethtool_link_ksettings cmd;
3237         int ret;
3238
3239         if (!hnae3_dev_phy_imp_supported(hdev))
3240                 return 0;
3241
3242         ret = hclge_get_phy_link_ksettings(&hdev->vport->nic, &cmd);
3243         if (ret)
3244                 return ret;
3245
3246         hdev->hw.mac.autoneg = cmd.base.autoneg;
3247         hdev->hw.mac.speed = cmd.base.speed;
3248         hdev->hw.mac.duplex = cmd.base.duplex;
3249
3250         return 0;
3251 }
3252
3253 static int hclge_tp_port_init(struct hclge_dev *hdev)
3254 {
3255         struct ethtool_link_ksettings cmd;
3256
3257         if (!hnae3_dev_phy_imp_supported(hdev))
3258                 return 0;
3259
3260         cmd.base.autoneg = hdev->hw.mac.autoneg;
3261         cmd.base.speed = hdev->hw.mac.speed;
3262         cmd.base.duplex = hdev->hw.mac.duplex;
3263         linkmode_copy(cmd.link_modes.advertising, hdev->hw.mac.advertising);
3264
3265         return hclge_set_phy_link_ksettings(&hdev->vport->nic, &cmd);
3266 }
3267
3268 static int hclge_update_port_info(struct hclge_dev *hdev)
3269 {
3270         struct hclge_mac *mac = &hdev->hw.mac;
3271         int speed = HCLGE_MAC_SPEED_UNKNOWN;
3272         int ret;
3273
3274         /* get the port info from SFP cmd if not copper port */
3275         if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER)
3276                 return hclge_update_tp_port_info(hdev);
3277
3278         /* if IMP does not support get SFP/qSFP info, return directly */
3279         if (!hdev->support_sfp_query)
3280                 return 0;
3281
3282         if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)
3283                 ret = hclge_get_sfp_info(hdev, mac);
3284         else
3285                 ret = hclge_get_sfp_speed(hdev, &speed);
3286
3287         if (ret == -EOPNOTSUPP) {
3288                 hdev->support_sfp_query = false;
3289                 return ret;
3290         } else if (ret) {
3291                 return ret;
3292         }
3293
3294         if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
3295                 if (mac->speed_type == QUERY_ACTIVE_SPEED) {
3296                         hclge_update_port_capability(hdev, mac);
3297                         return 0;
3298                 }
3299                 return hclge_cfg_mac_speed_dup(hdev, mac->speed,
3300                                                HCLGE_MAC_FULL);
3301         } else {
3302                 if (speed == HCLGE_MAC_SPEED_UNKNOWN)
3303                         return 0; /* do nothing if no SFP */
3304
3305                 /* must config full duplex for SFP */
3306                 return hclge_cfg_mac_speed_dup(hdev, speed, HCLGE_MAC_FULL);
3307         }
3308 }
3309
3310 static int hclge_get_status(struct hnae3_handle *handle)
3311 {
3312         struct hclge_vport *vport = hclge_get_vport(handle);
3313         struct hclge_dev *hdev = vport->back;
3314
3315         hclge_update_link_status(hdev);
3316
3317         return hdev->hw.mac.link;
3318 }
3319
3320 static struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf)
3321 {
3322         if (!pci_num_vf(hdev->pdev)) {
3323                 dev_err(&hdev->pdev->dev,
3324                         "SRIOV is disabled, can not get vport(%d) info.\n", vf);
3325                 return NULL;
3326         }
3327
3328         if (vf < 0 || vf >= pci_num_vf(hdev->pdev)) {
3329                 dev_err(&hdev->pdev->dev,
3330                         "vf id(%d) is out of range(0 <= vfid < %d)\n",
3331                         vf, pci_num_vf(hdev->pdev));
3332                 return NULL;
3333         }
3334
3335         /* VF start from 1 in vport */
3336         vf += HCLGE_VF_VPORT_START_NUM;
3337         return &hdev->vport[vf];
3338 }
3339
3340 static int hclge_get_vf_config(struct hnae3_handle *handle, int vf,
3341                                struct ifla_vf_info *ivf)
3342 {
3343         struct hclge_vport *vport = hclge_get_vport(handle);
3344         struct hclge_dev *hdev = vport->back;
3345
3346         vport = hclge_get_vf_vport(hdev, vf);
3347         if (!vport)
3348                 return -EINVAL;
3349
3350         ivf->vf = vf;
3351         ivf->linkstate = vport->vf_info.link_state;
3352         ivf->spoofchk = vport->vf_info.spoofchk;
3353         ivf->trusted = vport->vf_info.trusted;
3354         ivf->min_tx_rate = 0;
3355         ivf->max_tx_rate = vport->vf_info.max_tx_rate;
3356         ivf->vlan = vport->port_base_vlan_cfg.vlan_info.vlan_tag;
3357         ivf->vlan_proto = htons(vport->port_base_vlan_cfg.vlan_info.vlan_proto);
3358         ivf->qos = vport->port_base_vlan_cfg.vlan_info.qos;
3359         ether_addr_copy(ivf->mac, vport->vf_info.mac);
3360
3361         return 0;
3362 }
3363
3364 static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf,
3365                                    int link_state)
3366 {
3367         struct hclge_vport *vport = hclge_get_vport(handle);
3368         struct hclge_dev *hdev = vport->back;
3369         int link_state_old;
3370         int ret;
3371
3372         vport = hclge_get_vf_vport(hdev, vf);
3373         if (!vport)
3374                 return -EINVAL;
3375
3376         link_state_old = vport->vf_info.link_state;
3377         vport->vf_info.link_state = link_state;
3378
3379         ret = hclge_push_vf_link_status(vport);
3380         if (ret) {
3381                 vport->vf_info.link_state = link_state_old;
3382                 dev_err(&hdev->pdev->dev,
3383                         "failed to push vf%d link status, ret = %d\n", vf, ret);
3384         }
3385
3386         return ret;
3387 }
3388
3389 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
3390 {
3391         u32 cmdq_src_reg, msix_src_reg, hw_err_src_reg;
3392
3393         /* fetch the events from their corresponding regs */
3394         cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
3395         msix_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
3396         hw_err_src_reg = hclge_read_dev(&hdev->hw,
3397                                         HCLGE_RAS_PF_OTHER_INT_STS_REG);
3398
3399         /* Assumption: If by any chance reset and mailbox events are reported
3400          * together then we will only process reset event in this go and will
3401          * defer the processing of the mailbox events. Since, we would have not
3402          * cleared RX CMDQ event this time we would receive again another
3403          * interrupt from H/W just for the mailbox.
3404          *
3405          * check for vector0 reset event sources
3406          */
3407         if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) {
3408                 dev_info(&hdev->pdev->dev, "IMP reset interrupt\n");
3409                 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
3410                 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
3411                 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
3412                 hdev->rst_stats.imp_rst_cnt++;
3413                 return HCLGE_VECTOR0_EVENT_RST;
3414         }
3415
3416         if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & msix_src_reg) {
3417                 dev_info(&hdev->pdev->dev, "global reset interrupt\n");
3418                 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
3419                 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
3420                 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
3421                 hdev->rst_stats.global_rst_cnt++;
3422                 return HCLGE_VECTOR0_EVENT_RST;
3423         }
3424
3425         /* check for vector0 msix event and hardware error event source */
3426         if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK ||
3427             hw_err_src_reg & HCLGE_RAS_REG_ERR_MASK)
3428                 return HCLGE_VECTOR0_EVENT_ERR;
3429
3430         /* check for vector0 ptp event source */
3431         if (BIT(HCLGE_VECTOR0_REG_PTP_INT_B) & msix_src_reg) {
3432                 *clearval = msix_src_reg;
3433                 return HCLGE_VECTOR0_EVENT_PTP;
3434         }
3435
3436         /* check for vector0 mailbox(=CMDQ RX) event source */
3437         if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
3438                 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
3439                 *clearval = cmdq_src_reg;
3440                 return HCLGE_VECTOR0_EVENT_MBX;
3441         }
3442
3443         /* print other vector0 event source */
3444         dev_info(&hdev->pdev->dev,
3445                  "INT status: CMDQ(%#x) HW errors(%#x) other(%#x)\n",
3446                  cmdq_src_reg, hw_err_src_reg, msix_src_reg);
3447
3448         return HCLGE_VECTOR0_EVENT_OTHER;
3449 }
3450
3451 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
3452                                     u32 regclr)
3453 {
3454         switch (event_type) {
3455         case HCLGE_VECTOR0_EVENT_PTP:
3456         case HCLGE_VECTOR0_EVENT_RST:
3457                 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
3458                 break;
3459         case HCLGE_VECTOR0_EVENT_MBX:
3460                 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
3461                 break;
3462         default:
3463                 break;
3464         }
3465 }
3466
3467 static void hclge_clear_all_event_cause(struct hclge_dev *hdev)
3468 {
3469         hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST,
3470                                 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) |
3471                                 BIT(HCLGE_VECTOR0_CORERESET_INT_B) |
3472                                 BIT(HCLGE_VECTOR0_IMPRESET_INT_B));
3473         hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0);
3474 }
3475
3476 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
3477 {
3478         writel(enable ? 1 : 0, vector->addr);
3479 }
3480
3481 static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
3482 {
3483         struct hclge_dev *hdev = data;
3484         unsigned long flags;
3485         u32 clearval = 0;
3486         u32 event_cause;
3487
3488         hclge_enable_vector(&hdev->misc_vector, false);
3489         event_cause = hclge_check_event_cause(hdev, &clearval);
3490
3491         /* vector 0 interrupt is shared with reset and mailbox source events. */
3492         switch (event_cause) {
3493         case HCLGE_VECTOR0_EVENT_ERR:
3494                 hclge_errhand_task_schedule(hdev);
3495                 break;
3496         case HCLGE_VECTOR0_EVENT_RST:
3497                 hclge_reset_task_schedule(hdev);
3498                 break;
3499         case HCLGE_VECTOR0_EVENT_PTP:
3500                 spin_lock_irqsave(&hdev->ptp->lock, flags);
3501                 hclge_ptp_clean_tx_hwts(hdev);
3502                 spin_unlock_irqrestore(&hdev->ptp->lock, flags);
3503                 break;
3504         case HCLGE_VECTOR0_EVENT_MBX:
3505                 /* If we are here then,
3506                  * 1. Either we are not handling any mbx task and we are not
3507                  *    scheduled as well
3508                  *                        OR
3509                  * 2. We could be handling a mbx task but nothing more is
3510                  *    scheduled.
3511                  * In both cases, we should schedule mbx task as there are more
3512                  * mbx messages reported by this interrupt.
3513                  */
3514                 hclge_mbx_task_schedule(hdev);
3515                 break;
3516         default:
3517                 dev_warn(&hdev->pdev->dev,
3518                          "received unknown or unhandled event of vector0\n");
3519                 break;
3520         }
3521
3522         hclge_clear_event_cause(hdev, event_cause, clearval);
3523
3524         /* Enable interrupt if it is not caused by reset event or error event */
3525         if (event_cause == HCLGE_VECTOR0_EVENT_PTP ||
3526             event_cause == HCLGE_VECTOR0_EVENT_MBX ||
3527             event_cause == HCLGE_VECTOR0_EVENT_OTHER)
3528                 hclge_enable_vector(&hdev->misc_vector, true);
3529
3530         return IRQ_HANDLED;
3531 }
3532
3533 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
3534 {
3535         if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) {
3536                 dev_warn(&hdev->pdev->dev,
3537                          "vector(vector_id %d) has been freed.\n", vector_id);
3538                 return;
3539         }
3540
3541         hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
3542         hdev->num_msi_left += 1;
3543         hdev->num_msi_used -= 1;
3544 }
3545
3546 static void hclge_get_misc_vector(struct hclge_dev *hdev)
3547 {
3548         struct hclge_misc_vector *vector = &hdev->misc_vector;
3549
3550         vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
3551
3552         vector->addr = hdev->hw.hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
3553         hdev->vector_status[0] = 0;
3554
3555         hdev->num_msi_left -= 1;
3556         hdev->num_msi_used += 1;
3557 }
3558
3559 static int hclge_misc_irq_init(struct hclge_dev *hdev)
3560 {
3561         int ret;
3562
3563         hclge_get_misc_vector(hdev);
3564
3565         /* this would be explicitly freed in the end */
3566         snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s",
3567                  HCLGE_NAME, pci_name(hdev->pdev));
3568         ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
3569                           0, hdev->misc_vector.name, hdev);
3570         if (ret) {
3571                 hclge_free_vector(hdev, 0);
3572                 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
3573                         hdev->misc_vector.vector_irq);
3574         }
3575
3576         return ret;
3577 }
3578
3579 static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
3580 {
3581         free_irq(hdev->misc_vector.vector_irq, hdev);
3582         hclge_free_vector(hdev, 0);
3583 }
3584
3585 int hclge_notify_client(struct hclge_dev *hdev,
3586                         enum hnae3_reset_notify_type type)
3587 {
3588         struct hnae3_handle *handle = &hdev->vport[0].nic;
3589         struct hnae3_client *client = hdev->nic_client;
3590         int ret;
3591
3592         if (!test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state) || !client)
3593                 return 0;
3594
3595         if (!client->ops->reset_notify)
3596                 return -EOPNOTSUPP;
3597
3598         ret = client->ops->reset_notify(handle, type);
3599         if (ret)
3600                 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n",
3601                         type, ret);
3602
3603         return ret;
3604 }
3605
3606 static int hclge_notify_roce_client(struct hclge_dev *hdev,
3607                                     enum hnae3_reset_notify_type type)
3608 {
3609         struct hnae3_handle *handle = &hdev->vport[0].roce;
3610         struct hnae3_client *client = hdev->roce_client;
3611         int ret;
3612
3613         if (!test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state) || !client)
3614                 return 0;
3615
3616         if (!client->ops->reset_notify)
3617                 return -EOPNOTSUPP;
3618
3619         ret = client->ops->reset_notify(handle, type);
3620         if (ret)
3621                 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)",
3622                         type, ret);
3623
3624         return ret;
3625 }
3626
3627 static int hclge_reset_wait(struct hclge_dev *hdev)
3628 {
3629 #define HCLGE_RESET_WATI_MS     100
3630 #define HCLGE_RESET_WAIT_CNT    350
3631
3632         u32 val, reg, reg_bit;
3633         u32 cnt = 0;
3634
3635         switch (hdev->reset_type) {
3636         case HNAE3_IMP_RESET:
3637                 reg = HCLGE_GLOBAL_RESET_REG;
3638                 reg_bit = HCLGE_IMP_RESET_BIT;
3639                 break;
3640         case HNAE3_GLOBAL_RESET:
3641                 reg = HCLGE_GLOBAL_RESET_REG;
3642                 reg_bit = HCLGE_GLOBAL_RESET_BIT;
3643                 break;
3644         case HNAE3_FUNC_RESET:
3645                 reg = HCLGE_FUN_RST_ING;
3646                 reg_bit = HCLGE_FUN_RST_ING_B;
3647                 break;
3648         default:
3649                 dev_err(&hdev->pdev->dev,
3650                         "Wait for unsupported reset type: %d\n",
3651                         hdev->reset_type);
3652                 return -EINVAL;
3653         }
3654
3655         val = hclge_read_dev(&hdev->hw, reg);
3656         while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
3657                 msleep(HCLGE_RESET_WATI_MS);
3658                 val = hclge_read_dev(&hdev->hw, reg);
3659                 cnt++;
3660         }
3661
3662         if (cnt >= HCLGE_RESET_WAIT_CNT) {
3663                 dev_warn(&hdev->pdev->dev,
3664                          "Wait for reset timeout: %d\n", hdev->reset_type);
3665                 return -EBUSY;
3666         }
3667
3668         return 0;
3669 }
3670
3671 static int hclge_set_vf_rst(struct hclge_dev *hdev, int func_id, bool reset)
3672 {
3673         struct hclge_vf_rst_cmd *req;
3674         struct hclge_desc desc;
3675
3676         req = (struct hclge_vf_rst_cmd *)desc.data;
3677         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GBL_RST_STATUS, false);
3678         req->dest_vfid = func_id;
3679
3680         if (reset)
3681                 req->vf_rst = 0x1;
3682
3683         return hclge_cmd_send(&hdev->hw, &desc, 1);
3684 }
3685
3686 static int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset)
3687 {
3688         int i;
3689
3690         for (i = HCLGE_VF_VPORT_START_NUM; i < hdev->num_alloc_vport; i++) {
3691                 struct hclge_vport *vport = &hdev->vport[i];
3692                 int ret;
3693
3694                 /* Send cmd to set/clear VF's FUNC_RST_ING */
3695                 ret = hclge_set_vf_rst(hdev, vport->vport_id, reset);
3696                 if (ret) {
3697                         dev_err(&hdev->pdev->dev,
3698                                 "set vf(%u) rst failed %d!\n",
3699                                 vport->vport_id - HCLGE_VF_VPORT_START_NUM,
3700                                 ret);
3701                         return ret;
3702                 }
3703
3704                 if (!reset || !test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state))
3705                         continue;
3706
3707                 /* Inform VF to process the reset.
3708                  * hclge_inform_reset_assert_to_vf may fail if VF
3709                  * driver is not loaded.
3710                  */
3711                 ret = hclge_inform_reset_assert_to_vf(vport);
3712                 if (ret)
3713                         dev_warn(&hdev->pdev->dev,
3714                                  "inform reset to vf(%u) failed %d!\n",
3715                                  vport->vport_id - HCLGE_VF_VPORT_START_NUM,
3716                                  ret);
3717         }
3718
3719         return 0;
3720 }
3721
3722 static void hclge_mailbox_service_task(struct hclge_dev *hdev)
3723 {
3724         if (!test_and_clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state) ||
3725             test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state) ||
3726             test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
3727                 return;
3728
3729         if (time_is_before_jiffies(hdev->last_mbx_scheduled +
3730                                    HCLGE_MBX_SCHED_TIMEOUT))
3731                 dev_warn(&hdev->pdev->dev,
3732                          "mbx service task is scheduled after %ums on cpu%u!\n",
3733                          jiffies_to_msecs(jiffies - hdev->last_mbx_scheduled),
3734                          smp_processor_id());
3735
3736         hclge_mbx_handler(hdev);
3737
3738         clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
3739 }
3740
3741 static void hclge_func_reset_sync_vf(struct hclge_dev *hdev)
3742 {
3743         struct hclge_pf_rst_sync_cmd *req;
3744         struct hclge_desc desc;
3745         int cnt = 0;
3746         int ret;
3747
3748         req = (struct hclge_pf_rst_sync_cmd *)desc.data;
3749         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RST_RDY, true);
3750
3751         do {
3752                 /* vf need to down netdev by mbx during PF or FLR reset */
3753                 hclge_mailbox_service_task(hdev);
3754
3755                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3756                 /* for compatible with old firmware, wait
3757                  * 100 ms for VF to stop IO
3758                  */
3759                 if (ret == -EOPNOTSUPP) {
3760                         msleep(HCLGE_RESET_SYNC_TIME);
3761                         return;
3762                 } else if (ret) {
3763                         dev_warn(&hdev->pdev->dev, "sync with VF fail %d!\n",
3764                                  ret);
3765                         return;
3766                 } else if (req->all_vf_ready) {
3767                         return;
3768                 }
3769                 msleep(HCLGE_PF_RESET_SYNC_TIME);
3770                 hclge_comm_cmd_reuse_desc(&desc, true);
3771         } while (cnt++ < HCLGE_PF_RESET_SYNC_CNT);
3772
3773         dev_warn(&hdev->pdev->dev, "sync with VF timeout!\n");
3774 }
3775
3776 void hclge_report_hw_error(struct hclge_dev *hdev,
3777                            enum hnae3_hw_error_type type)
3778 {
3779         struct hnae3_client *client = hdev->nic_client;
3780
3781         if (!client || !client->ops->process_hw_error ||
3782             !test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state))
3783                 return;
3784
3785         client->ops->process_hw_error(&hdev->vport[0].nic, type);
3786 }
3787
3788 static void hclge_handle_imp_error(struct hclge_dev *hdev)
3789 {
3790         u32 reg_val;
3791
3792         reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);
3793         if (reg_val & BIT(HCLGE_VECTOR0_IMP_RD_POISON_B)) {
3794                 hclge_report_hw_error(hdev, HNAE3_IMP_RD_POISON_ERROR);
3795                 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_RD_POISON_B);
3796                 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val);
3797         }
3798
3799         if (reg_val & BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B)) {
3800                 hclge_report_hw_error(hdev, HNAE3_CMDQ_ECC_ERROR);
3801                 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B);
3802                 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val);
3803         }
3804 }
3805
3806 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
3807 {
3808         struct hclge_desc desc;
3809         struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
3810         int ret;
3811
3812         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
3813         hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
3814         req->fun_reset_vfid = func_id;
3815
3816         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3817         if (ret)
3818                 dev_err(&hdev->pdev->dev,
3819                         "send function reset cmd fail, status =%d\n", ret);
3820
3821         return ret;
3822 }
3823
3824 static void hclge_do_reset(struct hclge_dev *hdev)
3825 {
3826         struct hnae3_handle *handle = &hdev->vport[0].nic;
3827         struct pci_dev *pdev = hdev->pdev;
3828         u32 val;
3829
3830         if (hclge_get_hw_reset_stat(handle)) {
3831                 dev_info(&pdev->dev, "hardware reset not finish\n");
3832                 dev_info(&pdev->dev, "func_rst_reg:0x%x, global_rst_reg:0x%x\n",
3833                          hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING),
3834                          hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG));
3835                 return;
3836         }
3837
3838         switch (hdev->reset_type) {
3839         case HNAE3_IMP_RESET:
3840                 dev_info(&pdev->dev, "IMP reset requested\n");
3841                 val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);
3842                 hnae3_set_bit(val, HCLGE_TRIGGER_IMP_RESET_B, 1);
3843                 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, val);
3844                 break;
3845         case HNAE3_GLOBAL_RESET:
3846                 dev_info(&pdev->dev, "global reset requested\n");
3847                 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
3848                 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
3849                 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
3850                 break;
3851         case HNAE3_FUNC_RESET:
3852                 dev_info(&pdev->dev, "PF reset requested\n");
3853                 /* schedule again to check later */
3854                 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
3855                 hclge_reset_task_schedule(hdev);
3856                 break;
3857         default:
3858                 dev_warn(&pdev->dev,
3859                          "unsupported reset type: %d\n", hdev->reset_type);
3860                 break;
3861         }
3862 }
3863
3864 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev,
3865                                                    unsigned long *addr)
3866 {
3867         enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
3868         struct hclge_dev *hdev = ae_dev->priv;
3869
3870         /* return the highest priority reset level amongst all */
3871         if (test_bit(HNAE3_IMP_RESET, addr)) {
3872                 rst_level = HNAE3_IMP_RESET;
3873                 clear_bit(HNAE3_IMP_RESET, addr);
3874                 clear_bit(HNAE3_GLOBAL_RESET, addr);
3875                 clear_bit(HNAE3_FUNC_RESET, addr);
3876         } else if (test_bit(HNAE3_GLOBAL_RESET, addr)) {
3877                 rst_level = HNAE3_GLOBAL_RESET;
3878                 clear_bit(HNAE3_GLOBAL_RESET, addr);
3879                 clear_bit(HNAE3_FUNC_RESET, addr);
3880         } else if (test_bit(HNAE3_FUNC_RESET, addr)) {
3881                 rst_level = HNAE3_FUNC_RESET;
3882                 clear_bit(HNAE3_FUNC_RESET, addr);
3883         } else if (test_bit(HNAE3_FLR_RESET, addr)) {
3884                 rst_level = HNAE3_FLR_RESET;
3885                 clear_bit(HNAE3_FLR_RESET, addr);
3886         }
3887
3888         if (hdev->reset_type != HNAE3_NONE_RESET &&
3889             rst_level < hdev->reset_type)
3890                 return HNAE3_NONE_RESET;
3891
3892         return rst_level;
3893 }
3894
3895 static void hclge_clear_reset_cause(struct hclge_dev *hdev)
3896 {
3897         u32 clearval = 0;
3898
3899         switch (hdev->reset_type) {
3900         case HNAE3_IMP_RESET:
3901                 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
3902                 break;
3903         case HNAE3_GLOBAL_RESET:
3904                 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
3905                 break;
3906         default:
3907                 break;
3908         }
3909
3910         if (!clearval)
3911                 return;
3912
3913         /* For revision 0x20, the reset interrupt source
3914          * can only be cleared after hardware reset done
3915          */
3916         if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
3917                 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG,
3918                                 clearval);
3919
3920         hclge_enable_vector(&hdev->misc_vector, true);
3921 }
3922
3923 static void hclge_reset_handshake(struct hclge_dev *hdev, bool enable)
3924 {
3925         u32 reg_val;
3926
3927         reg_val = hclge_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG);
3928         if (enable)
3929                 reg_val |= HCLGE_COMM_NIC_SW_RST_RDY;
3930         else
3931                 reg_val &= ~HCLGE_COMM_NIC_SW_RST_RDY;
3932
3933         hclge_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, reg_val);
3934 }
3935
3936 static int hclge_func_reset_notify_vf(struct hclge_dev *hdev)
3937 {
3938         int ret;
3939
3940         ret = hclge_set_all_vf_rst(hdev, true);
3941         if (ret)
3942                 return ret;
3943
3944         hclge_func_reset_sync_vf(hdev);
3945
3946         return 0;
3947 }
3948
3949 static int hclge_reset_prepare_wait(struct hclge_dev *hdev)
3950 {
3951         u32 reg_val;
3952         int ret = 0;
3953
3954         switch (hdev->reset_type) {
3955         case HNAE3_FUNC_RESET:
3956                 ret = hclge_func_reset_notify_vf(hdev);
3957                 if (ret)
3958                         return ret;
3959
3960                 ret = hclge_func_reset_cmd(hdev, 0);
3961                 if (ret) {
3962                         dev_err(&hdev->pdev->dev,
3963                                 "asserting function reset fail %d!\n", ret);
3964                         return ret;
3965                 }
3966
3967                 /* After performaning pf reset, it is not necessary to do the
3968                  * mailbox handling or send any command to firmware, because
3969                  * any mailbox handling or command to firmware is only valid
3970                  * after hclge_comm_cmd_init is called.
3971                  */
3972                 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
3973                 hdev->rst_stats.pf_rst_cnt++;
3974                 break;
3975         case HNAE3_FLR_RESET:
3976                 ret = hclge_func_reset_notify_vf(hdev);
3977                 if (ret)
3978                         return ret;
3979                 break;
3980         case HNAE3_IMP_RESET:
3981                 hclge_handle_imp_error(hdev);
3982                 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);
3983                 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG,
3984                                 BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val);
3985                 break;
3986         default:
3987                 break;
3988         }
3989
3990         /* inform hardware that preparatory work is done */
3991         msleep(HCLGE_RESET_SYNC_TIME);
3992         hclge_reset_handshake(hdev, true);
3993         dev_info(&hdev->pdev->dev, "prepare wait ok\n");
3994
3995         return ret;
3996 }
3997
3998 static void hclge_show_rst_info(struct hclge_dev *hdev)
3999 {
4000         char *buf;
4001
4002         buf = kzalloc(HCLGE_DBG_RESET_INFO_LEN, GFP_KERNEL);
4003         if (!buf)
4004                 return;
4005
4006         hclge_dbg_dump_rst_info(hdev, buf, HCLGE_DBG_RESET_INFO_LEN);
4007
4008         dev_info(&hdev->pdev->dev, "dump reset info:\n%s", buf);
4009
4010         kfree(buf);
4011 }
4012
4013 static bool hclge_reset_err_handle(struct hclge_dev *hdev)
4014 {
4015 #define MAX_RESET_FAIL_CNT 5
4016
4017         if (hdev->reset_pending) {
4018                 dev_info(&hdev->pdev->dev, "Reset pending %lu\n",
4019                          hdev->reset_pending);
4020                 return true;
4021         } else if (hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) &
4022                    HCLGE_RESET_INT_M) {
4023                 dev_info(&hdev->pdev->dev,
4024                          "reset failed because new reset interrupt\n");
4025                 hclge_clear_reset_cause(hdev);
4026                 return false;
4027         } else if (hdev->rst_stats.reset_fail_cnt < MAX_RESET_FAIL_CNT) {
4028                 hdev->rst_stats.reset_fail_cnt++;
4029                 set_bit(hdev->reset_type, &hdev->reset_pending);
4030                 dev_info(&hdev->pdev->dev,
4031                          "re-schedule reset task(%u)\n",
4032                          hdev->rst_stats.reset_fail_cnt);
4033                 return true;
4034         }
4035
4036         hclge_clear_reset_cause(hdev);
4037
4038         /* recover the handshake status when reset fail */
4039         hclge_reset_handshake(hdev, true);
4040
4041         dev_err(&hdev->pdev->dev, "Reset fail!\n");
4042
4043         hclge_show_rst_info(hdev);
4044
4045         set_bit(HCLGE_STATE_RST_FAIL, &hdev->state);
4046
4047         return false;
4048 }
4049
4050 static void hclge_update_reset_level(struct hclge_dev *hdev)
4051 {
4052         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
4053         enum hnae3_reset_type reset_level;
4054
4055         /* reset request will not be set during reset, so clear
4056          * pending reset request to avoid unnecessary reset
4057          * caused by the same reason.
4058          */
4059         hclge_get_reset_level(ae_dev, &hdev->reset_request);
4060
4061         /* if default_reset_request has a higher level reset request,
4062          * it should be handled as soon as possible. since some errors
4063          * need this kind of reset to fix.
4064          */
4065         reset_level = hclge_get_reset_level(ae_dev,
4066                                             &hdev->default_reset_request);
4067         if (reset_level != HNAE3_NONE_RESET)
4068                 set_bit(reset_level, &hdev->reset_request);
4069 }
4070
4071 static int hclge_set_rst_done(struct hclge_dev *hdev)
4072 {
4073         struct hclge_pf_rst_done_cmd *req;
4074         struct hclge_desc desc;
4075         int ret;
4076
4077         req = (struct hclge_pf_rst_done_cmd *)desc.data;
4078         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PF_RST_DONE, false);
4079         req->pf_rst_done |= HCLGE_PF_RESET_DONE_BIT;
4080
4081         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4082         /* To be compatible with the old firmware, which does not support
4083          * command HCLGE_OPC_PF_RST_DONE, just print a warning and
4084          * return success
4085          */
4086         if (ret == -EOPNOTSUPP) {
4087                 dev_warn(&hdev->pdev->dev,
4088                          "current firmware does not support command(0x%x)!\n",
4089                          HCLGE_OPC_PF_RST_DONE);
4090                 return 0;
4091         } else if (ret) {
4092                 dev_err(&hdev->pdev->dev, "assert PF reset done fail %d!\n",
4093                         ret);
4094         }
4095
4096         return ret;
4097 }
4098
4099 static int hclge_reset_prepare_up(struct hclge_dev *hdev)
4100 {
4101         int ret = 0;
4102
4103         switch (hdev->reset_type) {
4104         case HNAE3_FUNC_RESET:
4105         case HNAE3_FLR_RESET:
4106                 ret = hclge_set_all_vf_rst(hdev, false);
4107                 break;
4108         case HNAE3_GLOBAL_RESET:
4109         case HNAE3_IMP_RESET:
4110                 ret = hclge_set_rst_done(hdev);
4111                 break;
4112         default:
4113                 break;
4114         }
4115
4116         /* clear up the handshake status after re-initialize done */
4117         hclge_reset_handshake(hdev, false);
4118
4119         return ret;
4120 }
4121
4122 static int hclge_reset_stack(struct hclge_dev *hdev)
4123 {
4124         int ret;
4125
4126         ret = hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
4127         if (ret)
4128                 return ret;
4129
4130         ret = hclge_reset_ae_dev(hdev->ae_dev);
4131         if (ret)
4132                 return ret;
4133
4134         return hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
4135 }
4136
4137 static int hclge_reset_prepare(struct hclge_dev *hdev)
4138 {
4139         int ret;
4140
4141         hdev->rst_stats.reset_cnt++;
4142         /* perform reset of the stack & ae device for a client */
4143         ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT);
4144         if (ret)
4145                 return ret;
4146
4147         rtnl_lock();
4148         ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
4149         rtnl_unlock();
4150         if (ret)
4151                 return ret;
4152
4153         return hclge_reset_prepare_wait(hdev);
4154 }
4155
4156 static int hclge_reset_rebuild(struct hclge_dev *hdev)
4157 {
4158         int ret;
4159
4160         hdev->rst_stats.hw_reset_done_cnt++;
4161
4162         ret = hclge_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT);
4163         if (ret)
4164                 return ret;
4165
4166         rtnl_lock();
4167         ret = hclge_reset_stack(hdev);
4168         rtnl_unlock();
4169         if (ret)
4170                 return ret;
4171
4172         hclge_clear_reset_cause(hdev);
4173
4174         ret = hclge_notify_roce_client(hdev, HNAE3_INIT_CLIENT);
4175         /* ignore RoCE notify error if it fails HCLGE_RESET_MAX_FAIL_CNT - 1
4176          * times
4177          */
4178         if (ret &&
4179             hdev->rst_stats.reset_fail_cnt < HCLGE_RESET_MAX_FAIL_CNT - 1)
4180                 return ret;
4181
4182         ret = hclge_reset_prepare_up(hdev);
4183         if (ret)
4184                 return ret;
4185
4186         rtnl_lock();
4187         ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT);
4188         rtnl_unlock();
4189         if (ret)
4190                 return ret;
4191
4192         ret = hclge_notify_roce_client(hdev, HNAE3_UP_CLIENT);
4193         if (ret)
4194                 return ret;
4195
4196         hdev->last_reset_time = jiffies;
4197         hdev->rst_stats.reset_fail_cnt = 0;
4198         hdev->rst_stats.reset_done_cnt++;
4199         clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state);
4200
4201         hclge_update_reset_level(hdev);
4202
4203         return 0;
4204 }
4205
4206 static void hclge_reset(struct hclge_dev *hdev)
4207 {
4208         if (hclge_reset_prepare(hdev))
4209                 goto err_reset;
4210
4211         if (hclge_reset_wait(hdev))
4212                 goto err_reset;
4213
4214         if (hclge_reset_rebuild(hdev))
4215                 goto err_reset;
4216
4217         return;
4218
4219 err_reset:
4220         if (hclge_reset_err_handle(hdev))
4221                 hclge_reset_task_schedule(hdev);
4222 }
4223
4224 static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle)
4225 {
4226         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
4227         struct hclge_dev *hdev = ae_dev->priv;
4228
4229         /* We might end up getting called broadly because of 2 below cases:
4230          * 1. Recoverable error was conveyed through APEI and only way to bring
4231          *    normalcy is to reset.
4232          * 2. A new reset request from the stack due to timeout
4233          *
4234          * check if this is a new reset request and we are not here just because
4235          * last reset attempt did not succeed and watchdog hit us again. We will
4236          * know this if last reset request did not occur very recently (watchdog
4237          * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
4238          * In case of new request we reset the "reset level" to PF reset.
4239          * And if it is a repeat reset request of the most recent one then we
4240          * want to make sure we throttle the reset request. Therefore, we will
4241          * not allow it again before 3*HZ times.
4242          */
4243
4244         if (time_before(jiffies, (hdev->last_reset_time +
4245                                   HCLGE_RESET_INTERVAL))) {
4246                 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL);
4247                 return;
4248         }
4249
4250         if (hdev->default_reset_request) {
4251                 hdev->reset_level =
4252                         hclge_get_reset_level(ae_dev,
4253                                               &hdev->default_reset_request);
4254         } else if (time_after(jiffies, (hdev->last_reset_time + 4 * 5 * HZ))) {
4255                 hdev->reset_level = HNAE3_FUNC_RESET;
4256         }
4257
4258         dev_info(&hdev->pdev->dev, "received reset event, reset type is %d\n",
4259                  hdev->reset_level);
4260
4261         /* request reset & schedule reset task */
4262         set_bit(hdev->reset_level, &hdev->reset_request);
4263         hclge_reset_task_schedule(hdev);
4264
4265         if (hdev->reset_level < HNAE3_GLOBAL_RESET)
4266                 hdev->reset_level++;
4267 }
4268
4269 static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
4270                                         enum hnae3_reset_type rst_type)
4271 {
4272         struct hclge_dev *hdev = ae_dev->priv;
4273
4274         set_bit(rst_type, &hdev->default_reset_request);
4275 }
4276
4277 static void hclge_reset_timer(struct timer_list *t)
4278 {
4279         struct hclge_dev *hdev = from_timer(hdev, t, reset_timer);
4280
4281         /* if default_reset_request has no value, it means that this reset
4282          * request has already be handled, so just return here
4283          */
4284         if (!hdev->default_reset_request)
4285                 return;
4286
4287         dev_info(&hdev->pdev->dev,
4288                  "triggering reset in reset timer\n");
4289         hclge_reset_event(hdev->pdev, NULL);
4290 }
4291
4292 static void hclge_reset_subtask(struct hclge_dev *hdev)
4293 {
4294         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
4295
4296         /* check if there is any ongoing reset in the hardware. This status can
4297          * be checked from reset_pending. If there is then, we need to wait for
4298          * hardware to complete reset.
4299          *    a. If we are able to figure out in reasonable time that hardware
4300          *       has fully resetted then, we can proceed with driver, client
4301          *       reset.
4302          *    b. else, we can come back later to check this status so re-sched
4303          *       now.
4304          */
4305         hdev->last_reset_time = jiffies;
4306         hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_pending);
4307         if (hdev->reset_type != HNAE3_NONE_RESET)
4308                 hclge_reset(hdev);
4309
4310         /* check if we got any *new* reset requests to be honored */
4311         hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_request);
4312         if (hdev->reset_type != HNAE3_NONE_RESET)
4313                 hclge_do_reset(hdev);
4314
4315         hdev->reset_type = HNAE3_NONE_RESET;
4316 }
4317
4318 static void hclge_handle_err_reset_request(struct hclge_dev *hdev)
4319 {
4320         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
4321         enum hnae3_reset_type reset_type;
4322
4323         if (ae_dev->hw_err_reset_req) {
4324                 reset_type = hclge_get_reset_level(ae_dev,
4325                                                    &ae_dev->hw_err_reset_req);
4326                 hclge_set_def_reset_request(ae_dev, reset_type);
4327         }
4328
4329         if (hdev->default_reset_request && ae_dev->ops->reset_event)
4330                 ae_dev->ops->reset_event(hdev->pdev, NULL);
4331
4332         /* enable interrupt after error handling complete */
4333         hclge_enable_vector(&hdev->misc_vector, true);
4334 }
4335
4336 static void hclge_handle_err_recovery(struct hclge_dev *hdev)
4337 {
4338         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
4339
4340         ae_dev->hw_err_reset_req = 0;
4341
4342         if (hclge_find_error_source(hdev)) {
4343                 hclge_handle_error_info_log(ae_dev);
4344                 hclge_handle_mac_tnl(hdev);
4345         }
4346
4347         hclge_handle_err_reset_request(hdev);
4348 }
4349
4350 static void hclge_misc_err_recovery(struct hclge_dev *hdev)
4351 {
4352         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
4353         struct device *dev = &hdev->pdev->dev;
4354         u32 msix_sts_reg;
4355
4356         msix_sts_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
4357         if (msix_sts_reg & HCLGE_VECTOR0_REG_MSIX_MASK) {
4358                 if (hclge_handle_hw_msix_error
4359                                 (hdev, &hdev->default_reset_request))
4360                         dev_info(dev, "received msix interrupt 0x%x\n",
4361                                  msix_sts_reg);
4362         }
4363
4364         hclge_handle_hw_ras_error(ae_dev);
4365
4366         hclge_handle_err_reset_request(hdev);
4367 }
4368
4369 static void hclge_errhand_service_task(struct hclge_dev *hdev)
4370 {
4371         if (!test_and_clear_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state))
4372                 return;
4373
4374         if (hnae3_dev_ras_imp_supported(hdev))
4375                 hclge_handle_err_recovery(hdev);
4376         else
4377                 hclge_misc_err_recovery(hdev);
4378 }
4379
4380 static void hclge_reset_service_task(struct hclge_dev *hdev)
4381 {
4382         if (!test_and_clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
4383                 return;
4384
4385         if (time_is_before_jiffies(hdev->last_rst_scheduled +
4386                                    HCLGE_RESET_SCHED_TIMEOUT))
4387                 dev_warn(&hdev->pdev->dev,
4388                          "reset service task is scheduled after %ums on cpu%u!\n",
4389                          jiffies_to_msecs(jiffies - hdev->last_rst_scheduled),
4390                          smp_processor_id());
4391
4392         down(&hdev->reset_sem);
4393         set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
4394
4395         hclge_reset_subtask(hdev);
4396
4397         clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
4398         up(&hdev->reset_sem);
4399 }
4400
4401 static void hclge_update_vport_alive(struct hclge_dev *hdev)
4402 {
4403         int i;
4404
4405         /* start from vport 1 for PF is always alive */
4406         for (i = 1; i < hdev->num_alloc_vport; i++) {
4407                 struct hclge_vport *vport = &hdev->vport[i];
4408
4409                 if (time_after(jiffies, vport->last_active_jiffies + 8 * HZ))
4410                         clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
4411
4412                 /* If vf is not alive, set to default value */
4413                 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state))
4414                         vport->mps = HCLGE_MAC_DEFAULT_FRAME;
4415         }
4416 }
4417
4418 static void hclge_periodic_service_task(struct hclge_dev *hdev)
4419 {
4420         unsigned long delta = round_jiffies_relative(HZ);
4421
4422         if (test_bit(HCLGE_STATE_RST_FAIL, &hdev->state))
4423                 return;
4424
4425         /* Always handle the link updating to make sure link state is
4426          * updated when it is triggered by mbx.
4427          */
4428         hclge_update_link_status(hdev);
4429         hclge_sync_mac_table(hdev);
4430         hclge_sync_promisc_mode(hdev);
4431         hclge_sync_fd_table(hdev);
4432
4433         if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) {
4434                 delta = jiffies - hdev->last_serv_processed;
4435
4436                 if (delta < round_jiffies_relative(HZ)) {
4437                         delta = round_jiffies_relative(HZ) - delta;
4438                         goto out;
4439                 }
4440         }
4441
4442         hdev->serv_processed_cnt++;
4443         hclge_update_vport_alive(hdev);
4444
4445         if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) {
4446                 hdev->last_serv_processed = jiffies;
4447                 goto out;
4448         }
4449
4450         if (!(hdev->serv_processed_cnt % HCLGE_STATS_TIMER_INTERVAL))
4451                 hclge_update_stats_for_all(hdev);
4452
4453         hclge_update_port_info(hdev);
4454         hclge_sync_vlan_filter(hdev);
4455
4456         if (!(hdev->serv_processed_cnt % HCLGE_ARFS_EXPIRE_INTERVAL))
4457                 hclge_rfs_filter_expire(hdev);
4458
4459         hdev->last_serv_processed = jiffies;
4460
4461 out:
4462         hclge_task_schedule(hdev, delta);
4463 }
4464
4465 static void hclge_ptp_service_task(struct hclge_dev *hdev)
4466 {
4467         unsigned long flags;
4468
4469         if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state) ||
4470             !test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state) ||
4471             !time_is_before_jiffies(hdev->ptp->tx_start + HZ))
4472                 return;
4473
4474         /* to prevent concurrence with the irq handler */
4475         spin_lock_irqsave(&hdev->ptp->lock, flags);
4476
4477         /* check HCLGE_STATE_PTP_TX_HANDLING here again, since the irq
4478          * handler may handle it just before spin_lock_irqsave().
4479          */
4480         if (test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state))
4481                 hclge_ptp_clean_tx_hwts(hdev);
4482
4483         spin_unlock_irqrestore(&hdev->ptp->lock, flags);
4484 }
4485
4486 static void hclge_service_task(struct work_struct *work)
4487 {
4488         struct hclge_dev *hdev =
4489                 container_of(work, struct hclge_dev, service_task.work);
4490
4491         hclge_errhand_service_task(hdev);
4492         hclge_reset_service_task(hdev);
4493         hclge_ptp_service_task(hdev);
4494         hclge_mailbox_service_task(hdev);
4495         hclge_periodic_service_task(hdev);
4496
4497         /* Handle error recovery, reset and mbx again in case periodical task
4498          * delays the handling by calling hclge_task_schedule() in
4499          * hclge_periodic_service_task().
4500          */
4501         hclge_errhand_service_task(hdev);
4502         hclge_reset_service_task(hdev);
4503         hclge_mailbox_service_task(hdev);
4504 }
4505
4506 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
4507 {
4508         /* VF handle has no client */
4509         if (!handle->client)
4510                 return container_of(handle, struct hclge_vport, nic);
4511         else if (handle->client->type == HNAE3_CLIENT_ROCE)
4512                 return container_of(handle, struct hclge_vport, roce);
4513         else
4514                 return container_of(handle, struct hclge_vport, nic);
4515 }
4516
4517 static void hclge_get_vector_info(struct hclge_dev *hdev, u16 idx,
4518                                   struct hnae3_vector_info *vector_info)
4519 {
4520 #define HCLGE_PF_MAX_VECTOR_NUM_DEV_V2  64
4521
4522         vector_info->vector = pci_irq_vector(hdev->pdev, idx);
4523
4524         /* need an extend offset to config vector >= 64 */
4525         if (idx - 1 < HCLGE_PF_MAX_VECTOR_NUM_DEV_V2)
4526                 vector_info->io_addr = hdev->hw.hw.io_base +
4527                                 HCLGE_VECTOR_REG_BASE +
4528                                 (idx - 1) * HCLGE_VECTOR_REG_OFFSET;
4529         else
4530                 vector_info->io_addr = hdev->hw.hw.io_base +
4531                                 HCLGE_VECTOR_EXT_REG_BASE +
4532                                 (idx - 1) / HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 *
4533                                 HCLGE_VECTOR_REG_OFFSET_H +
4534                                 (idx - 1) % HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 *
4535                                 HCLGE_VECTOR_REG_OFFSET;
4536
4537         hdev->vector_status[idx] = hdev->vport[0].vport_id;
4538         hdev->vector_irq[idx] = vector_info->vector;
4539 }
4540
4541 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
4542                             struct hnae3_vector_info *vector_info)
4543 {
4544         struct hclge_vport *vport = hclge_get_vport(handle);
4545         struct hnae3_vector_info *vector = vector_info;
4546         struct hclge_dev *hdev = vport->back;
4547         int alloc = 0;
4548         u16 i = 0;
4549         u16 j;
4550
4551         vector_num = min_t(u16, hdev->num_nic_msi - 1, vector_num);
4552         vector_num = min(hdev->num_msi_left, vector_num);
4553
4554         for (j = 0; j < vector_num; j++) {
4555                 while (++i < hdev->num_nic_msi) {
4556                         if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
4557                                 hclge_get_vector_info(hdev, i, vector);
4558                                 vector++;
4559                                 alloc++;
4560
4561                                 break;
4562                         }
4563                 }
4564         }
4565         hdev->num_msi_left -= alloc;
4566         hdev->num_msi_used += alloc;
4567
4568         return alloc;
4569 }
4570
4571 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
4572 {
4573         int i;
4574
4575         for (i = 0; i < hdev->num_msi; i++)
4576                 if (vector == hdev->vector_irq[i])
4577                         return i;
4578
4579         return -EINVAL;
4580 }
4581
4582 static int hclge_put_vector(struct hnae3_handle *handle, int vector)
4583 {
4584         struct hclge_vport *vport = hclge_get_vport(handle);
4585         struct hclge_dev *hdev = vport->back;
4586         int vector_id;
4587
4588         vector_id = hclge_get_vector_index(hdev, vector);
4589         if (vector_id < 0) {
4590                 dev_err(&hdev->pdev->dev,
4591                         "Get vector index fail. vector = %d\n", vector);
4592                 return vector_id;
4593         }
4594
4595         hclge_free_vector(hdev, vector_id);
4596
4597         return 0;
4598 }
4599
4600 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
4601                          u8 *key, u8 *hfunc)
4602 {
4603         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
4604         struct hclge_vport *vport = hclge_get_vport(handle);
4605         struct hclge_comm_rss_cfg *rss_cfg = &vport->back->rss_cfg;
4606
4607         hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc);
4608
4609         hclge_comm_get_rss_indir_tbl(rss_cfg, indir,
4610                                      ae_dev->dev_specs.rss_ind_tbl_size);
4611
4612         return 0;
4613 }
4614
4615 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
4616                          const  u8 *key, const  u8 hfunc)
4617 {
4618         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
4619         struct hclge_vport *vport = hclge_get_vport(handle);
4620         struct hclge_dev *hdev = vport->back;
4621         struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg;
4622         int ret, i;
4623
4624         ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, hfunc);
4625         if (ret) {
4626                 dev_err(&hdev->pdev->dev, "invalid hfunc type %u\n", hfunc);
4627                 return ret;
4628         }
4629
4630         /* Update the shadow RSS table with user specified qids */
4631         for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++)
4632                 rss_cfg->rss_indirection_tbl[i] = indir[i];
4633
4634         /* Update the hardware */
4635         return hclge_comm_set_rss_indir_table(ae_dev, &hdev->hw.hw,
4636                                               rss_cfg->rss_indirection_tbl);
4637 }
4638
4639 static int hclge_set_rss_tuple(struct hnae3_handle *handle,
4640                                struct ethtool_rxnfc *nfc)
4641 {
4642         struct hclge_vport *vport = hclge_get_vport(handle);
4643         struct hclge_dev *hdev = vport->back;
4644         int ret;
4645
4646         ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw,
4647                                        &hdev->rss_cfg, nfc);
4648         if (ret) {
4649                 dev_err(&hdev->pdev->dev,
4650                         "failed to set rss tuple, ret = %d.\n", ret);
4651                 return ret;
4652         }
4653
4654         hclge_comm_get_rss_type(&vport->nic, &hdev->rss_cfg.rss_tuple_sets);
4655         return 0;
4656 }
4657
4658 static int hclge_get_rss_tuple(struct hnae3_handle *handle,
4659                                struct ethtool_rxnfc *nfc)
4660 {
4661         struct hclge_vport *vport = hclge_get_vport(handle);
4662         u8 tuple_sets;
4663         int ret;
4664
4665         nfc->data = 0;
4666
4667         ret = hclge_comm_get_rss_tuple(&vport->back->rss_cfg, nfc->flow_type,
4668                                        &tuple_sets);
4669         if (ret || !tuple_sets)
4670                 return ret;
4671
4672         nfc->data = hclge_comm_convert_rss_tuple(tuple_sets);
4673
4674         return 0;
4675 }
4676
4677 static int hclge_get_tc_size(struct hnae3_handle *handle)
4678 {
4679         struct hclge_vport *vport = hclge_get_vport(handle);
4680         struct hclge_dev *hdev = vport->back;
4681
4682         return hdev->pf_rss_size_max;
4683 }
4684
4685 static int hclge_init_rss_tc_mode(struct hclge_dev *hdev)
4686 {
4687         struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
4688         struct hclge_vport *vport = hdev->vport;
4689         u16 tc_offset[HCLGE_MAX_TC_NUM] = {0};
4690         u16 tc_valid[HCLGE_MAX_TC_NUM] = {0};
4691         u16 tc_size[HCLGE_MAX_TC_NUM] = {0};
4692         struct hnae3_tc_info *tc_info;
4693         u16 roundup_size;
4694         u16 rss_size;
4695         int i;
4696
4697         tc_info = &vport->nic.kinfo.tc_info;
4698         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
4699                 rss_size = tc_info->tqp_count[i];
4700                 tc_valid[i] = 0;
4701
4702                 if (!(hdev->hw_tc_map & BIT(i)))
4703                         continue;
4704
4705                 /* tc_size set to hardware is the log2 of roundup power of two
4706                  * of rss_size, the acutal queue size is limited by indirection
4707                  * table.
4708                  */
4709                 if (rss_size > ae_dev->dev_specs.rss_ind_tbl_size ||
4710                     rss_size == 0) {
4711                         dev_err(&hdev->pdev->dev,
4712                                 "Configure rss tc size failed, invalid TC_SIZE = %u\n",
4713                                 rss_size);
4714                         return -EINVAL;
4715                 }
4716
4717                 roundup_size = roundup_pow_of_two(rss_size);
4718                 roundup_size = ilog2(roundup_size);
4719
4720                 tc_valid[i] = 1;
4721                 tc_size[i] = roundup_size;
4722                 tc_offset[i] = tc_info->tqp_offset[i];
4723         }
4724
4725         return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid,
4726                                           tc_size);
4727 }
4728
4729 int hclge_rss_init_hw(struct hclge_dev *hdev)
4730 {
4731         u16 *rss_indir = hdev->rss_cfg.rss_indirection_tbl;
4732         u8 *key = hdev->rss_cfg.rss_hash_key;
4733         u8 hfunc = hdev->rss_cfg.rss_algo;
4734         int ret;
4735
4736         ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw,
4737                                              rss_indir);
4738         if (ret)
4739                 return ret;
4740
4741         ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, hfunc, key);
4742         if (ret)
4743                 return ret;
4744
4745         ret = hclge_comm_set_rss_input_tuple(&hdev->vport[0].nic,
4746                                              &hdev->hw.hw, true,
4747                                              &hdev->rss_cfg);
4748         if (ret)
4749                 return ret;
4750
4751         return hclge_init_rss_tc_mode(hdev);
4752 }
4753
4754 int hclge_bind_ring_with_vector(struct hclge_vport *vport,
4755                                 int vector_id, bool en,
4756                                 struct hnae3_ring_chain_node *ring_chain)
4757 {
4758         struct hclge_dev *hdev = vport->back;
4759         struct hnae3_ring_chain_node *node;
4760         struct hclge_desc desc;
4761         struct hclge_ctrl_vector_chain_cmd *req =
4762                 (struct hclge_ctrl_vector_chain_cmd *)desc.data;
4763         enum hclge_comm_cmd_status status;
4764         enum hclge_opcode_type op;
4765         u16 tqp_type_and_id;
4766         int i;
4767
4768         op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
4769         hclge_cmd_setup_basic_desc(&desc, op, false);
4770         req->int_vector_id_l = hnae3_get_field(vector_id,
4771                                                HCLGE_VECTOR_ID_L_M,
4772                                                HCLGE_VECTOR_ID_L_S);
4773         req->int_vector_id_h = hnae3_get_field(vector_id,
4774                                                HCLGE_VECTOR_ID_H_M,
4775                                                HCLGE_VECTOR_ID_H_S);
4776
4777         i = 0;
4778         for (node = ring_chain; node; node = node->next) {
4779                 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
4780                 hnae3_set_field(tqp_type_and_id,  HCLGE_INT_TYPE_M,
4781                                 HCLGE_INT_TYPE_S,
4782                                 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B));
4783                 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
4784                                 HCLGE_TQP_ID_S, node->tqp_index);
4785                 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
4786                                 HCLGE_INT_GL_IDX_S,
4787                                 hnae3_get_field(node->int_gl_idx,
4788                                                 HNAE3_RING_GL_IDX_M,
4789                                                 HNAE3_RING_GL_IDX_S));
4790                 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
4791                 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
4792                         req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
4793                         req->vfid = vport->vport_id;
4794
4795                         status = hclge_cmd_send(&hdev->hw, &desc, 1);
4796                         if (status) {
4797                                 dev_err(&hdev->pdev->dev,
4798                                         "Map TQP fail, status is %d.\n",
4799                                         status);
4800                                 return -EIO;
4801                         }
4802                         i = 0;
4803
4804                         hclge_cmd_setup_basic_desc(&desc,
4805                                                    op,
4806                                                    false);
4807                         req->int_vector_id_l =
4808                                 hnae3_get_field(vector_id,
4809                                                 HCLGE_VECTOR_ID_L_M,
4810                                                 HCLGE_VECTOR_ID_L_S);
4811                         req->int_vector_id_h =
4812                                 hnae3_get_field(vector_id,
4813                                                 HCLGE_VECTOR_ID_H_M,
4814                                                 HCLGE_VECTOR_ID_H_S);
4815                 }
4816         }
4817
4818         if (i > 0) {
4819                 req->int_cause_num = i;
4820                 req->vfid = vport->vport_id;
4821                 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4822                 if (status) {
4823                         dev_err(&hdev->pdev->dev,
4824                                 "Map TQP fail, status is %d.\n", status);
4825                         return -EIO;
4826                 }
4827         }
4828
4829         return 0;
4830 }
4831
4832 static int hclge_map_ring_to_vector(struct hnae3_handle *handle, int vector,
4833                                     struct hnae3_ring_chain_node *ring_chain)
4834 {
4835         struct hclge_vport *vport = hclge_get_vport(handle);
4836         struct hclge_dev *hdev = vport->back;
4837         int vector_id;
4838
4839         vector_id = hclge_get_vector_index(hdev, vector);
4840         if (vector_id < 0) {
4841                 dev_err(&hdev->pdev->dev,
4842                         "failed to get vector index. vector=%d\n", vector);
4843                 return vector_id;
4844         }
4845
4846         return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
4847 }
4848
4849 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, int vector,
4850                                        struct hnae3_ring_chain_node *ring_chain)
4851 {
4852         struct hclge_vport *vport = hclge_get_vport(handle);
4853         struct hclge_dev *hdev = vport->back;
4854         int vector_id, ret;
4855
4856         if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
4857                 return 0;
4858
4859         vector_id = hclge_get_vector_index(hdev, vector);
4860         if (vector_id < 0) {
4861                 dev_err(&handle->pdev->dev,
4862                         "Get vector index fail. ret =%d\n", vector_id);
4863                 return vector_id;
4864         }
4865
4866         ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
4867         if (ret)
4868                 dev_err(&handle->pdev->dev,
4869                         "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
4870                         vector_id, ret);
4871
4872         return ret;
4873 }
4874
4875 static int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, u8 vf_id,
4876                                       bool en_uc, bool en_mc, bool en_bc)
4877 {
4878         struct hclge_vport *vport = &hdev->vport[vf_id];
4879         struct hnae3_handle *handle = &vport->nic;
4880         struct hclge_promisc_cfg_cmd *req;
4881         struct hclge_desc desc;
4882         bool uc_tx_en = en_uc;
4883         u8 promisc_cfg = 0;
4884         int ret;
4885
4886         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
4887
4888         req = (struct hclge_promisc_cfg_cmd *)desc.data;
4889         req->vf_id = vf_id;
4890
4891         if (test_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->priv_flags))
4892                 uc_tx_en = false;
4893
4894         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_RX_EN, en_uc ? 1 : 0);
4895         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_RX_EN, en_mc ? 1 : 0);
4896         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_RX_EN, en_bc ? 1 : 0);
4897         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_TX_EN, uc_tx_en ? 1 : 0);
4898         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_TX_EN, en_mc ? 1 : 0);
4899         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_TX_EN, en_bc ? 1 : 0);
4900         req->extend_promisc = promisc_cfg;
4901
4902         /* to be compatible with DEVICE_VERSION_V1/2 */
4903         promisc_cfg = 0;
4904         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_UC, en_uc ? 1 : 0);
4905         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_MC, en_mc ? 1 : 0);
4906         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_BC, en_bc ? 1 : 0);
4907         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_TX_EN, 1);
4908         hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_RX_EN, 1);
4909         req->promisc = promisc_cfg;
4910
4911         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4912         if (ret)
4913                 dev_err(&hdev->pdev->dev,
4914                         "failed to set vport %u promisc mode, ret = %d.\n",
4915                         vf_id, ret);
4916
4917         return ret;
4918 }
4919
4920 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc,
4921                                  bool en_mc_pmc, bool en_bc_pmc)
4922 {
4923         return hclge_cmd_set_promisc_mode(vport->back, vport->vport_id,
4924                                           en_uc_pmc, en_mc_pmc, en_bc_pmc);
4925 }
4926
4927 static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
4928                                   bool en_mc_pmc)
4929 {
4930         struct hclge_vport *vport = hclge_get_vport(handle);
4931         struct hclge_dev *hdev = vport->back;
4932         bool en_bc_pmc = true;
4933
4934         /* For device whose version below V2, if broadcast promisc enabled,
4935          * vlan filter is always bypassed. So broadcast promisc should be
4936          * disabled until user enable promisc mode
4937          */
4938         if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
4939                 en_bc_pmc = handle->netdev_flags & HNAE3_BPE ? true : false;
4940
4941         return hclge_set_vport_promisc_mode(vport, en_uc_pmc, en_mc_pmc,
4942                                             en_bc_pmc);
4943 }
4944
4945 static void hclge_request_update_promisc_mode(struct hnae3_handle *handle)
4946 {
4947         struct hclge_vport *vport = hclge_get_vport(handle);
4948
4949         set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
4950 }
4951
4952 static void hclge_sync_fd_state(struct hclge_dev *hdev)
4953 {
4954         if (hlist_empty(&hdev->fd_rule_list))
4955                 hdev->fd_active_type = HCLGE_FD_RULE_NONE;
4956 }
4957
4958 static void hclge_fd_inc_rule_cnt(struct hclge_dev *hdev, u16 location)
4959 {
4960         if (!test_bit(location, hdev->fd_bmap)) {
4961                 set_bit(location, hdev->fd_bmap);
4962                 hdev->hclge_fd_rule_num++;
4963         }
4964 }
4965
4966 static void hclge_fd_dec_rule_cnt(struct hclge_dev *hdev, u16 location)
4967 {
4968         if (test_bit(location, hdev->fd_bmap)) {
4969                 clear_bit(location, hdev->fd_bmap);
4970                 hdev->hclge_fd_rule_num--;
4971         }
4972 }
4973
4974 static void hclge_fd_free_node(struct hclge_dev *hdev,
4975                                struct hclge_fd_rule *rule)
4976 {
4977         hlist_del(&rule->rule_node);
4978         kfree(rule);
4979         hclge_sync_fd_state(hdev);
4980 }
4981
4982 static void hclge_update_fd_rule_node(struct hclge_dev *hdev,
4983                                       struct hclge_fd_rule *old_rule,
4984                                       struct hclge_fd_rule *new_rule,
4985                                       enum HCLGE_FD_NODE_STATE state)
4986 {
4987         switch (state) {
4988         case HCLGE_FD_TO_ADD:
4989         case HCLGE_FD_ACTIVE:
4990                 /* 1) if the new state is TO_ADD, just replace the old rule
4991                  * with the same location, no matter its state, because the
4992                  * new rule will be configured to the hardware.
4993                  * 2) if the new state is ACTIVE, it means the new rule
4994                  * has been configured to the hardware, so just replace
4995                  * the old rule node with the same location.
4996                  * 3) for it doesn't add a new node to the list, so it's
4997                  * unnecessary to update the rule number and fd_bmap.
4998                  */
4999                 new_rule->rule_node.next = old_rule->rule_node.next;
5000                 new_rule->rule_node.pprev = old_rule->rule_node.pprev;
5001                 memcpy(old_rule, new_rule, sizeof(*old_rule));
5002                 kfree(new_rule);
5003                 break;
5004         case HCLGE_FD_DELETED:
5005                 hclge_fd_dec_rule_cnt(hdev, old_rule->location);
5006                 hclge_fd_free_node(hdev, old_rule);
5007                 break;
5008         case HCLGE_FD_TO_DEL:
5009                 /* if new request is TO_DEL, and old rule is existent
5010                  * 1) the state of old rule is TO_DEL, we need do nothing,
5011                  * because we delete rule by location, other rule content
5012                  * is unncessary.
5013                  * 2) the state of old rule is ACTIVE, we need to change its
5014                  * state to TO_DEL, so the rule will be deleted when periodic
5015                  * task being scheduled.
5016                  * 3) the state of old rule is TO_ADD, it means the rule hasn't
5017                  * been added to hardware, so we just delete the rule node from
5018                  * fd_rule_list directly.
5019                  */
5020                 if (old_rule->state == HCLGE_FD_TO_ADD) {
5021                         hclge_fd_dec_rule_cnt(hdev, old_rule->location);
5022                         hclge_fd_free_node(hdev, old_rule);
5023                         return;
5024                 }
5025                 old_rule->state = HCLGE_FD_TO_DEL;
5026                 break;
5027         }
5028 }
5029
5030 static struct hclge_fd_rule *hclge_find_fd_rule(struct hlist_head *hlist,
5031                                                 u16 location,
5032                                                 struct hclge_fd_rule **parent)
5033 {
5034         struct hclge_fd_rule *rule;
5035         struct hlist_node *node;
5036
5037         hlist_for_each_entry_safe(rule, node, hlist, rule_node) {
5038                 if (rule->location == location)
5039                         return rule;
5040                 else if (rule->location > location)
5041                         return NULL;
5042                 /* record the parent node, use to keep the nodes in fd_rule_list
5043                  * in ascend order.
5044                  */
5045                 *parent = rule;
5046         }
5047
5048         return NULL;
5049 }
5050
5051 /* insert fd rule node in ascend order according to rule->location */
5052 static void hclge_fd_insert_rule_node(struct hlist_head *hlist,
5053                                       struct hclge_fd_rule *rule,
5054                                       struct hclge_fd_rule *parent)
5055 {
5056         INIT_HLIST_NODE(&rule->rule_node);
5057
5058         if (parent)
5059                 hlist_add_behind(&rule->rule_node, &parent->rule_node);
5060         else
5061                 hlist_add_head(&rule->rule_node, hlist);
5062 }
5063
5064 static int hclge_fd_set_user_def_cmd(struct hclge_dev *hdev,
5065                                      struct hclge_fd_user_def_cfg *cfg)
5066 {
5067         struct hclge_fd_user_def_cfg_cmd *req;
5068         struct hclge_desc desc;
5069         u16 data = 0;
5070         int ret;
5071
5072         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_USER_DEF_OP, false);
5073
5074         req = (struct hclge_fd_user_def_cfg_cmd *)desc.data;
5075
5076         hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[0].ref_cnt > 0);
5077         hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M,
5078                         HCLGE_FD_USER_DEF_OFT_S, cfg[0].offset);
5079         req->ol2_cfg = cpu_to_le16(data);
5080
5081         data = 0;
5082         hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[1].ref_cnt > 0);
5083         hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M,
5084                         HCLGE_FD_USER_DEF_OFT_S, cfg[1].offset);
5085         req->ol3_cfg = cpu_to_le16(data);
5086
5087         data = 0;
5088         hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[2].ref_cnt > 0);
5089         hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M,
5090                         HCLGE_FD_USER_DEF_OFT_S, cfg[2].offset);
5091         req->ol4_cfg = cpu_to_le16(data);
5092
5093         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5094         if (ret)
5095                 dev_err(&hdev->pdev->dev,
5096                         "failed to set fd user def data, ret= %d\n", ret);
5097         return ret;
5098 }
5099
5100 static void hclge_sync_fd_user_def_cfg(struct hclge_dev *hdev, bool locked)
5101 {
5102         int ret;
5103
5104         if (!test_and_clear_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state))
5105                 return;
5106
5107         if (!locked)
5108                 spin_lock_bh(&hdev->fd_rule_lock);
5109
5110         ret = hclge_fd_set_user_def_cmd(hdev, hdev->fd_cfg.user_def_cfg);
5111         if (ret)
5112                 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state);
5113
5114         if (!locked)
5115                 spin_unlock_bh(&hdev->fd_rule_lock);
5116 }
5117
5118 static int hclge_fd_check_user_def_refcnt(struct hclge_dev *hdev,
5119                                           struct hclge_fd_rule *rule)
5120 {
5121         struct hlist_head *hlist = &hdev->fd_rule_list;
5122         struct hclge_fd_rule *fd_rule, *parent = NULL;
5123         struct hclge_fd_user_def_info *info, *old_info;
5124         struct hclge_fd_user_def_cfg *cfg;
5125
5126         if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE ||
5127             rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE)
5128                 return 0;
5129
5130         /* for valid layer is start from 1, so need minus 1 to get the cfg */
5131         cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1];
5132         info = &rule->ep.user_def;
5133
5134         if (!cfg->ref_cnt || cfg->offset == info->offset)
5135                 return 0;
5136
5137         if (cfg->ref_cnt > 1)
5138                 goto error;
5139
5140         fd_rule = hclge_find_fd_rule(hlist, rule->location, &parent);
5141         if (fd_rule) {
5142                 old_info = &fd_rule->ep.user_def;
5143                 if (info->layer == old_info->layer)
5144                         return 0;
5145         }
5146
5147 error:
5148         dev_err(&hdev->pdev->dev,
5149                 "No available offset for layer%d fd rule, each layer only support one user def offset.\n",
5150                 info->layer + 1);
5151         return -ENOSPC;
5152 }
5153
5154 static void hclge_fd_inc_user_def_refcnt(struct hclge_dev *hdev,
5155                                          struct hclge_fd_rule *rule)
5156 {
5157         struct hclge_fd_user_def_cfg *cfg;
5158
5159         if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE ||
5160             rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE)
5161                 return;
5162
5163         cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1];
5164         if (!cfg->ref_cnt) {
5165                 cfg->offset = rule->ep.user_def.offset;
5166                 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state);
5167         }
5168         cfg->ref_cnt++;
5169 }
5170
5171 static void hclge_fd_dec_user_def_refcnt(struct hclge_dev *hdev,
5172                                          struct hclge_fd_rule *rule)
5173 {
5174         struct hclge_fd_user_def_cfg *cfg;
5175
5176         if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE ||
5177             rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE)
5178                 return;
5179
5180         cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1];
5181         if (!cfg->ref_cnt)
5182                 return;
5183
5184         cfg->ref_cnt--;
5185         if (!cfg->ref_cnt) {
5186                 cfg->offset = 0;
5187                 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state);
5188         }
5189 }
5190
5191 static void hclge_update_fd_list(struct hclge_dev *hdev,
5192                                  enum HCLGE_FD_NODE_STATE state, u16 location,
5193                                  struct hclge_fd_rule *new_rule)
5194 {
5195         struct hlist_head *hlist = &hdev->fd_rule_list;
5196         struct hclge_fd_rule *fd_rule, *parent = NULL;
5197
5198         fd_rule = hclge_find_fd_rule(hlist, location, &parent);
5199         if (fd_rule) {
5200                 hclge_fd_dec_user_def_refcnt(hdev, fd_rule);
5201                 if (state == HCLGE_FD_ACTIVE)
5202                         hclge_fd_inc_user_def_refcnt(hdev, new_rule);
5203                 hclge_sync_fd_user_def_cfg(hdev, true);
5204
5205                 hclge_update_fd_rule_node(hdev, fd_rule, new_rule, state);
5206                 return;
5207         }
5208
5209         /* it's unlikely to fail here, because we have checked the rule
5210          * exist before.
5211          */
5212         if (unlikely(state == HCLGE_FD_TO_DEL || state == HCLGE_FD_DELETED)) {
5213                 dev_warn(&hdev->pdev->dev,
5214                          "failed to delete fd rule %u, it's inexistent\n",
5215                          location);
5216                 return;
5217         }
5218
5219         hclge_fd_inc_user_def_refcnt(hdev, new_rule);
5220         hclge_sync_fd_user_def_cfg(hdev, true);
5221
5222         hclge_fd_insert_rule_node(hlist, new_rule, parent);
5223         hclge_fd_inc_rule_cnt(hdev, new_rule->location);
5224
5225         if (state == HCLGE_FD_TO_ADD) {
5226                 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state);
5227                 hclge_task_schedule(hdev, 0);
5228         }
5229 }
5230
5231 static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode)
5232 {
5233         struct hclge_get_fd_mode_cmd *req;
5234         struct hclge_desc desc;
5235         int ret;
5236
5237         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_MODE_CTRL, true);
5238
5239         req = (struct hclge_get_fd_mode_cmd *)desc.data;
5240
5241         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5242         if (ret) {
5243                 dev_err(&hdev->pdev->dev, "get fd mode fail, ret=%d\n", ret);
5244                 return ret;
5245         }
5246
5247         *fd_mode = req->mode;
5248
5249         return ret;
5250 }
5251
5252 static int hclge_get_fd_allocation(struct hclge_dev *hdev,
5253                                    u32 *stage1_entry_num,
5254                                    u32 *stage2_entry_num,
5255                                    u16 *stage1_counter_num,
5256                                    u16 *stage2_counter_num)
5257 {
5258         struct hclge_get_fd_allocation_cmd *req;
5259         struct hclge_desc desc;
5260         int ret;
5261
5262         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_GET_ALLOCATION, true);
5263
5264         req = (struct hclge_get_fd_allocation_cmd *)desc.data;
5265
5266         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5267         if (ret) {
5268                 dev_err(&hdev->pdev->dev, "query fd allocation fail, ret=%d\n",
5269                         ret);
5270                 return ret;
5271         }
5272
5273         *stage1_entry_num = le32_to_cpu(req->stage1_entry_num);
5274         *stage2_entry_num = le32_to_cpu(req->stage2_entry_num);
5275         *stage1_counter_num = le16_to_cpu(req->stage1_counter_num);
5276         *stage2_counter_num = le16_to_cpu(req->stage2_counter_num);
5277
5278         return ret;
5279 }
5280
5281 static int hclge_set_fd_key_config(struct hclge_dev *hdev,
5282                                    enum HCLGE_FD_STAGE stage_num)
5283 {
5284         struct hclge_set_fd_key_config_cmd *req;
5285         struct hclge_fd_key_cfg *stage;
5286         struct hclge_desc desc;
5287         int ret;
5288
5289         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_KEY_CONFIG, false);
5290
5291         req = (struct hclge_set_fd_key_config_cmd *)desc.data;
5292         stage = &hdev->fd_cfg.key_cfg[stage_num];
5293         req->stage = stage_num;
5294         req->key_select = stage->key_sel;
5295         req->inner_sipv6_word_en = stage->inner_sipv6_word_en;
5296         req->inner_dipv6_word_en = stage->inner_dipv6_word_en;
5297         req->outer_sipv6_word_en = stage->outer_sipv6_word_en;
5298         req->outer_dipv6_word_en = stage->outer_dipv6_word_en;
5299         req->tuple_mask = cpu_to_le32(~stage->tuple_active);
5300         req->meta_data_mask = cpu_to_le32(~stage->meta_data_active);
5301
5302         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5303         if (ret)
5304                 dev_err(&hdev->pdev->dev, "set fd key fail, ret=%d\n", ret);
5305
5306         return ret;
5307 }
5308
5309 static void hclge_fd_disable_user_def(struct hclge_dev *hdev)
5310 {
5311         struct hclge_fd_user_def_cfg *cfg = hdev->fd_cfg.user_def_cfg;
5312
5313         spin_lock_bh(&hdev->fd_rule_lock);
5314         memset(cfg, 0, sizeof(hdev->fd_cfg.user_def_cfg));
5315         spin_unlock_bh(&hdev->fd_rule_lock);
5316
5317         hclge_fd_set_user_def_cmd(hdev, cfg);
5318 }
5319
5320 static int hclge_init_fd_config(struct hclge_dev *hdev)
5321 {
5322 #define LOW_2_WORDS             0x03
5323         struct hclge_fd_key_cfg *key_cfg;
5324         int ret;
5325
5326         if (!hnae3_dev_fd_supported(hdev))
5327                 return 0;
5328
5329         ret = hclge_get_fd_mode(hdev, &hdev->fd_cfg.fd_mode);
5330         if (ret)
5331                 return ret;
5332
5333         switch (hdev->fd_cfg.fd_mode) {
5334         case HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1:
5335                 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH;
5336                 break;
5337         case HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1:
5338                 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH / 2;
5339                 break;
5340         default:
5341                 dev_err(&hdev->pdev->dev,
5342                         "Unsupported flow director mode %u\n",
5343                         hdev->fd_cfg.fd_mode);
5344                 return -EOPNOTSUPP;
5345         }
5346
5347         key_cfg = &hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1];
5348         key_cfg->key_sel = HCLGE_FD_KEY_BASE_ON_TUPLE;
5349         key_cfg->inner_sipv6_word_en = LOW_2_WORDS;
5350         key_cfg->inner_dipv6_word_en = LOW_2_WORDS;
5351         key_cfg->outer_sipv6_word_en = 0;
5352         key_cfg->outer_dipv6_word_en = 0;
5353
5354         key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) |
5355                                 BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) |
5356                                 BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) |
5357                                 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
5358
5359         /* If use max 400bit key, we can support tuples for ether type */
5360         if (hdev->fd_cfg.fd_mode == HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) {
5361                 key_cfg->tuple_active |=
5362                                 BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC);
5363                 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
5364                         key_cfg->tuple_active |= HCLGE_FD_TUPLE_USER_DEF_TUPLES;
5365         }
5366
5367         /* roce_type is used to filter roce frames
5368          * dst_vport is used to specify the rule
5369          */
5370         key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT);
5371
5372         ret = hclge_get_fd_allocation(hdev,
5373                                       &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1],
5374                                       &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2],
5375                                       &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1],
5376                                       &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]);
5377         if (ret)
5378                 return ret;
5379
5380         return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1);
5381 }
5382
5383 static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x,
5384                                 int loc, u8 *key, bool is_add)
5385 {
5386         struct hclge_fd_tcam_config_1_cmd *req1;
5387         struct hclge_fd_tcam_config_2_cmd *req2;
5388         struct hclge_fd_tcam_config_3_cmd *req3;
5389         struct hclge_desc desc[3];
5390         int ret;
5391
5392         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false);
5393         desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
5394         hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false);
5395         desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
5396         hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false);
5397
5398         req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data;
5399         req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data;
5400         req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data;
5401
5402         req1->stage = stage;
5403         req1->xy_sel = sel_x ? 1 : 0;
5404         hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0);
5405         req1->index = cpu_to_le32(loc);
5406         req1->entry_vld = sel_x ? is_add : 0;
5407
5408         if (key) {
5409                 memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data));
5410                 memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)],
5411                        sizeof(req2->tcam_data));
5412                 memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) +
5413                        sizeof(req2->tcam_data)], sizeof(req3->tcam_data));
5414         }
5415
5416         ret = hclge_cmd_send(&hdev->hw, desc, 3);
5417         if (ret)
5418                 dev_err(&hdev->pdev->dev,
5419                         "config tcam key fail, ret=%d\n",
5420                         ret);
5421
5422         return ret;
5423 }
5424
5425 static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc,
5426                               struct hclge_fd_ad_data *action)
5427 {
5428         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
5429         struct hclge_fd_ad_config_cmd *req;
5430         struct hclge_desc desc;
5431         u64 ad_data = 0;
5432         int ret;
5433
5434         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false);
5435
5436         req = (struct hclge_fd_ad_config_cmd *)desc.data;
5437         req->index = cpu_to_le32(loc);
5438         req->stage = stage;
5439
5440         hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B,
5441                       action->write_rule_id_to_bd);
5442         hnae3_set_field(ad_data, HCLGE_FD_AD_RULE_ID_M, HCLGE_FD_AD_RULE_ID_S,
5443                         action->rule_id);
5444         if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps)) {
5445                 hnae3_set_bit(ad_data, HCLGE_FD_AD_TC_OVRD_B,
5446                               action->override_tc);
5447                 hnae3_set_field(ad_data, HCLGE_FD_AD_TC_SIZE_M,
5448                                 HCLGE_FD_AD_TC_SIZE_S, (u32)action->tc_size);
5449         }
5450         ad_data <<= 32;
5451         hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet);
5452         hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B,
5453                       action->forward_to_direct_queue);
5454         hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S,
5455                         action->queue_id);
5456         hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter);
5457         hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M,
5458                         HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id);
5459         hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage);
5460         hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S,
5461                         action->counter_id);
5462
5463         req->ad_data = cpu_to_le64(ad_data);
5464         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5465         if (ret)
5466                 dev_err(&hdev->pdev->dev, "fd ad config fail, ret=%d\n", ret);
5467
5468         return ret;
5469 }
5470
5471 static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y,
5472                                    struct hclge_fd_rule *rule)
5473 {
5474         int offset, moffset, ip_offset;
5475         enum HCLGE_FD_KEY_OPT key_opt;
5476         u16 tmp_x_s, tmp_y_s;
5477         u32 tmp_x_l, tmp_y_l;
5478         u8 *p = (u8 *)rule;
5479         int i;
5480
5481         if (rule->unused_tuple & BIT(tuple_bit))
5482                 return true;
5483
5484         key_opt = tuple_key_info[tuple_bit].key_opt;
5485         offset = tuple_key_info[tuple_bit].offset;
5486         moffset = tuple_key_info[tuple_bit].moffset;
5487
5488         switch (key_opt) {
5489         case KEY_OPT_U8:
5490                 calc_x(*key_x, p[offset], p[moffset]);
5491                 calc_y(*key_y, p[offset], p[moffset]);
5492
5493                 return true;
5494         case KEY_OPT_LE16:
5495                 calc_x(tmp_x_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset]));
5496                 calc_y(tmp_y_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset]));
5497                 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
5498                 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
5499
5500                 return true;
5501         case KEY_OPT_LE32:
5502                 calc_x(tmp_x_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset]));
5503                 calc_y(tmp_y_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset]));
5504                 *(__le32 *)key_x = cpu_to_le32(tmp_x_l);
5505                 *(__le32 *)key_y = cpu_to_le32(tmp_y_l);
5506
5507                 return true;
5508         case KEY_OPT_MAC:
5509                 for (i = 0; i < ETH_ALEN; i++) {
5510                         calc_x(key_x[ETH_ALEN - 1 - i], p[offset + i],
5511                                p[moffset + i]);
5512                         calc_y(key_y[ETH_ALEN - 1 - i], p[offset + i],
5513                                p[moffset + i]);
5514                 }
5515
5516                 return true;
5517         case KEY_OPT_IP:
5518                 ip_offset = IPV4_INDEX * sizeof(u32);
5519                 calc_x(tmp_x_l, *(u32 *)(&p[offset + ip_offset]),
5520                        *(u32 *)(&p[moffset + ip_offset]));
5521                 calc_y(tmp_y_l, *(u32 *)(&p[offset + ip_offset]),
5522                        *(u32 *)(&p[moffset + ip_offset]));
5523                 *(__le32 *)key_x = cpu_to_le32(tmp_x_l);
5524                 *(__le32 *)key_y = cpu_to_le32(tmp_y_l);
5525
5526                 return true;
5527         default:
5528                 return false;
5529         }
5530 }
5531
5532 static u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id,
5533                                  u8 vf_id, u8 network_port_id)
5534 {
5535         u32 port_number = 0;
5536
5537         if (port_type == HOST_PORT) {
5538                 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S,
5539                                 pf_id);
5540                 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S,
5541                                 vf_id);
5542                 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT);
5543         } else {
5544                 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M,
5545                                 HCLGE_NETWORK_PORT_ID_S, network_port_id);
5546                 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT);
5547         }
5548
5549         return port_number;
5550 }
5551
5552 static void hclge_fd_convert_meta_data(struct hclge_fd_key_cfg *key_cfg,
5553                                        __le32 *key_x, __le32 *key_y,
5554                                        struct hclge_fd_rule *rule)
5555 {
5556         u32 tuple_bit, meta_data = 0, tmp_x, tmp_y, port_number;
5557         u8 cur_pos = 0, tuple_size, shift_bits;
5558         unsigned int i;
5559
5560         for (i = 0; i < MAX_META_DATA; i++) {
5561                 tuple_size = meta_data_key_info[i].key_length;
5562                 tuple_bit = key_cfg->meta_data_active & BIT(i);
5563
5564                 switch (tuple_bit) {
5565                 case BIT(ROCE_TYPE):
5566                         hnae3_set_bit(meta_data, cur_pos, NIC_PACKET);
5567                         cur_pos += tuple_size;
5568                         break;
5569                 case BIT(DST_VPORT):
5570                         port_number = hclge_get_port_number(HOST_PORT, 0,
5571                                                             rule->vf_id, 0);
5572                         hnae3_set_field(meta_data,
5573                                         GENMASK(cur_pos + tuple_size, cur_pos),
5574                                         cur_pos, port_number);
5575                         cur_pos += tuple_size;
5576                         break;
5577                 default:
5578                         break;
5579                 }
5580         }
5581
5582         calc_x(tmp_x, meta_data, 0xFFFFFFFF);
5583         calc_y(tmp_y, meta_data, 0xFFFFFFFF);
5584         shift_bits = sizeof(meta_data) * 8 - cur_pos;
5585
5586         *key_x = cpu_to_le32(tmp_x << shift_bits);
5587         *key_y = cpu_to_le32(tmp_y << shift_bits);
5588 }
5589
5590 /* A complete key is combined with meta data key and tuple key.
5591  * Meta data key is stored at the MSB region, and tuple key is stored at
5592  * the LSB region, unused bits will be filled 0.
5593  */
5594 static int hclge_config_key(struct hclge_dev *hdev, u8 stage,
5595                             struct hclge_fd_rule *rule)
5596 {
5597         struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage];
5598         u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES];
5599         u8 *cur_key_x, *cur_key_y;
5600         u8 meta_data_region;
5601         u8 tuple_size;
5602         int ret;
5603         u32 i;
5604
5605         memset(key_x, 0, sizeof(key_x));
5606         memset(key_y, 0, sizeof(key_y));
5607         cur_key_x = key_x;
5608         cur_key_y = key_y;
5609
5610         for (i = 0; i < MAX_TUPLE; i++) {
5611                 bool tuple_valid;
5612
5613                 tuple_size = tuple_key_info[i].key_length / 8;
5614                 if (!(key_cfg->tuple_active & BIT(i)))
5615                         continue;
5616
5617                 tuple_valid = hclge_fd_convert_tuple(i, cur_key_x,
5618                                                      cur_key_y, rule);
5619                 if (tuple_valid) {
5620                         cur_key_x += tuple_size;
5621                         cur_key_y += tuple_size;
5622                 }
5623         }
5624
5625         meta_data_region = hdev->fd_cfg.max_key_length / 8 -
5626                         MAX_META_DATA_LENGTH / 8;
5627
5628         hclge_fd_convert_meta_data(key_cfg,
5629                                    (__le32 *)(key_x + meta_data_region),
5630                                    (__le32 *)(key_y + meta_data_region),
5631                                    rule);
5632
5633         ret = hclge_fd_tcam_config(hdev, stage, false, rule->location, key_y,
5634                                    true);
5635         if (ret) {
5636                 dev_err(&hdev->pdev->dev,
5637                         "fd key_y config fail, loc=%u, ret=%d\n",
5638                         rule->queue_id, ret);
5639                 return ret;
5640         }
5641
5642         ret = hclge_fd_tcam_config(hdev, stage, true, rule->location, key_x,
5643                                    true);
5644         if (ret)
5645                 dev_err(&hdev->pdev->dev,
5646                         "fd key_x config fail, loc=%u, ret=%d\n",
5647                         rule->queue_id, ret);
5648         return ret;
5649 }
5650
5651 static int hclge_config_action(struct hclge_dev *hdev, u8 stage,
5652                                struct hclge_fd_rule *rule)
5653 {
5654         struct hclge_vport *vport = hdev->vport;
5655         struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5656         struct hclge_fd_ad_data ad_data;
5657
5658         memset(&ad_data, 0, sizeof(struct hclge_fd_ad_data));
5659         ad_data.ad_id = rule->location;
5660
5661         if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) {
5662                 ad_data.drop_packet = true;
5663         } else if (rule->action == HCLGE_FD_ACTION_SELECT_TC) {
5664                 ad_data.override_tc = true;
5665                 ad_data.queue_id =
5666                         kinfo->tc_info.tqp_offset[rule->cls_flower.tc];
5667                 ad_data.tc_size =
5668                         ilog2(kinfo->tc_info.tqp_count[rule->cls_flower.tc]);
5669         } else {
5670                 ad_data.forward_to_direct_queue = true;
5671                 ad_data.queue_id = rule->queue_id;
5672         }
5673
5674         if (hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]) {
5675                 ad_data.use_counter = true;
5676                 ad_data.counter_id = rule->vf_id %
5677                                      hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1];
5678         } else {
5679                 ad_data.use_counter = false;
5680                 ad_data.counter_id = 0;
5681         }
5682
5683         ad_data.use_next_stage = false;
5684         ad_data.next_input_key = 0;
5685
5686         ad_data.write_rule_id_to_bd = true;
5687         ad_data.rule_id = rule->location;
5688
5689         return hclge_fd_ad_config(hdev, stage, ad_data.ad_id, &ad_data);
5690 }
5691
5692 static int hclge_fd_check_tcpip4_tuple(struct ethtool_tcpip4_spec *spec,
5693                                        u32 *unused_tuple)
5694 {
5695         if (!spec || !unused_tuple)
5696                 return -EINVAL;
5697
5698         *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC);
5699
5700         if (!spec->ip4src)
5701                 *unused_tuple |= BIT(INNER_SRC_IP);
5702
5703         if (!spec->ip4dst)
5704                 *unused_tuple |= BIT(INNER_DST_IP);
5705
5706         if (!spec->psrc)
5707                 *unused_tuple |= BIT(INNER_SRC_PORT);
5708
5709         if (!spec->pdst)
5710                 *unused_tuple |= BIT(INNER_DST_PORT);
5711
5712         if (!spec->tos)
5713                 *unused_tuple |= BIT(INNER_IP_TOS);
5714
5715         return 0;
5716 }
5717
5718 static int hclge_fd_check_ip4_tuple(struct ethtool_usrip4_spec *spec,
5719                                     u32 *unused_tuple)
5720 {
5721         if (!spec || !unused_tuple)
5722                 return -EINVAL;
5723
5724         *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
5725                 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
5726
5727         if (!spec->ip4src)
5728                 *unused_tuple |= BIT(INNER_SRC_IP);
5729
5730         if (!spec->ip4dst)
5731                 *unused_tuple |= BIT(INNER_DST_IP);
5732
5733         if (!spec->tos)
5734                 *unused_tuple |= BIT(INNER_IP_TOS);
5735
5736         if (!spec->proto)
5737                 *unused_tuple |= BIT(INNER_IP_PROTO);
5738
5739         if (spec->l4_4_bytes)
5740                 return -EOPNOTSUPP;
5741
5742         if (spec->ip_ver != ETH_RX_NFC_IP4)
5743                 return -EOPNOTSUPP;
5744
5745         return 0;
5746 }
5747
5748 static int hclge_fd_check_tcpip6_tuple(struct ethtool_tcpip6_spec *spec,
5749                                        u32 *unused_tuple)
5750 {
5751         if (!spec || !unused_tuple)
5752                 return -EINVAL;
5753
5754         *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC);
5755
5756         /* check whether src/dst ip address used */
5757         if (ipv6_addr_any((struct in6_addr *)spec->ip6src))
5758                 *unused_tuple |= BIT(INNER_SRC_IP);
5759
5760         if (ipv6_addr_any((struct in6_addr *)spec->ip6dst))
5761                 *unused_tuple |= BIT(INNER_DST_IP);
5762
5763         if (!spec->psrc)
5764                 *unused_tuple |= BIT(INNER_SRC_PORT);
5765
5766         if (!spec->pdst)
5767                 *unused_tuple |= BIT(INNER_DST_PORT);
5768
5769         if (!spec->tclass)
5770                 *unused_tuple |= BIT(INNER_IP_TOS);
5771
5772         return 0;
5773 }
5774
5775 static int hclge_fd_check_ip6_tuple(struct ethtool_usrip6_spec *spec,
5776                                     u32 *unused_tuple)
5777 {
5778         if (!spec || !unused_tuple)
5779                 return -EINVAL;
5780
5781         *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
5782                         BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
5783
5784         /* check whether src/dst ip address used */
5785         if (ipv6_addr_any((struct in6_addr *)spec->ip6src))
5786                 *unused_tuple |= BIT(INNER_SRC_IP);
5787
5788         if (ipv6_addr_any((struct in6_addr *)spec->ip6dst))
5789                 *unused_tuple |= BIT(INNER_DST_IP);
5790
5791         if (!spec->l4_proto)
5792                 *unused_tuple |= BIT(INNER_IP_PROTO);
5793
5794         if (!spec->tclass)
5795                 *unused_tuple |= BIT(INNER_IP_TOS);
5796
5797         if (spec->l4_4_bytes)
5798                 return -EOPNOTSUPP;
5799
5800         return 0;
5801 }
5802
5803 static int hclge_fd_check_ether_tuple(struct ethhdr *spec, u32 *unused_tuple)
5804 {
5805         if (!spec || !unused_tuple)
5806                 return -EINVAL;
5807
5808         *unused_tuple |= BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) |
5809                 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT) |
5810                 BIT(INNER_IP_TOS) | BIT(INNER_IP_PROTO);
5811
5812         if (is_zero_ether_addr(spec->h_source))
5813                 *unused_tuple |= BIT(INNER_SRC_MAC);
5814
5815         if (is_zero_ether_addr(spec->h_dest))
5816                 *unused_tuple |= BIT(INNER_DST_MAC);
5817
5818         if (!spec->h_proto)
5819                 *unused_tuple |= BIT(INNER_ETH_TYPE);
5820
5821         return 0;
5822 }
5823
5824 static int hclge_fd_check_ext_tuple(struct hclge_dev *hdev,
5825                                     struct ethtool_rx_flow_spec *fs,
5826                                     u32 *unused_tuple)
5827 {
5828         if (fs->flow_type & FLOW_EXT) {
5829                 if (fs->h_ext.vlan_etype) {
5830                         dev_err(&hdev->pdev->dev, "vlan-etype is not supported!\n");
5831                         return -EOPNOTSUPP;
5832                 }
5833
5834                 if (!fs->h_ext.vlan_tci)
5835                         *unused_tuple |= BIT(INNER_VLAN_TAG_FST);
5836
5837                 if (fs->m_ext.vlan_tci &&
5838                     be16_to_cpu(fs->h_ext.vlan_tci) >= VLAN_N_VID) {
5839                         dev_err(&hdev->pdev->dev,
5840                                 "failed to config vlan_tci, invalid vlan_tci: %u, max is %d.\n",
5841                                 ntohs(fs->h_ext.vlan_tci), VLAN_N_VID - 1);
5842                         return -EINVAL;
5843                 }
5844         } else {
5845                 *unused_tuple |= BIT(INNER_VLAN_TAG_FST);
5846         }
5847
5848         if (fs->flow_type & FLOW_MAC_EXT) {
5849                 if (hdev->fd_cfg.fd_mode !=
5850                     HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) {
5851                         dev_err(&hdev->pdev->dev,
5852                                 "FLOW_MAC_EXT is not supported in current fd mode!\n");
5853                         return -EOPNOTSUPP;
5854                 }
5855
5856                 if (is_zero_ether_addr(fs->h_ext.h_dest))
5857                         *unused_tuple |= BIT(INNER_DST_MAC);
5858                 else
5859                         *unused_tuple &= ~BIT(INNER_DST_MAC);
5860         }
5861
5862         return 0;
5863 }
5864
5865 static int hclge_fd_get_user_def_layer(u32 flow_type, u32 *unused_tuple,
5866                                        struct hclge_fd_user_def_info *info)
5867 {
5868         switch (flow_type) {
5869         case ETHER_FLOW:
5870                 info->layer = HCLGE_FD_USER_DEF_L2;
5871                 *unused_tuple &= ~BIT(INNER_L2_RSV);
5872                 break;
5873         case IP_USER_FLOW:
5874         case IPV6_USER_FLOW:
5875                 info->layer = HCLGE_FD_USER_DEF_L3;
5876                 *unused_tuple &= ~BIT(INNER_L3_RSV);
5877                 break;
5878         case TCP_V4_FLOW:
5879         case UDP_V4_FLOW:
5880         case TCP_V6_FLOW:
5881         case UDP_V6_FLOW:
5882                 info->layer = HCLGE_FD_USER_DEF_L4;
5883                 *unused_tuple &= ~BIT(INNER_L4_RSV);
5884                 break;
5885         default:
5886                 return -EOPNOTSUPP;
5887         }
5888
5889         return 0;
5890 }
5891
5892 static bool hclge_fd_is_user_def_all_masked(struct ethtool_rx_flow_spec *fs)
5893 {
5894         return be32_to_cpu(fs->m_ext.data[1] | fs->m_ext.data[0]) == 0;
5895 }
5896
5897 static int hclge_fd_parse_user_def_field(struct hclge_dev *hdev,
5898                                          struct ethtool_rx_flow_spec *fs,
5899                                          u32 *unused_tuple,
5900                                          struct hclge_fd_user_def_info *info)
5901 {
5902         u32 tuple_active = hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1].tuple_active;
5903         u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT);
5904         u16 data, offset, data_mask, offset_mask;
5905         int ret;
5906
5907         info->layer = HCLGE_FD_USER_DEF_NONE;
5908         *unused_tuple |= HCLGE_FD_TUPLE_USER_DEF_TUPLES;
5909
5910         if (!(fs->flow_type & FLOW_EXT) || hclge_fd_is_user_def_all_masked(fs))
5911                 return 0;
5912
5913         /* user-def data from ethtool is 64 bit value, the bit0~15 is used
5914          * for data, and bit32~47 is used for offset.
5915          */
5916         data = be32_to_cpu(fs->h_ext.data[1]) & HCLGE_FD_USER_DEF_DATA;
5917         data_mask = be32_to_cpu(fs->m_ext.data[1]) & HCLGE_FD_USER_DEF_DATA;
5918         offset = be32_to_cpu(fs->h_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET;
5919         offset_mask = be32_to_cpu(fs->m_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET;
5920
5921         if (!(tuple_active & HCLGE_FD_TUPLE_USER_DEF_TUPLES)) {
5922                 dev_err(&hdev->pdev->dev, "user-def bytes are not supported\n");
5923                 return -EOPNOTSUPP;
5924         }
5925
5926         if (offset > HCLGE_FD_MAX_USER_DEF_OFFSET) {
5927                 dev_err(&hdev->pdev->dev,
5928                         "user-def offset[%u] should be no more than %u\n",
5929                         offset, HCLGE_FD_MAX_USER_DEF_OFFSET);
5930                 return -EINVAL;
5931         }
5932
5933         if (offset_mask != HCLGE_FD_USER_DEF_OFFSET_UNMASK) {
5934                 dev_err(&hdev->pdev->dev, "user-def offset can't be masked\n");
5935                 return -EINVAL;
5936         }
5937
5938         ret = hclge_fd_get_user_def_layer(flow_type, unused_tuple, info);
5939         if (ret) {
5940                 dev_err(&hdev->pdev->dev,
5941                         "unsupported flow type for user-def bytes, ret = %d\n",
5942                         ret);
5943                 return ret;
5944         }
5945
5946         info->data = data;
5947         info->data_mask = data_mask;
5948         info->offset = offset;
5949
5950         return 0;
5951 }
5952
5953 static int hclge_fd_check_spec(struct hclge_dev *hdev,
5954                                struct ethtool_rx_flow_spec *fs,
5955                                u32 *unused_tuple,
5956                                struct hclge_fd_user_def_info *info)
5957 {
5958         u32 flow_type;
5959         int ret;
5960
5961         if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) {
5962                 dev_err(&hdev->pdev->dev,
5963                         "failed to config fd rules, invalid rule location: %u, max is %u\n.",
5964                         fs->location,
5965                         hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1] - 1);
5966                 return -EINVAL;
5967         }
5968
5969         ret = hclge_fd_parse_user_def_field(hdev, fs, unused_tuple, info);
5970         if (ret)
5971                 return ret;
5972
5973         flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT);
5974         switch (flow_type) {
5975         case SCTP_V4_FLOW:
5976         case TCP_V4_FLOW:
5977         case UDP_V4_FLOW:
5978                 ret = hclge_fd_check_tcpip4_tuple(&fs->h_u.tcp_ip4_spec,
5979                                                   unused_tuple);
5980                 break;
5981         case IP_USER_FLOW:
5982                 ret = hclge_fd_check_ip4_tuple(&fs->h_u.usr_ip4_spec,
5983                                                unused_tuple);
5984                 break;
5985         case SCTP_V6_FLOW:
5986         case TCP_V6_FLOW:
5987         case UDP_V6_FLOW:
5988                 ret = hclge_fd_check_tcpip6_tuple(&fs->h_u.tcp_ip6_spec,
5989                                                   unused_tuple);
5990                 break;
5991         case IPV6_USER_FLOW:
5992                 ret = hclge_fd_check_ip6_tuple(&fs->h_u.usr_ip6_spec,
5993                                                unused_tuple);
5994                 break;
5995         case ETHER_FLOW:
5996                 if (hdev->fd_cfg.fd_mode !=
5997                         HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) {
5998                         dev_err(&hdev->pdev->dev,
5999                                 "ETHER_FLOW is not supported in current fd mode!\n");
6000                         return -EOPNOTSUPP;
6001                 }
6002
6003                 ret = hclge_fd_check_ether_tuple(&fs->h_u.ether_spec,
6004                                                  unused_tuple);
6005                 break;
6006         default:
6007                 dev_err(&hdev->pdev->dev,
6008                         "unsupported protocol type, protocol type = %#x\n",
6009                         flow_type);
6010                 return -EOPNOTSUPP;
6011         }
6012
6013         if (ret) {
6014                 dev_err(&hdev->pdev->dev,
6015                         "failed to check flow union tuple, ret = %d\n",
6016                         ret);
6017                 return ret;
6018         }
6019
6020         return hclge_fd_check_ext_tuple(hdev, fs, unused_tuple);
6021 }
6022
6023 static void hclge_fd_get_tcpip4_tuple(struct hclge_dev *hdev,
6024                                       struct ethtool_rx_flow_spec *fs,
6025                                       struct hclge_fd_rule *rule, u8 ip_proto)
6026 {
6027         rule->tuples.src_ip[IPV4_INDEX] =
6028                         be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4src);
6029         rule->tuples_mask.src_ip[IPV4_INDEX] =
6030                         be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4src);
6031
6032         rule->tuples.dst_ip[IPV4_INDEX] =
6033                         be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4dst);
6034         rule->tuples_mask.dst_ip[IPV4_INDEX] =
6035                         be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4dst);
6036
6037         rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc);
6038         rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.psrc);
6039
6040         rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst);
6041         rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.pdst);
6042
6043         rule->tuples.ip_tos = fs->h_u.tcp_ip4_spec.tos;
6044         rule->tuples_mask.ip_tos = fs->m_u.tcp_ip4_spec.tos;
6045
6046         rule->tuples.ether_proto = ETH_P_IP;
6047         rule->tuples_mask.ether_proto = 0xFFFF;
6048
6049         rule->tuples.ip_proto = ip_proto;
6050         rule->tuples_mask.ip_proto = 0xFF;
6051 }
6052
6053 static void hclge_fd_get_ip4_tuple(struct hclge_dev *hdev,
6054                                    struct ethtool_rx_flow_spec *fs,
6055                                    struct hclge_fd_rule *rule)
6056 {
6057         rule->tuples.src_ip[IPV4_INDEX] =
6058                         be32_to_cpu(fs->h_u.usr_ip4_spec.ip4src);
6059         rule->tuples_mask.src_ip[IPV4_INDEX] =
6060                         be32_to_cpu(fs->m_u.usr_ip4_spec.ip4src);
6061
6062         rule->tuples.dst_ip[IPV4_INDEX] =
6063                         be32_to_cpu(fs->h_u.usr_ip4_spec.ip4dst);
6064         rule->tuples_mask.dst_ip[IPV4_INDEX] =
6065                         be32_to_cpu(fs->m_u.usr_ip4_spec.ip4dst);
6066
6067         rule->tuples.ip_tos = fs->h_u.usr_ip4_spec.tos;
6068         rule->tuples_mask.ip_tos = fs->m_u.usr_ip4_spec.tos;
6069
6070         rule->tuples.ip_proto = fs->h_u.usr_ip4_spec.proto;
6071         rule->tuples_mask.ip_proto = fs->m_u.usr_ip4_spec.proto;
6072
6073         rule->tuples.ether_proto = ETH_P_IP;
6074         rule->tuples_mask.ether_proto = 0xFFFF;
6075 }
6076
6077 static void hclge_fd_get_tcpip6_tuple(struct hclge_dev *hdev,
6078                                       struct ethtool_rx_flow_spec *fs,
6079                                       struct hclge_fd_rule *rule, u8 ip_proto)
6080 {
6081         be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.tcp_ip6_spec.ip6src,
6082                           IPV6_SIZE);
6083         be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.tcp_ip6_spec.ip6src,
6084                           IPV6_SIZE);
6085
6086         be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.tcp_ip6_spec.ip6dst,
6087                           IPV6_SIZE);
6088         be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.tcp_ip6_spec.ip6dst,
6089                           IPV6_SIZE);
6090
6091         rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.psrc);
6092         rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.psrc);
6093
6094         rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.pdst);
6095         rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.pdst);
6096
6097         rule->tuples.ether_proto = ETH_P_IPV6;
6098         rule->tuples_mask.ether_proto = 0xFFFF;
6099
6100         rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass;
6101         rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass;
6102
6103         rule->tuples.ip_proto = ip_proto;
6104         rule->tuples_mask.ip_proto = 0xFF;
6105 }
6106
6107 static void hclge_fd_get_ip6_tuple(struct hclge_dev *hdev,
6108                                    struct ethtool_rx_flow_spec *fs,
6109                                    struct hclge_fd_rule *rule)
6110 {
6111         be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.usr_ip6_spec.ip6src,
6112                           IPV6_SIZE);
6113         be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.usr_ip6_spec.ip6src,
6114                           IPV6_SIZE);
6115
6116         be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.usr_ip6_spec.ip6dst,
6117                           IPV6_SIZE);
6118         be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.usr_ip6_spec.ip6dst,
6119                           IPV6_SIZE);
6120
6121         rule->tuples.ip_proto = fs->h_u.usr_ip6_spec.l4_proto;
6122         rule->tuples_mask.ip_proto = fs->m_u.usr_ip6_spec.l4_proto;
6123
6124         rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass;
6125         rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass;
6126
6127         rule->tuples.ether_proto = ETH_P_IPV6;
6128         rule->tuples_mask.ether_proto = 0xFFFF;
6129 }
6130
6131 static void hclge_fd_get_ether_tuple(struct hclge_dev *hdev,
6132                                      struct ethtool_rx_flow_spec *fs,
6133                                      struct hclge_fd_rule *rule)
6134 {
6135         ether_addr_copy(rule->tuples.src_mac, fs->h_u.ether_spec.h_source);
6136         ether_addr_copy(rule->tuples_mask.src_mac, fs->m_u.ether_spec.h_source);
6137
6138         ether_addr_copy(rule->tuples.dst_mac, fs->h_u.ether_spec.h_dest);
6139         ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_u.ether_spec.h_dest);
6140
6141         rule->tuples.ether_proto = be16_to_cpu(fs->h_u.ether_spec.h_proto);
6142         rule->tuples_mask.ether_proto = be16_to_cpu(fs->m_u.ether_spec.h_proto);
6143 }
6144
6145 static void hclge_fd_get_user_def_tuple(struct hclge_fd_user_def_info *info,
6146                                         struct hclge_fd_rule *rule)
6147 {
6148         switch (info->layer) {
6149         case HCLGE_FD_USER_DEF_L2:
6150                 rule->tuples.l2_user_def = info->data;
6151                 rule->tuples_mask.l2_user_def = info->data_mask;
6152                 break;
6153         case HCLGE_FD_USER_DEF_L3:
6154                 rule->tuples.l3_user_def = info->data;
6155                 rule->tuples_mask.l3_user_def = info->data_mask;
6156                 break;
6157         case HCLGE_FD_USER_DEF_L4:
6158                 rule->tuples.l4_user_def = (u32)info->data << 16;
6159                 rule->tuples_mask.l4_user_def = (u32)info->data_mask << 16;
6160                 break;
6161         default:
6162                 break;
6163         }
6164
6165         rule->ep.user_def = *info;
6166 }
6167
6168 static int hclge_fd_get_tuple(struct hclge_dev *hdev,
6169                               struct ethtool_rx_flow_spec *fs,
6170                               struct hclge_fd_rule *rule,
6171                               struct hclge_fd_user_def_info *info)
6172 {
6173         u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT);
6174
6175         switch (flow_type) {
6176         case SCTP_V4_FLOW:
6177                 hclge_fd_get_tcpip4_tuple(hdev, fs, rule, IPPROTO_SCTP);
6178                 break;
6179         case TCP_V4_FLOW:
6180                 hclge_fd_get_tcpip4_tuple(hdev, fs, rule, IPPROTO_TCP);
6181                 break;
6182         case UDP_V4_FLOW:
6183                 hclge_fd_get_tcpip4_tuple(hdev, fs, rule, IPPROTO_UDP);
6184                 break;
6185         case IP_USER_FLOW:
6186                 hclge_fd_get_ip4_tuple(hdev, fs, rule);
6187                 break;
6188         case SCTP_V6_FLOW:
6189                 hclge_fd_get_tcpip6_tuple(hdev, fs, rule, IPPROTO_SCTP);
6190                 break;
6191         case TCP_V6_FLOW:
6192                 hclge_fd_get_tcpip6_tuple(hdev, fs, rule, IPPROTO_TCP);
6193                 break;
6194         case UDP_V6_FLOW:
6195                 hclge_fd_get_tcpip6_tuple(hdev, fs, rule, IPPROTO_UDP);
6196                 break;
6197         case IPV6_USER_FLOW:
6198                 hclge_fd_get_ip6_tuple(hdev, fs, rule);
6199                 break;
6200         case ETHER_FLOW:
6201                 hclge_fd_get_ether_tuple(hdev, fs, rule);
6202                 break;
6203         default:
6204                 return -EOPNOTSUPP;
6205         }
6206
6207         if (fs->flow_type & FLOW_EXT) {
6208                 rule->tuples.vlan_tag1 = be16_to_cpu(fs->h_ext.vlan_tci);
6209                 rule->tuples_mask.vlan_tag1 = be16_to_cpu(fs->m_ext.vlan_tci);
6210                 hclge_fd_get_user_def_tuple(info, rule);
6211         }
6212
6213         if (fs->flow_type & FLOW_MAC_EXT) {
6214                 ether_addr_copy(rule->tuples.dst_mac, fs->h_ext.h_dest);
6215                 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_ext.h_dest);
6216         }
6217
6218         return 0;
6219 }
6220
6221 static int hclge_fd_config_rule(struct hclge_dev *hdev,
6222                                 struct hclge_fd_rule *rule)
6223 {
6224         int ret;
6225
6226         ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule);
6227         if (ret)
6228                 return ret;
6229
6230         return hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule);
6231 }
6232
6233 static int hclge_add_fd_entry_common(struct hclge_dev *hdev,
6234                                      struct hclge_fd_rule *rule)
6235 {
6236         int ret;
6237
6238         spin_lock_bh(&hdev->fd_rule_lock);
6239
6240         if (hdev->fd_active_type != rule->rule_type &&
6241             (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE ||
6242              hdev->fd_active_type == HCLGE_FD_EP_ACTIVE)) {
6243                 dev_err(&hdev->pdev->dev,
6244                         "mode conflict(new type %d, active type %d), please delete existent rules first\n",
6245                         rule->rule_type, hdev->fd_active_type);
6246                 spin_unlock_bh(&hdev->fd_rule_lock);
6247                 return -EINVAL;
6248         }
6249
6250         ret = hclge_fd_check_user_def_refcnt(hdev, rule);
6251         if (ret)
6252                 goto out;
6253
6254         ret = hclge_clear_arfs_rules(hdev);
6255         if (ret)
6256                 goto out;
6257
6258         ret = hclge_fd_config_rule(hdev, rule);
6259         if (ret)
6260                 goto out;
6261
6262         rule->state = HCLGE_FD_ACTIVE;
6263         hdev->fd_active_type = rule->rule_type;
6264         hclge_update_fd_list(hdev, rule->state, rule->location, rule);
6265
6266 out:
6267         spin_unlock_bh(&hdev->fd_rule_lock);
6268         return ret;
6269 }
6270
6271 static bool hclge_is_cls_flower_active(struct hnae3_handle *handle)
6272 {
6273         struct hclge_vport *vport = hclge_get_vport(handle);
6274         struct hclge_dev *hdev = vport->back;
6275
6276         return hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE;
6277 }
6278
6279 static int hclge_fd_parse_ring_cookie(struct hclge_dev *hdev, u64 ring_cookie,
6280                                       u16 *vport_id, u8 *action, u16 *queue_id)
6281 {
6282         struct hclge_vport *vport = hdev->vport;
6283
6284         if (ring_cookie == RX_CLS_FLOW_DISC) {
6285                 *action = HCLGE_FD_ACTION_DROP_PACKET;
6286         } else {
6287                 u32 ring = ethtool_get_flow_spec_ring(ring_cookie);
6288                 u8 vf = ethtool_get_flow_spec_ring_vf(ring_cookie);
6289                 u16 tqps;
6290
6291                 /* To keep consistent with user's configuration, minus 1 when
6292                  * printing 'vf', because vf id from ethtool is added 1 for vf.
6293                  */
6294                 if (vf > hdev->num_req_vfs) {
6295                         dev_err(&hdev->pdev->dev,
6296                                 "Error: vf id (%u) should be less than %u\n",
6297                                 vf - 1U, hdev->num_req_vfs);
6298                         return -EINVAL;
6299                 }
6300
6301                 *vport_id = vf ? hdev->vport[vf].vport_id : vport->vport_id;
6302                 tqps = hdev->vport[vf].nic.kinfo.num_tqps;
6303
6304                 if (ring >= tqps) {
6305                         dev_err(&hdev->pdev->dev,
6306                                 "Error: queue id (%u) > max tqp num (%u)\n",
6307                                 ring, tqps - 1U);
6308                         return -EINVAL;
6309                 }
6310
6311                 *action = HCLGE_FD_ACTION_SELECT_QUEUE;
6312                 *queue_id = ring;
6313         }
6314
6315         return 0;
6316 }
6317
6318 static int hclge_add_fd_entry(struct hnae3_handle *handle,
6319                               struct ethtool_rxnfc *cmd)
6320 {
6321         struct hclge_vport *vport = hclge_get_vport(handle);
6322         struct hclge_dev *hdev = vport->back;
6323         struct hclge_fd_user_def_info info;
6324         u16 dst_vport_id = 0, q_index = 0;
6325         struct ethtool_rx_flow_spec *fs;
6326         struct hclge_fd_rule *rule;
6327         u32 unused = 0;
6328         u8 action;
6329         int ret;
6330
6331         if (!hnae3_dev_fd_supported(hdev)) {
6332                 dev_err(&hdev->pdev->dev,
6333                         "flow table director is not supported\n");
6334                 return -EOPNOTSUPP;
6335         }
6336
6337         if (!hdev->fd_en) {
6338                 dev_err(&hdev->pdev->dev,
6339                         "please enable flow director first\n");
6340                 return -EOPNOTSUPP;
6341         }
6342
6343         fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
6344
6345         ret = hclge_fd_check_spec(hdev, fs, &unused, &info);
6346         if (ret)
6347                 return ret;
6348
6349         ret = hclge_fd_parse_ring_cookie(hdev, fs->ring_cookie, &dst_vport_id,
6350                                          &action, &q_index);
6351         if (ret)
6352                 return ret;
6353
6354         rule = kzalloc(sizeof(*rule), GFP_KERNEL);
6355         if (!rule)
6356                 return -ENOMEM;
6357
6358         ret = hclge_fd_get_tuple(hdev, fs, rule, &info);
6359         if (ret) {
6360                 kfree(rule);
6361                 return ret;
6362         }
6363
6364         rule->flow_type = fs->flow_type;
6365         rule->location = fs->location;
6366         rule->unused_tuple = unused;
6367         rule->vf_id = dst_vport_id;
6368         rule->queue_id = q_index;
6369         rule->action = action;
6370         rule->rule_type = HCLGE_FD_EP_ACTIVE;
6371
6372         ret = hclge_add_fd_entry_common(hdev, rule);
6373         if (ret)
6374                 kfree(rule);
6375
6376         return ret;
6377 }
6378
6379 static int hclge_del_fd_entry(struct hnae3_handle *handle,
6380                               struct ethtool_rxnfc *cmd)
6381 {
6382         struct hclge_vport *vport = hclge_get_vport(handle);
6383         struct hclge_dev *hdev = vport->back;
6384         struct ethtool_rx_flow_spec *fs;
6385         int ret;
6386
6387         if (!hnae3_dev_fd_supported(hdev))
6388                 return -EOPNOTSUPP;
6389
6390         fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
6391
6392         if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1])
6393                 return -EINVAL;
6394
6395         spin_lock_bh(&hdev->fd_rule_lock);
6396         if (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE ||
6397             !test_bit(fs->location, hdev->fd_bmap)) {
6398                 dev_err(&hdev->pdev->dev,
6399                         "Delete fail, rule %u is inexistent\n", fs->location);
6400                 spin_unlock_bh(&hdev->fd_rule_lock);
6401                 return -ENOENT;
6402         }
6403
6404         ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, fs->location,
6405                                    NULL, false);
6406         if (ret)
6407                 goto out;
6408
6409         hclge_update_fd_list(hdev, HCLGE_FD_DELETED, fs->location, NULL);
6410
6411 out:
6412         spin_unlock_bh(&hdev->fd_rule_lock);
6413         return ret;
6414 }
6415
6416 static void hclge_clear_fd_rules_in_list(struct hclge_dev *hdev,
6417                                          bool clear_list)
6418 {
6419         struct hclge_fd_rule *rule;
6420         struct hlist_node *node;
6421         u16 location;
6422
6423         if (!hnae3_dev_fd_supported(hdev))
6424                 return;
6425
6426         spin_lock_bh(&hdev->fd_rule_lock);
6427
6428         for_each_set_bit(location, hdev->fd_bmap,
6429                          hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1])
6430                 hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, location,
6431                                      NULL, false);
6432
6433         if (clear_list) {
6434                 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list,
6435                                           rule_node) {
6436                         hlist_del(&rule->rule_node);
6437                         kfree(rule);
6438                 }
6439                 hdev->fd_active_type = HCLGE_FD_RULE_NONE;
6440                 hdev->hclge_fd_rule_num = 0;
6441                 bitmap_zero(hdev->fd_bmap,
6442                             hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]);
6443         }
6444
6445         spin_unlock_bh(&hdev->fd_rule_lock);
6446 }
6447
6448 static void hclge_del_all_fd_entries(struct hclge_dev *hdev)
6449 {
6450         hclge_clear_fd_rules_in_list(hdev, true);
6451         hclge_fd_disable_user_def(hdev);
6452 }
6453
6454 static int hclge_restore_fd_entries(struct hnae3_handle *handle)
6455 {
6456         struct hclge_vport *vport = hclge_get_vport(handle);
6457         struct hclge_dev *hdev = vport->back;
6458         struct hclge_fd_rule *rule;
6459         struct hlist_node *node;
6460
6461         /* Return ok here, because reset error handling will check this
6462          * return value. If error is returned here, the reset process will
6463          * fail.
6464          */
6465         if (!hnae3_dev_fd_supported(hdev))
6466                 return 0;
6467
6468         /* if fd is disabled, should not restore it when reset */
6469         if (!hdev->fd_en)
6470                 return 0;
6471
6472         spin_lock_bh(&hdev->fd_rule_lock);
6473         hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
6474                 if (rule->state == HCLGE_FD_ACTIVE)
6475                         rule->state = HCLGE_FD_TO_ADD;
6476         }
6477         spin_unlock_bh(&hdev->fd_rule_lock);
6478         set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state);
6479
6480         return 0;
6481 }
6482
6483 static int hclge_get_fd_rule_cnt(struct hnae3_handle *handle,
6484                                  struct ethtool_rxnfc *cmd)
6485 {
6486         struct hclge_vport *vport = hclge_get_vport(handle);
6487         struct hclge_dev *hdev = vport->back;
6488
6489         if (!hnae3_dev_fd_supported(hdev) || hclge_is_cls_flower_active(handle))
6490                 return -EOPNOTSUPP;
6491
6492         cmd->rule_cnt = hdev->hclge_fd_rule_num;
6493         cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1];
6494
6495         return 0;
6496 }
6497
6498 static void hclge_fd_get_tcpip4_info(struct hclge_fd_rule *rule,
6499                                      struct ethtool_tcpip4_spec *spec,
6500                                      struct ethtool_tcpip4_spec *spec_mask)
6501 {
6502         spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]);
6503         spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ?
6504                         0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]);
6505
6506         spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]);
6507         spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ?
6508                         0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]);
6509
6510         spec->psrc = cpu_to_be16(rule->tuples.src_port);
6511         spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ?
6512                         0 : cpu_to_be16(rule->tuples_mask.src_port);
6513
6514         spec->pdst = cpu_to_be16(rule->tuples.dst_port);
6515         spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ?
6516                         0 : cpu_to_be16(rule->tuples_mask.dst_port);
6517
6518         spec->tos = rule->tuples.ip_tos;
6519         spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ?
6520                         0 : rule->tuples_mask.ip_tos;
6521 }
6522
6523 static void hclge_fd_get_ip4_info(struct hclge_fd_rule *rule,
6524                                   struct ethtool_usrip4_spec *spec,
6525                                   struct ethtool_usrip4_spec *spec_mask)
6526 {
6527         spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]);
6528         spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ?
6529                         0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]);
6530
6531         spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]);
6532         spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ?
6533                         0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]);
6534
6535         spec->tos = rule->tuples.ip_tos;
6536         spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ?
6537                         0 : rule->tuples_mask.ip_tos;
6538
6539         spec->proto = rule->tuples.ip_proto;
6540         spec_mask->proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ?
6541                         0 : rule->tuples_mask.ip_proto;
6542
6543         spec->ip_ver = ETH_RX_NFC_IP4;
6544 }
6545
6546 static void hclge_fd_get_tcpip6_info(struct hclge_fd_rule *rule,
6547                                      struct ethtool_tcpip6_spec *spec,
6548                                      struct ethtool_tcpip6_spec *spec_mask)
6549 {
6550         cpu_to_be32_array(spec->ip6src,
6551                           rule->tuples.src_ip, IPV6_SIZE);
6552         cpu_to_be32_array(spec->ip6dst,
6553                           rule->tuples.dst_ip, IPV6_SIZE);
6554         if (rule->unused_tuple & BIT(INNER_SRC_IP))
6555                 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src));
6556         else
6557                 cpu_to_be32_array(spec_mask->ip6src, rule->tuples_mask.src_ip,
6558                                   IPV6_SIZE);
6559
6560         if (rule->unused_tuple & BIT(INNER_DST_IP))
6561                 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst));
6562         else
6563                 cpu_to_be32_array(spec_mask->ip6dst, rule->tuples_mask.dst_ip,
6564                                   IPV6_SIZE);
6565
6566         spec->tclass = rule->tuples.ip_tos;
6567         spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ?
6568                         0 : rule->tuples_mask.ip_tos;
6569
6570         spec->psrc = cpu_to_be16(rule->tuples.src_port);
6571         spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ?
6572                         0 : cpu_to_be16(rule->tuples_mask.src_port);
6573
6574         spec->pdst = cpu_to_be16(rule->tuples.dst_port);
6575         spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ?
6576                         0 : cpu_to_be16(rule->tuples_mask.dst_port);
6577 }
6578
6579 static void hclge_fd_get_ip6_info(struct hclge_fd_rule *rule,
6580                                   struct ethtool_usrip6_spec *spec,
6581                                   struct ethtool_usrip6_spec *spec_mask)
6582 {
6583         cpu_to_be32_array(spec->ip6src, rule->tuples.src_ip, IPV6_SIZE);
6584         cpu_to_be32_array(spec->ip6dst, rule->tuples.dst_ip, IPV6_SIZE);
6585         if (rule->unused_tuple & BIT(INNER_SRC_IP))
6586                 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src));
6587         else
6588                 cpu_to_be32_array(spec_mask->ip6src,
6589                                   rule->tuples_mask.src_ip, IPV6_SIZE);
6590
6591         if (rule->unused_tuple & BIT(INNER_DST_IP))
6592                 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst));
6593         else
6594                 cpu_to_be32_array(spec_mask->ip6dst,
6595                                   rule->tuples_mask.dst_ip, IPV6_SIZE);
6596
6597         spec->tclass = rule->tuples.ip_tos;
6598         spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ?
6599                         0 : rule->tuples_mask.ip_tos;
6600
6601         spec->l4_proto = rule->tuples.ip_proto;
6602         spec_mask->l4_proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ?
6603                         0 : rule->tuples_mask.ip_proto;
6604 }
6605
6606 static void hclge_fd_get_ether_info(struct hclge_fd_rule *rule,
6607                                     struct ethhdr *spec,
6608                                     struct ethhdr *spec_mask)
6609 {
6610         ether_addr_copy(spec->h_source, rule->tuples.src_mac);
6611         ether_addr_copy(spec->h_dest, rule->tuples.dst_mac);
6612
6613         if (rule->unused_tuple & BIT(INNER_SRC_MAC))
6614                 eth_zero_addr(spec_mask->h_source);
6615         else
6616                 ether_addr_copy(spec_mask->h_source, rule->tuples_mask.src_mac);
6617
6618         if (rule->unused_tuple & BIT(INNER_DST_MAC))
6619                 eth_zero_addr(spec_mask->h_dest);
6620         else
6621                 ether_addr_copy(spec_mask->h_dest, rule->tuples_mask.dst_mac);
6622
6623         spec->h_proto = cpu_to_be16(rule->tuples.ether_proto);
6624         spec_mask->h_proto = rule->unused_tuple & BIT(INNER_ETH_TYPE) ?
6625                         0 : cpu_to_be16(rule->tuples_mask.ether_proto);
6626 }
6627
6628 static void hclge_fd_get_user_def_info(struct ethtool_rx_flow_spec *fs,
6629                                        struct hclge_fd_rule *rule)
6630 {
6631         if ((rule->unused_tuple & HCLGE_FD_TUPLE_USER_DEF_TUPLES) ==
6632             HCLGE_FD_TUPLE_USER_DEF_TUPLES) {
6633                 fs->h_ext.data[0] = 0;
6634                 fs->h_ext.data[1] = 0;
6635                 fs->m_ext.data[0] = 0;
6636                 fs->m_ext.data[1] = 0;
6637         } else {
6638                 fs->h_ext.data[0] = cpu_to_be32(rule->ep.user_def.offset);
6639                 fs->h_ext.data[1] = cpu_to_be32(rule->ep.user_def.data);
6640                 fs->m_ext.data[0] =
6641                                 cpu_to_be32(HCLGE_FD_USER_DEF_OFFSET_UNMASK);
6642                 fs->m_ext.data[1] = cpu_to_be32(rule->ep.user_def.data_mask);
6643         }
6644 }
6645
6646 static void hclge_fd_get_ext_info(struct ethtool_rx_flow_spec *fs,
6647                                   struct hclge_fd_rule *rule)
6648 {
6649         if (fs->flow_type & FLOW_EXT) {
6650                 fs->h_ext.vlan_tci = cpu_to_be16(rule->tuples.vlan_tag1);
6651                 fs->m_ext.vlan_tci =
6652                                 rule->unused_tuple & BIT(INNER_VLAN_TAG_FST) ?
6653                                 0 : cpu_to_be16(rule->tuples_mask.vlan_tag1);
6654
6655                 hclge_fd_get_user_def_info(fs, rule);
6656         }
6657
6658         if (fs->flow_type & FLOW_MAC_EXT) {
6659                 ether_addr_copy(fs->h_ext.h_dest, rule->tuples.dst_mac);
6660                 if (rule->unused_tuple & BIT(INNER_DST_MAC))
6661                         eth_zero_addr(fs->m_u.ether_spec.h_dest);
6662                 else
6663                         ether_addr_copy(fs->m_u.ether_spec.h_dest,
6664                                         rule->tuples_mask.dst_mac);
6665         }
6666 }
6667
6668 static struct hclge_fd_rule *hclge_get_fd_rule(struct hclge_dev *hdev,
6669                                                u16 location)
6670 {
6671         struct hclge_fd_rule *rule = NULL;
6672         struct hlist_node *node2;
6673
6674         hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) {
6675                 if (rule->location == location)
6676                         return rule;
6677                 else if (rule->location > location)
6678                         return NULL;
6679         }
6680
6681         return NULL;
6682 }
6683
6684 static void hclge_fd_get_ring_cookie(struct ethtool_rx_flow_spec *fs,
6685                                      struct hclge_fd_rule *rule)
6686 {
6687         if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) {
6688                 fs->ring_cookie = RX_CLS_FLOW_DISC;
6689         } else {
6690                 u64 vf_id;
6691
6692                 fs->ring_cookie = rule->queue_id;
6693                 vf_id = rule->vf_id;
6694                 vf_id <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
6695                 fs->ring_cookie |= vf_id;
6696         }
6697 }
6698
6699 static int hclge_get_fd_rule_info(struct hnae3_handle *handle,
6700                                   struct ethtool_rxnfc *cmd)
6701 {
6702         struct hclge_vport *vport = hclge_get_vport(handle);
6703         struct hclge_fd_rule *rule = NULL;
6704         struct hclge_dev *hdev = vport->back;
6705         struct ethtool_rx_flow_spec *fs;
6706
6707         if (!hnae3_dev_fd_supported(hdev))
6708                 return -EOPNOTSUPP;
6709
6710         fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
6711
6712         spin_lock_bh(&hdev->fd_rule_lock);
6713
6714         rule = hclge_get_fd_rule(hdev, fs->location);
6715         if (!rule) {
6716                 spin_unlock_bh(&hdev->fd_rule_lock);
6717                 return -ENOENT;
6718         }
6719
6720         fs->flow_type = rule->flow_type;
6721         switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
6722         case SCTP_V4_FLOW:
6723         case TCP_V4_FLOW:
6724         case UDP_V4_FLOW:
6725                 hclge_fd_get_tcpip4_info(rule, &fs->h_u.tcp_ip4_spec,
6726                                          &fs->m_u.tcp_ip4_spec);
6727                 break;
6728         case IP_USER_FLOW:
6729                 hclge_fd_get_ip4_info(rule, &fs->h_u.usr_ip4_spec,
6730                                       &fs->m_u.usr_ip4_spec);
6731                 break;
6732         case SCTP_V6_FLOW:
6733         case TCP_V6_FLOW:
6734         case UDP_V6_FLOW:
6735                 hclge_fd_get_tcpip6_info(rule, &fs->h_u.tcp_ip6_spec,
6736                                          &fs->m_u.tcp_ip6_spec);
6737                 break;
6738         case IPV6_USER_FLOW:
6739                 hclge_fd_get_ip6_info(rule, &fs->h_u.usr_ip6_spec,
6740                                       &fs->m_u.usr_ip6_spec);
6741                 break;
6742         /* The flow type of fd rule has been checked before adding in to rule
6743          * list. As other flow types have been handled, it must be ETHER_FLOW
6744          * for the default case
6745          */
6746         default:
6747                 hclge_fd_get_ether_info(rule, &fs->h_u.ether_spec,
6748                                         &fs->m_u.ether_spec);
6749                 break;
6750         }
6751
6752         hclge_fd_get_ext_info(fs, rule);
6753
6754         hclge_fd_get_ring_cookie(fs, rule);
6755
6756         spin_unlock_bh(&hdev->fd_rule_lock);
6757
6758         return 0;
6759 }
6760
6761 static int hclge_get_all_rules(struct hnae3_handle *handle,
6762                                struct ethtool_rxnfc *cmd, u32 *rule_locs)
6763 {
6764         struct hclge_vport *vport = hclge_get_vport(handle);
6765         struct hclge_dev *hdev = vport->back;
6766         struct hclge_fd_rule *rule;
6767         struct hlist_node *node2;
6768         int cnt = 0;
6769
6770         if (!hnae3_dev_fd_supported(hdev))
6771                 return -EOPNOTSUPP;
6772
6773         cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1];
6774
6775         spin_lock_bh(&hdev->fd_rule_lock);
6776         hlist_for_each_entry_safe(rule, node2,
6777                                   &hdev->fd_rule_list, rule_node) {
6778                 if (cnt == cmd->rule_cnt) {
6779                         spin_unlock_bh(&hdev->fd_rule_lock);
6780                         return -EMSGSIZE;
6781                 }
6782
6783                 if (rule->state == HCLGE_FD_TO_DEL)
6784                         continue;
6785
6786                 rule_locs[cnt] = rule->location;
6787                 cnt++;
6788         }
6789
6790         spin_unlock_bh(&hdev->fd_rule_lock);
6791
6792         cmd->rule_cnt = cnt;
6793
6794         return 0;
6795 }
6796
6797 static void hclge_fd_get_flow_tuples(const struct flow_keys *fkeys,
6798                                      struct hclge_fd_rule_tuples *tuples)
6799 {
6800 #define flow_ip6_src fkeys->addrs.v6addrs.src.in6_u.u6_addr32
6801 #define flow_ip6_dst fkeys->addrs.v6addrs.dst.in6_u.u6_addr32
6802
6803         tuples->ether_proto = be16_to_cpu(fkeys->basic.n_proto);
6804         tuples->ip_proto = fkeys->basic.ip_proto;
6805         tuples->dst_port = be16_to_cpu(fkeys->ports.dst);
6806
6807         if (fkeys->basic.n_proto == htons(ETH_P_IP)) {
6808                 tuples->src_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.src);
6809                 tuples->dst_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.dst);
6810         } else {
6811                 int i;
6812
6813                 for (i = 0; i < IPV6_SIZE; i++) {
6814                         tuples->src_ip[i] = be32_to_cpu(flow_ip6_src[i]);
6815                         tuples->dst_ip[i] = be32_to_cpu(flow_ip6_dst[i]);
6816                 }
6817         }
6818 }
6819
6820 /* traverse all rules, check whether an existed rule has the same tuples */
6821 static struct hclge_fd_rule *
6822 hclge_fd_search_flow_keys(struct hclge_dev *hdev,
6823                           const struct hclge_fd_rule_tuples *tuples)
6824 {
6825         struct hclge_fd_rule *rule = NULL;
6826         struct hlist_node *node;
6827
6828         hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
6829                 if (!memcmp(tuples, &rule->tuples, sizeof(*tuples)))
6830                         return rule;
6831         }
6832
6833         return NULL;
6834 }
6835
6836 static void hclge_fd_build_arfs_rule(const struct hclge_fd_rule_tuples *tuples,
6837                                      struct hclge_fd_rule *rule)
6838 {
6839         rule->unused_tuple = BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
6840                              BIT(INNER_VLAN_TAG_FST) | BIT(INNER_IP_TOS) |
6841                              BIT(INNER_SRC_PORT);
6842         rule->action = 0;
6843         rule->vf_id = 0;
6844         rule->rule_type = HCLGE_FD_ARFS_ACTIVE;
6845         rule->state = HCLGE_FD_TO_ADD;
6846         if (tuples->ether_proto == ETH_P_IP) {
6847                 if (tuples->ip_proto == IPPROTO_TCP)
6848                         rule->flow_type = TCP_V4_FLOW;
6849                 else
6850                         rule->flow_type = UDP_V4_FLOW;
6851         } else {
6852                 if (tuples->ip_proto == IPPROTO_TCP)
6853                         rule->flow_type = TCP_V6_FLOW;
6854                 else
6855                         rule->flow_type = UDP_V6_FLOW;
6856         }
6857         memcpy(&rule->tuples, tuples, sizeof(rule->tuples));
6858         memset(&rule->tuples_mask, 0xFF, sizeof(rule->tuples_mask));
6859 }
6860
6861 static int hclge_add_fd_entry_by_arfs(struct hnae3_handle *handle, u16 queue_id,
6862                                       u16 flow_id, struct flow_keys *fkeys)
6863 {
6864         struct hclge_vport *vport = hclge_get_vport(handle);
6865         struct hclge_fd_rule_tuples new_tuples = {};
6866         struct hclge_dev *hdev = vport->back;
6867         struct hclge_fd_rule *rule;
6868         u16 bit_id;
6869
6870         if (!hnae3_dev_fd_supported(hdev))
6871                 return -EOPNOTSUPP;
6872
6873         /* when there is already fd rule existed add by user,
6874          * arfs should not work
6875          */
6876         spin_lock_bh(&hdev->fd_rule_lock);
6877         if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE &&
6878             hdev->fd_active_type != HCLGE_FD_RULE_NONE) {
6879                 spin_unlock_bh(&hdev->fd_rule_lock);
6880                 return -EOPNOTSUPP;
6881         }
6882
6883         hclge_fd_get_flow_tuples(fkeys, &new_tuples);
6884
6885         /* check is there flow director filter existed for this flow,
6886          * if not, create a new filter for it;
6887          * if filter exist with different queue id, modify the filter;
6888          * if filter exist with same queue id, do nothing
6889          */
6890         rule = hclge_fd_search_flow_keys(hdev, &new_tuples);
6891         if (!rule) {
6892                 bit_id = find_first_zero_bit(hdev->fd_bmap, MAX_FD_FILTER_NUM);
6893                 if (bit_id >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) {
6894                         spin_unlock_bh(&hdev->fd_rule_lock);
6895                         return -ENOSPC;
6896                 }
6897
6898                 rule = kzalloc(sizeof(*rule), GFP_ATOMIC);
6899                 if (!rule) {
6900                         spin_unlock_bh(&hdev->fd_rule_lock);
6901                         return -ENOMEM;
6902                 }
6903
6904                 rule->location = bit_id;
6905                 rule->arfs.flow_id = flow_id;
6906                 rule->queue_id = queue_id;
6907                 hclge_fd_build_arfs_rule(&new_tuples, rule);
6908                 hclge_update_fd_list(hdev, rule->state, rule->location, rule);
6909                 hdev->fd_active_type = HCLGE_FD_ARFS_ACTIVE;
6910         } else if (rule->queue_id != queue_id) {
6911                 rule->queue_id = queue_id;
6912                 rule->state = HCLGE_FD_TO_ADD;
6913                 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state);
6914                 hclge_task_schedule(hdev, 0);
6915         }
6916         spin_unlock_bh(&hdev->fd_rule_lock);
6917         return rule->location;
6918 }
6919
6920 static void hclge_rfs_filter_expire(struct hclge_dev *hdev)
6921 {
6922 #ifdef CONFIG_RFS_ACCEL
6923         struct hnae3_handle *handle = &hdev->vport[0].nic;
6924         struct hclge_fd_rule *rule;
6925         struct hlist_node *node;
6926
6927         spin_lock_bh(&hdev->fd_rule_lock);
6928         if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) {
6929                 spin_unlock_bh(&hdev->fd_rule_lock);
6930                 return;
6931         }
6932         hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
6933                 if (rule->state != HCLGE_FD_ACTIVE)
6934                         continue;
6935                 if (rps_may_expire_flow(handle->netdev, rule->queue_id,
6936                                         rule->arfs.flow_id, rule->location)) {
6937                         rule->state = HCLGE_FD_TO_DEL;
6938                         set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state);
6939                 }
6940         }
6941         spin_unlock_bh(&hdev->fd_rule_lock);
6942 #endif
6943 }
6944
6945 /* make sure being called after lock up with fd_rule_lock */
6946 static int hclge_clear_arfs_rules(struct hclge_dev *hdev)
6947 {
6948 #ifdef CONFIG_RFS_ACCEL
6949         struct hclge_fd_rule *rule;
6950         struct hlist_node *node;
6951         int ret;
6952
6953         if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE)
6954                 return 0;
6955
6956         hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
6957                 switch (rule->state) {
6958                 case HCLGE_FD_TO_DEL:
6959                 case HCLGE_FD_ACTIVE:
6960                         ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
6961                                                    rule->location, NULL, false);
6962                         if (ret)
6963                                 return ret;
6964                         fallthrough;
6965                 case HCLGE_FD_TO_ADD:
6966                         hclge_fd_dec_rule_cnt(hdev, rule->location);
6967                         hlist_del(&rule->rule_node);
6968                         kfree(rule);
6969                         break;
6970                 default:
6971                         break;
6972                 }
6973         }
6974         hclge_sync_fd_state(hdev);
6975
6976 #endif
6977         return 0;
6978 }
6979
6980 static void hclge_get_cls_key_basic(const struct flow_rule *flow,
6981                                     struct hclge_fd_rule *rule)
6982 {
6983         if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_BASIC)) {
6984                 struct flow_match_basic match;
6985                 u16 ethtype_key, ethtype_mask;
6986
6987                 flow_rule_match_basic(flow, &match);
6988                 ethtype_key = ntohs(match.key->n_proto);
6989                 ethtype_mask = ntohs(match.mask->n_proto);
6990
6991                 if (ethtype_key == ETH_P_ALL) {
6992                         ethtype_key = 0;
6993                         ethtype_mask = 0;
6994                 }
6995                 rule->tuples.ether_proto = ethtype_key;
6996                 rule->tuples_mask.ether_proto = ethtype_mask;
6997                 rule->tuples.ip_proto = match.key->ip_proto;
6998                 rule->tuples_mask.ip_proto = match.mask->ip_proto;
6999         } else {
7000                 rule->unused_tuple |= BIT(INNER_IP_PROTO);
7001                 rule->unused_tuple |= BIT(INNER_ETH_TYPE);
7002         }
7003 }
7004
7005 static void hclge_get_cls_key_mac(const struct flow_rule *flow,
7006                                   struct hclge_fd_rule *rule)
7007 {
7008         if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
7009                 struct flow_match_eth_addrs match;
7010
7011                 flow_rule_match_eth_addrs(flow, &match);
7012                 ether_addr_copy(rule->tuples.dst_mac, match.key->dst);
7013                 ether_addr_copy(rule->tuples_mask.dst_mac, match.mask->dst);
7014                 ether_addr_copy(rule->tuples.src_mac, match.key->src);
7015                 ether_addr_copy(rule->tuples_mask.src_mac, match.mask->src);
7016         } else {
7017                 rule->unused_tuple |= BIT(INNER_DST_MAC);
7018                 rule->unused_tuple |= BIT(INNER_SRC_MAC);
7019         }
7020 }
7021
7022 static void hclge_get_cls_key_vlan(const struct flow_rule *flow,
7023                                    struct hclge_fd_rule *rule)
7024 {
7025         if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_VLAN)) {
7026                 struct flow_match_vlan match;
7027
7028                 flow_rule_match_vlan(flow, &match);
7029                 rule->tuples.vlan_tag1 = match.key->vlan_id |
7030                                 (match.key->vlan_priority << VLAN_PRIO_SHIFT);
7031                 rule->tuples_mask.vlan_tag1 = match.mask->vlan_id |
7032                                 (match.mask->vlan_priority << VLAN_PRIO_SHIFT);
7033         } else {
7034                 rule->unused_tuple |= BIT(INNER_VLAN_TAG_FST);
7035         }
7036 }
7037
7038 static void hclge_get_cls_key_ip(const struct flow_rule *flow,
7039                                  struct hclge_fd_rule *rule)
7040 {
7041         u16 addr_type = 0;
7042
7043         if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_CONTROL)) {
7044                 struct flow_match_control match;
7045
7046                 flow_rule_match_control(flow, &match);
7047                 addr_type = match.key->addr_type;
7048         }
7049
7050         if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
7051                 struct flow_match_ipv4_addrs match;
7052
7053                 flow_rule_match_ipv4_addrs(flow, &match);
7054                 rule->tuples.src_ip[IPV4_INDEX] = be32_to_cpu(match.key->src);
7055                 rule->tuples_mask.src_ip[IPV4_INDEX] =
7056                                                 be32_to_cpu(match.mask->src);
7057                 rule->tuples.dst_ip[IPV4_INDEX] = be32_to_cpu(match.key->dst);
7058                 rule->tuples_mask.dst_ip[IPV4_INDEX] =
7059                                                 be32_to_cpu(match.mask->dst);
7060         } else if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
7061                 struct flow_match_ipv6_addrs match;
7062
7063                 flow_rule_match_ipv6_addrs(flow, &match);
7064                 be32_to_cpu_array(rule->tuples.src_ip, match.key->src.s6_addr32,
7065                                   IPV6_SIZE);
7066                 be32_to_cpu_array(rule->tuples_mask.src_ip,
7067                                   match.mask->src.s6_addr32, IPV6_SIZE);
7068                 be32_to_cpu_array(rule->tuples.dst_ip, match.key->dst.s6_addr32,
7069                                   IPV6_SIZE);
7070                 be32_to_cpu_array(rule->tuples_mask.dst_ip,
7071                                   match.mask->dst.s6_addr32, IPV6_SIZE);
7072         } else {
7073                 rule->unused_tuple |= BIT(INNER_SRC_IP);
7074                 rule->unused_tuple |= BIT(INNER_DST_IP);
7075         }
7076 }
7077
7078 static void hclge_get_cls_key_port(const struct flow_rule *flow,
7079                                    struct hclge_fd_rule *rule)
7080 {
7081         if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_PORTS)) {
7082                 struct flow_match_ports match;
7083
7084                 flow_rule_match_ports(flow, &match);
7085
7086                 rule->tuples.src_port = be16_to_cpu(match.key->src);
7087                 rule->tuples_mask.src_port = be16_to_cpu(match.mask->src);
7088                 rule->tuples.dst_port = be16_to_cpu(match.key->dst);
7089                 rule->tuples_mask.dst_port = be16_to_cpu(match.mask->dst);
7090         } else {
7091                 rule->unused_tuple |= BIT(INNER_SRC_PORT);
7092                 rule->unused_tuple |= BIT(INNER_DST_PORT);
7093         }
7094 }
7095
7096 static int hclge_parse_cls_flower(struct hclge_dev *hdev,
7097                                   struct flow_cls_offload *cls_flower,
7098                                   struct hclge_fd_rule *rule)
7099 {
7100         struct flow_rule *flow = flow_cls_offload_flow_rule(cls_flower);
7101         struct flow_dissector *dissector = flow->match.dissector;
7102
7103         if (dissector->used_keys &
7104             ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
7105               BIT(FLOW_DISSECTOR_KEY_BASIC) |
7106               BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
7107               BIT(FLOW_DISSECTOR_KEY_VLAN) |
7108               BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
7109               BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
7110               BIT(FLOW_DISSECTOR_KEY_PORTS))) {
7111                 dev_err(&hdev->pdev->dev, "unsupported key set: %#x\n",
7112                         dissector->used_keys);
7113                 return -EOPNOTSUPP;
7114         }
7115
7116         hclge_get_cls_key_basic(flow, rule);
7117         hclge_get_cls_key_mac(flow, rule);
7118         hclge_get_cls_key_vlan(flow, rule);
7119         hclge_get_cls_key_ip(flow, rule);
7120         hclge_get_cls_key_port(flow, rule);
7121
7122         return 0;
7123 }
7124
7125 static int hclge_check_cls_flower(struct hclge_dev *hdev,
7126                                   struct flow_cls_offload *cls_flower, int tc)
7127 {
7128         u32 prio = cls_flower->common.prio;
7129
7130         if (tc < 0 || tc > hdev->tc_max) {
7131                 dev_err(&hdev->pdev->dev, "invalid traffic class\n");
7132                 return -EINVAL;
7133         }
7134
7135         if (prio == 0 ||
7136             prio > hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) {
7137                 dev_err(&hdev->pdev->dev,
7138                         "prio %u should be in range[1, %u]\n",
7139                         prio, hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]);
7140                 return -EINVAL;
7141         }
7142
7143         if (test_bit(prio - 1, hdev->fd_bmap)) {
7144                 dev_err(&hdev->pdev->dev, "prio %u is already used\n", prio);
7145                 return -EINVAL;
7146         }
7147         return 0;
7148 }
7149
7150 static int hclge_add_cls_flower(struct hnae3_handle *handle,
7151                                 struct flow_cls_offload *cls_flower,
7152                                 int tc)
7153 {
7154         struct hclge_vport *vport = hclge_get_vport(handle);
7155         struct hclge_dev *hdev = vport->back;
7156         struct hclge_fd_rule *rule;
7157         int ret;
7158
7159         ret = hclge_check_cls_flower(hdev, cls_flower, tc);
7160         if (ret) {
7161                 dev_err(&hdev->pdev->dev,
7162                         "failed to check cls flower params, ret = %d\n", ret);
7163                 return ret;
7164         }
7165
7166         rule = kzalloc(sizeof(*rule), GFP_KERNEL);
7167         if (!rule)
7168                 return -ENOMEM;
7169
7170         ret = hclge_parse_cls_flower(hdev, cls_flower, rule);
7171         if (ret) {
7172                 kfree(rule);
7173                 return ret;
7174         }
7175
7176         rule->action = HCLGE_FD_ACTION_SELECT_TC;
7177         rule->cls_flower.tc = tc;
7178         rule->location = cls_flower->common.prio - 1;
7179         rule->vf_id = 0;
7180         rule->cls_flower.cookie = cls_flower->cookie;
7181         rule->rule_type = HCLGE_FD_TC_FLOWER_ACTIVE;
7182
7183         ret = hclge_add_fd_entry_common(hdev, rule);
7184         if (ret)
7185                 kfree(rule);
7186
7187         return ret;
7188 }
7189
7190 static struct hclge_fd_rule *hclge_find_cls_flower(struct hclge_dev *hdev,
7191                                                    unsigned long cookie)
7192 {
7193         struct hclge_fd_rule *rule;
7194         struct hlist_node *node;
7195
7196         hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
7197                 if (rule->cls_flower.cookie == cookie)
7198                         return rule;
7199         }
7200
7201         return NULL;
7202 }
7203
7204 static int hclge_del_cls_flower(struct hnae3_handle *handle,
7205                                 struct flow_cls_offload *cls_flower)
7206 {
7207         struct hclge_vport *vport = hclge_get_vport(handle);
7208         struct hclge_dev *hdev = vport->back;
7209         struct hclge_fd_rule *rule;
7210         int ret;
7211
7212         spin_lock_bh(&hdev->fd_rule_lock);
7213
7214         rule = hclge_find_cls_flower(hdev, cls_flower->cookie);
7215         if (!rule) {
7216                 spin_unlock_bh(&hdev->fd_rule_lock);
7217                 return -EINVAL;
7218         }
7219
7220         ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, rule->location,
7221                                    NULL, false);
7222         if (ret) {
7223                 spin_unlock_bh(&hdev->fd_rule_lock);
7224                 return ret;
7225         }
7226
7227         hclge_update_fd_list(hdev, HCLGE_FD_DELETED, rule->location, NULL);
7228         spin_unlock_bh(&hdev->fd_rule_lock);
7229
7230         return 0;
7231 }
7232
7233 static void hclge_sync_fd_list(struct hclge_dev *hdev, struct hlist_head *hlist)
7234 {
7235         struct hclge_fd_rule *rule;
7236         struct hlist_node *node;
7237         int ret = 0;
7238
7239         if (!test_and_clear_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state))
7240                 return;
7241
7242         spin_lock_bh(&hdev->fd_rule_lock);
7243
7244         hlist_for_each_entry_safe(rule, node, hlist, rule_node) {
7245                 switch (rule->state) {
7246                 case HCLGE_FD_TO_ADD:
7247                         ret = hclge_fd_config_rule(hdev, rule);
7248                         if (ret)
7249                                 goto out;
7250                         rule->state = HCLGE_FD_ACTIVE;
7251                         break;
7252                 case HCLGE_FD_TO_DEL:
7253                         ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
7254                                                    rule->location, NULL, false);
7255                         if (ret)
7256                                 goto out;
7257                         hclge_fd_dec_rule_cnt(hdev, rule->location);
7258                         hclge_fd_free_node(hdev, rule);
7259                         break;
7260                 default:
7261                         break;
7262                 }
7263         }
7264
7265 out:
7266         if (ret)
7267                 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state);
7268
7269         spin_unlock_bh(&hdev->fd_rule_lock);
7270 }
7271
7272 static void hclge_sync_fd_table(struct hclge_dev *hdev)
7273 {
7274         if (test_and_clear_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state)) {
7275                 bool clear_list = hdev->fd_active_type == HCLGE_FD_ARFS_ACTIVE;
7276
7277                 hclge_clear_fd_rules_in_list(hdev, clear_list);
7278         }
7279
7280         hclge_sync_fd_user_def_cfg(hdev, false);
7281
7282         hclge_sync_fd_list(hdev, &hdev->fd_rule_list);
7283 }
7284
7285 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle)
7286 {
7287         struct hclge_vport *vport = hclge_get_vport(handle);
7288         struct hclge_dev *hdev = vport->back;
7289
7290         return hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) ||
7291                hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING);
7292 }
7293
7294 static bool hclge_get_cmdq_stat(struct hnae3_handle *handle)
7295 {
7296         struct hclge_vport *vport = hclge_get_vport(handle);
7297         struct hclge_dev *hdev = vport->back;
7298
7299         return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
7300 }
7301
7302 static bool hclge_ae_dev_resetting(struct hnae3_handle *handle)
7303 {
7304         struct hclge_vport *vport = hclge_get_vport(handle);
7305         struct hclge_dev *hdev = vport->back;
7306
7307         return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
7308 }
7309
7310 static unsigned long hclge_ae_dev_reset_cnt(struct hnae3_handle *handle)
7311 {
7312         struct hclge_vport *vport = hclge_get_vport(handle);
7313         struct hclge_dev *hdev = vport->back;
7314
7315         return hdev->rst_stats.hw_reset_done_cnt;
7316 }
7317
7318 static void hclge_enable_fd(struct hnae3_handle *handle, bool enable)
7319 {
7320         struct hclge_vport *vport = hclge_get_vport(handle);
7321         struct hclge_dev *hdev = vport->back;
7322
7323         hdev->fd_en = enable;
7324
7325         if (!enable)
7326                 set_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state);
7327         else
7328                 hclge_restore_fd_entries(handle);
7329
7330         hclge_task_schedule(hdev, 0);
7331 }
7332
7333 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
7334 {
7335         struct hclge_desc desc;
7336         struct hclge_config_mac_mode_cmd *req =
7337                 (struct hclge_config_mac_mode_cmd *)desc.data;
7338         u32 loop_en = 0;
7339         int ret;
7340
7341         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
7342
7343         if (enable) {
7344                 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, 1U);
7345                 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, 1U);
7346                 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, 1U);
7347                 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, 1U);
7348                 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, 1U);
7349                 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, 1U);
7350                 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, 1U);
7351                 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, 1U);
7352                 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, 1U);
7353                 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, 1U);
7354         }
7355
7356         req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
7357
7358         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7359         if (ret)
7360                 dev_err(&hdev->pdev->dev,
7361                         "mac enable fail, ret =%d.\n", ret);
7362 }
7363
7364 static int hclge_config_switch_param(struct hclge_dev *hdev, int vfid,
7365                                      u8 switch_param, u8 param_mask)
7366 {
7367         struct hclge_mac_vlan_switch_cmd *req;
7368         struct hclge_desc desc;
7369         u32 func_id;
7370         int ret;
7371
7372         func_id = hclge_get_port_number(HOST_PORT, 0, vfid, 0);
7373         req = (struct hclge_mac_vlan_switch_cmd *)desc.data;
7374
7375         /* read current config parameter */
7376         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_SWITCH_PARAM,
7377                                    true);
7378         req->roce_sel = HCLGE_MAC_VLAN_NIC_SEL;
7379         req->func_id = cpu_to_le32(func_id);
7380
7381         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7382         if (ret) {
7383                 dev_err(&hdev->pdev->dev,
7384                         "read mac vlan switch parameter fail, ret = %d\n", ret);
7385                 return ret;
7386         }
7387
7388         /* modify and write new config parameter */
7389         hclge_comm_cmd_reuse_desc(&desc, false);
7390         req->switch_param = (req->switch_param & param_mask) | switch_param;
7391         req->param_mask = param_mask;
7392
7393         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7394         if (ret)
7395                 dev_err(&hdev->pdev->dev,
7396                         "set mac vlan switch parameter fail, ret = %d\n", ret);
7397         return ret;
7398 }
7399
7400 static void hclge_phy_link_status_wait(struct hclge_dev *hdev,
7401                                        int link_ret)
7402 {
7403 #define HCLGE_PHY_LINK_STATUS_NUM  200
7404
7405         struct phy_device *phydev = hdev->hw.mac.phydev;
7406         int i = 0;
7407         int ret;
7408
7409         do {
7410                 ret = phy_read_status(phydev);
7411                 if (ret) {
7412                         dev_err(&hdev->pdev->dev,
7413                                 "phy update link status fail, ret = %d\n", ret);
7414                         return;
7415                 }
7416
7417                 if (phydev->link == link_ret)
7418                         break;
7419
7420                 msleep(HCLGE_LINK_STATUS_MS);
7421         } while (++i < HCLGE_PHY_LINK_STATUS_NUM);
7422 }
7423
7424 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret)
7425 {
7426 #define HCLGE_MAC_LINK_STATUS_NUM  100
7427
7428         int link_status;
7429         int i = 0;
7430         int ret;
7431
7432         do {
7433                 ret = hclge_get_mac_link_status(hdev, &link_status);
7434                 if (ret)
7435                         return ret;
7436                 if (link_status == link_ret)
7437                         return 0;
7438
7439                 msleep(HCLGE_LINK_STATUS_MS);
7440         } while (++i < HCLGE_MAC_LINK_STATUS_NUM);
7441         return -EBUSY;
7442 }
7443
7444 static int hclge_mac_phy_link_status_wait(struct hclge_dev *hdev, bool en,
7445                                           bool is_phy)
7446 {
7447         int link_ret;
7448
7449         link_ret = en ? HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN;
7450
7451         if (is_phy)
7452                 hclge_phy_link_status_wait(hdev, link_ret);
7453
7454         return hclge_mac_link_status_wait(hdev, link_ret);
7455 }
7456
7457 static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en)
7458 {
7459         struct hclge_config_mac_mode_cmd *req;
7460         struct hclge_desc desc;
7461         u32 loop_en;
7462         int ret;
7463
7464         req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
7465         /* 1 Read out the MAC mode config at first */
7466         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
7467         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7468         if (ret) {
7469                 dev_err(&hdev->pdev->dev,
7470                         "mac loopback get fail, ret =%d.\n", ret);
7471                 return ret;
7472         }
7473
7474         /* 2 Then setup the loopback flag */
7475         loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
7476         hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0);
7477
7478         req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
7479
7480         /* 3 Config mac work mode with loopback flag
7481          * and its original configure parameters
7482          */
7483         hclge_comm_cmd_reuse_desc(&desc, false);
7484         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7485         if (ret)
7486                 dev_err(&hdev->pdev->dev,
7487                         "mac loopback set fail, ret =%d.\n", ret);
7488         return ret;
7489 }
7490
7491 static int hclge_cfg_common_loopback_cmd_send(struct hclge_dev *hdev, bool en,
7492                                               enum hnae3_loop loop_mode)
7493 {
7494         struct hclge_common_lb_cmd *req;
7495         struct hclge_desc desc;
7496         u8 loop_mode_b;
7497         int ret;
7498
7499         req = (struct hclge_common_lb_cmd *)desc.data;
7500         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, false);
7501
7502         switch (loop_mode) {
7503         case HNAE3_LOOP_SERIAL_SERDES:
7504                 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
7505                 break;
7506         case HNAE3_LOOP_PARALLEL_SERDES:
7507                 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B;
7508                 break;
7509         case HNAE3_LOOP_PHY:
7510                 loop_mode_b = HCLGE_CMD_GE_PHY_INNER_LOOP_B;
7511                 break;
7512         default:
7513                 dev_err(&hdev->pdev->dev,
7514                         "unsupported loopback mode %d\n", loop_mode);
7515                 return -ENOTSUPP;
7516         }
7517
7518         req->mask = loop_mode_b;
7519         if (en)
7520                 req->enable = loop_mode_b;
7521
7522         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7523         if (ret)
7524                 dev_err(&hdev->pdev->dev,
7525                         "failed to send loopback cmd, loop_mode = %d, ret = %d\n",
7526                         loop_mode, ret);
7527
7528         return ret;
7529 }
7530
7531 static int hclge_cfg_common_loopback_wait(struct hclge_dev *hdev)
7532 {
7533 #define HCLGE_COMMON_LB_RETRY_MS        10
7534 #define HCLGE_COMMON_LB_RETRY_NUM       100
7535
7536         struct hclge_common_lb_cmd *req;
7537         struct hclge_desc desc;
7538         u32 i = 0;
7539         int ret;
7540
7541         req = (struct hclge_common_lb_cmd *)desc.data;
7542
7543         do {
7544                 msleep(HCLGE_COMMON_LB_RETRY_MS);
7545                 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK,
7546                                            true);
7547                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7548                 if (ret) {
7549                         dev_err(&hdev->pdev->dev,
7550                                 "failed to get loopback done status, ret = %d\n",
7551                                 ret);
7552                         return ret;
7553                 }
7554         } while (++i < HCLGE_COMMON_LB_RETRY_NUM &&
7555                  !(req->result & HCLGE_CMD_COMMON_LB_DONE_B));
7556
7557         if (!(req->result & HCLGE_CMD_COMMON_LB_DONE_B)) {
7558                 dev_err(&hdev->pdev->dev, "wait loopback timeout\n");
7559                 return -EBUSY;
7560         } else if (!(req->result & HCLGE_CMD_COMMON_LB_SUCCESS_B)) {
7561                 dev_err(&hdev->pdev->dev, "failed to do loopback test\n");
7562                 return -EIO;
7563         }
7564
7565         return 0;
7566 }
7567
7568 static int hclge_cfg_common_loopback(struct hclge_dev *hdev, bool en,
7569                                      enum hnae3_loop loop_mode)
7570 {
7571         int ret;
7572
7573         ret = hclge_cfg_common_loopback_cmd_send(hdev, en, loop_mode);
7574         if (ret)
7575                 return ret;
7576
7577         return hclge_cfg_common_loopback_wait(hdev);
7578 }
7579
7580 static int hclge_set_common_loopback(struct hclge_dev *hdev, bool en,
7581                                      enum hnae3_loop loop_mode)
7582 {
7583         int ret;
7584
7585         ret = hclge_cfg_common_loopback(hdev, en, loop_mode);
7586         if (ret)
7587                 return ret;
7588
7589         hclge_cfg_mac_mode(hdev, en);
7590
7591         ret = hclge_mac_phy_link_status_wait(hdev, en, false);
7592         if (ret)
7593                 dev_err(&hdev->pdev->dev,
7594                         "serdes loopback config mac mode timeout\n");
7595
7596         return ret;
7597 }
7598
7599 static int hclge_enable_phy_loopback(struct hclge_dev *hdev,
7600                                      struct phy_device *phydev)
7601 {
7602         int ret;
7603
7604         if (!phydev->suspended) {
7605                 ret = phy_suspend(phydev);
7606                 if (ret)
7607                         return ret;
7608         }
7609
7610         ret = phy_resume(phydev);
7611         if (ret)
7612                 return ret;
7613
7614         return phy_loopback(phydev, true);
7615 }
7616
7617 static int hclge_disable_phy_loopback(struct hclge_dev *hdev,
7618                                       struct phy_device *phydev)
7619 {
7620         int ret;
7621
7622         ret = phy_loopback(phydev, false);
7623         if (ret)
7624                 return ret;
7625
7626         return phy_suspend(phydev);
7627 }
7628
7629 static int hclge_set_phy_loopback(struct hclge_dev *hdev, bool en)
7630 {
7631         struct phy_device *phydev = hdev->hw.mac.phydev;
7632         int ret;
7633
7634         if (!phydev) {
7635                 if (hnae3_dev_phy_imp_supported(hdev))
7636                         return hclge_set_common_loopback(hdev, en,
7637                                                          HNAE3_LOOP_PHY);
7638                 return -ENOTSUPP;
7639         }
7640
7641         if (en)
7642                 ret = hclge_enable_phy_loopback(hdev, phydev);
7643         else
7644                 ret = hclge_disable_phy_loopback(hdev, phydev);
7645         if (ret) {
7646                 dev_err(&hdev->pdev->dev,
7647                         "set phy loopback fail, ret = %d\n", ret);
7648                 return ret;
7649         }
7650
7651         hclge_cfg_mac_mode(hdev, en);
7652
7653         ret = hclge_mac_phy_link_status_wait(hdev, en, true);
7654         if (ret)
7655                 dev_err(&hdev->pdev->dev,
7656                         "phy loopback config mac mode timeout\n");
7657
7658         return ret;
7659 }
7660
7661 static int hclge_tqp_enable_cmd_send(struct hclge_dev *hdev, u16 tqp_id,
7662                                      u16 stream_id, bool enable)
7663 {
7664         struct hclge_desc desc;
7665         struct hclge_cfg_com_tqp_queue_cmd *req =
7666                 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
7667
7668         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
7669         req->tqp_id = cpu_to_le16(tqp_id);
7670         req->stream_id = cpu_to_le16(stream_id);
7671         if (enable)
7672                 req->enable |= 1U << HCLGE_TQP_ENABLE_B;
7673
7674         return hclge_cmd_send(&hdev->hw, &desc, 1);
7675 }
7676
7677 static int hclge_tqp_enable(struct hnae3_handle *handle, bool enable)
7678 {
7679         struct hclge_vport *vport = hclge_get_vport(handle);
7680         struct hclge_dev *hdev = vport->back;
7681         int ret;
7682         u16 i;
7683
7684         for (i = 0; i < handle->kinfo.num_tqps; i++) {
7685                 ret = hclge_tqp_enable_cmd_send(hdev, i, 0, enable);
7686                 if (ret)
7687                         return ret;
7688         }
7689         return 0;
7690 }
7691
7692 static int hclge_set_loopback(struct hnae3_handle *handle,
7693                               enum hnae3_loop loop_mode, bool en)
7694 {
7695         struct hclge_vport *vport = hclge_get_vport(handle);
7696         struct hclge_dev *hdev = vport->back;
7697         int ret;
7698
7699         /* Loopback can be enabled in three places: SSU, MAC, and serdes. By
7700          * default, SSU loopback is enabled, so if the SMAC and the DMAC are
7701          * the same, the packets are looped back in the SSU. If SSU loopback
7702          * is disabled, packets can reach MAC even if SMAC is the same as DMAC.
7703          */
7704         if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
7705                 u8 switch_param = en ? 0 : BIT(HCLGE_SWITCH_ALW_LPBK_B);
7706
7707                 ret = hclge_config_switch_param(hdev, PF_VPORT_ID, switch_param,
7708                                                 HCLGE_SWITCH_ALW_LPBK_MASK);
7709                 if (ret)
7710                         return ret;
7711         }
7712
7713         switch (loop_mode) {
7714         case HNAE3_LOOP_APP:
7715                 ret = hclge_set_app_loopback(hdev, en);
7716                 break;
7717         case HNAE3_LOOP_SERIAL_SERDES:
7718         case HNAE3_LOOP_PARALLEL_SERDES:
7719                 ret = hclge_set_common_loopback(hdev, en, loop_mode);
7720                 break;
7721         case HNAE3_LOOP_PHY:
7722                 ret = hclge_set_phy_loopback(hdev, en);
7723                 break;
7724         default:
7725                 ret = -ENOTSUPP;
7726                 dev_err(&hdev->pdev->dev,
7727                         "loop_mode %d is not supported\n", loop_mode);
7728                 break;
7729         }
7730
7731         if (ret)
7732                 return ret;
7733
7734         ret = hclge_tqp_enable(handle, en);
7735         if (ret)
7736                 dev_err(&hdev->pdev->dev, "failed to %s tqp in loopback, ret = %d\n",
7737                         en ? "enable" : "disable", ret);
7738
7739         return ret;
7740 }
7741
7742 static int hclge_set_default_loopback(struct hclge_dev *hdev)
7743 {
7744         int ret;
7745
7746         ret = hclge_set_app_loopback(hdev, false);
7747         if (ret)
7748                 return ret;
7749
7750         ret = hclge_cfg_common_loopback(hdev, false, HNAE3_LOOP_SERIAL_SERDES);
7751         if (ret)
7752                 return ret;
7753
7754         return hclge_cfg_common_loopback(hdev, false,
7755                                          HNAE3_LOOP_PARALLEL_SERDES);
7756 }
7757
7758 static void hclge_flush_link_update(struct hclge_dev *hdev)
7759 {
7760 #define HCLGE_FLUSH_LINK_TIMEOUT        100000
7761
7762         unsigned long last = hdev->serv_processed_cnt;
7763         int i = 0;
7764
7765         while (test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state) &&
7766                i++ < HCLGE_FLUSH_LINK_TIMEOUT &&
7767                last == hdev->serv_processed_cnt)
7768                 usleep_range(1, 1);
7769 }
7770
7771 static void hclge_set_timer_task(struct hnae3_handle *handle, bool enable)
7772 {
7773         struct hclge_vport *vport = hclge_get_vport(handle);
7774         struct hclge_dev *hdev = vport->back;
7775
7776         if (enable) {
7777                 hclge_task_schedule(hdev, 0);
7778         } else {
7779                 /* Set the DOWN flag here to disable link updating */
7780                 set_bit(HCLGE_STATE_DOWN, &hdev->state);
7781
7782                 /* flush memory to make sure DOWN is seen by service task */
7783                 smp_mb__before_atomic();
7784                 hclge_flush_link_update(hdev);
7785         }
7786 }
7787
7788 static int hclge_ae_start(struct hnae3_handle *handle)
7789 {
7790         struct hclge_vport *vport = hclge_get_vport(handle);
7791         struct hclge_dev *hdev = vport->back;
7792
7793         /* mac enable */
7794         hclge_cfg_mac_mode(hdev, true);
7795         clear_bit(HCLGE_STATE_DOWN, &hdev->state);
7796         hdev->hw.mac.link = 0;
7797
7798         /* reset tqp stats */
7799         hclge_comm_reset_tqp_stats(handle);
7800
7801         hclge_mac_start_phy(hdev);
7802
7803         return 0;
7804 }
7805
7806 static void hclge_ae_stop(struct hnae3_handle *handle)
7807 {
7808         struct hclge_vport *vport = hclge_get_vport(handle);
7809         struct hclge_dev *hdev = vport->back;
7810
7811         set_bit(HCLGE_STATE_DOWN, &hdev->state);
7812         spin_lock_bh(&hdev->fd_rule_lock);
7813         hclge_clear_arfs_rules(hdev);
7814         spin_unlock_bh(&hdev->fd_rule_lock);
7815
7816         /* If it is not PF reset or FLR, the firmware will disable the MAC,
7817          * so it only need to stop phy here.
7818          */
7819         if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) &&
7820             hdev->reset_type != HNAE3_FUNC_RESET &&
7821             hdev->reset_type != HNAE3_FLR_RESET) {
7822                 hclge_mac_stop_phy(hdev);
7823                 hclge_update_link_status(hdev);
7824                 return;
7825         }
7826
7827         hclge_reset_tqp(handle);
7828
7829         hclge_config_mac_tnl_int(hdev, false);
7830
7831         /* Mac disable */
7832         hclge_cfg_mac_mode(hdev, false);
7833
7834         hclge_mac_stop_phy(hdev);
7835
7836         /* reset tqp stats */
7837         hclge_comm_reset_tqp_stats(handle);
7838         hclge_update_link_status(hdev);
7839 }
7840
7841 int hclge_vport_start(struct hclge_vport *vport)
7842 {
7843         struct hclge_dev *hdev = vport->back;
7844
7845         set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
7846         set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
7847         vport->last_active_jiffies = jiffies;
7848
7849         if (test_bit(vport->vport_id, hdev->vport_config_block)) {
7850                 if (vport->vport_id) {
7851                         hclge_restore_mac_table_common(vport);
7852                         hclge_restore_vport_vlan_table(vport);
7853                 } else {
7854                         hclge_restore_hw_table(hdev);
7855                 }
7856         }
7857
7858         clear_bit(vport->vport_id, hdev->vport_config_block);
7859
7860         return 0;
7861 }
7862
7863 void hclge_vport_stop(struct hclge_vport *vport)
7864 {
7865         clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
7866 }
7867
7868 static int hclge_client_start(struct hnae3_handle *handle)
7869 {
7870         struct hclge_vport *vport = hclge_get_vport(handle);
7871
7872         return hclge_vport_start(vport);
7873 }
7874
7875 static void hclge_client_stop(struct hnae3_handle *handle)
7876 {
7877         struct hclge_vport *vport = hclge_get_vport(handle);
7878
7879         hclge_vport_stop(vport);
7880 }
7881
7882 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
7883                                          u16 cmdq_resp, u8  resp_code,
7884                                          enum hclge_mac_vlan_tbl_opcode op)
7885 {
7886         struct hclge_dev *hdev = vport->back;
7887
7888         if (cmdq_resp) {
7889                 dev_err(&hdev->pdev->dev,
7890                         "cmdq execute failed for get_mac_vlan_cmd_status,status=%u.\n",
7891                         cmdq_resp);
7892                 return -EIO;
7893         }
7894
7895         if (op == HCLGE_MAC_VLAN_ADD) {
7896                 if (!resp_code || resp_code == 1)
7897                         return 0;
7898                 else if (resp_code == HCLGE_ADD_UC_OVERFLOW ||
7899                          resp_code == HCLGE_ADD_MC_OVERFLOW)
7900                         return -ENOSPC;
7901
7902                 dev_err(&hdev->pdev->dev,
7903                         "add mac addr failed for undefined, code=%u.\n",
7904                         resp_code);
7905                 return -EIO;
7906         } else if (op == HCLGE_MAC_VLAN_REMOVE) {
7907                 if (!resp_code) {
7908                         return 0;
7909                 } else if (resp_code == 1) {
7910                         dev_dbg(&hdev->pdev->dev,
7911                                 "remove mac addr failed for miss.\n");
7912                         return -ENOENT;
7913                 }
7914
7915                 dev_err(&hdev->pdev->dev,
7916                         "remove mac addr failed for undefined, code=%u.\n",
7917                         resp_code);
7918                 return -EIO;
7919         } else if (op == HCLGE_MAC_VLAN_LKUP) {
7920                 if (!resp_code) {
7921                         return 0;
7922                 } else if (resp_code == 1) {
7923                         dev_dbg(&hdev->pdev->dev,
7924                                 "lookup mac addr failed for miss.\n");
7925                         return -ENOENT;
7926                 }
7927
7928                 dev_err(&hdev->pdev->dev,
7929                         "lookup mac addr failed for undefined, code=%u.\n",
7930                         resp_code);
7931                 return -EIO;
7932         }
7933
7934         dev_err(&hdev->pdev->dev,
7935                 "unknown opcode for get_mac_vlan_cmd_status, opcode=%d.\n", op);
7936
7937         return -EINVAL;
7938 }
7939
7940 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
7941 {
7942 #define HCLGE_VF_NUM_IN_FIRST_DESC 192
7943
7944         unsigned int word_num;
7945         unsigned int bit_num;
7946
7947         if (vfid > 255 || vfid < 0)
7948                 return -EIO;
7949
7950         if (vfid >= 0 && vfid < HCLGE_VF_NUM_IN_FIRST_DESC) {
7951                 word_num = vfid / 32;
7952                 bit_num  = vfid % 32;
7953                 if (clr)
7954                         desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
7955                 else
7956                         desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
7957         } else {
7958                 word_num = (vfid - HCLGE_VF_NUM_IN_FIRST_DESC) / 32;
7959                 bit_num  = vfid % 32;
7960                 if (clr)
7961                         desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
7962                 else
7963                         desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
7964         }
7965
7966         return 0;
7967 }
7968
7969 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
7970 {
7971 #define HCLGE_DESC_NUMBER 3
7972 #define HCLGE_FUNC_NUMBER_PER_DESC 6
7973         int i, j;
7974
7975         for (i = 1; i < HCLGE_DESC_NUMBER; i++)
7976                 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
7977                         if (desc[i].data[j])
7978                                 return false;
7979
7980         return true;
7981 }
7982
7983 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
7984                                    const u8 *addr, bool is_mc)
7985 {
7986         const unsigned char *mac_addr = addr;
7987         u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
7988                        (mac_addr[0]) | (mac_addr[1] << 8);
7989         u32 low_val  = mac_addr[4] | (mac_addr[5] << 8);
7990
7991         hnae3_set_bit(new_req->flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
7992         if (is_mc) {
7993                 hnae3_set_bit(new_req->entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
7994                 hnae3_set_bit(new_req->mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
7995         }
7996
7997         new_req->mac_addr_hi32 = cpu_to_le32(high_val);
7998         new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
7999 }
8000
8001 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
8002                                      struct hclge_mac_vlan_tbl_entry_cmd *req)
8003 {
8004         struct hclge_dev *hdev = vport->back;
8005         struct hclge_desc desc;
8006         u8 resp_code;
8007         u16 retval;
8008         int ret;
8009
8010         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
8011
8012         memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
8013
8014         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
8015         if (ret) {
8016                 dev_err(&hdev->pdev->dev,
8017                         "del mac addr failed for cmd_send, ret =%d.\n",
8018                         ret);
8019                 return ret;
8020         }
8021         resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
8022         retval = le16_to_cpu(desc.retval);
8023
8024         return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
8025                                              HCLGE_MAC_VLAN_REMOVE);
8026 }
8027
8028 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
8029                                      struct hclge_mac_vlan_tbl_entry_cmd *req,
8030                                      struct hclge_desc *desc,
8031                                      bool is_mc)
8032 {
8033         struct hclge_dev *hdev = vport->back;
8034         u8 resp_code;
8035         u16 retval;
8036         int ret;
8037
8038         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
8039         if (is_mc) {
8040                 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
8041                 memcpy(desc[0].data,
8042                        req,
8043                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
8044                 hclge_cmd_setup_basic_desc(&desc[1],
8045                                            HCLGE_OPC_MAC_VLAN_ADD,
8046                                            true);
8047                 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
8048                 hclge_cmd_setup_basic_desc(&desc[2],
8049                                            HCLGE_OPC_MAC_VLAN_ADD,
8050                                            true);
8051                 ret = hclge_cmd_send(&hdev->hw, desc, 3);
8052         } else {
8053                 memcpy(desc[0].data,
8054                        req,
8055                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
8056                 ret = hclge_cmd_send(&hdev->hw, desc, 1);
8057         }
8058         if (ret) {
8059                 dev_err(&hdev->pdev->dev,
8060                         "lookup mac addr failed for cmd_send, ret =%d.\n",
8061                         ret);
8062                 return ret;
8063         }
8064         resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
8065         retval = le16_to_cpu(desc[0].retval);
8066
8067         return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
8068                                              HCLGE_MAC_VLAN_LKUP);
8069 }
8070
8071 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
8072                                   struct hclge_mac_vlan_tbl_entry_cmd *req,
8073                                   struct hclge_desc *mc_desc)
8074 {
8075         struct hclge_dev *hdev = vport->back;
8076         int cfg_status;
8077         u8 resp_code;
8078         u16 retval;
8079         int ret;
8080
8081         if (!mc_desc) {
8082                 struct hclge_desc desc;
8083
8084                 hclge_cmd_setup_basic_desc(&desc,
8085                                            HCLGE_OPC_MAC_VLAN_ADD,
8086                                            false);
8087                 memcpy(desc.data, req,
8088                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
8089                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
8090                 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
8091                 retval = le16_to_cpu(desc.retval);
8092
8093                 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
8094                                                            resp_code,
8095                                                            HCLGE_MAC_VLAN_ADD);
8096         } else {
8097                 hclge_comm_cmd_reuse_desc(&mc_desc[0], false);
8098                 mc_desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
8099                 hclge_comm_cmd_reuse_desc(&mc_desc[1], false);
8100                 mc_desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
8101                 hclge_comm_cmd_reuse_desc(&mc_desc[2], false);
8102                 mc_desc[2].flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_NEXT);
8103                 memcpy(mc_desc[0].data, req,
8104                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
8105                 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
8106                 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
8107                 retval = le16_to_cpu(mc_desc[0].retval);
8108
8109                 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
8110                                                            resp_code,
8111                                                            HCLGE_MAC_VLAN_ADD);
8112         }
8113
8114         if (ret) {
8115                 dev_err(&hdev->pdev->dev,
8116                         "add mac addr failed for cmd_send, ret =%d.\n",
8117                         ret);
8118                 return ret;
8119         }
8120
8121         return cfg_status;
8122 }
8123
8124 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size,
8125                                u16 *allocated_size)
8126 {
8127         struct hclge_umv_spc_alc_cmd *req;
8128         struct hclge_desc desc;
8129         int ret;
8130
8131         req = (struct hclge_umv_spc_alc_cmd *)desc.data;
8132         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false);
8133
8134         req->space_size = cpu_to_le32(space_size);
8135
8136         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
8137         if (ret) {
8138                 dev_err(&hdev->pdev->dev, "failed to set umv space, ret = %d\n",
8139                         ret);
8140                 return ret;
8141         }
8142
8143         *allocated_size = le32_to_cpu(desc.data[1]);
8144
8145         return 0;
8146 }
8147
8148 static int hclge_init_umv_space(struct hclge_dev *hdev)
8149 {
8150         u16 allocated_size = 0;
8151         int ret;
8152
8153         ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size);
8154         if (ret)
8155                 return ret;
8156
8157         if (allocated_size < hdev->wanted_umv_size)
8158                 dev_warn(&hdev->pdev->dev,
8159                          "failed to alloc umv space, want %u, get %u\n",
8160                          hdev->wanted_umv_size, allocated_size);
8161
8162         hdev->max_umv_size = allocated_size;
8163         hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_alloc_vport + 1);
8164         hdev->share_umv_size = hdev->priv_umv_size +
8165                         hdev->max_umv_size % (hdev->num_alloc_vport + 1);
8166
8167         if (hdev->ae_dev->dev_specs.mc_mac_size)
8168                 set_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, hdev->ae_dev->caps);
8169
8170         return 0;
8171 }
8172
8173 static void hclge_reset_umv_space(struct hclge_dev *hdev)
8174 {
8175         struct hclge_vport *vport;
8176         int i;
8177
8178         for (i = 0; i < hdev->num_alloc_vport; i++) {
8179                 vport = &hdev->vport[i];
8180                 vport->used_umv_num = 0;
8181         }
8182
8183         mutex_lock(&hdev->vport_lock);
8184         hdev->share_umv_size = hdev->priv_umv_size +
8185                         hdev->max_umv_size % (hdev->num_alloc_vport + 1);
8186         mutex_unlock(&hdev->vport_lock);
8187
8188         hdev->used_mc_mac_num = 0;
8189 }
8190
8191 static bool hclge_is_umv_space_full(struct hclge_vport *vport, bool need_lock)
8192 {
8193         struct hclge_dev *hdev = vport->back;
8194         bool is_full;
8195
8196         if (need_lock)
8197                 mutex_lock(&hdev->vport_lock);
8198
8199         is_full = (vport->used_umv_num >= hdev->priv_umv_size &&
8200                    hdev->share_umv_size == 0);
8201
8202         if (need_lock)
8203                 mutex_unlock(&hdev->vport_lock);
8204
8205         return is_full;
8206 }
8207
8208 static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free)
8209 {
8210         struct hclge_dev *hdev = vport->back;
8211
8212         if (is_free) {
8213                 if (vport->used_umv_num > hdev->priv_umv_size)
8214                         hdev->share_umv_size++;
8215
8216                 if (vport->used_umv_num > 0)
8217                         vport->used_umv_num--;
8218         } else {
8219                 if (vport->used_umv_num >= hdev->priv_umv_size &&
8220                     hdev->share_umv_size > 0)
8221                         hdev->share_umv_size--;
8222                 vport->used_umv_num++;
8223         }
8224 }
8225
8226 static struct hclge_mac_node *hclge_find_mac_node(struct list_head *list,
8227                                                   const u8 *mac_addr)
8228 {
8229         struct hclge_mac_node *mac_node, *tmp;
8230
8231         list_for_each_entry_safe(mac_node, tmp, list, node)
8232                 if (ether_addr_equal(mac_addr, mac_node->mac_addr))
8233                         return mac_node;
8234
8235         return NULL;
8236 }
8237
8238 static void hclge_update_mac_node(struct hclge_mac_node *mac_node,
8239                                   enum HCLGE_MAC_NODE_STATE state)
8240 {
8241         switch (state) {
8242         /* from set_rx_mode or tmp_add_list */
8243         case HCLGE_MAC_TO_ADD:
8244                 if (mac_node->state == HCLGE_MAC_TO_DEL)
8245                         mac_node->state = HCLGE_MAC_ACTIVE;
8246                 break;
8247         /* only from set_rx_mode */
8248         case HCLGE_MAC_TO_DEL:
8249                 if (mac_node->state == HCLGE_MAC_TO_ADD) {
8250                         list_del(&mac_node->node);
8251                         kfree(mac_node);
8252                 } else {
8253                         mac_node->state = HCLGE_MAC_TO_DEL;
8254                 }
8255                 break;
8256         /* only from tmp_add_list, the mac_node->state won't be
8257          * ACTIVE.
8258          */
8259         case HCLGE_MAC_ACTIVE:
8260                 if (mac_node->state == HCLGE_MAC_TO_ADD)
8261                         mac_node->state = HCLGE_MAC_ACTIVE;
8262
8263                 break;
8264         }
8265 }
8266
8267 int hclge_update_mac_list(struct hclge_vport *vport,
8268                           enum HCLGE_MAC_NODE_STATE state,
8269                           enum HCLGE_MAC_ADDR_TYPE mac_type,
8270                           const unsigned char *addr)
8271 {
8272         char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
8273         struct hclge_dev *hdev = vport->back;
8274         struct hclge_mac_node *mac_node;
8275         struct list_head *list;
8276
8277         list = (mac_type == HCLGE_MAC_ADDR_UC) ?
8278                 &vport->uc_mac_list : &vport->mc_mac_list;
8279
8280         spin_lock_bh(&vport->mac_list_lock);
8281
8282         /* if the mac addr is already in the mac list, no need to add a new
8283          * one into it, just check the mac addr state, convert it to a new
8284          * state, or just remove it, or do nothing.
8285          */
8286         mac_node = hclge_find_mac_node(list, addr);
8287         if (mac_node) {
8288                 hclge_update_mac_node(mac_node, state);
8289                 spin_unlock_bh(&vport->mac_list_lock);
8290                 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state);
8291                 return 0;
8292         }
8293
8294         /* if this address is never added, unnecessary to delete */
8295         if (state == HCLGE_MAC_TO_DEL) {
8296                 spin_unlock_bh(&vport->mac_list_lock);
8297                 hnae3_format_mac_addr(format_mac_addr, addr);
8298                 dev_err(&hdev->pdev->dev,
8299                         "failed to delete address %s from mac list\n",
8300                         format_mac_addr);
8301                 return -ENOENT;
8302         }
8303
8304         mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC);
8305         if (!mac_node) {
8306                 spin_unlock_bh(&vport->mac_list_lock);
8307                 return -ENOMEM;
8308         }
8309
8310         set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state);
8311
8312         mac_node->state = state;
8313         ether_addr_copy(mac_node->mac_addr, addr);
8314         list_add_tail(&mac_node->node, list);
8315
8316         spin_unlock_bh(&vport->mac_list_lock);
8317
8318         return 0;
8319 }
8320
8321 static int hclge_add_uc_addr(struct hnae3_handle *handle,
8322                              const unsigned char *addr)
8323 {
8324         struct hclge_vport *vport = hclge_get_vport(handle);
8325
8326         return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_UC,
8327                                      addr);
8328 }
8329
8330 int hclge_add_uc_addr_common(struct hclge_vport *vport,
8331                              const unsigned char *addr)
8332 {
8333         char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
8334         struct hclge_dev *hdev = vport->back;
8335         struct hclge_mac_vlan_tbl_entry_cmd req;
8336         struct hclge_desc desc;
8337         u16 egress_port = 0;
8338         int ret;
8339
8340         /* mac addr check */
8341         if (is_zero_ether_addr(addr) ||
8342             is_broadcast_ether_addr(addr) ||
8343             is_multicast_ether_addr(addr)) {
8344                 hnae3_format_mac_addr(format_mac_addr, addr);
8345                 dev_err(&hdev->pdev->dev,
8346                         "Set_uc mac err! invalid mac:%s. is_zero:%d,is_br=%d,is_mul=%d\n",
8347                          format_mac_addr, is_zero_ether_addr(addr),
8348                          is_broadcast_ether_addr(addr),
8349                          is_multicast_ether_addr(addr));
8350                 return -EINVAL;
8351         }
8352
8353         memset(&req, 0, sizeof(req));
8354
8355         hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
8356                         HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
8357
8358         req.egress_port = cpu_to_le16(egress_port);
8359
8360         hclge_prepare_mac_addr(&req, addr, false);
8361
8362         /* Lookup the mac address in the mac_vlan table, and add
8363          * it if the entry is inexistent. Repeated unicast entry
8364          * is not allowed in the mac vlan table.
8365          */
8366         ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false);
8367         if (ret == -ENOENT) {
8368                 mutex_lock(&hdev->vport_lock);
8369                 if (!hclge_is_umv_space_full(vport, false)) {
8370                         ret = hclge_add_mac_vlan_tbl(vport, &req, NULL);
8371                         if (!ret)
8372                                 hclge_update_umv_space(vport, false);
8373                         mutex_unlock(&hdev->vport_lock);
8374                         return ret;
8375                 }
8376                 mutex_unlock(&hdev->vport_lock);
8377
8378                 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE))
8379                         dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n",
8380                                 hdev->priv_umv_size);
8381
8382                 return -ENOSPC;
8383         }
8384
8385         /* check if we just hit the duplicate */
8386         if (!ret)
8387                 return -EEXIST;
8388
8389         return ret;
8390 }
8391
8392 static int hclge_rm_uc_addr(struct hnae3_handle *handle,
8393                             const unsigned char *addr)
8394 {
8395         struct hclge_vport *vport = hclge_get_vport(handle);
8396
8397         return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_UC,
8398                                      addr);
8399 }
8400
8401 int hclge_rm_uc_addr_common(struct hclge_vport *vport,
8402                             const unsigned char *addr)
8403 {
8404         char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
8405         struct hclge_dev *hdev = vport->back;
8406         struct hclge_mac_vlan_tbl_entry_cmd req;
8407         int ret;
8408
8409         /* mac addr check */
8410         if (is_zero_ether_addr(addr) ||
8411             is_broadcast_ether_addr(addr) ||
8412             is_multicast_ether_addr(addr)) {
8413                 hnae3_format_mac_addr(format_mac_addr, addr);
8414                 dev_dbg(&hdev->pdev->dev, "Remove mac err! invalid mac:%s.\n",
8415                         format_mac_addr);
8416                 return -EINVAL;
8417         }
8418
8419         memset(&req, 0, sizeof(req));
8420         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
8421         hclge_prepare_mac_addr(&req, addr, false);
8422         ret = hclge_remove_mac_vlan_tbl(vport, &req);
8423         if (!ret || ret == -ENOENT) {
8424                 mutex_lock(&hdev->vport_lock);
8425                 hclge_update_umv_space(vport, true);
8426                 mutex_unlock(&hdev->vport_lock);
8427                 return 0;
8428         }
8429
8430         return ret;
8431 }
8432
8433 static int hclge_add_mc_addr(struct hnae3_handle *handle,
8434                              const unsigned char *addr)
8435 {
8436         struct hclge_vport *vport = hclge_get_vport(handle);
8437
8438         return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_MC,
8439                                      addr);
8440 }
8441
8442 int hclge_add_mc_addr_common(struct hclge_vport *vport,
8443                              const unsigned char *addr)
8444 {
8445         char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
8446         struct hclge_dev *hdev = vport->back;
8447         struct hclge_mac_vlan_tbl_entry_cmd req;
8448         struct hclge_desc desc[3];
8449         bool is_new_addr = false;
8450         int status;
8451
8452         /* mac addr check */
8453         if (!is_multicast_ether_addr(addr)) {
8454                 hnae3_format_mac_addr(format_mac_addr, addr);
8455                 dev_err(&hdev->pdev->dev,
8456                         "Add mc mac err! invalid mac:%s.\n",
8457                          format_mac_addr);
8458                 return -EINVAL;
8459         }
8460         memset(&req, 0, sizeof(req));
8461         hclge_prepare_mac_addr(&req, addr, true);
8462         status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
8463         if (status) {
8464                 if (hnae3_ae_dev_mc_mac_mng_supported(hdev->ae_dev) &&
8465                     hdev->used_mc_mac_num >=
8466                     hdev->ae_dev->dev_specs.mc_mac_size)
8467                         goto err_no_space;
8468
8469                 is_new_addr = true;
8470
8471                 /* This mac addr do not exist, add new entry for it */
8472                 memset(desc[0].data, 0, sizeof(desc[0].data));
8473                 memset(desc[1].data, 0, sizeof(desc[0].data));
8474                 memset(desc[2].data, 0, sizeof(desc[0].data));
8475         }
8476         status = hclge_update_desc_vfid(desc, vport->vport_id, false);
8477         if (status)
8478                 return status;
8479         status = hclge_add_mac_vlan_tbl(vport, &req, desc);
8480         if (status == -ENOSPC)
8481                 goto err_no_space;
8482         else if (!status && is_new_addr)
8483                 hdev->used_mc_mac_num++;
8484
8485         return status;
8486
8487 err_no_space:
8488         /* if already overflow, not to print each time */
8489         if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE)) {
8490                 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE;
8491                 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n");
8492         }
8493
8494         return -ENOSPC;
8495 }
8496
8497 static int hclge_rm_mc_addr(struct hnae3_handle *handle,
8498                             const unsigned char *addr)
8499 {
8500         struct hclge_vport *vport = hclge_get_vport(handle);
8501
8502         return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_MC,
8503                                      addr);
8504 }
8505
8506 int hclge_rm_mc_addr_common(struct hclge_vport *vport,
8507                             const unsigned char *addr)
8508 {
8509         char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
8510         struct hclge_dev *hdev = vport->back;
8511         struct hclge_mac_vlan_tbl_entry_cmd req;
8512         enum hclge_comm_cmd_status status;
8513         struct hclge_desc desc[3];
8514
8515         /* mac addr check */
8516         if (!is_multicast_ether_addr(addr)) {
8517                 hnae3_format_mac_addr(format_mac_addr, addr);
8518                 dev_dbg(&hdev->pdev->dev,
8519                         "Remove mc mac err! invalid mac:%s.\n",
8520                          format_mac_addr);
8521                 return -EINVAL;
8522         }
8523
8524         memset(&req, 0, sizeof(req));
8525         hclge_prepare_mac_addr(&req, addr, true);
8526         status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
8527         if (!status) {
8528                 /* This mac addr exist, remove this handle's VFID for it */
8529                 status = hclge_update_desc_vfid(desc, vport->vport_id, true);
8530                 if (status)
8531                         return status;
8532
8533                 if (hclge_is_all_function_id_zero(desc)) {
8534                         /* All the vfid is zero, so need to delete this entry */
8535                         status = hclge_remove_mac_vlan_tbl(vport, &req);
8536                         if (!status)
8537                                 hdev->used_mc_mac_num--;
8538                 } else {
8539                         /* Not all the vfid is zero, update the vfid */
8540                         status = hclge_add_mac_vlan_tbl(vport, &req, desc);
8541                 }
8542         } else if (status == -ENOENT) {
8543                 status = 0;
8544         }
8545
8546         return status;
8547 }
8548
8549 static void hclge_sync_vport_mac_list(struct hclge_vport *vport,
8550                                       struct list_head *list,
8551                                       enum HCLGE_MAC_ADDR_TYPE mac_type)
8552 {
8553         int (*sync)(struct hclge_vport *vport, const unsigned char *addr);
8554         struct hclge_mac_node *mac_node, *tmp;
8555         int ret;
8556
8557         if (mac_type == HCLGE_MAC_ADDR_UC)
8558                 sync = hclge_add_uc_addr_common;
8559         else
8560                 sync = hclge_add_mc_addr_common;
8561
8562         list_for_each_entry_safe(mac_node, tmp, list, node) {
8563                 ret = sync(vport, mac_node->mac_addr);
8564                 if (!ret) {
8565                         mac_node->state = HCLGE_MAC_ACTIVE;
8566                 } else {
8567                         set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE,
8568                                 &vport->state);
8569
8570                         /* If one unicast mac address is existing in hardware,
8571                          * we need to try whether other unicast mac addresses
8572                          * are new addresses that can be added.
8573                          * Multicast mac address can be reusable, even though
8574                          * there is no space to add new multicast mac address,
8575                          * we should check whether other mac addresses are
8576                          * existing in hardware for reuse.
8577                          */
8578                         if ((mac_type == HCLGE_MAC_ADDR_UC && ret != -EEXIST) ||
8579                             (mac_type == HCLGE_MAC_ADDR_MC && ret != -ENOSPC))
8580                                 break;
8581                 }
8582         }
8583 }
8584
8585 static void hclge_unsync_vport_mac_list(struct hclge_vport *vport,
8586                                         struct list_head *list,
8587                                         enum HCLGE_MAC_ADDR_TYPE mac_type)
8588 {
8589         int (*unsync)(struct hclge_vport *vport, const unsigned char *addr);
8590         struct hclge_mac_node *mac_node, *tmp;
8591         int ret;
8592
8593         if (mac_type == HCLGE_MAC_ADDR_UC)
8594                 unsync = hclge_rm_uc_addr_common;
8595         else
8596                 unsync = hclge_rm_mc_addr_common;
8597
8598         list_for_each_entry_safe(mac_node, tmp, list, node) {
8599                 ret = unsync(vport, mac_node->mac_addr);
8600                 if (!ret || ret == -ENOENT) {
8601                         list_del(&mac_node->node);
8602                         kfree(mac_node);
8603                 } else {
8604                         set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE,
8605                                 &vport->state);
8606                         break;
8607                 }
8608         }
8609 }
8610
8611 static bool hclge_sync_from_add_list(struct list_head *add_list,
8612                                      struct list_head *mac_list)
8613 {
8614         struct hclge_mac_node *mac_node, *tmp, *new_node;
8615         bool all_added = true;
8616
8617         list_for_each_entry_safe(mac_node, tmp, add_list, node) {
8618                 if (mac_node->state == HCLGE_MAC_TO_ADD)
8619                         all_added = false;
8620
8621                 /* if the mac address from tmp_add_list is not in the
8622                  * uc/mc_mac_list, it means have received a TO_DEL request
8623                  * during the time window of adding the mac address into mac
8624                  * table. if mac_node state is ACTIVE, then change it to TO_DEL,
8625                  * then it will be removed at next time. else it must be TO_ADD,
8626                  * this address hasn't been added into mac table,
8627                  * so just remove the mac node.
8628                  */
8629                 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr);
8630                 if (new_node) {
8631                         hclge_update_mac_node(new_node, mac_node->state);
8632                         list_del(&mac_node->node);
8633                         kfree(mac_node);
8634                 } else if (mac_node->state == HCLGE_MAC_ACTIVE) {
8635                         mac_node->state = HCLGE_MAC_TO_DEL;
8636                         list_move_tail(&mac_node->node, mac_list);
8637                 } else {
8638                         list_del(&mac_node->node);
8639                         kfree(mac_node);
8640                 }
8641         }
8642
8643         return all_added;
8644 }
8645
8646 static void hclge_sync_from_del_list(struct list_head *del_list,
8647                                      struct list_head *mac_list)
8648 {
8649         struct hclge_mac_node *mac_node, *tmp, *new_node;
8650
8651         list_for_each_entry_safe(mac_node, tmp, del_list, node) {
8652                 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr);
8653                 if (new_node) {
8654                         /* If the mac addr exists in the mac list, it means
8655                          * received a new TO_ADD request during the time window
8656                          * of configuring the mac address. For the mac node
8657                          * state is TO_ADD, and the address is already in the
8658                          * in the hardware(due to delete fail), so we just need
8659                          * to change the mac node state to ACTIVE.
8660                          */
8661                         new_node->state = HCLGE_MAC_ACTIVE;
8662                         list_del(&mac_node->node);
8663                         kfree(mac_node);
8664                 } else {
8665                         list_move_tail(&mac_node->node, mac_list);
8666                 }
8667         }
8668 }
8669
8670 static void hclge_update_overflow_flags(struct hclge_vport *vport,
8671                                         enum HCLGE_MAC_ADDR_TYPE mac_type,
8672                                         bool is_all_added)
8673 {
8674         if (mac_type == HCLGE_MAC_ADDR_UC) {
8675                 if (is_all_added)
8676                         vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_UPE;
8677                 else
8678                         vport->overflow_promisc_flags |= HNAE3_OVERFLOW_UPE;
8679         } else {
8680                 if (is_all_added)
8681                         vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_MPE;
8682                 else
8683                         vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE;
8684         }
8685 }
8686
8687 static void hclge_sync_vport_mac_table(struct hclge_vport *vport,
8688                                        enum HCLGE_MAC_ADDR_TYPE mac_type)
8689 {
8690         struct hclge_mac_node *mac_node, *tmp, *new_node;
8691         struct list_head tmp_add_list, tmp_del_list;
8692         struct list_head *list;
8693         bool all_added;
8694
8695         INIT_LIST_HEAD(&tmp_add_list);
8696         INIT_LIST_HEAD(&tmp_del_list);
8697
8698         /* move the mac addr to the tmp_add_list and tmp_del_list, then
8699          * we can add/delete these mac addr outside the spin lock
8700          */
8701         list = (mac_type == HCLGE_MAC_ADDR_UC) ?
8702                 &vport->uc_mac_list : &vport->mc_mac_list;
8703
8704         spin_lock_bh(&vport->mac_list_lock);
8705
8706         list_for_each_entry_safe(mac_node, tmp, list, node) {
8707                 switch (mac_node->state) {
8708                 case HCLGE_MAC_TO_DEL:
8709                         list_move_tail(&mac_node->node, &tmp_del_list);
8710                         break;
8711                 case HCLGE_MAC_TO_ADD:
8712                         new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC);
8713                         if (!new_node)
8714                                 goto stop_traverse;
8715                         ether_addr_copy(new_node->mac_addr, mac_node->mac_addr);
8716                         new_node->state = mac_node->state;
8717                         list_add_tail(&new_node->node, &tmp_add_list);
8718                         break;
8719                 default:
8720                         break;
8721                 }
8722         }
8723
8724 stop_traverse:
8725         spin_unlock_bh(&vport->mac_list_lock);
8726
8727         /* delete first, in order to get max mac table space for adding */
8728         hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type);
8729         hclge_sync_vport_mac_list(vport, &tmp_add_list, mac_type);
8730
8731         /* if some mac addresses were added/deleted fail, move back to the
8732          * mac_list, and retry at next time.
8733          */
8734         spin_lock_bh(&vport->mac_list_lock);
8735
8736         hclge_sync_from_del_list(&tmp_del_list, list);
8737         all_added = hclge_sync_from_add_list(&tmp_add_list, list);
8738
8739         spin_unlock_bh(&vport->mac_list_lock);
8740
8741         hclge_update_overflow_flags(vport, mac_type, all_added);
8742 }
8743
8744 static bool hclge_need_sync_mac_table(struct hclge_vport *vport)
8745 {
8746         struct hclge_dev *hdev = vport->back;
8747
8748         if (test_bit(vport->vport_id, hdev->vport_config_block))
8749                 return false;
8750
8751         if (test_and_clear_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state))
8752                 return true;
8753
8754         return false;
8755 }
8756
8757 static void hclge_sync_mac_table(struct hclge_dev *hdev)
8758 {
8759         int i;
8760
8761         for (i = 0; i < hdev->num_alloc_vport; i++) {
8762                 struct hclge_vport *vport = &hdev->vport[i];
8763
8764                 if (!hclge_need_sync_mac_table(vport))
8765                         continue;
8766
8767                 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_UC);
8768                 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_MC);
8769         }
8770 }
8771
8772 static void hclge_build_del_list(struct list_head *list,
8773                                  bool is_del_list,
8774                                  struct list_head *tmp_del_list)
8775 {
8776         struct hclge_mac_node *mac_cfg, *tmp;
8777
8778         list_for_each_entry_safe(mac_cfg, tmp, list, node) {
8779                 switch (mac_cfg->state) {
8780                 case HCLGE_MAC_TO_DEL:
8781                 case HCLGE_MAC_ACTIVE:
8782                         list_move_tail(&mac_cfg->node, tmp_del_list);
8783                         break;
8784                 case HCLGE_MAC_TO_ADD:
8785                         if (is_del_list) {
8786                                 list_del(&mac_cfg->node);
8787                                 kfree(mac_cfg);
8788                         }
8789                         break;
8790                 }
8791         }
8792 }
8793
8794 static void hclge_unsync_del_list(struct hclge_vport *vport,
8795                                   int (*unsync)(struct hclge_vport *vport,
8796                                                 const unsigned char *addr),
8797                                   bool is_del_list,
8798                                   struct list_head *tmp_del_list)
8799 {
8800         struct hclge_mac_node *mac_cfg, *tmp;
8801         int ret;
8802
8803         list_for_each_entry_safe(mac_cfg, tmp, tmp_del_list, node) {
8804                 ret = unsync(vport, mac_cfg->mac_addr);
8805                 if (!ret || ret == -ENOENT) {
8806                         /* clear all mac addr from hardware, but remain these
8807                          * mac addr in the mac list, and restore them after
8808                          * vf reset finished.
8809                          */
8810                         if (!is_del_list &&
8811                             mac_cfg->state == HCLGE_MAC_ACTIVE) {
8812                                 mac_cfg->state = HCLGE_MAC_TO_ADD;
8813                         } else {
8814                                 list_del(&mac_cfg->node);
8815                                 kfree(mac_cfg);
8816                         }
8817                 } else if (is_del_list) {
8818                         mac_cfg->state = HCLGE_MAC_TO_DEL;
8819                 }
8820         }
8821 }
8822
8823 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list,
8824                                   enum HCLGE_MAC_ADDR_TYPE mac_type)
8825 {
8826         int (*unsync)(struct hclge_vport *vport, const unsigned char *addr);
8827         struct hclge_dev *hdev = vport->back;
8828         struct list_head tmp_del_list, *list;
8829
8830         if (mac_type == HCLGE_MAC_ADDR_UC) {
8831                 list = &vport->uc_mac_list;
8832                 unsync = hclge_rm_uc_addr_common;
8833         } else {
8834                 list = &vport->mc_mac_list;
8835                 unsync = hclge_rm_mc_addr_common;
8836         }
8837
8838         INIT_LIST_HEAD(&tmp_del_list);
8839
8840         if (!is_del_list)
8841                 set_bit(vport->vport_id, hdev->vport_config_block);
8842
8843         spin_lock_bh(&vport->mac_list_lock);
8844
8845         hclge_build_del_list(list, is_del_list, &tmp_del_list);
8846
8847         spin_unlock_bh(&vport->mac_list_lock);
8848
8849         hclge_unsync_del_list(vport, unsync, is_del_list, &tmp_del_list);
8850
8851         spin_lock_bh(&vport->mac_list_lock);
8852
8853         hclge_sync_from_del_list(&tmp_del_list, list);
8854
8855         spin_unlock_bh(&vport->mac_list_lock);
8856 }
8857
8858 /* remove all mac address when uninitailize */
8859 static void hclge_uninit_vport_mac_list(struct hclge_vport *vport,
8860                                         enum HCLGE_MAC_ADDR_TYPE mac_type)
8861 {
8862         struct hclge_mac_node *mac_node, *tmp;
8863         struct hclge_dev *hdev = vport->back;
8864         struct list_head tmp_del_list, *list;
8865
8866         INIT_LIST_HEAD(&tmp_del_list);
8867
8868         list = (mac_type == HCLGE_MAC_ADDR_UC) ?
8869                 &vport->uc_mac_list : &vport->mc_mac_list;
8870
8871         spin_lock_bh(&vport->mac_list_lock);
8872
8873         list_for_each_entry_safe(mac_node, tmp, list, node) {
8874                 switch (mac_node->state) {
8875                 case HCLGE_MAC_TO_DEL:
8876                 case HCLGE_MAC_ACTIVE:
8877                         list_move_tail(&mac_node->node, &tmp_del_list);
8878                         break;
8879                 case HCLGE_MAC_TO_ADD:
8880                         list_del(&mac_node->node);
8881                         kfree(mac_node);
8882                         break;
8883                 }
8884         }
8885
8886         spin_unlock_bh(&vport->mac_list_lock);
8887
8888         hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type);
8889
8890         if (!list_empty(&tmp_del_list))
8891                 dev_warn(&hdev->pdev->dev,
8892                          "uninit %s mac list for vport %u not completely.\n",
8893                          mac_type == HCLGE_MAC_ADDR_UC ? "uc" : "mc",
8894                          vport->vport_id);
8895
8896         list_for_each_entry_safe(mac_node, tmp, &tmp_del_list, node) {
8897                 list_del(&mac_node->node);
8898                 kfree(mac_node);
8899         }
8900 }
8901
8902 static void hclge_uninit_mac_table(struct hclge_dev *hdev)
8903 {
8904         struct hclge_vport *vport;
8905         int i;
8906
8907         for (i = 0; i < hdev->num_alloc_vport; i++) {
8908                 vport = &hdev->vport[i];
8909                 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_UC);
8910                 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_MC);
8911         }
8912 }
8913
8914 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev,
8915                                               u16 cmdq_resp, u8 resp_code)
8916 {
8917 #define HCLGE_ETHERTYPE_SUCCESS_ADD             0
8918 #define HCLGE_ETHERTYPE_ALREADY_ADD             1
8919 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW        2
8920 #define HCLGE_ETHERTYPE_KEY_CONFLICT            3
8921
8922         int return_status;
8923
8924         if (cmdq_resp) {
8925                 dev_err(&hdev->pdev->dev,
8926                         "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
8927                         cmdq_resp);
8928                 return -EIO;
8929         }
8930
8931         switch (resp_code) {
8932         case HCLGE_ETHERTYPE_SUCCESS_ADD:
8933         case HCLGE_ETHERTYPE_ALREADY_ADD:
8934                 return_status = 0;
8935                 break;
8936         case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW:
8937                 dev_err(&hdev->pdev->dev,
8938                         "add mac ethertype failed for manager table overflow.\n");
8939                 return_status = -EIO;
8940                 break;
8941         case HCLGE_ETHERTYPE_KEY_CONFLICT:
8942                 dev_err(&hdev->pdev->dev,
8943                         "add mac ethertype failed for key conflict.\n");
8944                 return_status = -EIO;
8945                 break;
8946         default:
8947                 dev_err(&hdev->pdev->dev,
8948                         "add mac ethertype failed for undefined, code=%u.\n",
8949                         resp_code);
8950                 return_status = -EIO;
8951         }
8952
8953         return return_status;
8954 }
8955
8956 static int hclge_set_vf_mac(struct hnae3_handle *handle, int vf,
8957                             u8 *mac_addr)
8958 {
8959         struct hclge_vport *vport = hclge_get_vport(handle);
8960         char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
8961         struct hclge_dev *hdev = vport->back;
8962
8963         vport = hclge_get_vf_vport(hdev, vf);
8964         if (!vport)
8965                 return -EINVAL;
8966
8967         hnae3_format_mac_addr(format_mac_addr, mac_addr);
8968         if (ether_addr_equal(mac_addr, vport->vf_info.mac)) {
8969                 dev_info(&hdev->pdev->dev,
8970                          "Specified MAC(=%s) is same as before, no change committed!\n",
8971                          format_mac_addr);
8972                 return 0;
8973         }
8974
8975         ether_addr_copy(vport->vf_info.mac, mac_addr);
8976
8977         /* there is a timewindow for PF to know VF unalive, it may
8978          * cause send mailbox fail, but it doesn't matter, VF will
8979          * query it when reinit.
8980          */
8981         if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) {
8982                 dev_info(&hdev->pdev->dev,
8983                          "MAC of VF %d has been set to %s, and it will be reinitialized!\n",
8984                          vf, format_mac_addr);
8985                 (void)hclge_inform_reset_assert_to_vf(vport);
8986                 return 0;
8987         }
8988
8989         dev_info(&hdev->pdev->dev, "MAC of VF %d has been set to %s\n",
8990                  vf, format_mac_addr);
8991         return 0;
8992 }
8993
8994 static int hclge_add_mgr_tbl(struct hclge_dev *hdev,
8995                              const struct hclge_mac_mgr_tbl_entry_cmd *req)
8996 {
8997         struct hclge_desc desc;
8998         u8 resp_code;
8999         u16 retval;
9000         int ret;
9001
9002         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false);
9003         memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd));
9004
9005         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
9006         if (ret) {
9007                 dev_err(&hdev->pdev->dev,
9008                         "add mac ethertype failed for cmd_send, ret =%d.\n",
9009                         ret);
9010                 return ret;
9011         }
9012
9013         resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
9014         retval = le16_to_cpu(desc.retval);
9015
9016         return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code);
9017 }
9018
9019 static int init_mgr_tbl(struct hclge_dev *hdev)
9020 {
9021         int ret;
9022         int i;
9023
9024         for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) {
9025                 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]);
9026                 if (ret) {
9027                         dev_err(&hdev->pdev->dev,
9028                                 "add mac ethertype failed, ret =%d.\n",
9029                                 ret);
9030                         return ret;
9031                 }
9032         }
9033
9034         return 0;
9035 }
9036
9037 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
9038 {
9039         struct hclge_vport *vport = hclge_get_vport(handle);
9040         struct hclge_dev *hdev = vport->back;
9041
9042         ether_addr_copy(p, hdev->hw.mac.mac_addr);
9043 }
9044
9045 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport,
9046                                        const u8 *old_addr, const u8 *new_addr)
9047 {
9048         struct list_head *list = &vport->uc_mac_list;
9049         struct hclge_mac_node *old_node, *new_node;
9050
9051         new_node = hclge_find_mac_node(list, new_addr);
9052         if (!new_node) {
9053                 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC);
9054                 if (!new_node)
9055                         return -ENOMEM;
9056
9057                 new_node->state = HCLGE_MAC_TO_ADD;
9058                 ether_addr_copy(new_node->mac_addr, new_addr);
9059                 list_add(&new_node->node, list);
9060         } else {
9061                 if (new_node->state == HCLGE_MAC_TO_DEL)
9062                         new_node->state = HCLGE_MAC_ACTIVE;
9063
9064                 /* make sure the new addr is in the list head, avoid dev
9065                  * addr may be not re-added into mac table for the umv space
9066                  * limitation after global/imp reset which will clear mac
9067                  * table by hardware.
9068                  */
9069                 list_move(&new_node->node, list);
9070         }
9071
9072         if (old_addr && !ether_addr_equal(old_addr, new_addr)) {
9073                 old_node = hclge_find_mac_node(list, old_addr);
9074                 if (old_node) {
9075                         if (old_node->state == HCLGE_MAC_TO_ADD) {
9076                                 list_del(&old_node->node);
9077                                 kfree(old_node);
9078                         } else {
9079                                 old_node->state = HCLGE_MAC_TO_DEL;
9080                         }
9081                 }
9082         }
9083
9084         set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state);
9085
9086         return 0;
9087 }
9088
9089 static int hclge_set_mac_addr(struct hnae3_handle *handle, const void *p,
9090                               bool is_first)
9091 {
9092         const unsigned char *new_addr = (const unsigned char *)p;
9093         struct hclge_vport *vport = hclge_get_vport(handle);
9094         char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
9095         struct hclge_dev *hdev = vport->back;
9096         unsigned char *old_addr = NULL;
9097         int ret;
9098
9099         /* mac addr check */
9100         if (is_zero_ether_addr(new_addr) ||
9101             is_broadcast_ether_addr(new_addr) ||
9102             is_multicast_ether_addr(new_addr)) {
9103                 hnae3_format_mac_addr(format_mac_addr, new_addr);
9104                 dev_err(&hdev->pdev->dev,
9105                         "change uc mac err! invalid mac: %s.\n",
9106                          format_mac_addr);
9107                 return -EINVAL;
9108         }
9109
9110         ret = hclge_pause_addr_cfg(hdev, new_addr);
9111         if (ret) {
9112                 dev_err(&hdev->pdev->dev,
9113                         "failed to configure mac pause address, ret = %d\n",
9114                         ret);
9115                 return ret;
9116         }
9117
9118         if (!is_first)
9119                 old_addr = hdev->hw.mac.mac_addr;
9120
9121         spin_lock_bh(&vport->mac_list_lock);
9122         ret = hclge_update_mac_node_for_dev_addr(vport, old_addr, new_addr);
9123         if (ret) {
9124                 hnae3_format_mac_addr(format_mac_addr, new_addr);
9125                 dev_err(&hdev->pdev->dev,
9126                         "failed to change the mac addr:%s, ret = %d\n",
9127                         format_mac_addr, ret);
9128                 spin_unlock_bh(&vport->mac_list_lock);
9129
9130                 if (!is_first)
9131                         hclge_pause_addr_cfg(hdev, old_addr);
9132
9133                 return ret;
9134         }
9135         /* we must update dev addr with spin lock protect, preventing dev addr
9136          * being removed by set_rx_mode path.
9137          */
9138         ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
9139         spin_unlock_bh(&vport->mac_list_lock);
9140
9141         hclge_task_schedule(hdev, 0);
9142
9143         return 0;
9144 }
9145
9146 static int hclge_mii_ioctl(struct hclge_dev *hdev, struct ifreq *ifr, int cmd)
9147 {
9148         struct mii_ioctl_data *data = if_mii(ifr);
9149
9150         if (!hnae3_dev_phy_imp_supported(hdev))
9151                 return -EOPNOTSUPP;
9152
9153         switch (cmd) {
9154         case SIOCGMIIPHY:
9155                 data->phy_id = hdev->hw.mac.phy_addr;
9156                 /* this command reads phy id and register at the same time */
9157                 fallthrough;
9158         case SIOCGMIIREG:
9159                 data->val_out = hclge_read_phy_reg(hdev, data->reg_num);
9160                 return 0;
9161
9162         case SIOCSMIIREG:
9163                 return hclge_write_phy_reg(hdev, data->reg_num, data->val_in);
9164         default:
9165                 return -EOPNOTSUPP;
9166         }
9167 }
9168
9169 static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr,
9170                           int cmd)
9171 {
9172         struct hclge_vport *vport = hclge_get_vport(handle);
9173         struct hclge_dev *hdev = vport->back;
9174
9175         switch (cmd) {
9176         case SIOCGHWTSTAMP:
9177                 return hclge_ptp_get_cfg(hdev, ifr);
9178         case SIOCSHWTSTAMP:
9179                 return hclge_ptp_set_cfg(hdev, ifr);
9180         default:
9181                 if (!hdev->hw.mac.phydev)
9182                         return hclge_mii_ioctl(hdev, ifr, cmd);
9183         }
9184
9185         return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd);
9186 }
9187
9188 static int hclge_set_port_vlan_filter_bypass(struct hclge_dev *hdev, u8 vf_id,
9189                                              bool bypass_en)
9190 {
9191         struct hclge_port_vlan_filter_bypass_cmd *req;
9192         struct hclge_desc desc;
9193         int ret;
9194
9195         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PORT_VLAN_BYPASS, false);
9196         req = (struct hclge_port_vlan_filter_bypass_cmd *)desc.data;
9197         req->vf_id = vf_id;
9198         hnae3_set_bit(req->bypass_state, HCLGE_INGRESS_BYPASS_B,
9199                       bypass_en ? 1 : 0);
9200
9201         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
9202         if (ret)
9203                 dev_err(&hdev->pdev->dev,
9204                         "failed to set vport%u port vlan filter bypass state, ret = %d.\n",
9205                         vf_id, ret);
9206
9207         return ret;
9208 }
9209
9210 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
9211                                       u8 fe_type, bool filter_en, u8 vf_id)
9212 {
9213         struct hclge_vlan_filter_ctrl_cmd *req;
9214         struct hclge_desc desc;
9215         int ret;
9216
9217         /* read current vlan filter parameter */
9218         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, true);
9219         req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
9220         req->vlan_type = vlan_type;
9221         req->vf_id = vf_id;
9222
9223         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
9224         if (ret) {
9225                 dev_err(&hdev->pdev->dev, "failed to get vport%u vlan filter config, ret = %d.\n",
9226                         vf_id, ret);
9227                 return ret;
9228         }
9229
9230         /* modify and write new config parameter */
9231         hclge_comm_cmd_reuse_desc(&desc, false);
9232         req->vlan_fe = filter_en ?
9233                         (req->vlan_fe | fe_type) : (req->vlan_fe & ~fe_type);
9234
9235         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
9236         if (ret)
9237                 dev_err(&hdev->pdev->dev, "failed to set vport%u vlan filter, ret = %d.\n",
9238                         vf_id, ret);
9239
9240         return ret;
9241 }
9242
9243 static int hclge_set_vport_vlan_filter(struct hclge_vport *vport, bool enable)
9244 {
9245         struct hclge_dev *hdev = vport->back;
9246         struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
9247         int ret;
9248
9249         if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
9250                 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
9251                                                   HCLGE_FILTER_FE_EGRESS_V1_B,
9252                                                   enable, vport->vport_id);
9253
9254         ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
9255                                          HCLGE_FILTER_FE_EGRESS, enable,
9256                                          vport->vport_id);
9257         if (ret)
9258                 return ret;
9259
9260         if (test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, ae_dev->caps)) {
9261                 ret = hclge_set_port_vlan_filter_bypass(hdev, vport->vport_id,
9262                                                         !enable);
9263         } else if (!vport->vport_id) {
9264                 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps))
9265                         enable = false;
9266
9267                 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT,
9268                                                  HCLGE_FILTER_FE_INGRESS,
9269                                                  enable, 0);
9270         }
9271
9272         return ret;
9273 }
9274
9275 static bool hclge_need_enable_vport_vlan_filter(struct hclge_vport *vport)
9276 {
9277         struct hnae3_handle *handle = &vport->nic;
9278         struct hclge_vport_vlan_cfg *vlan, *tmp;
9279         struct hclge_dev *hdev = vport->back;
9280
9281         if (vport->vport_id) {
9282                 if (vport->port_base_vlan_cfg.state !=
9283                         HNAE3_PORT_BASE_VLAN_DISABLE)
9284                         return true;
9285
9286                 if (vport->vf_info.trusted && vport->vf_info.request_uc_en)
9287                         return false;
9288         } else if (handle->netdev_flags & HNAE3_USER_UPE) {
9289                 return false;
9290         }
9291
9292         if (!vport->req_vlan_fltr_en)
9293                 return false;
9294
9295         /* compatible with former device, always enable vlan filter */
9296         if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps))
9297                 return true;
9298
9299         list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node)
9300                 if (vlan->vlan_id != 0)
9301                         return true;
9302
9303         return false;
9304 }
9305
9306 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en)
9307 {
9308         struct hclge_dev *hdev = vport->back;
9309         bool need_en;
9310         int ret;
9311
9312         mutex_lock(&hdev->vport_lock);
9313
9314         vport->req_vlan_fltr_en = request_en;
9315
9316         need_en = hclge_need_enable_vport_vlan_filter(vport);
9317         if (need_en == vport->cur_vlan_fltr_en) {
9318                 mutex_unlock(&hdev->vport_lock);
9319                 return 0;
9320         }
9321
9322         ret = hclge_set_vport_vlan_filter(vport, need_en);
9323         if (ret) {
9324                 mutex_unlock(&hdev->vport_lock);
9325                 return ret;
9326         }
9327
9328         vport->cur_vlan_fltr_en = need_en;
9329
9330         mutex_unlock(&hdev->vport_lock);
9331
9332         return 0;
9333 }
9334
9335 static int hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
9336 {
9337         struct hclge_vport *vport = hclge_get_vport(handle);
9338
9339         return hclge_enable_vport_vlan_filter(vport, enable);
9340 }
9341
9342 static int hclge_set_vf_vlan_filter_cmd(struct hclge_dev *hdev, u16 vfid,
9343                                         bool is_kill, u16 vlan,
9344                                         struct hclge_desc *desc)
9345 {
9346         struct hclge_vlan_filter_vf_cfg_cmd *req0;
9347         struct hclge_vlan_filter_vf_cfg_cmd *req1;
9348         u8 vf_byte_val;
9349         u8 vf_byte_off;
9350         int ret;
9351
9352         hclge_cmd_setup_basic_desc(&desc[0],
9353                                    HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
9354         hclge_cmd_setup_basic_desc(&desc[1],
9355                                    HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
9356
9357         desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
9358
9359         vf_byte_off = vfid / 8;
9360         vf_byte_val = 1 << (vfid % 8);
9361
9362         req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
9363         req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
9364
9365         req0->vlan_id  = cpu_to_le16(vlan);
9366         req0->vlan_cfg = is_kill;
9367
9368         if (vf_byte_off < HCLGE_MAX_VF_BYTES)
9369                 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
9370         else
9371                 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
9372
9373         ret = hclge_cmd_send(&hdev->hw, desc, 2);
9374         if (ret) {
9375                 dev_err(&hdev->pdev->dev,
9376                         "Send vf vlan command fail, ret =%d.\n",
9377                         ret);
9378                 return ret;
9379         }
9380
9381         return 0;
9382 }
9383
9384 static int hclge_check_vf_vlan_cmd_status(struct hclge_dev *hdev, u16 vfid,
9385                                           bool is_kill, struct hclge_desc *desc)
9386 {
9387         struct hclge_vlan_filter_vf_cfg_cmd *req;
9388
9389         req = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
9390
9391         if (!is_kill) {
9392 #define HCLGE_VF_VLAN_NO_ENTRY  2
9393                 if (!req->resp_code || req->resp_code == 1)
9394                         return 0;
9395
9396                 if (req->resp_code == HCLGE_VF_VLAN_NO_ENTRY) {
9397                         set_bit(vfid, hdev->vf_vlan_full);
9398                         dev_warn(&hdev->pdev->dev,
9399                                  "vf vlan table is full, vf vlan filter is disabled\n");
9400                         return 0;
9401                 }
9402
9403                 dev_err(&hdev->pdev->dev,
9404                         "Add vf vlan filter fail, ret =%u.\n",
9405                         req->resp_code);
9406         } else {
9407 #define HCLGE_VF_VLAN_DEL_NO_FOUND      1
9408                 if (!req->resp_code)
9409                         return 0;
9410
9411                 /* vf vlan filter is disabled when vf vlan table is full,
9412                  * then new vlan id will not be added into vf vlan table.
9413                  * Just return 0 without warning, avoid massive verbose
9414                  * print logs when unload.
9415                  */
9416                 if (req->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND)
9417                         return 0;
9418
9419                 dev_err(&hdev->pdev->dev,
9420                         "Kill vf vlan filter fail, ret =%u.\n",
9421                         req->resp_code);
9422         }
9423
9424         return -EIO;
9425 }
9426
9427 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, u16 vfid,
9428                                     bool is_kill, u16 vlan)
9429 {
9430         struct hclge_vport *vport = &hdev->vport[vfid];
9431         struct hclge_desc desc[2];
9432         int ret;
9433
9434         /* if vf vlan table is full, firmware will close vf vlan filter, it
9435          * is unable and unnecessary to add new vlan id to vf vlan filter.
9436          * If spoof check is enable, and vf vlan is full, it shouldn't add
9437          * new vlan, because tx packets with these vlan id will be dropped.
9438          */
9439         if (test_bit(vfid, hdev->vf_vlan_full) && !is_kill) {
9440                 if (vport->vf_info.spoofchk && vlan) {
9441                         dev_err(&hdev->pdev->dev,
9442                                 "Can't add vlan due to spoof check is on and vf vlan table is full\n");
9443                         return -EPERM;
9444                 }
9445                 return 0;
9446         }
9447
9448         ret = hclge_set_vf_vlan_filter_cmd(hdev, vfid, is_kill, vlan, desc);
9449         if (ret)
9450                 return ret;
9451
9452         return hclge_check_vf_vlan_cmd_status(hdev, vfid, is_kill, desc);
9453 }
9454
9455 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto,
9456                                       u16 vlan_id, bool is_kill)
9457 {
9458         struct hclge_vlan_filter_pf_cfg_cmd *req;
9459         struct hclge_desc desc;
9460         u8 vlan_offset_byte_val;
9461         u8 vlan_offset_byte;
9462         u8 vlan_offset_160;
9463         int ret;
9464
9465         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
9466
9467         vlan_offset_160 = vlan_id / HCLGE_VLAN_ID_OFFSET_STEP;
9468         vlan_offset_byte = (vlan_id % HCLGE_VLAN_ID_OFFSET_STEP) /
9469                            HCLGE_VLAN_BYTE_SIZE;
9470         vlan_offset_byte_val = 1 << (vlan_id % HCLGE_VLAN_BYTE_SIZE);
9471
9472         req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
9473         req->vlan_offset = vlan_offset_160;
9474         req->vlan_cfg = is_kill;
9475         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
9476
9477         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
9478         if (ret)
9479                 dev_err(&hdev->pdev->dev,
9480                         "port vlan command, send fail, ret =%d.\n", ret);
9481         return ret;
9482 }
9483
9484 static bool hclge_need_update_port_vlan(struct hclge_dev *hdev, u16 vport_id,
9485                                         u16 vlan_id, bool is_kill)
9486 {
9487         /* vlan 0 may be added twice when 8021q module is enabled */
9488         if (!is_kill && !vlan_id &&
9489             test_bit(vport_id, hdev->vlan_table[vlan_id]))
9490                 return false;
9491
9492         if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) {
9493                 dev_warn(&hdev->pdev->dev,
9494                          "Add port vlan failed, vport %u is already in vlan %u\n",
9495                          vport_id, vlan_id);
9496                 return false;
9497         }
9498
9499         if (is_kill &&
9500             !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) {
9501                 dev_warn(&hdev->pdev->dev,
9502                          "Delete port vlan failed, vport %u is not in vlan %u\n",
9503                          vport_id, vlan_id);
9504                 return false;
9505         }
9506
9507         return true;
9508 }
9509
9510 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto,
9511                                     u16 vport_id, u16 vlan_id,
9512                                     bool is_kill)
9513 {
9514         u16 vport_idx, vport_num = 0;
9515         int ret;
9516
9517         if (is_kill && !vlan_id)
9518                 return 0;
9519
9520         if (vlan_id >= VLAN_N_VID)
9521                 return -EINVAL;
9522
9523         ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id);
9524         if (ret) {
9525                 dev_err(&hdev->pdev->dev,
9526                         "Set %u vport vlan filter config fail, ret =%d.\n",
9527                         vport_id, ret);
9528                 return ret;
9529         }
9530
9531         if (!hclge_need_update_port_vlan(hdev, vport_id, vlan_id, is_kill))
9532                 return 0;
9533
9534         for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM)
9535                 vport_num++;
9536
9537         if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1))
9538                 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id,
9539                                                  is_kill);
9540
9541         return ret;
9542 }
9543
9544 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
9545 {
9546         struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
9547         struct hclge_vport_vtag_tx_cfg_cmd *req;
9548         struct hclge_dev *hdev = vport->back;
9549         struct hclge_desc desc;
9550         u16 bmap_index;
9551         int status;
9552
9553         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
9554
9555         req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
9556         req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
9557         req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
9558         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B,
9559                       vcfg->accept_tag1 ? 1 : 0);
9560         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B,
9561                       vcfg->accept_untag1 ? 1 : 0);
9562         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B,
9563                       vcfg->accept_tag2 ? 1 : 0);
9564         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B,
9565                       vcfg->accept_untag2 ? 1 : 0);
9566         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
9567                       vcfg->insert_tag1_en ? 1 : 0);
9568         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
9569                       vcfg->insert_tag2_en ? 1 : 0);
9570         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_TAG_SHIFT_MODE_EN_B,
9571                       vcfg->tag_shift_mode_en ? 1 : 0);
9572         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
9573
9574         req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
9575         bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD /
9576                         HCLGE_VF_NUM_PER_BYTE;
9577         req->vf_bitmap[bmap_index] =
9578                 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
9579
9580         status = hclge_cmd_send(&hdev->hw, &desc, 1);
9581         if (status)
9582                 dev_err(&hdev->pdev->dev,
9583                         "Send port txvlan cfg command fail, ret =%d\n",
9584                         status);
9585
9586         return status;
9587 }
9588
9589 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
9590 {
9591         struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
9592         struct hclge_vport_vtag_rx_cfg_cmd *req;
9593         struct hclge_dev *hdev = vport->back;
9594         struct hclge_desc desc;
9595         u16 bmap_index;
9596         int status;
9597
9598         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
9599
9600         req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
9601         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
9602                       vcfg->strip_tag1_en ? 1 : 0);
9603         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
9604                       vcfg->strip_tag2_en ? 1 : 0);
9605         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
9606                       vcfg->vlan1_vlan_prionly ? 1 : 0);
9607         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
9608                       vcfg->vlan2_vlan_prionly ? 1 : 0);
9609         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG1_EN_B,
9610                       vcfg->strip_tag1_discard_en ? 1 : 0);
9611         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG2_EN_B,
9612                       vcfg->strip_tag2_discard_en ? 1 : 0);
9613
9614         req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
9615         bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD /
9616                         HCLGE_VF_NUM_PER_BYTE;
9617         req->vf_bitmap[bmap_index] =
9618                 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
9619
9620         status = hclge_cmd_send(&hdev->hw, &desc, 1);
9621         if (status)
9622                 dev_err(&hdev->pdev->dev,
9623                         "Send port rxvlan cfg command fail, ret =%d\n",
9624                         status);
9625
9626         return status;
9627 }
9628
9629 static int hclge_vlan_offload_cfg(struct hclge_vport *vport,
9630                                   u16 port_base_vlan_state,
9631                                   u16 vlan_tag, u8 qos)
9632 {
9633         int ret;
9634
9635         if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) {
9636                 vport->txvlan_cfg.accept_tag1 = true;
9637                 vport->txvlan_cfg.insert_tag1_en = false;
9638                 vport->txvlan_cfg.default_tag1 = 0;
9639         } else {
9640                 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(vport->nic.pdev);
9641
9642                 vport->txvlan_cfg.accept_tag1 =
9643                         ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3;
9644                 vport->txvlan_cfg.insert_tag1_en = true;
9645                 vport->txvlan_cfg.default_tag1 = (qos << VLAN_PRIO_SHIFT) |
9646                                                  vlan_tag;
9647         }
9648
9649         vport->txvlan_cfg.accept_untag1 = true;
9650
9651         /* accept_tag2 and accept_untag2 are not supported on
9652          * pdev revision(0x20), new revision support them,
9653          * this two fields can not be configured by user.
9654          */
9655         vport->txvlan_cfg.accept_tag2 = true;
9656         vport->txvlan_cfg.accept_untag2 = true;
9657         vport->txvlan_cfg.insert_tag2_en = false;
9658         vport->txvlan_cfg.default_tag2 = 0;
9659         vport->txvlan_cfg.tag_shift_mode_en = true;
9660
9661         if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) {
9662                 vport->rxvlan_cfg.strip_tag1_en = false;
9663                 vport->rxvlan_cfg.strip_tag2_en =
9664                                 vport->rxvlan_cfg.rx_vlan_offload_en;
9665                 vport->rxvlan_cfg.strip_tag2_discard_en = false;
9666         } else {
9667                 vport->rxvlan_cfg.strip_tag1_en =
9668                                 vport->rxvlan_cfg.rx_vlan_offload_en;
9669                 vport->rxvlan_cfg.strip_tag2_en = true;
9670                 vport->rxvlan_cfg.strip_tag2_discard_en = true;
9671         }
9672
9673         vport->rxvlan_cfg.strip_tag1_discard_en = false;
9674         vport->rxvlan_cfg.vlan1_vlan_prionly = false;
9675         vport->rxvlan_cfg.vlan2_vlan_prionly = false;
9676
9677         ret = hclge_set_vlan_tx_offload_cfg(vport);
9678         if (ret)
9679                 return ret;
9680
9681         return hclge_set_vlan_rx_offload_cfg(vport);
9682 }
9683
9684 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
9685 {
9686         struct hclge_rx_vlan_type_cfg_cmd *rx_req;
9687         struct hclge_tx_vlan_type_cfg_cmd *tx_req;
9688         struct hclge_desc desc;
9689         int status;
9690
9691         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
9692         rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
9693         rx_req->ot_fst_vlan_type =
9694                 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
9695         rx_req->ot_sec_vlan_type =
9696                 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
9697         rx_req->in_fst_vlan_type =
9698                 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
9699         rx_req->in_sec_vlan_type =
9700                 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
9701
9702         status = hclge_cmd_send(&hdev->hw, &desc, 1);
9703         if (status) {
9704                 dev_err(&hdev->pdev->dev,
9705                         "Send rxvlan protocol type command fail, ret =%d\n",
9706                         status);
9707                 return status;
9708         }
9709
9710         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
9711
9712         tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data;
9713         tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
9714         tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
9715
9716         status = hclge_cmd_send(&hdev->hw, &desc, 1);
9717         if (status)
9718                 dev_err(&hdev->pdev->dev,
9719                         "Send txvlan protocol type command fail, ret =%d\n",
9720                         status);
9721
9722         return status;
9723 }
9724
9725 static int hclge_init_vlan_filter(struct hclge_dev *hdev)
9726 {
9727         struct hclge_vport *vport;
9728         int ret;
9729         int i;
9730
9731         if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
9732                 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
9733                                                   HCLGE_FILTER_FE_EGRESS_V1_B,
9734                                                   true, 0);
9735
9736         /* for revision 0x21, vf vlan filter is per function */
9737         for (i = 0; i < hdev->num_alloc_vport; i++) {
9738                 vport = &hdev->vport[i];
9739                 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
9740                                                  HCLGE_FILTER_FE_EGRESS, true,
9741                                                  vport->vport_id);
9742                 if (ret)
9743                         return ret;
9744                 vport->cur_vlan_fltr_en = true;
9745         }
9746
9747         return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT,
9748                                           HCLGE_FILTER_FE_INGRESS, true, 0);
9749 }
9750
9751 static int hclge_init_vlan_type(struct hclge_dev *hdev)
9752 {
9753         hdev->vlan_type_cfg.rx_in_fst_vlan_type = ETH_P_8021Q;
9754         hdev->vlan_type_cfg.rx_in_sec_vlan_type = ETH_P_8021Q;
9755         hdev->vlan_type_cfg.rx_ot_fst_vlan_type = ETH_P_8021Q;
9756         hdev->vlan_type_cfg.rx_ot_sec_vlan_type = ETH_P_8021Q;
9757         hdev->vlan_type_cfg.tx_ot_vlan_type = ETH_P_8021Q;
9758         hdev->vlan_type_cfg.tx_in_vlan_type = ETH_P_8021Q;
9759
9760         return hclge_set_vlan_protocol_type(hdev);
9761 }
9762
9763 static int hclge_init_vport_vlan_offload(struct hclge_dev *hdev)
9764 {
9765         struct hclge_port_base_vlan_config *cfg;
9766         struct hclge_vport *vport;
9767         int ret;
9768         int i;
9769
9770         for (i = 0; i < hdev->num_alloc_vport; i++) {
9771                 vport = &hdev->vport[i];
9772                 cfg = &vport->port_base_vlan_cfg;
9773
9774                 ret = hclge_vlan_offload_cfg(vport, cfg->state,
9775                                              cfg->vlan_info.vlan_tag,
9776                                              cfg->vlan_info.qos);
9777                 if (ret)
9778                         return ret;
9779         }
9780         return 0;
9781 }
9782
9783 static int hclge_init_vlan_config(struct hclge_dev *hdev)
9784 {
9785         struct hnae3_handle *handle = &hdev->vport[0].nic;
9786         int ret;
9787
9788         ret = hclge_init_vlan_filter(hdev);
9789         if (ret)
9790                 return ret;
9791
9792         ret = hclge_init_vlan_type(hdev);
9793         if (ret)
9794                 return ret;
9795
9796         ret = hclge_init_vport_vlan_offload(hdev);
9797         if (ret)
9798                 return ret;
9799
9800         return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
9801 }
9802
9803 static void hclge_add_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id,
9804                                        bool writen_to_tbl)
9805 {
9806         struct hclge_vport_vlan_cfg *vlan, *tmp;
9807         struct hclge_dev *hdev = vport->back;
9808
9809         mutex_lock(&hdev->vport_lock);
9810
9811         list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
9812                 if (vlan->vlan_id == vlan_id) {
9813                         mutex_unlock(&hdev->vport_lock);
9814                         return;
9815                 }
9816         }
9817
9818         vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
9819         if (!vlan) {
9820                 mutex_unlock(&hdev->vport_lock);
9821                 return;
9822         }
9823
9824         vlan->hd_tbl_status = writen_to_tbl;
9825         vlan->vlan_id = vlan_id;
9826
9827         list_add_tail(&vlan->node, &vport->vlan_list);
9828         mutex_unlock(&hdev->vport_lock);
9829 }
9830
9831 static int hclge_add_vport_all_vlan_table(struct hclge_vport *vport)
9832 {
9833         struct hclge_vport_vlan_cfg *vlan, *tmp;
9834         struct hclge_dev *hdev = vport->back;
9835         int ret;
9836
9837         mutex_lock(&hdev->vport_lock);
9838
9839         list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
9840                 if (!vlan->hd_tbl_status) {
9841                         ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q),
9842                                                        vport->vport_id,
9843                                                        vlan->vlan_id, false);
9844                         if (ret) {
9845                                 dev_err(&hdev->pdev->dev,
9846                                         "restore vport vlan list failed, ret=%d\n",
9847                                         ret);
9848
9849                                 mutex_unlock(&hdev->vport_lock);
9850                                 return ret;
9851                         }
9852                 }
9853                 vlan->hd_tbl_status = true;
9854         }
9855
9856         mutex_unlock(&hdev->vport_lock);
9857
9858         return 0;
9859 }
9860
9861 static void hclge_rm_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id,
9862                                       bool is_write_tbl)
9863 {
9864         struct hclge_vport_vlan_cfg *vlan, *tmp;
9865         struct hclge_dev *hdev = vport->back;
9866
9867         mutex_lock(&hdev->vport_lock);
9868
9869         list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
9870                 if (vlan->vlan_id == vlan_id) {
9871                         if (is_write_tbl && vlan->hd_tbl_status)
9872                                 hclge_set_vlan_filter_hw(hdev,
9873                                                          htons(ETH_P_8021Q),
9874                                                          vport->vport_id,
9875                                                          vlan_id,
9876                                                          true);
9877
9878                         list_del(&vlan->node);
9879                         kfree(vlan);
9880                         break;
9881                 }
9882         }
9883
9884         mutex_unlock(&hdev->vport_lock);
9885 }
9886
9887 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list)
9888 {
9889         struct hclge_vport_vlan_cfg *vlan, *tmp;
9890         struct hclge_dev *hdev = vport->back;
9891
9892         mutex_lock(&hdev->vport_lock);
9893
9894         list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
9895                 if (vlan->hd_tbl_status)
9896                         hclge_set_vlan_filter_hw(hdev,
9897                                                  htons(ETH_P_8021Q),
9898                                                  vport->vport_id,
9899                                                  vlan->vlan_id,
9900                                                  true);
9901
9902                 vlan->hd_tbl_status = false;
9903                 if (is_del_list) {
9904                         list_del(&vlan->node);
9905                         kfree(vlan);
9906                 }
9907         }
9908         clear_bit(vport->vport_id, hdev->vf_vlan_full);
9909         mutex_unlock(&hdev->vport_lock);
9910 }
9911
9912 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev)
9913 {
9914         struct hclge_vport_vlan_cfg *vlan, *tmp;
9915         struct hclge_vport *vport;
9916         int i;
9917
9918         mutex_lock(&hdev->vport_lock);
9919
9920         for (i = 0; i < hdev->num_alloc_vport; i++) {
9921                 vport = &hdev->vport[i];
9922                 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
9923                         list_del(&vlan->node);
9924                         kfree(vlan);
9925                 }
9926         }
9927
9928         mutex_unlock(&hdev->vport_lock);
9929 }
9930
9931 void hclge_restore_vport_port_base_vlan_config(struct hclge_dev *hdev)
9932 {
9933         struct hclge_vlan_info *vlan_info;
9934         struct hclge_vport *vport;
9935         u16 vlan_proto;
9936         u16 vlan_id;
9937         u16 state;
9938         int vf_id;
9939         int ret;
9940
9941         /* PF should restore all vfs port base vlan */
9942         for (vf_id = 0; vf_id < hdev->num_alloc_vfs; vf_id++) {
9943                 vport = &hdev->vport[vf_id + HCLGE_VF_VPORT_START_NUM];
9944                 vlan_info = vport->port_base_vlan_cfg.tbl_sta ?
9945                             &vport->port_base_vlan_cfg.vlan_info :
9946                             &vport->port_base_vlan_cfg.old_vlan_info;
9947
9948                 vlan_id = vlan_info->vlan_tag;
9949                 vlan_proto = vlan_info->vlan_proto;
9950                 state = vport->port_base_vlan_cfg.state;
9951
9952                 if (state != HNAE3_PORT_BASE_VLAN_DISABLE) {
9953                         clear_bit(vport->vport_id, hdev->vlan_table[vlan_id]);
9954                         ret = hclge_set_vlan_filter_hw(hdev, htons(vlan_proto),
9955                                                        vport->vport_id,
9956                                                        vlan_id, false);
9957                         vport->port_base_vlan_cfg.tbl_sta = ret == 0;
9958                 }
9959         }
9960 }
9961
9962 void hclge_restore_vport_vlan_table(struct hclge_vport *vport)
9963 {
9964         struct hclge_vport_vlan_cfg *vlan, *tmp;
9965         struct hclge_dev *hdev = vport->back;
9966         int ret;
9967
9968         mutex_lock(&hdev->vport_lock);
9969
9970         if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) {
9971                 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
9972                         ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q),
9973                                                        vport->vport_id,
9974                                                        vlan->vlan_id, false);
9975                         if (ret)
9976                                 break;
9977                         vlan->hd_tbl_status = true;
9978                 }
9979         }
9980
9981         mutex_unlock(&hdev->vport_lock);
9982 }
9983
9984 /* For global reset and imp reset, hardware will clear the mac table,
9985  * so we change the mac address state from ACTIVE to TO_ADD, then they
9986  * can be restored in the service task after reset complete. Furtherly,
9987  * the mac addresses with state TO_DEL or DEL_FAIL are unnecessary to
9988  * be restored after reset, so just remove these mac nodes from mac_list.
9989  */
9990 static void hclge_mac_node_convert_for_reset(struct list_head *list)
9991 {
9992         struct hclge_mac_node *mac_node, *tmp;
9993
9994         list_for_each_entry_safe(mac_node, tmp, list, node) {
9995                 if (mac_node->state == HCLGE_MAC_ACTIVE) {
9996                         mac_node->state = HCLGE_MAC_TO_ADD;
9997                 } else if (mac_node->state == HCLGE_MAC_TO_DEL) {
9998                         list_del(&mac_node->node);
9999                         kfree(mac_node);
10000                 }
10001         }
10002 }
10003
10004 void hclge_restore_mac_table_common(struct hclge_vport *vport)
10005 {
10006         spin_lock_bh(&vport->mac_list_lock);
10007
10008         hclge_mac_node_convert_for_reset(&vport->uc_mac_list);
10009         hclge_mac_node_convert_for_reset(&vport->mc_mac_list);
10010         set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state);
10011
10012         spin_unlock_bh(&vport->mac_list_lock);
10013 }
10014
10015 static void hclge_restore_hw_table(struct hclge_dev *hdev)
10016 {
10017         struct hclge_vport *vport = &hdev->vport[0];
10018         struct hnae3_handle *handle = &vport->nic;
10019
10020         hclge_restore_mac_table_common(vport);
10021         hclge_restore_vport_port_base_vlan_config(hdev);
10022         hclge_restore_vport_vlan_table(vport);
10023         set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state);
10024         hclge_restore_fd_entries(handle);
10025 }
10026
10027 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
10028 {
10029         struct hclge_vport *vport = hclge_get_vport(handle);
10030
10031         if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) {
10032                 vport->rxvlan_cfg.strip_tag1_en = false;
10033                 vport->rxvlan_cfg.strip_tag2_en = enable;
10034                 vport->rxvlan_cfg.strip_tag2_discard_en = false;
10035         } else {
10036                 vport->rxvlan_cfg.strip_tag1_en = enable;
10037                 vport->rxvlan_cfg.strip_tag2_en = true;
10038                 vport->rxvlan_cfg.strip_tag2_discard_en = true;
10039         }
10040
10041         vport->rxvlan_cfg.strip_tag1_discard_en = false;
10042         vport->rxvlan_cfg.vlan1_vlan_prionly = false;
10043         vport->rxvlan_cfg.vlan2_vlan_prionly = false;
10044         vport->rxvlan_cfg.rx_vlan_offload_en = enable;
10045
10046         return hclge_set_vlan_rx_offload_cfg(vport);
10047 }
10048
10049 static void hclge_set_vport_vlan_fltr_change(struct hclge_vport *vport)
10050 {
10051         struct hclge_dev *hdev = vport->back;
10052
10053         if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps))
10054                 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, &vport->state);
10055 }
10056
10057 static int hclge_update_vlan_filter_entries(struct hclge_vport *vport,
10058                                             u16 port_base_vlan_state,
10059                                             struct hclge_vlan_info *new_info,
10060                                             struct hclge_vlan_info *old_info)
10061 {
10062         struct hclge_dev *hdev = vport->back;
10063         int ret;
10064
10065         if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_ENABLE) {
10066                 hclge_rm_vport_all_vlan_table(vport, false);
10067                 /* force clear VLAN 0 */
10068                 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, true, 0);
10069                 if (ret)
10070                         return ret;
10071                 return hclge_set_vlan_filter_hw(hdev,
10072                                                  htons(new_info->vlan_proto),
10073                                                  vport->vport_id,
10074                                                  new_info->vlan_tag,
10075                                                  false);
10076         }
10077
10078         vport->port_base_vlan_cfg.tbl_sta = false;
10079
10080         /* force add VLAN 0 */
10081         ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, false, 0);
10082         if (ret)
10083                 return ret;
10084
10085         ret = hclge_set_vlan_filter_hw(hdev, htons(old_info->vlan_proto),
10086                                        vport->vport_id, old_info->vlan_tag,
10087                                        true);
10088         if (ret)
10089                 return ret;
10090
10091         return hclge_add_vport_all_vlan_table(vport);
10092 }
10093
10094 static bool hclge_need_update_vlan_filter(const struct hclge_vlan_info *new_cfg,
10095                                           const struct hclge_vlan_info *old_cfg)
10096 {
10097         if (new_cfg->vlan_tag != old_cfg->vlan_tag)
10098                 return true;
10099
10100         if (new_cfg->vlan_tag == 0 && (new_cfg->qos == 0 || old_cfg->qos == 0))
10101                 return true;
10102
10103         return false;
10104 }
10105
10106 static int hclge_modify_port_base_vlan_tag(struct hclge_vport *vport,
10107                                            struct hclge_vlan_info *new_info,
10108                                            struct hclge_vlan_info *old_info)
10109 {
10110         struct hclge_dev *hdev = vport->back;
10111         int ret;
10112
10113         /* add new VLAN tag */
10114         ret = hclge_set_vlan_filter_hw(hdev, htons(new_info->vlan_proto),
10115                                        vport->vport_id, new_info->vlan_tag,
10116                                        false);
10117         if (ret)
10118                 return ret;
10119
10120         /* remove old VLAN tag */
10121         if (old_info->vlan_tag == 0)
10122                 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id,
10123                                                true, 0);
10124         else
10125                 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q),
10126                                                vport->vport_id,
10127                                                old_info->vlan_tag, true);
10128         if (ret)
10129                 dev_err(&hdev->pdev->dev,
10130                         "failed to clear vport%u port base vlan %u, ret = %d.\n",
10131                         vport->vport_id, old_info->vlan_tag, ret);
10132
10133         return ret;
10134 }
10135
10136 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state,
10137                                     struct hclge_vlan_info *vlan_info)
10138 {
10139         struct hnae3_handle *nic = &vport->nic;
10140         struct hclge_vlan_info *old_vlan_info;
10141         int ret;
10142
10143         old_vlan_info = &vport->port_base_vlan_cfg.vlan_info;
10144
10145         ret = hclge_vlan_offload_cfg(vport, state, vlan_info->vlan_tag,
10146                                      vlan_info->qos);
10147         if (ret)
10148                 return ret;
10149
10150         if (!hclge_need_update_vlan_filter(vlan_info, old_vlan_info))
10151                 goto out;
10152
10153         if (state == HNAE3_PORT_BASE_VLAN_MODIFY)
10154                 ret = hclge_modify_port_base_vlan_tag(vport, vlan_info,
10155                                                       old_vlan_info);
10156         else
10157                 ret = hclge_update_vlan_filter_entries(vport, state, vlan_info,
10158                                                        old_vlan_info);
10159         if (ret)
10160                 return ret;
10161
10162 out:
10163         vport->port_base_vlan_cfg.state = state;
10164         if (state == HNAE3_PORT_BASE_VLAN_DISABLE)
10165                 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE;
10166         else
10167                 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE;
10168
10169         vport->port_base_vlan_cfg.old_vlan_info = *old_vlan_info;
10170         vport->port_base_vlan_cfg.vlan_info = *vlan_info;
10171         vport->port_base_vlan_cfg.tbl_sta = true;
10172         hclge_set_vport_vlan_fltr_change(vport);
10173
10174         return 0;
10175 }
10176
10177 static u16 hclge_get_port_base_vlan_state(struct hclge_vport *vport,
10178                                           enum hnae3_port_base_vlan_state state,
10179                                           u16 vlan, u8 qos)
10180 {
10181         if (state == HNAE3_PORT_BASE_VLAN_DISABLE) {
10182                 if (!vlan && !qos)
10183                         return HNAE3_PORT_BASE_VLAN_NOCHANGE;
10184
10185                 return HNAE3_PORT_BASE_VLAN_ENABLE;
10186         }
10187
10188         if (!vlan && !qos)
10189                 return HNAE3_PORT_BASE_VLAN_DISABLE;
10190
10191         if (vport->port_base_vlan_cfg.vlan_info.vlan_tag == vlan &&
10192             vport->port_base_vlan_cfg.vlan_info.qos == qos)
10193                 return HNAE3_PORT_BASE_VLAN_NOCHANGE;
10194
10195         return HNAE3_PORT_BASE_VLAN_MODIFY;
10196 }
10197
10198 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
10199                                     u16 vlan, u8 qos, __be16 proto)
10200 {
10201         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
10202         struct hclge_vport *vport = hclge_get_vport(handle);
10203         struct hclge_dev *hdev = vport->back;
10204         struct hclge_vlan_info vlan_info;
10205         u16 state;
10206         int ret;
10207
10208         if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
10209                 return -EOPNOTSUPP;
10210
10211         vport = hclge_get_vf_vport(hdev, vfid);
10212         if (!vport)
10213                 return -EINVAL;
10214
10215         /* qos is a 3 bits value, so can not be bigger than 7 */
10216         if (vlan > VLAN_N_VID - 1 || qos > 7)
10217                 return -EINVAL;
10218         if (proto != htons(ETH_P_8021Q))
10219                 return -EPROTONOSUPPORT;
10220
10221         state = hclge_get_port_base_vlan_state(vport,
10222                                                vport->port_base_vlan_cfg.state,
10223                                                vlan, qos);
10224         if (state == HNAE3_PORT_BASE_VLAN_NOCHANGE)
10225                 return 0;
10226
10227         vlan_info.vlan_tag = vlan;
10228         vlan_info.qos = qos;
10229         vlan_info.vlan_proto = ntohs(proto);
10230
10231         ret = hclge_update_port_base_vlan_cfg(vport, state, &vlan_info);
10232         if (ret) {
10233                 dev_err(&hdev->pdev->dev,
10234                         "failed to update port base vlan for vf %d, ret = %d\n",
10235                         vfid, ret);
10236                 return ret;
10237         }
10238
10239         /* there is a timewindow for PF to know VF unalive, it may
10240          * cause send mailbox fail, but it doesn't matter, VF will
10241          * query it when reinit.
10242          * for DEVICE_VERSION_V3, vf doesn't need to know about the port based
10243          * VLAN state.
10244          */
10245         if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3 &&
10246             test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state))
10247                 (void)hclge_push_vf_port_base_vlan_info(&hdev->vport[0],
10248                                                         vport->vport_id,
10249                                                         state, &vlan_info);
10250
10251         return 0;
10252 }
10253
10254 static void hclge_clear_vf_vlan(struct hclge_dev *hdev)
10255 {
10256         struct hclge_vlan_info *vlan_info;
10257         struct hclge_vport *vport;
10258         int ret;
10259         int vf;
10260
10261         /* clear port base vlan for all vf */
10262         for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) {
10263                 vport = &hdev->vport[vf];
10264                 vlan_info = &vport->port_base_vlan_cfg.vlan_info;
10265
10266                 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q),
10267                                                vport->vport_id,
10268                                                vlan_info->vlan_tag, true);
10269                 if (ret)
10270                         dev_err(&hdev->pdev->dev,
10271                                 "failed to clear vf vlan for vf%d, ret = %d\n",
10272                                 vf - HCLGE_VF_VPORT_START_NUM, ret);
10273         }
10274 }
10275
10276 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
10277                           u16 vlan_id, bool is_kill)
10278 {
10279         struct hclge_vport *vport = hclge_get_vport(handle);
10280         struct hclge_dev *hdev = vport->back;
10281         bool writen_to_tbl = false;
10282         int ret = 0;
10283
10284         /* When device is resetting or reset failed, firmware is unable to
10285          * handle mailbox. Just record the vlan id, and remove it after
10286          * reset finished.
10287          */
10288         if ((test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) ||
10289              test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) && is_kill) {
10290                 set_bit(vlan_id, vport->vlan_del_fail_bmap);
10291                 return -EBUSY;
10292         }
10293
10294         /* when port base vlan enabled, we use port base vlan as the vlan
10295          * filter entry. In this case, we don't update vlan filter table
10296          * when user add new vlan or remove exist vlan, just update the vport
10297          * vlan list. The vlan id in vlan list will be writen in vlan filter
10298          * table until port base vlan disabled
10299          */
10300         if (handle->port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) {
10301                 ret = hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id,
10302                                                vlan_id, is_kill);
10303                 writen_to_tbl = true;
10304         }
10305
10306         if (!ret) {
10307                 if (!is_kill)
10308                         hclge_add_vport_vlan_table(vport, vlan_id,
10309                                                    writen_to_tbl);
10310                 else if (is_kill && vlan_id != 0)
10311                         hclge_rm_vport_vlan_table(vport, vlan_id, false);
10312         } else if (is_kill) {
10313                 /* when remove hw vlan filter failed, record the vlan id,
10314                  * and try to remove it from hw later, to be consistence
10315                  * with stack
10316                  */
10317                 set_bit(vlan_id, vport->vlan_del_fail_bmap);
10318         }
10319
10320         hclge_set_vport_vlan_fltr_change(vport);
10321
10322         return ret;
10323 }
10324
10325 static void hclge_sync_vlan_fltr_state(struct hclge_dev *hdev)
10326 {
10327         struct hclge_vport *vport;
10328         int ret;
10329         u16 i;
10330
10331         for (i = 0; i < hdev->num_alloc_vport; i++) {
10332                 vport = &hdev->vport[i];
10333                 if (!test_and_clear_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE,
10334                                         &vport->state))
10335                         continue;
10336
10337                 ret = hclge_enable_vport_vlan_filter(vport,
10338                                                      vport->req_vlan_fltr_en);
10339                 if (ret) {
10340                         dev_err(&hdev->pdev->dev,
10341                                 "failed to sync vlan filter state for vport%u, ret = %d\n",
10342                                 vport->vport_id, ret);
10343                         set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE,
10344                                 &vport->state);
10345                         return;
10346                 }
10347         }
10348 }
10349
10350 static void hclge_sync_vlan_filter(struct hclge_dev *hdev)
10351 {
10352 #define HCLGE_MAX_SYNC_COUNT    60
10353
10354         int i, ret, sync_cnt = 0;
10355         u16 vlan_id;
10356
10357         /* start from vport 1 for PF is always alive */
10358         for (i = 0; i < hdev->num_alloc_vport; i++) {
10359                 struct hclge_vport *vport = &hdev->vport[i];
10360
10361                 vlan_id = find_first_bit(vport->vlan_del_fail_bmap,
10362                                          VLAN_N_VID);
10363                 while (vlan_id != VLAN_N_VID) {
10364                         ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q),
10365                                                        vport->vport_id, vlan_id,
10366                                                        true);
10367                         if (ret && ret != -EINVAL)
10368                                 return;
10369
10370                         clear_bit(vlan_id, vport->vlan_del_fail_bmap);
10371                         hclge_rm_vport_vlan_table(vport, vlan_id, false);
10372                         hclge_set_vport_vlan_fltr_change(vport);
10373
10374                         sync_cnt++;
10375                         if (sync_cnt >= HCLGE_MAX_SYNC_COUNT)
10376                                 return;
10377
10378                         vlan_id = find_first_bit(vport->vlan_del_fail_bmap,
10379                                                  VLAN_N_VID);
10380                 }
10381         }
10382
10383         hclge_sync_vlan_fltr_state(hdev);
10384 }
10385
10386 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps)
10387 {
10388         struct hclge_config_max_frm_size_cmd *req;
10389         struct hclge_desc desc;
10390
10391         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
10392
10393         req = (struct hclge_config_max_frm_size_cmd *)desc.data;
10394         req->max_frm_size = cpu_to_le16(new_mps);
10395         req->min_frm_size = HCLGE_MAC_MIN_FRAME;
10396
10397         return hclge_cmd_send(&hdev->hw, &desc, 1);
10398 }
10399
10400 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
10401 {
10402         struct hclge_vport *vport = hclge_get_vport(handle);
10403
10404         return hclge_set_vport_mtu(vport, new_mtu);
10405 }
10406
10407 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu)
10408 {
10409         struct hclge_dev *hdev = vport->back;
10410         int i, max_frm_size, ret;
10411
10412         /* HW supprt 2 layer vlan */
10413         max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN;
10414         if (max_frm_size < HCLGE_MAC_MIN_FRAME ||
10415             max_frm_size > hdev->ae_dev->dev_specs.max_frm_size)
10416                 return -EINVAL;
10417
10418         max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
10419         mutex_lock(&hdev->vport_lock);
10420         /* VF's mps must fit within hdev->mps */
10421         if (vport->vport_id && max_frm_size > hdev->mps) {
10422                 mutex_unlock(&hdev->vport_lock);
10423                 return -EINVAL;
10424         } else if (vport->vport_id) {
10425                 vport->mps = max_frm_size;
10426                 mutex_unlock(&hdev->vport_lock);
10427                 return 0;
10428         }
10429
10430         /* PF's mps must be greater then VF's mps */
10431         for (i = 1; i < hdev->num_alloc_vport; i++)
10432                 if (max_frm_size < hdev->vport[i].mps) {
10433                         dev_err(&hdev->pdev->dev,
10434                                 "failed to set pf mtu for less than vport %d, mps = %u.\n",
10435                                 i, hdev->vport[i].mps);
10436                         mutex_unlock(&hdev->vport_lock);
10437                         return -EINVAL;
10438                 }
10439
10440         hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
10441
10442         ret = hclge_set_mac_mtu(hdev, max_frm_size);
10443         if (ret) {
10444                 dev_err(&hdev->pdev->dev,
10445                         "Change mtu fail, ret =%d\n", ret);
10446                 goto out;
10447         }
10448
10449         hdev->mps = max_frm_size;
10450         vport->mps = max_frm_size;
10451
10452         ret = hclge_buffer_alloc(hdev);
10453         if (ret)
10454                 dev_err(&hdev->pdev->dev,
10455                         "Allocate buffer fail, ret =%d\n", ret);
10456
10457 out:
10458         hclge_notify_client(hdev, HNAE3_UP_CLIENT);
10459         mutex_unlock(&hdev->vport_lock);
10460         return ret;
10461 }
10462
10463 static int hclge_reset_tqp_cmd_send(struct hclge_dev *hdev, u16 queue_id,
10464                                     bool enable)
10465 {
10466         struct hclge_reset_tqp_queue_cmd *req;
10467         struct hclge_desc desc;
10468         int ret;
10469
10470         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
10471
10472         req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
10473         req->tqp_id = cpu_to_le16(queue_id);
10474         if (enable)
10475                 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, 1U);
10476
10477         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
10478         if (ret) {
10479                 dev_err(&hdev->pdev->dev,
10480                         "Send tqp reset cmd error, status =%d\n", ret);
10481                 return ret;
10482         }
10483
10484         return 0;
10485 }
10486
10487 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id,
10488                                   u8 *reset_status)
10489 {
10490         struct hclge_reset_tqp_queue_cmd *req;
10491         struct hclge_desc desc;
10492         int ret;
10493
10494         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
10495
10496         req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
10497         req->tqp_id = cpu_to_le16(queue_id);
10498
10499         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
10500         if (ret) {
10501                 dev_err(&hdev->pdev->dev,
10502                         "Get reset status error, status =%d\n", ret);
10503                 return ret;
10504         }
10505
10506         *reset_status = hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
10507
10508         return 0;
10509 }
10510
10511 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id)
10512 {
10513         struct hclge_comm_tqp *tqp;
10514         struct hnae3_queue *queue;
10515
10516         queue = handle->kinfo.tqp[queue_id];
10517         tqp = container_of(queue, struct hclge_comm_tqp, q);
10518
10519         return tqp->index;
10520 }
10521
10522 static int hclge_reset_tqp_cmd(struct hnae3_handle *handle)
10523 {
10524         struct hclge_vport *vport = hclge_get_vport(handle);
10525         struct hclge_dev *hdev = vport->back;
10526         u16 reset_try_times = 0;
10527         u8 reset_status;
10528         u16 queue_gid;
10529         int ret;
10530         u16 i;
10531
10532         for (i = 0; i < handle->kinfo.num_tqps; i++) {
10533                 queue_gid = hclge_covert_handle_qid_global(handle, i);
10534                 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, true);
10535                 if (ret) {
10536                         dev_err(&hdev->pdev->dev,
10537                                 "failed to send reset tqp cmd, ret = %d\n",
10538                                 ret);
10539                         return ret;
10540                 }
10541
10542                 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
10543                         ret = hclge_get_reset_status(hdev, queue_gid,
10544                                                      &reset_status);
10545                         if (ret)
10546                                 return ret;
10547
10548                         if (reset_status)
10549                                 break;
10550
10551                         /* Wait for tqp hw reset */
10552                         usleep_range(1000, 1200);
10553                 }
10554
10555                 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
10556                         dev_err(&hdev->pdev->dev,
10557                                 "wait for tqp hw reset timeout\n");
10558                         return -ETIME;
10559                 }
10560
10561                 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, false);
10562                 if (ret) {
10563                         dev_err(&hdev->pdev->dev,
10564                                 "failed to deassert soft reset, ret = %d\n",
10565                                 ret);
10566                         return ret;
10567                 }
10568                 reset_try_times = 0;
10569         }
10570         return 0;
10571 }
10572
10573 static int hclge_reset_rcb(struct hnae3_handle *handle)
10574 {
10575 #define HCLGE_RESET_RCB_NOT_SUPPORT     0U
10576 #define HCLGE_RESET_RCB_SUCCESS         1U
10577
10578         struct hclge_vport *vport = hclge_get_vport(handle);
10579         struct hclge_dev *hdev = vport->back;
10580         struct hclge_reset_cmd *req;
10581         struct hclge_desc desc;
10582         u8 return_status;
10583         u16 queue_gid;
10584         int ret;
10585
10586         queue_gid = hclge_covert_handle_qid_global(handle, 0);
10587
10588         req = (struct hclge_reset_cmd *)desc.data;
10589         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
10590         hnae3_set_bit(req->fun_reset_rcb, HCLGE_CFG_RESET_RCB_B, 1);
10591         req->fun_reset_rcb_vqid_start = cpu_to_le16(queue_gid);
10592         req->fun_reset_rcb_vqid_num = cpu_to_le16(handle->kinfo.num_tqps);
10593
10594         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
10595         if (ret) {
10596                 dev_err(&hdev->pdev->dev,
10597                         "failed to send rcb reset cmd, ret = %d\n", ret);
10598                 return ret;
10599         }
10600
10601         return_status = req->fun_reset_rcb_return_status;
10602         if (return_status == HCLGE_RESET_RCB_SUCCESS)
10603                 return 0;
10604
10605         if (return_status != HCLGE_RESET_RCB_NOT_SUPPORT) {
10606                 dev_err(&hdev->pdev->dev, "failed to reset rcb, ret = %u\n",
10607                         return_status);
10608                 return -EIO;
10609         }
10610
10611         /* if reset rcb cmd is unsupported, we need to send reset tqp cmd
10612          * again to reset all tqps
10613          */
10614         return hclge_reset_tqp_cmd(handle);
10615 }
10616
10617 int hclge_reset_tqp(struct hnae3_handle *handle)
10618 {
10619         struct hclge_vport *vport = hclge_get_vport(handle);
10620         struct hclge_dev *hdev = vport->back;
10621         int ret;
10622
10623         /* only need to disable PF's tqp */
10624         if (!vport->vport_id) {
10625                 ret = hclge_tqp_enable(handle, false);
10626                 if (ret) {
10627                         dev_err(&hdev->pdev->dev,
10628                                 "failed to disable tqp, ret = %d\n", ret);
10629                         return ret;
10630                 }
10631         }
10632
10633         return hclge_reset_rcb(handle);
10634 }
10635
10636 static u32 hclge_get_fw_version(struct hnae3_handle *handle)
10637 {
10638         struct hclge_vport *vport = hclge_get_vport(handle);
10639         struct hclge_dev *hdev = vport->back;
10640
10641         return hdev->fw_version;
10642 }
10643
10644 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
10645 {
10646         struct phy_device *phydev = hdev->hw.mac.phydev;
10647
10648         if (!phydev)
10649                 return;
10650
10651         phy_set_asym_pause(phydev, rx_en, tx_en);
10652 }
10653
10654 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
10655 {
10656         int ret;
10657
10658         if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
10659                 return 0;
10660
10661         ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
10662         if (ret)
10663                 dev_err(&hdev->pdev->dev,
10664                         "configure pauseparam error, ret = %d.\n", ret);
10665
10666         return ret;
10667 }
10668
10669 int hclge_cfg_flowctrl(struct hclge_dev *hdev)
10670 {
10671         struct phy_device *phydev = hdev->hw.mac.phydev;
10672         u16 remote_advertising = 0;
10673         u16 local_advertising;
10674         u32 rx_pause, tx_pause;
10675         u8 flowctl;
10676
10677         if (!phydev->link || !phydev->autoneg)
10678                 return 0;
10679
10680         local_advertising = linkmode_adv_to_lcl_adv_t(phydev->advertising);
10681
10682         if (phydev->pause)
10683                 remote_advertising = LPA_PAUSE_CAP;
10684
10685         if (phydev->asym_pause)
10686                 remote_advertising |= LPA_PAUSE_ASYM;
10687
10688         flowctl = mii_resolve_flowctrl_fdx(local_advertising,
10689                                            remote_advertising);
10690         tx_pause = flowctl & FLOW_CTRL_TX;
10691         rx_pause = flowctl & FLOW_CTRL_RX;
10692
10693         if (phydev->duplex == HCLGE_MAC_HALF) {
10694                 tx_pause = 0;
10695                 rx_pause = 0;
10696         }
10697
10698         return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
10699 }
10700
10701 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
10702                                  u32 *rx_en, u32 *tx_en)
10703 {
10704         struct hclge_vport *vport = hclge_get_vport(handle);
10705         struct hclge_dev *hdev = vport->back;
10706         u8 media_type = hdev->hw.mac.media_type;
10707
10708         *auto_neg = (media_type == HNAE3_MEDIA_TYPE_COPPER) ?
10709                     hclge_get_autoneg(handle) : 0;
10710
10711         if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
10712                 *rx_en = 0;
10713                 *tx_en = 0;
10714                 return;
10715         }
10716
10717         if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
10718                 *rx_en = 1;
10719                 *tx_en = 0;
10720         } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
10721                 *tx_en = 1;
10722                 *rx_en = 0;
10723         } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
10724                 *rx_en = 1;
10725                 *tx_en = 1;
10726         } else {
10727                 *rx_en = 0;
10728                 *tx_en = 0;
10729         }
10730 }
10731
10732 static void hclge_record_user_pauseparam(struct hclge_dev *hdev,
10733                                          u32 rx_en, u32 tx_en)
10734 {
10735         if (rx_en && tx_en)
10736                 hdev->fc_mode_last_time = HCLGE_FC_FULL;
10737         else if (rx_en && !tx_en)
10738                 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
10739         else if (!rx_en && tx_en)
10740                 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
10741         else
10742                 hdev->fc_mode_last_time = HCLGE_FC_NONE;
10743
10744         hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
10745 }
10746
10747 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
10748                                 u32 rx_en, u32 tx_en)
10749 {
10750         struct hclge_vport *vport = hclge_get_vport(handle);
10751         struct hclge_dev *hdev = vport->back;
10752         struct phy_device *phydev = hdev->hw.mac.phydev;
10753         u32 fc_autoneg;
10754
10755         if (phydev || hnae3_dev_phy_imp_supported(hdev)) {
10756                 fc_autoneg = hclge_get_autoneg(handle);
10757                 if (auto_neg != fc_autoneg) {
10758                         dev_info(&hdev->pdev->dev,
10759                                  "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
10760                         return -EOPNOTSUPP;
10761                 }
10762         }
10763
10764         if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
10765                 dev_info(&hdev->pdev->dev,
10766                          "Priority flow control enabled. Cannot set link flow control.\n");
10767                 return -EOPNOTSUPP;
10768         }
10769
10770         hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
10771
10772         hclge_record_user_pauseparam(hdev, rx_en, tx_en);
10773
10774         if (!auto_neg || hnae3_dev_phy_imp_supported(hdev))
10775                 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
10776
10777         if (phydev)
10778                 return phy_start_aneg(phydev);
10779
10780         return -EOPNOTSUPP;
10781 }
10782
10783 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
10784                                           u8 *auto_neg, u32 *speed, u8 *duplex)
10785 {
10786         struct hclge_vport *vport = hclge_get_vport(handle);
10787         struct hclge_dev *hdev = vport->back;
10788
10789         if (speed)
10790                 *speed = hdev->hw.mac.speed;
10791         if (duplex)
10792                 *duplex = hdev->hw.mac.duplex;
10793         if (auto_neg)
10794                 *auto_neg = hdev->hw.mac.autoneg;
10795 }
10796
10797 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type,
10798                                  u8 *module_type)
10799 {
10800         struct hclge_vport *vport = hclge_get_vport(handle);
10801         struct hclge_dev *hdev = vport->back;
10802
10803         /* When nic is down, the service task is not running, doesn't update
10804          * the port information per second. Query the port information before
10805          * return the media type, ensure getting the correct media information.
10806          */
10807         hclge_update_port_info(hdev);
10808
10809         if (media_type)
10810                 *media_type = hdev->hw.mac.media_type;
10811
10812         if (module_type)
10813                 *module_type = hdev->hw.mac.module_type;
10814 }
10815
10816 static void hclge_get_mdix_mode(struct hnae3_handle *handle,
10817                                 u8 *tp_mdix_ctrl, u8 *tp_mdix)
10818 {
10819         struct hclge_vport *vport = hclge_get_vport(handle);
10820         struct hclge_dev *hdev = vport->back;
10821         struct phy_device *phydev = hdev->hw.mac.phydev;
10822         int mdix_ctrl, mdix, is_resolved;
10823         unsigned int retval;
10824
10825         if (!phydev) {
10826                 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
10827                 *tp_mdix = ETH_TP_MDI_INVALID;
10828                 return;
10829         }
10830
10831         phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
10832
10833         retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
10834         mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
10835                                     HCLGE_PHY_MDIX_CTRL_S);
10836
10837         retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
10838         mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
10839         is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
10840
10841         phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
10842
10843         switch (mdix_ctrl) {
10844         case 0x0:
10845                 *tp_mdix_ctrl = ETH_TP_MDI;
10846                 break;
10847         case 0x1:
10848                 *tp_mdix_ctrl = ETH_TP_MDI_X;
10849                 break;
10850         case 0x3:
10851                 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
10852                 break;
10853         default:
10854                 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
10855                 break;
10856         }
10857
10858         if (!is_resolved)
10859                 *tp_mdix = ETH_TP_MDI_INVALID;
10860         else if (mdix)
10861                 *tp_mdix = ETH_TP_MDI_X;
10862         else
10863                 *tp_mdix = ETH_TP_MDI;
10864 }
10865
10866 static void hclge_info_show(struct hclge_dev *hdev)
10867 {
10868         struct device *dev = &hdev->pdev->dev;
10869
10870         dev_info(dev, "PF info begin:\n");
10871
10872         dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps);
10873         dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc);
10874         dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc);
10875         dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport);
10876         dev_info(dev, "Numbers of VF for this PF: %u\n", hdev->num_req_vfs);
10877         dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map);
10878         dev_info(dev, "Total buffer size for TX/RX: %u\n", hdev->pkt_buf_size);
10879         dev_info(dev, "TX buffer size for each TC: %u\n", hdev->tx_buf_size);
10880         dev_info(dev, "DV buffer size for each TC: %u\n", hdev->dv_buf_size);
10881         dev_info(dev, "This is %s PF\n",
10882                  hdev->flag & HCLGE_FLAG_MAIN ? "main" : "not main");
10883         dev_info(dev, "DCB %s\n",
10884                  hdev->flag & HCLGE_FLAG_DCB_ENABLE ? "enable" : "disable");
10885         dev_info(dev, "MQPRIO %s\n",
10886                  hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE ? "enable" : "disable");
10887         dev_info(dev, "Default tx spare buffer size: %u\n",
10888                  hdev->tx_spare_buf_size);
10889
10890         dev_info(dev, "PF info end.\n");
10891 }
10892
10893 static int hclge_init_nic_client_instance(struct hnae3_ae_dev *ae_dev,
10894                                           struct hclge_vport *vport)
10895 {
10896         struct hnae3_client *client = vport->nic.client;
10897         struct hclge_dev *hdev = ae_dev->priv;
10898         int rst_cnt = hdev->rst_stats.reset_cnt;
10899         int ret;
10900
10901         ret = client->ops->init_instance(&vport->nic);
10902         if (ret)
10903                 return ret;
10904
10905         set_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state);
10906         if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) ||
10907             rst_cnt != hdev->rst_stats.reset_cnt) {
10908                 ret = -EBUSY;
10909                 goto init_nic_err;
10910         }
10911
10912         /* Enable nic hw error interrupts */
10913         ret = hclge_config_nic_hw_error(hdev, true);
10914         if (ret) {
10915                 dev_err(&ae_dev->pdev->dev,
10916                         "fail(%d) to enable hw error interrupts\n", ret);
10917                 goto init_nic_err;
10918         }
10919
10920         hnae3_set_client_init_flag(client, ae_dev, 1);
10921
10922         if (netif_msg_drv(&hdev->vport->nic))
10923                 hclge_info_show(hdev);
10924
10925         return ret;
10926
10927 init_nic_err:
10928         clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state);
10929         while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
10930                 msleep(HCLGE_WAIT_RESET_DONE);
10931
10932         client->ops->uninit_instance(&vport->nic, 0);
10933
10934         return ret;
10935 }
10936
10937 static int hclge_init_roce_client_instance(struct hnae3_ae_dev *ae_dev,
10938                                            struct hclge_vport *vport)
10939 {
10940         struct hclge_dev *hdev = ae_dev->priv;
10941         struct hnae3_client *client;
10942         int rst_cnt;
10943         int ret;
10944
10945         if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client ||
10946             !hdev->nic_client)
10947                 return 0;
10948
10949         client = hdev->roce_client;
10950         ret = hclge_init_roce_base_info(vport);
10951         if (ret)
10952                 return ret;
10953
10954         rst_cnt = hdev->rst_stats.reset_cnt;
10955         ret = client->ops->init_instance(&vport->roce);
10956         if (ret)
10957                 return ret;
10958
10959         set_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state);
10960         if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) ||
10961             rst_cnt != hdev->rst_stats.reset_cnt) {
10962                 ret = -EBUSY;
10963                 goto init_roce_err;
10964         }
10965
10966         /* Enable roce ras interrupts */
10967         ret = hclge_config_rocee_ras_interrupt(hdev, true);
10968         if (ret) {
10969                 dev_err(&ae_dev->pdev->dev,
10970                         "fail(%d) to enable roce ras interrupts\n", ret);
10971                 goto init_roce_err;
10972         }
10973
10974         hnae3_set_client_init_flag(client, ae_dev, 1);
10975
10976         return 0;
10977
10978 init_roce_err:
10979         clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state);
10980         while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
10981                 msleep(HCLGE_WAIT_RESET_DONE);
10982
10983         hdev->roce_client->ops->uninit_instance(&vport->roce, 0);
10984
10985         return ret;
10986 }
10987
10988 static int hclge_init_client_instance(struct hnae3_client *client,
10989                                       struct hnae3_ae_dev *ae_dev)
10990 {
10991         struct hclge_dev *hdev = ae_dev->priv;
10992         struct hclge_vport *vport = &hdev->vport[0];
10993         int ret;
10994
10995         switch (client->type) {
10996         case HNAE3_CLIENT_KNIC:
10997                 hdev->nic_client = client;
10998                 vport->nic.client = client;
10999                 ret = hclge_init_nic_client_instance(ae_dev, vport);
11000                 if (ret)
11001                         goto clear_nic;
11002
11003                 ret = hclge_init_roce_client_instance(ae_dev, vport);
11004                 if (ret)
11005                         goto clear_roce;
11006
11007                 break;
11008         case HNAE3_CLIENT_ROCE:
11009                 if (hnae3_dev_roce_supported(hdev)) {
11010                         hdev->roce_client = client;
11011                         vport->roce.client = client;
11012                 }
11013
11014                 ret = hclge_init_roce_client_instance(ae_dev, vport);
11015                 if (ret)
11016                         goto clear_roce;
11017
11018                 break;
11019         default:
11020                 return -EINVAL;
11021         }
11022
11023         return 0;
11024
11025 clear_nic:
11026         hdev->nic_client = NULL;
11027         vport->nic.client = NULL;
11028         return ret;
11029 clear_roce:
11030         hdev->roce_client = NULL;
11031         vport->roce.client = NULL;
11032         return ret;
11033 }
11034
11035 static void hclge_uninit_client_instance(struct hnae3_client *client,
11036                                          struct hnae3_ae_dev *ae_dev)
11037 {
11038         struct hclge_dev *hdev = ae_dev->priv;
11039         struct hclge_vport *vport = &hdev->vport[0];
11040
11041         if (hdev->roce_client) {
11042                 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state);
11043                 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
11044                         msleep(HCLGE_WAIT_RESET_DONE);
11045
11046                 hdev->roce_client->ops->uninit_instance(&vport->roce, 0);
11047                 hdev->roce_client = NULL;
11048                 vport->roce.client = NULL;
11049         }
11050         if (client->type == HNAE3_CLIENT_ROCE)
11051                 return;
11052         if (hdev->nic_client && client->ops->uninit_instance) {
11053                 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state);
11054                 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
11055                         msleep(HCLGE_WAIT_RESET_DONE);
11056
11057                 client->ops->uninit_instance(&vport->nic, 0);
11058                 hdev->nic_client = NULL;
11059                 vport->nic.client = NULL;
11060         }
11061 }
11062
11063 static int hclge_dev_mem_map(struct hclge_dev *hdev)
11064 {
11065         struct pci_dev *pdev = hdev->pdev;
11066         struct hclge_hw *hw = &hdev->hw;
11067
11068         /* for device does not have device memory, return directly */
11069         if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGE_MEM_BAR)))
11070                 return 0;
11071
11072         hw->hw.mem_base =
11073                 devm_ioremap_wc(&pdev->dev,
11074                                 pci_resource_start(pdev, HCLGE_MEM_BAR),
11075                                 pci_resource_len(pdev, HCLGE_MEM_BAR));
11076         if (!hw->hw.mem_base) {
11077                 dev_err(&pdev->dev, "failed to map device memory\n");
11078                 return -EFAULT;
11079         }
11080
11081         return 0;
11082 }
11083
11084 static int hclge_pci_init(struct hclge_dev *hdev)
11085 {
11086         struct pci_dev *pdev = hdev->pdev;
11087         struct hclge_hw *hw;
11088         int ret;
11089
11090         ret = pci_enable_device(pdev);
11091         if (ret) {
11092                 dev_err(&pdev->dev, "failed to enable PCI device\n");
11093                 return ret;
11094         }
11095
11096         ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
11097         if (ret) {
11098                 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
11099                 if (ret) {
11100                         dev_err(&pdev->dev,
11101                                 "can't set consistent PCI DMA");
11102                         goto err_disable_device;
11103                 }
11104                 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
11105         }
11106
11107         ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
11108         if (ret) {
11109                 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
11110                 goto err_disable_device;
11111         }
11112
11113         pci_set_master(pdev);
11114         hw = &hdev->hw;
11115         hw->hw.io_base = pcim_iomap(pdev, 2, 0);
11116         if (!hw->hw.io_base) {
11117                 dev_err(&pdev->dev, "Can't map configuration register space\n");
11118                 ret = -ENOMEM;
11119                 goto err_clr_master;
11120         }
11121
11122         ret = hclge_dev_mem_map(hdev);
11123         if (ret)
11124                 goto err_unmap_io_base;
11125
11126         hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
11127
11128         return 0;
11129
11130 err_unmap_io_base:
11131         pcim_iounmap(pdev, hdev->hw.hw.io_base);
11132 err_clr_master:
11133         pci_clear_master(pdev);
11134         pci_release_regions(pdev);
11135 err_disable_device:
11136         pci_disable_device(pdev);
11137
11138         return ret;
11139 }
11140
11141 static void hclge_pci_uninit(struct hclge_dev *hdev)
11142 {
11143         struct pci_dev *pdev = hdev->pdev;
11144
11145         if (hdev->hw.hw.mem_base)
11146                 devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base);
11147
11148         pcim_iounmap(pdev, hdev->hw.hw.io_base);
11149         pci_free_irq_vectors(pdev);
11150         pci_clear_master(pdev);
11151         pci_release_mem_regions(pdev);
11152         pci_disable_device(pdev);
11153 }
11154
11155 static void hclge_state_init(struct hclge_dev *hdev)
11156 {
11157         set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
11158         set_bit(HCLGE_STATE_DOWN, &hdev->state);
11159         clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
11160         clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
11161         clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state);
11162         clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
11163         clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
11164 }
11165
11166 static void hclge_state_uninit(struct hclge_dev *hdev)
11167 {
11168         set_bit(HCLGE_STATE_DOWN, &hdev->state);
11169         set_bit(HCLGE_STATE_REMOVING, &hdev->state);
11170
11171         if (hdev->reset_timer.function)
11172                 del_timer_sync(&hdev->reset_timer);
11173         if (hdev->service_task.work.func)
11174                 cancel_delayed_work_sync(&hdev->service_task);
11175 }
11176
11177 static void hclge_reset_prepare_general(struct hnae3_ae_dev *ae_dev,
11178                                         enum hnae3_reset_type rst_type)
11179 {
11180 #define HCLGE_RESET_RETRY_WAIT_MS       500
11181 #define HCLGE_RESET_RETRY_CNT   5
11182
11183         struct hclge_dev *hdev = ae_dev->priv;
11184         int retry_cnt = 0;
11185         int ret;
11186
11187         while (retry_cnt++ < HCLGE_RESET_RETRY_CNT) {
11188                 down(&hdev->reset_sem);
11189                 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
11190                 hdev->reset_type = rst_type;
11191                 ret = hclge_reset_prepare(hdev);
11192                 if (!ret && !hdev->reset_pending)
11193                         break;
11194
11195                 dev_err(&hdev->pdev->dev,
11196                         "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n",
11197                         ret, hdev->reset_pending, retry_cnt);
11198                 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
11199                 up(&hdev->reset_sem);
11200                 msleep(HCLGE_RESET_RETRY_WAIT_MS);
11201         }
11202
11203         /* disable misc vector before reset done */
11204         hclge_enable_vector(&hdev->misc_vector, false);
11205         set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
11206
11207         if (hdev->reset_type == HNAE3_FLR_RESET)
11208                 hdev->rst_stats.flr_rst_cnt++;
11209 }
11210
11211 static void hclge_reset_done(struct hnae3_ae_dev *ae_dev)
11212 {
11213         struct hclge_dev *hdev = ae_dev->priv;
11214         int ret;
11215
11216         hclge_enable_vector(&hdev->misc_vector, true);
11217
11218         ret = hclge_reset_rebuild(hdev);
11219         if (ret)
11220                 dev_err(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", ret);
11221
11222         hdev->reset_type = HNAE3_NONE_RESET;
11223         clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
11224         up(&hdev->reset_sem);
11225 }
11226
11227 static void hclge_clear_resetting_state(struct hclge_dev *hdev)
11228 {
11229         u16 i;
11230
11231         for (i = 0; i < hdev->num_alloc_vport; i++) {
11232                 struct hclge_vport *vport = &hdev->vport[i];
11233                 int ret;
11234
11235                  /* Send cmd to clear vport's FUNC_RST_ING */
11236                 ret = hclge_set_vf_rst(hdev, vport->vport_id, false);
11237                 if (ret)
11238                         dev_warn(&hdev->pdev->dev,
11239                                  "clear vport(%u) rst failed %d!\n",
11240                                  vport->vport_id, ret);
11241         }
11242 }
11243
11244 static int hclge_clear_hw_resource(struct hclge_dev *hdev)
11245 {
11246         struct hclge_desc desc;
11247         int ret;
11248
11249         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CLEAR_HW_RESOURCE, false);
11250
11251         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
11252         /* This new command is only supported by new firmware, it will
11253          * fail with older firmware. Error value -EOPNOSUPP can only be
11254          * returned by older firmware running this command, to keep code
11255          * backward compatible we will override this value and return
11256          * success.
11257          */
11258         if (ret && ret != -EOPNOTSUPP) {
11259                 dev_err(&hdev->pdev->dev,
11260                         "failed to clear hw resource, ret = %d\n", ret);
11261                 return ret;
11262         }
11263         return 0;
11264 }
11265
11266 static void hclge_init_rxd_adv_layout(struct hclge_dev *hdev)
11267 {
11268         if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev))
11269                 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 1);
11270 }
11271
11272 static void hclge_uninit_rxd_adv_layout(struct hclge_dev *hdev)
11273 {
11274         if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev))
11275                 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 0);
11276 }
11277
11278 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
11279 {
11280         struct pci_dev *pdev = ae_dev->pdev;
11281         struct hclge_dev *hdev;
11282         int ret;
11283
11284         hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
11285         if (!hdev)
11286                 return -ENOMEM;
11287
11288         hdev->pdev = pdev;
11289         hdev->ae_dev = ae_dev;
11290         hdev->reset_type = HNAE3_NONE_RESET;
11291         hdev->reset_level = HNAE3_FUNC_RESET;
11292         ae_dev->priv = hdev;
11293
11294         /* HW supprt 2 layer vlan */
11295         hdev->mps = ETH_FRAME_LEN + ETH_FCS_LEN + 2 * VLAN_HLEN;
11296
11297         mutex_init(&hdev->vport_lock);
11298         spin_lock_init(&hdev->fd_rule_lock);
11299         sema_init(&hdev->reset_sem, 1);
11300
11301         ret = hclge_pci_init(hdev);
11302         if (ret)
11303                 goto out;
11304
11305         ret = hclge_devlink_init(hdev);
11306         if (ret)
11307                 goto err_pci_uninit;
11308
11309         /* Firmware command queue initialize */
11310         ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw);
11311         if (ret)
11312                 goto err_devlink_uninit;
11313
11314         /* Firmware command initialize */
11315         ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version,
11316                                   true, hdev->reset_pending);
11317         if (ret)
11318                 goto err_cmd_uninit;
11319
11320         ret  = hclge_clear_hw_resource(hdev);
11321         if (ret)
11322                 goto err_cmd_uninit;
11323
11324         ret = hclge_get_cap(hdev);
11325         if (ret)
11326                 goto err_cmd_uninit;
11327
11328         ret = hclge_query_dev_specs(hdev);
11329         if (ret) {
11330                 dev_err(&pdev->dev, "failed to query dev specifications, ret = %d.\n",
11331                         ret);
11332                 goto err_cmd_uninit;
11333         }
11334
11335         ret = hclge_configure(hdev);
11336         if (ret) {
11337                 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
11338                 goto err_cmd_uninit;
11339         }
11340
11341         ret = hclge_init_msi(hdev);
11342         if (ret) {
11343                 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
11344                 goto err_cmd_uninit;
11345         }
11346
11347         ret = hclge_misc_irq_init(hdev);
11348         if (ret)
11349                 goto err_msi_uninit;
11350
11351         ret = hclge_alloc_tqps(hdev);
11352         if (ret) {
11353                 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
11354                 goto err_msi_irq_uninit;
11355         }
11356
11357         ret = hclge_alloc_vport(hdev);
11358         if (ret)
11359                 goto err_msi_irq_uninit;
11360
11361         ret = hclge_map_tqp(hdev);
11362         if (ret)
11363                 goto err_msi_irq_uninit;
11364
11365         if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER &&
11366             !hnae3_dev_phy_imp_supported(hdev)) {
11367                 ret = hclge_mac_mdio_config(hdev);
11368                 if (ret)
11369                         goto err_msi_irq_uninit;
11370         }
11371
11372         ret = hclge_init_umv_space(hdev);
11373         if (ret)
11374                 goto err_mdiobus_unreg;
11375
11376         ret = hclge_mac_init(hdev);
11377         if (ret) {
11378                 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
11379                 goto err_mdiobus_unreg;
11380         }
11381
11382         ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
11383         if (ret) {
11384                 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
11385                 goto err_mdiobus_unreg;
11386         }
11387
11388         ret = hclge_config_gro(hdev);
11389         if (ret)
11390                 goto err_mdiobus_unreg;
11391
11392         ret = hclge_init_vlan_config(hdev);
11393         if (ret) {
11394                 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
11395                 goto err_mdiobus_unreg;
11396         }
11397
11398         ret = hclge_tm_schd_init(hdev);
11399         if (ret) {
11400                 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
11401                 goto err_mdiobus_unreg;
11402         }
11403
11404         ret = hclge_comm_rss_init_cfg(&hdev->vport->nic, hdev->ae_dev,
11405                                       &hdev->rss_cfg);
11406         if (ret) {
11407                 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret);
11408                 goto err_mdiobus_unreg;
11409         }
11410
11411         ret = hclge_rss_init_hw(hdev);
11412         if (ret) {
11413                 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
11414                 goto err_mdiobus_unreg;
11415         }
11416
11417         ret = init_mgr_tbl(hdev);
11418         if (ret) {
11419                 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret);
11420                 goto err_mdiobus_unreg;
11421         }
11422
11423         ret = hclge_init_fd_config(hdev);
11424         if (ret) {
11425                 dev_err(&pdev->dev,
11426                         "fd table init fail, ret=%d\n", ret);
11427                 goto err_mdiobus_unreg;
11428         }
11429
11430         ret = hclge_ptp_init(hdev);
11431         if (ret)
11432                 goto err_mdiobus_unreg;
11433
11434         INIT_KFIFO(hdev->mac_tnl_log);
11435
11436         hclge_dcb_ops_set(hdev);
11437
11438         timer_setup(&hdev->reset_timer, hclge_reset_timer, 0);
11439         INIT_DELAYED_WORK(&hdev->service_task, hclge_service_task);
11440
11441         hclge_clear_all_event_cause(hdev);
11442         hclge_clear_resetting_state(hdev);
11443
11444         /* Log and clear the hw errors those already occurred */
11445         if (hnae3_dev_ras_imp_supported(hdev))
11446                 hclge_handle_occurred_error(hdev);
11447         else
11448                 hclge_handle_all_hns_hw_errors(ae_dev);
11449
11450         /* request delayed reset for the error recovery because an immediate
11451          * global reset on a PF affecting pending initialization of other PFs
11452          */
11453         if (ae_dev->hw_err_reset_req) {
11454                 enum hnae3_reset_type reset_level;
11455
11456                 reset_level = hclge_get_reset_level(ae_dev,
11457                                                     &ae_dev->hw_err_reset_req);
11458                 hclge_set_def_reset_request(ae_dev, reset_level);
11459                 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL);
11460         }
11461
11462         hclge_init_rxd_adv_layout(hdev);
11463
11464         /* Enable MISC vector(vector0) */
11465         hclge_enable_vector(&hdev->misc_vector, true);
11466
11467         hclge_state_init(hdev);
11468         hdev->last_reset_time = jiffies;
11469
11470         dev_info(&hdev->pdev->dev, "%s driver initialization finished.\n",
11471                  HCLGE_DRIVER_NAME);
11472
11473         hclge_task_schedule(hdev, round_jiffies_relative(HZ));
11474
11475         return 0;
11476
11477 err_mdiobus_unreg:
11478         if (hdev->hw.mac.phydev)
11479                 mdiobus_unregister(hdev->hw.mac.mdio_bus);
11480 err_msi_irq_uninit:
11481         hclge_misc_irq_uninit(hdev);
11482 err_msi_uninit:
11483         pci_free_irq_vectors(pdev);
11484 err_cmd_uninit:
11485         hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw);
11486 err_devlink_uninit:
11487         hclge_devlink_uninit(hdev);
11488 err_pci_uninit:
11489         pcim_iounmap(pdev, hdev->hw.hw.io_base);
11490         pci_clear_master(pdev);
11491         pci_release_regions(pdev);
11492         pci_disable_device(pdev);
11493 out:
11494         mutex_destroy(&hdev->vport_lock);
11495         return ret;
11496 }
11497
11498 static void hclge_stats_clear(struct hclge_dev *hdev)
11499 {
11500         memset(&hdev->mac_stats, 0, sizeof(hdev->mac_stats));
11501 }
11502
11503 static int hclge_set_mac_spoofchk(struct hclge_dev *hdev, int vf, bool enable)
11504 {
11505         return hclge_config_switch_param(hdev, vf, enable,
11506                                          HCLGE_SWITCH_ANTI_SPOOF_MASK);
11507 }
11508
11509 static int hclge_set_vlan_spoofchk(struct hclge_dev *hdev, int vf, bool enable)
11510 {
11511         return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
11512                                           HCLGE_FILTER_FE_NIC_INGRESS_B,
11513                                           enable, vf);
11514 }
11515
11516 static int hclge_set_vf_spoofchk_hw(struct hclge_dev *hdev, int vf, bool enable)
11517 {
11518         int ret;
11519
11520         ret = hclge_set_mac_spoofchk(hdev, vf, enable);
11521         if (ret) {
11522                 dev_err(&hdev->pdev->dev,
11523                         "Set vf %d mac spoof check %s failed, ret=%d\n",
11524                         vf, enable ? "on" : "off", ret);
11525                 return ret;
11526         }
11527
11528         ret = hclge_set_vlan_spoofchk(hdev, vf, enable);
11529         if (ret)
11530                 dev_err(&hdev->pdev->dev,
11531                         "Set vf %d vlan spoof check %s failed, ret=%d\n",
11532                         vf, enable ? "on" : "off", ret);
11533
11534         return ret;
11535 }
11536
11537 static int hclge_set_vf_spoofchk(struct hnae3_handle *handle, int vf,
11538                                  bool enable)
11539 {
11540         struct hclge_vport *vport = hclge_get_vport(handle);
11541         struct hclge_dev *hdev = vport->back;
11542         u32 new_spoofchk = enable ? 1 : 0;
11543         int ret;
11544
11545         if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
11546                 return -EOPNOTSUPP;
11547
11548         vport = hclge_get_vf_vport(hdev, vf);
11549         if (!vport)
11550                 return -EINVAL;
11551
11552         if (vport->vf_info.spoofchk == new_spoofchk)
11553                 return 0;
11554
11555         if (enable && test_bit(vport->vport_id, hdev->vf_vlan_full))
11556                 dev_warn(&hdev->pdev->dev,
11557                          "vf %d vlan table is full, enable spoof check may cause its packet send fail\n",
11558                          vf);
11559         else if (enable && hclge_is_umv_space_full(vport, true))
11560                 dev_warn(&hdev->pdev->dev,
11561                          "vf %d mac table is full, enable spoof check may cause its packet send fail\n",
11562                          vf);
11563
11564         ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, enable);
11565         if (ret)
11566                 return ret;
11567
11568         vport->vf_info.spoofchk = new_spoofchk;
11569         return 0;
11570 }
11571
11572 static int hclge_reset_vport_spoofchk(struct hclge_dev *hdev)
11573 {
11574         struct hclge_vport *vport = hdev->vport;
11575         int ret;
11576         int i;
11577
11578         if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
11579                 return 0;
11580
11581         /* resume the vf spoof check state after reset */
11582         for (i = 0; i < hdev->num_alloc_vport; i++) {
11583                 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id,
11584                                                vport->vf_info.spoofchk);
11585                 if (ret)
11586                         return ret;
11587
11588                 vport++;
11589         }
11590
11591         return 0;
11592 }
11593
11594 static int hclge_set_vf_trust(struct hnae3_handle *handle, int vf, bool enable)
11595 {
11596         struct hclge_vport *vport = hclge_get_vport(handle);
11597         struct hclge_dev *hdev = vport->back;
11598         u32 new_trusted = enable ? 1 : 0;
11599
11600         vport = hclge_get_vf_vport(hdev, vf);
11601         if (!vport)
11602                 return -EINVAL;
11603
11604         if (vport->vf_info.trusted == new_trusted)
11605                 return 0;
11606
11607         vport->vf_info.trusted = new_trusted;
11608         set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
11609         hclge_task_schedule(hdev, 0);
11610
11611         return 0;
11612 }
11613
11614 static void hclge_reset_vf_rate(struct hclge_dev *hdev)
11615 {
11616         int ret;
11617         int vf;
11618
11619         /* reset vf rate to default value */
11620         for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) {
11621                 struct hclge_vport *vport = &hdev->vport[vf];
11622
11623                 vport->vf_info.max_tx_rate = 0;
11624                 ret = hclge_tm_qs_shaper_cfg(vport, vport->vf_info.max_tx_rate);
11625                 if (ret)
11626                         dev_err(&hdev->pdev->dev,
11627                                 "vf%d failed to reset to default, ret=%d\n",
11628                                 vf - HCLGE_VF_VPORT_START_NUM, ret);
11629         }
11630 }
11631
11632 static int hclge_vf_rate_param_check(struct hclge_dev *hdev,
11633                                      int min_tx_rate, int max_tx_rate)
11634 {
11635         if (min_tx_rate != 0 ||
11636             max_tx_rate < 0 || max_tx_rate > hdev->hw.mac.max_speed) {
11637                 dev_err(&hdev->pdev->dev,
11638                         "min_tx_rate:%d [0], max_tx_rate:%d [0, %u]\n",
11639                         min_tx_rate, max_tx_rate, hdev->hw.mac.max_speed);
11640                 return -EINVAL;
11641         }
11642
11643         return 0;
11644 }
11645
11646 static int hclge_set_vf_rate(struct hnae3_handle *handle, int vf,
11647                              int min_tx_rate, int max_tx_rate, bool force)
11648 {
11649         struct hclge_vport *vport = hclge_get_vport(handle);
11650         struct hclge_dev *hdev = vport->back;
11651         int ret;
11652
11653         ret = hclge_vf_rate_param_check(hdev, min_tx_rate, max_tx_rate);
11654         if (ret)
11655                 return ret;
11656
11657         vport = hclge_get_vf_vport(hdev, vf);
11658         if (!vport)
11659                 return -EINVAL;
11660
11661         if (!force && max_tx_rate == vport->vf_info.max_tx_rate)
11662                 return 0;
11663
11664         ret = hclge_tm_qs_shaper_cfg(vport, max_tx_rate);
11665         if (ret)
11666                 return ret;
11667
11668         vport->vf_info.max_tx_rate = max_tx_rate;
11669
11670         return 0;
11671 }
11672
11673 static int hclge_resume_vf_rate(struct hclge_dev *hdev)
11674 {
11675         struct hnae3_handle *handle = &hdev->vport->nic;
11676         struct hclge_vport *vport;
11677         int ret;
11678         int vf;
11679
11680         /* resume the vf max_tx_rate after reset */
11681         for (vf = 0; vf < pci_num_vf(hdev->pdev); vf++) {
11682                 vport = hclge_get_vf_vport(hdev, vf);
11683                 if (!vport)
11684                         return -EINVAL;
11685
11686                 /* zero means max rate, after reset, firmware already set it to
11687                  * max rate, so just continue.
11688                  */
11689                 if (!vport->vf_info.max_tx_rate)
11690                         continue;
11691
11692                 ret = hclge_set_vf_rate(handle, vf, 0,
11693                                         vport->vf_info.max_tx_rate, true);
11694                 if (ret) {
11695                         dev_err(&hdev->pdev->dev,
11696                                 "vf%d failed to resume tx_rate:%u, ret=%d\n",
11697                                 vf, vport->vf_info.max_tx_rate, ret);
11698                         return ret;
11699                 }
11700         }
11701
11702         return 0;
11703 }
11704
11705 static void hclge_reset_vport_state(struct hclge_dev *hdev)
11706 {
11707         struct hclge_vport *vport = hdev->vport;
11708         int i;
11709
11710         for (i = 0; i < hdev->num_alloc_vport; i++) {
11711                 hclge_vport_stop(vport);
11712                 vport++;
11713         }
11714 }
11715
11716 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
11717 {
11718         struct hclge_dev *hdev = ae_dev->priv;
11719         struct pci_dev *pdev = ae_dev->pdev;
11720         int ret;
11721
11722         set_bit(HCLGE_STATE_DOWN, &hdev->state);
11723
11724         hclge_stats_clear(hdev);
11725         /* NOTE: pf reset needn't to clear or restore pf and vf table entry.
11726          * so here should not clean table in memory.
11727          */
11728         if (hdev->reset_type == HNAE3_IMP_RESET ||
11729             hdev->reset_type == HNAE3_GLOBAL_RESET) {
11730                 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table));
11731                 memset(hdev->vf_vlan_full, 0, sizeof(hdev->vf_vlan_full));
11732                 bitmap_set(hdev->vport_config_block, 0, hdev->num_alloc_vport);
11733                 hclge_reset_umv_space(hdev);
11734         }
11735
11736         ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version,
11737                                   true, hdev->reset_pending);
11738         if (ret) {
11739                 dev_err(&pdev->dev, "Cmd queue init failed\n");
11740                 return ret;
11741         }
11742
11743         ret = hclge_map_tqp(hdev);
11744         if (ret) {
11745                 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
11746                 return ret;
11747         }
11748
11749         ret = hclge_mac_init(hdev);
11750         if (ret) {
11751                 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
11752                 return ret;
11753         }
11754
11755         ret = hclge_tp_port_init(hdev);
11756         if (ret) {
11757                 dev_err(&pdev->dev, "failed to init tp port, ret = %d\n",
11758                         ret);
11759                 return ret;
11760         }
11761
11762         ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
11763         if (ret) {
11764                 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
11765                 return ret;
11766         }
11767
11768         ret = hclge_config_gro(hdev);
11769         if (ret)
11770                 return ret;
11771
11772         ret = hclge_init_vlan_config(hdev);
11773         if (ret) {
11774                 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
11775                 return ret;
11776         }
11777
11778         ret = hclge_tm_init_hw(hdev, true);
11779         if (ret) {
11780                 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret);
11781                 return ret;
11782         }
11783
11784         ret = hclge_rss_init_hw(hdev);
11785         if (ret) {
11786                 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
11787                 return ret;
11788         }
11789
11790         ret = init_mgr_tbl(hdev);
11791         if (ret) {
11792                 dev_err(&pdev->dev,
11793                         "failed to reinit manager table, ret = %d\n", ret);
11794                 return ret;
11795         }
11796
11797         ret = hclge_init_fd_config(hdev);
11798         if (ret) {
11799                 dev_err(&pdev->dev, "fd table init fail, ret=%d\n", ret);
11800                 return ret;
11801         }
11802
11803         ret = hclge_ptp_init(hdev);
11804         if (ret)
11805                 return ret;
11806
11807         /* Log and clear the hw errors those already occurred */
11808         if (hnae3_dev_ras_imp_supported(hdev))
11809                 hclge_handle_occurred_error(hdev);
11810         else
11811                 hclge_handle_all_hns_hw_errors(ae_dev);
11812
11813         /* Re-enable the hw error interrupts because
11814          * the interrupts get disabled on global reset.
11815          */
11816         ret = hclge_config_nic_hw_error(hdev, true);
11817         if (ret) {
11818                 dev_err(&pdev->dev,
11819                         "fail(%d) to re-enable NIC hw error interrupts\n",
11820                         ret);
11821                 return ret;
11822         }
11823
11824         if (hdev->roce_client) {
11825                 ret = hclge_config_rocee_ras_interrupt(hdev, true);
11826                 if (ret) {
11827                         dev_err(&pdev->dev,
11828                                 "fail(%d) to re-enable roce ras interrupts\n",
11829                                 ret);
11830                         return ret;
11831                 }
11832         }
11833
11834         hclge_reset_vport_state(hdev);
11835         ret = hclge_reset_vport_spoofchk(hdev);
11836         if (ret)
11837                 return ret;
11838
11839         ret = hclge_resume_vf_rate(hdev);
11840         if (ret)
11841                 return ret;
11842
11843         hclge_init_rxd_adv_layout(hdev);
11844
11845         dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
11846                  HCLGE_DRIVER_NAME);
11847
11848         return 0;
11849 }
11850
11851 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
11852 {
11853         struct hclge_dev *hdev = ae_dev->priv;
11854         struct hclge_mac *mac = &hdev->hw.mac;
11855
11856         hclge_reset_vf_rate(hdev);
11857         hclge_clear_vf_vlan(hdev);
11858         hclge_state_uninit(hdev);
11859         hclge_ptp_uninit(hdev);
11860         hclge_uninit_rxd_adv_layout(hdev);
11861         hclge_uninit_mac_table(hdev);
11862         hclge_del_all_fd_entries(hdev);
11863
11864         if (mac->phydev)
11865                 mdiobus_unregister(mac->mdio_bus);
11866
11867         /* Disable MISC vector(vector0) */
11868         hclge_enable_vector(&hdev->misc_vector, false);
11869         synchronize_irq(hdev->misc_vector.vector_irq);
11870
11871         /* Disable all hw interrupts */
11872         hclge_config_mac_tnl_int(hdev, false);
11873         hclge_config_nic_hw_error(hdev, false);
11874         hclge_config_rocee_ras_interrupt(hdev, false);
11875
11876         hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw);
11877         hclge_misc_irq_uninit(hdev);
11878         hclge_devlink_uninit(hdev);
11879         hclge_pci_uninit(hdev);
11880         hclge_uninit_vport_vlan_table(hdev);
11881         mutex_destroy(&hdev->vport_lock);
11882         ae_dev->priv = NULL;
11883 }
11884
11885 static u32 hclge_get_max_channels(struct hnae3_handle *handle)
11886 {
11887         struct hclge_vport *vport = hclge_get_vport(handle);
11888         struct hclge_dev *hdev = vport->back;
11889
11890         return min_t(u32, hdev->pf_rss_size_max, vport->alloc_tqps);
11891 }
11892
11893 static void hclge_get_channels(struct hnae3_handle *handle,
11894                                struct ethtool_channels *ch)
11895 {
11896         ch->max_combined = hclge_get_max_channels(handle);
11897         ch->other_count = 1;
11898         ch->max_other = 1;
11899         ch->combined_count = handle->kinfo.rss_size;
11900 }
11901
11902 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
11903                                         u16 *alloc_tqps, u16 *max_rss_size)
11904 {
11905         struct hclge_vport *vport = hclge_get_vport(handle);
11906         struct hclge_dev *hdev = vport->back;
11907
11908         *alloc_tqps = vport->alloc_tqps;
11909         *max_rss_size = hdev->pf_rss_size_max;
11910 }
11911
11912 static int hclge_set_rss_tc_mode_cfg(struct hnae3_handle *handle)
11913 {
11914         struct hclge_vport *vport = hclge_get_vport(handle);
11915         u16 tc_offset[HCLGE_MAX_TC_NUM] = {0};
11916         struct hclge_dev *hdev = vport->back;
11917         u16 tc_size[HCLGE_MAX_TC_NUM] = {0};
11918         u16 tc_valid[HCLGE_MAX_TC_NUM];
11919         u16 roundup_size;
11920         unsigned int i;
11921
11922         roundup_size = roundup_pow_of_two(vport->nic.kinfo.rss_size);
11923         roundup_size = ilog2(roundup_size);
11924         /* Set the RSS TC mode according to the new RSS size */
11925         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
11926                 tc_valid[i] = 0;
11927
11928                 if (!(hdev->hw_tc_map & BIT(i)))
11929                         continue;
11930
11931                 tc_valid[i] = 1;
11932                 tc_size[i] = roundup_size;
11933                 tc_offset[i] = vport->nic.kinfo.rss_size * i;
11934         }
11935
11936         return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid,
11937                                           tc_size);
11938 }
11939
11940 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num,
11941                               bool rxfh_configured)
11942 {
11943         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
11944         struct hclge_vport *vport = hclge_get_vport(handle);
11945         struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
11946         struct hclge_dev *hdev = vport->back;
11947         u16 cur_rss_size = kinfo->rss_size;
11948         u16 cur_tqps = kinfo->num_tqps;
11949         u32 *rss_indir;
11950         unsigned int i;
11951         int ret;
11952
11953         kinfo->req_rss_size = new_tqps_num;
11954
11955         ret = hclge_tm_vport_map_update(hdev);
11956         if (ret) {
11957                 dev_err(&hdev->pdev->dev, "tm vport map fail, ret =%d\n", ret);
11958                 return ret;
11959         }
11960
11961         ret = hclge_set_rss_tc_mode_cfg(handle);
11962         if (ret)
11963                 return ret;
11964
11965         /* RSS indirection table has been configured by user */
11966         if (rxfh_configured)
11967                 goto out;
11968
11969         /* Reinitializes the rss indirect table according to the new RSS size */
11970         rss_indir = kcalloc(ae_dev->dev_specs.rss_ind_tbl_size, sizeof(u32),
11971                             GFP_KERNEL);
11972         if (!rss_indir)
11973                 return -ENOMEM;
11974
11975         for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++)
11976                 rss_indir[i] = i % kinfo->rss_size;
11977
11978         ret = hclge_set_rss(handle, rss_indir, NULL, 0);
11979         if (ret)
11980                 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
11981                         ret);
11982
11983         kfree(rss_indir);
11984
11985 out:
11986         if (!ret)
11987                 dev_info(&hdev->pdev->dev,
11988                          "Channels changed, rss_size from %u to %u, tqps from %u to %u",
11989                          cur_rss_size, kinfo->rss_size,
11990                          cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc);
11991
11992         return ret;
11993 }
11994
11995 static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit,
11996                               u32 *regs_num_64_bit)
11997 {
11998         struct hclge_desc desc;
11999         u32 total_num;
12000         int ret;
12001
12002         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true);
12003         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
12004         if (ret) {
12005                 dev_err(&hdev->pdev->dev,
12006                         "Query register number cmd failed, ret = %d.\n", ret);
12007                 return ret;
12008         }
12009
12010         *regs_num_32_bit = le32_to_cpu(desc.data[0]);
12011         *regs_num_64_bit = le32_to_cpu(desc.data[1]);
12012
12013         total_num = *regs_num_32_bit + *regs_num_64_bit;
12014         if (!total_num)
12015                 return -EINVAL;
12016
12017         return 0;
12018 }
12019
12020 static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num,
12021                                  void *data)
12022 {
12023 #define HCLGE_32_BIT_REG_RTN_DATANUM 8
12024 #define HCLGE_32_BIT_DESC_NODATA_LEN 2
12025
12026         struct hclge_desc *desc;
12027         u32 *reg_val = data;
12028         __le32 *desc_data;
12029         int nodata_num;
12030         int cmd_num;
12031         int i, k, n;
12032         int ret;
12033
12034         if (regs_num == 0)
12035                 return 0;
12036
12037         nodata_num = HCLGE_32_BIT_DESC_NODATA_LEN;
12038         cmd_num = DIV_ROUND_UP(regs_num + nodata_num,
12039                                HCLGE_32_BIT_REG_RTN_DATANUM);
12040         desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
12041         if (!desc)
12042                 return -ENOMEM;
12043
12044         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true);
12045         ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
12046         if (ret) {
12047                 dev_err(&hdev->pdev->dev,
12048                         "Query 32 bit register cmd failed, ret = %d.\n", ret);
12049                 kfree(desc);
12050                 return ret;
12051         }
12052
12053         for (i = 0; i < cmd_num; i++) {
12054                 if (i == 0) {
12055                         desc_data = (__le32 *)(&desc[i].data[0]);
12056                         n = HCLGE_32_BIT_REG_RTN_DATANUM - nodata_num;
12057                 } else {
12058                         desc_data = (__le32 *)(&desc[i]);
12059                         n = HCLGE_32_BIT_REG_RTN_DATANUM;
12060                 }
12061                 for (k = 0; k < n; k++) {
12062                         *reg_val++ = le32_to_cpu(*desc_data++);
12063
12064                         regs_num--;
12065                         if (!regs_num)
12066                                 break;
12067                 }
12068         }
12069
12070         kfree(desc);
12071         return 0;
12072 }
12073
12074 static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num,
12075                                  void *data)
12076 {
12077 #define HCLGE_64_BIT_REG_RTN_DATANUM 4
12078 #define HCLGE_64_BIT_DESC_NODATA_LEN 1
12079
12080         struct hclge_desc *desc;
12081         u64 *reg_val = data;
12082         __le64 *desc_data;
12083         int nodata_len;
12084         int cmd_num;
12085         int i, k, n;
12086         int ret;
12087
12088         if (regs_num == 0)
12089                 return 0;
12090
12091         nodata_len = HCLGE_64_BIT_DESC_NODATA_LEN;
12092         cmd_num = DIV_ROUND_UP(regs_num + nodata_len,
12093                                HCLGE_64_BIT_REG_RTN_DATANUM);
12094         desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
12095         if (!desc)
12096                 return -ENOMEM;
12097
12098         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true);
12099         ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
12100         if (ret) {
12101                 dev_err(&hdev->pdev->dev,
12102                         "Query 64 bit register cmd failed, ret = %d.\n", ret);
12103                 kfree(desc);
12104                 return ret;
12105         }
12106
12107         for (i = 0; i < cmd_num; i++) {
12108                 if (i == 0) {
12109                         desc_data = (__le64 *)(&desc[i].data[0]);
12110                         n = HCLGE_64_BIT_REG_RTN_DATANUM - nodata_len;
12111                 } else {
12112                         desc_data = (__le64 *)(&desc[i]);
12113                         n = HCLGE_64_BIT_REG_RTN_DATANUM;
12114                 }
12115                 for (k = 0; k < n; k++) {
12116                         *reg_val++ = le64_to_cpu(*desc_data++);
12117
12118                         regs_num--;
12119                         if (!regs_num)
12120                                 break;
12121                 }
12122         }
12123
12124         kfree(desc);
12125         return 0;
12126 }
12127
12128 #define MAX_SEPARATE_NUM        4
12129 #define SEPARATOR_VALUE         0xFDFCFBFA
12130 #define REG_NUM_PER_LINE        4
12131 #define REG_LEN_PER_LINE        (REG_NUM_PER_LINE * sizeof(u32))
12132 #define REG_SEPARATOR_LINE      1
12133 #define REG_NUM_REMAIN_MASK     3
12134
12135 int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev, struct hclge_desc *desc)
12136 {
12137         int i;
12138
12139         /* initialize command BD except the last one */
12140         for (i = 0; i < HCLGE_GET_DFX_REG_TYPE_CNT - 1; i++) {
12141                 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_DFX_BD_NUM,
12142                                            true);
12143                 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
12144         }
12145
12146         /* initialize the last command BD */
12147         hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_DFX_BD_NUM, true);
12148
12149         return hclge_cmd_send(&hdev->hw, desc, HCLGE_GET_DFX_REG_TYPE_CNT);
12150 }
12151
12152 static int hclge_get_dfx_reg_bd_num(struct hclge_dev *hdev,
12153                                     int *bd_num_list,
12154                                     u32 type_num)
12155 {
12156         u32 entries_per_desc, desc_index, index, offset, i;
12157         struct hclge_desc desc[HCLGE_GET_DFX_REG_TYPE_CNT];
12158         int ret;
12159
12160         ret = hclge_query_bd_num_cmd_send(hdev, desc);
12161         if (ret) {
12162                 dev_err(&hdev->pdev->dev,
12163                         "Get dfx bd num fail, status is %d.\n", ret);
12164                 return ret;
12165         }
12166
12167         entries_per_desc = ARRAY_SIZE(desc[0].data);
12168         for (i = 0; i < type_num; i++) {
12169                 offset = hclge_dfx_bd_offset_list[i];
12170                 index = offset % entries_per_desc;
12171                 desc_index = offset / entries_per_desc;
12172                 bd_num_list[i] = le32_to_cpu(desc[desc_index].data[index]);
12173         }
12174
12175         return ret;
12176 }
12177
12178 static int hclge_dfx_reg_cmd_send(struct hclge_dev *hdev,
12179                                   struct hclge_desc *desc_src, int bd_num,
12180                                   enum hclge_opcode_type cmd)
12181 {
12182         struct hclge_desc *desc = desc_src;
12183         int i, ret;
12184
12185         hclge_cmd_setup_basic_desc(desc, cmd, true);
12186         for (i = 0; i < bd_num - 1; i++) {
12187                 desc->flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
12188                 desc++;
12189                 hclge_cmd_setup_basic_desc(desc, cmd, true);
12190         }
12191
12192         desc = desc_src;
12193         ret = hclge_cmd_send(&hdev->hw, desc, bd_num);
12194         if (ret)
12195                 dev_err(&hdev->pdev->dev,
12196                         "Query dfx reg cmd(0x%x) send fail, status is %d.\n",
12197                         cmd, ret);
12198
12199         return ret;
12200 }
12201
12202 static int hclge_dfx_reg_fetch_data(struct hclge_desc *desc_src, int bd_num,
12203                                     void *data)
12204 {
12205         int entries_per_desc, reg_num, separator_num, desc_index, index, i;
12206         struct hclge_desc *desc = desc_src;
12207         u32 *reg = data;
12208
12209         entries_per_desc = ARRAY_SIZE(desc->data);
12210         reg_num = entries_per_desc * bd_num;
12211         separator_num = REG_NUM_PER_LINE - (reg_num & REG_NUM_REMAIN_MASK);
12212         for (i = 0; i < reg_num; i++) {
12213                 index = i % entries_per_desc;
12214                 desc_index = i / entries_per_desc;
12215                 *reg++ = le32_to_cpu(desc[desc_index].data[index]);
12216         }
12217         for (i = 0; i < separator_num; i++)
12218                 *reg++ = SEPARATOR_VALUE;
12219
12220         return reg_num + separator_num;
12221 }
12222
12223 static int hclge_get_dfx_reg_len(struct hclge_dev *hdev, int *len)
12224 {
12225         u32 dfx_reg_type_num = ARRAY_SIZE(hclge_dfx_bd_offset_list);
12226         int data_len_per_desc, bd_num, i;
12227         int *bd_num_list;
12228         u32 data_len;
12229         int ret;
12230
12231         bd_num_list = kcalloc(dfx_reg_type_num, sizeof(int), GFP_KERNEL);
12232         if (!bd_num_list)
12233                 return -ENOMEM;
12234
12235         ret = hclge_get_dfx_reg_bd_num(hdev, bd_num_list, dfx_reg_type_num);
12236         if (ret) {
12237                 dev_err(&hdev->pdev->dev,
12238                         "Get dfx reg bd num fail, status is %d.\n", ret);
12239                 goto out;
12240         }
12241
12242         data_len_per_desc = sizeof_field(struct hclge_desc, data);
12243         *len = 0;
12244         for (i = 0; i < dfx_reg_type_num; i++) {
12245                 bd_num = bd_num_list[i];
12246                 data_len = data_len_per_desc * bd_num;
12247                 *len += (data_len / REG_LEN_PER_LINE + 1) * REG_LEN_PER_LINE;
12248         }
12249
12250 out:
12251         kfree(bd_num_list);
12252         return ret;
12253 }
12254
12255 static int hclge_get_dfx_reg(struct hclge_dev *hdev, void *data)
12256 {
12257         u32 dfx_reg_type_num = ARRAY_SIZE(hclge_dfx_bd_offset_list);
12258         int bd_num, bd_num_max, buf_len, i;
12259         struct hclge_desc *desc_src;
12260         int *bd_num_list;
12261         u32 *reg = data;
12262         int ret;
12263
12264         bd_num_list = kcalloc(dfx_reg_type_num, sizeof(int), GFP_KERNEL);
12265         if (!bd_num_list)
12266                 return -ENOMEM;
12267
12268         ret = hclge_get_dfx_reg_bd_num(hdev, bd_num_list, dfx_reg_type_num);
12269         if (ret) {
12270                 dev_err(&hdev->pdev->dev,
12271                         "Get dfx reg bd num fail, status is %d.\n", ret);
12272                 goto out;
12273         }
12274
12275         bd_num_max = bd_num_list[0];
12276         for (i = 1; i < dfx_reg_type_num; i++)
12277                 bd_num_max = max_t(int, bd_num_max, bd_num_list[i]);
12278
12279         buf_len = sizeof(*desc_src) * bd_num_max;
12280         desc_src = kzalloc(buf_len, GFP_KERNEL);
12281         if (!desc_src) {
12282                 ret = -ENOMEM;
12283                 goto out;
12284         }
12285
12286         for (i = 0; i < dfx_reg_type_num; i++) {
12287                 bd_num = bd_num_list[i];
12288                 ret = hclge_dfx_reg_cmd_send(hdev, desc_src, bd_num,
12289                                              hclge_dfx_reg_opcode_list[i]);
12290                 if (ret) {
12291                         dev_err(&hdev->pdev->dev,
12292                                 "Get dfx reg fail, status is %d.\n", ret);
12293                         break;
12294                 }
12295
12296                 reg += hclge_dfx_reg_fetch_data(desc_src, bd_num, reg);
12297         }
12298
12299         kfree(desc_src);
12300 out:
12301         kfree(bd_num_list);
12302         return ret;
12303 }
12304
12305 static int hclge_fetch_pf_reg(struct hclge_dev *hdev, void *data,
12306                               struct hnae3_knic_private_info *kinfo)
12307 {
12308 #define HCLGE_RING_REG_OFFSET           0x200
12309 #define HCLGE_RING_INT_REG_OFFSET       0x4
12310
12311         int i, j, reg_num, separator_num;
12312         int data_num_sum;
12313         u32 *reg = data;
12314
12315         /* fetching per-PF registers valus from PF PCIe register space */
12316         reg_num = ARRAY_SIZE(cmdq_reg_addr_list);
12317         separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK);
12318         for (i = 0; i < reg_num; i++)
12319                 *reg++ = hclge_read_dev(&hdev->hw, cmdq_reg_addr_list[i]);
12320         for (i = 0; i < separator_num; i++)
12321                 *reg++ = SEPARATOR_VALUE;
12322         data_num_sum = reg_num + separator_num;
12323
12324         reg_num = ARRAY_SIZE(common_reg_addr_list);
12325         separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK);
12326         for (i = 0; i < reg_num; i++)
12327                 *reg++ = hclge_read_dev(&hdev->hw, common_reg_addr_list[i]);
12328         for (i = 0; i < separator_num; i++)
12329                 *reg++ = SEPARATOR_VALUE;
12330         data_num_sum += reg_num + separator_num;
12331
12332         reg_num = ARRAY_SIZE(ring_reg_addr_list);
12333         separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK);
12334         for (j = 0; j < kinfo->num_tqps; j++) {
12335                 for (i = 0; i < reg_num; i++)
12336                         *reg++ = hclge_read_dev(&hdev->hw,
12337                                                 ring_reg_addr_list[i] +
12338                                                 HCLGE_RING_REG_OFFSET * j);
12339                 for (i = 0; i < separator_num; i++)
12340                         *reg++ = SEPARATOR_VALUE;
12341         }
12342         data_num_sum += (reg_num + separator_num) * kinfo->num_tqps;
12343
12344         reg_num = ARRAY_SIZE(tqp_intr_reg_addr_list);
12345         separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK);
12346         for (j = 0; j < hdev->num_msi_used - 1; j++) {
12347                 for (i = 0; i < reg_num; i++)
12348                         *reg++ = hclge_read_dev(&hdev->hw,
12349                                                 tqp_intr_reg_addr_list[i] +
12350                                                 HCLGE_RING_INT_REG_OFFSET * j);
12351                 for (i = 0; i < separator_num; i++)
12352                         *reg++ = SEPARATOR_VALUE;
12353         }
12354         data_num_sum += (reg_num + separator_num) * (hdev->num_msi_used - 1);
12355
12356         return data_num_sum;
12357 }
12358
12359 static int hclge_get_regs_len(struct hnae3_handle *handle)
12360 {
12361         int cmdq_lines, common_lines, ring_lines, tqp_intr_lines;
12362         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
12363         struct hclge_vport *vport = hclge_get_vport(handle);
12364         struct hclge_dev *hdev = vport->back;
12365         int regs_num_32_bit, regs_num_64_bit, dfx_regs_len;
12366         int regs_lines_32_bit, regs_lines_64_bit;
12367         int ret;
12368
12369         ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
12370         if (ret) {
12371                 dev_err(&hdev->pdev->dev,
12372                         "Get register number failed, ret = %d.\n", ret);
12373                 return ret;
12374         }
12375
12376         ret = hclge_get_dfx_reg_len(hdev, &dfx_regs_len);
12377         if (ret) {
12378                 dev_err(&hdev->pdev->dev,
12379                         "Get dfx reg len failed, ret = %d.\n", ret);
12380                 return ret;
12381         }
12382
12383         cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE +
12384                 REG_SEPARATOR_LINE;
12385         common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE +
12386                 REG_SEPARATOR_LINE;
12387         ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE +
12388                 REG_SEPARATOR_LINE;
12389         tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE +
12390                 REG_SEPARATOR_LINE;
12391         regs_lines_32_bit = regs_num_32_bit * sizeof(u32) / REG_LEN_PER_LINE +
12392                 REG_SEPARATOR_LINE;
12393         regs_lines_64_bit = regs_num_64_bit * sizeof(u64) / REG_LEN_PER_LINE +
12394                 REG_SEPARATOR_LINE;
12395
12396         return (cmdq_lines + common_lines + ring_lines * kinfo->num_tqps +
12397                 tqp_intr_lines * (hdev->num_msi_used - 1) + regs_lines_32_bit +
12398                 regs_lines_64_bit) * REG_LEN_PER_LINE + dfx_regs_len;
12399 }
12400
12401 static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
12402                            void *data)
12403 {
12404         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
12405         struct hclge_vport *vport = hclge_get_vport(handle);
12406         struct hclge_dev *hdev = vport->back;
12407         u32 regs_num_32_bit, regs_num_64_bit;
12408         int i, reg_num, separator_num, ret;
12409         u32 *reg = data;
12410
12411         *version = hdev->fw_version;
12412
12413         ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
12414         if (ret) {
12415                 dev_err(&hdev->pdev->dev,
12416                         "Get register number failed, ret = %d.\n", ret);
12417                 return;
12418         }
12419
12420         reg += hclge_fetch_pf_reg(hdev, reg, kinfo);
12421
12422         ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, reg);
12423         if (ret) {
12424                 dev_err(&hdev->pdev->dev,
12425                         "Get 32 bit register failed, ret = %d.\n", ret);
12426                 return;
12427         }
12428         reg_num = regs_num_32_bit;
12429         reg += reg_num;
12430         separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK);
12431         for (i = 0; i < separator_num; i++)
12432                 *reg++ = SEPARATOR_VALUE;
12433
12434         ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit, reg);
12435         if (ret) {
12436                 dev_err(&hdev->pdev->dev,
12437                         "Get 64 bit register failed, ret = %d.\n", ret);
12438                 return;
12439         }
12440         reg_num = regs_num_64_bit * 2;
12441         reg += reg_num;
12442         separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK);
12443         for (i = 0; i < separator_num; i++)
12444                 *reg++ = SEPARATOR_VALUE;
12445
12446         ret = hclge_get_dfx_reg(hdev, reg);
12447         if (ret)
12448                 dev_err(&hdev->pdev->dev,
12449                         "Get dfx register failed, ret = %d.\n", ret);
12450 }
12451
12452 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status)
12453 {
12454         struct hclge_set_led_state_cmd *req;
12455         struct hclge_desc desc;
12456         int ret;
12457
12458         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false);
12459
12460         req = (struct hclge_set_led_state_cmd *)desc.data;
12461         hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M,
12462                         HCLGE_LED_LOCATE_STATE_S, locate_led_status);
12463
12464         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
12465         if (ret)
12466                 dev_err(&hdev->pdev->dev,
12467                         "Send set led state cmd error, ret =%d\n", ret);
12468
12469         return ret;
12470 }
12471
12472 enum hclge_led_status {
12473         HCLGE_LED_OFF,
12474         HCLGE_LED_ON,
12475         HCLGE_LED_NO_CHANGE = 0xFF,
12476 };
12477
12478 static int hclge_set_led_id(struct hnae3_handle *handle,
12479                             enum ethtool_phys_id_state status)
12480 {
12481         struct hclge_vport *vport = hclge_get_vport(handle);
12482         struct hclge_dev *hdev = vport->back;
12483
12484         switch (status) {
12485         case ETHTOOL_ID_ACTIVE:
12486                 return hclge_set_led_status(hdev, HCLGE_LED_ON);
12487         case ETHTOOL_ID_INACTIVE:
12488                 return hclge_set_led_status(hdev, HCLGE_LED_OFF);
12489         default:
12490                 return -EINVAL;
12491         }
12492 }
12493
12494 static void hclge_get_link_mode(struct hnae3_handle *handle,
12495                                 unsigned long *supported,
12496                                 unsigned long *advertising)
12497 {
12498         unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS);
12499         struct hclge_vport *vport = hclge_get_vport(handle);
12500         struct hclge_dev *hdev = vport->back;
12501         unsigned int idx = 0;
12502
12503         for (; idx < size; idx++) {
12504                 supported[idx] = hdev->hw.mac.supported[idx];
12505                 advertising[idx] = hdev->hw.mac.advertising[idx];
12506         }
12507 }
12508
12509 static int hclge_gro_en(struct hnae3_handle *handle, bool enable)
12510 {
12511         struct hclge_vport *vport = hclge_get_vport(handle);
12512         struct hclge_dev *hdev = vport->back;
12513         bool gro_en_old = hdev->gro_en;
12514         int ret;
12515
12516         hdev->gro_en = enable;
12517         ret = hclge_config_gro(hdev);
12518         if (ret)
12519                 hdev->gro_en = gro_en_old;
12520
12521         return ret;
12522 }
12523
12524 static void hclge_sync_promisc_mode(struct hclge_dev *hdev)
12525 {
12526         struct hclge_vport *vport = &hdev->vport[0];
12527         struct hnae3_handle *handle = &vport->nic;
12528         u8 tmp_flags;
12529         int ret;
12530         u16 i;
12531
12532         if (vport->last_promisc_flags != vport->overflow_promisc_flags) {
12533                 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
12534                 vport->last_promisc_flags = vport->overflow_promisc_flags;
12535         }
12536
12537         if (test_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state)) {
12538                 tmp_flags = handle->netdev_flags | vport->last_promisc_flags;
12539                 ret = hclge_set_promisc_mode(handle, tmp_flags & HNAE3_UPE,
12540                                              tmp_flags & HNAE3_MPE);
12541                 if (!ret) {
12542                         clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE,
12543                                   &vport->state);
12544                         set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE,
12545                                 &vport->state);
12546                 }
12547         }
12548
12549         for (i = 1; i < hdev->num_alloc_vport; i++) {
12550                 bool uc_en = false;
12551                 bool mc_en = false;
12552                 bool bc_en;
12553
12554                 vport = &hdev->vport[i];
12555
12556                 if (!test_and_clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE,
12557                                         &vport->state))
12558                         continue;
12559
12560                 if (vport->vf_info.trusted) {
12561                         uc_en = vport->vf_info.request_uc_en > 0 ||
12562                                 vport->overflow_promisc_flags &
12563                                 HNAE3_OVERFLOW_UPE;
12564                         mc_en = vport->vf_info.request_mc_en > 0 ||
12565                                 vport->overflow_promisc_flags &
12566                                 HNAE3_OVERFLOW_MPE;
12567                 }
12568                 bc_en = vport->vf_info.request_bc_en > 0;
12569
12570                 ret = hclge_cmd_set_promisc_mode(hdev, vport->vport_id, uc_en,
12571                                                  mc_en, bc_en);
12572                 if (ret) {
12573                         set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE,
12574                                 &vport->state);
12575                         return;
12576                 }
12577                 hclge_set_vport_vlan_fltr_change(vport);
12578         }
12579 }
12580
12581 static bool hclge_module_existed(struct hclge_dev *hdev)
12582 {
12583         struct hclge_desc desc;
12584         u32 existed;
12585         int ret;
12586
12587         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_EXIST, true);
12588         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
12589         if (ret) {
12590                 dev_err(&hdev->pdev->dev,
12591                         "failed to get SFP exist state, ret = %d\n", ret);
12592                 return false;
12593         }
12594
12595         existed = le32_to_cpu(desc.data[0]);
12596
12597         return existed != 0;
12598 }
12599
12600 /* need 6 bds(total 140 bytes) in one reading
12601  * return the number of bytes actually read, 0 means read failed.
12602  */
12603 static u16 hclge_get_sfp_eeprom_info(struct hclge_dev *hdev, u32 offset,
12604                                      u32 len, u8 *data)
12605 {
12606         struct hclge_desc desc[HCLGE_SFP_INFO_CMD_NUM];
12607         struct hclge_sfp_info_bd0_cmd *sfp_info_bd0;
12608         u16 read_len;
12609         u16 copy_len;
12610         int ret;
12611         int i;
12612
12613         /* setup all 6 bds to read module eeprom info. */
12614         for (i = 0; i < HCLGE_SFP_INFO_CMD_NUM; i++) {
12615                 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_SFP_EEPROM,
12616                                            true);
12617
12618                 /* bd0~bd4 need next flag */
12619                 if (i < HCLGE_SFP_INFO_CMD_NUM - 1)
12620                         desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
12621         }
12622
12623         /* setup bd0, this bd contains offset and read length. */
12624         sfp_info_bd0 = (struct hclge_sfp_info_bd0_cmd *)desc[0].data;
12625         sfp_info_bd0->offset = cpu_to_le16((u16)offset);
12626         read_len = min_t(u16, len, HCLGE_SFP_INFO_MAX_LEN);
12627         sfp_info_bd0->read_len = cpu_to_le16(read_len);
12628
12629         ret = hclge_cmd_send(&hdev->hw, desc, i);
12630         if (ret) {
12631                 dev_err(&hdev->pdev->dev,
12632                         "failed to get SFP eeprom info, ret = %d\n", ret);
12633                 return 0;
12634         }
12635
12636         /* copy sfp info from bd0 to out buffer. */
12637         copy_len = min_t(u16, len, HCLGE_SFP_INFO_BD0_LEN);
12638         memcpy(data, sfp_info_bd0->data, copy_len);
12639         read_len = copy_len;
12640
12641         /* copy sfp info from bd1~bd5 to out buffer if needed. */
12642         for (i = 1; i < HCLGE_SFP_INFO_CMD_NUM; i++) {
12643                 if (read_len >= len)
12644                         return read_len;
12645
12646                 copy_len = min_t(u16, len - read_len, HCLGE_SFP_INFO_BDX_LEN);
12647                 memcpy(data + read_len, desc[i].data, copy_len);
12648                 read_len += copy_len;
12649         }
12650
12651         return read_len;
12652 }
12653
12654 static int hclge_get_module_eeprom(struct hnae3_handle *handle, u32 offset,
12655                                    u32 len, u8 *data)
12656 {
12657         struct hclge_vport *vport = hclge_get_vport(handle);
12658         struct hclge_dev *hdev = vport->back;
12659         u32 read_len = 0;
12660         u16 data_len;
12661
12662         if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER)
12663                 return -EOPNOTSUPP;
12664
12665         if (!hclge_module_existed(hdev))
12666                 return -ENXIO;
12667
12668         while (read_len < len) {
12669                 data_len = hclge_get_sfp_eeprom_info(hdev,
12670                                                      offset + read_len,
12671                                                      len - read_len,
12672                                                      data + read_len);
12673                 if (!data_len)
12674                         return -EIO;
12675
12676                 read_len += data_len;
12677         }
12678
12679         return 0;
12680 }
12681
12682 static int hclge_get_link_diagnosis_info(struct hnae3_handle *handle,
12683                                          u32 *status_code)
12684 {
12685         struct hclge_vport *vport = hclge_get_vport(handle);
12686         struct hclge_dev *hdev = vport->back;
12687         struct hclge_desc desc;
12688         int ret;
12689
12690         if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2)
12691                 return -EOPNOTSUPP;
12692
12693         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_DIAGNOSIS, true);
12694         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
12695         if (ret) {
12696                 dev_err(&hdev->pdev->dev,
12697                         "failed to query link diagnosis info, ret = %d\n", ret);
12698                 return ret;
12699         }
12700
12701         *status_code = le32_to_cpu(desc.data[0]);
12702         return 0;
12703 }
12704
12705 /* After disable sriov, VF still has some config and info need clean,
12706  * which configed by PF.
12707  */
12708 static void hclge_clear_vport_vf_info(struct hclge_vport *vport, int vfid)
12709 {
12710         struct hclge_dev *hdev = vport->back;
12711         struct hclge_vlan_info vlan_info;
12712         int ret;
12713
12714         /* after disable sriov, clean VF rate configured by PF */
12715         ret = hclge_tm_qs_shaper_cfg(vport, 0);
12716         if (ret)
12717                 dev_err(&hdev->pdev->dev,
12718                         "failed to clean vf%d rate config, ret = %d\n",
12719                         vfid, ret);
12720
12721         vlan_info.vlan_tag = 0;
12722         vlan_info.qos = 0;
12723         vlan_info.vlan_proto = ETH_P_8021Q;
12724         ret = hclge_update_port_base_vlan_cfg(vport,
12725                                               HNAE3_PORT_BASE_VLAN_DISABLE,
12726                                               &vlan_info);
12727         if (ret)
12728                 dev_err(&hdev->pdev->dev,
12729                         "failed to clean vf%d port base vlan, ret = %d\n",
12730                         vfid, ret);
12731
12732         ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, false);
12733         if (ret)
12734                 dev_err(&hdev->pdev->dev,
12735                         "failed to clean vf%d spoof config, ret = %d\n",
12736                         vfid, ret);
12737
12738         memset(&vport->vf_info, 0, sizeof(vport->vf_info));
12739 }
12740
12741 static void hclge_clean_vport_config(struct hnae3_ae_dev *ae_dev, int num_vfs)
12742 {
12743         struct hclge_dev *hdev = ae_dev->priv;
12744         struct hclge_vport *vport;
12745         int i;
12746
12747         for (i = 0; i < num_vfs; i++) {
12748                 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM];
12749
12750                 hclge_clear_vport_vf_info(vport, i);
12751         }
12752 }
12753
12754 static const struct hnae3_ae_ops hclge_ops = {
12755         .init_ae_dev = hclge_init_ae_dev,
12756         .uninit_ae_dev = hclge_uninit_ae_dev,
12757         .reset_prepare = hclge_reset_prepare_general,
12758         .reset_done = hclge_reset_done,
12759         .init_client_instance = hclge_init_client_instance,
12760         .uninit_client_instance = hclge_uninit_client_instance,
12761         .map_ring_to_vector = hclge_map_ring_to_vector,
12762         .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
12763         .get_vector = hclge_get_vector,
12764         .put_vector = hclge_put_vector,
12765         .set_promisc_mode = hclge_set_promisc_mode,
12766         .request_update_promisc_mode = hclge_request_update_promisc_mode,
12767         .set_loopback = hclge_set_loopback,
12768         .start = hclge_ae_start,
12769         .stop = hclge_ae_stop,
12770         .client_start = hclge_client_start,
12771         .client_stop = hclge_client_stop,
12772         .get_status = hclge_get_status,
12773         .get_ksettings_an_result = hclge_get_ksettings_an_result,
12774         .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
12775         .get_media_type = hclge_get_media_type,
12776         .check_port_speed = hclge_check_port_speed,
12777         .get_fec = hclge_get_fec,
12778         .set_fec = hclge_set_fec,
12779         .get_rss_key_size = hclge_comm_get_rss_key_size,
12780         .get_rss = hclge_get_rss,
12781         .set_rss = hclge_set_rss,
12782         .set_rss_tuple = hclge_set_rss_tuple,
12783         .get_rss_tuple = hclge_get_rss_tuple,
12784         .get_tc_size = hclge_get_tc_size,
12785         .get_mac_addr = hclge_get_mac_addr,
12786         .set_mac_addr = hclge_set_mac_addr,
12787         .do_ioctl = hclge_do_ioctl,
12788         .add_uc_addr = hclge_add_uc_addr,
12789         .rm_uc_addr = hclge_rm_uc_addr,
12790         .add_mc_addr = hclge_add_mc_addr,
12791         .rm_mc_addr = hclge_rm_mc_addr,
12792         .set_autoneg = hclge_set_autoneg,
12793         .get_autoneg = hclge_get_autoneg,
12794         .restart_autoneg = hclge_restart_autoneg,
12795         .halt_autoneg = hclge_halt_autoneg,
12796         .get_pauseparam = hclge_get_pauseparam,
12797         .set_pauseparam = hclge_set_pauseparam,
12798         .set_mtu = hclge_set_mtu,
12799         .reset_queue = hclge_reset_tqp,
12800         .get_stats = hclge_get_stats,
12801         .get_mac_stats = hclge_get_mac_stat,
12802         .update_stats = hclge_update_stats,
12803         .get_strings = hclge_get_strings,
12804         .get_sset_count = hclge_get_sset_count,
12805         .get_fw_version = hclge_get_fw_version,
12806         .get_mdix_mode = hclge_get_mdix_mode,
12807         .enable_vlan_filter = hclge_enable_vlan_filter,
12808         .set_vlan_filter = hclge_set_vlan_filter,
12809         .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
12810         .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
12811         .reset_event = hclge_reset_event,
12812         .get_reset_level = hclge_get_reset_level,
12813         .set_default_reset_request = hclge_set_def_reset_request,
12814         .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
12815         .set_channels = hclge_set_channels,
12816         .get_channels = hclge_get_channels,
12817         .get_regs_len = hclge_get_regs_len,
12818         .get_regs = hclge_get_regs,
12819         .set_led_id = hclge_set_led_id,
12820         .get_link_mode = hclge_get_link_mode,
12821         .add_fd_entry = hclge_add_fd_entry,
12822         .del_fd_entry = hclge_del_fd_entry,
12823         .get_fd_rule_cnt = hclge_get_fd_rule_cnt,
12824         .get_fd_rule_info = hclge_get_fd_rule_info,
12825         .get_fd_all_rules = hclge_get_all_rules,
12826         .enable_fd = hclge_enable_fd,
12827         .add_arfs_entry = hclge_add_fd_entry_by_arfs,
12828         .dbg_read_cmd = hclge_dbg_read_cmd,
12829         .handle_hw_ras_error = hclge_handle_hw_ras_error,
12830         .get_hw_reset_stat = hclge_get_hw_reset_stat,
12831         .ae_dev_resetting = hclge_ae_dev_resetting,
12832         .ae_dev_reset_cnt = hclge_ae_dev_reset_cnt,
12833         .set_gro_en = hclge_gro_en,
12834         .get_global_queue_id = hclge_covert_handle_qid_global,
12835         .set_timer_task = hclge_set_timer_task,
12836         .mac_connect_phy = hclge_mac_connect_phy,
12837         .mac_disconnect_phy = hclge_mac_disconnect_phy,
12838         .get_vf_config = hclge_get_vf_config,
12839         .set_vf_link_state = hclge_set_vf_link_state,
12840         .set_vf_spoofchk = hclge_set_vf_spoofchk,
12841         .set_vf_trust = hclge_set_vf_trust,
12842         .set_vf_rate = hclge_set_vf_rate,
12843         .set_vf_mac = hclge_set_vf_mac,
12844         .get_module_eeprom = hclge_get_module_eeprom,
12845         .get_cmdq_stat = hclge_get_cmdq_stat,
12846         .add_cls_flower = hclge_add_cls_flower,
12847         .del_cls_flower = hclge_del_cls_flower,
12848         .cls_flower_active = hclge_is_cls_flower_active,
12849         .get_phy_link_ksettings = hclge_get_phy_link_ksettings,
12850         .set_phy_link_ksettings = hclge_set_phy_link_ksettings,
12851         .set_tx_hwts_info = hclge_ptp_set_tx_info,
12852         .get_rx_hwts = hclge_ptp_get_rx_hwts,
12853         .get_ts_info = hclge_ptp_get_ts_info,
12854         .get_link_diagnosis_info = hclge_get_link_diagnosis_info,
12855         .clean_vf_config = hclge_clean_vport_config,
12856 };
12857
12858 static struct hnae3_ae_algo ae_algo = {
12859         .ops = &hclge_ops,
12860         .pdev_id_table = ae_algo_pci_tbl,
12861 };
12862
12863 static int hclge_init(void)
12864 {
12865         pr_info("%s is initializing\n", HCLGE_NAME);
12866
12867         hclge_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGE_NAME);
12868         if (!hclge_wq) {
12869                 pr_err("%s: failed to create workqueue\n", HCLGE_NAME);
12870                 return -ENOMEM;
12871         }
12872
12873         hnae3_register_ae_algo(&ae_algo);
12874
12875         return 0;
12876 }
12877
12878 static void hclge_exit(void)
12879 {
12880         hnae3_unregister_ae_algo_prepare(&ae_algo);
12881         hnae3_unregister_ae_algo(&ae_algo);
12882         destroy_workqueue(hclge_wq);
12883 }
12884 module_init(hclge_init);
12885 module_exit(hclge_exit);
12886
12887 MODULE_LICENSE("GPL");
12888 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
12889 MODULE_DESCRIPTION("HCLGE Driver");
12890 MODULE_VERSION(HCLGE_MOD_VERSION);