drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4 #include <linux/acpi.h>
   5 #include <linux/device.h>
   6 #include <linux/etherdevice.h>
   7 #include <linux/init.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/netdevice.h>
  12 #include <linux/pci.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/if_vlan.h>
  15 #include <net/rtnetlink.h>
  16 #include "hclge_cmd.h"
  17 #include "hclge_dcb.h"
  18 #include "hclge_main.h"
  19 #include "hclge_mbx.h"
  20 #include "hclge_mdio.h"
  21 #include "hclge_tm.h"
  22 #include "hclge_err.h"
  23 #include "hnae3.h"
  24
  25 #define HCLGE_NAME                      "hclge"
  26 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
  27 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
  28
  29 #define HCLGE_BUF_SIZE_UNIT     256
  30
  31 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps);
  32 static int hclge_init_vlan_config(struct hclge_dev *hdev);
  33 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
  34 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size,
  35                                u16 *allocated_size, bool is_alloc);
  36
  37 static struct hnae3_ae_algo ae_algo;
  38
  39 static const struct pci_device_id ae_algo_pci_tbl[] = {
  40         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
  41         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
  42         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
  43         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
  44         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
  45         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
  46         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
  47         /* required last entry */
  48         {0, }
  49 };
  50
  51 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
  52
  53 static const u32 cmdq_reg_addr_list[] = {HCLGE_CMDQ_TX_ADDR_L_REG,
  54                                          HCLGE_CMDQ_TX_ADDR_H_REG,
  55                                          HCLGE_CMDQ_TX_DEPTH_REG,
  56                                          HCLGE_CMDQ_TX_TAIL_REG,
  57                                          HCLGE_CMDQ_TX_HEAD_REG,
  58                                          HCLGE_CMDQ_RX_ADDR_L_REG,
  59                                          HCLGE_CMDQ_RX_ADDR_H_REG,
  60                                          HCLGE_CMDQ_RX_DEPTH_REG,
  61                                          HCLGE_CMDQ_RX_TAIL_REG,
  62                                          HCLGE_CMDQ_RX_HEAD_REG,
  63                                          HCLGE_VECTOR0_CMDQ_SRC_REG,
  64                                          HCLGE_CMDQ_INTR_STS_REG,
  65                                          HCLGE_CMDQ_INTR_EN_REG,
  66                                          HCLGE_CMDQ_INTR_GEN_REG};
  67
  68 static const u32 common_reg_addr_list[] = {HCLGE_MISC_VECTOR_REG_BASE,
  69                                            HCLGE_VECTOR0_OTER_EN_REG,
  70                                            HCLGE_MISC_RESET_STS_REG,
  71                                            HCLGE_MISC_VECTOR_INT_STS,
  72                                            HCLGE_GLOBAL_RESET_REG,
  73                                            HCLGE_FUN_RST_ING,
  74                                            HCLGE_GRO_EN_REG};
  75
  76 static const u32 ring_reg_addr_list[] = {HCLGE_RING_RX_ADDR_L_REG,
  77                                          HCLGE_RING_RX_ADDR_H_REG,
  78                                          HCLGE_RING_RX_BD_NUM_REG,
  79                                          HCLGE_RING_RX_BD_LENGTH_REG,
  80                                          HCLGE_RING_RX_MERGE_EN_REG,
  81                                          HCLGE_RING_RX_TAIL_REG,
  82                                          HCLGE_RING_RX_HEAD_REG,
  83                                          HCLGE_RING_RX_FBD_NUM_REG,
  84                                          HCLGE_RING_RX_OFFSET_REG,
  85                                          HCLGE_RING_RX_FBD_OFFSET_REG,
  86                                          HCLGE_RING_RX_STASH_REG,
  87                                          HCLGE_RING_RX_BD_ERR_REG,
  88                                          HCLGE_RING_TX_ADDR_L_REG,
  89                                          HCLGE_RING_TX_ADDR_H_REG,
  90                                          HCLGE_RING_TX_BD_NUM_REG,
  91                                          HCLGE_RING_TX_PRIORITY_REG,
  92                                          HCLGE_RING_TX_TC_REG,
  93                                          HCLGE_RING_TX_MERGE_EN_REG,
  94                                          HCLGE_RING_TX_TAIL_REG,
  95                                          HCLGE_RING_TX_HEAD_REG,
  96                                          HCLGE_RING_TX_FBD_NUM_REG,
  97                                          HCLGE_RING_TX_OFFSET_REG,
  98                                          HCLGE_RING_TX_EBD_NUM_REG,
  99                                          HCLGE_RING_TX_EBD_OFFSET_REG,
 100                                          HCLGE_RING_TX_BD_ERR_REG,
 101                                          HCLGE_RING_EN_REG};
 102
 103 static const u32 tqp_intr_reg_addr_list[] = {HCLGE_TQP_INTR_CTRL_REG,
 104                                              HCLGE_TQP_INTR_GL0_REG,
 105                                              HCLGE_TQP_INTR_GL1_REG,
 106                                              HCLGE_TQP_INTR_GL2_REG,
 107                                              HCLGE_TQP_INTR_RL_REG};
 108
 109 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
 110         "App    Loopback test",
 111         "Serdes serial Loopback test",
 112         "Serdes parallel Loopback test",
 113         "Phy    Loopback test"
 114 };
 115
 116 static const struct hclge_comm_stats_str g_mac_stats_string[] = {
 117         {"mac_tx_mac_pause_num",
 118                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
 119         {"mac_rx_mac_pause_num",
 120                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
 121         {"mac_tx_pfc_pri0_pkt_num",
 122                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
 123         {"mac_tx_pfc_pri1_pkt_num",
 124                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
 125         {"mac_tx_pfc_pri2_pkt_num",
 126                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
 127         {"mac_tx_pfc_pri3_pkt_num",
 128                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
 129         {"mac_tx_pfc_pri4_pkt_num",
 130                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
 131         {"mac_tx_pfc_pri5_pkt_num",
 132                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
 133         {"mac_tx_pfc_pri6_pkt_num",
 134                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
 135         {"mac_tx_pfc_pri7_pkt_num",
 136                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
 137         {"mac_rx_pfc_pri0_pkt_num",
 138                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
 139         {"mac_rx_pfc_pri1_pkt_num",
 140                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
 141         {"mac_rx_pfc_pri2_pkt_num",
 142                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
 143         {"mac_rx_pfc_pri3_pkt_num",
 144                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
 145         {"mac_rx_pfc_pri4_pkt_num",
 146                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
 147         {"mac_rx_pfc_pri5_pkt_num",
 148                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
 149         {"mac_rx_pfc_pri6_pkt_num",
 150                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
 151         {"mac_rx_pfc_pri7_pkt_num",
 152                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
 153         {"mac_tx_total_pkt_num",
 154                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
 155         {"mac_tx_total_oct_num",
 156                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
 157         {"mac_tx_good_pkt_num",
 158                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
 159         {"mac_tx_bad_pkt_num",
 160                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
 161         {"mac_tx_good_oct_num",
 162                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
 163         {"mac_tx_bad_oct_num",
 164                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
 165         {"mac_tx_uni_pkt_num",
 166                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
 167         {"mac_tx_multi_pkt_num",
 168                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
 169         {"mac_tx_broad_pkt_num",
 170                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
 171         {"mac_tx_undersize_pkt_num",
 172                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
 173         {"mac_tx_oversize_pkt_num",
 174                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
 175         {"mac_tx_64_oct_pkt_num",
 176                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
 177         {"mac_tx_65_127_oct_pkt_num",
 178                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
 179         {"mac_tx_128_255_oct_pkt_num",
 180                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
 181         {"mac_tx_256_511_oct_pkt_num",
 182                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
 183         {"mac_tx_512_1023_oct_pkt_num",
 184                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
 185         {"mac_tx_1024_1518_oct_pkt_num",
 186                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
 187         {"mac_tx_1519_2047_oct_pkt_num",
 188                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
 189         {"mac_tx_2048_4095_oct_pkt_num",
 190                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
 191         {"mac_tx_4096_8191_oct_pkt_num",
 192                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
 193         {"mac_tx_8192_9216_oct_pkt_num",
 194                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
 195         {"mac_tx_9217_12287_oct_pkt_num",
 196                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
 197         {"mac_tx_12288_16383_oct_pkt_num",
 198                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
 199         {"mac_tx_1519_max_good_pkt_num",
 200                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
 201         {"mac_tx_1519_max_bad_pkt_num",
 202                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
 203         {"mac_rx_total_pkt_num",
 204                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
 205         {"mac_rx_total_oct_num",
 206                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
 207         {"mac_rx_good_pkt_num",
 208                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
 209         {"mac_rx_bad_pkt_num",
 210                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
 211         {"mac_rx_good_oct_num",
 212                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
 213         {"mac_rx_bad_oct_num",
 214                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
 215         {"mac_rx_uni_pkt_num",
 216                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
 217         {"mac_rx_multi_pkt_num",
 218                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
 219         {"mac_rx_broad_pkt_num",
 220                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
 221         {"mac_rx_undersize_pkt_num",
 222                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
 223         {"mac_rx_oversize_pkt_num",
 224                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
 225         {"mac_rx_64_oct_pkt_num",
 226                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
 227         {"mac_rx_65_127_oct_pkt_num",
 228                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
 229         {"mac_rx_128_255_oct_pkt_num",
 230                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
 231         {"mac_rx_256_511_oct_pkt_num",
 232                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
 233         {"mac_rx_512_1023_oct_pkt_num",
 234                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
 235         {"mac_rx_1024_1518_oct_pkt_num",
 236                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
 237         {"mac_rx_1519_2047_oct_pkt_num",
 238                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
 239         {"mac_rx_2048_4095_oct_pkt_num",
 240                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
 241         {"mac_rx_4096_8191_oct_pkt_num",
 242                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
 243         {"mac_rx_8192_9216_oct_pkt_num",
 244                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
 245         {"mac_rx_9217_12287_oct_pkt_num",
 246                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
 247         {"mac_rx_12288_16383_oct_pkt_num",
 248                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
 249         {"mac_rx_1519_max_good_pkt_num",
 250                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
 251         {"mac_rx_1519_max_bad_pkt_num",
 252                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
 253
 254         {"mac_tx_fragment_pkt_num",
 255                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
 256         {"mac_tx_undermin_pkt_num",
 257                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
 258         {"mac_tx_jabber_pkt_num",
 259                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
 260         {"mac_tx_err_all_pkt_num",
 261                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
 262         {"mac_tx_from_app_good_pkt_num",
 263                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
 264         {"mac_tx_from_app_bad_pkt_num",
 265                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
 266         {"mac_rx_fragment_pkt_num",
 267                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
 268         {"mac_rx_undermin_pkt_num",
 269                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
 270         {"mac_rx_jabber_pkt_num",
 271                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
 272         {"mac_rx_fcs_err_pkt_num",
 273                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
 274         {"mac_rx_send_app_good_pkt_num",
 275                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
 276         {"mac_rx_send_app_bad_pkt_num",
 277                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
 278 };
 279
 280 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
 281         {
 282                 .flags = HCLGE_MAC_MGR_MASK_VLAN_B,
 283                 .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP),
 284                 .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)),
 285                 .mac_addr_lo16 = cpu_to_le16(htons(0x000E)),
 286                 .i_port_bitmap = 0x1,
 287         },
 288 };
 289
 290 static int hclge_mac_update_stats(struct hclge_dev *hdev)
 291 {
 292 #define HCLGE_MAC_CMD_NUM 21
 293 #define HCLGE_RTN_DATA_NUM 4
 294
 295         u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
 296         struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
 297         __le64 *desc_data;
 298         int i, k, n;
 299         int ret;
 300
 301         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
 302         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
 303         if (ret) {
 304                 dev_err(&hdev->pdev->dev,
 305                         "Get MAC pkt stats fail, status = %d.\n", ret);
 306
 307                 return ret;
 308         }
 309
 310         for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
 311                 if (unlikely(i == 0)) {
 312                         desc_data = (__le64 *)(&desc[i].data[0]);
 313                         n = HCLGE_RTN_DATA_NUM - 2;
 314                 } else {
 315                         desc_data = (__le64 *)(&desc[i]);
 316                         n = HCLGE_RTN_DATA_NUM;
 317                 }
 318                 for (k = 0; k < n; k++) {
 319                         *data++ += le64_to_cpu(*desc_data);
 320                         desc_data++;
 321                 }
 322         }
 323
 324         return 0;
 325 }
 326
 327 static int hclge_tqps_update_stats(struct hnae3_handle *handle)
 328 {
 329         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 330         struct hclge_vport *vport = hclge_get_vport(handle);
 331         struct hclge_dev *hdev = vport->back;
 332         struct hnae3_queue *queue;
 333         struct hclge_desc desc[1];
 334         struct hclge_tqp *tqp;
 335         int ret, i;
 336
 337         for (i = 0; i < kinfo->num_tqps; i++) {
 338                 queue = handle->kinfo.tqp[i];
 339                 tqp = container_of(queue, struct hclge_tqp, q);
 340                 /* command : HCLGE_OPC_QUERY_IGU_STAT */
 341                 hclge_cmd_setup_basic_desc(&desc[0],
 342                                            HCLGE_OPC_QUERY_RX_STATUS,
 343                                            true);
 344
 345                 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
 346                 ret = hclge_cmd_send(&hdev->hw, desc, 1);
 347                 if (ret) {
 348                         dev_err(&hdev->pdev->dev,
 349                                 "Query tqp stat fail, status = %d,queue = %d\n",
 350                                 ret,    i);
 351                         return ret;
 352                 }
 353                 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
 354                         le32_to_cpu(desc[0].data[1]);
 355         }
 356
 357         for (i = 0; i < kinfo->num_tqps; i++) {
 358                 queue = handle->kinfo.tqp[i];
 359                 tqp = container_of(queue, struct hclge_tqp, q);
 360                 /* command : HCLGE_OPC_QUERY_IGU_STAT */
 361                 hclge_cmd_setup_basic_desc(&desc[0],
 362                                            HCLGE_OPC_QUERY_TX_STATUS,
 363                                            true);
 364
 365                 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
 366                 ret = hclge_cmd_send(&hdev->hw, desc, 1);
 367                 if (ret) {
 368                         dev_err(&hdev->pdev->dev,
 369                                 "Query tqp stat fail, status = %d,queue = %d\n",
 370                                 ret, i);
 371                         return ret;
 372                 }
 373                 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
 374                         le32_to_cpu(desc[0].data[1]);
 375         }
 376
 377         return 0;
 378 }
 379
 380 static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
 381 {
 382         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 383         struct hclge_tqp *tqp;
 384         u64 *buff = data;
 385         int i;
 386
 387         for (i = 0; i < kinfo->num_tqps; i++) {
 388                 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
 389                 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
 390         }
 391
 392         for (i = 0; i < kinfo->num_tqps; i++) {
 393                 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
 394                 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
 395         }
 396
 397         return buff;
 398 }
 399
 400 static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
 401 {
 402         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 403
 404         return kinfo->num_tqps * (2);
 405 }
 406
 407 static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
 408 {
 409         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 410         u8 *buff = data;
 411         int i = 0;
 412
 413         for (i = 0; i < kinfo->num_tqps; i++) {
 414                 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
 415                         struct hclge_tqp, q);
 416                 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd",
 417                          tqp->index);
 418                 buff = buff + ETH_GSTRING_LEN;
 419         }
 420
 421         for (i = 0; i < kinfo->num_tqps; i++) {
 422                 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
 423                         struct hclge_tqp, q);
 424                 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd",
 425                          tqp->index);
 426                 buff = buff + ETH_GSTRING_LEN;
 427         }
 428
 429         return buff;
 430 }
 431
 432 static u64 *hclge_comm_get_stats(void *comm_stats,
 433                                  const struct hclge_comm_stats_str strs[],
 434                                  int size, u64 *data)
 435 {
 436         u64 *buf = data;
 437         u32 i;
 438
 439         for (i = 0; i < size; i++)
 440                 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
 441
 442         return buf + size;
 443 }
 444
 445 static u8 *hclge_comm_get_strings(u32 stringset,
 446                                   const struct hclge_comm_stats_str strs[],
 447                                   int size, u8 *data)
 448 {
 449         char *buff = (char *)data;
 450         u32 i;
 451
 452         if (stringset != ETH_SS_STATS)
 453                 return buff;
 454
 455         for (i = 0; i < size; i++) {
 456                 snprintf(buff, ETH_GSTRING_LEN,
 457                          strs[i].desc);
 458                 buff = buff + ETH_GSTRING_LEN;
 459         }
 460
 461         return (u8 *)buff;
 462 }
 463
 464 static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
 465                                  struct net_device_stats *net_stats)
 466 {
 467         net_stats->tx_dropped = 0;
 468         net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num;
 469         net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
 470         net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
 471
 472         net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
 473         net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
 474
 475         net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
 476         net_stats->rx_length_errors =
 477                 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
 478         net_stats->rx_length_errors +=
 479                 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
 480         net_stats->rx_over_errors =
 481                 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
 482 }
 483
 484 static void hclge_update_stats_for_all(struct hclge_dev *hdev)
 485 {
 486         struct hnae3_handle *handle;
 487         int status;
 488
 489         handle = &hdev->vport[0].nic;
 490         if (handle->client) {
 491                 status = hclge_tqps_update_stats(handle);
 492                 if (status) {
 493                         dev_err(&hdev->pdev->dev,
 494                                 "Update TQPS stats fail, status = %d.\n",
 495                                 status);
 496                 }
 497         }
 498
 499         status = hclge_mac_update_stats(hdev);
 500         if (status)
 501                 dev_err(&hdev->pdev->dev,
 502                         "Update MAC stats fail, status = %d.\n", status);
 503
 504         hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
 505 }
 506
 507 static void hclge_update_stats(struct hnae3_handle *handle,
 508                                struct net_device_stats *net_stats)
 509 {
 510         struct hclge_vport *vport = hclge_get_vport(handle);
 511         struct hclge_dev *hdev = vport->back;
 512         struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
 513         int status;
 514
 515         if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
 516                 return;
 517
 518         status = hclge_mac_update_stats(hdev);
 519         if (status)
 520                 dev_err(&hdev->pdev->dev,
 521                         "Update MAC stats fail, status = %d.\n",
 522                         status);
 523
 524         status = hclge_tqps_update_stats(handle);
 525         if (status)
 526                 dev_err(&hdev->pdev->dev,
 527                         "Update TQPS stats fail, status = %d.\n",
 528                         status);
 529
 530         hclge_update_netstat(hw_stats, net_stats);
 531
 532         clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
 533 }
 534
 535 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
 536 {
 537 #define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK |\
 538                 HNAE3_SUPPORT_PHY_LOOPBACK |\
 539                 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK |\
 540                 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK)
 541
 542         struct hclge_vport *vport = hclge_get_vport(handle);
 543         struct hclge_dev *hdev = vport->back;
 544         int count = 0;
 545
 546         /* Loopback test support rules:
 547          * mac: only GE mode support
 548          * serdes: all mac mode will support include GE/XGE/LGE/CGE
 549          * phy: only support when phy device exist on board
 550          */
 551         if (stringset == ETH_SS_TEST) {
 552                 /* clear loopback bit flags at first */
 553                 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
 554                 if (hdev->pdev->revision >= 0x21 ||
 555                     hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
 556                     hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
 557                     hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
 558                         count += 1;
 559                         handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK;
 560                 }
 561
 562                 count += 2;
 563                 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK;
 564                 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK;
 565         } else if (stringset == ETH_SS_STATS) {
 566                 count = ARRAY_SIZE(g_mac_stats_string) +
 567                         hclge_tqps_get_sset_count(handle, stringset);
 568         }
 569
 570         return count;
 571 }
 572
 573 static void hclge_get_strings(struct hnae3_handle *handle,
 574                               u32 stringset,
 575                               u8 *data)
 576 {
 577         u8 *p = (char *)data;
 578         int size;
 579
 580         if (stringset == ETH_SS_STATS) {
 581                 size = ARRAY_SIZE(g_mac_stats_string);
 582                 p = hclge_comm_get_strings(stringset,
 583                                            g_mac_stats_string,
 584                                            size,
 585                                            p);
 586                 p = hclge_tqps_get_strings(handle, p);
 587         } else if (stringset == ETH_SS_TEST) {
 588                 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) {
 589                         memcpy(p,
 590                                hns3_nic_test_strs[HNAE3_LOOP_APP],
 591                                ETH_GSTRING_LEN);
 592                         p += ETH_GSTRING_LEN;
 593                 }
 594                 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) {
 595                         memcpy(p,
 596                                hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES],
 597                                ETH_GSTRING_LEN);
 598                         p += ETH_GSTRING_LEN;
 599                 }
 600                 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) {
 601                         memcpy(p,
 602                                hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES],
 603                                ETH_GSTRING_LEN);
 604                         p += ETH_GSTRING_LEN;
 605                 }
 606                 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
 607                         memcpy(p,
 608                                hns3_nic_test_strs[HNAE3_LOOP_PHY],
 609                                ETH_GSTRING_LEN);
 610                         p += ETH_GSTRING_LEN;
 611                 }
 612         }
 613 }
 614
 615 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
 616 {
 617         struct hclge_vport *vport = hclge_get_vport(handle);
 618         struct hclge_dev *hdev = vport->back;
 619         u64 *p;
 620
 621         p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
 622                                  g_mac_stats_string,
 623                                  ARRAY_SIZE(g_mac_stats_string),
 624                                  data);
 625         p = hclge_tqps_get_stats(handle, p);
 626 }
 627
 628 static int hclge_parse_func_status(struct hclge_dev *hdev,
 629                                    struct hclge_func_status_cmd *status)
 630 {
 631         if (!(status->pf_state & HCLGE_PF_STATE_DONE))
 632                 return -EINVAL;
 633
 634         /* Set the pf to main pf */
 635         if (status->pf_state & HCLGE_PF_STATE_MAIN)
 636                 hdev->flag |= HCLGE_FLAG_MAIN;
 637         else
 638                 hdev->flag &= ~HCLGE_FLAG_MAIN;
 639
 640         return 0;
 641 }
 642
 643 static int hclge_query_function_status(struct hclge_dev *hdev)
 644 {
 645         struct hclge_func_status_cmd *req;
 646         struct hclge_desc desc;
 647         int timeout = 0;
 648         int ret;
 649
 650         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
 651         req = (struct hclge_func_status_cmd *)desc.data;
 652
 653         do {
 654                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 655                 if (ret) {
 656                         dev_err(&hdev->pdev->dev,
 657                                 "query function status failed %d.\n",
 658                                 ret);
 659
 660                         return ret;
 661                 }
 662
 663                 /* Check pf reset is done */
 664                 if (req->pf_state)
 665                         break;
 666                 usleep_range(1000, 2000);
 667         } while (timeout++ < 5);
 668
 669         ret = hclge_parse_func_status(hdev, req);
 670
 671         return ret;
 672 }
 673
 674 static int hclge_query_pf_resource(struct hclge_dev *hdev)
 675 {
 676         struct hclge_pf_res_cmd *req;
 677         struct hclge_desc desc;
 678         int ret;
 679
 680         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
 681         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 682         if (ret) {
 683                 dev_err(&hdev->pdev->dev,
 684                         "query pf resource failed %d.\n", ret);
 685                 return ret;
 686         }
 687
 688         req = (struct hclge_pf_res_cmd *)desc.data;
 689         hdev->num_tqps = __le16_to_cpu(req->tqp_num);
 690         hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
 691
 692         if (req->tx_buf_size)
 693                 hdev->tx_buf_size =
 694                         __le16_to_cpu(req->tx_buf_size) << HCLGE_BUF_UNIT_S;
 695         else
 696                 hdev->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
 697
 698         hdev->tx_buf_size = roundup(hdev->tx_buf_size, HCLGE_BUF_SIZE_UNIT);
 699
 700         if (req->dv_buf_size)
 701                 hdev->dv_buf_size =
 702                         __le16_to_cpu(req->dv_buf_size) << HCLGE_BUF_UNIT_S;
 703         else
 704                 hdev->dv_buf_size = HCLGE_DEFAULT_DV;
 705
 706         hdev->dv_buf_size = roundup(hdev->dv_buf_size, HCLGE_BUF_SIZE_UNIT);
 707
 708         if (hnae3_dev_roce_supported(hdev)) {
 709                 hdev->roce_base_msix_offset =
 710                 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee),
 711                                 HCLGE_MSIX_OFT_ROCEE_M, HCLGE_MSIX_OFT_ROCEE_S);
 712                 hdev->num_roce_msi =
 713                 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
 714                                 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
 715
 716                 /* PF should have NIC vectors and Roce vectors,
 717                  * NIC vectors are queued before Roce vectors.
 718                  */
 719                 hdev->num_msi = hdev->num_roce_msi  +
 720                                 hdev->roce_base_msix_offset;
 721         } else {
 722                 hdev->num_msi =
 723                 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
 724                                 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
 725         }
 726
 727         return 0;
 728 }
 729
 730 static int hclge_parse_speed(int speed_cmd, int *speed)
 731 {
 732         switch (speed_cmd) {
 733         case 6:
 734                 *speed = HCLGE_MAC_SPEED_10M;
 735                 break;
 736         case 7:
 737                 *speed = HCLGE_MAC_SPEED_100M;
 738                 break;
 739         case 0:
 740                 *speed = HCLGE_MAC_SPEED_1G;
 741                 break;
 742         case 1:
 743                 *speed = HCLGE_MAC_SPEED_10G;
 744                 break;
 745         case 2:
 746                 *speed = HCLGE_MAC_SPEED_25G;
 747                 break;
 748         case 3:
 749                 *speed = HCLGE_MAC_SPEED_40G;
 750                 break;
 751         case 4:
 752                 *speed = HCLGE_MAC_SPEED_50G;
 753                 break;
 754         case 5:
 755                 *speed = HCLGE_MAC_SPEED_100G;
 756                 break;
 757         default:
 758                 return -EINVAL;
 759         }
 760
 761         return 0;
 762 }
 763
 764 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
 765                                         u8 speed_ability)
 766 {
 767         unsigned long *supported = hdev->hw.mac.supported;
 768
 769         if (speed_ability & HCLGE_SUPPORT_1G_BIT)
 770                 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
 771                         supported);
 772
 773         if (speed_ability & HCLGE_SUPPORT_10G_BIT)
 774                 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
 775                         supported);
 776
 777         if (speed_ability & HCLGE_SUPPORT_25G_BIT)
 778                 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
 779                         supported);
 780
 781         if (speed_ability & HCLGE_SUPPORT_50G_BIT)
 782                 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
 783                         supported);
 784
 785         if (speed_ability & HCLGE_SUPPORT_100G_BIT)
 786                 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
 787                         supported);
 788
 789         set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
 790         set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
 791 }
 792
 793 static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability)
 794 {
 795         u8 media_type = hdev->hw.mac.media_type;
 796
 797         if (media_type != HNAE3_MEDIA_TYPE_FIBER)
 798                 return;
 799
 800         hclge_parse_fiber_link_mode(hdev, speed_ability);
 801 }
 802
 803 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
 804 {
 805         struct hclge_cfg_param_cmd *req;
 806         u64 mac_addr_tmp_high;
 807         u64 mac_addr_tmp;
 808         int i;
 809
 810         req = (struct hclge_cfg_param_cmd *)desc[0].data;
 811
 812         /* get the configuration */
 813         cfg->vmdq_vport_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
 814                                               HCLGE_CFG_VMDQ_M,
 815                                               HCLGE_CFG_VMDQ_S);
 816         cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
 817                                       HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
 818         cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
 819                                             HCLGE_CFG_TQP_DESC_N_M,
 820                                             HCLGE_CFG_TQP_DESC_N_S);
 821
 822         cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]),
 823                                         HCLGE_CFG_PHY_ADDR_M,
 824                                         HCLGE_CFG_PHY_ADDR_S);
 825         cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]),
 826                                           HCLGE_CFG_MEDIA_TP_M,
 827                                           HCLGE_CFG_MEDIA_TP_S);
 828         cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]),
 829                                           HCLGE_CFG_RX_BUF_LEN_M,
 830                                           HCLGE_CFG_RX_BUF_LEN_S);
 831         /* get mac_address */
 832         mac_addr_tmp = __le32_to_cpu(req->param[2]);
 833         mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]),
 834                                             HCLGE_CFG_MAC_ADDR_H_M,
 835                                             HCLGE_CFG_MAC_ADDR_H_S);
 836
 837         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
 838
 839         cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]),
 840                                              HCLGE_CFG_DEFAULT_SPEED_M,
 841                                              HCLGE_CFG_DEFAULT_SPEED_S);
 842         cfg->rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]),
 843                                             HCLGE_CFG_RSS_SIZE_M,
 844                                             HCLGE_CFG_RSS_SIZE_S);
 845
 846         for (i = 0; i < ETH_ALEN; i++)
 847                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
 848
 849         req = (struct hclge_cfg_param_cmd *)desc[1].data;
 850         cfg->numa_node_map = __le32_to_cpu(req->param[0]);
 851
 852         cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]),
 853                                              HCLGE_CFG_SPEED_ABILITY_M,
 854                                              HCLGE_CFG_SPEED_ABILITY_S);
 855         cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]),
 856                                          HCLGE_CFG_UMV_TBL_SPACE_M,
 857                                          HCLGE_CFG_UMV_TBL_SPACE_S);
 858         if (!cfg->umv_space)
 859                 cfg->umv_space = HCLGE_DEFAULT_UMV_SPACE_PER_PF;
 860 }
 861
 862 /* hclge_get_cfg: query the static parameter from flash
 863  * @hdev: pointer to struct hclge_dev
 864  * @hcfg: the config structure to be getted
 865  */
 866 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
 867 {
 868         struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
 869         struct hclge_cfg_param_cmd *req;
 870         int i, ret;
 871
 872         for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
 873                 u32 offset = 0;
 874
 875                 req = (struct hclge_cfg_param_cmd *)desc[i].data;
 876                 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
 877                                            true);
 878                 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M,
 879                                 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
 880                 /* Len should be united by 4 bytes when send to hardware */
 881                 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
 882                                 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
 883                 req->offset = cpu_to_le32(offset);
 884         }
 885
 886         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
 887         if (ret) {
 888                 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret);
 889                 return ret;
 890         }
 891
 892         hclge_parse_cfg(hcfg, desc);
 893
 894         return 0;
 895 }
 896
 897 static int hclge_get_cap(struct hclge_dev *hdev)
 898 {
 899         int ret;
 900
 901         ret = hclge_query_function_status(hdev);
 902         if (ret) {
 903                 dev_err(&hdev->pdev->dev,
 904                         "query function status error %d.\n", ret);
 905                 return ret;
 906         }
 907
 908         /* get pf resource */
 909         ret = hclge_query_pf_resource(hdev);
 910         if (ret)
 911                 dev_err(&hdev->pdev->dev, "query pf resource error %d.\n", ret);
 912
 913         return ret;
 914 }
 915
 916 static int hclge_configure(struct hclge_dev *hdev)
 917 {
 918         struct hclge_cfg cfg;
 919         int ret, i;
 920
 921         ret = hclge_get_cfg(hdev, &cfg);
 922         if (ret) {
 923                 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
 924                 return ret;
 925         }
 926
 927         hdev->num_vmdq_vport = cfg.vmdq_vport_num;
 928         hdev->base_tqp_pid = 0;
 929         hdev->rss_size_max = cfg.rss_size_max;
 930         hdev->rx_buf_len = cfg.rx_buf_len;
 931         ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
 932         hdev->hw.mac.media_type = cfg.media_type;
 933         hdev->hw.mac.phy_addr = cfg.phy_addr;
 934         hdev->num_desc = cfg.tqp_desc_num;
 935         hdev->tm_info.num_pg = 1;
 936         hdev->tc_max = cfg.tc_num;
 937         hdev->tm_info.hw_pfc_map = 0;
 938         hdev->wanted_umv_size = cfg.umv_space;
 939
 940         ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
 941         if (ret) {
 942                 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
 943                 return ret;
 944         }
 945
 946         hclge_parse_link_mode(hdev, cfg.speed_ability);
 947
 948         if ((hdev->tc_max > HNAE3_MAX_TC) ||
 949             (hdev->tc_max < 1)) {
 950                 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
 951                          hdev->tc_max);
 952                 hdev->tc_max = 1;
 953         }
 954
 955         /* Dev does not support DCB */
 956         if (!hnae3_dev_dcb_supported(hdev)) {
 957                 hdev->tc_max = 1;
 958                 hdev->pfc_max = 0;
 959         } else {
 960                 hdev->pfc_max = hdev->tc_max;
 961         }
 962
 963         hdev->tm_info.num_tc = 1;
 964
 965         /* Currently not support uncontiuous tc */
 966         for (i = 0; i < hdev->tm_info.num_tc; i++)
 967                 hnae3_set_bit(hdev->hw_tc_map, i, 1);
 968
 969         hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
 970
 971         return ret;
 972 }
 973
 974 static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
 975                             int tso_mss_max)
 976 {
 977         struct hclge_cfg_tso_status_cmd *req;
 978         struct hclge_desc desc;
 979         u16 tso_mss;
 980
 981         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
 982
 983         req = (struct hclge_cfg_tso_status_cmd *)desc.data;
 984
 985         tso_mss = 0;
 986         hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
 987                         HCLGE_TSO_MSS_MIN_S, tso_mss_min);
 988         req->tso_mss_min = cpu_to_le16(tso_mss);
 989
 990         tso_mss = 0;
 991         hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
 992                         HCLGE_TSO_MSS_MIN_S, tso_mss_max);
 993         req->tso_mss_max = cpu_to_le16(tso_mss);
 994
 995         return hclge_cmd_send(&hdev->hw, &desc, 1);
 996 }
 997
 998 static int hclge_config_gro(struct hclge_dev *hdev, bool en)
 999 {
1000         struct hclge_cfg_gro_status_cmd *req;
1001         struct hclge_desc desc;
1002         int ret;
1003
1004         if (!hnae3_dev_gro_supported(hdev))
1005                 return 0;
1006
1007         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, false);
1008         req = (struct hclge_cfg_gro_status_cmd *)desc.data;
1009
1010         req->gro_en = cpu_to_le16(en ? 1 : 0);
1011
1012         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1013         if (ret)
1014                 dev_err(&hdev->pdev->dev,
1015                         "GRO hardware config cmd failed, ret = %d\n", ret);
1016
1017         return ret;
1018 }
1019
1020 static int hclge_alloc_tqps(struct hclge_dev *hdev)
1021 {
1022         struct hclge_tqp *tqp;
1023         int i;
1024
1025         hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1026                                   sizeof(struct hclge_tqp), GFP_KERNEL);
1027         if (!hdev->htqp)
1028                 return -ENOMEM;
1029
1030         tqp = hdev->htqp;
1031
1032         for (i = 0; i < hdev->num_tqps; i++) {
1033                 tqp->dev = &hdev->pdev->dev;
1034                 tqp->index = i;
1035
1036                 tqp->q.ae_algo = &ae_algo;
1037                 tqp->q.buf_size = hdev->rx_buf_len;
1038                 tqp->q.desc_num = hdev->num_desc;
1039                 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
1040                         i * HCLGE_TQP_REG_SIZE;
1041
1042                 tqp++;
1043         }
1044
1045         return 0;
1046 }
1047
1048 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1049                                   u16 tqp_pid, u16 tqp_vid, bool is_pf)
1050 {
1051         struct hclge_tqp_map_cmd *req;
1052         struct hclge_desc desc;
1053         int ret;
1054
1055         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1056
1057         req = (struct hclge_tqp_map_cmd *)desc.data;
1058         req->tqp_id = cpu_to_le16(tqp_pid);
1059         req->tqp_vf = func_id;
1060         req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1061                         1 << HCLGE_TQP_MAP_EN_B;
1062         req->tqp_vid = cpu_to_le16(tqp_vid);
1063
1064         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1065         if (ret)
1066                 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret);
1067
1068         return ret;
1069 }
1070
1071 static int  hclge_assign_tqp(struct hclge_vport *vport, u16 num_tqps)
1072 {
1073         struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
1074         struct hclge_dev *hdev = vport->back;
1075         int i, alloced;
1076
1077         for (i = 0, alloced = 0; i < hdev->num_tqps &&
1078              alloced < num_tqps; i++) {
1079                 if (!hdev->htqp[i].alloced) {
1080                         hdev->htqp[i].q.handle = &vport->nic;
1081                         hdev->htqp[i].q.tqp_index = alloced;
1082                         hdev->htqp[i].q.desc_num = kinfo->num_desc;
1083                         kinfo->tqp[alloced] = &hdev->htqp[i].q;
1084                         hdev->htqp[i].alloced = true;
1085                         alloced++;
1086                 }
1087         }
1088         vport->alloc_tqps = alloced;
1089         kinfo->rss_size = min_t(u16, hdev->rss_size_max,
1090                                 vport->alloc_tqps / hdev->tm_info.num_tc);
1091
1092         return 0;
1093 }
1094
1095 static int hclge_knic_setup(struct hclge_vport *vport,
1096                             u16 num_tqps, u16 num_desc)
1097 {
1098         struct hnae3_handle *nic = &vport->nic;
1099         struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1100         struct hclge_dev *hdev = vport->back;
1101         int ret;
1102
1103         kinfo->num_desc = num_desc;
1104         kinfo->rx_buf_len = hdev->rx_buf_len;
1105
1106         kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, num_tqps,
1107                                   sizeof(struct hnae3_queue *), GFP_KERNEL);
1108         if (!kinfo->tqp)
1109                 return -ENOMEM;
1110
1111         ret = hclge_assign_tqp(vport, num_tqps);
1112         if (ret)
1113                 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1114
1115         return ret;
1116 }
1117
1118 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1119                                   struct hclge_vport *vport)
1120 {
1121         struct hnae3_handle *nic = &vport->nic;
1122         struct hnae3_knic_private_info *kinfo;
1123         u16 i;
1124
1125         kinfo = &nic->kinfo;
1126         for (i = 0; i < vport->alloc_tqps; i++) {
1127                 struct hclge_tqp *q =
1128                         container_of(kinfo->tqp[i], struct hclge_tqp, q);
1129                 bool is_pf;
1130                 int ret;
1131
1132                 is_pf = !(vport->vport_id);
1133                 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1134                                              i, is_pf);
1135                 if (ret)
1136                         return ret;
1137         }
1138
1139         return 0;
1140 }
1141
1142 static int hclge_map_tqp(struct hclge_dev *hdev)
1143 {
1144         struct hclge_vport *vport = hdev->vport;
1145         u16 i, num_vport;
1146
1147         num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1148         for (i = 0; i < num_vport; i++) {
1149                 int ret;
1150
1151                 ret = hclge_map_tqp_to_vport(hdev, vport);
1152                 if (ret)
1153                         return ret;
1154
1155                 vport++;
1156         }
1157
1158         return 0;
1159 }
1160
1161 static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1162 {
1163         /* this would be initialized later */
1164 }
1165
1166 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1167 {
1168         struct hnae3_handle *nic = &vport->nic;
1169         struct hclge_dev *hdev = vport->back;
1170         int ret;
1171
1172         nic->pdev = hdev->pdev;
1173         nic->ae_algo = &ae_algo;
1174         nic->numa_node_mask = hdev->numa_node_mask;
1175
1176         if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1177                 ret = hclge_knic_setup(vport, num_tqps, hdev->num_desc);
1178                 if (ret) {
1179                         dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1180                                 ret);
1181                         return ret;
1182                 }
1183         } else {
1184                 hclge_unic_setup(vport, num_tqps);
1185         }
1186
1187         return 0;
1188 }
1189
1190 static int hclge_alloc_vport(struct hclge_dev *hdev)
1191 {
1192         struct pci_dev *pdev = hdev->pdev;
1193         struct hclge_vport *vport;
1194         u32 tqp_main_vport;
1195         u32 tqp_per_vport;
1196         int num_vport, i;
1197         int ret;
1198
1199         /* We need to alloc a vport for main NIC of PF */
1200         num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1201
1202         if (hdev->num_tqps < num_vport) {
1203                 dev_err(&hdev->pdev->dev, "tqps(%d) is less than vports(%d)",
1204                         hdev->num_tqps, num_vport);
1205                 return -EINVAL;
1206         }
1207
1208         /* Alloc the same number of TQPs for every vport */
1209         tqp_per_vport = hdev->num_tqps / num_vport;
1210         tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1211
1212         vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1213                              GFP_KERNEL);
1214         if (!vport)
1215                 return -ENOMEM;
1216
1217         hdev->vport = vport;
1218         hdev->num_alloc_vport = num_vport;
1219
1220         if (IS_ENABLED(CONFIG_PCI_IOV))
1221                 hdev->num_alloc_vfs = hdev->num_req_vfs;
1222
1223         for (i = 0; i < num_vport; i++) {
1224                 vport->back = hdev;
1225                 vport->vport_id = i;
1226                 vport->mps = HCLGE_MAC_DEFAULT_FRAME;
1227
1228                 if (i == 0)
1229                         ret = hclge_vport_setup(vport, tqp_main_vport);
1230                 else
1231                         ret = hclge_vport_setup(vport, tqp_per_vport);
1232                 if (ret) {
1233                         dev_err(&pdev->dev,
1234                                 "vport setup failed for vport %d, %d\n",
1235                                 i, ret);
1236                         return ret;
1237                 }
1238
1239                 vport++;
1240         }
1241
1242         return 0;
1243 }
1244
1245 static int  hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1246                                     struct hclge_pkt_buf_alloc *buf_alloc)
1247 {
1248 /* TX buffer size is unit by 128 byte */
1249 #define HCLGE_BUF_SIZE_UNIT_SHIFT       7
1250 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK    BIT(15)
1251         struct hclge_tx_buff_alloc_cmd *req;
1252         struct hclge_desc desc;
1253         int ret;
1254         u8 i;
1255
1256         req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
1257
1258         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
1259         for (i = 0; i < HCLGE_TC_NUM; i++) {
1260                 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
1261
1262                 req->tx_pkt_buff[i] =
1263                         cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1264                                      HCLGE_BUF_SIZE_UPDATE_EN_MSK);
1265         }
1266
1267         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1268         if (ret)
1269                 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1270                         ret);
1271
1272         return ret;
1273 }
1274
1275 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1276                                  struct hclge_pkt_buf_alloc *buf_alloc)
1277 {
1278         int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
1279
1280         if (ret)
1281                 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret);
1282
1283         return ret;
1284 }
1285
1286 static int hclge_get_tc_num(struct hclge_dev *hdev)
1287 {
1288         int i, cnt = 0;
1289
1290         for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1291                 if (hdev->hw_tc_map & BIT(i))
1292                         cnt++;
1293         return cnt;
1294 }
1295
1296 static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1297 {
1298         int i, cnt = 0;
1299
1300         for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1301                 if (hdev->hw_tc_map & BIT(i) &&
1302                     hdev->tm_info.hw_pfc_map & BIT(i))
1303                         cnt++;
1304         return cnt;
1305 }
1306
1307 /* Get the number of pfc enabled TCs, which have private buffer */
1308 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1309                                   struct hclge_pkt_buf_alloc *buf_alloc)
1310 {
1311         struct hclge_priv_buf *priv;
1312         int i, cnt = 0;
1313
1314         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1315                 priv = &buf_alloc->priv_buf[i];
1316                 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1317                     priv->enable)
1318                         cnt++;
1319         }
1320
1321         return cnt;
1322 }
1323
1324 /* Get the number of pfc disabled TCs, which have private buffer */
1325 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1326                                      struct hclge_pkt_buf_alloc *buf_alloc)
1327 {
1328         struct hclge_priv_buf *priv;
1329         int i, cnt = 0;
1330
1331         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1332                 priv = &buf_alloc->priv_buf[i];
1333                 if (hdev->hw_tc_map & BIT(i) &&
1334                     !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1335                     priv->enable)
1336                         cnt++;
1337         }
1338
1339         return cnt;
1340 }
1341
1342 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1343 {
1344         struct hclge_priv_buf *priv;
1345         u32 rx_priv = 0;
1346         int i;
1347
1348         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1349                 priv = &buf_alloc->priv_buf[i];
1350                 if (priv->enable)
1351                         rx_priv += priv->buf_size;
1352         }
1353         return rx_priv;
1354 }
1355
1356 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1357 {
1358         u32 i, total_tx_size = 0;
1359
1360         for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1361                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
1362
1363         return total_tx_size;
1364 }
1365
1366 static bool  hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1367                                 struct hclge_pkt_buf_alloc *buf_alloc,
1368                                 u32 rx_all)
1369 {
1370         u32 shared_buf_min, shared_buf_tc, shared_std;
1371         int tc_num, pfc_enable_num;
1372         u32 shared_buf, aligned_mps;
1373         u32 rx_priv;
1374         int i;
1375
1376         tc_num = hclge_get_tc_num(hdev);
1377         pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1378         aligned_mps = roundup(hdev->mps, HCLGE_BUF_SIZE_UNIT);
1379
1380         if (hnae3_dev_dcb_supported(hdev))
1381                 shared_buf_min = 2 * aligned_mps + hdev->dv_buf_size;
1382         else
1383                 shared_buf_min = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF
1384                                         + hdev->dv_buf_size;
1385
1386         shared_buf_tc = pfc_enable_num * aligned_mps +
1387                         (tc_num - pfc_enable_num) * aligned_mps / 2 +
1388                         aligned_mps;
1389         shared_std = roundup(max_t(u32, shared_buf_min, shared_buf_tc),
1390                              HCLGE_BUF_SIZE_UNIT);
1391
1392         rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
1393         if (rx_all < rx_priv + shared_std)
1394                 return false;
1395
1396         shared_buf = rounddown(rx_all - rx_priv, HCLGE_BUF_SIZE_UNIT);
1397         buf_alloc->s_buf.buf_size = shared_buf;
1398         if (hnae3_dev_dcb_supported(hdev)) {
1399                 buf_alloc->s_buf.self.high = shared_buf - hdev->dv_buf_size;
1400                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
1401                         - roundup(aligned_mps / 2, HCLGE_BUF_SIZE_UNIT);
1402         } else {
1403                 buf_alloc->s_buf.self.high = aligned_mps +
1404                                                 HCLGE_NON_DCB_ADDITIONAL_BUF;
1405                 buf_alloc->s_buf.self.low =
1406                         roundup(aligned_mps / 2, HCLGE_BUF_SIZE_UNIT);
1407         }
1408
1409         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1410                 if ((hdev->hw_tc_map & BIT(i)) &&
1411                     (hdev->tm_info.hw_pfc_map & BIT(i))) {
1412                         buf_alloc->s_buf.tc_thrd[i].low = aligned_mps;
1413                         buf_alloc->s_buf.tc_thrd[i].high = 2 * aligned_mps;
1414                 } else {
1415                         buf_alloc->s_buf.tc_thrd[i].low = 0;
1416                         buf_alloc->s_buf.tc_thrd[i].high = aligned_mps;
1417                 }
1418         }
1419
1420         return true;
1421 }
1422
1423 static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1424                                 struct hclge_pkt_buf_alloc *buf_alloc)
1425 {
1426         u32 i, total_size;
1427
1428         total_size = hdev->pkt_buf_size;
1429
1430         /* alloc tx buffer for all enabled tc */
1431         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1432                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
1433
1434                 if (total_size < hdev->tx_buf_size)
1435                         return -ENOMEM;
1436
1437                 if (hdev->hw_tc_map & BIT(i))
1438                         priv->tx_buf_size = hdev->tx_buf_size;
1439                 else
1440                         priv->tx_buf_size = 0;
1441
1442                 total_size -= priv->tx_buf_size;
1443         }
1444
1445         return 0;
1446 }
1447
1448 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1449  * @hdev: pointer to struct hclge_dev
1450  * @buf_alloc: pointer to buffer calculation data
1451  * @return: 0: calculate sucessful, negative: fail
1452  */
1453 static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1454                                 struct hclge_pkt_buf_alloc *buf_alloc)
1455 {
1456         u32 rx_all = hdev->pkt_buf_size, aligned_mps;
1457         int no_pfc_priv_num, pfc_priv_num;
1458         struct hclge_priv_buf *priv;
1459         int i;
1460
1461         aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT);
1462         rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
1463
1464         /* When DCB is not supported, rx private
1465          * buffer is not allocated.
1466          */
1467         if (!hnae3_dev_dcb_supported(hdev)) {
1468                 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1469                         return -ENOMEM;
1470
1471                 return 0;
1472         }
1473
1474         /* step 1, try to alloc private buffer for all enabled tc */
1475         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1476                 priv = &buf_alloc->priv_buf[i];
1477                 if (hdev->hw_tc_map & BIT(i)) {
1478                         priv->enable = 1;
1479                         if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1480                                 priv->wl.low = aligned_mps;
1481                                 priv->wl.high =
1482                                         roundup(priv->wl.low + aligned_mps,
1483                                                 HCLGE_BUF_SIZE_UNIT);
1484                                 priv->buf_size = priv->wl.high +
1485                                         hdev->dv_buf_size;
1486                         } else {
1487                                 priv->wl.low = 0;
1488                                 priv->wl.high = 2 * aligned_mps;
1489                                 priv->buf_size = priv->wl.high +
1490                                                 hdev->dv_buf_size;
1491                         }
1492                 } else {
1493                         priv->enable = 0;
1494                         priv->wl.low = 0;
1495                         priv->wl.high = 0;
1496                         priv->buf_size = 0;
1497                 }
1498         }
1499
1500         if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1501                 return 0;
1502
1503         /* step 2, try to decrease the buffer size of
1504          * no pfc TC's private buffer
1505          */
1506         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1507                 priv = &buf_alloc->priv_buf[i];
1508
1509                 priv->enable = 0;
1510                 priv->wl.low = 0;
1511                 priv->wl.high = 0;
1512                 priv->buf_size = 0;
1513
1514                 if (!(hdev->hw_tc_map & BIT(i)))
1515                         continue;
1516
1517                 priv->enable = 1;
1518
1519                 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1520                         priv->wl.low = 256;
1521                         priv->wl.high = priv->wl.low + aligned_mps;
1522                         priv->buf_size = priv->wl.high + hdev->dv_buf_size;
1523                 } else {
1524                         priv->wl.low = 0;
1525                         priv->wl.high = aligned_mps;
1526                         priv->buf_size = priv->wl.high + hdev->dv_buf_size;
1527                 }
1528         }
1529
1530         if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1531                 return 0;
1532
1533         /* step 3, try to reduce the number of pfc disabled TCs,
1534          * which have private buffer
1535          */
1536         /* get the total no pfc enable TC number, which have private buffer */
1537         no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
1538
1539         /* let the last to be cleared first */
1540         for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1541                 priv = &buf_alloc->priv_buf[i];
1542
1543                 if (hdev->hw_tc_map & BIT(i) &&
1544                     !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1545                         /* Clear the no pfc TC private buffer */
1546                         priv->wl.low = 0;
1547                         priv->wl.high = 0;
1548                         priv->buf_size = 0;
1549                         priv->enable = 0;
1550                         no_pfc_priv_num--;
1551                 }
1552
1553                 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
1554                     no_pfc_priv_num == 0)
1555                         break;
1556         }
1557
1558         if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1559                 return 0;
1560
1561         /* step 4, try to reduce the number of pfc enabled TCs
1562          * which have private buffer.
1563          */
1564         pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
1565
1566         /* let the last to be cleared first */
1567         for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1568                 priv = &buf_alloc->priv_buf[i];
1569
1570                 if (hdev->hw_tc_map & BIT(i) &&
1571                     hdev->tm_info.hw_pfc_map & BIT(i)) {
1572                         /* Reduce the number of pfc TC with private buffer */
1573                         priv->wl.low = 0;
1574                         priv->enable = 0;
1575                         priv->wl.high = 0;
1576                         priv->buf_size = 0;
1577                         pfc_priv_num--;
1578                 }
1579
1580                 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
1581                     pfc_priv_num == 0)
1582                         break;
1583         }
1584         if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1585                 return 0;
1586
1587         return -ENOMEM;
1588 }
1589
1590 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1591                                    struct hclge_pkt_buf_alloc *buf_alloc)
1592 {
1593         struct hclge_rx_priv_buff_cmd *req;
1594         struct hclge_desc desc;
1595         int ret;
1596         int i;
1597
1598         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
1599         req = (struct hclge_rx_priv_buff_cmd *)desc.data;
1600
1601         /* Alloc private buffer TCs */
1602         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1603                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
1604
1605                 req->buf_num[i] =
1606                         cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1607                 req->buf_num[i] |=
1608                         cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
1609         }
1610
1611         req->shared_buf =
1612                 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
1613                             (1 << HCLGE_TC0_PRI_BUF_EN_B));
1614
1615         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1616         if (ret)
1617                 dev_err(&hdev->pdev->dev,
1618                         "rx private buffer alloc cmd failed %d\n", ret);
1619
1620         return ret;
1621 }
1622
1623 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1624                                    struct hclge_pkt_buf_alloc *buf_alloc)
1625 {
1626         struct hclge_rx_priv_wl_buf *req;
1627         struct hclge_priv_buf *priv;
1628         struct hclge_desc desc[2];
1629         int i, j;
1630         int ret;
1631
1632         for (i = 0; i < 2; i++) {
1633                 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1634                                            false);
1635                 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1636
1637                 /* The first descriptor set the NEXT bit to 1 */
1638                 if (i == 0)
1639                         desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1640                 else
1641                         desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1642
1643                 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1644                         u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1645
1646                         priv = &buf_alloc->priv_buf[idx];
1647                         req->tc_wl[j].high =
1648                                 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1649                         req->tc_wl[j].high |=
1650                                 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1651                         req->tc_wl[j].low =
1652                                 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1653                         req->tc_wl[j].low |=
1654                                  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1655                 }
1656         }
1657
1658         /* Send 2 descriptor at one time */
1659         ret = hclge_cmd_send(&hdev->hw, desc, 2);
1660         if (ret)
1661                 dev_err(&hdev->pdev->dev,
1662                         "rx private waterline config cmd failed %d\n",
1663                         ret);
1664         return ret;
1665 }
1666
1667 static int hclge_common_thrd_config(struct hclge_dev *hdev,
1668                                     struct hclge_pkt_buf_alloc *buf_alloc)
1669 {
1670         struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
1671         struct hclge_rx_com_thrd *req;
1672         struct hclge_desc desc[2];
1673         struct hclge_tc_thrd *tc;
1674         int i, j;
1675         int ret;
1676
1677         for (i = 0; i < 2; i++) {
1678                 hclge_cmd_setup_basic_desc(&desc[i],
1679                                            HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1680                 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1681
1682                 /* The first descriptor set the NEXT bit to 1 */
1683                 if (i == 0)
1684                         desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1685                 else
1686                         desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1687
1688                 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1689                         tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1690
1691                         req->com_thrd[j].high =
1692                                 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1693                         req->com_thrd[j].high |=
1694                                  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1695                         req->com_thrd[j].low =
1696                                 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1697                         req->com_thrd[j].low |=
1698                                  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1699                 }
1700         }
1701
1702         /* Send 2 descriptors at one time */
1703         ret = hclge_cmd_send(&hdev->hw, desc, 2);
1704         if (ret)
1705                 dev_err(&hdev->pdev->dev,
1706                         "common threshold config cmd failed %d\n", ret);
1707         return ret;
1708 }
1709
1710 static int hclge_common_wl_config(struct hclge_dev *hdev,
1711                                   struct hclge_pkt_buf_alloc *buf_alloc)
1712 {
1713         struct hclge_shared_buf *buf = &buf_alloc->s_buf;
1714         struct hclge_rx_com_wl *req;
1715         struct hclge_desc desc;
1716         int ret;
1717
1718         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1719
1720         req = (struct hclge_rx_com_wl *)desc.data;
1721         req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1722         req->com_wl.high |=  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1723
1724         req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1725         req->com_wl.low |=  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1726
1727         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1728         if (ret)
1729                 dev_err(&hdev->pdev->dev,
1730                         "common waterline config cmd failed %d\n", ret);
1731
1732         return ret;
1733 }
1734
1735 int hclge_buffer_alloc(struct hclge_dev *hdev)
1736 {
1737         struct hclge_pkt_buf_alloc *pkt_buf;
1738         int ret;
1739
1740         pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1741         if (!pkt_buf)
1742                 return -ENOMEM;
1743
1744         ret = hclge_tx_buffer_calc(hdev, pkt_buf);
1745         if (ret) {
1746                 dev_err(&hdev->pdev->dev,
1747                         "could not calc tx buffer size for all TCs %d\n", ret);
1748                 goto out;
1749         }
1750
1751         ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
1752         if (ret) {
1753                 dev_err(&hdev->pdev->dev,
1754                         "could not alloc tx buffers %d\n", ret);
1755                 goto out;
1756         }
1757
1758         ret = hclge_rx_buffer_calc(hdev, pkt_buf);
1759         if (ret) {
1760                 dev_err(&hdev->pdev->dev,
1761                         "could not calc rx priv buffer size for all TCs %d\n",
1762                         ret);
1763                 goto out;
1764         }
1765
1766         ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
1767         if (ret) {
1768                 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1769                         ret);
1770                 goto out;
1771         }
1772
1773         if (hnae3_dev_dcb_supported(hdev)) {
1774                 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
1775                 if (ret) {
1776                         dev_err(&hdev->pdev->dev,
1777                                 "could not configure rx private waterline %d\n",
1778                                 ret);
1779                         goto out;
1780                 }
1781
1782                 ret = hclge_common_thrd_config(hdev, pkt_buf);
1783                 if (ret) {
1784                         dev_err(&hdev->pdev->dev,
1785                                 "could not configure common threshold %d\n",
1786                                 ret);
1787                         goto out;
1788                 }
1789         }
1790
1791         ret = hclge_common_wl_config(hdev, pkt_buf);
1792         if (ret)
1793                 dev_err(&hdev->pdev->dev,
1794                         "could not configure common waterline %d\n", ret);
1795
1796 out:
1797         kfree(pkt_buf);
1798         return ret;
1799 }
1800
1801 static int hclge_init_roce_base_info(struct hclge_vport *vport)
1802 {
1803         struct hnae3_handle *roce = &vport->roce;
1804         struct hnae3_handle *nic = &vport->nic;
1805
1806         roce->rinfo.num_vectors = vport->back->num_roce_msi;
1807
1808         if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
1809             vport->back->num_msi_left == 0)
1810                 return -EINVAL;
1811
1812         roce->rinfo.base_vector = vport->back->roce_base_vector;
1813
1814         roce->rinfo.netdev = nic->kinfo.netdev;
1815         roce->rinfo.roce_io_base = vport->back->hw.io_base;
1816
1817         roce->pdev = nic->pdev;
1818         roce->ae_algo = nic->ae_algo;
1819         roce->numa_node_mask = nic->numa_node_mask;
1820
1821         return 0;
1822 }
1823
1824 static int hclge_init_msi(struct hclge_dev *hdev)
1825 {
1826         struct pci_dev *pdev = hdev->pdev;
1827         int vectors;
1828         int i;
1829
1830         vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
1831                                         PCI_IRQ_MSI | PCI_IRQ_MSIX);
1832         if (vectors < 0) {
1833                 dev_err(&pdev->dev,
1834                         "failed(%d) to allocate MSI/MSI-X vectors\n",
1835                         vectors);
1836                 return vectors;
1837         }
1838         if (vectors < hdev->num_msi)
1839                 dev_warn(&hdev->pdev->dev,
1840                          "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
1841                          hdev->num_msi, vectors);
1842
1843         hdev->num_msi = vectors;
1844         hdev->num_msi_left = vectors;
1845         hdev->base_msi_vector = pdev->irq;
1846         hdev->roce_base_vector = hdev->base_msi_vector +
1847                                 hdev->roce_base_msix_offset;
1848
1849         hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1850                                            sizeof(u16), GFP_KERNEL);
1851         if (!hdev->vector_status) {
1852                 pci_free_irq_vectors(pdev);
1853                 return -ENOMEM;
1854         }
1855
1856         for (i = 0; i < hdev->num_msi; i++)
1857                 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
1858
1859         hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
1860                                         sizeof(int), GFP_KERNEL);
1861         if (!hdev->vector_irq) {
1862                 pci_free_irq_vectors(pdev);
1863                 return -ENOMEM;
1864         }
1865
1866         return 0;
1867 }
1868
1869 static u8 hclge_check_speed_dup(u8 duplex, int speed)
1870 {
1871
1872         if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M))
1873                 duplex = HCLGE_MAC_FULL;
1874
1875         return duplex;
1876 }
1877
1878 static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed,
1879                                       u8 duplex)
1880 {
1881         struct hclge_config_mac_speed_dup_cmd *req;
1882         struct hclge_desc desc;
1883         int ret;
1884
1885         req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
1886
1887         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
1888
1889         hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
1890
1891         switch (speed) {
1892         case HCLGE_MAC_SPEED_10M:
1893                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1894                                 HCLGE_CFG_SPEED_S, 6);
1895                 break;
1896         case HCLGE_MAC_SPEED_100M:
1897                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1898                                 HCLGE_CFG_SPEED_S, 7);
1899                 break;
1900         case HCLGE_MAC_SPEED_1G:
1901                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1902                                 HCLGE_CFG_SPEED_S, 0);
1903                 break;
1904         case HCLGE_MAC_SPEED_10G:
1905                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1906                                 HCLGE_CFG_SPEED_S, 1);
1907                 break;
1908         case HCLGE_MAC_SPEED_25G:
1909                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1910                                 HCLGE_CFG_SPEED_S, 2);
1911                 break;
1912         case HCLGE_MAC_SPEED_40G:
1913                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1914                                 HCLGE_CFG_SPEED_S, 3);
1915                 break;
1916         case HCLGE_MAC_SPEED_50G:
1917                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1918                                 HCLGE_CFG_SPEED_S, 4);
1919                 break;
1920         case HCLGE_MAC_SPEED_100G:
1921                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1922                                 HCLGE_CFG_SPEED_S, 5);
1923                 break;
1924         default:
1925                 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
1926                 return -EINVAL;
1927         }
1928
1929         hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
1930                       1);
1931
1932         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1933         if (ret) {
1934                 dev_err(&hdev->pdev->dev,
1935                         "mac speed/duplex config cmd failed %d.\n", ret);
1936                 return ret;
1937         }
1938
1939         return 0;
1940 }
1941
1942 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
1943 {
1944         int ret;
1945
1946         duplex = hclge_check_speed_dup(duplex, speed);
1947         if (hdev->hw.mac.speed == speed && hdev->hw.mac.duplex == duplex)
1948                 return 0;
1949
1950         ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex);
1951         if (ret)
1952                 return ret;
1953
1954         hdev->hw.mac.speed = speed;
1955         hdev->hw.mac.duplex = duplex;
1956
1957         return 0;
1958 }
1959
1960 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
1961                                      u8 duplex)
1962 {
1963         struct hclge_vport *vport = hclge_get_vport(handle);
1964         struct hclge_dev *hdev = vport->back;
1965
1966         return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
1967 }
1968
1969 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
1970 {
1971         struct hclge_config_auto_neg_cmd *req;
1972         struct hclge_desc desc;
1973         u32 flag = 0;
1974         int ret;
1975
1976         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
1977
1978         req = (struct hclge_config_auto_neg_cmd *)desc.data;
1979         hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
1980         req->cfg_an_cmd_flag = cpu_to_le32(flag);
1981
1982         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1983         if (ret)
1984                 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
1985                         ret);
1986
1987         return ret;
1988 }
1989
1990 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
1991 {
1992         struct hclge_vport *vport = hclge_get_vport(handle);
1993         struct hclge_dev *hdev = vport->back;
1994
1995         return hclge_set_autoneg_en(hdev, enable);
1996 }
1997
1998 static int hclge_get_autoneg(struct hnae3_handle *handle)
1999 {
2000         struct hclge_vport *vport = hclge_get_vport(handle);
2001         struct hclge_dev *hdev = vport->back;
2002         struct phy_device *phydev = hdev->hw.mac.phydev;
2003
2004         if (phydev)
2005                 return phydev->autoneg;
2006
2007         return hdev->hw.mac.autoneg;
2008 }
2009
2010 static int hclge_mac_init(struct hclge_dev *hdev)
2011 {
2012         struct hclge_mac *mac = &hdev->hw.mac;
2013         int ret;
2014
2015         hdev->support_sfp_query = true;
2016         hdev->hw.mac.duplex = HCLGE_MAC_FULL;
2017         ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed,
2018                                          hdev->hw.mac.duplex);
2019         if (ret) {
2020                 dev_err(&hdev->pdev->dev,
2021                         "Config mac speed dup fail ret=%d\n", ret);
2022                 return ret;
2023         }
2024
2025         mac->link = 0;
2026
2027         ret = hclge_set_mac_mtu(hdev, hdev->mps);
2028         if (ret) {
2029                 dev_err(&hdev->pdev->dev, "set mtu failed ret=%d\n", ret);
2030                 return ret;
2031         }
2032
2033         ret = hclge_buffer_alloc(hdev);
2034         if (ret)
2035                 dev_err(&hdev->pdev->dev,
2036                         "allocate buffer fail, ret=%d\n", ret);
2037
2038         return ret;
2039 }
2040
2041 static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
2042 {
2043         if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state))
2044                 schedule_work(&hdev->mbx_service_task);
2045 }
2046
2047 static void hclge_reset_task_schedule(struct hclge_dev *hdev)
2048 {
2049         if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
2050                 schedule_work(&hdev->rst_service_task);
2051 }
2052
2053 static void hclge_task_schedule(struct hclge_dev *hdev)
2054 {
2055         if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2056             !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2057             !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2058                 (void)schedule_work(&hdev->service_task);
2059 }
2060
2061 static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2062 {
2063         struct hclge_link_status_cmd *req;
2064         struct hclge_desc desc;
2065         int link_status;
2066         int ret;
2067
2068         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2069         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2070         if (ret) {
2071                 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2072                         ret);
2073                 return ret;
2074         }
2075
2076         req = (struct hclge_link_status_cmd *)desc.data;
2077         link_status = req->status & HCLGE_LINK_STATUS_UP_M;
2078
2079         return !!link_status;
2080 }
2081
2082 static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2083 {
2084         int mac_state;
2085         int link_stat;
2086
2087         if (test_bit(HCLGE_STATE_DOWN, &hdev->state))
2088                 return 0;
2089
2090         mac_state = hclge_get_mac_link_status(hdev);
2091
2092         if (hdev->hw.mac.phydev) {
2093                 if (hdev->hw.mac.phydev->state == PHY_RUNNING)
2094                         link_stat = mac_state &
2095                                 hdev->hw.mac.phydev->link;
2096                 else
2097                         link_stat = 0;
2098
2099         } else {
2100                 link_stat = mac_state;
2101         }
2102
2103         return !!link_stat;
2104 }
2105
2106 static void hclge_update_link_status(struct hclge_dev *hdev)
2107 {
2108         struct hnae3_client *client = hdev->nic_client;
2109         struct hnae3_handle *handle;
2110         int state;
2111         int i;
2112
2113         if (!client)
2114                 return;
2115         state = hclge_get_mac_phy_link(hdev);
2116         if (state != hdev->hw.mac.link) {
2117                 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2118                         handle = &hdev->vport[i].nic;
2119                         client->ops->link_status_change(handle, state);
2120                 }
2121                 hdev->hw.mac.link = state;
2122         }
2123 }
2124
2125 static int hclge_get_sfp_speed(struct hclge_dev *hdev, u32 *speed)
2126 {
2127         struct hclge_sfp_speed_cmd *resp = NULL;
2128         struct hclge_desc desc;
2129         int ret;
2130
2131         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SFP_GET_SPEED, true);
2132         resp = (struct hclge_sfp_speed_cmd *)desc.data;
2133         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2134         if (ret == -EOPNOTSUPP) {
2135                 dev_warn(&hdev->pdev->dev,
2136                          "IMP do not support get SFP speed %d\n", ret);
2137                 return ret;
2138         } else if (ret) {
2139                 dev_err(&hdev->pdev->dev, "get sfp speed failed %d\n", ret);
2140                 return ret;
2141         }
2142
2143         *speed = resp->sfp_speed;
2144
2145         return 0;
2146 }
2147
2148 static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2149 {
2150         struct hclge_mac mac = hdev->hw.mac;
2151         int speed;
2152         int ret;
2153
2154         /* get the speed from SFP cmd when phy
2155          * doesn't exit.
2156          */
2157         if (mac.phydev)
2158                 return 0;
2159
2160         /* if IMP does not support get SFP/qSFP speed, return directly */
2161         if (!hdev->support_sfp_query)
2162                 return 0;
2163
2164         ret = hclge_get_sfp_speed(hdev, &speed);
2165         if (ret == -EOPNOTSUPP) {
2166                 hdev->support_sfp_query = false;
2167                 return ret;
2168         } else if (ret) {
2169                 return ret;
2170         }
2171
2172         if (speed == HCLGE_MAC_SPEED_UNKNOWN)
2173                 return 0; /* do nothing if no SFP */
2174
2175         /* must config full duplex for SFP */
2176         return hclge_cfg_mac_speed_dup(hdev, speed, HCLGE_MAC_FULL);
2177 }
2178
2179 static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2180 {
2181         struct hclge_vport *vport = hclge_get_vport(handle);
2182         struct hclge_dev *hdev = vport->back;
2183
2184         return hclge_update_speed_duplex(hdev);
2185 }
2186
2187 static int hclge_get_status(struct hnae3_handle *handle)
2188 {
2189         struct hclge_vport *vport = hclge_get_vport(handle);
2190         struct hclge_dev *hdev = vport->back;
2191
2192         hclge_update_link_status(hdev);
2193
2194         return hdev->hw.mac.link;
2195 }
2196
2197 static void hclge_service_timer(struct timer_list *t)
2198 {
2199         struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
2200
2201         mod_timer(&hdev->service_timer, jiffies + HZ);
2202         hdev->hw_stats.stats_timer++;
2203         hclge_task_schedule(hdev);
2204 }
2205
2206 static void hclge_service_complete(struct hclge_dev *hdev)
2207 {
2208         WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2209
2210         /* Flush memory before next watchdog */
2211         smp_mb__before_atomic();
2212         clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2213 }
2214
2215 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2216 {
2217         u32 rst_src_reg, cmdq_src_reg, msix_src_reg;
2218
2219         /* fetch the events from their corresponding regs */
2220         rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
2221         cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
2222         msix_src_reg = hclge_read_dev(&hdev->hw,
2223                                       HCLGE_VECTOR0_PF_OTHER_INT_STS_REG);
2224
2225         /* Assumption: If by any chance reset and mailbox events are reported
2226          * together then we will only process reset event in this go and will
2227          * defer the processing of the mailbox events. Since, we would have not
2228          * cleared RX CMDQ event this time we would receive again another
2229          * interrupt from H/W just for the mailbox.
2230          */
2231
2232         /* check for vector0 reset event sources */
2233         if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2234                 dev_info(&hdev->pdev->dev, "IMP reset interrupt\n");
2235                 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2236                 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2237                 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2238                 return HCLGE_VECTOR0_EVENT_RST;
2239         }
2240
2241         if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
2242                 dev_info(&hdev->pdev->dev, "global reset interrupt\n");
2243                 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2244                 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2245                 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2246                 return HCLGE_VECTOR0_EVENT_RST;
2247         }
2248
2249         if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
2250                 dev_info(&hdev->pdev->dev, "core reset interrupt\n");
2251                 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2252                 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2253                 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2254                 return HCLGE_VECTOR0_EVENT_RST;
2255         }
2256
2257         /* check for vector0 msix event source */
2258         if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK)
2259                 return HCLGE_VECTOR0_EVENT_ERR;
2260
2261         /* check for vector0 mailbox(=CMDQ RX) event source */
2262         if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
2263                 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
2264                 *clearval = cmdq_src_reg;
2265                 return HCLGE_VECTOR0_EVENT_MBX;
2266         }
2267
2268         return HCLGE_VECTOR0_EVENT_OTHER;
2269 }
2270
2271 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2272                                     u32 regclr)
2273 {
2274         switch (event_type) {
2275         case HCLGE_VECTOR0_EVENT_RST:
2276                 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
2277                 break;
2278         case HCLGE_VECTOR0_EVENT_MBX:
2279                 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
2280                 break;
2281         default:
2282                 break;
2283         }
2284 }
2285
2286 static void hclge_clear_all_event_cause(struct hclge_dev *hdev)
2287 {
2288         hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST,
2289                                 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) |
2290                                 BIT(HCLGE_VECTOR0_CORERESET_INT_B) |
2291                                 BIT(HCLGE_VECTOR0_IMPRESET_INT_B));
2292         hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0);
2293 }
2294
2295 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2296 {
2297         writel(enable ? 1 : 0, vector->addr);
2298 }
2299
2300 static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2301 {
2302         struct hclge_dev *hdev = data;
2303         u32 event_cause;
2304         u32 clearval;
2305
2306         hclge_enable_vector(&hdev->misc_vector, false);
2307         event_cause = hclge_check_event_cause(hdev, &clearval);
2308
2309         /* vector 0 interrupt is shared with reset and mailbox source events.*/
2310         switch (event_cause) {
2311         case HCLGE_VECTOR0_EVENT_ERR:
2312                 /* we do not know what type of reset is required now. This could
2313                  * only be decided after we fetch the type of errors which
2314                  * caused this event. Therefore, we will do below for now:
2315                  * 1. Assert HNAE3_UNKNOWN_RESET type of reset. This means we
2316                  *    have defered type of reset to be used.
2317                  * 2. Schedule the reset serivce task.
2318                  * 3. When service task receives  HNAE3_UNKNOWN_RESET type it
2319                  *    will fetch the correct type of reset.  This would be done
2320                  *    by first decoding the types of errors.
2321                  */
2322                 set_bit(HNAE3_UNKNOWN_RESET, &hdev->reset_request);
2323                 /* fall through */
2324         case HCLGE_VECTOR0_EVENT_RST:
2325                 hclge_reset_task_schedule(hdev);
2326                 break;
2327         case HCLGE_VECTOR0_EVENT_MBX:
2328                 /* If we are here then,
2329                  * 1. Either we are not handling any mbx task and we are not
2330                  *    scheduled as well
2331                  *                        OR
2332                  * 2. We could be handling a mbx task but nothing more is
2333                  *    scheduled.
2334                  * In both cases, we should schedule mbx task as there are more
2335                  * mbx messages reported by this interrupt.
2336                  */
2337                 hclge_mbx_task_schedule(hdev);
2338                 break;
2339         default:
2340                 dev_warn(&hdev->pdev->dev,
2341                          "received unknown or unhandled event of vector0\n");
2342                 break;
2343         }
2344
2345         /* clear the source of interrupt if it is not cause by reset */
2346         if (event_cause == HCLGE_VECTOR0_EVENT_MBX) {
2347                 hclge_clear_event_cause(hdev, event_cause, clearval);
2348                 hclge_enable_vector(&hdev->misc_vector, true);
2349         }
2350
2351         return IRQ_HANDLED;
2352 }
2353
2354 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2355 {
2356         if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) {
2357                 dev_warn(&hdev->pdev->dev,
2358                          "vector(vector_id %d) has been freed.\n", vector_id);
2359                 return;
2360         }
2361
2362         hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2363         hdev->num_msi_left += 1;
2364         hdev->num_msi_used -= 1;
2365 }
2366
2367 static void hclge_get_misc_vector(struct hclge_dev *hdev)
2368 {
2369         struct hclge_misc_vector *vector = &hdev->misc_vector;
2370
2371         vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2372
2373         vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2374         hdev->vector_status[0] = 0;
2375
2376         hdev->num_msi_left -= 1;
2377         hdev->num_msi_used += 1;
2378 }
2379
2380 static int hclge_misc_irq_init(struct hclge_dev *hdev)
2381 {
2382         int ret;
2383
2384         hclge_get_misc_vector(hdev);
2385
2386         /* this would be explicitly freed in the end */
2387         ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2388                           0, "hclge_misc", hdev);
2389         if (ret) {
2390                 hclge_free_vector(hdev, 0);
2391                 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2392                         hdev->misc_vector.vector_irq);
2393         }
2394
2395         return ret;
2396 }
2397
2398 static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2399 {
2400         free_irq(hdev->misc_vector.vector_irq, hdev);
2401         hclge_free_vector(hdev, 0);
2402 }
2403
2404 int hclge_notify_client(struct hclge_dev *hdev,
2405                         enum hnae3_reset_notify_type type)
2406 {
2407         struct hnae3_client *client = hdev->nic_client;
2408         u16 i;
2409
2410         if (!client->ops->reset_notify)
2411                 return -EOPNOTSUPP;
2412
2413         for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2414                 struct hnae3_handle *handle = &hdev->vport[i].nic;
2415                 int ret;
2416
2417                 ret = client->ops->reset_notify(handle, type);
2418                 if (ret) {
2419                         dev_err(&hdev->pdev->dev,
2420                                 "notify nic client failed %d(%d)\n", type, ret);
2421                         return ret;
2422                 }
2423         }
2424
2425         return 0;
2426 }
2427
2428 static int hclge_notify_roce_client(struct hclge_dev *hdev,
2429                                     enum hnae3_reset_notify_type type)
2430 {
2431         struct hnae3_client *client = hdev->roce_client;
2432         int ret = 0;
2433         u16 i;
2434
2435         if (!client)
2436                 return 0;
2437
2438         if (!client->ops->reset_notify)
2439                 return -EOPNOTSUPP;
2440
2441         for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2442                 struct hnae3_handle *handle = &hdev->vport[i].roce;
2443
2444                 ret = client->ops->reset_notify(handle, type);
2445                 if (ret) {
2446                         dev_err(&hdev->pdev->dev,
2447                                 "notify roce client failed %d(%d)",
2448                                 type, ret);
2449                         return ret;
2450                 }
2451         }
2452
2453         return ret;
2454 }
2455
2456 static int hclge_reset_wait(struct hclge_dev *hdev)
2457 {
2458 #define HCLGE_RESET_WATI_MS     100
2459 #define HCLGE_RESET_WAIT_CNT    200
2460         u32 val, reg, reg_bit;
2461         u32 cnt = 0;
2462
2463         switch (hdev->reset_type) {
2464         case HNAE3_IMP_RESET:
2465                 reg = HCLGE_GLOBAL_RESET_REG;
2466                 reg_bit = HCLGE_IMP_RESET_BIT;
2467                 break;
2468         case HNAE3_GLOBAL_RESET:
2469                 reg = HCLGE_GLOBAL_RESET_REG;
2470                 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2471                 break;
2472         case HNAE3_CORE_RESET:
2473                 reg = HCLGE_GLOBAL_RESET_REG;
2474                 reg_bit = HCLGE_CORE_RESET_BIT;
2475                 break;
2476         case HNAE3_FUNC_RESET:
2477                 reg = HCLGE_FUN_RST_ING;
2478                 reg_bit = HCLGE_FUN_RST_ING_B;
2479                 break;
2480         case HNAE3_FLR_RESET:
2481                 break;
2482         default:
2483                 dev_err(&hdev->pdev->dev,
2484                         "Wait for unsupported reset type: %d\n",
2485                         hdev->reset_type);
2486                 return -EINVAL;
2487         }
2488
2489         if (hdev->reset_type == HNAE3_FLR_RESET) {
2490                 while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) &&
2491                        cnt++ < HCLGE_RESET_WAIT_CNT)
2492                         msleep(HCLGE_RESET_WATI_MS);
2493
2494                 if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) {
2495                         dev_err(&hdev->pdev->dev,
2496                                 "flr wait timeout: %d\n", cnt);
2497                         return -EBUSY;
2498                 }
2499
2500                 return 0;
2501         }
2502
2503         val = hclge_read_dev(&hdev->hw, reg);
2504         while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
2505                 msleep(HCLGE_RESET_WATI_MS);
2506                 val = hclge_read_dev(&hdev->hw, reg);
2507                 cnt++;
2508         }
2509
2510         if (cnt >= HCLGE_RESET_WAIT_CNT) {
2511                 dev_warn(&hdev->pdev->dev,
2512                          "Wait for reset timeout: %d\n", hdev->reset_type);
2513                 return -EBUSY;
2514         }
2515
2516         return 0;
2517 }
2518
2519 static int hclge_set_vf_rst(struct hclge_dev *hdev, int func_id, bool reset)
2520 {
2521         struct hclge_vf_rst_cmd *req;
2522         struct hclge_desc desc;
2523
2524         req = (struct hclge_vf_rst_cmd *)desc.data;
2525         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GBL_RST_STATUS, false);
2526         req->dest_vfid = func_id;
2527
2528         if (reset)
2529                 req->vf_rst = 0x1;
2530
2531         return hclge_cmd_send(&hdev->hw, &desc, 1);
2532 }
2533
2534 int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset)
2535 {
2536         int i;
2537
2538         for (i = hdev->num_vmdq_vport + 1; i < hdev->num_alloc_vport; i++) {
2539                 struct hclge_vport *vport = &hdev->vport[i];
2540                 int ret;
2541
2542                 /* Send cmd to set/clear VF's FUNC_RST_ING */
2543                 ret = hclge_set_vf_rst(hdev, vport->vport_id, reset);
2544                 if (ret) {
2545                         dev_err(&hdev->pdev->dev,
2546                                 "set vf(%d) rst failed %d!\n",
2547                                 vport->vport_id, ret);
2548                         return ret;
2549                 }
2550
2551                 if (!reset)
2552                         continue;
2553
2554                 /* Inform VF to process the reset.
2555                  * hclge_inform_reset_assert_to_vf may fail if VF
2556                  * driver is not loaded.
2557                  */
2558                 ret = hclge_inform_reset_assert_to_vf(vport);
2559                 if (ret)
2560                         dev_warn(&hdev->pdev->dev,
2561                                  "inform reset to vf(%d) failed %d!\n",
2562                                  vport->vport_id, ret);
2563         }
2564
2565         return 0;
2566 }
2567
2568 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
2569 {
2570         struct hclge_desc desc;
2571         struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2572         int ret;
2573
2574         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
2575         hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
2576         req->fun_reset_vfid = func_id;
2577
2578         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2579         if (ret)
2580                 dev_err(&hdev->pdev->dev,
2581                         "send function reset cmd fail, status =%d\n", ret);
2582
2583         return ret;
2584 }
2585
2586 static void hclge_do_reset(struct hclge_dev *hdev)
2587 {
2588         struct pci_dev *pdev = hdev->pdev;
2589         u32 val;
2590
2591         switch (hdev->reset_type) {
2592         case HNAE3_GLOBAL_RESET:
2593                 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2594                 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
2595                 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2596                 dev_info(&pdev->dev, "Global Reset requested\n");
2597                 break;
2598         case HNAE3_CORE_RESET:
2599                 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2600                 hnae3_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
2601                 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2602                 dev_info(&pdev->dev, "Core Reset requested\n");
2603                 break;
2604         case HNAE3_FUNC_RESET:
2605                 dev_info(&pdev->dev, "PF Reset requested\n");
2606                 /* schedule again to check later */
2607                 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2608                 hclge_reset_task_schedule(hdev);
2609                 break;
2610         case HNAE3_FLR_RESET:
2611                 dev_info(&pdev->dev, "FLR requested\n");
2612                 /* schedule again to check later */
2613                 set_bit(HNAE3_FLR_RESET, &hdev->reset_pending);
2614                 hclge_reset_task_schedule(hdev);
2615                 break;
2616         default:
2617                 dev_warn(&pdev->dev,
2618                          "Unsupported reset type: %d\n", hdev->reset_type);
2619                 break;
2620         }
2621 }
2622
2623 static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2624                                                    unsigned long *addr)
2625 {
2626         enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2627
2628         /* first, resolve any unknown reset type to the known type(s) */
2629         if (test_bit(HNAE3_UNKNOWN_RESET, addr)) {
2630                 /* we will intentionally ignore any errors from this function
2631                  *  as we will end up in *some* reset request in any case
2632                  */
2633                 hclge_handle_hw_msix_error(hdev, addr);
2634                 clear_bit(HNAE3_UNKNOWN_RESET, addr);
2635                 /* We defered the clearing of the error event which caused
2636                  * interrupt since it was not posssible to do that in
2637                  * interrupt context (and this is the reason we introduced
2638                  * new UNKNOWN reset type). Now, the errors have been
2639                  * handled and cleared in hardware we can safely enable
2640                  * interrupts. This is an exception to the norm.
2641                  */
2642                 hclge_enable_vector(&hdev->misc_vector, true);
2643         }
2644
2645         /* return the highest priority reset level amongst all */
2646         if (test_bit(HNAE3_IMP_RESET, addr)) {
2647                 rst_level = HNAE3_IMP_RESET;
2648                 clear_bit(HNAE3_IMP_RESET, addr);
2649                 clear_bit(HNAE3_GLOBAL_RESET, addr);
2650                 clear_bit(HNAE3_CORE_RESET, addr);
2651                 clear_bit(HNAE3_FUNC_RESET, addr);
2652         } else if (test_bit(HNAE3_GLOBAL_RESET, addr)) {
2653                 rst_level = HNAE3_GLOBAL_RESET;
2654                 clear_bit(HNAE3_GLOBAL_RESET, addr);
2655                 clear_bit(HNAE3_CORE_RESET, addr);
2656                 clear_bit(HNAE3_FUNC_RESET, addr);
2657         } else if (test_bit(HNAE3_CORE_RESET, addr)) {
2658                 rst_level = HNAE3_CORE_RESET;
2659                 clear_bit(HNAE3_CORE_RESET, addr);
2660                 clear_bit(HNAE3_FUNC_RESET, addr);
2661         } else if (test_bit(HNAE3_FUNC_RESET, addr)) {
2662                 rst_level = HNAE3_FUNC_RESET;
2663                 clear_bit(HNAE3_FUNC_RESET, addr);
2664         } else if (test_bit(HNAE3_FLR_RESET, addr)) {
2665                 rst_level = HNAE3_FLR_RESET;
2666                 clear_bit(HNAE3_FLR_RESET, addr);
2667         }
2668
2669         return rst_level;
2670 }
2671
2672 static void hclge_clear_reset_cause(struct hclge_dev *hdev)
2673 {
2674         u32 clearval = 0;
2675
2676         switch (hdev->reset_type) {
2677         case HNAE3_IMP_RESET:
2678                 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2679                 break;
2680         case HNAE3_GLOBAL_RESET:
2681                 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2682                 break;
2683         case HNAE3_CORE_RESET:
2684                 clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2685                 break;
2686         default:
2687                 break;
2688         }
2689
2690         if (!clearval)
2691                 return;
2692
2693         hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, clearval);
2694         hclge_enable_vector(&hdev->misc_vector, true);
2695 }
2696
2697 static int hclge_reset_prepare_down(struct hclge_dev *hdev)
2698 {
2699         int ret = 0;
2700
2701         switch (hdev->reset_type) {
2702         case HNAE3_FUNC_RESET:
2703                 /* fall through */
2704         case HNAE3_FLR_RESET:
2705                 ret = hclge_set_all_vf_rst(hdev, true);
2706                 break;
2707         default:
2708                 break;
2709         }
2710
2711         return ret;
2712 }
2713
2714 static int hclge_reset_prepare_wait(struct hclge_dev *hdev)
2715 {
2716         u32 reg_val;
2717         int ret = 0;
2718
2719         switch (hdev->reset_type) {
2720         case HNAE3_FUNC_RESET:
2721                 /* There is no mechanism for PF to know if VF has stopped IO
2722                  * for now, just wait 100 ms for VF to stop IO
2723                  */
2724                 msleep(100);
2725                 ret = hclge_func_reset_cmd(hdev, 0);
2726                 if (ret) {
2727                         dev_err(&hdev->pdev->dev,
2728                                 "asserting function reset fail %d!\n", ret);
2729                         return ret;
2730                 }
2731
2732                 /* After performaning pf reset, it is not necessary to do the
2733                  * mailbox handling or send any command to firmware, because
2734                  * any mailbox handling or command to firmware is only valid
2735                  * after hclge_cmd_init is called.
2736                  */
2737                 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2738                 break;
2739         case HNAE3_FLR_RESET:
2740                 /* There is no mechanism for PF to know if VF has stopped IO
2741                  * for now, just wait 100 ms for VF to stop IO
2742                  */
2743                 msleep(100);
2744                 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2745                 set_bit(HNAE3_FLR_DOWN, &hdev->flr_state);
2746                 break;
2747         case HNAE3_IMP_RESET:
2748                 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);
2749                 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG,
2750                                 BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val);
2751                 break;
2752         default:
2753                 break;
2754         }
2755
2756         dev_info(&hdev->pdev->dev, "prepare wait ok\n");
2757
2758         return ret;
2759 }
2760
2761 static bool hclge_reset_err_handle(struct hclge_dev *hdev, bool is_timeout)
2762 {
2763 #define MAX_RESET_FAIL_CNT 5
2764 #define RESET_UPGRADE_DELAY_SEC 10
2765
2766         if (hdev->reset_pending) {
2767                 dev_info(&hdev->pdev->dev, "Reset pending %lu\n",
2768                          hdev->reset_pending);
2769                 return true;
2770         } else if ((hdev->reset_type != HNAE3_IMP_RESET) &&
2771                    (hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) &
2772                     BIT(HCLGE_IMP_RESET_BIT))) {
2773                 dev_info(&hdev->pdev->dev,
2774                          "reset failed because IMP Reset is pending\n");
2775                 hclge_clear_reset_cause(hdev);
2776                 return false;
2777         } else if (hdev->reset_fail_cnt < MAX_RESET_FAIL_CNT) {
2778                 hdev->reset_fail_cnt++;
2779                 if (is_timeout) {
2780                         set_bit(hdev->reset_type, &hdev->reset_pending);
2781                         dev_info(&hdev->pdev->dev,
2782                                  "re-schedule to wait for hw reset done\n");
2783                         return true;
2784                 }
2785
2786                 dev_info(&hdev->pdev->dev, "Upgrade reset level\n");
2787                 hclge_clear_reset_cause(hdev);
2788                 mod_timer(&hdev->reset_timer,
2789                           jiffies + RESET_UPGRADE_DELAY_SEC * HZ);
2790
2791                 return false;
2792         }
2793
2794         hclge_clear_reset_cause(hdev);
2795         dev_err(&hdev->pdev->dev, "Reset fail!\n");
2796         return false;
2797 }
2798
2799 static int hclge_reset_prepare_up(struct hclge_dev *hdev)
2800 {
2801         int ret = 0;
2802
2803         switch (hdev->reset_type) {
2804         case HNAE3_FUNC_RESET:
2805                 /* fall through */
2806         case HNAE3_FLR_RESET:
2807                 ret = hclge_set_all_vf_rst(hdev, false);
2808                 break;
2809         default:
2810                 break;
2811         }
2812
2813         return ret;
2814 }
2815
2816 static void hclge_reset(struct hclge_dev *hdev)
2817 {
2818         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
2819         bool is_timeout = false;
2820         int ret;
2821
2822         /* Initialize ae_dev reset status as well, in case enet layer wants to
2823          * know if device is undergoing reset
2824          */
2825         ae_dev->reset_type = hdev->reset_type;
2826         hdev->reset_count++;
2827         /* perform reset of the stack & ae device for a client */
2828         ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT);
2829         if (ret)
2830                 goto err_reset;
2831
2832         ret = hclge_reset_prepare_down(hdev);
2833         if (ret)
2834                 goto err_reset;
2835
2836         rtnl_lock();
2837         ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2838         if (ret)
2839                 goto err_reset_lock;
2840
2841         rtnl_unlock();
2842
2843         ret = hclge_reset_prepare_wait(hdev);
2844         if (ret)
2845                 goto err_reset;
2846
2847         if (hclge_reset_wait(hdev)) {
2848                 is_timeout = true;
2849                 goto err_reset;
2850         }
2851
2852         ret = hclge_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT);
2853         if (ret)
2854                 goto err_reset;
2855
2856         rtnl_lock();
2857         ret = hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2858         if (ret)
2859                 goto err_reset_lock;
2860
2861         ret = hclge_reset_ae_dev(hdev->ae_dev);
2862         if (ret)
2863                 goto err_reset_lock;
2864
2865         ret = hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
2866         if (ret)
2867                 goto err_reset_lock;
2868
2869         ret = hclge_notify_client(hdev, HNAE3_RESTORE_CLIENT);
2870         if (ret)
2871                 goto err_reset_lock;
2872
2873         hclge_clear_reset_cause(hdev);
2874
2875         ret = hclge_reset_prepare_up(hdev);
2876         if (ret)
2877                 goto err_reset_lock;
2878
2879         ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2880         if (ret)
2881                 goto err_reset_lock;
2882
2883         rtnl_unlock();
2884
2885         ret = hclge_notify_roce_client(hdev, HNAE3_INIT_CLIENT);
2886         if (ret)
2887                 goto err_reset;
2888
2889         ret = hclge_notify_roce_client(hdev, HNAE3_UP_CLIENT);
2890         if (ret)
2891                 goto err_reset;
2892
2893         hdev->last_reset_time = jiffies;
2894         hdev->reset_fail_cnt = 0;
2895         ae_dev->reset_type = HNAE3_NONE_RESET;
2896
2897         return;
2898
2899 err_reset_lock:
2900         rtnl_unlock();
2901 err_reset:
2902         if (hclge_reset_err_handle(hdev, is_timeout))
2903                 hclge_reset_task_schedule(hdev);
2904 }
2905
2906 static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle)
2907 {
2908         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2909         struct hclge_dev *hdev = ae_dev->priv;
2910
2911         /* We might end up getting called broadly because of 2 below cases:
2912          * 1. Recoverable error was conveyed through APEI and only way to bring
2913          *    normalcy is to reset.
2914          * 2. A new reset request from the stack due to timeout
2915          *
2916          * For the first case,error event might not have ae handle available.
2917          * check if this is a new reset request and we are not here just because
2918          * last reset attempt did not succeed and watchdog hit us again. We will
2919          * know this if last reset request did not occur very recently (watchdog
2920          * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2921          * In case of new request we reset the "reset level" to PF reset.
2922          * And if it is a repeat reset request of the most recent one then we
2923          * want to make sure we throttle the reset request. Therefore, we will
2924          * not allow it again before 3*HZ times.
2925          */
2926         if (!handle)
2927                 handle = &hdev->vport[0].nic;
2928
2929         if (time_before(jiffies, (hdev->last_reset_time + 3 * HZ)))
2930                 return;
2931         else if (hdev->default_reset_request)
2932                 hdev->reset_level =
2933                         hclge_get_reset_level(hdev,
2934                                               &hdev->default_reset_request);
2935         else if (time_after(jiffies, (hdev->last_reset_time + 4 * 5 * HZ)))
2936                 hdev->reset_level = HNAE3_FUNC_RESET;
2937
2938         dev_info(&hdev->pdev->dev, "received reset event , reset type is %d",
2939                  hdev->reset_level);
2940
2941         /* request reset & schedule reset task */
2942         set_bit(hdev->reset_level, &hdev->reset_request);
2943         hclge_reset_task_schedule(hdev);
2944
2945         if (hdev->reset_level < HNAE3_GLOBAL_RESET)
2946                 hdev->reset_level++;
2947 }
2948
2949 static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
2950                                         enum hnae3_reset_type rst_type)
2951 {
2952         struct hclge_dev *hdev = ae_dev->priv;
2953
2954         set_bit(rst_type, &hdev->default_reset_request);
2955 }
2956
2957 static void hclge_reset_timer(struct timer_list *t)
2958 {
2959         struct hclge_dev *hdev = from_timer(hdev, t, reset_timer);
2960
2961         dev_info(&hdev->pdev->dev,
2962                  "triggering global reset in reset timer\n");
2963         set_bit(HNAE3_GLOBAL_RESET, &hdev->default_reset_request);
2964         hclge_reset_event(hdev->pdev, NULL);
2965 }
2966
2967 static void hclge_reset_subtask(struct hclge_dev *hdev)
2968 {
2969         /* check if there is any ongoing reset in the hardware. This status can
2970          * be checked from reset_pending. If there is then, we need to wait for
2971          * hardware to complete reset.
2972          *    a. If we are able to figure out in reasonable time that hardware
2973          *       has fully resetted then, we can proceed with driver, client
2974          *       reset.
2975          *    b. else, we can come back later to check this status so re-sched
2976          *       now.
2977          */
2978         hdev->last_reset_time = jiffies;
2979         hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
2980         if (hdev->reset_type != HNAE3_NONE_RESET)
2981                 hclge_reset(hdev);
2982
2983         /* check if we got any *new* reset requests to be honored */
2984         hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
2985         if (hdev->reset_type != HNAE3_NONE_RESET)
2986                 hclge_do_reset(hdev);
2987
2988         hdev->reset_type = HNAE3_NONE_RESET;
2989 }
2990
2991 static void hclge_reset_service_task(struct work_struct *work)
2992 {
2993         struct hclge_dev *hdev =
2994                 container_of(work, struct hclge_dev, rst_service_task);
2995
2996         if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2997                 return;
2998
2999         clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
3000
3001         hclge_reset_subtask(hdev);
3002
3003         clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
3004 }
3005
3006 static void hclge_mailbox_service_task(struct work_struct *work)
3007 {
3008         struct hclge_dev *hdev =
3009                 container_of(work, struct hclge_dev, mbx_service_task);
3010
3011         if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
3012                 return;
3013
3014         clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
3015
3016         hclge_mbx_handler(hdev);
3017
3018         clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
3019 }
3020
3021 static void hclge_update_vport_alive(struct hclge_dev *hdev)
3022 {
3023         int i;
3024
3025         /* start from vport 1 for PF is always alive */
3026         for (i = 1; i < hdev->num_alloc_vport; i++) {
3027                 struct hclge_vport *vport = &hdev->vport[i];
3028
3029                 if (time_after(jiffies, vport->last_active_jiffies + 8 * HZ))
3030                         clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
3031
3032                 /* If vf is not alive, set to default value */
3033                 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state))
3034                         vport->mps = HCLGE_MAC_DEFAULT_FRAME;
3035         }
3036 }
3037
3038 static void hclge_service_task(struct work_struct *work)
3039 {
3040         struct hclge_dev *hdev =
3041                 container_of(work, struct hclge_dev, service_task);
3042
3043         if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) {
3044                 hclge_update_stats_for_all(hdev);
3045                 hdev->hw_stats.stats_timer = 0;
3046         }
3047
3048         hclge_update_speed_duplex(hdev);
3049         hclge_update_link_status(hdev);
3050         hclge_update_vport_alive(hdev);
3051         hclge_service_complete(hdev);
3052 }
3053
3054 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
3055 {
3056         /* VF handle has no client */
3057         if (!handle->client)
3058                 return container_of(handle, struct hclge_vport, nic);
3059         else if (handle->client->type == HNAE3_CLIENT_ROCE)
3060                 return container_of(handle, struct hclge_vport, roce);
3061         else
3062                 return container_of(handle, struct hclge_vport, nic);
3063 }
3064
3065 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
3066                             struct hnae3_vector_info *vector_info)
3067 {
3068         struct hclge_vport *vport = hclge_get_vport(handle);
3069         struct hnae3_vector_info *vector = vector_info;
3070         struct hclge_dev *hdev = vport->back;
3071         int alloc = 0;
3072         int i, j;
3073
3074         vector_num = min(hdev->num_msi_left, vector_num);
3075
3076         for (j = 0; j < vector_num; j++) {
3077                 for (i = 1; i < hdev->num_msi; i++) {
3078                         if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
3079                                 vector->vector = pci_irq_vector(hdev->pdev, i);
3080                                 vector->io_addr = hdev->hw.io_base +
3081                                         HCLGE_VECTOR_REG_BASE +
3082                                         (i - 1) * HCLGE_VECTOR_REG_OFFSET +
3083                                         vport->vport_id *
3084                                         HCLGE_VECTOR_VF_OFFSET;
3085                                 hdev->vector_status[i] = vport->vport_id;
3086                                 hdev->vector_irq[i] = vector->vector;
3087
3088                                 vector++;
3089                                 alloc++;
3090
3091                                 break;
3092                         }
3093                 }
3094         }
3095         hdev->num_msi_left -= alloc;
3096         hdev->num_msi_used += alloc;
3097
3098         return alloc;
3099 }
3100
3101 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
3102 {
3103         int i;
3104
3105         for (i = 0; i < hdev->num_msi; i++)
3106                 if (vector == hdev->vector_irq[i])
3107                         return i;
3108
3109         return -EINVAL;
3110 }
3111
3112 static int hclge_put_vector(struct hnae3_handle *handle, int vector)
3113 {
3114         struct hclge_vport *vport = hclge_get_vport(handle);
3115         struct hclge_dev *hdev = vport->back;
3116         int vector_id;
3117
3118         vector_id = hclge_get_vector_index(hdev, vector);
3119         if (vector_id < 0) {
3120                 dev_err(&hdev->pdev->dev,
3121                         "Get vector index fail. vector_id =%d\n", vector_id);
3122                 return vector_id;
3123         }
3124
3125         hclge_free_vector(hdev, vector_id);
3126
3127         return 0;
3128 }
3129
3130 static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
3131 {
3132         return HCLGE_RSS_KEY_SIZE;
3133 }
3134
3135 static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
3136 {
3137         return HCLGE_RSS_IND_TBL_SIZE;
3138 }
3139
3140 static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
3141                                   const u8 hfunc, const u8 *key)
3142 {
3143         struct hclge_rss_config_cmd *req;
3144         struct hclge_desc desc;
3145         int key_offset;
3146         int key_size;
3147         int ret;
3148
3149         req = (struct hclge_rss_config_cmd *)desc.data;
3150
3151         for (key_offset = 0; key_offset < 3; key_offset++) {
3152                 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
3153                                            false);
3154
3155                 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
3156                 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
3157
3158                 if (key_offset == 2)
3159                         key_size =
3160                         HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
3161                 else
3162                         key_size = HCLGE_RSS_HASH_KEY_NUM;
3163
3164                 memcpy(req->hash_key,
3165                        key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
3166
3167                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3168                 if (ret) {
3169                         dev_err(&hdev->pdev->dev,
3170                                 "Configure RSS config fail, status = %d\n",
3171                                 ret);
3172                         return ret;
3173                 }
3174         }
3175         return 0;
3176 }
3177
3178 static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir)
3179 {
3180         struct hclge_rss_indirection_table_cmd *req;
3181         struct hclge_desc desc;
3182         int i, j;
3183         int ret;
3184
3185         req = (struct hclge_rss_indirection_table_cmd *)desc.data;
3186
3187         for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
3188                 hclge_cmd_setup_basic_desc
3189                         (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
3190
3191                 req->start_table_index =
3192                         cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
3193                 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
3194
3195                 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
3196                         req->rss_result[j] =
3197                                 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
3198
3199                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3200                 if (ret) {
3201                         dev_err(&hdev->pdev->dev,
3202                                 "Configure rss indir table fail,status = %d\n",
3203                                 ret);
3204                         return ret;
3205                 }
3206         }
3207         return 0;
3208 }
3209
3210 static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
3211                                  u16 *tc_size, u16 *tc_offset)
3212 {
3213         struct hclge_rss_tc_mode_cmd *req;
3214         struct hclge_desc desc;
3215         int ret;
3216         int i;
3217
3218         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
3219         req = (struct hclge_rss_tc_mode_cmd *)desc.data;
3220
3221         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
3222                 u16 mode = 0;
3223
3224                 hnae3_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
3225                 hnae3_set_field(mode, HCLGE_RSS_TC_SIZE_M,
3226                                 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
3227                 hnae3_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
3228                                 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
3229
3230                 req->rss_tc_mode[i] = cpu_to_le16(mode);
3231         }
3232
3233         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3234         if (ret)
3235                 dev_err(&hdev->pdev->dev,
3236                         "Configure rss tc mode fail, status = %d\n", ret);
3237
3238         return ret;
3239 }
3240
3241 static void hclge_get_rss_type(struct hclge_vport *vport)
3242 {
3243         if (vport->rss_tuple_sets.ipv4_tcp_en ||
3244             vport->rss_tuple_sets.ipv4_udp_en ||
3245             vport->rss_tuple_sets.ipv4_sctp_en ||
3246             vport->rss_tuple_sets.ipv6_tcp_en ||
3247             vport->rss_tuple_sets.ipv6_udp_en ||
3248             vport->rss_tuple_sets.ipv6_sctp_en)
3249                 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_L4;
3250         else if (vport->rss_tuple_sets.ipv4_fragment_en ||
3251                  vport->rss_tuple_sets.ipv6_fragment_en)
3252                 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_L3;
3253         else
3254                 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_NONE;
3255 }
3256
3257 static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
3258 {
3259         struct hclge_rss_input_tuple_cmd *req;
3260         struct hclge_desc desc;
3261         int ret;
3262
3263         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
3264
3265         req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3266
3267         /* Get the tuple cfg from pf */
3268         req->ipv4_tcp_en = hdev->vport[0].rss_tuple_sets.ipv4_tcp_en;
3269         req->ipv4_udp_en = hdev->vport[0].rss_tuple_sets.ipv4_udp_en;
3270         req->ipv4_sctp_en = hdev->vport[0].rss_tuple_sets.ipv4_sctp_en;
3271         req->ipv4_fragment_en = hdev->vport[0].rss_tuple_sets.ipv4_fragment_en;
3272         req->ipv6_tcp_en = hdev->vport[0].rss_tuple_sets.ipv6_tcp_en;
3273         req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en;
3274         req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en;
3275         req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en;
3276         hclge_get_rss_type(&hdev->vport[0]);
3277         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3278         if (ret)
3279                 dev_err(&hdev->pdev->dev,
3280                         "Configure rss input fail, status = %d\n", ret);
3281         return ret;
3282 }
3283
3284 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
3285                          u8 *key, u8 *hfunc)
3286 {
3287         struct hclge_vport *vport = hclge_get_vport(handle);
3288         int i;
3289
3290         /* Get hash algorithm */
3291         if (hfunc) {
3292                 switch (vport->rss_algo) {
3293                 case HCLGE_RSS_HASH_ALGO_TOEPLITZ:
3294                         *hfunc = ETH_RSS_HASH_TOP;
3295                         break;
3296                 case HCLGE_RSS_HASH_ALGO_SIMPLE:
3297                         *hfunc = ETH_RSS_HASH_XOR;
3298                         break;
3299                 default:
3300                         *hfunc = ETH_RSS_HASH_UNKNOWN;
3301                         break;
3302                 }
3303         }
3304
3305         /* Get the RSS Key required by the user */
3306         if (key)
3307                 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
3308
3309         /* Get indirect table */
3310         if (indir)
3311                 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3312                         indir[i] =  vport->rss_indirection_tbl[i];
3313
3314         return 0;
3315 }
3316
3317 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
3318                          const  u8 *key, const  u8 hfunc)
3319 {
3320         struct hclge_vport *vport = hclge_get_vport(handle);
3321         struct hclge_dev *hdev = vport->back;
3322         u8 hash_algo;
3323         int ret, i;
3324
3325         /* Set the RSS Hash Key if specififed by the user */
3326         if (key) {
3327                 switch (hfunc) {
3328                 case ETH_RSS_HASH_TOP:
3329                         hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3330                         break;
3331                 case ETH_RSS_HASH_XOR:
3332                         hash_algo = HCLGE_RSS_HASH_ALGO_SIMPLE;
3333                         break;
3334                 case ETH_RSS_HASH_NO_CHANGE:
3335                         hash_algo = vport->rss_algo;
3336                         break;
3337                 default:
3338                         return -EINVAL;
3339                 }
3340
3341                 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
3342                 if (ret)
3343                         return ret;
3344
3345                 /* Update the shadow RSS key with user specified qids */
3346                 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
3347                 vport->rss_algo = hash_algo;
3348         }
3349
3350         /* Update the shadow RSS table with user specified qids */
3351         for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3352                 vport->rss_indirection_tbl[i] = indir[i];
3353
3354         /* Update the hardware */
3355         return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl);
3356 }
3357
3358 static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
3359 {
3360         u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
3361
3362         if (nfc->data & RXH_L4_B_2_3)
3363                 hash_sets |= HCLGE_D_PORT_BIT;
3364         else
3365                 hash_sets &= ~HCLGE_D_PORT_BIT;
3366
3367         if (nfc->data & RXH_IP_SRC)
3368                 hash_sets |= HCLGE_S_IP_BIT;
3369         else
3370                 hash_sets &= ~HCLGE_S_IP_BIT;
3371
3372         if (nfc->data & RXH_IP_DST)
3373                 hash_sets |= HCLGE_D_IP_BIT;
3374         else
3375                 hash_sets &= ~HCLGE_D_IP_BIT;
3376
3377         if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
3378                 hash_sets |= HCLGE_V_TAG_BIT;
3379
3380         return hash_sets;
3381 }
3382
3383 static int hclge_set_rss_tuple(struct hnae3_handle *handle,
3384                                struct ethtool_rxnfc *nfc)
3385 {
3386         struct hclge_vport *vport = hclge_get_vport(handle);
3387         struct hclge_dev *hdev = vport->back;
3388         struct hclge_rss_input_tuple_cmd *req;
3389         struct hclge_desc desc;
3390         u8 tuple_sets;
3391         int ret;
3392
3393         if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3394                           RXH_L4_B_0_1 | RXH_L4_B_2_3))
3395                 return -EINVAL;
3396
3397         req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3398         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
3399
3400         req->ipv4_tcp_en = vport->rss_tuple_sets.ipv4_tcp_en;
3401         req->ipv4_udp_en = vport->rss_tuple_sets.ipv4_udp_en;
3402         req->ipv4_sctp_en = vport->rss_tuple_sets.ipv4_sctp_en;
3403         req->ipv4_fragment_en = vport->rss_tuple_sets.ipv4_fragment_en;
3404         req->ipv6_tcp_en = vport->rss_tuple_sets.ipv6_tcp_en;
3405         req->ipv6_udp_en = vport->rss_tuple_sets.ipv6_udp_en;
3406         req->ipv6_sctp_en = vport->rss_tuple_sets.ipv6_sctp_en;
3407         req->ipv6_fragment_en = vport->rss_tuple_sets.ipv6_fragment_en;
3408
3409         tuple_sets = hclge_get_rss_hash_bits(nfc);
3410         switch (nfc->flow_type) {
3411         case TCP_V4_FLOW:
3412                 req->ipv4_tcp_en = tuple_sets;
3413                 break;
3414         case TCP_V6_FLOW:
3415                 req->ipv6_tcp_en = tuple_sets;
3416                 break;
3417         case UDP_V4_FLOW:
3418                 req->ipv4_udp_en = tuple_sets;
3419                 break;
3420         case UDP_V6_FLOW:
3421                 req->ipv6_udp_en = tuple_sets;
3422                 break;
3423         case SCTP_V4_FLOW:
3424                 req->ipv4_sctp_en = tuple_sets;
3425                 break;
3426         case SCTP_V6_FLOW:
3427                 if ((nfc->data & RXH_L4_B_0_1) ||
3428                     (nfc->data & RXH_L4_B_2_3))
3429                         return -EINVAL;
3430
3431                 req->ipv6_sctp_en = tuple_sets;
3432                 break;
3433         case IPV4_FLOW:
3434                 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3435                 break;
3436         case IPV6_FLOW:
3437                 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3438                 break;
3439         default:
3440                 return -EINVAL;
3441         }
3442
3443         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3444         if (ret) {
3445                 dev_err(&hdev->pdev->dev,
3446                         "Set rss tuple fail, status = %d\n", ret);
3447                 return ret;
3448         }
3449
3450         vport->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
3451         vport->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
3452         vport->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
3453         vport->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
3454         vport->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
3455         vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
3456         vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
3457         vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
3458         hclge_get_rss_type(vport);
3459         return 0;
3460 }
3461
3462 static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3463                                struct ethtool_rxnfc *nfc)
3464 {
3465         struct hclge_vport *vport = hclge_get_vport(handle);
3466         u8 tuple_sets;
3467
3468         nfc->data = 0;
3469
3470         switch (nfc->flow_type) {
3471         case TCP_V4_FLOW:
3472                 tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en;
3473                 break;
3474         case UDP_V4_FLOW:
3475                 tuple_sets = vport->rss_tuple_sets.ipv4_udp_en;
3476                 break;
3477         case TCP_V6_FLOW:
3478                 tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en;
3479                 break;
3480         case UDP_V6_FLOW:
3481                 tuple_sets = vport->rss_tuple_sets.ipv6_udp_en;
3482                 break;
3483         case SCTP_V4_FLOW:
3484                 tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en;
3485                 break;
3486         case SCTP_V6_FLOW:
3487                 tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en;
3488                 break;
3489         case IPV4_FLOW:
3490         case IPV6_FLOW:
3491                 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3492                 break;
3493         default:
3494                 return -EINVAL;
3495         }
3496
3497         if (!tuple_sets)
3498                 return 0;
3499
3500         if (tuple_sets & HCLGE_D_PORT_BIT)
3501                 nfc->data |= RXH_L4_B_2_3;
3502         if (tuple_sets & HCLGE_S_PORT_BIT)
3503                 nfc->data |= RXH_L4_B_0_1;
3504         if (tuple_sets & HCLGE_D_IP_BIT)
3505                 nfc->data |= RXH_IP_DST;
3506         if (tuple_sets & HCLGE_S_IP_BIT)
3507                 nfc->data |= RXH_IP_SRC;
3508
3509         return 0;
3510 }
3511
3512 static int hclge_get_tc_size(struct hnae3_handle *handle)
3513 {
3514         struct hclge_vport *vport = hclge_get_vport(handle);
3515         struct hclge_dev *hdev = vport->back;
3516
3517         return hdev->rss_size_max;
3518 }
3519
3520 int hclge_rss_init_hw(struct hclge_dev *hdev)
3521 {
3522         struct hclge_vport *vport = hdev->vport;
3523         u8 *rss_indir = vport[0].rss_indirection_tbl;
3524         u16 rss_size = vport[0].alloc_rss_size;
3525         u8 *key = vport[0].rss_hash_key;
3526         u8 hfunc = vport[0].rss_algo;
3527         u16 tc_offset[HCLGE_MAX_TC_NUM];
3528         u16 tc_valid[HCLGE_MAX_TC_NUM];
3529         u16 tc_size[HCLGE_MAX_TC_NUM];
3530         u16 roundup_size;
3531         int i, ret;
3532
3533         ret = hclge_set_rss_indir_table(hdev, rss_indir);
3534         if (ret)
3535                 return ret;
3536
3537         ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3538         if (ret)
3539                 return ret;
3540
3541         ret = hclge_set_rss_input_tuple(hdev);
3542         if (ret)
3543                 return ret;
3544
3545         /* Each TC have the same queue size, and tc_size set to hardware is
3546          * the log2 of roundup power of two of rss_size, the acutal queue
3547          * size is limited by indirection table.
3548          */
3549         if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3550                 dev_err(&hdev->pdev->dev,
3551                         "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3552                         rss_size);
3553                 return -EINVAL;
3554         }
3555
3556         roundup_size = roundup_pow_of_two(rss_size);
3557         roundup_size = ilog2(roundup_size);
3558
3559         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
3560                 tc_valid[i] = 0;
3561
3562                 if (!(hdev->hw_tc_map & BIT(i)))
3563                         continue;
3564
3565                 tc_valid[i] = 1;
3566                 tc_size[i] = roundup_size;
3567                 tc_offset[i] = rss_size * i;
3568         }
3569
3570         return hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3571 }
3572
3573 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev)
3574 {
3575         struct hclge_vport *vport = hdev->vport;
3576         int i, j;
3577
3578         for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3579                 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3580                         vport[j].rss_indirection_tbl[i] =
3581                                 i % vport[j].alloc_rss_size;
3582         }
3583 }
3584
3585 static void hclge_rss_init_cfg(struct hclge_dev *hdev)
3586 {
3587         struct hclge_vport *vport = hdev->vport;
3588         int i;
3589
3590         for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
3591                 vport[i].rss_tuple_sets.ipv4_tcp_en =
3592                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3593                 vport[i].rss_tuple_sets.ipv4_udp_en =
3594                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3595                 vport[i].rss_tuple_sets.ipv4_sctp_en =
3596                         HCLGE_RSS_INPUT_TUPLE_SCTP;
3597                 vport[i].rss_tuple_sets.ipv4_fragment_en =
3598                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3599                 vport[i].rss_tuple_sets.ipv6_tcp_en =
3600                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3601                 vport[i].rss_tuple_sets.ipv6_udp_en =
3602                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3603                 vport[i].rss_tuple_sets.ipv6_sctp_en =
3604                         HCLGE_RSS_INPUT_TUPLE_SCTP;
3605                 vport[i].rss_tuple_sets.ipv6_fragment_en =
3606                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3607
3608                 vport[i].rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3609
3610                 netdev_rss_key_fill(vport[i].rss_hash_key, HCLGE_RSS_KEY_SIZE);
3611         }
3612
3613         hclge_rss_indir_init_cfg(hdev);
3614 }
3615
3616 int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3617                                 int vector_id, bool en,
3618                                 struct hnae3_ring_chain_node *ring_chain)
3619 {
3620         struct hclge_dev *hdev = vport->back;
3621         struct hnae3_ring_chain_node *node;
3622         struct hclge_desc desc;
3623         struct hclge_ctrl_vector_chain_cmd *req
3624                 = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3625         enum hclge_cmd_status status;
3626         enum hclge_opcode_type op;
3627         u16 tqp_type_and_id;
3628         int i;
3629
3630         op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
3631         hclge_cmd_setup_basic_desc(&desc, op, false);
3632         req->int_vector_id = vector_id;
3633
3634         i = 0;
3635         for (node = ring_chain; node; node = node->next) {
3636                 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
3637                 hnae3_set_field(tqp_type_and_id,  HCLGE_INT_TYPE_M,
3638                                 HCLGE_INT_TYPE_S,
3639                                 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B));
3640                 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3641                                 HCLGE_TQP_ID_S, node->tqp_index);
3642                 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
3643                                 HCLGE_INT_GL_IDX_S,
3644                                 hnae3_get_field(node->int_gl_idx,
3645                                                 HNAE3_RING_GL_IDX_M,
3646                                                 HNAE3_RING_GL_IDX_S));
3647                 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
3648                 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3649                         req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
3650                         req->vfid = vport->vport_id;
3651
3652                         status = hclge_cmd_send(&hdev->hw, &desc, 1);
3653                         if (status) {
3654                                 dev_err(&hdev->pdev->dev,
3655                                         "Map TQP fail, status is %d.\n",
3656                                         status);
3657                                 return -EIO;
3658                         }
3659                         i = 0;
3660
3661                         hclge_cmd_setup_basic_desc(&desc,
3662                                                    op,
3663                                                    false);
3664                         req->int_vector_id = vector_id;
3665                 }
3666         }
3667
3668         if (i > 0) {
3669                 req->int_cause_num = i;
3670                 req->vfid = vport->vport_id;
3671                 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3672                 if (status) {
3673                         dev_err(&hdev->pdev->dev,
3674                                 "Map TQP fail, status is %d.\n", status);
3675                         return -EIO;
3676                 }
3677         }
3678
3679         return 0;
3680 }
3681
3682 static int hclge_map_ring_to_vector(struct hnae3_handle *handle,
3683                                     int vector,
3684                                     struct hnae3_ring_chain_node *ring_chain)
3685 {
3686         struct hclge_vport *vport = hclge_get_vport(handle);
3687         struct hclge_dev *hdev = vport->back;
3688         int vector_id;
3689
3690         vector_id = hclge_get_vector_index(hdev, vector);
3691         if (vector_id < 0) {
3692                 dev_err(&hdev->pdev->dev,
3693                         "Get vector index fail. vector_id =%d\n", vector_id);
3694                 return vector_id;
3695         }
3696
3697         return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
3698 }
3699
3700 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle,
3701                                        int vector,
3702                                        struct hnae3_ring_chain_node *ring_chain)
3703 {
3704         struct hclge_vport *vport = hclge_get_vport(handle);
3705         struct hclge_dev *hdev = vport->back;
3706         int vector_id, ret;
3707
3708         if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
3709                 return 0;
3710
3711         vector_id = hclge_get_vector_index(hdev, vector);
3712         if (vector_id < 0) {
3713                 dev_err(&handle->pdev->dev,
3714                         "Get vector index fail. ret =%d\n", vector_id);
3715                 return vector_id;
3716         }
3717
3718         ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
3719         if (ret)
3720                 dev_err(&handle->pdev->dev,
3721                         "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3722                         vector_id,
3723                         ret);
3724
3725         return ret;
3726 }
3727
3728 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3729                                struct hclge_promisc_param *param)
3730 {
3731         struct hclge_promisc_cfg_cmd *req;
3732         struct hclge_desc desc;
3733         int ret;
3734
3735         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3736
3737         req = (struct hclge_promisc_cfg_cmd *)desc.data;
3738         req->vf_id = param->vf_id;
3739
3740         /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on
3741          * pdev revision(0x20), new revision support them. The
3742          * value of this two fields will not return error when driver
3743          * send command to fireware in revision(0x20).
3744          */
3745         req->flag = (param->enable << HCLGE_PROMISC_EN_B) |
3746                 HCLGE_PROMISC_TX_EN_B | HCLGE_PROMISC_RX_EN_B;
3747
3748         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3749         if (ret)
3750                 dev_err(&hdev->pdev->dev,
3751                         "Set promisc mode fail, status is %d.\n", ret);
3752
3753         return ret;
3754 }
3755
3756 void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3757                               bool en_mc, bool en_bc, int vport_id)
3758 {
3759         if (!param)
3760                 return;
3761
3762         memset(param, 0, sizeof(struct hclge_promisc_param));
3763         if (en_uc)
3764                 param->enable = HCLGE_PROMISC_EN_UC;
3765         if (en_mc)
3766                 param->enable |= HCLGE_PROMISC_EN_MC;
3767         if (en_bc)
3768                 param->enable |= HCLGE_PROMISC_EN_BC;
3769         param->vf_id = vport_id;
3770 }
3771
3772 static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
3773                                   bool en_mc_pmc)
3774 {
3775         struct hclge_vport *vport = hclge_get_vport(handle);
3776         struct hclge_dev *hdev = vport->back;
3777         struct hclge_promisc_param param;
3778
3779         hclge_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, true,
3780                                  vport->vport_id);
3781         return hclge_cmd_set_promisc_mode(hdev, &param);
3782 }
3783
3784 static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode)
3785 {
3786         struct hclge_get_fd_mode_cmd *req;
3787         struct hclge_desc desc;
3788         int ret;
3789
3790         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_MODE_CTRL, true);
3791
3792         req = (struct hclge_get_fd_mode_cmd *)desc.data;
3793
3794         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3795         if (ret) {
3796                 dev_err(&hdev->pdev->dev, "get fd mode fail, ret=%d\n", ret);
3797                 return ret;
3798         }
3799
3800         *fd_mode = req->mode;
3801
3802         return ret;
3803 }
3804
3805 static int hclge_get_fd_allocation(struct hclge_dev *hdev,
3806                                    u32 *stage1_entry_num,
3807                                    u32 *stage2_entry_num,
3808                                    u16 *stage1_counter_num,
3809                                    u16 *stage2_counter_num)
3810 {
3811         struct hclge_get_fd_allocation_cmd *req;
3812         struct hclge_desc desc;
3813         int ret;
3814
3815         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_GET_ALLOCATION, true);
3816
3817         req = (struct hclge_get_fd_allocation_cmd *)desc.data;
3818
3819         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3820         if (ret) {
3821                 dev_err(&hdev->pdev->dev, "query fd allocation fail, ret=%d\n",
3822                         ret);
3823                 return ret;
3824         }
3825
3826         *stage1_entry_num = le32_to_cpu(req->stage1_entry_num);
3827         *stage2_entry_num = le32_to_cpu(req->stage2_entry_num);
3828         *stage1_counter_num = le16_to_cpu(req->stage1_counter_num);
3829         *stage2_counter_num = le16_to_cpu(req->stage2_counter_num);
3830
3831         return ret;
3832 }
3833
3834 static int hclge_set_fd_key_config(struct hclge_dev *hdev, int stage_num)
3835 {
3836         struct hclge_set_fd_key_config_cmd *req;
3837         struct hclge_fd_key_cfg *stage;
3838         struct hclge_desc desc;
3839         int ret;
3840
3841         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_KEY_CONFIG, false);
3842
3843         req = (struct hclge_set_fd_key_config_cmd *)desc.data;
3844         stage = &hdev->fd_cfg.key_cfg[stage_num];
3845         req->stage = stage_num;
3846         req->key_select = stage->key_sel;
3847         req->inner_sipv6_word_en = stage->inner_sipv6_word_en;
3848         req->inner_dipv6_word_en = stage->inner_dipv6_word_en;
3849         req->outer_sipv6_word_en = stage->outer_sipv6_word_en;
3850         req->outer_dipv6_word_en = stage->outer_dipv6_word_en;
3851         req->tuple_mask = cpu_to_le32(~stage->tuple_active);
3852         req->meta_data_mask = cpu_to_le32(~stage->meta_data_active);
3853
3854         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3855         if (ret)
3856                 dev_err(&hdev->pdev->dev, "set fd key fail, ret=%d\n", ret);
3857
3858         return ret;
3859 }
3860
3861 static int hclge_init_fd_config(struct hclge_dev *hdev)
3862 {
3863 #define LOW_2_WORDS             0x03
3864         struct hclge_fd_key_cfg *key_cfg;
3865         int ret;
3866
3867         if (!hnae3_dev_fd_supported(hdev))
3868                 return 0;
3869
3870         ret = hclge_get_fd_mode(hdev, &hdev->fd_cfg.fd_mode);
3871         if (ret)
3872                 return ret;
3873
3874         switch (hdev->fd_cfg.fd_mode) {
3875         case HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1:
3876                 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH;
3877                 break;
3878         case HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1:
3879                 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH / 2;
3880                 break;
3881         default:
3882                 dev_err(&hdev->pdev->dev,
3883                         "Unsupported flow director mode %d\n",
3884                         hdev->fd_cfg.fd_mode);
3885                 return -EOPNOTSUPP;
3886         }
3887
3888         hdev->fd_cfg.fd_en = true;
3889         hdev->fd_cfg.proto_support =
3890                 TCP_V4_FLOW | UDP_V4_FLOW | SCTP_V4_FLOW | TCP_V6_FLOW |
3891                 UDP_V6_FLOW | SCTP_V6_FLOW | IPV4_USER_FLOW | IPV6_USER_FLOW;
3892         key_cfg = &hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1];
3893         key_cfg->key_sel = HCLGE_FD_KEY_BASE_ON_TUPLE,
3894         key_cfg->inner_sipv6_word_en = LOW_2_WORDS;
3895         key_cfg->inner_dipv6_word_en = LOW_2_WORDS;
3896         key_cfg->outer_sipv6_word_en = 0;
3897         key_cfg->outer_dipv6_word_en = 0;
3898
3899         key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) |
3900                                 BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) |
3901                                 BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) |
3902                                 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
3903
3904         /* If use max 400bit key, we can support tuples for ether type */
3905         if (hdev->fd_cfg.max_key_length == MAX_KEY_LENGTH) {
3906                 hdev->fd_cfg.proto_support |= ETHER_FLOW;
3907                 key_cfg->tuple_active |=
3908                                 BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC);
3909         }
3910
3911         /* roce_type is used to filter roce frames
3912          * dst_vport is used to specify the rule
3913          */
3914         key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT);
3915
3916         ret = hclge_get_fd_allocation(hdev,
3917                                       &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1],
3918                                       &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2],
3919                                       &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1],
3920                                       &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]);
3921         if (ret)
3922                 return ret;
3923
3924         return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1);
3925 }
3926
3927 static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x,
3928                                 int loc, u8 *key, bool is_add)
3929 {
3930         struct hclge_fd_tcam_config_1_cmd *req1;
3931         struct hclge_fd_tcam_config_2_cmd *req2;
3932         struct hclge_fd_tcam_config_3_cmd *req3;
3933         struct hclge_desc desc[3];
3934         int ret;
3935
3936         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false);
3937         desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3938         hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false);
3939         desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3940         hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false);
3941
3942         req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data;
3943         req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data;
3944         req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data;
3945
3946         req1->stage = stage;
3947         req1->xy_sel = sel_x ? 1 : 0;
3948         hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0);
3949         req1->index = cpu_to_le32(loc);
3950         req1->entry_vld = sel_x ? is_add : 0;
3951
3952         if (key) {
3953                 memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data));
3954                 memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)],
3955                        sizeof(req2->tcam_data));
3956                 memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) +
3957                        sizeof(req2->tcam_data)], sizeof(req3->tcam_data));
3958         }
3959
3960         ret = hclge_cmd_send(&hdev->hw, desc, 3);
3961         if (ret)
3962                 dev_err(&hdev->pdev->dev,
3963                         "config tcam key fail, ret=%d\n",
3964                         ret);
3965
3966         return ret;
3967 }
3968
3969 static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc,
3970                               struct hclge_fd_ad_data *action)
3971 {
3972         struct hclge_fd_ad_config_cmd *req;
3973         struct hclge_desc desc;
3974         u64 ad_data = 0;
3975         int ret;
3976
3977         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false);
3978
3979         req = (struct hclge_fd_ad_config_cmd *)desc.data;
3980         req->index = cpu_to_le32(loc);
3981         req->stage = stage;
3982
3983         hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B,
3984                       action->write_rule_id_to_bd);
3985         hnae3_set_field(ad_data, HCLGE_FD_AD_RULE_ID_M, HCLGE_FD_AD_RULE_ID_S,
3986                         action->rule_id);
3987         ad_data <<= 32;
3988         hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet);
3989         hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B,
3990                       action->forward_to_direct_queue);
3991         hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S,
3992                         action->queue_id);
3993         hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter);
3994         hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M,
3995                         HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id);
3996         hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage);
3997         hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S,
3998                         action->counter_id);
3999
4000         req->ad_data = cpu_to_le64(ad_data);
4001         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4002         if (ret)
4003                 dev_err(&hdev->pdev->dev, "fd ad config fail, ret=%d\n", ret);
4004
4005         return ret;
4006 }
4007
4008 static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y,
4009                                    struct hclge_fd_rule *rule)
4010 {
4011         u16 tmp_x_s, tmp_y_s;
4012         u32 tmp_x_l, tmp_y_l;
4013         int i;
4014
4015         if (rule->unused_tuple & tuple_bit)
4016                 return true;
4017
4018         switch (tuple_bit) {
4019         case 0:
4020                 return false;
4021         case BIT(INNER_DST_MAC):
4022                 for (i = 0; i < 6; i++) {
4023                         calc_x(key_x[5 - i], rule->tuples.dst_mac[i],
4024                                rule->tuples_mask.dst_mac[i]);
4025                         calc_y(key_y[5 - i], rule->tuples.dst_mac[i],
4026                                rule->tuples_mask.dst_mac[i]);
4027                 }
4028
4029                 return true;
4030         case BIT(INNER_SRC_MAC):
4031                 for (i = 0; i < 6; i++) {
4032                         calc_x(key_x[5 - i], rule->tuples.src_mac[i],
4033                                rule->tuples.src_mac[i]);
4034                         calc_y(key_y[5 - i], rule->tuples.src_mac[i],
4035                                rule->tuples.src_mac[i]);
4036                 }
4037
4038                 return true;
4039         case BIT(INNER_VLAN_TAG_FST):
4040                 calc_x(tmp_x_s, rule->tuples.vlan_tag1,
4041                        rule->tuples_mask.vlan_tag1);
4042                 calc_y(tmp_y_s, rule->tuples.vlan_tag1,
4043                        rule->tuples_mask.vlan_tag1);
4044                 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
4045                 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
4046
4047                 return true;
4048         case BIT(INNER_ETH_TYPE):
4049                 calc_x(tmp_x_s, rule->tuples.ether_proto,
4050                        rule->tuples_mask.ether_proto);
4051                 calc_y(tmp_y_s, rule->tuples.ether_proto,
4052                        rule->tuples_mask.ether_proto);
4053                 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
4054                 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
4055
4056                 return true;
4057         case BIT(INNER_IP_TOS):
4058                 calc_x(*key_x, rule->tuples.ip_tos, rule->tuples_mask.ip_tos);
4059                 calc_y(*key_y, rule->tuples.ip_tos, rule->tuples_mask.ip_tos);
4060
4061                 return true;
4062         case BIT(INNER_IP_PROTO):
4063                 calc_x(*key_x, rule->tuples.ip_proto,
4064                        rule->tuples_mask.ip_proto);
4065                 calc_y(*key_y, rule->tuples.ip_proto,
4066                        rule->tuples_mask.ip_proto);
4067
4068                 return true;
4069         case BIT(INNER_SRC_IP):
4070                 calc_x(tmp_x_l, rule->tuples.src_ip[3],
4071                        rule->tuples_mask.src_ip[3]);
4072                 calc_y(tmp_y_l, rule->tuples.src_ip[3],
4073                        rule->tuples_mask.src_ip[3]);
4074                 *(__le32 *)key_x = cpu_to_le32(tmp_x_l);
4075                 *(__le32 *)key_y = cpu_to_le32(tmp_y_l);
4076
4077                 return true;
4078         case BIT(INNER_DST_IP):
4079                 calc_x(tmp_x_l, rule->tuples.dst_ip[3],
4080                        rule->tuples_mask.dst_ip[3]);
4081                 calc_y(tmp_y_l, rule->tuples.dst_ip[3],
4082                        rule->tuples_mask.dst_ip[3]);
4083                 *(__le32 *)key_x = cpu_to_le32(tmp_x_l);
4084                 *(__le32 *)key_y = cpu_to_le32(tmp_y_l);
4085
4086                 return true;
4087         case BIT(INNER_SRC_PORT):
4088                 calc_x(tmp_x_s, rule->tuples.src_port,
4089                        rule->tuples_mask.src_port);
4090                 calc_y(tmp_y_s, rule->tuples.src_port,
4091                        rule->tuples_mask.src_port);
4092                 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
4093                 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
4094
4095                 return true;
4096         case BIT(INNER_DST_PORT):
4097                 calc_x(tmp_x_s, rule->tuples.dst_port,
4098                        rule->tuples_mask.dst_port);
4099                 calc_y(tmp_y_s, rule->tuples.dst_port,
4100                        rule->tuples_mask.dst_port);
4101                 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
4102                 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
4103
4104                 return true;
4105         default:
4106                 return false;
4107         }
4108 }
4109
4110 static u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id,
4111                                  u8 vf_id, u8 network_port_id)
4112 {
4113         u32 port_number = 0;
4114
4115         if (port_type == HOST_PORT) {
4116                 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S,
4117                                 pf_id);
4118                 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S,
4119                                 vf_id);
4120                 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT);
4121         } else {
4122                 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M,
4123                                 HCLGE_NETWORK_PORT_ID_S, network_port_id);
4124                 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT);
4125         }
4126
4127         return port_number;
4128 }
4129
4130 static void hclge_fd_convert_meta_data(struct hclge_fd_key_cfg *key_cfg,
4131                                        __le32 *key_x, __le32 *key_y,
4132                                        struct hclge_fd_rule *rule)
4133 {
4134         u32 tuple_bit, meta_data = 0, tmp_x, tmp_y, port_number;
4135         u8 cur_pos = 0, tuple_size, shift_bits;
4136         int i;
4137
4138         for (i = 0; i < MAX_META_DATA; i++) {
4139                 tuple_size = meta_data_key_info[i].key_length;
4140                 tuple_bit = key_cfg->meta_data_active & BIT(i);
4141
4142                 switch (tuple_bit) {
4143                 case BIT(ROCE_TYPE):
4144                         hnae3_set_bit(meta_data, cur_pos, NIC_PACKET);
4145                         cur_pos += tuple_size;
4146                         break;
4147                 case BIT(DST_VPORT):
4148                         port_number = hclge_get_port_number(HOST_PORT, 0,
4149                                                             rule->vf_id, 0);
4150                         hnae3_set_field(meta_data,
4151                                         GENMASK(cur_pos + tuple_size, cur_pos),
4152                                         cur_pos, port_number);
4153                         cur_pos += tuple_size;
4154                         break;
4155                 default:
4156                         break;
4157                 }
4158         }
4159
4160         calc_x(tmp_x, meta_data, 0xFFFFFFFF);
4161         calc_y(tmp_y, meta_data, 0xFFFFFFFF);
4162         shift_bits = sizeof(meta_data) * 8 - cur_pos;
4163
4164         *key_x = cpu_to_le32(tmp_x << shift_bits);
4165         *key_y = cpu_to_le32(tmp_y << shift_bits);
4166 }
4167
4168 /* A complete key is combined with meta data key and tuple key.
4169  * Meta data key is stored at the MSB region, and tuple key is stored at
4170  * the LSB region, unused bits will be filled 0.
4171  */
4172 static int hclge_config_key(struct hclge_dev *hdev, u8 stage,
4173                             struct hclge_fd_rule *rule)
4174 {
4175         struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage];
4176         u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES];
4177         u8 *cur_key_x, *cur_key_y;
4178         int i, ret, tuple_size;
4179         u8 meta_data_region;
4180
4181         memset(key_x, 0, sizeof(key_x));
4182         memset(key_y, 0, sizeof(key_y));
4183         cur_key_x = key_x;
4184         cur_key_y = key_y;
4185
4186         for (i = 0 ; i < MAX_TUPLE; i++) {
4187                 bool tuple_valid;
4188                 u32 check_tuple;
4189
4190                 tuple_size = tuple_key_info[i].key_length / 8;
4191                 check_tuple = key_cfg->tuple_active & BIT(i);
4192
4193                 tuple_valid = hclge_fd_convert_tuple(check_tuple, cur_key_x,
4194                                                      cur_key_y, rule);
4195                 if (tuple_valid) {
4196                         cur_key_x += tuple_size;
4197                         cur_key_y += tuple_size;
4198                 }
4199         }
4200
4201         meta_data_region = hdev->fd_cfg.max_key_length / 8 -
4202                         MAX_META_DATA_LENGTH / 8;
4203
4204         hclge_fd_convert_meta_data(key_cfg,
4205                                    (__le32 *)(key_x + meta_data_region),
4206                                    (__le32 *)(key_y + meta_data_region),
4207                                    rule);
4208
4209         ret = hclge_fd_tcam_config(hdev, stage, false, rule->location, key_y,
4210                                    true);
4211         if (ret) {
4212                 dev_err(&hdev->pdev->dev,
4213                         "fd key_y config fail, loc=%d, ret=%d\n",
4214                         rule->queue_id, ret);
4215                 return ret;
4216         }
4217
4218         ret = hclge_fd_tcam_config(hdev, stage, true, rule->location, key_x,
4219                                    true);
4220         if (ret)
4221                 dev_err(&hdev->pdev->dev,
4222                         "fd key_x config fail, loc=%d, ret=%d\n",
4223                         rule->queue_id, ret);
4224         return ret;
4225 }
4226
4227 static int hclge_config_action(struct hclge_dev *hdev, u8 stage,
4228                                struct hclge_fd_rule *rule)
4229 {
4230         struct hclge_fd_ad_data ad_data;
4231
4232         ad_data.ad_id = rule->location;
4233
4234         if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) {
4235                 ad_data.drop_packet = true;
4236                 ad_data.forward_to_direct_queue = false;
4237                 ad_data.queue_id = 0;
4238         } else {
4239                 ad_data.drop_packet = false;
4240                 ad_data.forward_to_direct_queue = true;
4241                 ad_data.queue_id = rule->queue_id;
4242         }
4243
4244         ad_data.use_counter = false;
4245         ad_data.counter_id = 0;
4246
4247         ad_data.use_next_stage = false;
4248         ad_data.next_input_key = 0;
4249
4250         ad_data.write_rule_id_to_bd = true;
4251         ad_data.rule_id = rule->location;
4252
4253         return hclge_fd_ad_config(hdev, stage, ad_data.ad_id, &ad_data);
4254 }
4255
4256 static int hclge_fd_check_spec(struct hclge_dev *hdev,
4257                                struct ethtool_rx_flow_spec *fs, u32 *unused)
4258 {
4259         struct ethtool_tcpip4_spec *tcp_ip4_spec;
4260         struct ethtool_usrip4_spec *usr_ip4_spec;
4261         struct ethtool_tcpip6_spec *tcp_ip6_spec;
4262         struct ethtool_usrip6_spec *usr_ip6_spec;
4263         struct ethhdr *ether_spec;
4264
4265         if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1])
4266                 return -EINVAL;
4267
4268         if (!(fs->flow_type & hdev->fd_cfg.proto_support))
4269                 return -EOPNOTSUPP;
4270
4271         if ((fs->flow_type & FLOW_EXT) &&
4272             (fs->h_ext.data[0] != 0 || fs->h_ext.data[1] != 0)) {
4273                 dev_err(&hdev->pdev->dev, "user-def bytes are not supported\n");
4274                 return -EOPNOTSUPP;
4275         }
4276
4277         switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
4278         case SCTP_V4_FLOW:
4279         case TCP_V4_FLOW:
4280         case UDP_V4_FLOW:
4281                 tcp_ip4_spec = &fs->h_u.tcp_ip4_spec;
4282                 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC);
4283
4284                 if (!tcp_ip4_spec->ip4src)
4285                         *unused |= BIT(INNER_SRC_IP);
4286
4287                 if (!tcp_ip4_spec->ip4dst)
4288                         *unused |= BIT(INNER_DST_IP);
4289
4290                 if (!tcp_ip4_spec->psrc)
4291                         *unused |= BIT(INNER_SRC_PORT);
4292
4293                 if (!tcp_ip4_spec->pdst)
4294                         *unused |= BIT(INNER_DST_PORT);
4295
4296                 if (!tcp_ip4_spec->tos)
4297                         *unused |= BIT(INNER_IP_TOS);
4298
4299                 break;
4300         case IP_USER_FLOW:
4301                 usr_ip4_spec = &fs->h_u.usr_ip4_spec;
4302                 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
4303                         BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
4304
4305                 if (!usr_ip4_spec->ip4src)
4306                         *unused |= BIT(INNER_SRC_IP);
4307
4308                 if (!usr_ip4_spec->ip4dst)
4309                         *unused |= BIT(INNER_DST_IP);
4310
4311                 if (!usr_ip4_spec->tos)
4312                         *unused |= BIT(INNER_IP_TOS);
4313
4314                 if (!usr_ip4_spec->proto)
4315                         *unused |= BIT(INNER_IP_PROTO);
4316
4317                 if (usr_ip4_spec->l4_4_bytes)
4318                         return -EOPNOTSUPP;
4319
4320                 if (usr_ip4_spec->ip_ver != ETH_RX_NFC_IP4)
4321                         return -EOPNOTSUPP;
4322
4323                 break;
4324         case SCTP_V6_FLOW:
4325         case TCP_V6_FLOW:
4326         case UDP_V6_FLOW:
4327                 tcp_ip6_spec = &fs->h_u.tcp_ip6_spec;
4328                 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
4329                         BIT(INNER_IP_TOS);
4330
4331                 if (!tcp_ip6_spec->ip6src[0] && !tcp_ip6_spec->ip6src[1] &&
4332                     !tcp_ip6_spec->ip6src[2] && !tcp_ip6_spec->ip6src[3])
4333                         *unused |= BIT(INNER_SRC_IP);
4334
4335                 if (!tcp_ip6_spec->ip6dst[0] && !tcp_ip6_spec->ip6dst[1] &&
4336                     !tcp_ip6_spec->ip6dst[2] && !tcp_ip6_spec->ip6dst[3])
4337                         *unused |= BIT(INNER_DST_IP);
4338
4339                 if (!tcp_ip6_spec->psrc)
4340                         *unused |= BIT(INNER_SRC_PORT);
4341
4342                 if (!tcp_ip6_spec->pdst)
4343                         *unused |= BIT(INNER_DST_PORT);
4344
4345                 if (tcp_ip6_spec->tclass)
4346                         return -EOPNOTSUPP;
4347
4348                 break;
4349         case IPV6_USER_FLOW:
4350                 usr_ip6_spec = &fs->h_u.usr_ip6_spec;
4351                 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
4352                         BIT(INNER_IP_TOS) | BIT(INNER_SRC_PORT) |
4353                         BIT(INNER_DST_PORT);
4354
4355                 if (!usr_ip6_spec->ip6src[0] && !usr_ip6_spec->ip6src[1] &&
4356                     !usr_ip6_spec->ip6src[2] && !usr_ip6_spec->ip6src[3])
4357                         *unused |= BIT(INNER_SRC_IP);
4358
4359                 if (!usr_ip6_spec->ip6dst[0] && !usr_ip6_spec->ip6dst[1] &&
4360                     !usr_ip6_spec->ip6dst[2] && !usr_ip6_spec->ip6dst[3])
4361                         *unused |= BIT(INNER_DST_IP);
4362
4363                 if (!usr_ip6_spec->l4_proto)
4364                         *unused |= BIT(INNER_IP_PROTO);
4365
4366                 if (usr_ip6_spec->tclass)
4367                         return -EOPNOTSUPP;
4368
4369                 if (usr_ip6_spec->l4_4_bytes)
4370                         return -EOPNOTSUPP;
4371
4372                 break;
4373         case ETHER_FLOW:
4374                 ether_spec = &fs->h_u.ether_spec;
4375                 *unused |= BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) |
4376                         BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT) |
4377                         BIT(INNER_IP_TOS) | BIT(INNER_IP_PROTO);
4378
4379                 if (is_zero_ether_addr(ether_spec->h_source))
4380                         *unused |= BIT(INNER_SRC_MAC);
4381
4382                 if (is_zero_ether_addr(ether_spec->h_dest))
4383                         *unused |= BIT(INNER_DST_MAC);
4384
4385                 if (!ether_spec->h_proto)
4386                         *unused |= BIT(INNER_ETH_TYPE);
4387
4388                 break;
4389         default:
4390                 return -EOPNOTSUPP;
4391         }
4392
4393         if ((fs->flow_type & FLOW_EXT)) {
4394                 if (fs->h_ext.vlan_etype)
4395                         return -EOPNOTSUPP;
4396                 if (!fs->h_ext.vlan_tci)
4397                         *unused |= BIT(INNER_VLAN_TAG_FST);
4398
4399                 if (fs->m_ext.vlan_tci) {
4400                         if (be16_to_cpu(fs->h_ext.vlan_tci) >= VLAN_N_VID)
4401                                 return -EINVAL;
4402                 }
4403         } else {
4404                 *unused |= BIT(INNER_VLAN_TAG_FST);
4405         }
4406
4407         if (fs->flow_type & FLOW_MAC_EXT) {
4408                 if (!(hdev->fd_cfg.proto_support & ETHER_FLOW))
4409                         return -EOPNOTSUPP;
4410
4411                 if (is_zero_ether_addr(fs->h_ext.h_dest))
4412                         *unused |= BIT(INNER_DST_MAC);
4413                 else
4414                         *unused &= ~(BIT(INNER_DST_MAC));
4415         }
4416
4417         return 0;
4418 }
4419
4420 static bool hclge_fd_rule_exist(struct hclge_dev *hdev, u16 location)
4421 {
4422         struct hclge_fd_rule *rule = NULL;
4423         struct hlist_node *node2;
4424
4425         hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) {
4426                 if (rule->location >= location)
4427                         break;
4428         }
4429
4430         return  rule && rule->location == location;
4431 }
4432
4433 static int hclge_fd_update_rule_list(struct hclge_dev *hdev,
4434                                      struct hclge_fd_rule *new_rule,
4435                                      u16 location,
4436                                      bool is_add)
4437 {
4438         struct hclge_fd_rule *rule = NULL, *parent = NULL;
4439         struct hlist_node *node2;
4440
4441         if (is_add && !new_rule)
4442                 return -EINVAL;
4443
4444         hlist_for_each_entry_safe(rule, node2,
4445                                   &hdev->fd_rule_list, rule_node) {
4446                 if (rule->location >= location)
4447                         break;
4448                 parent = rule;
4449         }
4450
4451         if (rule && rule->location == location) {
4452                 hlist_del(&rule->rule_node);
4453                 kfree(rule);
4454                 hdev->hclge_fd_rule_num--;
4455
4456                 if (!is_add)
4457                         return 0;
4458
4459         } else if (!is_add) {
4460                 dev_err(&hdev->pdev->dev,
4461                         "delete fail, rule %d is inexistent\n",
4462                         location);
4463                 return -EINVAL;
4464         }
4465
4466         INIT_HLIST_NODE(&new_rule->rule_node);
4467
4468         if (parent)
4469                 hlist_add_behind(&new_rule->rule_node, &parent->rule_node);
4470         else
4471                 hlist_add_head(&new_rule->rule_node, &hdev->fd_rule_list);
4472
4473         hdev->hclge_fd_rule_num++;
4474
4475         return 0;
4476 }
4477
4478 static int hclge_fd_get_tuple(struct hclge_dev *hdev,
4479                               struct ethtool_rx_flow_spec *fs,
4480                               struct hclge_fd_rule *rule)
4481 {
4482         u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT);
4483
4484         switch (flow_type) {
4485         case SCTP_V4_FLOW:
4486         case TCP_V4_FLOW:
4487         case UDP_V4_FLOW:
4488                 rule->tuples.src_ip[3] =
4489                                 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4src);
4490                 rule->tuples_mask.src_ip[3] =
4491                                 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4src);
4492
4493                 rule->tuples.dst_ip[3] =
4494                                 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4dst);
4495                 rule->tuples_mask.dst_ip[3] =
4496                                 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4dst);
4497
4498                 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc);
4499                 rule->tuples_mask.src_port =
4500                                 be16_to_cpu(fs->m_u.tcp_ip4_spec.psrc);
4501
4502                 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst);
4503                 rule->tuples_mask.dst_port =
4504                                 be16_to_cpu(fs->m_u.tcp_ip4_spec.pdst);
4505
4506                 rule->tuples.ip_tos = fs->h_u.tcp_ip4_spec.tos;
4507                 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip4_spec.tos;
4508
4509                 rule->tuples.ether_proto = ETH_P_IP;
4510                 rule->tuples_mask.ether_proto = 0xFFFF;
4511
4512                 break;
4513         case IP_USER_FLOW:
4514                 rule->tuples.src_ip[3] =
4515                                 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4src);
4516                 rule->tuples_mask.src_ip[3] =
4517                                 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4src);
4518
4519                 rule->tuples.dst_ip[3] =
4520                                 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4dst);
4521                 rule->tuples_mask.dst_ip[3] =
4522                                 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4dst);
4523
4524                 rule->tuples.ip_tos = fs->h_u.usr_ip4_spec.tos;
4525                 rule->tuples_mask.ip_tos = fs->m_u.usr_ip4_spec.tos;
4526
4527                 rule->tuples.ip_proto = fs->h_u.usr_ip4_spec.proto;
4528                 rule->tuples_mask.ip_proto = fs->m_u.usr_ip4_spec.proto;
4529
4530                 rule->tuples.ether_proto = ETH_P_IP;
4531                 rule->tuples_mask.ether_proto = 0xFFFF;
4532
4533                 break;
4534         case SCTP_V6_FLOW:
4535         case TCP_V6_FLOW:
4536         case UDP_V6_FLOW:
4537                 be32_to_cpu_array(rule->tuples.src_ip,
4538                                   fs->h_u.tcp_ip6_spec.ip6src, 4);
4539                 be32_to_cpu_array(rule->tuples_mask.src_ip,
4540                                   fs->m_u.tcp_ip6_spec.ip6src, 4);
4541
4542                 be32_to_cpu_array(rule->tuples.dst_ip,
4543                                   fs->h_u.tcp_ip6_spec.ip6dst, 4);
4544                 be32_to_cpu_array(rule->tuples_mask.dst_ip,
4545                                   fs->m_u.tcp_ip6_spec.ip6dst, 4);
4546
4547                 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.psrc);
4548                 rule->tuples_mask.src_port =
4549                                 be16_to_cpu(fs->m_u.tcp_ip6_spec.psrc);
4550
4551                 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.pdst);
4552                 rule->tuples_mask.dst_port =
4553                                 be16_to_cpu(fs->m_u.tcp_ip6_spec.pdst);
4554
4555                 rule->tuples.ether_proto = ETH_P_IPV6;
4556                 rule->tuples_mask.ether_proto = 0xFFFF;
4557
4558                 break;
4559         case IPV6_USER_FLOW:
4560                 be32_to_cpu_array(rule->tuples.src_ip,
4561                                   fs->h_u.usr_ip6_spec.ip6src, 4);
4562                 be32_to_cpu_array(rule->tuples_mask.src_ip,
4563                                   fs->m_u.usr_ip6_spec.ip6src, 4);
4564
4565                 be32_to_cpu_array(rule->tuples.dst_ip,
4566                                   fs->h_u.usr_ip6_spec.ip6dst, 4);
4567                 be32_to_cpu_array(rule->tuples_mask.dst_ip,
4568                                   fs->m_u.usr_ip6_spec.ip6dst, 4);
4569
4570                 rule->tuples.ip_proto = fs->h_u.usr_ip6_spec.l4_proto;
4571                 rule->tuples_mask.ip_proto = fs->m_u.usr_ip6_spec.l4_proto;
4572
4573                 rule->tuples.ether_proto = ETH_P_IPV6;
4574                 rule->tuples_mask.ether_proto = 0xFFFF;
4575
4576                 break;
4577         case ETHER_FLOW:
4578                 ether_addr_copy(rule->tuples.src_mac,
4579                                 fs->h_u.ether_spec.h_source);
4580                 ether_addr_copy(rule->tuples_mask.src_mac,
4581                                 fs->m_u.ether_spec.h_source);
4582
4583                 ether_addr_copy(rule->tuples.dst_mac,
4584                                 fs->h_u.ether_spec.h_dest);
4585                 ether_addr_copy(rule->tuples_mask.dst_mac,
4586                                 fs->m_u.ether_spec.h_dest);
4587
4588                 rule->tuples.ether_proto =
4589                                 be16_to_cpu(fs->h_u.ether_spec.h_proto);
4590                 rule->tuples_mask.ether_proto =
4591                                 be16_to_cpu(fs->m_u.ether_spec.h_proto);
4592
4593                 break;
4594         default:
4595                 return -EOPNOTSUPP;
4596         }
4597
4598         switch (flow_type) {
4599         case SCTP_V4_FLOW:
4600         case SCTP_V6_FLOW:
4601                 rule->tuples.ip_proto = IPPROTO_SCTP;
4602                 rule->tuples_mask.ip_proto = 0xFF;
4603                 break;
4604         case TCP_V4_FLOW:
4605         case TCP_V6_FLOW:
4606                 rule->tuples.ip_proto = IPPROTO_TCP;
4607                 rule->tuples_mask.ip_proto = 0xFF;
4608                 break;
4609         case UDP_V4_FLOW:
4610         case UDP_V6_FLOW:
4611                 rule->tuples.ip_proto = IPPROTO_UDP;
4612                 rule->tuples_mask.ip_proto = 0xFF;
4613                 break;
4614         default:
4615                 break;
4616         }
4617
4618         if ((fs->flow_type & FLOW_EXT)) {
4619                 rule->tuples.vlan_tag1 = be16_to_cpu(fs->h_ext.vlan_tci);
4620                 rule->tuples_mask.vlan_tag1 = be16_to_cpu(fs->m_ext.vlan_tci);
4621         }
4622
4623         if (fs->flow_type & FLOW_MAC_EXT) {
4624                 ether_addr_copy(rule->tuples.dst_mac, fs->h_ext.h_dest);
4625                 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_ext.h_dest);
4626         }
4627
4628         return 0;
4629 }
4630
4631 static int hclge_add_fd_entry(struct hnae3_handle *handle,
4632                               struct ethtool_rxnfc *cmd)
4633 {
4634         struct hclge_vport *vport = hclge_get_vport(handle);
4635         struct hclge_dev *hdev = vport->back;
4636         u16 dst_vport_id = 0, q_index = 0;
4637         struct ethtool_rx_flow_spec *fs;
4638         struct hclge_fd_rule *rule;
4639         u32 unused = 0;
4640         u8 action;
4641         int ret;
4642
4643         if (!hnae3_dev_fd_supported(hdev))
4644                 return -EOPNOTSUPP;
4645
4646         if (!hdev->fd_cfg.fd_en) {
4647                 dev_warn(&hdev->pdev->dev,
4648                          "Please enable flow director first\n");
4649                 return -EOPNOTSUPP;
4650         }
4651
4652         fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
4653
4654         ret = hclge_fd_check_spec(hdev, fs, &unused);
4655         if (ret) {
4656                 dev_err(&hdev->pdev->dev, "Check fd spec failed\n");
4657                 return ret;
4658         }
4659
4660         if (fs->ring_cookie == RX_CLS_FLOW_DISC) {
4661                 action = HCLGE_FD_ACTION_DROP_PACKET;
4662         } else {
4663                 u32 ring = ethtool_get_flow_spec_ring(fs->ring_cookie);
4664                 u8 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie);
4665                 u16 tqps;
4666
4667                 if (vf > hdev->num_req_vfs) {
4668                         dev_err(&hdev->pdev->dev,
4669                                 "Error: vf id (%d) > max vf num (%d)\n",
4670                                 vf, hdev->num_req_vfs);
4671                         return -EINVAL;
4672                 }
4673
4674                 dst_vport_id = vf ? hdev->vport[vf].vport_id : vport->vport_id;
4675                 tqps = vf ? hdev->vport[vf].alloc_tqps : vport->alloc_tqps;
4676
4677                 if (ring >= tqps) {
4678                         dev_err(&hdev->pdev->dev,
4679                                 "Error: queue id (%d) > max tqp num (%d)\n",
4680                                 ring, tqps - 1);
4681                         return -EINVAL;
4682                 }
4683
4684                 action = HCLGE_FD_ACTION_ACCEPT_PACKET;
4685                 q_index = ring;
4686         }
4687
4688         rule = kzalloc(sizeof(*rule), GFP_KERNEL);
4689         if (!rule)
4690                 return -ENOMEM;
4691
4692         ret = hclge_fd_get_tuple(hdev, fs, rule);
4693         if (ret)
4694                 goto free_rule;
4695
4696         rule->flow_type = fs->flow_type;
4697
4698         rule->location = fs->location;
4699         rule->unused_tuple = unused;
4700         rule->vf_id = dst_vport_id;
4701         rule->queue_id = q_index;
4702         rule->action = action;
4703
4704         ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule);
4705         if (ret)
4706                 goto free_rule;
4707
4708         ret = hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule);
4709         if (ret)
4710                 goto free_rule;
4711
4712         ret = hclge_fd_update_rule_list(hdev, rule, fs->location, true);
4713         if (ret)
4714                 goto free_rule;
4715
4716         return ret;
4717
4718 free_rule:
4719         kfree(rule);
4720         return ret;
4721 }
4722
4723 static int hclge_del_fd_entry(struct hnae3_handle *handle,
4724                               struct ethtool_rxnfc *cmd)
4725 {
4726         struct hclge_vport *vport = hclge_get_vport(handle);
4727         struct hclge_dev *hdev = vport->back;
4728         struct ethtool_rx_flow_spec *fs;
4729         int ret;
4730
4731         if (!hnae3_dev_fd_supported(hdev))
4732                 return -EOPNOTSUPP;
4733
4734         fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
4735
4736         if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1])
4737                 return -EINVAL;
4738
4739         if (!hclge_fd_rule_exist(hdev, fs->location)) {
4740                 dev_err(&hdev->pdev->dev,
4741                         "Delete fail, rule %d is inexistent\n",
4742                         fs->location);
4743                 return -ENOENT;
4744         }
4745
4746         ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
4747                                    fs->location, NULL, false);
4748         if (ret)
4749                 return ret;
4750
4751         return hclge_fd_update_rule_list(hdev, NULL, fs->location,
4752                                          false);
4753 }
4754
4755 static void hclge_del_all_fd_entries(struct hnae3_handle *handle,
4756                                      bool clear_list)
4757 {
4758         struct hclge_vport *vport = hclge_get_vport(handle);
4759         struct hclge_dev *hdev = vport->back;
4760         struct hclge_fd_rule *rule;
4761         struct hlist_node *node;
4762
4763         if (!hnae3_dev_fd_supported(hdev))
4764                 return;
4765
4766         if (clear_list) {
4767                 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list,
4768                                           rule_node) {
4769                         hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
4770                                              rule->location, NULL, false);
4771                         hlist_del(&rule->rule_node);
4772                         kfree(rule);
4773                         hdev->hclge_fd_rule_num--;
4774                 }
4775         } else {
4776                 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list,
4777                                           rule_node)
4778                         hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
4779                                              rule->location, NULL, false);
4780         }
4781 }
4782
4783 static int hclge_restore_fd_entries(struct hnae3_handle *handle)
4784 {
4785         struct hclge_vport *vport = hclge_get_vport(handle);
4786         struct hclge_dev *hdev = vport->back;
4787         struct hclge_fd_rule *rule;
4788         struct hlist_node *node;
4789         int ret;
4790
4791         /* Return ok here, because reset error handling will check this
4792          * return value. If error is returned here, the reset process will
4793          * fail.
4794          */
4795         if (!hnae3_dev_fd_supported(hdev))
4796                 return 0;
4797
4798         /* if fd is disabled, should not restore it when reset */
4799         if (!hdev->fd_cfg.fd_en)
4800                 return 0;
4801
4802         hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
4803                 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule);
4804                 if (!ret)
4805                         ret = hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule);
4806
4807                 if (ret) {
4808                         dev_warn(&hdev->pdev->dev,
4809                                  "Restore rule %d failed, remove it\n",
4810                                  rule->location);
4811                         hlist_del(&rule->rule_node);
4812                         kfree(rule);
4813                         hdev->hclge_fd_rule_num--;
4814                 }
4815         }
4816         return 0;
4817 }
4818
4819 static int hclge_get_fd_rule_cnt(struct hnae3_handle *handle,
4820                                  struct ethtool_rxnfc *cmd)
4821 {
4822         struct hclge_vport *vport = hclge_get_vport(handle);
4823         struct hclge_dev *hdev = vport->back;
4824
4825         if (!hnae3_dev_fd_supported(hdev))
4826                 return -EOPNOTSUPP;
4827
4828         cmd->rule_cnt = hdev->hclge_fd_rule_num;
4829         cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1];
4830
4831         return 0;
4832 }
4833
4834 static int hclge_get_fd_rule_info(struct hnae3_handle *handle,
4835                                   struct ethtool_rxnfc *cmd)
4836 {
4837         struct hclge_vport *vport = hclge_get_vport(handle);
4838         struct hclge_fd_rule *rule = NULL;
4839         struct hclge_dev *hdev = vport->back;
4840         struct ethtool_rx_flow_spec *fs;
4841         struct hlist_node *node2;
4842
4843         if (!hnae3_dev_fd_supported(hdev))
4844                 return -EOPNOTSUPP;
4845
4846         fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
4847
4848         hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) {
4849                 if (rule->location >= fs->location)
4850                         break;
4851         }
4852
4853         if (!rule || fs->location != rule->location)
4854                 return -ENOENT;
4855
4856         fs->flow_type = rule->flow_type;
4857         switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
4858         case SCTP_V4_FLOW:
4859         case TCP_V4_FLOW:
4860         case UDP_V4_FLOW:
4861                 fs->h_u.tcp_ip4_spec.ip4src =
4862                                 cpu_to_be32(rule->tuples.src_ip[3]);
4863                 fs->m_u.tcp_ip4_spec.ip4src =
4864                                 rule->unused_tuple & BIT(INNER_SRC_IP) ?
4865                                 0 : cpu_to_be32(rule->tuples_mask.src_ip[3]);
4866
4867                 fs->h_u.tcp_ip4_spec.ip4dst =
4868                                 cpu_to_be32(rule->tuples.dst_ip[3]);
4869                 fs->m_u.tcp_ip4_spec.ip4dst =
4870                                 rule->unused_tuple & BIT(INNER_DST_IP) ?
4871                                 0 : cpu_to_be32(rule->tuples_mask.dst_ip[3]);
4872
4873                 fs->h_u.tcp_ip4_spec.psrc = cpu_to_be16(rule->tuples.src_port);
4874                 fs->m_u.tcp_ip4_spec.psrc =
4875                                 rule->unused_tuple & BIT(INNER_SRC_PORT) ?
4876                                 0 : cpu_to_be16(rule->tuples_mask.src_port);
4877
4878                 fs->h_u.tcp_ip4_spec.pdst = cpu_to_be16(rule->tuples.dst_port);
4879                 fs->m_u.tcp_ip4_spec.pdst =
4880                                 rule->unused_tuple & BIT(INNER_DST_PORT) ?
4881                                 0 : cpu_to_be16(rule->tuples_mask.dst_port);
4882
4883                 fs->h_u.tcp_ip4_spec.tos = rule->tuples.ip_tos;
4884                 fs->m_u.tcp_ip4_spec.tos =
4885                                 rule->unused_tuple & BIT(INNER_IP_TOS) ?
4886                                 0 : rule->tuples_mask.ip_tos;
4887
4888                 break;
4889         case IP_USER_FLOW:
4890                 fs->h_u.usr_ip4_spec.ip4src =
4891                                 cpu_to_be32(rule->tuples.src_ip[3]);
4892                 fs->m_u.tcp_ip4_spec.ip4src =
4893                                 rule->unused_tuple & BIT(INNER_SRC_IP) ?
4894                                 0 : cpu_to_be32(rule->tuples_mask.src_ip[3]);
4895
4896                 fs->h_u.usr_ip4_spec.ip4dst =
4897                                 cpu_to_be32(rule->tuples.dst_ip[3]);
4898                 fs->m_u.usr_ip4_spec.ip4dst =
4899                                 rule->unused_tuple & BIT(INNER_DST_IP) ?
4900                                 0 : cpu_to_be32(rule->tuples_mask.dst_ip[3]);
4901
4902                 fs->h_u.usr_ip4_spec.tos = rule->tuples.ip_tos;
4903                 fs->m_u.usr_ip4_spec.tos =
4904                                 rule->unused_tuple & BIT(INNER_IP_TOS) ?
4905                                 0 : rule->tuples_mask.ip_tos;
4906
4907                 fs->h_u.usr_ip4_spec.proto = rule->tuples.ip_proto;
4908                 fs->m_u.usr_ip4_spec.proto =
4909                                 rule->unused_tuple & BIT(INNER_IP_PROTO) ?
4910                                 0 : rule->tuples_mask.ip_proto;
4911
4912                 fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
4913
4914                 break;
4915         case SCTP_V6_FLOW:
4916         case TCP_V6_FLOW:
4917         case UDP_V6_FLOW:
4918                 cpu_to_be32_array(fs->h_u.tcp_ip6_spec.ip6src,
4919                                   rule->tuples.src_ip, 4);
4920                 if (rule->unused_tuple & BIT(INNER_SRC_IP))
4921                         memset(fs->m_u.tcp_ip6_spec.ip6src, 0, sizeof(int) * 4);
4922                 else
4923                         cpu_to_be32_array(fs->m_u.tcp_ip6_spec.ip6src,
4924                                           rule->tuples_mask.src_ip, 4);
4925
4926                 cpu_to_be32_array(fs->h_u.tcp_ip6_spec.ip6dst,
4927                                   rule->tuples.dst_ip, 4);
4928                 if (rule->unused_tuple & BIT(INNER_DST_IP))
4929                         memset(fs->m_u.tcp_ip6_spec.ip6dst, 0, sizeof(int) * 4);
4930                 else
4931                         cpu_to_be32_array(fs->m_u.tcp_ip6_spec.ip6dst,
4932                                           rule->tuples_mask.dst_ip, 4);
4933
4934                 fs->h_u.tcp_ip6_spec.psrc = cpu_to_be16(rule->tuples.src_port);
4935                 fs->m_u.tcp_ip6_spec.psrc =
4936                                 rule->unused_tuple & BIT(INNER_SRC_PORT) ?
4937                                 0 : cpu_to_be16(rule->tuples_mask.src_port);
4938
4939                 fs->h_u.tcp_ip6_spec.pdst = cpu_to_be16(rule->tuples.dst_port);
4940                 fs->m_u.tcp_ip6_spec.pdst =
4941                                 rule->unused_tuple & BIT(INNER_DST_PORT) ?
4942                                 0 : cpu_to_be16(rule->tuples_mask.dst_port);
4943
4944                 break;
4945         case IPV6_USER_FLOW:
4946                 cpu_to_be32_array(fs->h_u.usr_ip6_spec.ip6src,
4947                                   rule->tuples.src_ip, 4);
4948                 if (rule->unused_tuple & BIT(INNER_SRC_IP))
4949                         memset(fs->m_u.usr_ip6_spec.ip6src, 0, sizeof(int) * 4);
4950                 else
4951                         cpu_to_be32_array(fs->m_u.usr_ip6_spec.ip6src,
4952                                           rule->tuples_mask.src_ip, 4);
4953
4954                 cpu_to_be32_array(fs->h_u.usr_ip6_spec.ip6dst,
4955                                   rule->tuples.dst_ip, 4);
4956                 if (rule->unused_tuple & BIT(INNER_DST_IP))
4957                         memset(fs->m_u.usr_ip6_spec.ip6dst, 0, sizeof(int) * 4);
4958                 else
4959                         cpu_to_be32_array(fs->m_u.usr_ip6_spec.ip6dst,
4960                                           rule->tuples_mask.dst_ip, 4);
4961
4962                 fs->h_u.usr_ip6_spec.l4_proto = rule->tuples.ip_proto;
4963                 fs->m_u.usr_ip6_spec.l4_proto =
4964                                 rule->unused_tuple & BIT(INNER_IP_PROTO) ?
4965                                 0 : rule->tuples_mask.ip_proto;
4966
4967                 break;
4968         case ETHER_FLOW:
4969                 ether_addr_copy(fs->h_u.ether_spec.h_source,
4970                                 rule->tuples.src_mac);
4971                 if (rule->unused_tuple & BIT(INNER_SRC_MAC))
4972                         eth_zero_addr(fs->m_u.ether_spec.h_source);
4973                 else
4974                         ether_addr_copy(fs->m_u.ether_spec.h_source,
4975                                         rule->tuples_mask.src_mac);
4976
4977                 ether_addr_copy(fs->h_u.ether_spec.h_dest,
4978                                 rule->tuples.dst_mac);
4979                 if (rule->unused_tuple & BIT(INNER_DST_MAC))
4980                         eth_zero_addr(fs->m_u.ether_spec.h_dest);
4981                 else
4982                         ether_addr_copy(fs->m_u.ether_spec.h_dest,
4983                                         rule->tuples_mask.dst_mac);
4984
4985                 fs->h_u.ether_spec.h_proto =
4986                                 cpu_to_be16(rule->tuples.ether_proto);
4987                 fs->m_u.ether_spec.h_proto =
4988                                 rule->unused_tuple & BIT(INNER_ETH_TYPE) ?
4989                                 0 : cpu_to_be16(rule->tuples_mask.ether_proto);
4990
4991                 break;
4992         default:
4993                 return -EOPNOTSUPP;
4994         }
4995
4996         if (fs->flow_type & FLOW_EXT) {
4997                 fs->h_ext.vlan_tci = cpu_to_be16(rule->tuples.vlan_tag1);
4998                 fs->m_ext.vlan_tci =
4999                                 rule->unused_tuple & BIT(INNER_VLAN_TAG_FST) ?
5000                                 cpu_to_be16(VLAN_VID_MASK) :
5001                                 cpu_to_be16(rule->tuples_mask.vlan_tag1);
5002         }
5003
5004         if (fs->flow_type & FLOW_MAC_EXT) {
5005                 ether_addr_copy(fs->h_ext.h_dest, rule->tuples.dst_mac);
5006                 if (rule->unused_tuple & BIT(INNER_DST_MAC))
5007                         eth_zero_addr(fs->m_u.ether_spec.h_dest);
5008                 else
5009                         ether_addr_copy(fs->m_u.ether_spec.h_dest,
5010                                         rule->tuples_mask.dst_mac);
5011         }
5012
5013         if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) {
5014                 fs->ring_cookie = RX_CLS_FLOW_DISC;
5015         } else {
5016                 u64 vf_id;
5017
5018                 fs->ring_cookie = rule->queue_id;
5019                 vf_id = rule->vf_id;
5020                 vf_id <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
5021                 fs->ring_cookie |= vf_id;
5022         }
5023
5024         return 0;
5025 }
5026
5027 static int hclge_get_all_rules(struct hnae3_handle *handle,
5028                                struct ethtool_rxnfc *cmd, u32 *rule_locs)
5029 {
5030         struct hclge_vport *vport = hclge_get_vport(handle);
5031         struct hclge_dev *hdev = vport->back;
5032         struct hclge_fd_rule *rule;
5033         struct hlist_node *node2;
5034         int cnt = 0;
5035
5036         if (!hnae3_dev_fd_supported(hdev))
5037                 return -EOPNOTSUPP;
5038
5039         cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1];
5040
5041         hlist_for_each_entry_safe(rule, node2,
5042                                   &hdev->fd_rule_list, rule_node) {
5043                 if (cnt == cmd->rule_cnt)
5044                         return -EMSGSIZE;
5045
5046                 rule_locs[cnt] = rule->location;
5047                 cnt++;
5048         }
5049
5050         cmd->rule_cnt = cnt;
5051
5052         return 0;
5053 }
5054
5055 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle)
5056 {
5057         struct hclge_vport *vport = hclge_get_vport(handle);
5058         struct hclge_dev *hdev = vport->back;
5059
5060         return hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) ||
5061                hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING);
5062 }
5063
5064 static bool hclge_ae_dev_resetting(struct hnae3_handle *handle)
5065 {
5066         struct hclge_vport *vport = hclge_get_vport(handle);
5067         struct hclge_dev *hdev = vport->back;
5068
5069         return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
5070 }
5071
5072 static unsigned long hclge_ae_dev_reset_cnt(struct hnae3_handle *handle)
5073 {
5074         struct hclge_vport *vport = hclge_get_vport(handle);
5075         struct hclge_dev *hdev = vport->back;
5076
5077         return hdev->reset_count;
5078 }
5079
5080 static void hclge_enable_fd(struct hnae3_handle *handle, bool enable)
5081 {
5082         struct hclge_vport *vport = hclge_get_vport(handle);
5083         struct hclge_dev *hdev = vport->back;
5084
5085         hdev->fd_cfg.fd_en = enable;
5086         if (!enable)
5087                 hclge_del_all_fd_entries(handle, false);
5088         else
5089                 hclge_restore_fd_entries(handle);
5090 }
5091
5092 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
5093 {
5094         struct hclge_desc desc;
5095         struct hclge_config_mac_mode_cmd *req =
5096                 (struct hclge_config_mac_mode_cmd *)desc.data;
5097         u32 loop_en = 0;
5098         int ret;
5099
5100         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
5101         hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
5102         hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
5103         hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
5104         hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
5105         hnae3_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
5106         hnae3_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
5107         hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
5108         hnae3_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
5109         hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
5110         hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
5111         hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
5112         hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
5113         hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
5114         hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
5115         req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
5116
5117         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5118         if (ret)
5119                 dev_err(&hdev->pdev->dev,
5120                         "mac enable fail, ret =%d.\n", ret);
5121 }
5122
5123 static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en)
5124 {
5125         struct hclge_config_mac_mode_cmd *req;
5126         struct hclge_desc desc;
5127         u32 loop_en;
5128         int ret;
5129
5130         req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
5131         /* 1 Read out the MAC mode config at first */
5132         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
5133         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5134         if (ret) {
5135                 dev_err(&hdev->pdev->dev,
5136                         "mac loopback get fail, ret =%d.\n", ret);
5137                 return ret;
5138         }
5139
5140         /* 2 Then setup the loopback flag */
5141         loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
5142         hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0);
5143         hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, en ? 1 : 0);
5144         hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, en ? 1 : 0);
5145
5146         req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
5147
5148         /* 3 Config mac work mode with loopback flag
5149          * and its original configure parameters
5150          */
5151         hclge_cmd_reuse_desc(&desc, false);
5152         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5153         if (ret)
5154                 dev_err(&hdev->pdev->dev,
5155                         "mac loopback set fail, ret =%d.\n", ret);
5156         return ret;
5157 }
5158
5159 static int hclge_set_serdes_loopback(struct hclge_dev *hdev, bool en,
5160                                      enum hnae3_loop loop_mode)
5161 {
5162 #define HCLGE_SERDES_RETRY_MS   10
5163 #define HCLGE_SERDES_RETRY_NUM  100
5164         struct hclge_serdes_lb_cmd *req;
5165         struct hclge_desc desc;
5166         int ret, i = 0;
5167         u8 loop_mode_b;
5168
5169         req = (struct hclge_serdes_lb_cmd *)desc.data;
5170         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK, false);
5171
5172         switch (loop_mode) {
5173         case HNAE3_LOOP_SERIAL_SERDES:
5174                 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
5175                 break;
5176         case HNAE3_LOOP_PARALLEL_SERDES:
5177                 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B;
5178                 break;
5179         default:
5180                 dev_err(&hdev->pdev->dev,
5181                         "unsupported serdes loopback mode %d\n", loop_mode);
5182                 return -ENOTSUPP;
5183         }
5184
5185         if (en) {
5186                 req->enable = loop_mode_b;
5187                 req->mask = loop_mode_b;
5188         } else {
5189                 req->mask = loop_mode_b;
5190         }
5191
5192         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5193         if (ret) {
5194                 dev_err(&hdev->pdev->dev,
5195                         "serdes loopback set fail, ret = %d\n", ret);
5196                 return ret;
5197         }
5198
5199         do {
5200                 msleep(HCLGE_SERDES_RETRY_MS);
5201                 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK,
5202                                            true);
5203                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5204                 if (ret) {
5205                         dev_err(&hdev->pdev->dev,
5206                                 "serdes loopback get, ret = %d\n", ret);
5207                         return ret;
5208                 }
5209         } while (++i < HCLGE_SERDES_RETRY_NUM &&
5210                  !(req->result & HCLGE_CMD_SERDES_DONE_B));
5211
5212         if (!(req->result & HCLGE_CMD_SERDES_DONE_B)) {
5213                 dev_err(&hdev->pdev->dev, "serdes loopback set timeout\n");
5214                 return -EBUSY;
5215         } else if (!(req->result & HCLGE_CMD_SERDES_SUCCESS_B)) {
5216                 dev_err(&hdev->pdev->dev, "serdes loopback set failed in fw\n");
5217                 return -EIO;
5218         }
5219
5220         hclge_cfg_mac_mode(hdev, en);
5221         return 0;
5222 }
5223
5224 static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
5225                             int stream_id, bool enable)
5226 {
5227         struct hclge_desc desc;
5228         struct hclge_cfg_com_tqp_queue_cmd *req =
5229                 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
5230         int ret;
5231
5232         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
5233         req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
5234         req->stream_id = cpu_to_le16(stream_id);
5235         req->enable |= enable << HCLGE_TQP_ENABLE_B;
5236
5237         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5238         if (ret)
5239                 dev_err(&hdev->pdev->dev,
5240                         "Tqp enable fail, status =%d.\n", ret);
5241         return ret;
5242 }
5243
5244 static int hclge_set_loopback(struct hnae3_handle *handle,
5245                               enum hnae3_loop loop_mode, bool en)
5246 {
5247         struct hclge_vport *vport = hclge_get_vport(handle);
5248         struct hnae3_knic_private_info *kinfo;
5249         struct hclge_dev *hdev = vport->back;
5250         int i, ret;
5251
5252         switch (loop_mode) {
5253         case HNAE3_LOOP_APP:
5254                 ret = hclge_set_app_loopback(hdev, en);
5255                 break;
5256         case HNAE3_LOOP_SERIAL_SERDES:
5257         case HNAE3_LOOP_PARALLEL_SERDES:
5258                 ret = hclge_set_serdes_loopback(hdev, en, loop_mode);
5259                 break;
5260         default:
5261                 ret = -ENOTSUPP;
5262                 dev_err(&hdev->pdev->dev,
5263                         "loop_mode %d is not supported\n", loop_mode);
5264                 break;
5265         }
5266
5267         kinfo = &vport->nic.kinfo;
5268         for (i = 0; i < kinfo->num_tqps; i++) {
5269                 ret = hclge_tqp_enable(hdev, i, 0, en);
5270                 if (ret)
5271                         return ret;
5272         }
5273
5274         return 0;
5275 }
5276
5277 static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
5278 {
5279         struct hclge_vport *vport = hclge_get_vport(handle);
5280         struct hnae3_knic_private_info *kinfo;
5281         struct hnae3_queue *queue;
5282         struct hclge_tqp *tqp;
5283         int i;
5284
5285         kinfo = &vport->nic.kinfo;
5286         for (i = 0; i < kinfo->num_tqps; i++) {
5287                 queue = handle->kinfo.tqp[i];
5288                 tqp = container_of(queue, struct hclge_tqp, q);
5289                 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
5290         }
5291 }
5292
5293 static void hclge_set_timer_task(struct hnae3_handle *handle, bool enable)
5294 {
5295         struct hclge_vport *vport = hclge_get_vport(handle);
5296         struct hclge_dev *hdev = vport->back;
5297
5298         if (enable) {
5299                 mod_timer(&hdev->service_timer, jiffies + HZ);
5300         } else {
5301                 del_timer_sync(&hdev->service_timer);
5302                 cancel_work_sync(&hdev->service_task);
5303                 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
5304         }
5305 }
5306
5307 static int hclge_ae_start(struct hnae3_handle *handle)
5308 {
5309         struct hclge_vport *vport = hclge_get_vport(handle);
5310         struct hclge_dev *hdev = vport->back;
5311
5312         /* mac enable */
5313         hclge_cfg_mac_mode(hdev, true);
5314         clear_bit(HCLGE_STATE_DOWN, &hdev->state);
5315         hdev->hw.mac.link = 0;
5316
5317         /* reset tqp stats */
5318         hclge_reset_tqp_stats(handle);
5319
5320         hclge_mac_start_phy(hdev);
5321
5322         return 0;
5323 }
5324
5325 static void hclge_ae_stop(struct hnae3_handle *handle)
5326 {
5327         struct hclge_vport *vport = hclge_get_vport(handle);
5328         struct hclge_dev *hdev = vport->back;
5329         int i;
5330
5331         set_bit(HCLGE_STATE_DOWN, &hdev->state);
5332
5333         /* If it is not PF reset, the firmware will disable the MAC,
5334          * so it only need to stop phy here.
5335          */
5336         if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) &&
5337             hdev->reset_type != HNAE3_FUNC_RESET) {
5338                 hclge_mac_stop_phy(hdev);
5339                 return;
5340         }
5341
5342         for (i = 0; i < handle->kinfo.num_tqps; i++)
5343                 hclge_reset_tqp(handle, i);
5344
5345         /* Mac disable */
5346         hclge_cfg_mac_mode(hdev, false);
5347
5348         hclge_mac_stop_phy(hdev);
5349
5350         /* reset tqp stats */
5351         hclge_reset_tqp_stats(handle);
5352         hclge_update_link_status(hdev);
5353 }
5354
5355 int hclge_vport_start(struct hclge_vport *vport)
5356 {
5357         set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
5358         vport->last_active_jiffies = jiffies;
5359         return 0;
5360 }
5361
5362 void hclge_vport_stop(struct hclge_vport *vport)
5363 {
5364         clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
5365 }
5366
5367 static int hclge_client_start(struct hnae3_handle *handle)
5368 {
5369         struct hclge_vport *vport = hclge_get_vport(handle);
5370
5371         return hclge_vport_start(vport);
5372 }
5373
5374 static void hclge_client_stop(struct hnae3_handle *handle)
5375 {
5376         struct hclge_vport *vport = hclge_get_vport(handle);
5377
5378         hclge_vport_stop(vport);
5379 }
5380
5381 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
5382                                          u16 cmdq_resp, u8  resp_code,
5383                                          enum hclge_mac_vlan_tbl_opcode op)
5384 {
5385         struct hclge_dev *hdev = vport->back;
5386         int return_status = -EIO;
5387
5388         if (cmdq_resp) {
5389                 dev_err(&hdev->pdev->dev,
5390                         "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
5391                         cmdq_resp);
5392                 return -EIO;
5393         }
5394
5395         if (op == HCLGE_MAC_VLAN_ADD) {
5396                 if ((!resp_code) || (resp_code == 1)) {
5397                         return_status = 0;
5398                 } else if (resp_code == 2) {
5399                         return_status = -ENOSPC;
5400                         dev_err(&hdev->pdev->dev,
5401                                 "add mac addr failed for uc_overflow.\n");
5402                 } else if (resp_code == 3) {
5403                         return_status = -ENOSPC;
5404                         dev_err(&hdev->pdev->dev,
5405                                 "add mac addr failed for mc_overflow.\n");
5406                 } else {
5407                         dev_err(&hdev->pdev->dev,
5408                                 "add mac addr failed for undefined, code=%d.\n",
5409                                 resp_code);
5410                 }
5411         } else if (op == HCLGE_MAC_VLAN_REMOVE) {
5412                 if (!resp_code) {
5413                         return_status = 0;
5414                 } else if (resp_code == 1) {
5415                         return_status = -ENOENT;
5416                         dev_dbg(&hdev->pdev->dev,
5417                                 "remove mac addr failed for miss.\n");
5418                 } else {
5419                         dev_err(&hdev->pdev->dev,
5420                                 "remove mac addr failed for undefined, code=%d.\n",
5421                                 resp_code);
5422                 }
5423         } else if (op == HCLGE_MAC_VLAN_LKUP) {
5424                 if (!resp_code) {
5425                         return_status = 0;
5426                 } else if (resp_code == 1) {
5427                         return_status = -ENOENT;
5428                         dev_dbg(&hdev->pdev->dev,
5429                                 "lookup mac addr failed for miss.\n");
5430                 } else {
5431                         dev_err(&hdev->pdev->dev,
5432                                 "lookup mac addr failed for undefined, code=%d.\n",
5433                                 resp_code);
5434                 }
5435         } else {
5436                 return_status = -EINVAL;
5437                 dev_err(&hdev->pdev->dev,
5438                         "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
5439                         op);
5440         }
5441
5442         return return_status;
5443 }
5444
5445 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
5446 {
5447         int word_num;
5448         int bit_num;
5449
5450         if (vfid > 255 || vfid < 0)
5451                 return -EIO;
5452
5453         if (vfid >= 0 && vfid <= 191) {
5454                 word_num = vfid / 32;
5455                 bit_num  = vfid % 32;
5456                 if (clr)
5457                         desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
5458                 else
5459                         desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
5460         } else {
5461                 word_num = (vfid - 192) / 32;
5462                 bit_num  = vfid % 32;
5463                 if (clr)
5464                         desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
5465                 else
5466                         desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
5467         }
5468
5469         return 0;
5470 }
5471
5472 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
5473 {
5474 #define HCLGE_DESC_NUMBER 3
5475 #define HCLGE_FUNC_NUMBER_PER_DESC 6
5476         int i, j;
5477
5478         for (i = 1; i < HCLGE_DESC_NUMBER; i++)
5479                 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
5480                         if (desc[i].data[j])
5481                                 return false;
5482
5483         return true;
5484 }
5485
5486 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
5487                                    const u8 *addr)
5488 {
5489         const unsigned char *mac_addr = addr;
5490         u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
5491                        (mac_addr[0]) | (mac_addr[1] << 8);
5492         u32 low_val  = mac_addr[4] | (mac_addr[5] << 8);
5493
5494         new_req->mac_addr_hi32 = cpu_to_le32(high_val);
5495         new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
5496 }
5497
5498 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
5499                                      struct hclge_mac_vlan_tbl_entry_cmd *req)
5500 {
5501         struct hclge_dev *hdev = vport->back;
5502         struct hclge_desc desc;
5503         u8 resp_code;
5504         u16 retval;
5505         int ret;
5506
5507         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
5508
5509         memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
5510
5511         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5512         if (ret) {
5513                 dev_err(&hdev->pdev->dev,
5514                         "del mac addr failed for cmd_send, ret =%d.\n",
5515                         ret);
5516                 return ret;
5517         }
5518         resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
5519         retval = le16_to_cpu(desc.retval);
5520
5521         return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
5522                                              HCLGE_MAC_VLAN_REMOVE);
5523 }
5524
5525 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
5526                                      struct hclge_mac_vlan_tbl_entry_cmd *req,
5527                                      struct hclge_desc *desc,
5528                                      bool is_mc)
5529 {
5530         struct hclge_dev *hdev = vport->back;
5531         u8 resp_code;
5532         u16 retval;
5533         int ret;
5534
5535         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
5536         if (is_mc) {
5537                 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
5538                 memcpy(desc[0].data,
5539                        req,
5540                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
5541                 hclge_cmd_setup_basic_desc(&desc[1],
5542                                            HCLGE_OPC_MAC_VLAN_ADD,
5543                                            true);
5544                 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
5545                 hclge_cmd_setup_basic_desc(&desc[2],
5546                                            HCLGE_OPC_MAC_VLAN_ADD,
5547                                            true);
5548                 ret = hclge_cmd_send(&hdev->hw, desc, 3);
5549         } else {
5550                 memcpy(desc[0].data,
5551                        req,
5552                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
5553                 ret = hclge_cmd_send(&hdev->hw, desc, 1);
5554         }
5555         if (ret) {
5556                 dev_err(&hdev->pdev->dev,
5557                         "lookup mac addr failed for cmd_send, ret =%d.\n",
5558                         ret);
5559                 return ret;
5560         }
5561         resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
5562         retval = le16_to_cpu(desc[0].retval);
5563
5564         return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
5565                                              HCLGE_MAC_VLAN_LKUP);
5566 }
5567
5568 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
5569                                   struct hclge_mac_vlan_tbl_entry_cmd *req,
5570                                   struct hclge_desc *mc_desc)
5571 {
5572         struct hclge_dev *hdev = vport->back;
5573         int cfg_status;
5574         u8 resp_code;
5575         u16 retval;
5576         int ret;
5577
5578         if (!mc_desc) {
5579                 struct hclge_desc desc;
5580
5581                 hclge_cmd_setup_basic_desc(&desc,
5582                                            HCLGE_OPC_MAC_VLAN_ADD,
5583                                            false);
5584                 memcpy(desc.data, req,
5585                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
5586                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5587                 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
5588                 retval = le16_to_cpu(desc.retval);
5589
5590                 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
5591                                                            resp_code,
5592                                                            HCLGE_MAC_VLAN_ADD);
5593         } else {
5594                 hclge_cmd_reuse_desc(&mc_desc[0], false);
5595                 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
5596                 hclge_cmd_reuse_desc(&mc_desc[1], false);
5597                 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
5598                 hclge_cmd_reuse_desc(&mc_desc[2], false);
5599                 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
5600                 memcpy(mc_desc[0].data, req,
5601                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
5602                 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
5603                 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
5604                 retval = le16_to_cpu(mc_desc[0].retval);
5605
5606                 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
5607                                                            resp_code,
5608                                                            HCLGE_MAC_VLAN_ADD);
5609         }
5610
5611         if (ret) {
5612                 dev_err(&hdev->pdev->dev,
5613                         "add mac addr failed for cmd_send, ret =%d.\n",
5614                         ret);
5615                 return ret;
5616         }
5617
5618         return cfg_status;
5619 }
5620
5621 static int hclge_init_umv_space(struct hclge_dev *hdev)
5622 {
5623         u16 allocated_size = 0;
5624         int ret;
5625
5626         ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size,
5627                                   true);
5628         if (ret)
5629                 return ret;
5630
5631         if (allocated_size < hdev->wanted_umv_size)
5632                 dev_warn(&hdev->pdev->dev,
5633                          "Alloc umv space failed, want %d, get %d\n",
5634                          hdev->wanted_umv_size, allocated_size);
5635
5636         mutex_init(&hdev->umv_mutex);
5637         hdev->max_umv_size = allocated_size;
5638         hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_req_vfs + 2);
5639         hdev->share_umv_size = hdev->priv_umv_size +
5640                         hdev->max_umv_size % (hdev->num_req_vfs + 2);
5641
5642         return 0;
5643 }
5644
5645 static int hclge_uninit_umv_space(struct hclge_dev *hdev)
5646 {
5647         int ret;
5648
5649         if (hdev->max_umv_size > 0) {
5650                 ret = hclge_set_umv_space(hdev, hdev->max_umv_size, NULL,
5651                                           false);
5652                 if (ret)
5653                         return ret;
5654                 hdev->max_umv_size = 0;
5655         }
5656         mutex_destroy(&hdev->umv_mutex);
5657
5658         return 0;
5659 }
5660
5661 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size,
5662                                u16 *allocated_size, bool is_alloc)
5663 {
5664         struct hclge_umv_spc_alc_cmd *req;
5665         struct hclge_desc desc;
5666         int ret;
5667
5668         req = (struct hclge_umv_spc_alc_cmd *)desc.data;
5669         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false);
5670         hnae3_set_bit(req->allocate, HCLGE_UMV_SPC_ALC_B, !is_alloc);
5671         req->space_size = cpu_to_le32(space_size);
5672
5673         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5674         if (ret) {
5675                 dev_err(&hdev->pdev->dev,
5676                         "%s umv space failed for cmd_send, ret =%d\n",
5677                         is_alloc ? "allocate" : "free", ret);
5678                 return ret;
5679         }
5680
5681         if (is_alloc && allocated_size)
5682                 *allocated_size = le32_to_cpu(desc.data[1]);
5683
5684         return 0;
5685 }
5686
5687 static void hclge_reset_umv_space(struct hclge_dev *hdev)
5688 {
5689         struct hclge_vport *vport;
5690         int i;
5691
5692         for (i = 0; i < hdev->num_alloc_vport; i++) {
5693                 vport = &hdev->vport[i];
5694                 vport->used_umv_num = 0;
5695         }
5696
5697         mutex_lock(&hdev->umv_mutex);
5698         hdev->share_umv_size = hdev->priv_umv_size +
5699                         hdev->max_umv_size % (hdev->num_req_vfs + 2);
5700         mutex_unlock(&hdev->umv_mutex);
5701 }
5702
5703 static bool hclge_is_umv_space_full(struct hclge_vport *vport)
5704 {
5705         struct hclge_dev *hdev = vport->back;
5706         bool is_full;
5707
5708         mutex_lock(&hdev->umv_mutex);
5709         is_full = (vport->used_umv_num >= hdev->priv_umv_size &&
5710                    hdev->share_umv_size == 0);
5711         mutex_unlock(&hdev->umv_mutex);
5712
5713         return is_full;
5714 }
5715
5716 static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free)
5717 {
5718         struct hclge_dev *hdev = vport->back;
5719
5720         mutex_lock(&hdev->umv_mutex);
5721         if (is_free) {
5722                 if (vport->used_umv_num > hdev->priv_umv_size)
5723                         hdev->share_umv_size++;
5724                 vport->used_umv_num--;
5725         } else {
5726                 if (vport->used_umv_num >= hdev->priv_umv_size)
5727                         hdev->share_umv_size--;
5728                 vport->used_umv_num++;
5729         }
5730         mutex_unlock(&hdev->umv_mutex);
5731 }
5732
5733 static int hclge_add_uc_addr(struct hnae3_handle *handle,
5734                              const unsigned char *addr)
5735 {
5736         struct hclge_vport *vport = hclge_get_vport(handle);
5737
5738         return hclge_add_uc_addr_common(vport, addr);
5739 }
5740
5741 int hclge_add_uc_addr_common(struct hclge_vport *vport,
5742                              const unsigned char *addr)
5743 {
5744         struct hclge_dev *hdev = vport->back;
5745         struct hclge_mac_vlan_tbl_entry_cmd req;
5746         struct hclge_desc desc;
5747         u16 egress_port = 0;
5748         int ret;
5749
5750         /* mac addr check */
5751         if (is_zero_ether_addr(addr) ||
5752             is_broadcast_ether_addr(addr) ||
5753             is_multicast_ether_addr(addr)) {
5754                 dev_err(&hdev->pdev->dev,
5755                         "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
5756                          addr,
5757                          is_zero_ether_addr(addr),
5758                          is_broadcast_ether_addr(addr),
5759                          is_multicast_ether_addr(addr));
5760                 return -EINVAL;
5761         }
5762
5763         memset(&req, 0, sizeof(req));
5764         hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5765
5766         hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
5767                         HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
5768
5769         req.egress_port = cpu_to_le16(egress_port);
5770
5771         hclge_prepare_mac_addr(&req, addr);
5772
5773         /* Lookup the mac address in the mac_vlan table, and add
5774          * it if the entry is inexistent. Repeated unicast entry
5775          * is not allowed in the mac vlan table.
5776          */
5777         ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false);
5778         if (ret == -ENOENT) {
5779                 if (!hclge_is_umv_space_full(vport)) {
5780                         ret = hclge_add_mac_vlan_tbl(vport, &req, NULL);
5781                         if (!ret)
5782                                 hclge_update_umv_space(vport, false);
5783                         return ret;
5784                 }
5785
5786                 dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n",
5787                         hdev->priv_umv_size);
5788
5789                 return -ENOSPC;
5790         }
5791
5792         /* check if we just hit the duplicate */
5793         if (!ret)
5794                 ret = -EINVAL;
5795
5796         dev_err(&hdev->pdev->dev,
5797                 "PF failed to add unicast entry(%pM) in the MAC table\n",
5798                 addr);
5799
5800         return ret;
5801 }
5802
5803 static int hclge_rm_uc_addr(struct hnae3_handle *handle,
5804                             const unsigned char *addr)
5805 {
5806         struct hclge_vport *vport = hclge_get_vport(handle);
5807
5808         return hclge_rm_uc_addr_common(vport, addr);
5809 }
5810
5811 int hclge_rm_uc_addr_common(struct hclge_vport *vport,
5812                             const unsigned char *addr)
5813 {
5814         struct hclge_dev *hdev = vport->back;
5815         struct hclge_mac_vlan_tbl_entry_cmd req;
5816         int ret;
5817
5818         /* mac addr check */
5819         if (is_zero_ether_addr(addr) ||
5820             is_broadcast_ether_addr(addr) ||
5821             is_multicast_ether_addr(addr)) {
5822                 dev_dbg(&hdev->pdev->dev,
5823                         "Remove mac err! invalid mac:%pM.\n",
5824                          addr);
5825                 return -EINVAL;
5826         }
5827
5828         memset(&req, 0, sizeof(req));
5829         hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5830         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
5831         hclge_prepare_mac_addr(&req, addr);
5832         ret = hclge_remove_mac_vlan_tbl(vport, &req);
5833         if (!ret)
5834                 hclge_update_umv_space(vport, true);
5835
5836         return ret;
5837 }
5838
5839 static int hclge_add_mc_addr(struct hnae3_handle *handle,
5840                              const unsigned char *addr)
5841 {
5842         struct hclge_vport *vport = hclge_get_vport(handle);
5843
5844         return hclge_add_mc_addr_common(vport, addr);
5845 }
5846
5847 int hclge_add_mc_addr_common(struct hclge_vport *vport,
5848                              const unsigned char *addr)
5849 {
5850         struct hclge_dev *hdev = vport->back;
5851         struct hclge_mac_vlan_tbl_entry_cmd req;
5852         struct hclge_desc desc[3];
5853         int status;
5854
5855         /* mac addr check */
5856         if (!is_multicast_ether_addr(addr)) {
5857                 dev_err(&hdev->pdev->dev,
5858                         "Add mc mac err! invalid mac:%pM.\n",
5859                          addr);
5860                 return -EINVAL;
5861         }
5862         memset(&req, 0, sizeof(req));
5863         hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5864         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
5865         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
5866         hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5867         hclge_prepare_mac_addr(&req, addr);
5868         status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
5869         if (!status) {
5870                 /* This mac addr exist, update VFID for it */
5871                 hclge_update_desc_vfid(desc, vport->vport_id, false);
5872                 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
5873         } else {
5874                 /* This mac addr do not exist, add new entry for it */
5875                 memset(desc[0].data, 0, sizeof(desc[0].data));
5876                 memset(desc[1].data, 0, sizeof(desc[0].data));
5877                 memset(desc[2].data, 0, sizeof(desc[0].data));
5878                 hclge_update_desc_vfid(desc, vport->vport_id, false);
5879                 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
5880         }
5881
5882         if (status == -ENOSPC)
5883                 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n");
5884
5885         return status;
5886 }
5887
5888 static int hclge_rm_mc_addr(struct hnae3_handle *handle,
5889                             const unsigned char *addr)
5890 {
5891         struct hclge_vport *vport = hclge_get_vport(handle);
5892
5893         return hclge_rm_mc_addr_common(vport, addr);
5894 }
5895
5896 int hclge_rm_mc_addr_common(struct hclge_vport *vport,
5897                             const unsigned char *addr)
5898 {
5899         struct hclge_dev *hdev = vport->back;
5900         struct hclge_mac_vlan_tbl_entry_cmd req;
5901         enum hclge_cmd_status status;
5902         struct hclge_desc desc[3];
5903
5904         /* mac addr check */
5905         if (!is_multicast_ether_addr(addr)) {
5906                 dev_dbg(&hdev->pdev->dev,
5907                         "Remove mc mac err! invalid mac:%pM.\n",
5908                          addr);
5909                 return -EINVAL;
5910         }
5911
5912         memset(&req, 0, sizeof(req));
5913         hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5914         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
5915         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
5916         hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5917         hclge_prepare_mac_addr(&req, addr);
5918         status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
5919         if (!status) {
5920                 /* This mac addr exist, remove this handle's VFID for it */
5921                 hclge_update_desc_vfid(desc, vport->vport_id, true);
5922
5923                 if (hclge_is_all_function_id_zero(desc))
5924                         /* All the vfid is zero, so need to delete this entry */
5925                         status = hclge_remove_mac_vlan_tbl(vport, &req);
5926                 else
5927                         /* Not all the vfid is zero, update the vfid */
5928                         status = hclge_add_mac_vlan_tbl(vport, &req, desc);
5929
5930         } else {
5931                 /* Maybe this mac address is in mta table, but it cannot be
5932                  * deleted here because an entry of mta represents an address
5933                  * range rather than a specific address. the delete action to
5934                  * all entries will take effect in update_mta_status called by
5935                  * hns3_nic_set_rx_mode.
5936                  */
5937                 status = 0;
5938         }
5939
5940         return status;
5941 }
5942
5943 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev,
5944                                               u16 cmdq_resp, u8 resp_code)
5945 {
5946 #define HCLGE_ETHERTYPE_SUCCESS_ADD             0
5947 #define HCLGE_ETHERTYPE_ALREADY_ADD             1
5948 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW        2
5949 #define HCLGE_ETHERTYPE_KEY_CONFLICT            3
5950
5951         int return_status;
5952
5953         if (cmdq_resp) {
5954                 dev_err(&hdev->pdev->dev,
5955                         "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
5956                         cmdq_resp);
5957                 return -EIO;
5958         }
5959
5960         switch (resp_code) {
5961         case HCLGE_ETHERTYPE_SUCCESS_ADD:
5962         case HCLGE_ETHERTYPE_ALREADY_ADD:
5963                 return_status = 0;
5964                 break;
5965         case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW:
5966                 dev_err(&hdev->pdev->dev,
5967                         "add mac ethertype failed for manager table overflow.\n");
5968                 return_status = -EIO;
5969                 break;
5970         case HCLGE_ETHERTYPE_KEY_CONFLICT:
5971                 dev_err(&hdev->pdev->dev,
5972                         "add mac ethertype failed for key conflict.\n");
5973                 return_status = -EIO;
5974                 break;
5975         default:
5976                 dev_err(&hdev->pdev->dev,
5977                         "add mac ethertype failed for undefined, code=%d.\n",
5978                         resp_code);
5979                 return_status = -EIO;
5980         }
5981
5982         return return_status;
5983 }
5984
5985 static int hclge_add_mgr_tbl(struct hclge_dev *hdev,
5986                              const struct hclge_mac_mgr_tbl_entry_cmd *req)
5987 {
5988         struct hclge_desc desc;
5989         u8 resp_code;
5990         u16 retval;
5991         int ret;
5992
5993         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false);
5994         memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd));
5995
5996         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5997         if (ret) {
5998                 dev_err(&hdev->pdev->dev,
5999                         "add mac ethertype failed for cmd_send, ret =%d.\n",
6000                         ret);
6001                 return ret;
6002         }
6003
6004         resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
6005         retval = le16_to_cpu(desc.retval);
6006
6007         return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code);
6008 }
6009
6010 static int init_mgr_tbl(struct hclge_dev *hdev)
6011 {
6012         int ret;
6013         int i;
6014
6015         for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) {
6016                 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]);
6017                 if (ret) {
6018                         dev_err(&hdev->pdev->dev,
6019                                 "add mac ethertype failed, ret =%d.\n",
6020                                 ret);
6021                         return ret;
6022                 }
6023         }
6024
6025         return 0;
6026 }
6027
6028 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
6029 {
6030         struct hclge_vport *vport = hclge_get_vport(handle);
6031         struct hclge_dev *hdev = vport->back;
6032
6033         ether_addr_copy(p, hdev->hw.mac.mac_addr);
6034 }
6035
6036 static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p,
6037                               bool is_first)
6038 {
6039         const unsigned char *new_addr = (const unsigned char *)p;
6040         struct hclge_vport *vport = hclge_get_vport(handle);
6041         struct hclge_dev *hdev = vport->back;
6042         int ret;
6043
6044         /* mac addr check */
6045         if (is_zero_ether_addr(new_addr) ||
6046             is_broadcast_ether_addr(new_addr) ||
6047             is_multicast_ether_addr(new_addr)) {
6048                 dev_err(&hdev->pdev->dev,
6049                         "Change uc mac err! invalid mac:%p.\n",
6050                          new_addr);
6051                 return -EINVAL;
6052         }
6053
6054         if (!is_first && hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr))
6055                 dev_warn(&hdev->pdev->dev,
6056                          "remove old uc mac address fail.\n");
6057
6058         ret = hclge_add_uc_addr(handle, new_addr);
6059         if (ret) {
6060                 dev_err(&hdev->pdev->dev,
6061                         "add uc mac address fail, ret =%d.\n",
6062                         ret);
6063
6064                 if (!is_first &&
6065                     hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr))
6066                         dev_err(&hdev->pdev->dev,
6067                                 "restore uc mac address fail.\n");
6068
6069                 return -EIO;
6070         }
6071
6072         ret = hclge_pause_addr_cfg(hdev, new_addr);
6073         if (ret) {
6074                 dev_err(&hdev->pdev->dev,
6075                         "configure mac pause address fail, ret =%d.\n",
6076                         ret);
6077                 return -EIO;
6078         }
6079
6080         ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
6081
6082         return 0;
6083 }
6084
6085 static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr,
6086                           int cmd)
6087 {
6088         struct hclge_vport *vport = hclge_get_vport(handle);
6089         struct hclge_dev *hdev = vport->back;
6090
6091         if (!hdev->hw.mac.phydev)
6092                 return -EOPNOTSUPP;
6093
6094         return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd);
6095 }
6096
6097 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
6098                                       u8 fe_type, bool filter_en)
6099 {
6100         struct hclge_vlan_filter_ctrl_cmd *req;
6101         struct hclge_desc desc;
6102         int ret;
6103
6104         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
6105
6106         req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
6107         req->vlan_type = vlan_type;
6108         req->vlan_fe = filter_en ? fe_type : 0;
6109
6110         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6111         if (ret)
6112                 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
6113                         ret);
6114
6115         return ret;
6116 }
6117
6118 #define HCLGE_FILTER_TYPE_VF            0
6119 #define HCLGE_FILTER_TYPE_PORT          1
6120 #define HCLGE_FILTER_FE_EGRESS_V1_B     BIT(0)
6121 #define HCLGE_FILTER_FE_NIC_INGRESS_B   BIT(0)
6122 #define HCLGE_FILTER_FE_NIC_EGRESS_B    BIT(1)
6123 #define HCLGE_FILTER_FE_ROCE_INGRESS_B  BIT(2)
6124 #define HCLGE_FILTER_FE_ROCE_EGRESS_B   BIT(3)
6125 #define HCLGE_FILTER_FE_EGRESS          (HCLGE_FILTER_FE_NIC_EGRESS_B \
6126                                         | HCLGE_FILTER_FE_ROCE_EGRESS_B)
6127 #define HCLGE_FILTER_FE_INGRESS         (HCLGE_FILTER_FE_NIC_INGRESS_B \
6128                                         | HCLGE_FILTER_FE_ROCE_INGRESS_B)
6129
6130 static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
6131 {
6132         struct hclge_vport *vport = hclge_get_vport(handle);
6133         struct hclge_dev *hdev = vport->back;
6134
6135         if (hdev->pdev->revision >= 0x21) {
6136                 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
6137                                            HCLGE_FILTER_FE_EGRESS, enable);
6138                 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT,
6139                                            HCLGE_FILTER_FE_INGRESS, enable);
6140         } else {
6141                 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
6142                                            HCLGE_FILTER_FE_EGRESS_V1_B, enable);
6143         }
6144         if (enable)
6145                 handle->netdev_flags |= HNAE3_VLAN_FLTR;
6146         else
6147                 handle->netdev_flags &= ~HNAE3_VLAN_FLTR;
6148 }
6149
6150 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
6151                                     bool is_kill, u16 vlan, u8 qos,
6152                                     __be16 proto)
6153 {
6154 #define HCLGE_MAX_VF_BYTES  16
6155         struct hclge_vlan_filter_vf_cfg_cmd *req0;
6156         struct hclge_vlan_filter_vf_cfg_cmd *req1;
6157         struct hclge_desc desc[2];
6158         u8 vf_byte_val;
6159         u8 vf_byte_off;
6160         int ret;
6161
6162         hclge_cmd_setup_basic_desc(&desc[0],
6163                                    HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
6164         hclge_cmd_setup_basic_desc(&desc[1],
6165                                    HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
6166
6167         desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
6168
6169         vf_byte_off = vfid / 8;
6170         vf_byte_val = 1 << (vfid % 8);
6171
6172         req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
6173         req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
6174
6175         req0->vlan_id  = cpu_to_le16(vlan);
6176         req0->vlan_cfg = is_kill;
6177
6178         if (vf_byte_off < HCLGE_MAX_VF_BYTES)
6179                 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
6180         else
6181                 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
6182
6183         ret = hclge_cmd_send(&hdev->hw, desc, 2);
6184         if (ret) {
6185                 dev_err(&hdev->pdev->dev,
6186                         "Send vf vlan command fail, ret =%d.\n",
6187                         ret);
6188                 return ret;
6189         }
6190
6191         if (!is_kill) {
6192 #define HCLGE_VF_VLAN_NO_ENTRY  2
6193                 if (!req0->resp_code || req0->resp_code == 1)
6194                         return 0;
6195
6196                 if (req0->resp_code == HCLGE_VF_VLAN_NO_ENTRY) {
6197                         dev_warn(&hdev->pdev->dev,
6198                                  "vf vlan table is full, vf vlan filter is disabled\n");
6199                         return 0;
6200                 }
6201
6202                 dev_err(&hdev->pdev->dev,
6203                         "Add vf vlan filter fail, ret =%d.\n",
6204                         req0->resp_code);
6205         } else {
6206 #define HCLGE_VF_VLAN_DEL_NO_FOUND      1
6207                 if (!req0->resp_code)
6208                         return 0;
6209
6210                 if (req0->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) {
6211                         dev_warn(&hdev->pdev->dev,
6212                                  "vlan %d filter is not in vf vlan table\n",
6213                                  vlan);
6214                         return 0;
6215                 }
6216
6217                 dev_err(&hdev->pdev->dev,
6218                         "Kill vf vlan filter fail, ret =%d.\n",
6219                         req0->resp_code);
6220         }
6221
6222         return -EIO;
6223 }
6224
6225 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto,
6226                                       u16 vlan_id, bool is_kill)
6227 {
6228         struct hclge_vlan_filter_pf_cfg_cmd *req;
6229         struct hclge_desc desc;
6230         u8 vlan_offset_byte_val;
6231         u8 vlan_offset_byte;
6232         u8 vlan_offset_160;
6233         int ret;
6234
6235         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
6236
6237         vlan_offset_160 = vlan_id / 160;
6238         vlan_offset_byte = (vlan_id % 160) / 8;
6239         vlan_offset_byte_val = 1 << (vlan_id % 8);
6240
6241         req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
6242         req->vlan_offset = vlan_offset_160;
6243         req->vlan_cfg = is_kill;
6244         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
6245
6246         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6247         if (ret)
6248                 dev_err(&hdev->pdev->dev,
6249                         "port vlan command, send fail, ret =%d.\n", ret);
6250         return ret;
6251 }
6252
6253 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto,
6254                                     u16 vport_id, u16 vlan_id, u8 qos,
6255                                     bool is_kill)
6256 {
6257         u16 vport_idx, vport_num = 0;
6258         int ret;
6259
6260         if (is_kill && !vlan_id)
6261                 return 0;
6262
6263         ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id,
6264                                        0, proto);
6265         if (ret) {
6266                 dev_err(&hdev->pdev->dev,
6267                         "Set %d vport vlan filter config fail, ret =%d.\n",
6268                         vport_id, ret);
6269                 return ret;
6270         }
6271
6272         /* vlan 0 may be added twice when 8021q module is enabled */
6273         if (!is_kill && !vlan_id &&
6274             test_bit(vport_id, hdev->vlan_table[vlan_id]))
6275                 return 0;
6276
6277         if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) {
6278                 dev_err(&hdev->pdev->dev,
6279                         "Add port vlan failed, vport %d is already in vlan %d\n",
6280                         vport_id, vlan_id);
6281                 return -EINVAL;
6282         }
6283
6284         if (is_kill &&
6285             !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) {
6286                 dev_err(&hdev->pdev->dev,
6287                         "Delete port vlan failed, vport %d is not in vlan %d\n",
6288                         vport_id, vlan_id);
6289                 return -EINVAL;
6290         }
6291
6292         for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM)
6293                 vport_num++;
6294
6295         if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1))
6296                 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id,
6297                                                  is_kill);
6298
6299         return ret;
6300 }
6301
6302 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
6303                           u16 vlan_id, bool is_kill)
6304 {
6305         struct hclge_vport *vport = hclge_get_vport(handle);
6306         struct hclge_dev *hdev = vport->back;
6307
6308         return hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, vlan_id,
6309                                         0, is_kill);
6310 }
6311
6312 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
6313                                     u16 vlan, u8 qos, __be16 proto)
6314 {
6315         struct hclge_vport *vport = hclge_get_vport(handle);
6316         struct hclge_dev *hdev = vport->back;
6317
6318         if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
6319                 return -EINVAL;
6320         if (proto != htons(ETH_P_8021Q))
6321                 return -EPROTONOSUPPORT;
6322
6323         return hclge_set_vlan_filter_hw(hdev, proto, vfid, vlan, qos, false);
6324 }
6325
6326 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
6327 {
6328         struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
6329         struct hclge_vport_vtag_tx_cfg_cmd *req;
6330         struct hclge_dev *hdev = vport->back;
6331         struct hclge_desc desc;
6332         int status;
6333
6334         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
6335
6336         req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
6337         req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
6338         req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
6339         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B,
6340                       vcfg->accept_tag1 ? 1 : 0);
6341         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B,
6342                       vcfg->accept_untag1 ? 1 : 0);
6343         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B,
6344                       vcfg->accept_tag2 ? 1 : 0);
6345         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B,
6346                       vcfg->accept_untag2 ? 1 : 0);
6347         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
6348                       vcfg->insert_tag1_en ? 1 : 0);
6349         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
6350                       vcfg->insert_tag2_en ? 1 : 0);
6351         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
6352
6353         req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
6354         req->vf_bitmap[req->vf_offset] =
6355                 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
6356
6357         status = hclge_cmd_send(&hdev->hw, &desc, 1);
6358         if (status)
6359                 dev_err(&hdev->pdev->dev,
6360                         "Send port txvlan cfg command fail, ret =%d\n",
6361                         status);
6362
6363         return status;
6364 }
6365
6366 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
6367 {
6368         struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
6369         struct hclge_vport_vtag_rx_cfg_cmd *req;
6370         struct hclge_dev *hdev = vport->back;
6371         struct hclge_desc desc;
6372         int status;
6373
6374         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
6375
6376         req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
6377         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
6378                       vcfg->strip_tag1_en ? 1 : 0);
6379         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
6380                       vcfg->strip_tag2_en ? 1 : 0);
6381         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
6382                       vcfg->vlan1_vlan_prionly ? 1 : 0);
6383         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
6384                       vcfg->vlan2_vlan_prionly ? 1 : 0);
6385
6386         req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
6387         req->vf_bitmap[req->vf_offset] =
6388                 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
6389
6390         status = hclge_cmd_send(&hdev->hw, &desc, 1);
6391         if (status)
6392                 dev_err(&hdev->pdev->dev,
6393                         "Send port rxvlan cfg command fail, ret =%d\n",
6394                         status);
6395
6396         return status;
6397 }
6398
6399 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
6400 {
6401         struct hclge_rx_vlan_type_cfg_cmd *rx_req;
6402         struct hclge_tx_vlan_type_cfg_cmd *tx_req;
6403         struct hclge_desc desc;
6404         int status;
6405
6406         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
6407         rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
6408         rx_req->ot_fst_vlan_type =
6409                 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
6410         rx_req->ot_sec_vlan_type =
6411                 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
6412         rx_req->in_fst_vlan_type =
6413                 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
6414         rx_req->in_sec_vlan_type =
6415                 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
6416
6417         status = hclge_cmd_send(&hdev->hw, &desc, 1);
6418         if (status) {
6419                 dev_err(&hdev->pdev->dev,
6420                         "Send rxvlan protocol type command fail, ret =%d\n",
6421                         status);
6422                 return status;
6423         }
6424
6425         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
6426
6427         tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data;
6428         tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
6429         tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
6430
6431         status = hclge_cmd_send(&hdev->hw, &desc, 1);
6432         if (status)
6433                 dev_err(&hdev->pdev->dev,
6434                         "Send txvlan protocol type command fail, ret =%d\n",
6435                         status);
6436
6437         return status;
6438 }
6439
6440 static int hclge_init_vlan_config(struct hclge_dev *hdev)
6441 {
6442 #define HCLGE_DEF_VLAN_TYPE             0x8100
6443
6444         struct hnae3_handle *handle = &hdev->vport[0].nic;
6445         struct hclge_vport *vport;
6446         int ret;
6447         int i;
6448
6449         if (hdev->pdev->revision >= 0x21) {
6450                 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
6451                                                  HCLGE_FILTER_FE_EGRESS, true);
6452                 if (ret)
6453                         return ret;
6454
6455                 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT,
6456                                                  HCLGE_FILTER_FE_INGRESS, true);
6457                 if (ret)
6458                         return ret;
6459         } else {
6460                 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
6461                                                  HCLGE_FILTER_FE_EGRESS_V1_B,
6462                                                  true);
6463                 if (ret)
6464                         return ret;
6465         }
6466
6467         handle->netdev_flags |= HNAE3_VLAN_FLTR;
6468
6469         hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
6470         hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
6471         hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
6472         hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
6473         hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE;
6474         hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE;
6475
6476         ret = hclge_set_vlan_protocol_type(hdev);
6477         if (ret)
6478                 return ret;
6479
6480         for (i = 0; i < hdev->num_alloc_vport; i++) {
6481                 vport = &hdev->vport[i];
6482                 vport->txvlan_cfg.accept_tag1 = true;
6483                 vport->txvlan_cfg.accept_untag1 = true;
6484
6485                 /* accept_tag2 and accept_untag2 are not supported on
6486                  * pdev revision(0x20), new revision support them. The
6487                  * value of this two fields will not return error when driver
6488                  * send command to fireware in revision(0x20).
6489                  * This two fields can not configured by user.
6490                  */
6491                 vport->txvlan_cfg.accept_tag2 = true;
6492                 vport->txvlan_cfg.accept_untag2 = true;
6493
6494                 vport->txvlan_cfg.insert_tag1_en = false;
6495                 vport->txvlan_cfg.insert_tag2_en = false;
6496                 vport->txvlan_cfg.default_tag1 = 0;
6497                 vport->txvlan_cfg.default_tag2 = 0;
6498
6499                 ret = hclge_set_vlan_tx_offload_cfg(vport);
6500                 if (ret)
6501                         return ret;
6502
6503                 vport->rxvlan_cfg.strip_tag1_en = false;
6504                 vport->rxvlan_cfg.strip_tag2_en = true;
6505                 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
6506                 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
6507
6508                 ret = hclge_set_vlan_rx_offload_cfg(vport);
6509                 if (ret)
6510                         return ret;
6511         }
6512
6513         return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
6514 }
6515
6516 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
6517 {
6518         struct hclge_vport *vport = hclge_get_vport(handle);
6519
6520         vport->rxvlan_cfg.strip_tag1_en = false;
6521         vport->rxvlan_cfg.strip_tag2_en = enable;
6522         vport->rxvlan_cfg.vlan1_vlan_prionly = false;
6523         vport->rxvlan_cfg.vlan2_vlan_prionly = false;
6524
6525         return hclge_set_vlan_rx_offload_cfg(vport);
6526 }
6527
6528 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps)
6529 {
6530         struct hclge_config_max_frm_size_cmd *req;
6531         struct hclge_desc desc;
6532
6533         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
6534
6535         req = (struct hclge_config_max_frm_size_cmd *)desc.data;
6536         req->max_frm_size = cpu_to_le16(new_mps);
6537         req->min_frm_size = HCLGE_MAC_MIN_FRAME;
6538
6539         return hclge_cmd_send(&hdev->hw, &desc, 1);
6540 }
6541
6542 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
6543 {
6544         struct hclge_vport *vport = hclge_get_vport(handle);
6545
6546         return hclge_set_vport_mtu(vport, new_mtu);
6547 }
6548
6549 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu)
6550 {
6551         struct hclge_dev *hdev = vport->back;
6552         int i, max_frm_size, ret = 0;
6553
6554         max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN;
6555         if (max_frm_size < HCLGE_MAC_MIN_FRAME ||
6556             max_frm_size > HCLGE_MAC_MAX_FRAME)
6557                 return -EINVAL;
6558
6559         max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
6560         mutex_lock(&hdev->vport_lock);
6561         /* VF's mps must fit within hdev->mps */
6562         if (vport->vport_id && max_frm_size > hdev->mps) {
6563                 mutex_unlock(&hdev->vport_lock);
6564                 return -EINVAL;
6565         } else if (vport->vport_id) {
6566                 vport->mps = max_frm_size;
6567                 mutex_unlock(&hdev->vport_lock);
6568                 return 0;
6569         }
6570
6571         /* PF's mps must be greater then VF's mps */
6572         for (i = 1; i < hdev->num_alloc_vport; i++)
6573                 if (max_frm_size < hdev->vport[i].mps) {
6574                         mutex_unlock(&hdev->vport_lock);
6575                         return -EINVAL;
6576                 }
6577
6578         hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
6579
6580         ret = hclge_set_mac_mtu(hdev, max_frm_size);
6581         if (ret) {
6582                 dev_err(&hdev->pdev->dev,
6583                         "Change mtu fail, ret =%d\n", ret);
6584                 goto out;
6585         }
6586
6587         hdev->mps = max_frm_size;
6588         vport->mps = max_frm_size;
6589
6590         ret = hclge_buffer_alloc(hdev);
6591         if (ret)
6592                 dev_err(&hdev->pdev->dev,
6593                         "Allocate buffer fail, ret =%d\n", ret);
6594
6595 out:
6596         hclge_notify_client(hdev, HNAE3_UP_CLIENT);
6597         mutex_unlock(&hdev->vport_lock);
6598         return ret;
6599 }
6600
6601 static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
6602                                     bool enable)
6603 {
6604         struct hclge_reset_tqp_queue_cmd *req;
6605         struct hclge_desc desc;
6606         int ret;
6607
6608         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
6609
6610         req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
6611         req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
6612         hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
6613
6614         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6615         if (ret) {
6616                 dev_err(&hdev->pdev->dev,
6617                         "Send tqp reset cmd error, status =%d\n", ret);
6618                 return ret;
6619         }
6620
6621         return 0;
6622 }
6623
6624 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
6625 {
6626         struct hclge_reset_tqp_queue_cmd *req;
6627         struct hclge_desc desc;
6628         int ret;
6629
6630         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
6631
6632         req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
6633         req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
6634
6635         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6636         if (ret) {
6637                 dev_err(&hdev->pdev->dev,
6638                         "Get reset status error, status =%d\n", ret);
6639                 return ret;
6640         }
6641
6642         return hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
6643 }
6644
6645 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id)
6646 {
6647         struct hnae3_queue *queue;
6648         struct hclge_tqp *tqp;
6649
6650         queue = handle->kinfo.tqp[queue_id];
6651         tqp = container_of(queue, struct hclge_tqp, q);
6652
6653         return tqp->index;
6654 }
6655
6656 int hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
6657 {
6658         struct hclge_vport *vport = hclge_get_vport(handle);
6659         struct hclge_dev *hdev = vport->back;
6660         int reset_try_times = 0;
6661         int reset_status;
6662         u16 queue_gid;
6663         int ret = 0;
6664
6665         queue_gid = hclge_covert_handle_qid_global(handle, queue_id);
6666
6667         ret = hclge_tqp_enable(hdev, queue_id, 0, false);
6668         if (ret) {
6669                 dev_err(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
6670                 return ret;
6671         }
6672
6673         ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
6674         if (ret) {
6675                 dev_err(&hdev->pdev->dev,
6676                         "Send reset tqp cmd fail, ret = %d\n", ret);
6677                 return ret;
6678         }
6679
6680         reset_try_times = 0;
6681         while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
6682                 /* Wait for tqp hw reset */
6683                 msleep(20);
6684                 reset_status = hclge_get_reset_status(hdev, queue_gid);
6685                 if (reset_status)
6686                         break;
6687         }
6688
6689         if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
6690                 dev_err(&hdev->pdev->dev, "Reset TQP fail\n");
6691                 return ret;
6692         }
6693
6694         ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
6695         if (ret)
6696                 dev_err(&hdev->pdev->dev,
6697                         "Deassert the soft reset fail, ret = %d\n", ret);
6698
6699         return ret;
6700 }
6701
6702 void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id)
6703 {
6704         struct hclge_dev *hdev = vport->back;
6705         int reset_try_times = 0;
6706         int reset_status;
6707         u16 queue_gid;
6708         int ret;
6709
6710         queue_gid = hclge_covert_handle_qid_global(&vport->nic, queue_id);
6711
6712         ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
6713         if (ret) {
6714                 dev_warn(&hdev->pdev->dev,
6715                          "Send reset tqp cmd fail, ret = %d\n", ret);
6716                 return;
6717         }
6718
6719         reset_try_times = 0;
6720         while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
6721                 /* Wait for tqp hw reset */
6722                 msleep(20);
6723                 reset_status = hclge_get_reset_status(hdev, queue_gid);
6724                 if (reset_status)
6725                         break;
6726         }
6727
6728         if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
6729                 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
6730                 return;
6731         }
6732
6733         ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
6734         if (ret)
6735                 dev_warn(&hdev->pdev->dev,
6736                          "Deassert the soft reset fail, ret = %d\n", ret);
6737 }
6738
6739 static u32 hclge_get_fw_version(struct hnae3_handle *handle)
6740 {
6741         struct hclge_vport *vport = hclge_get_vport(handle);
6742         struct hclge_dev *hdev = vport->back;
6743
6744         return hdev->fw_version;
6745 }
6746
6747 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
6748 {
6749         struct phy_device *phydev = hdev->hw.mac.phydev;
6750
6751         if (!phydev)
6752                 return;
6753
6754         phy_set_asym_pause(phydev, rx_en, tx_en);
6755 }
6756
6757 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
6758 {
6759         int ret;
6760
6761         if (rx_en && tx_en)
6762                 hdev->fc_mode_last_time = HCLGE_FC_FULL;
6763         else if (rx_en && !tx_en)
6764                 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
6765         else if (!rx_en && tx_en)
6766                 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
6767         else
6768                 hdev->fc_mode_last_time = HCLGE_FC_NONE;
6769
6770         if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
6771                 return 0;
6772
6773         ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
6774         if (ret) {
6775                 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n",
6776                         ret);
6777                 return ret;
6778         }
6779
6780         hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
6781
6782         return 0;
6783 }
6784
6785 int hclge_cfg_flowctrl(struct hclge_dev *hdev)
6786 {
6787         struct phy_device *phydev = hdev->hw.mac.phydev;
6788         u16 remote_advertising = 0;
6789         u16 local_advertising = 0;
6790         u32 rx_pause, tx_pause;
6791         u8 flowctl;
6792
6793         if (!phydev->link || !phydev->autoneg)
6794                 return 0;
6795
6796         local_advertising = linkmode_adv_to_lcl_adv_t(phydev->advertising);
6797
6798         if (phydev->pause)
6799                 remote_advertising = LPA_PAUSE_CAP;
6800
6801         if (phydev->asym_pause)
6802                 remote_advertising |= LPA_PAUSE_ASYM;
6803
6804         flowctl = mii_resolve_flowctrl_fdx(local_advertising,
6805                                            remote_advertising);
6806         tx_pause = flowctl & FLOW_CTRL_TX;
6807         rx_pause = flowctl & FLOW_CTRL_RX;
6808
6809         if (phydev->duplex == HCLGE_MAC_HALF) {
6810                 tx_pause = 0;
6811                 rx_pause = 0;
6812         }
6813
6814         return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
6815 }
6816
6817 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
6818                                  u32 *rx_en, u32 *tx_en)
6819 {
6820         struct hclge_vport *vport = hclge_get_vport(handle);
6821         struct hclge_dev *hdev = vport->back;
6822
6823         *auto_neg = hclge_get_autoneg(handle);
6824
6825         if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
6826                 *rx_en = 0;
6827                 *tx_en = 0;
6828                 return;
6829         }
6830
6831         if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
6832                 *rx_en = 1;
6833                 *tx_en = 0;
6834         } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
6835                 *tx_en = 1;
6836                 *rx_en = 0;
6837         } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
6838                 *rx_en = 1;
6839                 *tx_en = 1;
6840         } else {
6841                 *rx_en = 0;
6842                 *tx_en = 0;
6843         }
6844 }
6845
6846 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
6847                                 u32 rx_en, u32 tx_en)
6848 {
6849         struct hclge_vport *vport = hclge_get_vport(handle);
6850         struct hclge_dev *hdev = vport->back;
6851         struct phy_device *phydev = hdev->hw.mac.phydev;
6852         u32 fc_autoneg;
6853
6854         fc_autoneg = hclge_get_autoneg(handle);
6855         if (auto_neg != fc_autoneg) {
6856                 dev_info(&hdev->pdev->dev,
6857                          "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
6858                 return -EOPNOTSUPP;
6859         }
6860
6861         if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
6862                 dev_info(&hdev->pdev->dev,
6863                          "Priority flow control enabled. Cannot set link flow control.\n");
6864                 return -EOPNOTSUPP;
6865         }
6866
6867         hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
6868
6869         if (!fc_autoneg)
6870                 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
6871
6872         /* Only support flow control negotiation for netdev with
6873          * phy attached for now.
6874          */
6875         if (!phydev)
6876                 return -EOPNOTSUPP;
6877
6878         return phy_start_aneg(phydev);
6879 }
6880
6881 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
6882                                           u8 *auto_neg, u32 *speed, u8 *duplex)
6883 {
6884         struct hclge_vport *vport = hclge_get_vport(handle);
6885         struct hclge_dev *hdev = vport->back;
6886
6887         if (speed)
6888                 *speed = hdev->hw.mac.speed;
6889         if (duplex)
6890                 *duplex = hdev->hw.mac.duplex;
6891         if (auto_neg)
6892                 *auto_neg = hdev->hw.mac.autoneg;
6893 }
6894
6895 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
6896 {
6897         struct hclge_vport *vport = hclge_get_vport(handle);
6898         struct hclge_dev *hdev = vport->back;
6899
6900         if (media_type)
6901                 *media_type = hdev->hw.mac.media_type;
6902 }
6903
6904 static void hclge_get_mdix_mode(struct hnae3_handle *handle,
6905                                 u8 *tp_mdix_ctrl, u8 *tp_mdix)
6906 {
6907         struct hclge_vport *vport = hclge_get_vport(handle);
6908         struct hclge_dev *hdev = vport->back;
6909         struct phy_device *phydev = hdev->hw.mac.phydev;
6910         int mdix_ctrl, mdix, retval, is_resolved;
6911
6912         if (!phydev) {
6913                 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
6914                 *tp_mdix = ETH_TP_MDI_INVALID;
6915                 return;
6916         }
6917
6918         phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
6919
6920         retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
6921         mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
6922                                     HCLGE_PHY_MDIX_CTRL_S);
6923
6924         retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
6925         mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
6926         is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
6927
6928         phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
6929
6930         switch (mdix_ctrl) {
6931         case 0x0:
6932                 *tp_mdix_ctrl = ETH_TP_MDI;
6933                 break;
6934         case 0x1:
6935                 *tp_mdix_ctrl = ETH_TP_MDI_X;
6936                 break;
6937         case 0x3:
6938                 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
6939                 break;
6940         default:
6941                 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
6942                 break;
6943         }
6944
6945         if (!is_resolved)
6946                 *tp_mdix = ETH_TP_MDI_INVALID;
6947         else if (mdix)
6948                 *tp_mdix = ETH_TP_MDI_X;
6949         else
6950                 *tp_mdix = ETH_TP_MDI;
6951 }
6952
6953 static int hclge_init_instance_hw(struct hclge_dev *hdev)
6954 {
6955         return hclge_mac_connect_phy(hdev);
6956 }
6957
6958 static void hclge_uninit_instance_hw(struct hclge_dev *hdev)
6959 {
6960         hclge_mac_disconnect_phy(hdev);
6961 }
6962
6963 static int hclge_init_client_instance(struct hnae3_client *client,
6964                                       struct hnae3_ae_dev *ae_dev)
6965 {
6966         struct hclge_dev *hdev = ae_dev->priv;
6967         struct hclge_vport *vport;
6968         int i, ret;
6969
6970         for (i = 0; i <  hdev->num_vmdq_vport + 1; i++) {
6971                 vport = &hdev->vport[i];
6972
6973                 switch (client->type) {
6974                 case HNAE3_CLIENT_KNIC:
6975
6976                         hdev->nic_client = client;
6977                         vport->nic.client = client;
6978                         ret = client->ops->init_instance(&vport->nic);
6979                         if (ret)
6980                                 goto clear_nic;
6981
6982                         ret = hclge_init_instance_hw(hdev);
6983                         if (ret) {
6984                                 client->ops->uninit_instance(&vport->nic,
6985                                                              0);
6986                                 goto clear_nic;
6987                         }
6988
6989                         hnae3_set_client_init_flag(client, ae_dev, 1);
6990
6991                         if (hdev->roce_client &&
6992                             hnae3_dev_roce_supported(hdev)) {
6993                                 struct hnae3_client *rc = hdev->roce_client;
6994
6995                                 ret = hclge_init_roce_base_info(vport);
6996                                 if (ret)
6997                                         goto clear_roce;
6998
6999                                 ret = rc->ops->init_instance(&vport->roce);
7000                                 if (ret)
7001                                         goto clear_roce;
7002
7003                                 hnae3_set_client_init_flag(hdev->roce_client,
7004                                                            ae_dev, 1);
7005                         }
7006
7007                         break;
7008                 case HNAE3_CLIENT_UNIC:
7009                         hdev->nic_client = client;
7010                         vport->nic.client = client;
7011
7012                         ret = client->ops->init_instance(&vport->nic);
7013                         if (ret)
7014                                 goto clear_nic;
7015
7016                         hnae3_set_client_init_flag(client, ae_dev, 1);
7017
7018                         break;
7019                 case HNAE3_CLIENT_ROCE:
7020                         if (hnae3_dev_roce_supported(hdev)) {
7021                                 hdev->roce_client = client;
7022                                 vport->roce.client = client;
7023                         }
7024
7025                         if (hdev->roce_client && hdev->nic_client) {
7026                                 ret = hclge_init_roce_base_info(vport);
7027                                 if (ret)
7028                                         goto clear_roce;
7029
7030                                 ret = client->ops->init_instance(&vport->roce);
7031                                 if (ret)
7032                                         goto clear_roce;
7033
7034                                 hnae3_set_client_init_flag(client, ae_dev, 1);
7035                         }
7036
7037                         break;
7038                 default:
7039                         return -EINVAL;
7040                 }
7041         }
7042
7043         return 0;
7044
7045 clear_nic:
7046         hdev->nic_client = NULL;
7047         vport->nic.client = NULL;
7048         return ret;
7049 clear_roce:
7050         hdev->roce_client = NULL;
7051         vport->roce.client = NULL;
7052         return ret;
7053 }
7054
7055 static void hclge_uninit_client_instance(struct hnae3_client *client,
7056                                          struct hnae3_ae_dev *ae_dev)
7057 {
7058         struct hclge_dev *hdev = ae_dev->priv;
7059         struct hclge_vport *vport;
7060         int i;
7061
7062         for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
7063                 vport = &hdev->vport[i];
7064                 if (hdev->roce_client) {
7065                         hdev->roce_client->ops->uninit_instance(&vport->roce,
7066                                                                 0);
7067                         hdev->roce_client = NULL;
7068                         vport->roce.client = NULL;
7069                 }
7070                 if (client->type == HNAE3_CLIENT_ROCE)
7071                         return;
7072                 if (hdev->nic_client && client->ops->uninit_instance) {
7073                         hclge_uninit_instance_hw(hdev);
7074                         client->ops->uninit_instance(&vport->nic, 0);
7075                         hdev->nic_client = NULL;
7076                         vport->nic.client = NULL;
7077                 }
7078         }
7079 }
7080
7081 static int hclge_pci_init(struct hclge_dev *hdev)
7082 {
7083         struct pci_dev *pdev = hdev->pdev;
7084         struct hclge_hw *hw;
7085         int ret;
7086
7087         ret = pci_enable_device(pdev);
7088         if (ret) {
7089                 dev_err(&pdev->dev, "failed to enable PCI device\n");
7090                 return ret;
7091         }
7092
7093         ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
7094         if (ret) {
7095                 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
7096                 if (ret) {
7097                         dev_err(&pdev->dev,
7098                                 "can't set consistent PCI DMA");
7099                         goto err_disable_device;
7100                 }
7101                 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
7102         }
7103
7104         ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
7105         if (ret) {
7106                 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
7107                 goto err_disable_device;
7108         }
7109
7110         pci_set_master(pdev);
7111         hw = &hdev->hw;
7112         hw->io_base = pcim_iomap(pdev, 2, 0);
7113         if (!hw->io_base) {
7114                 dev_err(&pdev->dev, "Can't map configuration register space\n");
7115                 ret = -ENOMEM;
7116                 goto err_clr_master;
7117         }
7118
7119         hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
7120
7121         return 0;
7122 err_clr_master:
7123         pci_clear_master(pdev);
7124         pci_release_regions(pdev);
7125 err_disable_device:
7126         pci_disable_device(pdev);
7127
7128         return ret;
7129 }
7130
7131 static void hclge_pci_uninit(struct hclge_dev *hdev)
7132 {
7133         struct pci_dev *pdev = hdev->pdev;
7134
7135         pcim_iounmap(pdev, hdev->hw.io_base);
7136         pci_free_irq_vectors(pdev);
7137         pci_clear_master(pdev);
7138         pci_release_mem_regions(pdev);
7139         pci_disable_device(pdev);
7140 }
7141
7142 static void hclge_state_init(struct hclge_dev *hdev)
7143 {
7144         set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
7145         set_bit(HCLGE_STATE_DOWN, &hdev->state);
7146         clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
7147         clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
7148         clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
7149         clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
7150 }
7151
7152 static void hclge_state_uninit(struct hclge_dev *hdev)
7153 {
7154         set_bit(HCLGE_STATE_DOWN, &hdev->state);
7155
7156         if (hdev->service_timer.function)
7157                 del_timer_sync(&hdev->service_timer);
7158         if (hdev->reset_timer.function)
7159                 del_timer_sync(&hdev->reset_timer);
7160         if (hdev->service_task.func)
7161                 cancel_work_sync(&hdev->service_task);
7162         if (hdev->rst_service_task.func)
7163                 cancel_work_sync(&hdev->rst_service_task);
7164         if (hdev->mbx_service_task.func)
7165                 cancel_work_sync(&hdev->mbx_service_task);
7166 }
7167
7168 static void hclge_flr_prepare(struct hnae3_ae_dev *ae_dev)
7169 {
7170 #define HCLGE_FLR_WAIT_MS       100
7171 #define HCLGE_FLR_WAIT_CNT      50
7172         struct hclge_dev *hdev = ae_dev->priv;
7173         int cnt = 0;
7174
7175         clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state);
7176         clear_bit(HNAE3_FLR_DONE, &hdev->flr_state);
7177         set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request);
7178         hclge_reset_event(hdev->pdev, NULL);
7179
7180         while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) &&
7181                cnt++ < HCLGE_FLR_WAIT_CNT)
7182                 msleep(HCLGE_FLR_WAIT_MS);
7183
7184         if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state))
7185                 dev_err(&hdev->pdev->dev,
7186                         "flr wait down timeout: %d\n", cnt);
7187 }
7188
7189 static void hclge_flr_done(struct hnae3_ae_dev *ae_dev)
7190 {
7191         struct hclge_dev *hdev = ae_dev->priv;
7192
7193         set_bit(HNAE3_FLR_DONE, &hdev->flr_state);
7194 }
7195
7196 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
7197 {
7198         struct pci_dev *pdev = ae_dev->pdev;
7199         struct hclge_dev *hdev;
7200         int ret;
7201
7202         hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
7203         if (!hdev) {
7204                 ret = -ENOMEM;
7205                 goto out;
7206         }
7207
7208         hdev->pdev = pdev;
7209         hdev->ae_dev = ae_dev;
7210         hdev->reset_type = HNAE3_NONE_RESET;
7211         hdev->reset_level = HNAE3_FUNC_RESET;
7212         ae_dev->priv = hdev;
7213         hdev->mps = ETH_FRAME_LEN + ETH_FCS_LEN + 2 * VLAN_HLEN;
7214
7215         mutex_init(&hdev->vport_lock);
7216
7217         ret = hclge_pci_init(hdev);
7218         if (ret) {
7219                 dev_err(&pdev->dev, "PCI init failed\n");
7220                 goto out;
7221         }
7222
7223         /* Firmware command queue initialize */
7224         ret = hclge_cmd_queue_init(hdev);
7225         if (ret) {
7226                 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
7227                 goto err_pci_uninit;
7228         }
7229
7230         /* Firmware command initialize */
7231         ret = hclge_cmd_init(hdev);
7232         if (ret)
7233                 goto err_cmd_uninit;
7234
7235         ret = hclge_get_cap(hdev);
7236         if (ret) {
7237                 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
7238                         ret);
7239                 goto err_cmd_uninit;
7240         }
7241
7242         ret = hclge_configure(hdev);
7243         if (ret) {
7244                 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
7245                 goto err_cmd_uninit;
7246         }
7247
7248         ret = hclge_init_msi(hdev);
7249         if (ret) {
7250                 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
7251                 goto err_cmd_uninit;
7252         }
7253
7254         ret = hclge_misc_irq_init(hdev);
7255         if (ret) {
7256                 dev_err(&pdev->dev,
7257                         "Misc IRQ(vector0) init error, ret = %d.\n",
7258                         ret);
7259                 goto err_msi_uninit;
7260         }
7261
7262         ret = hclge_alloc_tqps(hdev);
7263         if (ret) {
7264                 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
7265                 goto err_msi_irq_uninit;
7266         }
7267
7268         ret = hclge_alloc_vport(hdev);
7269         if (ret) {
7270                 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
7271                 goto err_msi_irq_uninit;
7272         }
7273
7274         ret = hclge_map_tqp(hdev);
7275         if (ret) {
7276                 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
7277                 goto err_msi_irq_uninit;
7278         }
7279
7280         if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) {
7281                 ret = hclge_mac_mdio_config(hdev);
7282                 if (ret) {
7283                         dev_err(&hdev->pdev->dev,
7284                                 "mdio config fail ret=%d\n", ret);
7285                         goto err_msi_irq_uninit;
7286                 }
7287         }
7288
7289         ret = hclge_init_umv_space(hdev);
7290         if (ret) {
7291                 dev_err(&pdev->dev, "umv space init error, ret=%d.\n", ret);
7292                 goto err_msi_irq_uninit;
7293         }
7294
7295         ret = hclge_mac_init(hdev);
7296         if (ret) {
7297                 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
7298                 goto err_mdiobus_unreg;
7299         }
7300
7301         ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
7302         if (ret) {
7303                 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
7304                 goto err_mdiobus_unreg;
7305         }
7306
7307         ret = hclge_config_gro(hdev, true);
7308         if (ret)
7309                 goto err_mdiobus_unreg;
7310
7311         ret = hclge_init_vlan_config(hdev);
7312         if (ret) {
7313                 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
7314                 goto err_mdiobus_unreg;
7315         }
7316
7317         ret = hclge_tm_schd_init(hdev);
7318         if (ret) {
7319                 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
7320                 goto err_mdiobus_unreg;
7321         }
7322
7323         hclge_rss_init_cfg(hdev);
7324         ret = hclge_rss_init_hw(hdev);
7325         if (ret) {
7326                 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
7327                 goto err_mdiobus_unreg;
7328         }
7329
7330         ret = init_mgr_tbl(hdev);
7331         if (ret) {
7332                 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret);
7333                 goto err_mdiobus_unreg;
7334         }
7335
7336         ret = hclge_init_fd_config(hdev);
7337         if (ret) {
7338                 dev_err(&pdev->dev,
7339                         "fd table init fail, ret=%d\n", ret);
7340                 goto err_mdiobus_unreg;
7341         }
7342
7343         ret = hclge_hw_error_set_state(hdev, true);
7344         if (ret) {
7345                 dev_err(&pdev->dev,
7346                         "fail(%d) to enable hw error interrupts\n", ret);
7347                 goto err_mdiobus_unreg;
7348         }
7349
7350         hclge_dcb_ops_set(hdev);
7351
7352         timer_setup(&hdev->service_timer, hclge_service_timer, 0);
7353         timer_setup(&hdev->reset_timer, hclge_reset_timer, 0);
7354         INIT_WORK(&hdev->service_task, hclge_service_task);
7355         INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
7356         INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task);
7357
7358         hclge_clear_all_event_cause(hdev);
7359
7360         /* Enable MISC vector(vector0) */
7361         hclge_enable_vector(&hdev->misc_vector, true);
7362
7363         hclge_state_init(hdev);
7364         hdev->last_reset_time = jiffies;
7365
7366         pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
7367         return 0;
7368
7369 err_mdiobus_unreg:
7370         if (hdev->hw.mac.phydev)
7371                 mdiobus_unregister(hdev->hw.mac.mdio_bus);
7372 err_msi_irq_uninit:
7373         hclge_misc_irq_uninit(hdev);
7374 err_msi_uninit:
7375         pci_free_irq_vectors(pdev);
7376 err_cmd_uninit:
7377         hclge_destroy_cmd_queue(&hdev->hw);
7378 err_pci_uninit:
7379         pcim_iounmap(pdev, hdev->hw.io_base);
7380         pci_clear_master(pdev);
7381         pci_release_regions(pdev);
7382         pci_disable_device(pdev);
7383 out:
7384         return ret;
7385 }
7386
7387 static void hclge_stats_clear(struct hclge_dev *hdev)
7388 {
7389         memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
7390 }
7391
7392 static void hclge_reset_vport_state(struct hclge_dev *hdev)
7393 {
7394         struct hclge_vport *vport = hdev->vport;
7395         int i;
7396
7397         for (i = 0; i < hdev->num_alloc_vport; i++) {
7398                 hclge_vport_start(vport);
7399                 vport++;
7400         }
7401 }
7402
7403 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
7404 {
7405         struct hclge_dev *hdev = ae_dev->priv;
7406         struct pci_dev *pdev = ae_dev->pdev;
7407         int ret;
7408
7409         set_bit(HCLGE_STATE_DOWN, &hdev->state);
7410
7411         hclge_stats_clear(hdev);
7412         memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table));
7413
7414         ret = hclge_cmd_init(hdev);
7415         if (ret) {
7416                 dev_err(&pdev->dev, "Cmd queue init failed\n");
7417                 return ret;
7418         }
7419
7420         ret = hclge_map_tqp(hdev);
7421         if (ret) {
7422                 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
7423                 return ret;
7424         }
7425
7426         hclge_reset_umv_space(hdev);
7427
7428         ret = hclge_mac_init(hdev);
7429         if (ret) {
7430                 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
7431                 return ret;
7432         }
7433
7434         ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
7435         if (ret) {
7436                 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
7437                 return ret;
7438         }
7439
7440         ret = hclge_config_gro(hdev, true);
7441         if (ret)
7442                 return ret;
7443
7444         ret = hclge_init_vlan_config(hdev);
7445         if (ret) {
7446                 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
7447                 return ret;
7448         }
7449
7450         ret = hclge_tm_init_hw(hdev);
7451         if (ret) {
7452                 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret);
7453                 return ret;
7454         }
7455
7456         ret = hclge_rss_init_hw(hdev);
7457         if (ret) {
7458                 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
7459                 return ret;
7460         }
7461
7462         ret = hclge_init_fd_config(hdev);
7463         if (ret) {
7464                 dev_err(&pdev->dev,
7465                         "fd table init fail, ret=%d\n", ret);
7466                 return ret;
7467         }
7468
7469         /* Re-enable the hw error interrupts because
7470          * the interrupts get disabled on core/global reset.
7471          */
7472         ret = hclge_hw_error_set_state(hdev, true);
7473         if (ret) {
7474                 dev_err(&pdev->dev,
7475                         "fail(%d) to re-enable HNS hw error interrupts\n", ret);
7476                 return ret;
7477         }
7478
7479         hclge_reset_vport_state(hdev);
7480
7481         dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
7482                  HCLGE_DRIVER_NAME);
7483
7484         return 0;
7485 }
7486
7487 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
7488 {
7489         struct hclge_dev *hdev = ae_dev->priv;
7490         struct hclge_mac *mac = &hdev->hw.mac;
7491
7492         hclge_state_uninit(hdev);
7493
7494         if (mac->phydev)
7495                 mdiobus_unregister(mac->mdio_bus);
7496
7497         hclge_uninit_umv_space(hdev);
7498
7499         /* Disable MISC vector(vector0) */
7500         hclge_enable_vector(&hdev->misc_vector, false);
7501         synchronize_irq(hdev->misc_vector.vector_irq);
7502
7503         hclge_hw_error_set_state(hdev, false);
7504         hclge_destroy_cmd_queue(&hdev->hw);
7505         hclge_misc_irq_uninit(hdev);
7506         hclge_pci_uninit(hdev);
7507         mutex_destroy(&hdev->vport_lock);
7508         ae_dev->priv = NULL;
7509 }
7510
7511 static u32 hclge_get_max_channels(struct hnae3_handle *handle)
7512 {
7513         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
7514         struct hclge_vport *vport = hclge_get_vport(handle);
7515         struct hclge_dev *hdev = vport->back;
7516
7517         return min_t(u32, hdev->rss_size_max,
7518                      vport->alloc_tqps / kinfo->num_tc);
7519 }
7520
7521 static void hclge_get_channels(struct hnae3_handle *handle,
7522                                struct ethtool_channels *ch)
7523 {
7524         ch->max_combined = hclge_get_max_channels(handle);
7525         ch->other_count = 1;
7526         ch->max_other = 1;
7527         ch->combined_count = handle->kinfo.rss_size;
7528 }
7529
7530 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
7531                                         u16 *alloc_tqps, u16 *max_rss_size)
7532 {
7533         struct hclge_vport *vport = hclge_get_vport(handle);
7534         struct hclge_dev *hdev = vport->back;
7535
7536         *alloc_tqps = vport->alloc_tqps;
7537         *max_rss_size = hdev->rss_size_max;
7538 }
7539
7540 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num)
7541 {
7542         struct hclge_vport *vport = hclge_get_vport(handle);
7543         struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
7544         struct hclge_dev *hdev = vport->back;
7545         int cur_rss_size = kinfo->rss_size;
7546         int cur_tqps = kinfo->num_tqps;
7547         u16 tc_offset[HCLGE_MAX_TC_NUM];
7548         u16 tc_valid[HCLGE_MAX_TC_NUM];
7549         u16 tc_size[HCLGE_MAX_TC_NUM];
7550         u16 roundup_size;
7551         u32 *rss_indir;
7552         int ret, i;
7553
7554         kinfo->req_rss_size = new_tqps_num;
7555
7556         ret = hclge_tm_vport_map_update(hdev);
7557         if (ret) {
7558                 dev_err(&hdev->pdev->dev, "tm vport map fail, ret =%d\n", ret);
7559                 return ret;
7560         }
7561
7562         roundup_size = roundup_pow_of_two(kinfo->rss_size);
7563         roundup_size = ilog2(roundup_size);
7564         /* Set the RSS TC mode according to the new RSS size */
7565         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
7566                 tc_valid[i] = 0;
7567
7568                 if (!(hdev->hw_tc_map & BIT(i)))
7569                         continue;
7570
7571                 tc_valid[i] = 1;
7572                 tc_size[i] = roundup_size;
7573                 tc_offset[i] = kinfo->rss_size * i;
7574         }
7575         ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
7576         if (ret)
7577                 return ret;
7578
7579         /* Reinitializes the rss indirect table according to the new RSS size */
7580         rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
7581         if (!rss_indir)
7582                 return -ENOMEM;
7583
7584         for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
7585                 rss_indir[i] = i % kinfo->rss_size;
7586
7587         ret = hclge_set_rss(handle, rss_indir, NULL, 0);
7588         if (ret)
7589                 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
7590                         ret);
7591
7592         kfree(rss_indir);
7593
7594         if (!ret)
7595                 dev_info(&hdev->pdev->dev,
7596                          "Channels changed, rss_size from %d to %d, tqps from %d to %d",
7597                          cur_rss_size, kinfo->rss_size,
7598                          cur_tqps, kinfo->rss_size * kinfo->num_tc);
7599
7600         return ret;
7601 }
7602
7603 static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit,
7604                               u32 *regs_num_64_bit)
7605 {
7606         struct hclge_desc desc;
7607         u32 total_num;
7608         int ret;
7609
7610         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true);
7611         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7612         if (ret) {
7613                 dev_err(&hdev->pdev->dev,
7614                         "Query register number cmd failed, ret = %d.\n", ret);
7615                 return ret;
7616         }
7617
7618         *regs_num_32_bit = le32_to_cpu(desc.data[0]);
7619         *regs_num_64_bit = le32_to_cpu(desc.data[1]);
7620
7621         total_num = *regs_num_32_bit + *regs_num_64_bit;
7622         if (!total_num)
7623                 return -EINVAL;
7624
7625         return 0;
7626 }
7627
7628 static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num,
7629                                  void *data)
7630 {
7631 #define HCLGE_32_BIT_REG_RTN_DATANUM 8
7632
7633         struct hclge_desc *desc;
7634         u32 *reg_val = data;
7635         __le32 *desc_data;
7636         int cmd_num;
7637         int i, k, n;
7638         int ret;
7639
7640         if (regs_num == 0)
7641                 return 0;
7642
7643         cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM);
7644         desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
7645         if (!desc)
7646                 return -ENOMEM;
7647
7648         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true);
7649         ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
7650         if (ret) {
7651                 dev_err(&hdev->pdev->dev,
7652                         "Query 32 bit register cmd failed, ret = %d.\n", ret);
7653                 kfree(desc);
7654                 return ret;
7655         }
7656
7657         for (i = 0; i < cmd_num; i++) {
7658                 if (i == 0) {
7659                         desc_data = (__le32 *)(&desc[i].data[0]);
7660                         n = HCLGE_32_BIT_REG_RTN_DATANUM - 2;
7661                 } else {
7662                         desc_data = (__le32 *)(&desc[i]);
7663                         n = HCLGE_32_BIT_REG_RTN_DATANUM;
7664                 }
7665                 for (k = 0; k < n; k++) {
7666                         *reg_val++ = le32_to_cpu(*desc_data++);
7667
7668                         regs_num--;
7669                         if (!regs_num)
7670                                 break;
7671                 }
7672         }
7673
7674         kfree(desc);
7675         return 0;
7676 }
7677
7678 static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num,
7679                                  void *data)
7680 {
7681 #define HCLGE_64_BIT_REG_RTN_DATANUM 4
7682
7683         struct hclge_desc *desc;
7684         u64 *reg_val = data;
7685         __le64 *desc_data;
7686         int cmd_num;
7687         int i, k, n;
7688         int ret;
7689
7690         if (regs_num == 0)
7691                 return 0;
7692
7693         cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM);
7694         desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
7695         if (!desc)
7696                 return -ENOMEM;
7697
7698         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true);
7699         ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
7700         if (ret) {
7701                 dev_err(&hdev->pdev->dev,
7702                         "Query 64 bit register cmd failed, ret = %d.\n", ret);
7703                 kfree(desc);
7704                 return ret;
7705         }
7706
7707         for (i = 0; i < cmd_num; i++) {
7708                 if (i == 0) {
7709                         desc_data = (__le64 *)(&desc[i].data[0]);
7710                         n = HCLGE_64_BIT_REG_RTN_DATANUM - 1;
7711                 } else {
7712                         desc_data = (__le64 *)(&desc[i]);
7713                         n = HCLGE_64_BIT_REG_RTN_DATANUM;
7714                 }
7715                 for (k = 0; k < n; k++) {
7716                         *reg_val++ = le64_to_cpu(*desc_data++);
7717
7718                         regs_num--;
7719                         if (!regs_num)
7720                                 break;
7721                 }
7722         }
7723
7724         kfree(desc);
7725         return 0;
7726 }
7727
7728 #define MAX_SEPARATE_NUM        4
7729 #define SEPARATOR_VALUE         0xFFFFFFFF
7730 #define REG_NUM_PER_LINE        4
7731 #define REG_LEN_PER_LINE        (REG_NUM_PER_LINE * sizeof(u32))
7732
7733 static int hclge_get_regs_len(struct hnae3_handle *handle)
7734 {
7735         int cmdq_lines, common_lines, ring_lines, tqp_intr_lines;
7736         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
7737         struct hclge_vport *vport = hclge_get_vport(handle);
7738         struct hclge_dev *hdev = vport->back;
7739         u32 regs_num_32_bit, regs_num_64_bit;
7740         int ret;
7741
7742         ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
7743         if (ret) {
7744                 dev_err(&hdev->pdev->dev,
7745                         "Get register number failed, ret = %d.\n", ret);
7746                 return -EOPNOTSUPP;
7747         }
7748
7749         cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1;
7750         common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1;
7751         ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1;
7752         tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1;
7753
7754         return (cmdq_lines + common_lines + ring_lines * kinfo->num_tqps +
7755                 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE +
7756                 regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64);
7757 }
7758
7759 static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
7760                            void *data)
7761 {
7762         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
7763         struct hclge_vport *vport = hclge_get_vport(handle);
7764         struct hclge_dev *hdev = vport->back;
7765         u32 regs_num_32_bit, regs_num_64_bit;
7766         int i, j, reg_um, separator_num;
7767         u32 *reg = data;
7768         int ret;
7769
7770         *version = hdev->fw_version;
7771
7772         ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
7773         if (ret) {
7774                 dev_err(&hdev->pdev->dev,
7775                         "Get register number failed, ret = %d.\n", ret);
7776                 return;
7777         }
7778
7779         /* fetching per-PF registers valus from PF PCIe register space */
7780         reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32);
7781         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
7782         for (i = 0; i < reg_um; i++)
7783                 *reg++ = hclge_read_dev(&hdev->hw, cmdq_reg_addr_list[i]);
7784         for (i = 0; i < separator_num; i++)
7785                 *reg++ = SEPARATOR_VALUE;
7786
7787         reg_um = sizeof(common_reg_addr_list) / sizeof(u32);
7788         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
7789         for (i = 0; i < reg_um; i++)
7790                 *reg++ = hclge_read_dev(&hdev->hw, common_reg_addr_list[i]);
7791         for (i = 0; i < separator_num; i++)
7792                 *reg++ = SEPARATOR_VALUE;
7793
7794         reg_um = sizeof(ring_reg_addr_list) / sizeof(u32);
7795         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
7796         for (j = 0; j < kinfo->num_tqps; j++) {
7797                 for (i = 0; i < reg_um; i++)
7798                         *reg++ = hclge_read_dev(&hdev->hw,
7799                                                 ring_reg_addr_list[i] +
7800                                                 0x200 * j);
7801                 for (i = 0; i < separator_num; i++)
7802                         *reg++ = SEPARATOR_VALUE;
7803         }
7804
7805         reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32);
7806         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
7807         for (j = 0; j < hdev->num_msi_used - 1; j++) {
7808                 for (i = 0; i < reg_um; i++)
7809                         *reg++ = hclge_read_dev(&hdev->hw,
7810                                                 tqp_intr_reg_addr_list[i] +
7811                                                 4 * j);
7812                 for (i = 0; i < separator_num; i++)
7813                         *reg++ = SEPARATOR_VALUE;
7814         }
7815
7816         /* fetching PF common registers values from firmware */
7817         ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, reg);
7818         if (ret) {
7819                 dev_err(&hdev->pdev->dev,
7820                         "Get 32 bit register failed, ret = %d.\n", ret);
7821                 return;
7822         }
7823
7824         reg += regs_num_32_bit;
7825         ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit, reg);
7826         if (ret)
7827                 dev_err(&hdev->pdev->dev,
7828                         "Get 64 bit register failed, ret = %d.\n", ret);
7829 }
7830
7831 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status)
7832 {
7833         struct hclge_set_led_state_cmd *req;
7834         struct hclge_desc desc;
7835         int ret;
7836
7837         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false);
7838
7839         req = (struct hclge_set_led_state_cmd *)desc.data;
7840         hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M,
7841                         HCLGE_LED_LOCATE_STATE_S, locate_led_status);
7842
7843         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7844         if (ret)
7845                 dev_err(&hdev->pdev->dev,
7846                         "Send set led state cmd error, ret =%d\n", ret);
7847
7848         return ret;
7849 }
7850
7851 enum hclge_led_status {
7852         HCLGE_LED_OFF,
7853         HCLGE_LED_ON,
7854         HCLGE_LED_NO_CHANGE = 0xFF,
7855 };
7856
7857 static int hclge_set_led_id(struct hnae3_handle *handle,
7858                             enum ethtool_phys_id_state status)
7859 {
7860         struct hclge_vport *vport = hclge_get_vport(handle);
7861         struct hclge_dev *hdev = vport->back;
7862
7863         switch (status) {
7864         case ETHTOOL_ID_ACTIVE:
7865                 return hclge_set_led_status(hdev, HCLGE_LED_ON);
7866         case ETHTOOL_ID_INACTIVE:
7867                 return hclge_set_led_status(hdev, HCLGE_LED_OFF);
7868         default:
7869                 return -EINVAL;
7870         }
7871 }
7872
7873 static void hclge_get_link_mode(struct hnae3_handle *handle,
7874                                 unsigned long *supported,
7875                                 unsigned long *advertising)
7876 {
7877         unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS);
7878         struct hclge_vport *vport = hclge_get_vport(handle);
7879         struct hclge_dev *hdev = vport->back;
7880         unsigned int idx = 0;
7881
7882         for (; idx < size; idx++) {
7883                 supported[idx] = hdev->hw.mac.supported[idx];
7884                 advertising[idx] = hdev->hw.mac.advertising[idx];
7885         }
7886 }
7887
7888 static int hclge_gro_en(struct hnae3_handle *handle, int enable)
7889 {
7890         struct hclge_vport *vport = hclge_get_vport(handle);
7891         struct hclge_dev *hdev = vport->back;
7892
7893         return hclge_config_gro(hdev, enable);
7894 }
7895
7896 static const struct hnae3_ae_ops hclge_ops = {
7897         .init_ae_dev = hclge_init_ae_dev,
7898         .uninit_ae_dev = hclge_uninit_ae_dev,
7899         .flr_prepare = hclge_flr_prepare,
7900         .flr_done = hclge_flr_done,
7901         .init_client_instance = hclge_init_client_instance,
7902         .uninit_client_instance = hclge_uninit_client_instance,
7903         .map_ring_to_vector = hclge_map_ring_to_vector,
7904         .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
7905         .get_vector = hclge_get_vector,
7906         .put_vector = hclge_put_vector,
7907         .set_promisc_mode = hclge_set_promisc_mode,
7908         .set_loopback = hclge_set_loopback,
7909         .start = hclge_ae_start,
7910         .stop = hclge_ae_stop,
7911         .client_start = hclge_client_start,
7912         .client_stop = hclge_client_stop,
7913         .get_status = hclge_get_status,
7914         .get_ksettings_an_result = hclge_get_ksettings_an_result,
7915         .update_speed_duplex_h = hclge_update_speed_duplex_h,
7916         .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
7917         .get_media_type = hclge_get_media_type,
7918         .get_rss_key_size = hclge_get_rss_key_size,
7919         .get_rss_indir_size = hclge_get_rss_indir_size,
7920         .get_rss = hclge_get_rss,
7921         .set_rss = hclge_set_rss,
7922         .set_rss_tuple = hclge_set_rss_tuple,
7923         .get_rss_tuple = hclge_get_rss_tuple,
7924         .get_tc_size = hclge_get_tc_size,
7925         .get_mac_addr = hclge_get_mac_addr,
7926         .set_mac_addr = hclge_set_mac_addr,
7927         .do_ioctl = hclge_do_ioctl,
7928         .add_uc_addr = hclge_add_uc_addr,
7929         .rm_uc_addr = hclge_rm_uc_addr,
7930         .add_mc_addr = hclge_add_mc_addr,
7931         .rm_mc_addr = hclge_rm_mc_addr,
7932         .set_autoneg = hclge_set_autoneg,
7933         .get_autoneg = hclge_get_autoneg,
7934         .get_pauseparam = hclge_get_pauseparam,
7935         .set_pauseparam = hclge_set_pauseparam,
7936         .set_mtu = hclge_set_mtu,
7937         .reset_queue = hclge_reset_tqp,
7938         .get_stats = hclge_get_stats,
7939         .update_stats = hclge_update_stats,
7940         .get_strings = hclge_get_strings,
7941         .get_sset_count = hclge_get_sset_count,
7942         .get_fw_version = hclge_get_fw_version,
7943         .get_mdix_mode = hclge_get_mdix_mode,
7944         .enable_vlan_filter = hclge_enable_vlan_filter,
7945         .set_vlan_filter = hclge_set_vlan_filter,
7946         .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
7947         .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
7948         .reset_event = hclge_reset_event,
7949         .set_default_reset_request = hclge_set_def_reset_request,
7950         .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
7951         .set_channels = hclge_set_channels,
7952         .get_channels = hclge_get_channels,
7953         .get_regs_len = hclge_get_regs_len,
7954         .get_regs = hclge_get_regs,
7955         .set_led_id = hclge_set_led_id,
7956         .get_link_mode = hclge_get_link_mode,
7957         .add_fd_entry = hclge_add_fd_entry,
7958         .del_fd_entry = hclge_del_fd_entry,
7959         .del_all_fd_entries = hclge_del_all_fd_entries,
7960         .get_fd_rule_cnt = hclge_get_fd_rule_cnt,
7961         .get_fd_rule_info = hclge_get_fd_rule_info,
7962         .get_fd_all_rules = hclge_get_all_rules,
7963         .restore_fd_rules = hclge_restore_fd_entries,
7964         .enable_fd = hclge_enable_fd,
7965         .dbg_run_cmd = hclge_dbg_run_cmd,
7966         .handle_hw_ras_error = hclge_handle_hw_ras_error,
7967         .get_hw_reset_stat = hclge_get_hw_reset_stat,
7968         .ae_dev_resetting = hclge_ae_dev_resetting,
7969         .ae_dev_reset_cnt = hclge_ae_dev_reset_cnt,
7970         .set_gro_en = hclge_gro_en,
7971         .get_global_queue_id = hclge_covert_handle_qid_global,
7972         .set_timer_task = hclge_set_timer_task,
7973 };
7974
7975 static struct hnae3_ae_algo ae_algo = {
7976         .ops = &hclge_ops,
7977         .pdev_id_table = ae_algo_pci_tbl,
7978 };
7979
7980 static int hclge_init(void)
7981 {
7982         pr_info("%s is initializing\n", HCLGE_NAME);
7983
7984         hnae3_register_ae_algo(&ae_algo);
7985
7986         return 0;
7987 }
7988
7989 static void hclge_exit(void)
7990 {
7991         hnae3_unregister_ae_algo(&ae_algo);
7992 }
7993 module_init(hclge_init);
7994 module_exit(hclge_exit);
7995
7996 MODULE_LICENSE("GPL");
7997 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
7998 MODULE_DESCRIPTION("HCLGE Driver");
7999 MODULE_VERSION(HCLGE_MOD_VERSION);