drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4 #include "hclge_main.h"
   5 #include "hclge_tm.h"
   6 #include "hnae3.h"
   7
   8 #define BW_PERCENT      100
   9
  10 static int hclge_ieee_ets_to_tm_info(struct hclge_dev *hdev,
  11                                      struct ieee_ets *ets)
  12 {
  13         u8 i;
  14
  15         for (i = 0; i < HNAE3_MAX_TC; i++) {
  16                 switch (ets->tc_tsa[i]) {
  17                 case IEEE_8021QAZ_TSA_STRICT:
  18                         hdev->tm_info.tc_info[i].tc_sch_mode =
  19                                 HCLGE_SCH_MODE_SP;
  20                         hdev->tm_info.pg_info[0].tc_dwrr[i] = 0;
  21                         break;
  22                 case IEEE_8021QAZ_TSA_ETS:
  23                         hdev->tm_info.tc_info[i].tc_sch_mode =
  24                                 HCLGE_SCH_MODE_DWRR;
  25                         hdev->tm_info.pg_info[0].tc_dwrr[i] =
  26                                 ets->tc_tx_bw[i];
  27                         break;
  28                 default:
  29                         /* Hardware only supports SP (strict priority)
  30                          * or ETS (enhanced transmission selection)
  31                          * algorithms, if we receive some other value
  32                          * from dcbnl, then throw an error.
  33                          */
  34                         return -EINVAL;
  35                 }
  36         }
  37
  38         hclge_tm_prio_tc_info_update(hdev, ets->prio_tc);
  39
  40         return 0;
  41 }
  42
  43 static void hclge_tm_info_to_ieee_ets(struct hclge_dev *hdev,
  44                                       struct ieee_ets *ets)
  45 {
  46         u32 i;
  47
  48         memset(ets, 0, sizeof(*ets));
  49         ets->willing = 1;
  50         ets->ets_cap = hdev->tc_max;
  51
  52         for (i = 0; i < HNAE3_MAX_TC; i++) {
  53                 ets->prio_tc[i] = hdev->tm_info.prio_tc[i];
  54                 ets->tc_tx_bw[i] = hdev->tm_info.pg_info[0].tc_dwrr[i];
  55
  56                 if (hdev->tm_info.tc_info[i].tc_sch_mode ==
  57                     HCLGE_SCH_MODE_SP)
  58                         ets->tc_tsa[i] = IEEE_8021QAZ_TSA_STRICT;
  59                 else
  60                         ets->tc_tsa[i] = IEEE_8021QAZ_TSA_ETS;
  61         }
  62 }
  63
  64 /* IEEE std */
  65 static int hclge_ieee_getets(struct hnae3_handle *h, struct ieee_ets *ets)
  66 {
  67         struct hclge_vport *vport = hclge_get_vport(h);
  68         struct hclge_dev *hdev = vport->back;
  69
  70         hclge_tm_info_to_ieee_ets(hdev, ets);
  71
  72         return 0;
  73 }
  74
  75 static int hclge_dcb_common_validate(struct hclge_dev *hdev, u8 num_tc,
  76                                      u8 *prio_tc)
  77 {
  78         int i;
  79
  80         if (num_tc > hdev->tc_max) {
  81                 dev_err(&hdev->pdev->dev,
  82                         "tc num checking failed, %u > tc_max(%u)\n",
  83                         num_tc, hdev->tc_max);
  84                 return -EINVAL;
  85         }
  86
  87         for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
  88                 if (prio_tc[i] >= num_tc) {
  89                         dev_err(&hdev->pdev->dev,
  90                                 "prio_tc[%u] checking failed, %u >= num_tc(%u)\n",
  91                                 i, prio_tc[i], num_tc);
  92                         return -EINVAL;
  93                 }
  94         }
  95
  96         for (i = 0; i < hdev->num_alloc_vport; i++) {
  97                 if (num_tc > hdev->vport[i].alloc_tqps) {
  98                         dev_err(&hdev->pdev->dev,
  99                                 "allocated tqp(%u) checking failed, %u > tqp(%u)\n",
 100                                 i, num_tc, hdev->vport[i].alloc_tqps);
 101                         return -EINVAL;
 102                 }
 103         }
 104
 105         return 0;
 106 }
 107
 108 static int hclge_ets_validate(struct hclge_dev *hdev, struct ieee_ets *ets,
 109                               u8 *tc, bool *changed)
 110 {
 111         bool has_ets_tc = false;
 112         u32 total_ets_bw = 0;
 113         u8 max_tc = 0;
 114         int ret;
 115         u8 i;
 116
 117         for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
 118                 if (ets->prio_tc[i] != hdev->tm_info.prio_tc[i])
 119                         *changed = true;
 120
 121                 if (ets->prio_tc[i] > max_tc)
 122                         max_tc = ets->prio_tc[i];
 123         }
 124
 125         ret = hclge_dcb_common_validate(hdev, max_tc + 1, ets->prio_tc);
 126         if (ret)
 127                 return ret;
 128
 129         for (i = 0; i < HNAE3_MAX_TC; i++) {
 130                 switch (ets->tc_tsa[i]) {
 131                 case IEEE_8021QAZ_TSA_STRICT:
 132                         if (hdev->tm_info.tc_info[i].tc_sch_mode !=
 133                                 HCLGE_SCH_MODE_SP)
 134                                 *changed = true;
 135                         break;
 136                 case IEEE_8021QAZ_TSA_ETS:
 137                         if (hdev->tm_info.tc_info[i].tc_sch_mode !=
 138                                 HCLGE_SCH_MODE_DWRR)
 139                                 *changed = true;
 140
 141                         total_ets_bw += ets->tc_tx_bw[i];
 142                         has_ets_tc = true;
 143                         break;
 144                 default:
 145                         return -EINVAL;
 146                 }
 147         }
 148
 149         if (has_ets_tc && total_ets_bw != BW_PERCENT)
 150                 return -EINVAL;
 151
 152         *tc = max_tc + 1;
 153         if (*tc != hdev->tm_info.num_tc)
 154                 *changed = true;
 155
 156         return 0;
 157 }
 158
 159 static int hclge_map_update(struct hnae3_handle *h)
 160 {
 161         struct hclge_vport *vport = hclge_get_vport(h);
 162         struct hclge_dev *hdev = vport->back;
 163         int ret;
 164
 165         ret = hclge_tm_schd_setup_hw(hdev);
 166         if (ret)
 167                 return ret;
 168
 169         ret = hclge_pause_setup_hw(hdev, false);
 170         if (ret)
 171                 return ret;
 172
 173         ret = hclge_buffer_alloc(hdev);
 174         if (ret)
 175                 return ret;
 176
 177         hclge_rss_indir_init_cfg(hdev);
 178
 179         return hclge_rss_init_hw(hdev);
 180 }
 181
 182 static int hclge_client_setup_tc(struct hclge_dev *hdev)
 183 {
 184         struct hclge_vport *vport = hdev->vport;
 185         struct hnae3_client *client;
 186         struct hnae3_handle *handle;
 187         int ret;
 188         u32 i;
 189
 190         for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
 191                 handle = &vport[i].nic;
 192                 client = handle->client;
 193
 194                 if (!client || !client->ops || !client->ops->setup_tc)
 195                         continue;
 196
 197                 ret = client->ops->setup_tc(handle, hdev->tm_info.num_tc);
 198                 if (ret)
 199                         return ret;
 200         }
 201
 202         return 0;
 203 }
 204
 205 static int hclge_ieee_setets(struct hnae3_handle *h, struct ieee_ets *ets)
 206 {
 207         struct hclge_vport *vport = hclge_get_vport(h);
 208         struct hclge_dev *hdev = vport->back;
 209         bool map_changed = false;
 210         u8 num_tc = 0;
 211         int ret;
 212
 213         if (!(hdev->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) ||
 214             hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE)
 215                 return -EINVAL;
 216
 217         ret = hclge_ets_validate(hdev, ets, &num_tc, &map_changed);
 218         if (ret)
 219                 return ret;
 220
 221         if (map_changed) {
 222                 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
 223                 if (ret)
 224                         return ret;
 225
 226                 ret = hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
 227                 if (ret)
 228                         return ret;
 229         }
 230
 231         hclge_tm_schd_info_update(hdev, num_tc);
 232
 233         ret = hclge_ieee_ets_to_tm_info(hdev, ets);
 234         if (ret)
 235                 return ret;
 236
 237         if (map_changed) {
 238                 ret = hclge_client_setup_tc(hdev);
 239                 if (ret)
 240                         return ret;
 241                 ret = hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
 242                 if (ret)
 243                         return ret;
 244
 245                 ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT);
 246                 if (ret)
 247                         return ret;
 248         }
 249
 250         return hclge_tm_dwrr_cfg(hdev);
 251 }
 252
 253 static int hclge_ieee_getpfc(struct hnae3_handle *h, struct ieee_pfc *pfc)
 254 {
 255         u64 requests[HNAE3_MAX_TC], indications[HNAE3_MAX_TC];
 256         struct hclge_vport *vport = hclge_get_vport(h);
 257         struct hclge_dev *hdev = vport->back;
 258         u8 i, j, pfc_map, *prio_tc;
 259         int ret;
 260
 261         memset(pfc, 0, sizeof(*pfc));
 262         pfc->pfc_cap = hdev->pfc_max;
 263         prio_tc = hdev->tm_info.prio_tc;
 264         pfc_map = hdev->tm_info.hw_pfc_map;
 265
 266         /* Pfc setting is based on TC */
 267         for (i = 0; i < hdev->tm_info.num_tc; i++) {
 268                 for (j = 0; j < HNAE3_MAX_USER_PRIO; j++) {
 269                         if ((prio_tc[j] == i) && (pfc_map & BIT(i)))
 270                                 pfc->pfc_en |= BIT(j);
 271                 }
 272         }
 273
 274         ret = hclge_pfc_tx_stats_get(hdev, requests);
 275         if (ret)
 276                 return ret;
 277
 278         ret = hclge_pfc_rx_stats_get(hdev, indications);
 279         if (ret)
 280                 return ret;
 281
 282         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
 283                 pfc->requests[i] = requests[i];
 284                 pfc->indications[i] = indications[i];
 285         }
 286         return 0;
 287 }
 288
 289 static int hclge_ieee_setpfc(struct hnae3_handle *h, struct ieee_pfc *pfc)
 290 {
 291         struct hclge_vport *vport = hclge_get_vport(h);
 292         struct hclge_dev *hdev = vport->back;
 293         u8 i, j, pfc_map, *prio_tc;
 294
 295         if (!(hdev->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) ||
 296             hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE)
 297                 return -EINVAL;
 298
 299         prio_tc = hdev->tm_info.prio_tc;
 300         pfc_map = 0;
 301
 302         for (i = 0; i < hdev->tm_info.num_tc; i++) {
 303                 for (j = 0; j < HNAE3_MAX_USER_PRIO; j++) {
 304                         if ((prio_tc[j] == i) && (pfc->pfc_en & BIT(j))) {
 305                                 pfc_map |= BIT(i);
 306                                 break;
 307                         }
 308                 }
 309         }
 310
 311         if (pfc_map == hdev->tm_info.hw_pfc_map)
 312                 return 0;
 313
 314         hdev->tm_info.hw_pfc_map = pfc_map;
 315
 316         return hclge_pause_setup_hw(hdev, false);
 317 }
 318
 319 /* DCBX configuration */
 320 static u8 hclge_getdcbx(struct hnae3_handle *h)
 321 {
 322         struct hclge_vport *vport = hclge_get_vport(h);
 323         struct hclge_dev *hdev = vport->back;
 324
 325         if (hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE)
 326                 return 0;
 327
 328         return hdev->dcbx_cap;
 329 }
 330
 331 static u8 hclge_setdcbx(struct hnae3_handle *h, u8 mode)
 332 {
 333         struct hclge_vport *vport = hclge_get_vport(h);
 334         struct hclge_dev *hdev = vport->back;
 335
 336         /* No support for LLD_MANAGED modes or CEE */
 337         if ((mode & DCB_CAP_DCBX_LLD_MANAGED) ||
 338             (mode & DCB_CAP_DCBX_VER_CEE) ||
 339             !(mode & DCB_CAP_DCBX_HOST))
 340                 return 1;
 341
 342         hdev->dcbx_cap = mode;
 343
 344         return 0;
 345 }
 346
 347 /* Set up TC for hardware offloaded mqprio in channel mode */
 348 static int hclge_setup_tc(struct hnae3_handle *h, u8 tc, u8 *prio_tc)
 349 {
 350         struct hclge_vport *vport = hclge_get_vport(h);
 351         struct hclge_dev *hdev = vport->back;
 352         int ret;
 353
 354         if (hdev->flag & HCLGE_FLAG_DCB_ENABLE)
 355                 return -EINVAL;
 356
 357         ret = hclge_dcb_common_validate(hdev, tc, prio_tc);
 358         if (ret)
 359                 return -EINVAL;
 360
 361         hclge_tm_schd_info_update(hdev, tc);
 362         hclge_tm_prio_tc_info_update(hdev, prio_tc);
 363
 364         ret = hclge_tm_init_hw(hdev, false);
 365         if (ret)
 366                 return ret;
 367
 368         hdev->flag &= ~HCLGE_FLAG_DCB_ENABLE;
 369
 370         if (tc > 1)
 371                 hdev->flag |= HCLGE_FLAG_MQPRIO_ENABLE;
 372         else
 373                 hdev->flag &= ~HCLGE_FLAG_MQPRIO_ENABLE;
 374
 375         return 0;
 376 }
 377
 378 static const struct hnae3_dcb_ops hns3_dcb_ops = {
 379         .ieee_getets    = hclge_ieee_getets,
 380         .ieee_setets    = hclge_ieee_setets,
 381         .ieee_getpfc    = hclge_ieee_getpfc,
 382         .ieee_setpfc    = hclge_ieee_setpfc,
 383         .getdcbx        = hclge_getdcbx,
 384         .setdcbx        = hclge_setdcbx,
 385         .map_update     = hclge_map_update,
 386         .setup_tc       = hclge_setup_tc,
 387 };
 388
 389 void hclge_dcb_ops_set(struct hclge_dev *hdev)
 390 {
 391         struct hclge_vport *vport = hdev->vport;
 392         struct hnae3_knic_private_info *kinfo;
 393
 394         /* Hdev does not support DCB or vport is
 395          * not a pf, then dcb_ops is not set.
 396          */
 397         if (!hnae3_dev_dcb_supported(hdev) ||
 398             vport->vport_id != 0)
 399                 return;
 400
 401         kinfo = &vport->nic.kinfo;
 402         kinfo->dcb_ops = &hns3_dcb_ops;
 403         hdev->dcbx_cap = DCB_CAP_DCBX_VER_IEEE | DCB_CAP_DCBX_HOST;
 404 }