1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
4 #include <linux/dma-mapping.h>
5 #include <linux/slab.h>
7 #include <linux/device.h>
9 #include <linux/dma-direction.h>
10 #include "hclge_cmd.h"
12 #include "hclge_main.h"
14 #define cmq_ring_to_dev(ring) (&(ring)->dev->pdev->dev)
16 static int hclge_ring_space(struct hclge_cmq_ring *ring)
18 int ntu = ring->next_to_use;
19 int ntc = ring->next_to_clean;
20 int used = (ntu - ntc + ring->desc_num) % ring->desc_num;
22 return ring->desc_num - used - 1;
25 static int is_valid_csq_clean_head(struct hclge_cmq_ring *ring, int head)
27 int ntu = ring->next_to_use;
28 int ntc = ring->next_to_clean;
31 return head >= ntc && head <= ntu;
33 return head >= ntc || head <= ntu;
36 static int hclge_alloc_cmd_desc(struct hclge_cmq_ring *ring)
38 int size = ring->desc_num * sizeof(struct hclge_desc);
40 ring->desc = dma_alloc_coherent(cmq_ring_to_dev(ring), size,
41 &ring->desc_dma_addr, GFP_KERNEL);
48 static void hclge_free_cmd_desc(struct hclge_cmq_ring *ring)
50 int size = ring->desc_num * sizeof(struct hclge_desc);
53 dma_free_coherent(cmq_ring_to_dev(ring), size,
54 ring->desc, ring->desc_dma_addr);
59 static int hclge_alloc_cmd_queue(struct hclge_dev *hdev, int ring_type)
61 struct hclge_hw *hw = &hdev->hw;
62 struct hclge_cmq_ring *ring =
63 (ring_type == HCLGE_TYPE_CSQ) ? &hw->cmq.csq : &hw->cmq.crq;
66 ring->ring_type = ring_type;
69 ret = hclge_alloc_cmd_desc(ring);
71 dev_err(&hdev->pdev->dev, "descriptor %s alloc error %d\n",
72 (ring_type == HCLGE_TYPE_CSQ) ? "CSQ" : "CRQ", ret);
79 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read)
81 desc->flag = cpu_to_le16(HCLGE_CMD_FLAG_NO_INTR | HCLGE_CMD_FLAG_IN);
83 desc->flag |= cpu_to_le16(HCLGE_CMD_FLAG_WR);
85 desc->flag &= cpu_to_le16(~HCLGE_CMD_FLAG_WR);
88 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc,
89 enum hclge_opcode_type opcode, bool is_read)
91 memset((void *)desc, 0, sizeof(struct hclge_desc));
92 desc->opcode = cpu_to_le16(opcode);
93 desc->flag = cpu_to_le16(HCLGE_CMD_FLAG_NO_INTR | HCLGE_CMD_FLAG_IN);
96 desc->flag |= cpu_to_le16(HCLGE_CMD_FLAG_WR);
99 static void hclge_cmd_config_regs(struct hclge_cmq_ring *ring)
101 dma_addr_t dma = ring->desc_dma_addr;
102 struct hclge_dev *hdev = ring->dev;
103 struct hclge_hw *hw = &hdev->hw;
106 if (ring->ring_type == HCLGE_TYPE_CSQ) {
107 hclge_write_dev(hw, HCLGE_NIC_CSQ_BASEADDR_L_REG,
109 hclge_write_dev(hw, HCLGE_NIC_CSQ_BASEADDR_H_REG,
111 reg_val = hclge_read_dev(hw, HCLGE_NIC_CSQ_DEPTH_REG);
112 reg_val &= HCLGE_NIC_SW_RST_RDY;
113 reg_val |= ring->desc_num >> HCLGE_NIC_CMQ_DESC_NUM_S;
114 hclge_write_dev(hw, HCLGE_NIC_CSQ_DEPTH_REG, reg_val);
115 hclge_write_dev(hw, HCLGE_NIC_CSQ_HEAD_REG, 0);
116 hclge_write_dev(hw, HCLGE_NIC_CSQ_TAIL_REG, 0);
118 hclge_write_dev(hw, HCLGE_NIC_CRQ_BASEADDR_L_REG,
120 hclge_write_dev(hw, HCLGE_NIC_CRQ_BASEADDR_H_REG,
122 hclge_write_dev(hw, HCLGE_NIC_CRQ_DEPTH_REG,
123 ring->desc_num >> HCLGE_NIC_CMQ_DESC_NUM_S);
124 hclge_write_dev(hw, HCLGE_NIC_CRQ_HEAD_REG, 0);
125 hclge_write_dev(hw, HCLGE_NIC_CRQ_TAIL_REG, 0);
129 static void hclge_cmd_init_regs(struct hclge_hw *hw)
131 hclge_cmd_config_regs(&hw->cmq.csq);
132 hclge_cmd_config_regs(&hw->cmq.crq);
135 static int hclge_cmd_csq_clean(struct hclge_hw *hw)
137 struct hclge_dev *hdev = container_of(hw, struct hclge_dev, hw);
138 struct hclge_cmq_ring *csq = &hw->cmq.csq;
142 head = hclge_read_dev(hw, HCLGE_NIC_CSQ_HEAD_REG);
143 rmb(); /* Make sure head is ready before touch any data */
145 if (!is_valid_csq_clean_head(csq, head)) {
146 dev_warn(&hdev->pdev->dev, "wrong cmd head (%u, %d-%d)\n", head,
147 csq->next_to_use, csq->next_to_clean);
148 dev_warn(&hdev->pdev->dev,
149 "Disabling any further commands to IMP firmware\n");
150 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
151 dev_warn(&hdev->pdev->dev,
152 "IMP firmware watchdog reset soon expected!\n");
156 clean = (head - csq->next_to_clean + csq->desc_num) % csq->desc_num;
157 csq->next_to_clean = head;
161 static int hclge_cmd_csq_done(struct hclge_hw *hw)
163 u32 head = hclge_read_dev(hw, HCLGE_NIC_CSQ_HEAD_REG);
164 return head == hw->cmq.csq.next_to_use;
167 static bool hclge_is_special_opcode(u16 opcode)
169 /* these commands have several descriptors,
170 * and use the first one to save opcode and return value
172 u16 spec_opcode[] = {HCLGE_OPC_STATS_64_BIT,
173 HCLGE_OPC_STATS_32_BIT,
175 HCLGE_OPC_STATS_MAC_ALL,
176 HCLGE_OPC_QUERY_32_BIT_REG,
177 HCLGE_OPC_QUERY_64_BIT_REG,
178 HCLGE_QUERY_CLEAR_MPF_RAS_INT,
179 HCLGE_QUERY_CLEAR_PF_RAS_INT,
180 HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT,
181 HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT};
184 for (i = 0; i < ARRAY_SIZE(spec_opcode); i++) {
185 if (spec_opcode[i] == opcode)
197 static void hclge_cmd_copy_desc(struct hclge_hw *hw, struct hclge_desc *desc,
200 struct hclge_desc *desc_to_use;
203 while (handle < num) {
204 desc_to_use = &hw->cmq.csq.desc[hw->cmq.csq.next_to_use];
205 *desc_to_use = desc[handle];
206 (hw->cmq.csq.next_to_use)++;
207 if (hw->cmq.csq.next_to_use >= hw->cmq.csq.desc_num)
208 hw->cmq.csq.next_to_use = 0;
213 static int hclge_cmd_convert_err_code(u16 desc_ret)
215 struct errcode hclge_cmd_errcode[] = {
216 {HCLGE_CMD_EXEC_SUCCESS, 0},
217 {HCLGE_CMD_NO_AUTH, -EPERM},
218 {HCLGE_CMD_NOT_SUPPORTED, -EOPNOTSUPP},
219 {HCLGE_CMD_QUEUE_FULL, -EXFULL},
220 {HCLGE_CMD_NEXT_ERR, -ENOSR},
221 {HCLGE_CMD_UNEXE_ERR, -ENOTBLK},
222 {HCLGE_CMD_PARA_ERR, -EINVAL},
223 {HCLGE_CMD_RESULT_ERR, -ERANGE},
224 {HCLGE_CMD_TIMEOUT, -ETIME},
225 {HCLGE_CMD_HILINK_ERR, -ENOLINK},
226 {HCLGE_CMD_QUEUE_ILLEGAL, -ENXIO},
227 {HCLGE_CMD_INVALID, -EBADR},
229 u32 errcode_count = ARRAY_SIZE(hclge_cmd_errcode);
232 for (i = 0; i < errcode_count; i++)
233 if (hclge_cmd_errcode[i].imp_errcode == desc_ret)
234 return hclge_cmd_errcode[i].common_errno;
239 static int hclge_cmd_check_retval(struct hclge_hw *hw, struct hclge_desc *desc,
242 u16 opcode, desc_ret;
245 opcode = le16_to_cpu(desc[0].opcode);
246 for (handle = 0; handle < num; handle++) {
247 desc[handle] = hw->cmq.csq.desc[ntc];
249 if (ntc >= hw->cmq.csq.desc_num)
252 if (likely(!hclge_is_special_opcode(opcode)))
253 desc_ret = le16_to_cpu(desc[num - 1].retval);
255 desc_ret = le16_to_cpu(desc[0].retval);
257 hw->cmq.last_status = desc_ret;
259 return hclge_cmd_convert_err_code(desc_ret);
262 static int hclge_cmd_check_result(struct hclge_hw *hw, struct hclge_desc *desc,
265 struct hclge_dev *hdev = container_of(hw, struct hclge_dev, hw);
266 bool is_completed = false;
271 * If the command is sync, wait for the firmware to write back,
272 * if multi descriptors to be sent, use the first one to check
274 if (HCLGE_SEND_SYNC(le16_to_cpu(desc->flag))) {
276 if (hclge_cmd_csq_done(hw)) {
282 } while (timeout < hw->cmq.tx_timeout);
288 ret = hclge_cmd_check_retval(hw, desc, num, ntc);
290 /* Clean the command send queue */
291 handle = hclge_cmd_csq_clean(hw);
294 else if (handle != num)
295 dev_warn(&hdev->pdev->dev,
296 "cleaned %d, need to clean %d\n", handle, num);
301 * hclge_cmd_send - send command to command queue
302 * @hw: pointer to the hw struct
303 * @desc: prefilled descriptor for describing the command
304 * @num : the number of descriptors to be sent
306 * This is the main send command for command queue, it
307 * sends the queue, cleans the queue, etc
309 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num)
311 struct hclge_dev *hdev = container_of(hw, struct hclge_dev, hw);
312 struct hclge_cmq_ring *csq = &hw->cmq.csq;
316 spin_lock_bh(&hw->cmq.csq.lock);
318 if (test_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state)) {
319 spin_unlock_bh(&hw->cmq.csq.lock);
323 if (num > hclge_ring_space(&hw->cmq.csq)) {
324 /* If CMDQ ring is full, SW HEAD and HW HEAD may be different,
325 * need update the SW HEAD pointer csq->next_to_clean
327 csq->next_to_clean = hclge_read_dev(hw, HCLGE_NIC_CSQ_HEAD_REG);
328 spin_unlock_bh(&hw->cmq.csq.lock);
333 * Record the location of desc in the ring for this time
334 * which will be use for hardware to write back
336 ntc = hw->cmq.csq.next_to_use;
338 hclge_cmd_copy_desc(hw, desc, num);
340 /* Write to hardware */
341 hclge_write_dev(hw, HCLGE_NIC_CSQ_TAIL_REG, hw->cmq.csq.next_to_use);
343 ret = hclge_cmd_check_result(hw, desc, num, ntc);
345 spin_unlock_bh(&hw->cmq.csq.lock);
350 static void hclge_set_default_capability(struct hclge_dev *hdev)
352 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
354 set_bit(HNAE3_DEV_SUPPORT_FD_B, ae_dev->caps);
355 set_bit(HNAE3_DEV_SUPPORT_GRO_B, ae_dev->caps);
356 if (hdev->ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) {
357 set_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps);
358 set_bit(HNAE3_DEV_SUPPORT_PAUSE_B, ae_dev->caps);
362 static void hclge_parse_capability(struct hclge_dev *hdev,
363 struct hclge_query_version_cmd *cmd)
365 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
368 caps = __le32_to_cpu(cmd->caps[0]);
370 if (hnae3_get_bit(caps, HCLGE_CAP_UDP_GSO_B))
371 set_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps);
372 if (hnae3_get_bit(caps, HCLGE_CAP_PTP_B))
373 set_bit(HNAE3_DEV_SUPPORT_PTP_B, ae_dev->caps);
374 if (hnae3_get_bit(caps, HCLGE_CAP_INT_QL_B))
375 set_bit(HNAE3_DEV_SUPPORT_INT_QL_B, ae_dev->caps);
376 if (hnae3_get_bit(caps, HCLGE_CAP_TQP_TXRX_INDEP_B))
377 set_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, ae_dev->caps);
378 if (hnae3_get_bit(caps, HCLGE_CAP_HW_TX_CSUM_B))
379 set_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps);
380 if (hnae3_get_bit(caps, HCLGE_CAP_UDP_TUNNEL_CSUM_B))
381 set_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, ae_dev->caps);
382 if (hnae3_get_bit(caps, HCLGE_CAP_FD_FORWARD_TC_B))
383 set_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps);
384 if (hnae3_get_bit(caps, HCLGE_CAP_FEC_B))
385 set_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps);
386 if (hnae3_get_bit(caps, HCLGE_CAP_PAUSE_B))
387 set_bit(HNAE3_DEV_SUPPORT_PAUSE_B, ae_dev->caps);
390 static __le32 hclge_build_api_caps(void)
394 hnae3_set_bit(api_caps, HCLGE_API_CAP_FLEX_RSS_TBL_B, 1);
396 return cpu_to_le32(api_caps);
399 static enum hclge_cmd_status
400 hclge_cmd_query_version_and_capability(struct hclge_dev *hdev)
402 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
403 struct hclge_query_version_cmd *resp;
404 struct hclge_desc desc;
407 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FW_VER, 1);
408 resp = (struct hclge_query_version_cmd *)desc.data;
409 resp->api_caps = hclge_build_api_caps();
411 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
415 hdev->fw_version = le32_to_cpu(resp->firmware);
417 ae_dev->dev_version = le32_to_cpu(resp->hardware) <<
418 HNAE3_PCI_REVISION_BIT_SIZE;
419 ae_dev->dev_version |= hdev->pdev->revision;
421 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)
422 hclge_set_default_capability(hdev);
424 hclge_parse_capability(hdev, resp);
429 int hclge_cmd_queue_init(struct hclge_dev *hdev)
433 /* Setup the lock for command queue */
434 spin_lock_init(&hdev->hw.cmq.csq.lock);
435 spin_lock_init(&hdev->hw.cmq.crq.lock);
437 /* Setup the queue entries for use cmd queue */
438 hdev->hw.cmq.csq.desc_num = HCLGE_NIC_CMQ_DESC_NUM;
439 hdev->hw.cmq.crq.desc_num = HCLGE_NIC_CMQ_DESC_NUM;
441 /* Setup Tx write back timeout */
442 hdev->hw.cmq.tx_timeout = HCLGE_CMDQ_TX_TIMEOUT;
444 /* Setup queue rings */
445 ret = hclge_alloc_cmd_queue(hdev, HCLGE_TYPE_CSQ);
447 dev_err(&hdev->pdev->dev,
448 "CSQ ring setup error %d\n", ret);
452 ret = hclge_alloc_cmd_queue(hdev, HCLGE_TYPE_CRQ);
454 dev_err(&hdev->pdev->dev,
455 "CRQ ring setup error %d\n", ret);
461 hclge_free_cmd_desc(&hdev->hw.cmq.csq);
465 static int hclge_firmware_compat_config(struct hclge_dev *hdev)
467 struct hclge_firmware_compat_cmd *req;
468 struct hclge_desc desc;
471 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_M7_COMPAT_CFG, false);
473 req = (struct hclge_firmware_compat_cmd *)desc.data;
475 hnae3_set_bit(compat, HCLGE_LINK_EVENT_REPORT_EN_B, 1);
476 hnae3_set_bit(compat, HCLGE_NCSI_ERROR_REPORT_EN_B, 1);
477 req->compat = cpu_to_le32(compat);
479 return hclge_cmd_send(&hdev->hw, &desc, 1);
482 int hclge_cmd_init(struct hclge_dev *hdev)
486 spin_lock_bh(&hdev->hw.cmq.csq.lock);
487 spin_lock(&hdev->hw.cmq.crq.lock);
489 hdev->hw.cmq.csq.next_to_clean = 0;
490 hdev->hw.cmq.csq.next_to_use = 0;
491 hdev->hw.cmq.crq.next_to_clean = 0;
492 hdev->hw.cmq.crq.next_to_use = 0;
494 hclge_cmd_init_regs(&hdev->hw);
496 spin_unlock(&hdev->hw.cmq.crq.lock);
497 spin_unlock_bh(&hdev->hw.cmq.csq.lock);
499 clear_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
501 /* Check if there is new reset pending, because the higher level
502 * reset may happen when lower level reset is being processed.
504 if ((hclge_is_reset_pending(hdev))) {
505 dev_err(&hdev->pdev->dev,
506 "failed to init cmd since reset %#lx pending\n",
507 hdev->reset_pending);
512 /* get version and device capabilities */
513 ret = hclge_cmd_query_version_and_capability(hdev);
515 dev_err(&hdev->pdev->dev,
516 "failed to query version and capabilities, ret = %d\n",
521 dev_info(&hdev->pdev->dev, "The firmware version is %lu.%lu.%lu.%lu\n",
522 hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE3_MASK,
523 HNAE3_FW_VERSION_BYTE3_SHIFT),
524 hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE2_MASK,
525 HNAE3_FW_VERSION_BYTE2_SHIFT),
526 hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE1_MASK,
527 HNAE3_FW_VERSION_BYTE1_SHIFT),
528 hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE0_MASK,
529 HNAE3_FW_VERSION_BYTE0_SHIFT));
531 /* ask the firmware to enable some features, driver can work without
534 ret = hclge_firmware_compat_config(hdev);
536 dev_warn(&hdev->pdev->dev,
537 "Firmware compatible features not enabled(%d).\n",
543 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
548 static void hclge_cmd_uninit_regs(struct hclge_hw *hw)
550 hclge_write_dev(hw, HCLGE_NIC_CSQ_BASEADDR_L_REG, 0);
551 hclge_write_dev(hw, HCLGE_NIC_CSQ_BASEADDR_H_REG, 0);
552 hclge_write_dev(hw, HCLGE_NIC_CSQ_DEPTH_REG, 0);
553 hclge_write_dev(hw, HCLGE_NIC_CSQ_HEAD_REG, 0);
554 hclge_write_dev(hw, HCLGE_NIC_CSQ_TAIL_REG, 0);
555 hclge_write_dev(hw, HCLGE_NIC_CRQ_BASEADDR_L_REG, 0);
556 hclge_write_dev(hw, HCLGE_NIC_CRQ_BASEADDR_H_REG, 0);
557 hclge_write_dev(hw, HCLGE_NIC_CRQ_DEPTH_REG, 0);
558 hclge_write_dev(hw, HCLGE_NIC_CRQ_HEAD_REG, 0);
559 hclge_write_dev(hw, HCLGE_NIC_CRQ_TAIL_REG, 0);
562 void hclge_cmd_uninit(struct hclge_dev *hdev)
564 spin_lock_bh(&hdev->hw.cmq.csq.lock);
565 spin_lock(&hdev->hw.cmq.crq.lock);
566 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
567 hclge_cmd_uninit_regs(&hdev->hw);
568 spin_unlock(&hdev->hw.cmq.crq.lock);
569 spin_unlock_bh(&hdev->hw.cmq.csq.lock);
571 hclge_free_cmd_desc(&hdev->hw.cmq.csq);
572 hclge_free_cmd_desc(&hdev->hw.cmq.crq);