1 /* SPDX-License-Identifier: GPL-2.0+ */
2 // Copyright (c) 2016-2017 Hisilicon Limited.
8 #include <linux/if_vlan.h>
13 HNS3_NIC_STATE_TESTING,
14 HNS3_NIC_STATE_RESETTING,
15 HNS3_NIC_STATE_INITED,
17 HNS3_NIC_STATE_DISABLED,
18 HNS3_NIC_STATE_REMOVING,
19 HNS3_NIC_STATE_SERVICE_INITED,
20 HNS3_NIC_STATE_SERVICE_SCHED,
21 HNS3_NIC_STATE2_RESET_REQUESTED,
22 HNS3_NIC_STATE_HW_TX_CSUM_ENABLE,
23 HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE,
27 #define HNS3_RING_RX_RING_BASEADDR_L_REG 0x00000
28 #define HNS3_RING_RX_RING_BASEADDR_H_REG 0x00004
29 #define HNS3_RING_RX_RING_BD_NUM_REG 0x00008
30 #define HNS3_RING_RX_RING_BD_LEN_REG 0x0000C
31 #define HNS3_RING_RX_RING_TAIL_REG 0x00018
32 #define HNS3_RING_RX_RING_HEAD_REG 0x0001C
33 #define HNS3_RING_RX_RING_FBDNUM_REG 0x00020
34 #define HNS3_RING_RX_RING_PKTNUM_RECORD_REG 0x0002C
36 #define HNS3_RING_TX_RING_BASEADDR_L_REG 0x00040
37 #define HNS3_RING_TX_RING_BASEADDR_H_REG 0x00044
38 #define HNS3_RING_TX_RING_BD_NUM_REG 0x00048
39 #define HNS3_RING_TX_RING_TC_REG 0x00050
40 #define HNS3_RING_TX_RING_TAIL_REG 0x00058
41 #define HNS3_RING_TX_RING_HEAD_REG 0x0005C
42 #define HNS3_RING_TX_RING_FBDNUM_REG 0x00060
43 #define HNS3_RING_TX_RING_OFFSET_REG 0x00064
44 #define HNS3_RING_TX_RING_EBDNUM_REG 0x00068
45 #define HNS3_RING_TX_RING_PKTNUM_RECORD_REG 0x0006C
46 #define HNS3_RING_TX_RING_EBD_OFFSET_REG 0x00070
47 #define HNS3_RING_TX_RING_BD_ERR_REG 0x00074
48 #define HNS3_RING_EN_REG 0x00090
49 #define HNS3_RING_RX_EN_REG 0x00098
50 #define HNS3_RING_TX_EN_REG 0x000D4
52 #define HNS3_RX_HEAD_SIZE 256
54 #define HNS3_TX_TIMEOUT (5 * HZ)
55 #define HNS3_RING_NAME_LEN 16
56 #define HNS3_BUFFER_SIZE_2048 2048
57 #define HNS3_RING_MAX_PENDING 32760
58 #define HNS3_RING_MIN_PENDING 72
59 #define HNS3_RING_BD_MULTIPLE 8
60 /* max frame size of mac */
61 #define HNS3_MAX_MTU(max_frm_size) \
62 ((max_frm_size) - (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN))
64 #define HNS3_BD_SIZE_512_TYPE 0
65 #define HNS3_BD_SIZE_1024_TYPE 1
66 #define HNS3_BD_SIZE_2048_TYPE 2
67 #define HNS3_BD_SIZE_4096_TYPE 3
69 #define HNS3_RX_FLAG_VLAN_PRESENT 0x1
70 #define HNS3_RX_FLAG_L3ID_IPV4 0x0
71 #define HNS3_RX_FLAG_L3ID_IPV6 0x1
72 #define HNS3_RX_FLAG_L4ID_UDP 0x0
73 #define HNS3_RX_FLAG_L4ID_TCP 0x1
75 #define HNS3_RXD_DMAC_S 0
76 #define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S)
77 #define HNS3_RXD_VLAN_S 2
78 #define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S)
79 #define HNS3_RXD_L3ID_S 4
80 #define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S)
81 #define HNS3_RXD_L4ID_S 8
82 #define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S)
83 #define HNS3_RXD_FRAG_B 12
84 #define HNS3_RXD_STRP_TAGP_S 13
85 #define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S)
87 #define HNS3_RXD_L2E_B 16
88 #define HNS3_RXD_L3E_B 17
89 #define HNS3_RXD_L4E_B 18
90 #define HNS3_RXD_TRUNCAT_B 19
91 #define HNS3_RXD_HOI_B 20
92 #define HNS3_RXD_DOI_B 21
93 #define HNS3_RXD_OL3E_B 22
94 #define HNS3_RXD_OL4E_B 23
95 #define HNS3_RXD_GRO_COUNT_S 24
96 #define HNS3_RXD_GRO_COUNT_M (0x3f << HNS3_RXD_GRO_COUNT_S)
97 #define HNS3_RXD_GRO_FIXID_B 30
98 #define HNS3_RXD_GRO_ECN_B 31
100 #define HNS3_RXD_ODMAC_S 0
101 #define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S)
102 #define HNS3_RXD_OVLAN_S 2
103 #define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S)
104 #define HNS3_RXD_OL3ID_S 4
105 #define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S)
106 #define HNS3_RXD_OL4ID_S 8
107 #define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S)
108 #define HNS3_RXD_FBHI_S 12
109 #define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S)
110 #define HNS3_RXD_FBLI_S 14
111 #define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S)
113 #define HNS3_RXD_PTYPE_S 4
114 #define HNS3_RXD_PTYPE_M GENMASK(11, 4)
116 #define HNS3_RXD_BDTYPE_S 0
117 #define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S)
118 #define HNS3_RXD_VLD_B 4
119 #define HNS3_RXD_UDP0_B 5
120 #define HNS3_RXD_EXTEND_B 7
121 #define HNS3_RXD_FE_B 8
122 #define HNS3_RXD_LUM_B 9
123 #define HNS3_RXD_CRCP_B 10
124 #define HNS3_RXD_L3L4P_B 11
125 #define HNS3_RXD_TSIDX_S 12
126 #define HNS3_RXD_TSIDX_M (0x3 << HNS3_RXD_TSIDX_S)
127 #define HNS3_RXD_TS_VLD_B 14
128 #define HNS3_RXD_LKBK_B 15
129 #define HNS3_RXD_GRO_SIZE_S 16
130 #define HNS3_RXD_GRO_SIZE_M (0x3fff << HNS3_RXD_GRO_SIZE_S)
132 #define HNS3_TXD_L3T_S 0
133 #define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S)
134 #define HNS3_TXD_L4T_S 2
135 #define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S)
136 #define HNS3_TXD_L3CS_B 4
137 #define HNS3_TXD_L4CS_B 5
138 #define HNS3_TXD_VLAN_B 6
139 #define HNS3_TXD_TSO_B 7
141 #define HNS3_TXD_L2LEN_S 8
142 #define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S)
143 #define HNS3_TXD_L3LEN_S 16
144 #define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S)
145 #define HNS3_TXD_L4LEN_S 24
146 #define HNS3_TXD_L4LEN_M (0xff << HNS3_TXD_L4LEN_S)
148 #define HNS3_TXD_CSUM_START_S 8
149 #define HNS3_TXD_CSUM_START_M (0xffff << HNS3_TXD_CSUM_START_S)
151 #define HNS3_TXD_OL3T_S 0
152 #define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S)
153 #define HNS3_TXD_OVLAN_B 2
154 #define HNS3_TXD_MACSEC_B 3
155 #define HNS3_TXD_TUNTYPE_S 4
156 #define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S)
158 #define HNS3_TXD_CSUM_OFFSET_S 8
159 #define HNS3_TXD_CSUM_OFFSET_M (0xffff << HNS3_TXD_CSUM_OFFSET_S)
161 #define HNS3_TXD_BDTYPE_S 0
162 #define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S)
163 #define HNS3_TXD_FE_B 4
164 #define HNS3_TXD_SC_S 5
165 #define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S)
166 #define HNS3_TXD_EXTEND_B 7
167 #define HNS3_TXD_VLD_B 8
168 #define HNS3_TXD_RI_B 9
169 #define HNS3_TXD_RA_B 10
170 #define HNS3_TXD_TSYN_B 11
171 #define HNS3_TXD_DECTTL_S 12
172 #define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S)
174 #define HNS3_TXD_OL4CS_B 22
176 #define HNS3_TXD_MSS_S 0
177 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S)
178 #define HNS3_TXD_HW_CS_B 14
180 #define HNS3_VECTOR_TX_IRQ BIT_ULL(0)
181 #define HNS3_VECTOR_RX_IRQ BIT_ULL(1)
183 #define HNS3_VECTOR_NOT_INITED 0
184 #define HNS3_VECTOR_INITED 1
186 #define HNS3_MAX_BD_SIZE 65535
187 #define HNS3_MAX_TSO_BD_NUM 63U
188 #define HNS3_MAX_TSO_SIZE \
189 (HNS3_MAX_BD_SIZE * HNS3_MAX_TSO_BD_NUM)
191 #define HNS3_MAX_NON_TSO_SIZE(max_non_tso_bd_num) \
192 (HNS3_MAX_BD_SIZE * (max_non_tso_bd_num))
194 #define HNS3_VECTOR_GL0_OFFSET 0x100
195 #define HNS3_VECTOR_GL1_OFFSET 0x200
196 #define HNS3_VECTOR_GL2_OFFSET 0x300
197 #define HNS3_VECTOR_RL_OFFSET 0x900
198 #define HNS3_VECTOR_RL_EN_B 6
199 #define HNS3_VECTOR_TX_QL_OFFSET 0xe00
200 #define HNS3_VECTOR_RX_QL_OFFSET 0xf00
202 #define HNS3_RING_EN_B 0
204 enum hns3_pkt_l2t_type {
205 HNS3_L2_TYPE_UNICAST,
206 HNS3_L2_TYPE_MULTICAST,
207 HNS3_L2_TYPE_BROADCAST,
208 HNS3_L2_TYPE_INVALID,
211 enum hns3_pkt_l3t_type {
218 enum hns3_pkt_l4t_type {
225 enum hns3_pkt_ol3t_type {
228 HNS3_OL3T_IPV4_NO_CSUM,
232 enum hns3_pkt_tun_type {
239 /* hardware spec ring buffer format */
240 struct __packed hns3_desc {
254 __le32 type_cs_vlan_tso_len;
256 __u8 type_cs_vlan_tso;
262 __le16 outer_vlan_tag;
266 __le32 ol_type_vlan_len_msec;
268 __u8 ol_type_vlan_msec;
276 __le16 bdtp_fe_sc_vld_ra_ri;
292 __le16 o_dm_vlan_id_fb;
302 enum hns3_desc_type {
303 DESC_TYPE_UNKNOWN = 0,
304 DESC_TYPE_SKB = 1 << 0,
305 DESC_TYPE_FRAGLIST_SKB = 1 << 1,
306 DESC_TYPE_PAGE = 1 << 2,
307 DESC_TYPE_BOUNCE_ALL = 1 << 3,
308 DESC_TYPE_BOUNCE_HEAD = 1 << 4,
309 DESC_TYPE_SGL_SKB = 1 << 5,
312 struct hns3_desc_cb {
313 dma_addr_t dma; /* dma address of this desc */
314 void *buf; /* cpu addr for a desc */
316 /* priv data for the desc, e.g. skb when use with ip stack */
320 u32 page_offset; /* for rx */
321 u32 send_bytes; /* for tx */
324 u32 length; /* length of the buffer */
328 /* desc type, used by the ring user to mark the type of the priv data */
333 enum hns3_pkt_l3type {
338 HNS3_L3_TYPE_IPV4_OPT,
339 HNS3_L3_TYPE_IPV6_EXT,
342 HNS3_L3_TYPE_MAC_PAUSE,
343 HNS3_L3_TYPE_PFC_PAUSE,/* 0x9*/
345 /* reserved for 0xA~0xB */
347 HNS3_L3_TYPE_CNM = 0xc,
349 /* reserved for 0xD~0xE */
351 HNS3_L3_TYPE_PARSE_FAIL = 0xf /* must be last */
354 enum hns3_pkt_l4type {
362 /* reserved for 0x6~0xE */
364 HNS3_L4_TYPE_PARSE_FAIL = 0xf /* must be last */
367 enum hns3_pkt_ol3type {
368 HNS3_OL3_TYPE_IPV4 = 0,
370 /* reserved for 0x2~0x3 */
371 HNS3_OL3_TYPE_IPV4_OPT = 4,
372 HNS3_OL3_TYPE_IPV6_EXT,
374 /* reserved for 0x6~0xE */
376 HNS3_OL3_TYPE_PARSE_FAIL = 0xf /* must be last */
379 enum hns3_pkt_ol4type {
380 HNS3_OL4_TYPE_NO_TUN,
381 HNS3_OL4_TYPE_MAC_IN_UDP,
383 HNS3_OL4_TYPE_UNKNOWN
386 struct hns3_rx_ptype {
409 u64 over_max_recursion;
435 struct hns3_tx_spare {
444 struct hns3_enet_ring {
445 struct hns3_desc *desc; /* dma map address space */
446 struct hns3_desc_cb *desc_cb;
447 struct hns3_enet_ring *next;
448 struct hns3_enet_tqp_vector *tqp_vector;
449 struct hnae3_queue *tqp;
451 struct device *dev; /* will be used for DMA mapping of descriptors */
454 struct ring_stats stats;
455 struct u64_stats_sync syncp;
457 dma_addr_t desc_dma_addr;
458 u32 buf_size; /* size for hnae_desc->addr, preset by AE */
459 u16 desc_num; /* total number of desc */
460 int next_to_use; /* idx of next spare desc */
462 /* idx of lastest sent desc, the ring is empty when equal to
466 u32 flag; /* ring attribute */
473 int last_to_use; /* last idx used by xmit */
475 struct hns3_tx_spare *tx_spare;
480 u32 pull_len; /* memcpy len for current rx packet */
482 /* first buffer address for current packet */
485 struct sk_buff *tail_skb;
488 } ____cacheline_internodealigned_in_smp;
490 enum hns3_flow_level_range {
497 #define HNS3_INT_GL_50K 0x0014
498 #define HNS3_INT_GL_20K 0x0032
499 #define HNS3_INT_GL_18K 0x0036
500 #define HNS3_INT_GL_8K 0x007C
502 #define HNS3_INT_GL_1US BIT(31)
504 #define HNS3_INT_RL_MAX 0x00EC
505 #define HNS3_INT_RL_ENABLE_MASK 0x40
507 #define HNS3_INT_QL_DEFAULT_CFG 0x20
509 struct hns3_enet_coalesce {
516 enum hns3_flow_level_range flow_level;
519 struct hns3_enet_ring_group {
520 /* array of pointers to rings */
521 struct hns3_enet_ring *ring;
522 u64 total_bytes; /* total bytes processed this group */
523 u64 total_packets; /* total packets processed this group */
525 struct hns3_enet_coalesce coal;
529 struct hns3_enet_tqp_vector {
530 struct hnae3_handle *handle;
531 u8 __iomem *mask_addr;
535 u16 idx; /* index in the TQP vector array per handle. */
537 struct napi_struct napi;
539 struct hns3_enet_ring_group rx_group;
540 struct hns3_enet_ring_group tx_group;
542 cpumask_t affinity_mask;
543 u16 num_tqps; /* total number of tqps in TQP vector */
544 struct irq_affinity_notify affinity_notify;
546 char name[HNAE3_INT_NAME_LEN];
549 } ____cacheline_internodealigned_in_smp;
551 struct hns3_nic_priv {
552 struct hnae3_handle *ae_handle;
553 struct net_device *netdev;
557 * the cb for nic to manage the ring buffer, the first half of the
558 * array is for tx_ring and vice versa for the second half
560 struct hns3_enet_ring *ring;
561 struct hns3_enet_tqp_vector *tqp_vector;
563 u8 max_non_tso_bd_num;
565 u64 tx_timeout_count;
569 struct hns3_enet_coalesce tx_coal;
570 struct hns3_enet_coalesce rx_coal;
583 struct gre_base_hdr *gre;
587 struct hns3_hw_error_info {
588 enum hnae3_hw_error_type type;
592 static inline int ring_space(struct hns3_enet_ring *ring)
594 /* This smp_load_acquire() pairs with smp_store_release() in
595 * hns3_nic_reclaim_one_desc called by hns3_clean_tx_ring.
597 int begin = smp_load_acquire(&ring->next_to_clean);
598 int end = READ_ONCE(ring->next_to_use);
600 return ((end >= begin) ? (ring->desc_num - end + begin) :
604 static inline u32 hns3_read_reg(void __iomem *base, u32 reg)
606 return readl(base + reg);
609 static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value)
611 u8 __iomem *reg_addr = READ_ONCE(base);
613 writel(value, reg_addr + reg);
616 #define hns3_read_dev(a, reg) \
617 hns3_read_reg((a)->io_base, reg)
619 static inline bool hns3_nic_resetting(struct net_device *netdev)
621 struct hns3_nic_priv *priv = netdev_priv(netdev);
623 return test_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
626 #define hns3_write_dev(a, reg, value) \
627 hns3_write_reg((a)->io_base, reg, value)
629 #define ring_to_dev(ring) ((ring)->dev)
631 #define ring_to_netdev(ring) ((ring)->tqp_vector->napi.dev)
633 #define ring_to_dma_dir(ring) (HNAE3_IS_TX_RING(ring) ? \
634 DMA_TO_DEVICE : DMA_FROM_DEVICE)
636 #define hns3_buf_size(_ring) ((_ring)->buf_size)
638 static inline unsigned int hns3_page_order(struct hns3_enet_ring *ring)
640 #if (PAGE_SIZE < 8192)
641 if (ring->buf_size > (PAGE_SIZE / 2))
647 #define hns3_page_size(_ring) (PAGE_SIZE << hns3_page_order(_ring))
649 /* iterator for handling rings in ring group */
650 #define hns3_for_each_ring(pos, head) \
651 for (pos = (head).ring; (pos); pos = (pos)->next)
653 #define hns3_get_handle(ndev) \
654 (((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle)
656 #define hns3_gl_usec_to_reg(int_gl) ((int_gl) >> 1)
657 #define hns3_gl_round_down(int_gl) round_down(int_gl, 2)
659 #define hns3_rl_usec_to_reg(int_rl) ((int_rl) >> 2)
660 #define hns3_rl_round_down(int_rl) round_down(int_rl, 4)
662 void hns3_ethtool_set_ops(struct net_device *netdev);
663 int hns3_set_channels(struct net_device *netdev,
664 struct ethtool_channels *ch);
666 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget);
667 int hns3_init_all_ring(struct hns3_nic_priv *priv);
668 int hns3_nic_reset_all_ring(struct hnae3_handle *h);
669 void hns3_fini_ring(struct hns3_enet_ring *ring);
670 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev);
671 bool hns3_is_phys_func(struct pci_dev *pdev);
672 int hns3_clean_rx_ring(
673 struct hns3_enet_ring *ring, int budget,
674 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *));
676 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
678 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
680 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
682 void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector,
684 void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector,
687 void hns3_request_update_promisc_mode(struct hnae3_handle *handle);
689 #ifdef CONFIG_HNS3_DCB
690 void hns3_dcbnl_setup(struct hnae3_handle *handle);
692 static inline void hns3_dcbnl_setup(struct hnae3_handle *handle) {}
695 int hns3_dbg_init(struct hnae3_handle *handle);
696 void hns3_dbg_uninit(struct hnae3_handle *handle);
697 void hns3_dbg_register_debugfs(const char *debugfs_dir_name);
698 void hns3_dbg_unregister_debugfs(void);
699 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size);
700 u16 hns3_get_max_available_channels(struct hnae3_handle *h);