drivers/net/ethernet/hisilicon/hns3/hns3_enet.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4 #include <linux/dma-mapping.h>
   5 #include <linux/etherdevice.h>
   6 #include <linux/interrupt.h>
   7 #ifdef CONFIG_RFS_ACCEL
   8 #include <linux/cpu_rmap.h>
   9 #endif
  10 #include <linux/if_vlan.h>
  11 #include <linux/irq.h>
  12 #include <linux/ip.h>
  13 #include <linux/ipv6.h>
  14 #include <linux/module.h>
  15 #include <linux/pci.h>
  16 #include <linux/skbuff.h>
  17 #include <linux/sctp.h>
  18 #include <net/gre.h>
  19 #include <net/gro.h>
  20 #include <net/ip6_checksum.h>
  21 #include <net/pkt_cls.h>
  22 #include <net/pkt_sched.h>
  23 #include <net/tcp.h>
  24 #include <net/vxlan.h>
  25 #include <net/geneve.h>
  26
  27 #include "hnae3.h"
  28 #include "hns3_enet.h"
  29 /* All hns3 tracepoints are defined by the include below, which
  30  * must be included exactly once across the whole kernel with
  31  * CREATE_TRACE_POINTS defined
  32  */
  33 #define CREATE_TRACE_POINTS
  34 #include "hns3_trace.h"
  35
  36 #define hns3_set_field(origin, shift, val)      ((origin) |= (val) << (shift))
  37 #define hns3_tx_bd_count(S)     DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
  38
  39 #define hns3_rl_err(fmt, ...)                                           \
  40         do {                                                            \
  41                 if (net_ratelimit())                                    \
  42                         netdev_err(fmt, ##__VA_ARGS__);                 \
  43         } while (0)
  44
  45 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force);
  46
  47 static const char hns3_driver_name[] = "hns3";
  48 static const char hns3_driver_string[] =
  49                         "Hisilicon Ethernet Network Driver for Hip08 Family";
  50 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
  51 static struct hnae3_client client;
  52
  53 static int debug = -1;
  54 module_param(debug, int, 0);
  55 MODULE_PARM_DESC(debug, " Network interface message level setting");
  56
  57 static unsigned int tx_sgl = 1;
  58 module_param(tx_sgl, uint, 0600);
  59 MODULE_PARM_DESC(tx_sgl, "Minimum number of frags when using dma_map_sg() to optimize the IOMMU mapping");
  60
  61 static bool page_pool_enabled = true;
  62 module_param(page_pool_enabled, bool, 0400);
  63
  64 #define HNS3_SGL_SIZE(nfrag)    (sizeof(struct scatterlist) * (nfrag) + \
  65                                  sizeof(struct sg_table))
  66 #define HNS3_MAX_SGL_SIZE       ALIGN(HNS3_SGL_SIZE(HNS3_MAX_TSO_BD_NUM), \
  67                                       dma_get_cache_alignment())
  68
  69 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
  70                            NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
  71
  72 #define HNS3_INNER_VLAN_TAG     1
  73 #define HNS3_OUTER_VLAN_TAG     2
  74
  75 #define HNS3_MIN_TX_LEN         33U
  76 #define HNS3_MIN_TUN_PKT_LEN    65U
  77
  78 /* hns3_pci_tbl - PCI Device ID Table
  79  *
  80  * Last entry must be all 0s
  81  *
  82  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  83  *   Class, Class Mask, private data (not used) }
  84  */
  85 static const struct pci_device_id hns3_pci_tbl[] = {
  86         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
  87         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
  88         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
  89          HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
  90         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
  91          HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
  92         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
  93          HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
  94         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
  95          HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
  96         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
  97          HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
  98         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA),
  99          HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
 100         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0},
 101         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
 102          HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
 103         /* required last entry */
 104         {0,}
 105 };
 106 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
 107
 108 #define HNS3_RX_PTYPE_ENTRY(ptype, l, s, t, h) \
 109         {       ptype, \
 110                 l, \
 111                 CHECKSUM_##s, \
 112                 HNS3_L3_TYPE_##t, \
 113                 1, \
 114                 h}
 115
 116 #define HNS3_RX_PTYPE_UNUSED_ENTRY(ptype) \
 117                 { ptype, 0, CHECKSUM_NONE, HNS3_L3_TYPE_PARSE_FAIL, 0, \
 118                   PKT_HASH_TYPE_NONE }
 119
 120 static const struct hns3_rx_ptype hns3_rx_ptype_tbl[] = {
 121         HNS3_RX_PTYPE_UNUSED_ENTRY(0),
 122         HNS3_RX_PTYPE_ENTRY(1, 0, COMPLETE, ARP, PKT_HASH_TYPE_NONE),
 123         HNS3_RX_PTYPE_ENTRY(2, 0, COMPLETE, RARP, PKT_HASH_TYPE_NONE),
 124         HNS3_RX_PTYPE_ENTRY(3, 0, COMPLETE, LLDP, PKT_HASH_TYPE_NONE),
 125         HNS3_RX_PTYPE_ENTRY(4, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
 126         HNS3_RX_PTYPE_ENTRY(5, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
 127         HNS3_RX_PTYPE_ENTRY(6, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
 128         HNS3_RX_PTYPE_ENTRY(7, 0, COMPLETE, CNM, PKT_HASH_TYPE_NONE),
 129         HNS3_RX_PTYPE_ENTRY(8, 0, NONE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
 130         HNS3_RX_PTYPE_UNUSED_ENTRY(9),
 131         HNS3_RX_PTYPE_UNUSED_ENTRY(10),
 132         HNS3_RX_PTYPE_UNUSED_ENTRY(11),
 133         HNS3_RX_PTYPE_UNUSED_ENTRY(12),
 134         HNS3_RX_PTYPE_UNUSED_ENTRY(13),
 135         HNS3_RX_PTYPE_UNUSED_ENTRY(14),
 136         HNS3_RX_PTYPE_UNUSED_ENTRY(15),
 137         HNS3_RX_PTYPE_ENTRY(16, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
 138         HNS3_RX_PTYPE_ENTRY(17, 0, COMPLETE, IPV4, PKT_HASH_TYPE_NONE),
 139         HNS3_RX_PTYPE_ENTRY(18, 0, COMPLETE, IPV4, PKT_HASH_TYPE_NONE),
 140         HNS3_RX_PTYPE_ENTRY(19, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
 141         HNS3_RX_PTYPE_ENTRY(20, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
 142         HNS3_RX_PTYPE_ENTRY(21, 0, NONE, IPV4, PKT_HASH_TYPE_NONE),
 143         HNS3_RX_PTYPE_ENTRY(22, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
 144         HNS3_RX_PTYPE_ENTRY(23, 0, NONE, IPV4, PKT_HASH_TYPE_L3),
 145         HNS3_RX_PTYPE_ENTRY(24, 0, NONE, IPV4, PKT_HASH_TYPE_L3),
 146         HNS3_RX_PTYPE_ENTRY(25, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
 147         HNS3_RX_PTYPE_UNUSED_ENTRY(26),
 148         HNS3_RX_PTYPE_UNUSED_ENTRY(27),
 149         HNS3_RX_PTYPE_UNUSED_ENTRY(28),
 150         HNS3_RX_PTYPE_ENTRY(29, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
 151         HNS3_RX_PTYPE_ENTRY(30, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
 152         HNS3_RX_PTYPE_ENTRY(31, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
 153         HNS3_RX_PTYPE_ENTRY(32, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
 154         HNS3_RX_PTYPE_ENTRY(33, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
 155         HNS3_RX_PTYPE_ENTRY(34, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
 156         HNS3_RX_PTYPE_ENTRY(35, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
 157         HNS3_RX_PTYPE_ENTRY(36, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
 158         HNS3_RX_PTYPE_ENTRY(37, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
 159         HNS3_RX_PTYPE_UNUSED_ENTRY(38),
 160         HNS3_RX_PTYPE_ENTRY(39, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
 161         HNS3_RX_PTYPE_ENTRY(40, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
 162         HNS3_RX_PTYPE_ENTRY(41, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
 163         HNS3_RX_PTYPE_ENTRY(42, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
 164         HNS3_RX_PTYPE_ENTRY(43, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
 165         HNS3_RX_PTYPE_ENTRY(44, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
 166         HNS3_RX_PTYPE_ENTRY(45, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
 167         HNS3_RX_PTYPE_UNUSED_ENTRY(46),
 168         HNS3_RX_PTYPE_UNUSED_ENTRY(47),
 169         HNS3_RX_PTYPE_UNUSED_ENTRY(48),
 170         HNS3_RX_PTYPE_UNUSED_ENTRY(49),
 171         HNS3_RX_PTYPE_UNUSED_ENTRY(50),
 172         HNS3_RX_PTYPE_UNUSED_ENTRY(51),
 173         HNS3_RX_PTYPE_UNUSED_ENTRY(52),
 174         HNS3_RX_PTYPE_UNUSED_ENTRY(53),
 175         HNS3_RX_PTYPE_UNUSED_ENTRY(54),
 176         HNS3_RX_PTYPE_UNUSED_ENTRY(55),
 177         HNS3_RX_PTYPE_UNUSED_ENTRY(56),
 178         HNS3_RX_PTYPE_UNUSED_ENTRY(57),
 179         HNS3_RX_PTYPE_UNUSED_ENTRY(58),
 180         HNS3_RX_PTYPE_UNUSED_ENTRY(59),
 181         HNS3_RX_PTYPE_UNUSED_ENTRY(60),
 182         HNS3_RX_PTYPE_UNUSED_ENTRY(61),
 183         HNS3_RX_PTYPE_UNUSED_ENTRY(62),
 184         HNS3_RX_PTYPE_UNUSED_ENTRY(63),
 185         HNS3_RX_PTYPE_UNUSED_ENTRY(64),
 186         HNS3_RX_PTYPE_UNUSED_ENTRY(65),
 187         HNS3_RX_PTYPE_UNUSED_ENTRY(66),
 188         HNS3_RX_PTYPE_UNUSED_ENTRY(67),
 189         HNS3_RX_PTYPE_UNUSED_ENTRY(68),
 190         HNS3_RX_PTYPE_UNUSED_ENTRY(69),
 191         HNS3_RX_PTYPE_UNUSED_ENTRY(70),
 192         HNS3_RX_PTYPE_UNUSED_ENTRY(71),
 193         HNS3_RX_PTYPE_UNUSED_ENTRY(72),
 194         HNS3_RX_PTYPE_UNUSED_ENTRY(73),
 195         HNS3_RX_PTYPE_UNUSED_ENTRY(74),
 196         HNS3_RX_PTYPE_UNUSED_ENTRY(75),
 197         HNS3_RX_PTYPE_UNUSED_ENTRY(76),
 198         HNS3_RX_PTYPE_UNUSED_ENTRY(77),
 199         HNS3_RX_PTYPE_UNUSED_ENTRY(78),
 200         HNS3_RX_PTYPE_UNUSED_ENTRY(79),
 201         HNS3_RX_PTYPE_UNUSED_ENTRY(80),
 202         HNS3_RX_PTYPE_UNUSED_ENTRY(81),
 203         HNS3_RX_PTYPE_UNUSED_ENTRY(82),
 204         HNS3_RX_PTYPE_UNUSED_ENTRY(83),
 205         HNS3_RX_PTYPE_UNUSED_ENTRY(84),
 206         HNS3_RX_PTYPE_UNUSED_ENTRY(85),
 207         HNS3_RX_PTYPE_UNUSED_ENTRY(86),
 208         HNS3_RX_PTYPE_UNUSED_ENTRY(87),
 209         HNS3_RX_PTYPE_UNUSED_ENTRY(88),
 210         HNS3_RX_PTYPE_UNUSED_ENTRY(89),
 211         HNS3_RX_PTYPE_UNUSED_ENTRY(90),
 212         HNS3_RX_PTYPE_UNUSED_ENTRY(91),
 213         HNS3_RX_PTYPE_UNUSED_ENTRY(92),
 214         HNS3_RX_PTYPE_UNUSED_ENTRY(93),
 215         HNS3_RX_PTYPE_UNUSED_ENTRY(94),
 216         HNS3_RX_PTYPE_UNUSED_ENTRY(95),
 217         HNS3_RX_PTYPE_UNUSED_ENTRY(96),
 218         HNS3_RX_PTYPE_UNUSED_ENTRY(97),
 219         HNS3_RX_PTYPE_UNUSED_ENTRY(98),
 220         HNS3_RX_PTYPE_UNUSED_ENTRY(99),
 221         HNS3_RX_PTYPE_UNUSED_ENTRY(100),
 222         HNS3_RX_PTYPE_UNUSED_ENTRY(101),
 223         HNS3_RX_PTYPE_UNUSED_ENTRY(102),
 224         HNS3_RX_PTYPE_UNUSED_ENTRY(103),
 225         HNS3_RX_PTYPE_UNUSED_ENTRY(104),
 226         HNS3_RX_PTYPE_UNUSED_ENTRY(105),
 227         HNS3_RX_PTYPE_UNUSED_ENTRY(106),
 228         HNS3_RX_PTYPE_UNUSED_ENTRY(107),
 229         HNS3_RX_PTYPE_UNUSED_ENTRY(108),
 230         HNS3_RX_PTYPE_UNUSED_ENTRY(109),
 231         HNS3_RX_PTYPE_UNUSED_ENTRY(110),
 232         HNS3_RX_PTYPE_ENTRY(111, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
 233         HNS3_RX_PTYPE_ENTRY(112, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
 234         HNS3_RX_PTYPE_ENTRY(113, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
 235         HNS3_RX_PTYPE_ENTRY(114, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
 236         HNS3_RX_PTYPE_ENTRY(115, 0, NONE, IPV6, PKT_HASH_TYPE_L3),
 237         HNS3_RX_PTYPE_ENTRY(116, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
 238         HNS3_RX_PTYPE_ENTRY(117, 0, NONE, IPV6, PKT_HASH_TYPE_L3),
 239         HNS3_RX_PTYPE_ENTRY(118, 0, NONE, IPV6, PKT_HASH_TYPE_L3),
 240         HNS3_RX_PTYPE_ENTRY(119, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
 241         HNS3_RX_PTYPE_UNUSED_ENTRY(120),
 242         HNS3_RX_PTYPE_UNUSED_ENTRY(121),
 243         HNS3_RX_PTYPE_UNUSED_ENTRY(122),
 244         HNS3_RX_PTYPE_ENTRY(123, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
 245         HNS3_RX_PTYPE_ENTRY(124, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
 246         HNS3_RX_PTYPE_ENTRY(125, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
 247         HNS3_RX_PTYPE_ENTRY(126, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
 248         HNS3_RX_PTYPE_ENTRY(127, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
 249         HNS3_RX_PTYPE_ENTRY(128, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
 250         HNS3_RX_PTYPE_ENTRY(129, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
 251         HNS3_RX_PTYPE_ENTRY(130, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
 252         HNS3_RX_PTYPE_ENTRY(131, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
 253         HNS3_RX_PTYPE_UNUSED_ENTRY(132),
 254         HNS3_RX_PTYPE_ENTRY(133, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
 255         HNS3_RX_PTYPE_ENTRY(134, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
 256         HNS3_RX_PTYPE_ENTRY(135, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
 257         HNS3_RX_PTYPE_ENTRY(136, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
 258         HNS3_RX_PTYPE_ENTRY(137, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
 259         HNS3_RX_PTYPE_ENTRY(138, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
 260         HNS3_RX_PTYPE_ENTRY(139, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
 261         HNS3_RX_PTYPE_UNUSED_ENTRY(140),
 262         HNS3_RX_PTYPE_UNUSED_ENTRY(141),
 263         HNS3_RX_PTYPE_UNUSED_ENTRY(142),
 264         HNS3_RX_PTYPE_UNUSED_ENTRY(143),
 265         HNS3_RX_PTYPE_UNUSED_ENTRY(144),
 266         HNS3_RX_PTYPE_UNUSED_ENTRY(145),
 267         HNS3_RX_PTYPE_UNUSED_ENTRY(146),
 268         HNS3_RX_PTYPE_UNUSED_ENTRY(147),
 269         HNS3_RX_PTYPE_UNUSED_ENTRY(148),
 270         HNS3_RX_PTYPE_UNUSED_ENTRY(149),
 271         HNS3_RX_PTYPE_UNUSED_ENTRY(150),
 272         HNS3_RX_PTYPE_UNUSED_ENTRY(151),
 273         HNS3_RX_PTYPE_UNUSED_ENTRY(152),
 274         HNS3_RX_PTYPE_UNUSED_ENTRY(153),
 275         HNS3_RX_PTYPE_UNUSED_ENTRY(154),
 276         HNS3_RX_PTYPE_UNUSED_ENTRY(155),
 277         HNS3_RX_PTYPE_UNUSED_ENTRY(156),
 278         HNS3_RX_PTYPE_UNUSED_ENTRY(157),
 279         HNS3_RX_PTYPE_UNUSED_ENTRY(158),
 280         HNS3_RX_PTYPE_UNUSED_ENTRY(159),
 281         HNS3_RX_PTYPE_UNUSED_ENTRY(160),
 282         HNS3_RX_PTYPE_UNUSED_ENTRY(161),
 283         HNS3_RX_PTYPE_UNUSED_ENTRY(162),
 284         HNS3_RX_PTYPE_UNUSED_ENTRY(163),
 285         HNS3_RX_PTYPE_UNUSED_ENTRY(164),
 286         HNS3_RX_PTYPE_UNUSED_ENTRY(165),
 287         HNS3_RX_PTYPE_UNUSED_ENTRY(166),
 288         HNS3_RX_PTYPE_UNUSED_ENTRY(167),
 289         HNS3_RX_PTYPE_UNUSED_ENTRY(168),
 290         HNS3_RX_PTYPE_UNUSED_ENTRY(169),
 291         HNS3_RX_PTYPE_UNUSED_ENTRY(170),
 292         HNS3_RX_PTYPE_UNUSED_ENTRY(171),
 293         HNS3_RX_PTYPE_UNUSED_ENTRY(172),
 294         HNS3_RX_PTYPE_UNUSED_ENTRY(173),
 295         HNS3_RX_PTYPE_UNUSED_ENTRY(174),
 296         HNS3_RX_PTYPE_UNUSED_ENTRY(175),
 297         HNS3_RX_PTYPE_UNUSED_ENTRY(176),
 298         HNS3_RX_PTYPE_UNUSED_ENTRY(177),
 299         HNS3_RX_PTYPE_UNUSED_ENTRY(178),
 300         HNS3_RX_PTYPE_UNUSED_ENTRY(179),
 301         HNS3_RX_PTYPE_UNUSED_ENTRY(180),
 302         HNS3_RX_PTYPE_UNUSED_ENTRY(181),
 303         HNS3_RX_PTYPE_UNUSED_ENTRY(182),
 304         HNS3_RX_PTYPE_UNUSED_ENTRY(183),
 305         HNS3_RX_PTYPE_UNUSED_ENTRY(184),
 306         HNS3_RX_PTYPE_UNUSED_ENTRY(185),
 307         HNS3_RX_PTYPE_UNUSED_ENTRY(186),
 308         HNS3_RX_PTYPE_UNUSED_ENTRY(187),
 309         HNS3_RX_PTYPE_UNUSED_ENTRY(188),
 310         HNS3_RX_PTYPE_UNUSED_ENTRY(189),
 311         HNS3_RX_PTYPE_UNUSED_ENTRY(190),
 312         HNS3_RX_PTYPE_UNUSED_ENTRY(191),
 313         HNS3_RX_PTYPE_UNUSED_ENTRY(192),
 314         HNS3_RX_PTYPE_UNUSED_ENTRY(193),
 315         HNS3_RX_PTYPE_UNUSED_ENTRY(194),
 316         HNS3_RX_PTYPE_UNUSED_ENTRY(195),
 317         HNS3_RX_PTYPE_UNUSED_ENTRY(196),
 318         HNS3_RX_PTYPE_UNUSED_ENTRY(197),
 319         HNS3_RX_PTYPE_UNUSED_ENTRY(198),
 320         HNS3_RX_PTYPE_UNUSED_ENTRY(199),
 321         HNS3_RX_PTYPE_UNUSED_ENTRY(200),
 322         HNS3_RX_PTYPE_UNUSED_ENTRY(201),
 323         HNS3_RX_PTYPE_UNUSED_ENTRY(202),
 324         HNS3_RX_PTYPE_UNUSED_ENTRY(203),
 325         HNS3_RX_PTYPE_UNUSED_ENTRY(204),
 326         HNS3_RX_PTYPE_UNUSED_ENTRY(205),
 327         HNS3_RX_PTYPE_UNUSED_ENTRY(206),
 328         HNS3_RX_PTYPE_UNUSED_ENTRY(207),
 329         HNS3_RX_PTYPE_UNUSED_ENTRY(208),
 330         HNS3_RX_PTYPE_UNUSED_ENTRY(209),
 331         HNS3_RX_PTYPE_UNUSED_ENTRY(210),
 332         HNS3_RX_PTYPE_UNUSED_ENTRY(211),
 333         HNS3_RX_PTYPE_UNUSED_ENTRY(212),
 334         HNS3_RX_PTYPE_UNUSED_ENTRY(213),
 335         HNS3_RX_PTYPE_UNUSED_ENTRY(214),
 336         HNS3_RX_PTYPE_UNUSED_ENTRY(215),
 337         HNS3_RX_PTYPE_UNUSED_ENTRY(216),
 338         HNS3_RX_PTYPE_UNUSED_ENTRY(217),
 339         HNS3_RX_PTYPE_UNUSED_ENTRY(218),
 340         HNS3_RX_PTYPE_UNUSED_ENTRY(219),
 341         HNS3_RX_PTYPE_UNUSED_ENTRY(220),
 342         HNS3_RX_PTYPE_UNUSED_ENTRY(221),
 343         HNS3_RX_PTYPE_UNUSED_ENTRY(222),
 344         HNS3_RX_PTYPE_UNUSED_ENTRY(223),
 345         HNS3_RX_PTYPE_UNUSED_ENTRY(224),
 346         HNS3_RX_PTYPE_UNUSED_ENTRY(225),
 347         HNS3_RX_PTYPE_UNUSED_ENTRY(226),
 348         HNS3_RX_PTYPE_UNUSED_ENTRY(227),
 349         HNS3_RX_PTYPE_UNUSED_ENTRY(228),
 350         HNS3_RX_PTYPE_UNUSED_ENTRY(229),
 351         HNS3_RX_PTYPE_UNUSED_ENTRY(230),
 352         HNS3_RX_PTYPE_UNUSED_ENTRY(231),
 353         HNS3_RX_PTYPE_UNUSED_ENTRY(232),
 354         HNS3_RX_PTYPE_UNUSED_ENTRY(233),
 355         HNS3_RX_PTYPE_UNUSED_ENTRY(234),
 356         HNS3_RX_PTYPE_UNUSED_ENTRY(235),
 357         HNS3_RX_PTYPE_UNUSED_ENTRY(236),
 358         HNS3_RX_PTYPE_UNUSED_ENTRY(237),
 359         HNS3_RX_PTYPE_UNUSED_ENTRY(238),
 360         HNS3_RX_PTYPE_UNUSED_ENTRY(239),
 361         HNS3_RX_PTYPE_UNUSED_ENTRY(240),
 362         HNS3_RX_PTYPE_UNUSED_ENTRY(241),
 363         HNS3_RX_PTYPE_UNUSED_ENTRY(242),
 364         HNS3_RX_PTYPE_UNUSED_ENTRY(243),
 365         HNS3_RX_PTYPE_UNUSED_ENTRY(244),
 366         HNS3_RX_PTYPE_UNUSED_ENTRY(245),
 367         HNS3_RX_PTYPE_UNUSED_ENTRY(246),
 368         HNS3_RX_PTYPE_UNUSED_ENTRY(247),
 369         HNS3_RX_PTYPE_UNUSED_ENTRY(248),
 370         HNS3_RX_PTYPE_UNUSED_ENTRY(249),
 371         HNS3_RX_PTYPE_UNUSED_ENTRY(250),
 372         HNS3_RX_PTYPE_UNUSED_ENTRY(251),
 373         HNS3_RX_PTYPE_UNUSED_ENTRY(252),
 374         HNS3_RX_PTYPE_UNUSED_ENTRY(253),
 375         HNS3_RX_PTYPE_UNUSED_ENTRY(254),
 376         HNS3_RX_PTYPE_UNUSED_ENTRY(255),
 377 };
 378
 379 #define HNS3_INVALID_PTYPE \
 380                 ARRAY_SIZE(hns3_rx_ptype_tbl)
 381
 382 static irqreturn_t hns3_irq_handle(int irq, void *vector)
 383 {
 384         struct hns3_enet_tqp_vector *tqp_vector = vector;
 385
 386         napi_schedule_irqoff(&tqp_vector->napi);
 387         tqp_vector->event_cnt++;
 388
 389         return IRQ_HANDLED;
 390 }
 391
 392 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
 393 {
 394         struct hns3_enet_tqp_vector *tqp_vectors;
 395         unsigned int i;
 396
 397         for (i = 0; i < priv->vector_num; i++) {
 398                 tqp_vectors = &priv->tqp_vector[i];
 399
 400                 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
 401                         continue;
 402
 403                 /* clear the affinity mask */
 404                 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
 405
 406                 /* release the irq resource */
 407                 free_irq(tqp_vectors->vector_irq, tqp_vectors);
 408                 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
 409         }
 410 }
 411
 412 static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
 413 {
 414         struct hns3_enet_tqp_vector *tqp_vectors;
 415         int txrx_int_idx = 0;
 416         int rx_int_idx = 0;
 417         int tx_int_idx = 0;
 418         unsigned int i;
 419         int ret;
 420
 421         for (i = 0; i < priv->vector_num; i++) {
 422                 tqp_vectors = &priv->tqp_vector[i];
 423
 424                 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
 425                         continue;
 426
 427                 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
 428                         snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
 429                                  "%s-%s-%s-%d", hns3_driver_name,
 430                                  pci_name(priv->ae_handle->pdev),
 431                                  "TxRx", txrx_int_idx++);
 432                         txrx_int_idx++;
 433                 } else if (tqp_vectors->rx_group.ring) {
 434                         snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
 435                                  "%s-%s-%s-%d", hns3_driver_name,
 436                                  pci_name(priv->ae_handle->pdev),
 437                                  "Rx", rx_int_idx++);
 438                 } else if (tqp_vectors->tx_group.ring) {
 439                         snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
 440                                  "%s-%s-%s-%d", hns3_driver_name,
 441                                  pci_name(priv->ae_handle->pdev),
 442                                  "Tx", tx_int_idx++);
 443                 } else {
 444                         /* Skip this unused q_vector */
 445                         continue;
 446                 }
 447
 448                 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
 449
 450                 irq_set_status_flags(tqp_vectors->vector_irq, IRQ_NOAUTOEN);
 451                 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
 452                                   tqp_vectors->name, tqp_vectors);
 453                 if (ret) {
 454                         netdev_err(priv->netdev, "request irq(%d) fail\n",
 455                                    tqp_vectors->vector_irq);
 456                         hns3_nic_uninit_irq(priv);
 457                         return ret;
 458                 }
 459
 460                 irq_set_affinity_hint(tqp_vectors->vector_irq,
 461                                       &tqp_vectors->affinity_mask);
 462
 463                 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
 464         }
 465
 466         return 0;
 467 }
 468
 469 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
 470                                  u32 mask_en)
 471 {
 472         writel(mask_en, tqp_vector->mask_addr);
 473 }
 474
 475 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
 476 {
 477         napi_enable(&tqp_vector->napi);
 478         enable_irq(tqp_vector->vector_irq);
 479
 480         /* enable vector */
 481         hns3_mask_vector_irq(tqp_vector, 1);
 482 }
 483
 484 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
 485 {
 486         /* disable vector */
 487         hns3_mask_vector_irq(tqp_vector, 0);
 488
 489         disable_irq(tqp_vector->vector_irq);
 490         napi_disable(&tqp_vector->napi);
 491         cancel_work_sync(&tqp_vector->rx_group.dim.work);
 492         cancel_work_sync(&tqp_vector->tx_group.dim.work);
 493 }
 494
 495 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
 496                                  u32 rl_value)
 497 {
 498         u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
 499
 500         /* this defines the configuration for RL (Interrupt Rate Limiter).
 501          * Rl defines rate of interrupts i.e. number of interrupts-per-second
 502          * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
 503          */
 504         if (rl_reg > 0 && !tqp_vector->tx_group.coal.adapt_enable &&
 505             !tqp_vector->rx_group.coal.adapt_enable)
 506                 /* According to the hardware, the range of rl_reg is
 507                  * 0-59 and the unit is 4.
 508                  */
 509                 rl_reg |=  HNS3_INT_RL_ENABLE_MASK;
 510
 511         writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
 512 }
 513
 514 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
 515                                     u32 gl_value)
 516 {
 517         u32 new_val;
 518
 519         if (tqp_vector->rx_group.coal.unit_1us)
 520                 new_val = gl_value | HNS3_INT_GL_1US;
 521         else
 522                 new_val = hns3_gl_usec_to_reg(gl_value);
 523
 524         writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
 525 }
 526
 527 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
 528                                     u32 gl_value)
 529 {
 530         u32 new_val;
 531
 532         if (tqp_vector->tx_group.coal.unit_1us)
 533                 new_val = gl_value | HNS3_INT_GL_1US;
 534         else
 535                 new_val = hns3_gl_usec_to_reg(gl_value);
 536
 537         writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
 538 }
 539
 540 void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector,
 541                                     u32 ql_value)
 542 {
 543         writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_TX_QL_OFFSET);
 544 }
 545
 546 void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector,
 547                                     u32 ql_value)
 548 {
 549         writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_RX_QL_OFFSET);
 550 }
 551
 552 static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector,
 553                                       struct hns3_nic_priv *priv)
 554 {
 555         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
 556         struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
 557         struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
 558         struct hns3_enet_coalesce *ptx_coal = &priv->tx_coal;
 559         struct hns3_enet_coalesce *prx_coal = &priv->rx_coal;
 560
 561         tx_coal->adapt_enable = ptx_coal->adapt_enable;
 562         rx_coal->adapt_enable = prx_coal->adapt_enable;
 563
 564         tx_coal->int_gl = ptx_coal->int_gl;
 565         rx_coal->int_gl = prx_coal->int_gl;
 566
 567         rx_coal->flow_level = prx_coal->flow_level;
 568         tx_coal->flow_level = ptx_coal->flow_level;
 569
 570         /* device version above V3(include V3), GL can configure 1us
 571          * unit, so uses 1us unit.
 572          */
 573         if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) {
 574                 tx_coal->unit_1us = 1;
 575                 rx_coal->unit_1us = 1;
 576         }
 577
 578         if (ae_dev->dev_specs.int_ql_max) {
 579                 tx_coal->ql_enable = 1;
 580                 rx_coal->ql_enable = 1;
 581                 tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
 582                 rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
 583                 tx_coal->int_ql = ptx_coal->int_ql;
 584                 rx_coal->int_ql = prx_coal->int_ql;
 585         }
 586 }
 587
 588 static void
 589 hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
 590                              struct hns3_nic_priv *priv)
 591 {
 592         struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
 593         struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
 594         struct hnae3_handle *h = priv->ae_handle;
 595
 596         hns3_set_vector_coalesce_tx_gl(tqp_vector, tx_coal->int_gl);
 597         hns3_set_vector_coalesce_rx_gl(tqp_vector, rx_coal->int_gl);
 598         hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
 599
 600         if (tx_coal->ql_enable)
 601                 hns3_set_vector_coalesce_tx_ql(tqp_vector, tx_coal->int_ql);
 602
 603         if (rx_coal->ql_enable)
 604                 hns3_set_vector_coalesce_rx_ql(tqp_vector, rx_coal->int_ql);
 605 }
 606
 607 static int hns3_nic_set_real_num_queue(struct net_device *netdev)
 608 {
 609         struct hnae3_handle *h = hns3_get_handle(netdev);
 610         struct hnae3_knic_private_info *kinfo = &h->kinfo;
 611         struct hnae3_tc_info *tc_info = &kinfo->tc_info;
 612         unsigned int queue_size = kinfo->num_tqps;
 613         int i, ret;
 614
 615         if (tc_info->num_tc <= 1 && !tc_info->mqprio_active) {
 616                 netdev_reset_tc(netdev);
 617         } else {
 618                 ret = netdev_set_num_tc(netdev, tc_info->num_tc);
 619                 if (ret) {
 620                         netdev_err(netdev,
 621                                    "netdev_set_num_tc fail, ret=%d!\n", ret);
 622                         return ret;
 623                 }
 624
 625                 for (i = 0; i < tc_info->num_tc; i++)
 626                         netdev_set_tc_queue(netdev, i, tc_info->tqp_count[i],
 627                                             tc_info->tqp_offset[i]);
 628         }
 629
 630         ret = netif_set_real_num_tx_queues(netdev, queue_size);
 631         if (ret) {
 632                 netdev_err(netdev,
 633                            "netif_set_real_num_tx_queues fail, ret=%d!\n", ret);
 634                 return ret;
 635         }
 636
 637         ret = netif_set_real_num_rx_queues(netdev, queue_size);
 638         if (ret) {
 639                 netdev_err(netdev,
 640                            "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
 641                 return ret;
 642         }
 643
 644         return 0;
 645 }
 646
 647 u16 hns3_get_max_available_channels(struct hnae3_handle *h)
 648 {
 649         u16 alloc_tqps, max_rss_size, rss_size;
 650
 651         h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
 652         rss_size = alloc_tqps / h->kinfo.tc_info.num_tc;
 653
 654         return min_t(u16, rss_size, max_rss_size);
 655 }
 656
 657 static void hns3_tqp_enable(struct hnae3_queue *tqp)
 658 {
 659         u32 rcb_reg;
 660
 661         rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
 662         rcb_reg |= BIT(HNS3_RING_EN_B);
 663         hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
 664 }
 665
 666 static void hns3_tqp_disable(struct hnae3_queue *tqp)
 667 {
 668         u32 rcb_reg;
 669
 670         rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
 671         rcb_reg &= ~BIT(HNS3_RING_EN_B);
 672         hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
 673 }
 674
 675 static void hns3_free_rx_cpu_rmap(struct net_device *netdev)
 676 {
 677 #ifdef CONFIG_RFS_ACCEL
 678         free_irq_cpu_rmap(netdev->rx_cpu_rmap);
 679         netdev->rx_cpu_rmap = NULL;
 680 #endif
 681 }
 682
 683 static int hns3_set_rx_cpu_rmap(struct net_device *netdev)
 684 {
 685 #ifdef CONFIG_RFS_ACCEL
 686         struct hns3_nic_priv *priv = netdev_priv(netdev);
 687         struct hns3_enet_tqp_vector *tqp_vector;
 688         int i, ret;
 689
 690         if (!netdev->rx_cpu_rmap) {
 691                 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num);
 692                 if (!netdev->rx_cpu_rmap)
 693                         return -ENOMEM;
 694         }
 695
 696         for (i = 0; i < priv->vector_num; i++) {
 697                 tqp_vector = &priv->tqp_vector[i];
 698                 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap,
 699                                        tqp_vector->vector_irq);
 700                 if (ret) {
 701                         hns3_free_rx_cpu_rmap(netdev);
 702                         return ret;
 703                 }
 704         }
 705 #endif
 706         return 0;
 707 }
 708
 709 static int hns3_nic_net_up(struct net_device *netdev)
 710 {
 711         struct hns3_nic_priv *priv = netdev_priv(netdev);
 712         struct hnae3_handle *h = priv->ae_handle;
 713         int i, j;
 714         int ret;
 715
 716         ret = hns3_nic_reset_all_ring(h);
 717         if (ret)
 718                 return ret;
 719
 720         clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
 721
 722         /* enable the vectors */
 723         for (i = 0; i < priv->vector_num; i++)
 724                 hns3_vector_enable(&priv->tqp_vector[i]);
 725
 726         /* enable rcb */
 727         for (j = 0; j < h->kinfo.num_tqps; j++)
 728                 hns3_tqp_enable(h->kinfo.tqp[j]);
 729
 730         /* start the ae_dev */
 731         ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
 732         if (ret) {
 733                 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
 734                 while (j--)
 735                         hns3_tqp_disable(h->kinfo.tqp[j]);
 736
 737                 for (j = i - 1; j >= 0; j--)
 738                         hns3_vector_disable(&priv->tqp_vector[j]);
 739         }
 740
 741         return ret;
 742 }
 743
 744 static void hns3_config_xps(struct hns3_nic_priv *priv)
 745 {
 746         int i;
 747
 748         for (i = 0; i < priv->vector_num; i++) {
 749                 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
 750                 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
 751
 752                 while (ring) {
 753                         int ret;
 754
 755                         ret = netif_set_xps_queue(priv->netdev,
 756                                                   &tqp_vector->affinity_mask,
 757                                                   ring->tqp->tqp_index);
 758                         if (ret)
 759                                 netdev_warn(priv->netdev,
 760                                             "set xps queue failed: %d", ret);
 761
 762                         ring = ring->next;
 763                 }
 764         }
 765 }
 766
 767 static int hns3_nic_net_open(struct net_device *netdev)
 768 {
 769         struct hns3_nic_priv *priv = netdev_priv(netdev);
 770         struct hnae3_handle *h = hns3_get_handle(netdev);
 771         struct hnae3_knic_private_info *kinfo;
 772         int i, ret;
 773
 774         if (hns3_nic_resetting(netdev))
 775                 return -EBUSY;
 776
 777         if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
 778                 netdev_warn(netdev, "net open repeatedly!\n");
 779                 return 0;
 780         }
 781
 782         netif_carrier_off(netdev);
 783
 784         ret = hns3_nic_set_real_num_queue(netdev);
 785         if (ret)
 786                 return ret;
 787
 788         ret = hns3_nic_net_up(netdev);
 789         if (ret) {
 790                 netdev_err(netdev, "net up fail, ret=%d!\n", ret);
 791                 return ret;
 792         }
 793
 794         kinfo = &h->kinfo;
 795         for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
 796                 netdev_set_prio_tc_map(netdev, i, kinfo->tc_info.prio_tc[i]);
 797
 798         if (h->ae_algo->ops->set_timer_task)
 799                 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
 800
 801         hns3_config_xps(priv);
 802
 803         netif_dbg(h, drv, netdev, "net open\n");
 804
 805         return 0;
 806 }
 807
 808 static void hns3_reset_tx_queue(struct hnae3_handle *h)
 809 {
 810         struct net_device *ndev = h->kinfo.netdev;
 811         struct hns3_nic_priv *priv = netdev_priv(ndev);
 812         struct netdev_queue *dev_queue;
 813         u32 i;
 814
 815         for (i = 0; i < h->kinfo.num_tqps; i++) {
 816                 dev_queue = netdev_get_tx_queue(ndev,
 817                                                 priv->ring[i].queue_index);
 818                 netdev_tx_reset_queue(dev_queue);
 819         }
 820 }
 821
 822 static void hns3_nic_net_down(struct net_device *netdev)
 823 {
 824         struct hns3_nic_priv *priv = netdev_priv(netdev);
 825         struct hnae3_handle *h = hns3_get_handle(netdev);
 826         const struct hnae3_ae_ops *ops;
 827         int i;
 828
 829         /* disable vectors */
 830         for (i = 0; i < priv->vector_num; i++)
 831                 hns3_vector_disable(&priv->tqp_vector[i]);
 832
 833         /* disable rcb */
 834         for (i = 0; i < h->kinfo.num_tqps; i++)
 835                 hns3_tqp_disable(h->kinfo.tqp[i]);
 836
 837         /* stop ae_dev */
 838         ops = priv->ae_handle->ae_algo->ops;
 839         if (ops->stop)
 840                 ops->stop(priv->ae_handle);
 841
 842         /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
 843          * during reset process, because driver may not be able
 844          * to disable the ring through firmware when downing the netdev.
 845          */
 846         if (!hns3_nic_resetting(netdev))
 847                 hns3_clear_all_ring(priv->ae_handle, false);
 848
 849         hns3_reset_tx_queue(priv->ae_handle);
 850 }
 851
 852 static int hns3_nic_net_stop(struct net_device *netdev)
 853 {
 854         struct hns3_nic_priv *priv = netdev_priv(netdev);
 855         struct hnae3_handle *h = hns3_get_handle(netdev);
 856
 857         if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
 858                 return 0;
 859
 860         netif_dbg(h, drv, netdev, "net stop\n");
 861
 862         if (h->ae_algo->ops->set_timer_task)
 863                 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
 864
 865         netif_carrier_off(netdev);
 866         netif_tx_disable(netdev);
 867
 868         hns3_nic_net_down(netdev);
 869
 870         return 0;
 871 }
 872
 873 static int hns3_nic_uc_sync(struct net_device *netdev,
 874                             const unsigned char *addr)
 875 {
 876         struct hnae3_handle *h = hns3_get_handle(netdev);
 877
 878         if (h->ae_algo->ops->add_uc_addr)
 879                 return h->ae_algo->ops->add_uc_addr(h, addr);
 880
 881         return 0;
 882 }
 883
 884 static int hns3_nic_uc_unsync(struct net_device *netdev,
 885                               const unsigned char *addr)
 886 {
 887         struct hnae3_handle *h = hns3_get_handle(netdev);
 888
 889         /* need ignore the request of removing device address, because
 890          * we store the device address and other addresses of uc list
 891          * in the function's mac filter list.
 892          */
 893         if (ether_addr_equal(addr, netdev->dev_addr))
 894                 return 0;
 895
 896         if (h->ae_algo->ops->rm_uc_addr)
 897                 return h->ae_algo->ops->rm_uc_addr(h, addr);
 898
 899         return 0;
 900 }
 901
 902 static int hns3_nic_mc_sync(struct net_device *netdev,
 903                             const unsigned char *addr)
 904 {
 905         struct hnae3_handle *h = hns3_get_handle(netdev);
 906
 907         if (h->ae_algo->ops->add_mc_addr)
 908                 return h->ae_algo->ops->add_mc_addr(h, addr);
 909
 910         return 0;
 911 }
 912
 913 static int hns3_nic_mc_unsync(struct net_device *netdev,
 914                               const unsigned char *addr)
 915 {
 916         struct hnae3_handle *h = hns3_get_handle(netdev);
 917
 918         if (h->ae_algo->ops->rm_mc_addr)
 919                 return h->ae_algo->ops->rm_mc_addr(h, addr);
 920
 921         return 0;
 922 }
 923
 924 static u8 hns3_get_netdev_flags(struct net_device *netdev)
 925 {
 926         u8 flags = 0;
 927
 928         if (netdev->flags & IFF_PROMISC)
 929                 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
 930         else if (netdev->flags & IFF_ALLMULTI)
 931                 flags = HNAE3_USER_MPE;
 932
 933         return flags;
 934 }
 935
 936 static void hns3_nic_set_rx_mode(struct net_device *netdev)
 937 {
 938         struct hnae3_handle *h = hns3_get_handle(netdev);
 939         u8 new_flags;
 940
 941         new_flags = hns3_get_netdev_flags(netdev);
 942
 943         __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
 944         __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync);
 945
 946         /* User mode Promisc mode enable and vlan filtering is disabled to
 947          * let all packets in.
 948          */
 949         h->netdev_flags = new_flags;
 950         hns3_request_update_promisc_mode(h);
 951 }
 952
 953 void hns3_request_update_promisc_mode(struct hnae3_handle *handle)
 954 {
 955         const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
 956
 957         if (ops->request_update_promisc_mode)
 958                 ops->request_update_promisc_mode(handle);
 959 }
 960
 961 static u32 hns3_tx_spare_space(struct hns3_enet_ring *ring)
 962 {
 963         struct hns3_tx_spare *tx_spare = ring->tx_spare;
 964         u32 ntc, ntu;
 965
 966         /* This smp_load_acquire() pairs with smp_store_release() in
 967          * hns3_tx_spare_update() called in tx desc cleaning process.
 968          */
 969         ntc = smp_load_acquire(&tx_spare->last_to_clean);
 970         ntu = tx_spare->next_to_use;
 971
 972         if (ntc > ntu)
 973                 return ntc - ntu - 1;
 974
 975         /* The free tx buffer is divided into two part, so pick the
 976          * larger one.
 977          */
 978         return max(ntc, tx_spare->len - ntu) - 1;
 979 }
 980
 981 static void hns3_tx_spare_update(struct hns3_enet_ring *ring)
 982 {
 983         struct hns3_tx_spare *tx_spare = ring->tx_spare;
 984
 985         if (!tx_spare ||
 986             tx_spare->last_to_clean == tx_spare->next_to_clean)
 987                 return;
 988
 989         /* This smp_store_release() pairs with smp_load_acquire() in
 990          * hns3_tx_spare_space() called in xmit process.
 991          */
 992         smp_store_release(&tx_spare->last_to_clean,
 993                           tx_spare->next_to_clean);
 994 }
 995
 996 static bool hns3_can_use_tx_bounce(struct hns3_enet_ring *ring,
 997                                    struct sk_buff *skb,
 998                                    u32 space)
 999 {
1000         u32 len = skb->len <= ring->tx_copybreak ? skb->len :
1001                                 skb_headlen(skb);
1002
1003         if (len > ring->tx_copybreak)
1004                 return false;
1005
1006         if (ALIGN(len, dma_get_cache_alignment()) > space) {
1007                 hns3_ring_stats_update(ring, tx_spare_full);
1008                 return false;
1009         }
1010
1011         return true;
1012 }
1013
1014 static bool hns3_can_use_tx_sgl(struct hns3_enet_ring *ring,
1015                                 struct sk_buff *skb,
1016                                 u32 space)
1017 {
1018         if (skb->len <= ring->tx_copybreak || !tx_sgl ||
1019             (!skb_has_frag_list(skb) &&
1020              skb_shinfo(skb)->nr_frags < tx_sgl))
1021                 return false;
1022
1023         if (space < HNS3_MAX_SGL_SIZE) {
1024                 hns3_ring_stats_update(ring, tx_spare_full);
1025                 return false;
1026         }
1027
1028         return true;
1029 }
1030
1031 static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring)
1032 {
1033         u32 alloc_size = ring->tqp->handle->kinfo.tx_spare_buf_size;
1034         struct hns3_tx_spare *tx_spare;
1035         struct page *page;
1036         dma_addr_t dma;
1037         int order;
1038
1039         if (!alloc_size)
1040                 return;
1041
1042         order = get_order(alloc_size);
1043         if (order > MAX_ORDER) {
1044                 if (net_ratelimit())
1045                         dev_warn(ring_to_dev(ring), "failed to allocate tx spare buffer, exceed to max order\n");
1046                 return;
1047         }
1048
1049         tx_spare = devm_kzalloc(ring_to_dev(ring), sizeof(*tx_spare),
1050                                 GFP_KERNEL);
1051         if (!tx_spare) {
1052                 /* The driver still work without the tx spare buffer */
1053                 dev_warn(ring_to_dev(ring), "failed to allocate hns3_tx_spare\n");
1054                 goto devm_kzalloc_error;
1055         }
1056
1057         page = alloc_pages_node(dev_to_node(ring_to_dev(ring)),
1058                                 GFP_KERNEL, order);
1059         if (!page) {
1060                 dev_warn(ring_to_dev(ring), "failed to allocate tx spare pages\n");
1061                 goto alloc_pages_error;
1062         }
1063
1064         dma = dma_map_page(ring_to_dev(ring), page, 0,
1065                            PAGE_SIZE << order, DMA_TO_DEVICE);
1066         if (dma_mapping_error(ring_to_dev(ring), dma)) {
1067                 dev_warn(ring_to_dev(ring), "failed to map pages for tx spare\n");
1068                 goto dma_mapping_error;
1069         }
1070
1071         tx_spare->dma = dma;
1072         tx_spare->buf = page_address(page);
1073         tx_spare->len = PAGE_SIZE << order;
1074         ring->tx_spare = tx_spare;
1075         return;
1076
1077 dma_mapping_error:
1078         put_page(page);
1079 alloc_pages_error:
1080         devm_kfree(ring_to_dev(ring), tx_spare);
1081 devm_kzalloc_error:
1082         ring->tqp->handle->kinfo.tx_spare_buf_size = 0;
1083 }
1084
1085 /* Use hns3_tx_spare_space() to make sure there is enough buffer
1086  * before calling below function to allocate tx buffer.
1087  */
1088 static void *hns3_tx_spare_alloc(struct hns3_enet_ring *ring,
1089                                  unsigned int size, dma_addr_t *dma,
1090                                  u32 *cb_len)
1091 {
1092         struct hns3_tx_spare *tx_spare = ring->tx_spare;
1093         u32 ntu = tx_spare->next_to_use;
1094
1095         size = ALIGN(size, dma_get_cache_alignment());
1096         *cb_len = size;
1097
1098         /* Tx spare buffer wraps back here because the end of
1099          * freed tx buffer is not enough.
1100          */
1101         if (ntu + size > tx_spare->len) {
1102                 *cb_len += (tx_spare->len - ntu);
1103                 ntu = 0;
1104         }
1105
1106         tx_spare->next_to_use = ntu + size;
1107         if (tx_spare->next_to_use == tx_spare->len)
1108                 tx_spare->next_to_use = 0;
1109
1110         *dma = tx_spare->dma + ntu;
1111
1112         return tx_spare->buf + ntu;
1113 }
1114
1115 static void hns3_tx_spare_rollback(struct hns3_enet_ring *ring, u32 len)
1116 {
1117         struct hns3_tx_spare *tx_spare = ring->tx_spare;
1118
1119         if (len > tx_spare->next_to_use) {
1120                 len -= tx_spare->next_to_use;
1121                 tx_spare->next_to_use = tx_spare->len - len;
1122         } else {
1123                 tx_spare->next_to_use -= len;
1124         }
1125 }
1126
1127 static void hns3_tx_spare_reclaim_cb(struct hns3_enet_ring *ring,
1128                                      struct hns3_desc_cb *cb)
1129 {
1130         struct hns3_tx_spare *tx_spare = ring->tx_spare;
1131         u32 ntc = tx_spare->next_to_clean;
1132         u32 len = cb->length;
1133
1134         tx_spare->next_to_clean += len;
1135
1136         if (tx_spare->next_to_clean >= tx_spare->len) {
1137                 tx_spare->next_to_clean -= tx_spare->len;
1138
1139                 if (tx_spare->next_to_clean) {
1140                         ntc = 0;
1141                         len = tx_spare->next_to_clean;
1142                 }
1143         }
1144
1145         /* This tx spare buffer is only really reclaimed after calling
1146          * hns3_tx_spare_update(), so it is still safe to use the info in
1147          * the tx buffer to do the dma sync or sg unmapping after
1148          * tx_spare->next_to_clean is moved forword.
1149          */
1150         if (cb->type & (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL)) {
1151                 dma_addr_t dma = tx_spare->dma + ntc;
1152
1153                 dma_sync_single_for_cpu(ring_to_dev(ring), dma, len,
1154                                         DMA_TO_DEVICE);
1155         } else {
1156                 struct sg_table *sgt = tx_spare->buf + ntc;
1157
1158                 dma_unmap_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
1159                              DMA_TO_DEVICE);
1160         }
1161 }
1162
1163 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen_fdop_ol4cs,
1164                         u16 *mss, u32 *type_cs_vlan_tso, u32 *send_bytes)
1165 {
1166         u32 l4_offset, hdr_len;
1167         union l3_hdr_info l3;
1168         union l4_hdr_info l4;
1169         u32 l4_paylen;
1170         int ret;
1171
1172         if (!skb_is_gso(skb))
1173                 return 0;
1174
1175         ret = skb_cow_head(skb, 0);
1176         if (unlikely(ret < 0))
1177                 return ret;
1178
1179         l3.hdr = skb_network_header(skb);
1180         l4.hdr = skb_transport_header(skb);
1181
1182         /* Software should clear the IPv4's checksum field when tso is
1183          * needed.
1184          */
1185         if (l3.v4->version == 4)
1186                 l3.v4->check = 0;
1187
1188         /* tunnel packet */
1189         if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
1190                                          SKB_GSO_GRE_CSUM |
1191                                          SKB_GSO_UDP_TUNNEL |
1192                                          SKB_GSO_UDP_TUNNEL_CSUM)) {
1193                 /* reset l3&l4 pointers from outer to inner headers */
1194                 l3.hdr = skb_inner_network_header(skb);
1195                 l4.hdr = skb_inner_transport_header(skb);
1196
1197                 /* Software should clear the IPv4's checksum field when
1198                  * tso is needed.
1199                  */
1200                 if (l3.v4->version == 4)
1201                         l3.v4->check = 0;
1202         }
1203
1204         /* normal or tunnel packet */
1205         l4_offset = l4.hdr - skb->data;
1206
1207         /* remove payload length from inner pseudo checksum when tso */
1208         l4_paylen = skb->len - l4_offset;
1209
1210         if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
1211                 hdr_len = sizeof(*l4.udp) + l4_offset;
1212                 csum_replace_by_diff(&l4.udp->check,
1213                                      (__force __wsum)htonl(l4_paylen));
1214         } else {
1215                 hdr_len = (l4.tcp->doff << 2) + l4_offset;
1216                 csum_replace_by_diff(&l4.tcp->check,
1217                                      (__force __wsum)htonl(l4_paylen));
1218         }
1219
1220         *send_bytes = (skb_shinfo(skb)->gso_segs - 1) * hdr_len + skb->len;
1221
1222         /* find the txbd field values */
1223         *paylen_fdop_ol4cs = skb->len - hdr_len;
1224         hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
1225
1226         /* offload outer UDP header checksum */
1227         if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)
1228                 hns3_set_field(*paylen_fdop_ol4cs, HNS3_TXD_OL4CS_B, 1);
1229
1230         /* get MSS for TSO */
1231         *mss = skb_shinfo(skb)->gso_size;
1232
1233         trace_hns3_tso(skb);
1234
1235         return 0;
1236 }
1237
1238 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
1239                                 u8 *il4_proto)
1240 {
1241         union l3_hdr_info l3;
1242         unsigned char *l4_hdr;
1243         unsigned char *exthdr;
1244         u8 l4_proto_tmp;
1245         __be16 frag_off;
1246
1247         /* find outer header point */
1248         l3.hdr = skb_network_header(skb);
1249         l4_hdr = skb_transport_header(skb);
1250
1251         if (skb->protocol == htons(ETH_P_IPV6)) {
1252                 exthdr = l3.hdr + sizeof(*l3.v6);
1253                 l4_proto_tmp = l3.v6->nexthdr;
1254                 if (l4_hdr != exthdr)
1255                         ipv6_skip_exthdr(skb, exthdr - skb->data,
1256                                          &l4_proto_tmp, &frag_off);
1257         } else if (skb->protocol == htons(ETH_P_IP)) {
1258                 l4_proto_tmp = l3.v4->protocol;
1259         } else {
1260                 return -EINVAL;
1261         }
1262
1263         *ol4_proto = l4_proto_tmp;
1264
1265         /* tunnel packet */
1266         if (!skb->encapsulation) {
1267                 *il4_proto = 0;
1268                 return 0;
1269         }
1270
1271         /* find inner header point */
1272         l3.hdr = skb_inner_network_header(skb);
1273         l4_hdr = skb_inner_transport_header(skb);
1274
1275         if (l3.v6->version == 6) {
1276                 exthdr = l3.hdr + sizeof(*l3.v6);
1277                 l4_proto_tmp = l3.v6->nexthdr;
1278                 if (l4_hdr != exthdr)
1279                         ipv6_skip_exthdr(skb, exthdr - skb->data,
1280                                          &l4_proto_tmp, &frag_off);
1281         } else if (l3.v4->version == 4) {
1282                 l4_proto_tmp = l3.v4->protocol;
1283         }
1284
1285         *il4_proto = l4_proto_tmp;
1286
1287         return 0;
1288 }
1289
1290 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
1291  * and it is udp packet, which has a dest port as the IANA assigned.
1292  * the hardware is expected to do the checksum offload, but the
1293  * hardware will not do the checksum offload when udp dest port is
1294  * 4789, 4790 or 6081.
1295  */
1296 static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
1297 {
1298         struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1299         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
1300         union l4_hdr_info l4;
1301
1302         /* device version above V3(include V3), the hardware can
1303          * do this checksum offload.
1304          */
1305         if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
1306                 return false;
1307
1308         l4.hdr = skb_transport_header(skb);
1309
1310         if (!(!skb->encapsulation &&
1311               (l4.udp->dest == htons(IANA_VXLAN_UDP_PORT) ||
1312               l4.udp->dest == htons(GENEVE_UDP_PORT) ||
1313               l4.udp->dest == htons(IANA_VXLAN_GPE_UDP_PORT))))
1314                 return false;
1315
1316         return true;
1317 }
1318
1319 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
1320                                   u32 *ol_type_vlan_len_msec)
1321 {
1322         u32 l2_len, l3_len, l4_len;
1323         unsigned char *il2_hdr;
1324         union l3_hdr_info l3;
1325         union l4_hdr_info l4;
1326
1327         l3.hdr = skb_network_header(skb);
1328         l4.hdr = skb_transport_header(skb);
1329
1330         /* compute OL2 header size, defined in 2 Bytes */
1331         l2_len = l3.hdr - skb->data;
1332         hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1);
1333
1334         /* compute OL3 header size, defined in 4 Bytes */
1335         l3_len = l4.hdr - l3.hdr;
1336         hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2);
1337
1338         il2_hdr = skb_inner_mac_header(skb);
1339         /* compute OL4 header size, defined in 4 Bytes */
1340         l4_len = il2_hdr - l4.hdr;
1341         hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2);
1342
1343         /* define outer network header type */
1344         if (skb->protocol == htons(ETH_P_IP)) {
1345                 if (skb_is_gso(skb))
1346                         hns3_set_field(*ol_type_vlan_len_msec,
1347                                        HNS3_TXD_OL3T_S,
1348                                        HNS3_OL3T_IPV4_CSUM);
1349                 else
1350                         hns3_set_field(*ol_type_vlan_len_msec,
1351                                        HNS3_TXD_OL3T_S,
1352                                        HNS3_OL3T_IPV4_NO_CSUM);
1353         } else if (skb->protocol == htons(ETH_P_IPV6)) {
1354                 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S,
1355                                HNS3_OL3T_IPV6);
1356         }
1357
1358         if (ol4_proto == IPPROTO_UDP)
1359                 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
1360                                HNS3_TUN_MAC_IN_UDP);
1361         else if (ol4_proto == IPPROTO_GRE)
1362                 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
1363                                HNS3_TUN_NVGRE);
1364 }
1365
1366 static void hns3_set_l3_type(struct sk_buff *skb, union l3_hdr_info l3,
1367                              u32 *type_cs_vlan_tso)
1368 {
1369         if (l3.v4->version == 4) {
1370                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
1371                                HNS3_L3T_IPV4);
1372
1373                 /* the stack computes the IP header already, the only time we
1374                  * need the hardware to recompute it is in the case of TSO.
1375                  */
1376                 if (skb_is_gso(skb))
1377                         hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
1378         } else if (l3.v6->version == 6) {
1379                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
1380                                HNS3_L3T_IPV6);
1381         }
1382 }
1383
1384 static int hns3_set_l4_csum_length(struct sk_buff *skb, union l4_hdr_info l4,
1385                                    u32 l4_proto, u32 *type_cs_vlan_tso)
1386 {
1387         /* compute inner(/normal) L4 header size, defined in 4 Bytes */
1388         switch (l4_proto) {
1389         case IPPROTO_TCP:
1390                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1391                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1392                                HNS3_L4T_TCP);
1393                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1394                                l4.tcp->doff);
1395                 break;
1396         case IPPROTO_UDP:
1397                 if (hns3_tunnel_csum_bug(skb)) {
1398                         int ret = skb_put_padto(skb, HNS3_MIN_TUN_PKT_LEN);
1399
1400                         return ret ? ret : skb_checksum_help(skb);
1401                 }
1402
1403                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1404                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1405                                HNS3_L4T_UDP);
1406                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1407                                (sizeof(struct udphdr) >> 2));
1408                 break;
1409         case IPPROTO_SCTP:
1410                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1411                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1412                                HNS3_L4T_SCTP);
1413                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1414                                (sizeof(struct sctphdr) >> 2));
1415                 break;
1416         default:
1417                 /* drop the skb tunnel packet if hardware don't support,
1418                  * because hardware can't calculate csum when TSO.
1419                  */
1420                 if (skb_is_gso(skb))
1421                         return -EDOM;
1422
1423                 /* the stack computes the IP header already,
1424                  * driver calculate l4 checksum when not TSO.
1425                  */
1426                 return skb_checksum_help(skb);
1427         }
1428
1429         return 0;
1430 }
1431
1432 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
1433                            u8 il4_proto, u32 *type_cs_vlan_tso,
1434                            u32 *ol_type_vlan_len_msec)
1435 {
1436         unsigned char *l2_hdr = skb->data;
1437         u32 l4_proto = ol4_proto;
1438         union l4_hdr_info l4;
1439         union l3_hdr_info l3;
1440         u32 l2_len, l3_len;
1441
1442         l4.hdr = skb_transport_header(skb);
1443         l3.hdr = skb_network_header(skb);
1444
1445         /* handle encapsulation skb */
1446         if (skb->encapsulation) {
1447                 /* If this is a not UDP/GRE encapsulation skb */
1448                 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) {
1449                         /* drop the skb tunnel packet if hardware don't support,
1450                          * because hardware can't calculate csum when TSO.
1451                          */
1452                         if (skb_is_gso(skb))
1453                                 return -EDOM;
1454
1455                         /* the stack computes the IP header already,
1456                          * driver calculate l4 checksum when not TSO.
1457                          */
1458                         return skb_checksum_help(skb);
1459                 }
1460
1461                 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec);
1462
1463                 /* switch to inner header */
1464                 l2_hdr = skb_inner_mac_header(skb);
1465                 l3.hdr = skb_inner_network_header(skb);
1466                 l4.hdr = skb_inner_transport_header(skb);
1467                 l4_proto = il4_proto;
1468         }
1469
1470         hns3_set_l3_type(skb, l3, type_cs_vlan_tso);
1471
1472         /* compute inner(/normal) L2 header size, defined in 2 Bytes */
1473         l2_len = l3.hdr - l2_hdr;
1474         hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1);
1475
1476         /* compute inner(/normal) L3 header size, defined in 4 Bytes */
1477         l3_len = l4.hdr - l3.hdr;
1478         hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2);
1479
1480         return hns3_set_l4_csum_length(skb, l4, l4_proto, type_cs_vlan_tso);
1481 }
1482
1483 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring,
1484                              struct sk_buff *skb)
1485 {
1486         struct hnae3_handle *handle = tx_ring->tqp->handle;
1487         struct hnae3_ae_dev *ae_dev;
1488         struct vlan_ethhdr *vhdr;
1489         int rc;
1490
1491         if (!(skb->protocol == htons(ETH_P_8021Q) ||
1492               skb_vlan_tag_present(skb)))
1493                 return 0;
1494
1495         /* For HW limitation on HNAE3_DEVICE_VERSION_V2, if port based insert
1496          * VLAN enabled, only one VLAN header is allowed in skb, otherwise it
1497          * will cause RAS error.
1498          */
1499         ae_dev = pci_get_drvdata(handle->pdev);
1500         if (unlikely(skb_vlan_tagged_multi(skb) &&
1501                      ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 &&
1502                      handle->port_base_vlan_state ==
1503                      HNAE3_PORT_BASE_VLAN_ENABLE))
1504                 return -EINVAL;
1505
1506         if (skb->protocol == htons(ETH_P_8021Q) &&
1507             !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1508                 /* When HW VLAN acceleration is turned off, and the stack
1509                  * sets the protocol to 802.1q, the driver just need to
1510                  * set the protocol to the encapsulated ethertype.
1511                  */
1512                 skb->protocol = vlan_get_protocol(skb);
1513                 return 0;
1514         }
1515
1516         if (skb_vlan_tag_present(skb)) {
1517                 /* Based on hw strategy, use out_vtag in two layer tag case,
1518                  * and use inner_vtag in one tag case.
1519                  */
1520                 if (skb->protocol == htons(ETH_P_8021Q) &&
1521                     handle->port_base_vlan_state ==
1522                     HNAE3_PORT_BASE_VLAN_DISABLE)
1523                         rc = HNS3_OUTER_VLAN_TAG;
1524                 else
1525                         rc = HNS3_INNER_VLAN_TAG;
1526
1527                 skb->protocol = vlan_get_protocol(skb);
1528                 return rc;
1529         }
1530
1531         rc = skb_cow_head(skb, 0);
1532         if (unlikely(rc < 0))
1533                 return rc;
1534
1535         vhdr = skb_vlan_eth_hdr(skb);
1536         vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT)
1537                                          & VLAN_PRIO_MASK);
1538
1539         skb->protocol = vlan_get_protocol(skb);
1540         return 0;
1541 }
1542
1543 /* check if the hardware is capable of checksum offloading */
1544 static bool hns3_check_hw_tx_csum(struct sk_buff *skb)
1545 {
1546         struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1547
1548         /* Kindly note, due to backward compatibility of the TX descriptor,
1549          * HW checksum of the non-IP packets and GSO packets is handled at
1550          * different place in the following code
1551          */
1552         if (skb_csum_is_sctp(skb) || skb_is_gso(skb) ||
1553             !test_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state))
1554                 return false;
1555
1556         return true;
1557 }
1558
1559 struct hns3_desc_param {
1560         u32 paylen_ol4cs;
1561         u32 ol_type_vlan_len_msec;
1562         u32 type_cs_vlan_tso;
1563         u16 mss_hw_csum;
1564         u16 inner_vtag;
1565         u16 out_vtag;
1566 };
1567
1568 static void hns3_init_desc_data(struct sk_buff *skb, struct hns3_desc_param *pa)
1569 {
1570         pa->paylen_ol4cs = skb->len;
1571         pa->ol_type_vlan_len_msec = 0;
1572         pa->type_cs_vlan_tso = 0;
1573         pa->mss_hw_csum = 0;
1574         pa->inner_vtag = 0;
1575         pa->out_vtag = 0;
1576 }
1577
1578 static int hns3_handle_vlan_info(struct hns3_enet_ring *ring,
1579                                  struct sk_buff *skb,
1580                                  struct hns3_desc_param *param)
1581 {
1582         int ret;
1583
1584         ret = hns3_handle_vtags(ring, skb);
1585         if (unlikely(ret < 0)) {
1586                 hns3_ring_stats_update(ring, tx_vlan_err);
1587                 return ret;
1588         } else if (ret == HNS3_INNER_VLAN_TAG) {
1589                 param->inner_vtag = skb_vlan_tag_get(skb);
1590                 param->inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1591                                 VLAN_PRIO_MASK;
1592                 hns3_set_field(param->type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1);
1593         } else if (ret == HNS3_OUTER_VLAN_TAG) {
1594                 param->out_vtag = skb_vlan_tag_get(skb);
1595                 param->out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1596                                 VLAN_PRIO_MASK;
1597                 hns3_set_field(param->ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B,
1598                                1);
1599         }
1600         return 0;
1601 }
1602
1603 static int hns3_handle_csum_partial(struct hns3_enet_ring *ring,
1604                                     struct sk_buff *skb,
1605                                     struct hns3_desc_cb *desc_cb,
1606                                     struct hns3_desc_param *param)
1607 {
1608         u8 ol4_proto, il4_proto;
1609         int ret;
1610
1611         if (hns3_check_hw_tx_csum(skb)) {
1612                 /* set checksum start and offset, defined in 2 Bytes */
1613                 hns3_set_field(param->type_cs_vlan_tso, HNS3_TXD_CSUM_START_S,
1614                                skb_checksum_start_offset(skb) >> 1);
1615                 hns3_set_field(param->ol_type_vlan_len_msec,
1616                                HNS3_TXD_CSUM_OFFSET_S,
1617                                skb->csum_offset >> 1);
1618                 param->mss_hw_csum |= BIT(HNS3_TXD_HW_CS_B);
1619                 return 0;
1620         }
1621
1622         skb_reset_mac_len(skb);
1623
1624         ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
1625         if (unlikely(ret < 0)) {
1626                 hns3_ring_stats_update(ring, tx_l4_proto_err);
1627                 return ret;
1628         }
1629
1630         ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
1631                               &param->type_cs_vlan_tso,
1632                               &param->ol_type_vlan_len_msec);
1633         if (unlikely(ret < 0)) {
1634                 hns3_ring_stats_update(ring, tx_l2l3l4_err);
1635                 return ret;
1636         }
1637
1638         ret = hns3_set_tso(skb, &param->paylen_ol4cs, &param->mss_hw_csum,
1639                            &param->type_cs_vlan_tso, &desc_cb->send_bytes);
1640         if (unlikely(ret < 0)) {
1641                 hns3_ring_stats_update(ring, tx_tso_err);
1642                 return ret;
1643         }
1644         return 0;
1645 }
1646
1647 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
1648                               struct sk_buff *skb, struct hns3_desc *desc,
1649                               struct hns3_desc_cb *desc_cb)
1650 {
1651         struct hns3_desc_param param;
1652         int ret;
1653
1654         hns3_init_desc_data(skb, &param);
1655         ret = hns3_handle_vlan_info(ring, skb, &param);
1656         if (unlikely(ret < 0))
1657                 return ret;
1658
1659         desc_cb->send_bytes = skb->len;
1660
1661         if (skb->ip_summed == CHECKSUM_PARTIAL) {
1662                 ret = hns3_handle_csum_partial(ring, skb, desc_cb, &param);
1663                 if (ret)
1664                         return ret;
1665         }
1666
1667         /* Set txbd */
1668         desc->tx.ol_type_vlan_len_msec =
1669                 cpu_to_le32(param.ol_type_vlan_len_msec);
1670         desc->tx.type_cs_vlan_tso_len = cpu_to_le32(param.type_cs_vlan_tso);
1671         desc->tx.paylen_ol4cs = cpu_to_le32(param.paylen_ol4cs);
1672         desc->tx.mss_hw_csum = cpu_to_le16(param.mss_hw_csum);
1673         desc->tx.vlan_tag = cpu_to_le16(param.inner_vtag);
1674         desc->tx.outer_vlan_tag = cpu_to_le16(param.out_vtag);
1675
1676         return 0;
1677 }
1678
1679 static int hns3_fill_desc(struct hns3_enet_ring *ring, dma_addr_t dma,
1680                           unsigned int size)
1681 {
1682 #define HNS3_LIKELY_BD_NUM      1
1683
1684         struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1685         unsigned int frag_buf_num;
1686         int k, sizeoflast;
1687
1688         if (likely(size <= HNS3_MAX_BD_SIZE)) {
1689                 desc->addr = cpu_to_le64(dma);
1690                 desc->tx.send_size = cpu_to_le16(size);
1691                 desc->tx.bdtp_fe_sc_vld_ra_ri =
1692                         cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1693
1694                 trace_hns3_tx_desc(ring, ring->next_to_use);
1695                 ring_ptr_move_fw(ring, next_to_use);
1696                 return HNS3_LIKELY_BD_NUM;
1697         }
1698
1699         frag_buf_num = hns3_tx_bd_count(size);
1700         sizeoflast = size % HNS3_MAX_BD_SIZE;
1701         sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1702
1703         /* When frag size is bigger than hardware limit, split this frag */
1704         for (k = 0; k < frag_buf_num; k++) {
1705                 /* now, fill the descriptor */
1706                 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
1707                 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
1708                                      (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1709                 desc->tx.bdtp_fe_sc_vld_ra_ri =
1710                                 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1711
1712                 trace_hns3_tx_desc(ring, ring->next_to_use);
1713                 /* move ring pointer to next */
1714                 ring_ptr_move_fw(ring, next_to_use);
1715
1716                 desc = &ring->desc[ring->next_to_use];
1717         }
1718
1719         return frag_buf_num;
1720 }
1721
1722 static int hns3_map_and_fill_desc(struct hns3_enet_ring *ring, void *priv,
1723                                   unsigned int type)
1724 {
1725         struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1726         struct device *dev = ring_to_dev(ring);
1727         unsigned int size;
1728         dma_addr_t dma;
1729
1730         if (type & (DESC_TYPE_FRAGLIST_SKB | DESC_TYPE_SKB)) {
1731                 struct sk_buff *skb = (struct sk_buff *)priv;
1732
1733                 size = skb_headlen(skb);
1734                 if (!size)
1735                         return 0;
1736
1737                 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1738         } else if (type & DESC_TYPE_BOUNCE_HEAD) {
1739                 /* Head data has been filled in hns3_handle_tx_bounce(),
1740                  * just return 0 here.
1741                  */
1742                 return 0;
1743         } else {
1744                 skb_frag_t *frag = (skb_frag_t *)priv;
1745
1746                 size = skb_frag_size(frag);
1747                 if (!size)
1748                         return 0;
1749
1750                 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1751         }
1752
1753         if (unlikely(dma_mapping_error(dev, dma))) {
1754                 hns3_ring_stats_update(ring, sw_err_cnt);
1755                 return -ENOMEM;
1756         }
1757
1758         desc_cb->priv = priv;
1759         desc_cb->length = size;
1760         desc_cb->dma = dma;
1761         desc_cb->type = type;
1762
1763         return hns3_fill_desc(ring, dma, size);
1764 }
1765
1766 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1767                                     unsigned int bd_num)
1768 {
1769         unsigned int size;
1770         int i;
1771
1772         size = skb_headlen(skb);
1773         while (size > HNS3_MAX_BD_SIZE) {
1774                 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1775                 size -= HNS3_MAX_BD_SIZE;
1776
1777                 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1778                         return bd_num;
1779         }
1780
1781         if (size) {
1782                 bd_size[bd_num++] = size;
1783                 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1784                         return bd_num;
1785         }
1786
1787         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1788                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1789                 size = skb_frag_size(frag);
1790                 if (!size)
1791                         continue;
1792
1793                 while (size > HNS3_MAX_BD_SIZE) {
1794                         bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1795                         size -= HNS3_MAX_BD_SIZE;
1796
1797                         if (bd_num > HNS3_MAX_TSO_BD_NUM)
1798                                 return bd_num;
1799                 }
1800
1801                 bd_size[bd_num++] = size;
1802                 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1803                         return bd_num;
1804         }
1805
1806         return bd_num;
1807 }
1808
1809 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1810                                    u8 max_non_tso_bd_num, unsigned int bd_num,
1811                                    unsigned int recursion_level)
1812 {
1813 #define HNS3_MAX_RECURSION_LEVEL        24
1814
1815         struct sk_buff *frag_skb;
1816
1817         /* If the total len is within the max bd limit */
1818         if (likely(skb->len <= HNS3_MAX_BD_SIZE && !recursion_level &&
1819                    !skb_has_frag_list(skb) &&
1820                    skb_shinfo(skb)->nr_frags < max_non_tso_bd_num))
1821                 return skb_shinfo(skb)->nr_frags + 1U;
1822
1823         if (unlikely(recursion_level >= HNS3_MAX_RECURSION_LEVEL))
1824                 return UINT_MAX;
1825
1826         bd_num = hns3_skb_bd_num(skb, bd_size, bd_num);
1827         if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM)
1828                 return bd_num;
1829
1830         skb_walk_frags(skb, frag_skb) {
1831                 bd_num = hns3_tx_bd_num(frag_skb, bd_size, max_non_tso_bd_num,
1832                                         bd_num, recursion_level + 1);
1833                 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1834                         return bd_num;
1835         }
1836
1837         return bd_num;
1838 }
1839
1840 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb)
1841 {
1842         if (!skb->encapsulation)
1843                 return skb_tcp_all_headers(skb);
1844
1845         return skb_inner_tcp_all_headers(skb);
1846 }
1847
1848 /* HW need every continuous max_non_tso_bd_num buffer data to be larger
1849  * than MSS, we simplify it by ensuring skb_headlen + the first continuous
1850  * max_non_tso_bd_num - 1 frags to be larger than gso header len + mss,
1851  * and the remaining continuous max_non_tso_bd_num - 1 frags to be larger
1852  * than MSS except the last max_non_tso_bd_num - 1 frags.
1853  */
1854 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size,
1855                                      unsigned int bd_num, u8 max_non_tso_bd_num)
1856 {
1857         unsigned int tot_len = 0;
1858         int i;
1859
1860         for (i = 0; i < max_non_tso_bd_num - 1U; i++)
1861                 tot_len += bd_size[i];
1862
1863         /* ensure the first max_non_tso_bd_num frags is greater than
1864          * mss + header
1865          */
1866         if (tot_len + bd_size[max_non_tso_bd_num - 1U] <
1867             skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb))
1868                 return true;
1869
1870         /* ensure every continuous max_non_tso_bd_num - 1 buffer is greater
1871          * than mss except the last one.
1872          */
1873         for (i = 0; i < bd_num - max_non_tso_bd_num; i++) {
1874                 tot_len -= bd_size[i];
1875                 tot_len += bd_size[i + max_non_tso_bd_num - 1U];
1876
1877                 if (tot_len < skb_shinfo(skb)->gso_size)
1878                         return true;
1879         }
1880
1881         return false;
1882 }
1883
1884 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size)
1885 {
1886         int i;
1887
1888         for (i = 0; i < MAX_SKB_FRAGS; i++)
1889                 size[i] = skb_frag_size(&shinfo->frags[i]);
1890 }
1891
1892 static int hns3_skb_linearize(struct hns3_enet_ring *ring,
1893                               struct sk_buff *skb,
1894                               unsigned int bd_num)
1895 {
1896         /* 'bd_num == UINT_MAX' means the skb' fraglist has a
1897          * recursion level of over HNS3_MAX_RECURSION_LEVEL.
1898          */
1899         if (bd_num == UINT_MAX) {
1900                 hns3_ring_stats_update(ring, over_max_recursion);
1901                 return -ENOMEM;
1902         }
1903
1904         /* The skb->len has exceeded the hw limitation, linearization
1905          * will not help.
1906          */
1907         if (skb->len > HNS3_MAX_TSO_SIZE ||
1908             (!skb_is_gso(skb) && skb->len > HNS3_MAX_NON_TSO_SIZE)) {
1909                 hns3_ring_stats_update(ring, hw_limitation);
1910                 return -ENOMEM;
1911         }
1912
1913         if (__skb_linearize(skb)) {
1914                 hns3_ring_stats_update(ring, sw_err_cnt);
1915                 return -ENOMEM;
1916         }
1917
1918         return 0;
1919 }
1920
1921 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring,
1922                                   struct net_device *netdev,
1923                                   struct sk_buff *skb)
1924 {
1925         struct hns3_nic_priv *priv = netdev_priv(netdev);
1926         u8 max_non_tso_bd_num = priv->max_non_tso_bd_num;
1927         unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U];
1928         unsigned int bd_num;
1929
1930         bd_num = hns3_tx_bd_num(skb, bd_size, max_non_tso_bd_num, 0, 0);
1931         if (unlikely(bd_num > max_non_tso_bd_num)) {
1932                 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) &&
1933                     !hns3_skb_need_linearized(skb, bd_size, bd_num,
1934                                               max_non_tso_bd_num)) {
1935                         trace_hns3_over_max_bd(skb);
1936                         goto out;
1937                 }
1938
1939                 if (hns3_skb_linearize(ring, skb, bd_num))
1940                         return -ENOMEM;
1941
1942                 bd_num = hns3_tx_bd_count(skb->len);
1943
1944                 hns3_ring_stats_update(ring, tx_copy);
1945         }
1946
1947 out:
1948         if (likely(ring_space(ring) >= bd_num))
1949                 return bd_num;
1950
1951         netif_stop_subqueue(netdev, ring->queue_index);
1952         smp_mb(); /* Memory barrier before checking ring_space */
1953
1954         /* Start queue in case hns3_clean_tx_ring has just made room
1955          * available and has not seen the queue stopped state performed
1956          * by netif_stop_subqueue above.
1957          */
1958         if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) &&
1959             !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
1960                 netif_start_subqueue(netdev, ring->queue_index);
1961                 return bd_num;
1962         }
1963
1964         hns3_ring_stats_update(ring, tx_busy);
1965
1966         return -EBUSY;
1967 }
1968
1969 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
1970 {
1971         struct device *dev = ring_to_dev(ring);
1972         unsigned int i;
1973
1974         for (i = 0; i < ring->desc_num; i++) {
1975                 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1976                 struct hns3_desc_cb *desc_cb;
1977
1978                 memset(desc, 0, sizeof(*desc));
1979
1980                 /* check if this is where we started */
1981                 if (ring->next_to_use == next_to_use_orig)
1982                         break;
1983
1984                 /* rollback one */
1985                 ring_ptr_move_bw(ring, next_to_use);
1986
1987                 desc_cb = &ring->desc_cb[ring->next_to_use];
1988
1989                 if (!desc_cb->dma)
1990                         continue;
1991
1992                 /* unmap the descriptor dma address */
1993                 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
1994                         dma_unmap_single(dev, desc_cb->dma, desc_cb->length,
1995                                          DMA_TO_DEVICE);
1996                 else if (desc_cb->type &
1997                          (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL))
1998                         hns3_tx_spare_rollback(ring, desc_cb->length);
1999                 else if (desc_cb->length)
2000                         dma_unmap_page(dev, desc_cb->dma, desc_cb->length,
2001                                        DMA_TO_DEVICE);
2002
2003                 desc_cb->length = 0;
2004                 desc_cb->dma = 0;
2005                 desc_cb->type = DESC_TYPE_UNKNOWN;
2006         }
2007 }
2008
2009 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring,
2010                                  struct sk_buff *skb, unsigned int type)
2011 {
2012         struct sk_buff *frag_skb;
2013         int i, ret, bd_num = 0;
2014
2015         ret = hns3_map_and_fill_desc(ring, skb, type);
2016         if (unlikely(ret < 0))
2017                 return ret;
2018
2019         bd_num += ret;
2020
2021         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2022                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2023
2024                 ret = hns3_map_and_fill_desc(ring, frag, DESC_TYPE_PAGE);
2025                 if (unlikely(ret < 0))
2026                         return ret;
2027
2028                 bd_num += ret;
2029         }
2030
2031         skb_walk_frags(skb, frag_skb) {
2032                 ret = hns3_fill_skb_to_desc(ring, frag_skb,
2033                                             DESC_TYPE_FRAGLIST_SKB);
2034                 if (unlikely(ret < 0))
2035                         return ret;
2036
2037                 bd_num += ret;
2038         }
2039
2040         return bd_num;
2041 }
2042
2043 static void hns3_tx_push_bd(struct hns3_enet_ring *ring, int num)
2044 {
2045 #define HNS3_BYTES_PER_64BIT            8
2046
2047         struct hns3_desc desc[HNS3_MAX_PUSH_BD_NUM] = {};
2048         int offset = 0;
2049
2050         /* make sure everything is visible to device before
2051          * excuting tx push or updating doorbell
2052          */
2053         dma_wmb();
2054
2055         do {
2056                 int idx = (ring->next_to_use - num + ring->desc_num) %
2057                           ring->desc_num;
2058
2059                 u64_stats_update_begin(&ring->syncp);
2060                 ring->stats.tx_push++;
2061                 u64_stats_update_end(&ring->syncp);
2062                 memcpy(&desc[offset], &ring->desc[idx],
2063                        sizeof(struct hns3_desc));
2064                 offset++;
2065         } while (--num);
2066
2067         __iowrite64_copy(ring->tqp->mem_base, desc,
2068                          (sizeof(struct hns3_desc) * HNS3_MAX_PUSH_BD_NUM) /
2069                          HNS3_BYTES_PER_64BIT);
2070
2071         io_stop_wc();
2072 }
2073
2074 static void hns3_tx_mem_doorbell(struct hns3_enet_ring *ring)
2075 {
2076 #define HNS3_MEM_DOORBELL_OFFSET        64
2077
2078         __le64 bd_num = cpu_to_le64((u64)ring->pending_buf);
2079
2080         /* make sure everything is visible to device before
2081          * excuting tx push or updating doorbell
2082          */
2083         dma_wmb();
2084
2085         __iowrite64_copy(ring->tqp->mem_base + HNS3_MEM_DOORBELL_OFFSET,
2086                          &bd_num, 1);
2087         u64_stats_update_begin(&ring->syncp);
2088         ring->stats.tx_mem_doorbell += ring->pending_buf;
2089         u64_stats_update_end(&ring->syncp);
2090
2091         io_stop_wc();
2092 }
2093
2094 static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num,
2095                              bool doorbell)
2096 {
2097         struct net_device *netdev = ring_to_netdev(ring);
2098         struct hns3_nic_priv *priv = netdev_priv(netdev);
2099
2100         /* when tx push is enabled, the packet whose number of BD below
2101          * HNS3_MAX_PUSH_BD_NUM can be pushed directly.
2102          */
2103         if (test_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state) && num &&
2104             !ring->pending_buf && num <= HNS3_MAX_PUSH_BD_NUM && doorbell) {
2105                 hns3_tx_push_bd(ring, num);
2106                 WRITE_ONCE(ring->last_to_use, ring->next_to_use);
2107                 return;
2108         }
2109
2110         ring->pending_buf += num;
2111
2112         if (!doorbell) {
2113                 hns3_ring_stats_update(ring, tx_more);
2114                 return;
2115         }
2116
2117         if (ring->tqp->mem_base)
2118                 hns3_tx_mem_doorbell(ring);
2119         else
2120                 writel(ring->pending_buf,
2121                        ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG);
2122
2123         ring->pending_buf = 0;
2124         WRITE_ONCE(ring->last_to_use, ring->next_to_use);
2125 }
2126
2127 static void hns3_tsyn(struct net_device *netdev, struct sk_buff *skb,
2128                       struct hns3_desc *desc)
2129 {
2130         struct hnae3_handle *h = hns3_get_handle(netdev);
2131
2132         if (!(h->ae_algo->ops->set_tx_hwts_info &&
2133               h->ae_algo->ops->set_tx_hwts_info(h, skb)))
2134                 return;
2135
2136         desc->tx.bdtp_fe_sc_vld_ra_ri |= cpu_to_le16(BIT(HNS3_TXD_TSYN_B));
2137 }
2138
2139 static int hns3_handle_tx_bounce(struct hns3_enet_ring *ring,
2140                                  struct sk_buff *skb)
2141 {
2142         struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2143         unsigned int type = DESC_TYPE_BOUNCE_HEAD;
2144         unsigned int size = skb_headlen(skb);
2145         dma_addr_t dma;
2146         int bd_num = 0;
2147         u32 cb_len;
2148         void *buf;
2149         int ret;
2150
2151         if (skb->len <= ring->tx_copybreak) {
2152                 size = skb->len;
2153                 type = DESC_TYPE_BOUNCE_ALL;
2154         }
2155
2156         /* hns3_can_use_tx_bounce() is called to ensure the below
2157          * function can always return the tx buffer.
2158          */
2159         buf = hns3_tx_spare_alloc(ring, size, &dma, &cb_len);
2160
2161         ret = skb_copy_bits(skb, 0, buf, size);
2162         if (unlikely(ret < 0)) {
2163                 hns3_tx_spare_rollback(ring, cb_len);
2164                 hns3_ring_stats_update(ring, copy_bits_err);
2165                 return ret;
2166         }
2167
2168         desc_cb->priv = skb;
2169         desc_cb->length = cb_len;
2170         desc_cb->dma = dma;
2171         desc_cb->type = type;
2172
2173         bd_num += hns3_fill_desc(ring, dma, size);
2174
2175         if (type == DESC_TYPE_BOUNCE_HEAD) {
2176                 ret = hns3_fill_skb_to_desc(ring, skb,
2177                                             DESC_TYPE_BOUNCE_HEAD);
2178                 if (unlikely(ret < 0))
2179                         return ret;
2180
2181                 bd_num += ret;
2182         }
2183
2184         dma_sync_single_for_device(ring_to_dev(ring), dma, size,
2185                                    DMA_TO_DEVICE);
2186
2187         hns3_ring_stats_update(ring, tx_bounce);
2188
2189         return bd_num;
2190 }
2191
2192 static int hns3_handle_tx_sgl(struct hns3_enet_ring *ring,
2193                               struct sk_buff *skb)
2194 {
2195         struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2196         u32 nfrag = skb_shinfo(skb)->nr_frags + 1;
2197         struct sg_table *sgt;
2198         int i, bd_num = 0;
2199         dma_addr_t dma;
2200         u32 cb_len;
2201         int nents;
2202
2203         if (skb_has_frag_list(skb))
2204                 nfrag = HNS3_MAX_TSO_BD_NUM;
2205
2206         /* hns3_can_use_tx_sgl() is called to ensure the below
2207          * function can always return the tx buffer.
2208          */
2209         sgt = hns3_tx_spare_alloc(ring, HNS3_SGL_SIZE(nfrag),
2210                                   &dma, &cb_len);
2211
2212         /* scatterlist follows by the sg table */
2213         sgt->sgl = (struct scatterlist *)(sgt + 1);
2214         sg_init_table(sgt->sgl, nfrag);
2215         nents = skb_to_sgvec(skb, sgt->sgl, 0, skb->len);
2216         if (unlikely(nents < 0)) {
2217                 hns3_tx_spare_rollback(ring, cb_len);
2218                 hns3_ring_stats_update(ring, skb2sgl_err);
2219                 return -ENOMEM;
2220         }
2221
2222         sgt->orig_nents = nents;
2223         sgt->nents = dma_map_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
2224                                 DMA_TO_DEVICE);
2225         if (unlikely(!sgt->nents)) {
2226                 hns3_tx_spare_rollback(ring, cb_len);
2227                 hns3_ring_stats_update(ring, map_sg_err);
2228                 return -ENOMEM;
2229         }
2230
2231         desc_cb->priv = skb;
2232         desc_cb->length = cb_len;
2233         desc_cb->dma = dma;
2234         desc_cb->type = DESC_TYPE_SGL_SKB;
2235
2236         for (i = 0; i < sgt->nents; i++)
2237                 bd_num += hns3_fill_desc(ring, sg_dma_address(sgt->sgl + i),
2238                                          sg_dma_len(sgt->sgl + i));
2239         hns3_ring_stats_update(ring, tx_sgl);
2240
2241         return bd_num;
2242 }
2243
2244 static int hns3_handle_desc_filling(struct hns3_enet_ring *ring,
2245                                     struct sk_buff *skb)
2246 {
2247         u32 space;
2248
2249         if (!ring->tx_spare)
2250                 goto out;
2251
2252         space = hns3_tx_spare_space(ring);
2253
2254         if (hns3_can_use_tx_sgl(ring, skb, space))
2255                 return hns3_handle_tx_sgl(ring, skb);
2256
2257         if (hns3_can_use_tx_bounce(ring, skb, space))
2258                 return hns3_handle_tx_bounce(ring, skb);
2259
2260 out:
2261         return hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB);
2262 }
2263
2264 static int hns3_handle_skb_desc(struct hns3_enet_ring *ring,
2265                                 struct sk_buff *skb,
2266                                 struct hns3_desc_cb *desc_cb,
2267                                 int next_to_use_head)
2268 {
2269         int ret;
2270
2271         ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use],
2272                                  desc_cb);
2273         if (unlikely(ret < 0))
2274                 goto fill_err;
2275
2276         /* 'ret < 0' means filling error, 'ret == 0' means skb->len is
2277          * zero, which is unlikely, and 'ret > 0' means how many tx desc
2278          * need to be notified to the hw.
2279          */
2280         ret = hns3_handle_desc_filling(ring, skb);
2281         if (likely(ret > 0))
2282                 return ret;
2283
2284 fill_err:
2285         hns3_clear_desc(ring, next_to_use_head);
2286         return ret;
2287 }
2288
2289 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
2290 {
2291         struct hns3_nic_priv *priv = netdev_priv(netdev);
2292         struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping];
2293         struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2294         struct netdev_queue *dev_queue;
2295         int pre_ntu, ret;
2296         bool doorbell;
2297
2298         /* Hardware can only handle short frames above 32 bytes */
2299         if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) {
2300                 hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
2301
2302                 hns3_ring_stats_update(ring, sw_err_cnt);
2303
2304                 return NETDEV_TX_OK;
2305         }
2306
2307         /* Prefetch the data used later */
2308         prefetch(skb->data);
2309
2310         ret = hns3_nic_maybe_stop_tx(ring, netdev, skb);
2311         if (unlikely(ret <= 0)) {
2312                 if (ret == -EBUSY) {
2313                         hns3_tx_doorbell(ring, 0, true);
2314                         return NETDEV_TX_BUSY;
2315                 }
2316
2317                 hns3_rl_err(netdev, "xmit error: %d!\n", ret);
2318                 goto out_err_tx_ok;
2319         }
2320
2321         ret = hns3_handle_skb_desc(ring, skb, desc_cb, ring->next_to_use);
2322         if (unlikely(ret <= 0))
2323                 goto out_err_tx_ok;
2324
2325         pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) :
2326                                         (ring->desc_num - 1);
2327
2328         if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
2329                 hns3_tsyn(netdev, skb, &ring->desc[pre_ntu]);
2330
2331         ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |=
2332                                 cpu_to_le16(BIT(HNS3_TXD_FE_B));
2333         trace_hns3_tx_desc(ring, pre_ntu);
2334
2335         skb_tx_timestamp(skb);
2336
2337         /* Complete translate all packets */
2338         dev_queue = netdev_get_tx_queue(netdev, ring->queue_index);
2339         doorbell = __netdev_tx_sent_queue(dev_queue, desc_cb->send_bytes,
2340                                           netdev_xmit_more());
2341         hns3_tx_doorbell(ring, ret, doorbell);
2342
2343         return NETDEV_TX_OK;
2344
2345 out_err_tx_ok:
2346         dev_kfree_skb_any(skb);
2347         hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
2348         return NETDEV_TX_OK;
2349 }
2350
2351 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
2352 {
2353         char format_mac_addr_perm[HNAE3_FORMAT_MAC_ADDR_LEN];
2354         char format_mac_addr_sa[HNAE3_FORMAT_MAC_ADDR_LEN];
2355         struct hnae3_handle *h = hns3_get_handle(netdev);
2356         struct sockaddr *mac_addr = p;
2357         int ret;
2358
2359         if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
2360                 return -EADDRNOTAVAIL;
2361
2362         if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
2363                 hnae3_format_mac_addr(format_mac_addr_sa, mac_addr->sa_data);
2364                 netdev_info(netdev, "already using mac address %s\n",
2365                             format_mac_addr_sa);
2366                 return 0;
2367         }
2368
2369         /* For VF device, if there is a perm_addr, then the user will not
2370          * be allowed to change the address.
2371          */
2372         if (!hns3_is_phys_func(h->pdev) &&
2373             !is_zero_ether_addr(netdev->perm_addr)) {
2374                 hnae3_format_mac_addr(format_mac_addr_perm, netdev->perm_addr);
2375                 hnae3_format_mac_addr(format_mac_addr_sa, mac_addr->sa_data);
2376                 netdev_err(netdev, "has permanent MAC %s, user MAC %s not allow\n",
2377                            format_mac_addr_perm, format_mac_addr_sa);
2378                 return -EPERM;
2379         }
2380
2381         ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
2382         if (ret) {
2383                 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
2384                 return ret;
2385         }
2386
2387         eth_hw_addr_set(netdev, mac_addr->sa_data);
2388
2389         return 0;
2390 }
2391
2392 static int hns3_nic_do_ioctl(struct net_device *netdev,
2393                              struct ifreq *ifr, int cmd)
2394 {
2395         struct hnae3_handle *h = hns3_get_handle(netdev);
2396
2397         if (!netif_running(netdev))
2398                 return -EINVAL;
2399
2400         if (!h->ae_algo->ops->do_ioctl)
2401                 return -EOPNOTSUPP;
2402
2403         return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
2404 }
2405
2406 static int hns3_nic_set_features(struct net_device *netdev,
2407                                  netdev_features_t features)
2408 {
2409         netdev_features_t changed = netdev->features ^ features;
2410         struct hns3_nic_priv *priv = netdev_priv(netdev);
2411         struct hnae3_handle *h = priv->ae_handle;
2412         bool enable;
2413         int ret;
2414
2415         if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
2416                 enable = !!(features & NETIF_F_GRO_HW);
2417                 ret = h->ae_algo->ops->set_gro_en(h, enable);
2418                 if (ret)
2419                         return ret;
2420         }
2421
2422         if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
2423             h->ae_algo->ops->enable_hw_strip_rxvtag) {
2424                 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
2425                 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
2426                 if (ret)
2427                         return ret;
2428         }
2429
2430         if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
2431                 enable = !!(features & NETIF_F_NTUPLE);
2432                 h->ae_algo->ops->enable_fd(h, enable);
2433         }
2434
2435         if ((netdev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) &&
2436             h->ae_algo->ops->cls_flower_active(h)) {
2437                 netdev_err(netdev,
2438                            "there are offloaded TC filters active, cannot disable HW TC offload");
2439                 return -EINVAL;
2440         }
2441
2442         if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
2443             h->ae_algo->ops->enable_vlan_filter) {
2444                 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER);
2445                 ret = h->ae_algo->ops->enable_vlan_filter(h, enable);
2446                 if (ret)
2447                         return ret;
2448         }
2449
2450         netdev->features = features;
2451         return 0;
2452 }
2453
2454 static netdev_features_t hns3_features_check(struct sk_buff *skb,
2455                                              struct net_device *dev,
2456                                              netdev_features_t features)
2457 {
2458 #define HNS3_MAX_HDR_LEN        480U
2459 #define HNS3_MAX_L4_HDR_LEN     60U
2460
2461         size_t len;
2462
2463         if (skb->ip_summed != CHECKSUM_PARTIAL)
2464                 return features;
2465
2466         if (skb->encapsulation)
2467                 len = skb_inner_transport_header(skb) - skb->data;
2468         else
2469                 len = skb_transport_header(skb) - skb->data;
2470
2471         /* Assume L4 is 60 byte as TCP is the only protocol with a
2472          * a flexible value, and it's max len is 60 bytes.
2473          */
2474         len += HNS3_MAX_L4_HDR_LEN;
2475
2476         /* Hardware only supports checksum on the skb with a max header
2477          * len of 480 bytes.
2478          */
2479         if (len > HNS3_MAX_HDR_LEN)
2480                 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2481
2482         return features;
2483 }
2484
2485 static void hns3_fetch_stats(struct rtnl_link_stats64 *stats,
2486                              struct hns3_enet_ring *ring, bool is_tx)
2487 {
2488         unsigned int start;
2489
2490         do {
2491                 start = u64_stats_fetch_begin(&ring->syncp);
2492                 if (is_tx) {
2493                         stats->tx_bytes += ring->stats.tx_bytes;
2494                         stats->tx_packets += ring->stats.tx_pkts;
2495                         stats->tx_dropped += ring->stats.sw_err_cnt;
2496                         stats->tx_dropped += ring->stats.tx_vlan_err;
2497                         stats->tx_dropped += ring->stats.tx_l4_proto_err;
2498                         stats->tx_dropped += ring->stats.tx_l2l3l4_err;
2499                         stats->tx_dropped += ring->stats.tx_tso_err;
2500                         stats->tx_dropped += ring->stats.over_max_recursion;
2501                         stats->tx_dropped += ring->stats.hw_limitation;
2502                         stats->tx_dropped += ring->stats.copy_bits_err;
2503                         stats->tx_dropped += ring->stats.skb2sgl_err;
2504                         stats->tx_dropped += ring->stats.map_sg_err;
2505                         stats->tx_errors += ring->stats.sw_err_cnt;
2506                         stats->tx_errors += ring->stats.tx_vlan_err;
2507                         stats->tx_errors += ring->stats.tx_l4_proto_err;
2508                         stats->tx_errors += ring->stats.tx_l2l3l4_err;
2509                         stats->tx_errors += ring->stats.tx_tso_err;
2510                         stats->tx_errors += ring->stats.over_max_recursion;
2511                         stats->tx_errors += ring->stats.hw_limitation;
2512                         stats->tx_errors += ring->stats.copy_bits_err;
2513                         stats->tx_errors += ring->stats.skb2sgl_err;
2514                         stats->tx_errors += ring->stats.map_sg_err;
2515                 } else {
2516                         stats->rx_bytes += ring->stats.rx_bytes;
2517                         stats->rx_packets += ring->stats.rx_pkts;
2518                         stats->rx_dropped += ring->stats.l2_err;
2519                         stats->rx_errors += ring->stats.l2_err;
2520                         stats->rx_errors += ring->stats.l3l4_csum_err;
2521                         stats->rx_crc_errors += ring->stats.l2_err;
2522                         stats->multicast += ring->stats.rx_multicast;
2523                         stats->rx_length_errors += ring->stats.err_pkt_len;
2524                 }
2525         } while (u64_stats_fetch_retry(&ring->syncp, start));
2526 }
2527
2528 static void hns3_nic_get_stats64(struct net_device *netdev,
2529                                  struct rtnl_link_stats64 *stats)
2530 {
2531         struct hns3_nic_priv *priv = netdev_priv(netdev);
2532         int queue_num = priv->ae_handle->kinfo.num_tqps;
2533         struct hnae3_handle *handle = priv->ae_handle;
2534         struct rtnl_link_stats64 ring_total_stats;
2535         struct hns3_enet_ring *ring;
2536         unsigned int idx;
2537
2538         if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
2539                 return;
2540
2541         handle->ae_algo->ops->update_stats(handle);
2542
2543         memset(&ring_total_stats, 0, sizeof(ring_total_stats));
2544         for (idx = 0; idx < queue_num; idx++) {
2545                 /* fetch the tx stats */
2546                 ring = &priv->ring[idx];
2547                 hns3_fetch_stats(&ring_total_stats, ring, true);
2548
2549                 /* fetch the rx stats */
2550                 ring = &priv->ring[idx + queue_num];
2551                 hns3_fetch_stats(&ring_total_stats, ring, false);
2552         }
2553
2554         stats->tx_bytes = ring_total_stats.tx_bytes;
2555         stats->tx_packets = ring_total_stats.tx_packets;
2556         stats->rx_bytes = ring_total_stats.rx_bytes;
2557         stats->rx_packets = ring_total_stats.rx_packets;
2558
2559         stats->rx_errors = ring_total_stats.rx_errors;
2560         stats->multicast = ring_total_stats.multicast;
2561         stats->rx_length_errors = ring_total_stats.rx_length_errors;
2562         stats->rx_crc_errors = ring_total_stats.rx_crc_errors;
2563         stats->rx_missed_errors = netdev->stats.rx_missed_errors;
2564
2565         stats->tx_errors = ring_total_stats.tx_errors;
2566         stats->rx_dropped = ring_total_stats.rx_dropped;
2567         stats->tx_dropped = ring_total_stats.tx_dropped;
2568         stats->collisions = netdev->stats.collisions;
2569         stats->rx_over_errors = netdev->stats.rx_over_errors;
2570         stats->rx_frame_errors = netdev->stats.rx_frame_errors;
2571         stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
2572         stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
2573         stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
2574         stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
2575         stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
2576         stats->tx_window_errors = netdev->stats.tx_window_errors;
2577         stats->rx_compressed = netdev->stats.rx_compressed;
2578         stats->tx_compressed = netdev->stats.tx_compressed;
2579 }
2580
2581 static int hns3_setup_tc(struct net_device *netdev, void *type_data)
2582 {
2583         struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
2584         struct hnae3_knic_private_info *kinfo;
2585         u8 tc = mqprio_qopt->qopt.num_tc;
2586         u16 mode = mqprio_qopt->mode;
2587         u8 hw = mqprio_qopt->qopt.hw;
2588         struct hnae3_handle *h;
2589
2590         if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
2591                mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
2592                 return -EOPNOTSUPP;
2593
2594         if (tc > HNAE3_MAX_TC)
2595                 return -EINVAL;
2596
2597         if (!netdev)
2598                 return -EINVAL;
2599
2600         h = hns3_get_handle(netdev);
2601         kinfo = &h->kinfo;
2602
2603         netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc);
2604
2605         return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
2606                 kinfo->dcb_ops->setup_tc(h, mqprio_qopt) : -EOPNOTSUPP;
2607 }
2608
2609 static int hns3_setup_tc_cls_flower(struct hns3_nic_priv *priv,
2610                                     struct flow_cls_offload *flow)
2611 {
2612         int tc = tc_classid_to_hwtc(priv->netdev, flow->classid);
2613         struct hnae3_handle *h = hns3_get_handle(priv->netdev);
2614
2615         switch (flow->command) {
2616         case FLOW_CLS_REPLACE:
2617                 if (h->ae_algo->ops->add_cls_flower)
2618                         return h->ae_algo->ops->add_cls_flower(h, flow, tc);
2619                 break;
2620         case FLOW_CLS_DESTROY:
2621                 if (h->ae_algo->ops->del_cls_flower)
2622                         return h->ae_algo->ops->del_cls_flower(h, flow);
2623                 break;
2624         default:
2625                 break;
2626         }
2627
2628         return -EOPNOTSUPP;
2629 }
2630
2631 static int hns3_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2632                                   void *cb_priv)
2633 {
2634         struct hns3_nic_priv *priv = cb_priv;
2635
2636         if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
2637                 return -EOPNOTSUPP;
2638
2639         switch (type) {
2640         case TC_SETUP_CLSFLOWER:
2641                 return hns3_setup_tc_cls_flower(priv, type_data);
2642         default:
2643                 return -EOPNOTSUPP;
2644         }
2645 }
2646
2647 static LIST_HEAD(hns3_block_cb_list);
2648
2649 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
2650                              void *type_data)
2651 {
2652         struct hns3_nic_priv *priv = netdev_priv(dev);
2653         int ret;
2654
2655         switch (type) {
2656         case TC_SETUP_QDISC_MQPRIO:
2657                 ret = hns3_setup_tc(dev, type_data);
2658                 break;
2659         case TC_SETUP_BLOCK:
2660                 ret = flow_block_cb_setup_simple(type_data,
2661                                                  &hns3_block_cb_list,
2662                                                  hns3_setup_tc_block_cb,
2663                                                  priv, priv, true);
2664                 break;
2665         default:
2666                 return -EOPNOTSUPP;
2667         }
2668
2669         return ret;
2670 }
2671
2672 static int hns3_vlan_rx_add_vid(struct net_device *netdev,
2673                                 __be16 proto, u16 vid)
2674 {
2675         struct hnae3_handle *h = hns3_get_handle(netdev);
2676         int ret = -EIO;
2677
2678         if (h->ae_algo->ops->set_vlan_filter)
2679                 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
2680
2681         return ret;
2682 }
2683
2684 static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
2685                                  __be16 proto, u16 vid)
2686 {
2687         struct hnae3_handle *h = hns3_get_handle(netdev);
2688         int ret = -EIO;
2689
2690         if (h->ae_algo->ops->set_vlan_filter)
2691                 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
2692
2693         return ret;
2694 }
2695
2696 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
2697                                 u8 qos, __be16 vlan_proto)
2698 {
2699         struct hnae3_handle *h = hns3_get_handle(netdev);
2700         int ret = -EIO;
2701
2702         netif_dbg(h, drv, netdev,
2703                   "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n",
2704                   vf, vlan, qos, ntohs(vlan_proto));
2705
2706         if (h->ae_algo->ops->set_vf_vlan_filter)
2707                 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
2708                                                           qos, vlan_proto);
2709
2710         return ret;
2711 }
2712
2713 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable)
2714 {
2715         struct hnae3_handle *handle = hns3_get_handle(netdev);
2716
2717         if (hns3_nic_resetting(netdev))
2718                 return -EBUSY;
2719
2720         if (!handle->ae_algo->ops->set_vf_spoofchk)
2721                 return -EOPNOTSUPP;
2722
2723         return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable);
2724 }
2725
2726 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable)
2727 {
2728         struct hnae3_handle *handle = hns3_get_handle(netdev);
2729
2730         if (!handle->ae_algo->ops->set_vf_trust)
2731                 return -EOPNOTSUPP;
2732
2733         return handle->ae_algo->ops->set_vf_trust(handle, vf, enable);
2734 }
2735
2736 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
2737 {
2738         struct hnae3_handle *h = hns3_get_handle(netdev);
2739         int ret;
2740
2741         if (hns3_nic_resetting(netdev))
2742                 return -EBUSY;
2743
2744         if (!h->ae_algo->ops->set_mtu)
2745                 return -EOPNOTSUPP;
2746
2747         netif_dbg(h, drv, netdev,
2748                   "change mtu from %u to %d\n", netdev->mtu, new_mtu);
2749
2750         ret = h->ae_algo->ops->set_mtu(h, new_mtu);
2751         if (ret)
2752                 netdev_err(netdev, "failed to change MTU in hardware %d\n",
2753                            ret);
2754         else
2755                 netdev->mtu = new_mtu;
2756
2757         return ret;
2758 }
2759
2760 static int hns3_get_timeout_queue(struct net_device *ndev)
2761 {
2762         int i;
2763
2764         /* Find the stopped queue the same way the stack does */
2765         for (i = 0; i < ndev->num_tx_queues; i++) {
2766                 struct netdev_queue *q;
2767                 unsigned long trans_start;
2768
2769                 q = netdev_get_tx_queue(ndev, i);
2770                 trans_start = READ_ONCE(q->trans_start);
2771                 if (netif_xmit_stopped(q) &&
2772                     time_after(jiffies,
2773                                (trans_start + ndev->watchdog_timeo))) {
2774 #ifdef CONFIG_BQL
2775                         struct dql *dql = &q->dql;
2776
2777                         netdev_info(ndev, "DQL info last_cnt: %u, queued: %u, adj_limit: %u, completed: %u\n",
2778                                     dql->last_obj_cnt, dql->num_queued,
2779                                     dql->adj_limit, dql->num_completed);
2780 #endif
2781                         netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",
2782                                     q->state,
2783                                     jiffies_to_msecs(jiffies - trans_start));
2784                         break;
2785                 }
2786         }
2787
2788         return i;
2789 }
2790
2791 static void hns3_dump_queue_stats(struct net_device *ndev,
2792                                   struct hns3_enet_ring *tx_ring,
2793                                   int timeout_queue)
2794 {
2795         struct napi_struct *napi = &tx_ring->tqp_vector->napi;
2796         struct hns3_nic_priv *priv = netdev_priv(ndev);
2797
2798         netdev_info(ndev,
2799                     "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n",
2800                     priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use,
2801                     tx_ring->next_to_clean, napi->state);
2802
2803         netdev_info(ndev,
2804                     "tx_pkts: %llu, tx_bytes: %llu, sw_err_cnt: %llu, tx_pending: %d\n",
2805                     tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes,
2806                     tx_ring->stats.sw_err_cnt, tx_ring->pending_buf);
2807
2808         netdev_info(ndev,
2809                     "seg_pkt_cnt: %llu, tx_more: %llu, restart_queue: %llu, tx_busy: %llu\n",
2810                     tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_more,
2811                     tx_ring->stats.restart_queue, tx_ring->stats.tx_busy);
2812
2813         netdev_info(ndev, "tx_push: %llu, tx_mem_doorbell: %llu\n",
2814                     tx_ring->stats.tx_push, tx_ring->stats.tx_mem_doorbell);
2815 }
2816
2817 static void hns3_dump_queue_reg(struct net_device *ndev,
2818                                 struct hns3_enet_ring *tx_ring)
2819 {
2820         netdev_info(ndev,
2821                     "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n",
2822                     hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_BD_NUM_REG),
2823                     hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_HEAD_REG),
2824                     hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_TAIL_REG),
2825                     hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_BD_ERR_REG),
2826                     readl(tx_ring->tqp_vector->mask_addr));
2827         netdev_info(ndev,
2828                     "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n",
2829                     hns3_tqp_read_reg(tx_ring, HNS3_RING_EN_REG),
2830                     hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_TC_REG),
2831                     hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_FBDNUM_REG),
2832                     hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_OFFSET_REG),
2833                     hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_EBDNUM_REG),
2834                     hns3_tqp_read_reg(tx_ring,
2835                                       HNS3_RING_TX_RING_EBD_OFFSET_REG));
2836 }
2837
2838 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
2839 {
2840         struct hns3_nic_priv *priv = netdev_priv(ndev);
2841         struct hnae3_handle *h = hns3_get_handle(ndev);
2842         struct hns3_enet_ring *tx_ring;
2843         int timeout_queue;
2844
2845         timeout_queue = hns3_get_timeout_queue(ndev);
2846         if (timeout_queue >= ndev->num_tx_queues) {
2847                 netdev_info(ndev,
2848                             "no netdev TX timeout queue found, timeout count: %llu\n",
2849                             priv->tx_timeout_count);
2850                 return false;
2851         }
2852
2853         priv->tx_timeout_count++;
2854
2855         tx_ring = &priv->ring[timeout_queue];
2856         hns3_dump_queue_stats(ndev, tx_ring, timeout_queue);
2857
2858         /* When mac received many pause frames continuous, it's unable to send
2859          * packets, which may cause tx timeout
2860          */
2861         if (h->ae_algo->ops->get_mac_stats) {
2862                 struct hns3_mac_stats mac_stats;
2863
2864                 h->ae_algo->ops->get_mac_stats(h, &mac_stats);
2865                 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
2866                             mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt);
2867         }
2868
2869         hns3_dump_queue_reg(ndev, tx_ring);
2870
2871         return true;
2872 }
2873
2874 static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue)
2875 {
2876         struct hns3_nic_priv *priv = netdev_priv(ndev);
2877         struct hnae3_handle *h = priv->ae_handle;
2878
2879         if (!hns3_get_tx_timeo_queue_info(ndev))
2880                 return;
2881
2882         /* request the reset, and let the hclge to determine
2883          * which reset level should be done
2884          */
2885         if (h->ae_algo->ops->reset_event)
2886                 h->ae_algo->ops->reset_event(h->pdev, h);
2887 }
2888
2889 #ifdef CONFIG_RFS_ACCEL
2890 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
2891                               u16 rxq_index, u32 flow_id)
2892 {
2893         struct hnae3_handle *h = hns3_get_handle(dev);
2894         struct flow_keys fkeys;
2895
2896         if (!h->ae_algo->ops->add_arfs_entry)
2897                 return -EOPNOTSUPP;
2898
2899         if (skb->encapsulation)
2900                 return -EPROTONOSUPPORT;
2901
2902         if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0))
2903                 return -EPROTONOSUPPORT;
2904
2905         if ((fkeys.basic.n_proto != htons(ETH_P_IP) &&
2906              fkeys.basic.n_proto != htons(ETH_P_IPV6)) ||
2907             (fkeys.basic.ip_proto != IPPROTO_TCP &&
2908              fkeys.basic.ip_proto != IPPROTO_UDP))
2909                 return -EPROTONOSUPPORT;
2910
2911         return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys);
2912 }
2913 #endif
2914
2915 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf,
2916                                   struct ifla_vf_info *ivf)
2917 {
2918         struct hnae3_handle *h = hns3_get_handle(ndev);
2919
2920         if (!h->ae_algo->ops->get_vf_config)
2921                 return -EOPNOTSUPP;
2922
2923         return h->ae_algo->ops->get_vf_config(h, vf, ivf);
2924 }
2925
2926 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf,
2927                                       int link_state)
2928 {
2929         struct hnae3_handle *h = hns3_get_handle(ndev);
2930
2931         if (!h->ae_algo->ops->set_vf_link_state)
2932                 return -EOPNOTSUPP;
2933
2934         return h->ae_algo->ops->set_vf_link_state(h, vf, link_state);
2935 }
2936
2937 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf,
2938                                 int min_tx_rate, int max_tx_rate)
2939 {
2940         struct hnae3_handle *h = hns3_get_handle(ndev);
2941
2942         if (!h->ae_algo->ops->set_vf_rate)
2943                 return -EOPNOTSUPP;
2944
2945         return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate,
2946                                             false);
2947 }
2948
2949 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
2950 {
2951         struct hnae3_handle *h = hns3_get_handle(netdev);
2952         char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
2953
2954         if (!h->ae_algo->ops->set_vf_mac)
2955                 return -EOPNOTSUPP;
2956
2957         if (is_multicast_ether_addr(mac)) {
2958                 hnae3_format_mac_addr(format_mac_addr, mac);
2959                 netdev_err(netdev,
2960                            "Invalid MAC:%s specified. Could not set MAC\n",
2961                            format_mac_addr);
2962                 return -EINVAL;
2963         }
2964
2965         return h->ae_algo->ops->set_vf_mac(h, vf_id, mac);
2966 }
2967
2968 #define HNS3_INVALID_DSCP               0xff
2969 #define HNS3_DSCP_SHIFT                 2
2970
2971 static u8 hns3_get_skb_dscp(struct sk_buff *skb)
2972 {
2973         __be16 protocol = skb->protocol;
2974         u8 dscp = HNS3_INVALID_DSCP;
2975
2976         if (protocol == htons(ETH_P_8021Q))
2977                 protocol = vlan_get_protocol(skb);
2978
2979         if (protocol == htons(ETH_P_IP))
2980                 dscp = ipv4_get_dsfield(ip_hdr(skb)) >> HNS3_DSCP_SHIFT;
2981         else if (protocol == htons(ETH_P_IPV6))
2982                 dscp = ipv6_get_dsfield(ipv6_hdr(skb)) >> HNS3_DSCP_SHIFT;
2983
2984         return dscp;
2985 }
2986
2987 static u16 hns3_nic_select_queue(struct net_device *netdev,
2988                                  struct sk_buff *skb,
2989                                  struct net_device *sb_dev)
2990 {
2991         struct hnae3_handle *h = hns3_get_handle(netdev);
2992         u8 dscp;
2993
2994         if (h->kinfo.tc_map_mode != HNAE3_TC_MAP_MODE_DSCP ||
2995             !h->ae_algo->ops->get_dscp_prio)
2996                 goto out;
2997
2998         dscp = hns3_get_skb_dscp(skb);
2999         if (unlikely(dscp >= HNAE3_MAX_DSCP))
3000                 goto out;
3001
3002         skb->priority = h->kinfo.dscp_prio[dscp];
3003         if (skb->priority == HNAE3_PRIO_ID_INVALID)
3004                 skb->priority = 0;
3005
3006 out:
3007         return netdev_pick_tx(netdev, skb, sb_dev);
3008 }
3009
3010 static const struct net_device_ops hns3_nic_netdev_ops = {
3011         .ndo_open               = hns3_nic_net_open,
3012         .ndo_stop               = hns3_nic_net_stop,
3013         .ndo_start_xmit         = hns3_nic_net_xmit,
3014         .ndo_tx_timeout         = hns3_nic_net_timeout,
3015         .ndo_set_mac_address    = hns3_nic_net_set_mac_address,
3016         .ndo_eth_ioctl          = hns3_nic_do_ioctl,
3017         .ndo_change_mtu         = hns3_nic_change_mtu,
3018         .ndo_set_features       = hns3_nic_set_features,
3019         .ndo_features_check     = hns3_features_check,
3020         .ndo_get_stats64        = hns3_nic_get_stats64,
3021         .ndo_setup_tc           = hns3_nic_setup_tc,
3022         .ndo_set_rx_mode        = hns3_nic_set_rx_mode,
3023         .ndo_vlan_rx_add_vid    = hns3_vlan_rx_add_vid,
3024         .ndo_vlan_rx_kill_vid   = hns3_vlan_rx_kill_vid,
3025         .ndo_set_vf_vlan        = hns3_ndo_set_vf_vlan,
3026         .ndo_set_vf_spoofchk    = hns3_set_vf_spoofchk,
3027         .ndo_set_vf_trust       = hns3_set_vf_trust,
3028 #ifdef CONFIG_RFS_ACCEL
3029         .ndo_rx_flow_steer      = hns3_rx_flow_steer,
3030 #endif
3031         .ndo_get_vf_config      = hns3_nic_get_vf_config,
3032         .ndo_set_vf_link_state  = hns3_nic_set_vf_link_state,
3033         .ndo_set_vf_rate        = hns3_nic_set_vf_rate,
3034         .ndo_set_vf_mac         = hns3_nic_set_vf_mac,
3035         .ndo_select_queue       = hns3_nic_select_queue,
3036 };
3037
3038 bool hns3_is_phys_func(struct pci_dev *pdev)
3039 {
3040         u32 dev_id = pdev->device;
3041
3042         switch (dev_id) {
3043         case HNAE3_DEV_ID_GE:
3044         case HNAE3_DEV_ID_25GE:
3045         case HNAE3_DEV_ID_25GE_RDMA:
3046         case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
3047         case HNAE3_DEV_ID_50GE_RDMA:
3048         case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
3049         case HNAE3_DEV_ID_100G_RDMA_MACSEC:
3050         case HNAE3_DEV_ID_200G_RDMA:
3051                 return true;
3052         case HNAE3_DEV_ID_VF:
3053         case HNAE3_DEV_ID_RDMA_DCB_PFC_VF:
3054                 return false;
3055         default:
3056                 dev_warn(&pdev->dev, "un-recognized pci device-id %u",
3057                          dev_id);
3058         }
3059
3060         return false;
3061 }
3062
3063 static void hns3_disable_sriov(struct pci_dev *pdev)
3064 {
3065         /* If our VFs are assigned we cannot shut down SR-IOV
3066          * without causing issues, so just leave the hardware
3067          * available but disabled
3068          */
3069         if (pci_vfs_assigned(pdev)) {
3070                 dev_warn(&pdev->dev,
3071                          "disabling driver while VFs are assigned\n");
3072                 return;
3073         }
3074
3075         pci_disable_sriov(pdev);
3076 }
3077
3078 /* hns3_probe - Device initialization routine
3079  * @pdev: PCI device information struct
3080  * @ent: entry in hns3_pci_tbl
3081  *
3082  * hns3_probe initializes a PF identified by a pci_dev structure.
3083  * The OS initialization, configuring of the PF private structure,
3084  * and a hardware reset occur.
3085  *
3086  * Returns 0 on success, negative on failure
3087  */
3088 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3089 {
3090         struct hnae3_ae_dev *ae_dev;
3091         int ret;
3092
3093         ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL);
3094         if (!ae_dev)
3095                 return -ENOMEM;
3096
3097         ae_dev->pdev = pdev;
3098         ae_dev->flag = ent->driver_data;
3099         pci_set_drvdata(pdev, ae_dev);
3100
3101         ret = hnae3_register_ae_dev(ae_dev);
3102         if (ret)
3103                 pci_set_drvdata(pdev, NULL);
3104
3105         return ret;
3106 }
3107
3108 /**
3109  * hns3_clean_vf_config
3110  * @pdev: pointer to a pci_dev structure
3111  * @num_vfs: number of VFs allocated
3112  *
3113  * Clean residual vf config after disable sriov
3114  **/
3115 static void hns3_clean_vf_config(struct pci_dev *pdev, int num_vfs)
3116 {
3117         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3118
3119         if (ae_dev->ops->clean_vf_config)
3120                 ae_dev->ops->clean_vf_config(ae_dev, num_vfs);
3121 }
3122
3123 /* hns3_remove - Device removal routine
3124  * @pdev: PCI device information struct
3125  */
3126 static void hns3_remove(struct pci_dev *pdev)
3127 {
3128         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3129
3130         if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
3131                 hns3_disable_sriov(pdev);
3132
3133         hnae3_unregister_ae_dev(ae_dev);
3134         pci_set_drvdata(pdev, NULL);
3135 }
3136
3137 /**
3138  * hns3_pci_sriov_configure
3139  * @pdev: pointer to a pci_dev structure
3140  * @num_vfs: number of VFs to allocate
3141  *
3142  * Enable or change the number of VFs. Called when the user updates the number
3143  * of VFs in sysfs.
3144  **/
3145 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
3146 {
3147         int ret;
3148
3149         if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
3150                 dev_warn(&pdev->dev, "Can not config SRIOV\n");
3151                 return -EINVAL;
3152         }
3153
3154         if (num_vfs) {
3155                 ret = pci_enable_sriov(pdev, num_vfs);
3156                 if (ret)
3157                         dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
3158                 else
3159                         return num_vfs;
3160         } else if (!pci_vfs_assigned(pdev)) {
3161                 int num_vfs_pre = pci_num_vf(pdev);
3162
3163                 pci_disable_sriov(pdev);
3164                 hns3_clean_vf_config(pdev, num_vfs_pre);
3165         } else {
3166                 dev_warn(&pdev->dev,
3167                          "Unable to free VFs because some are assigned to VMs.\n");
3168         }
3169
3170         return 0;
3171 }
3172
3173 static void hns3_shutdown(struct pci_dev *pdev)
3174 {
3175         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3176
3177         hnae3_unregister_ae_dev(ae_dev);
3178         pci_set_drvdata(pdev, NULL);
3179
3180         if (system_state == SYSTEM_POWER_OFF)
3181                 pci_set_power_state(pdev, PCI_D3hot);
3182 }
3183
3184 static int __maybe_unused hns3_suspend(struct device *dev)
3185 {
3186         struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev);
3187
3188         if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) {
3189                 dev_info(dev, "Begin to suspend.\n");
3190                 if (ae_dev->ops && ae_dev->ops->reset_prepare)
3191                         ae_dev->ops->reset_prepare(ae_dev, HNAE3_FUNC_RESET);
3192         }
3193
3194         return 0;
3195 }
3196
3197 static int __maybe_unused hns3_resume(struct device *dev)
3198 {
3199         struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev);
3200
3201         if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) {
3202                 dev_info(dev, "Begin to resume.\n");
3203                 if (ae_dev->ops && ae_dev->ops->reset_done)
3204                         ae_dev->ops->reset_done(ae_dev);
3205         }
3206
3207         return 0;
3208 }
3209
3210 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
3211                                             pci_channel_state_t state)
3212 {
3213         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3214         pci_ers_result_t ret;
3215
3216         dev_info(&pdev->dev, "PCI error detected, state(=%u)!!\n", state);
3217
3218         if (state == pci_channel_io_perm_failure)
3219                 return PCI_ERS_RESULT_DISCONNECT;
3220
3221         if (!ae_dev || !ae_dev->ops) {
3222                 dev_err(&pdev->dev,
3223                         "Can't recover - error happened before device initialized\n");
3224                 return PCI_ERS_RESULT_NONE;
3225         }
3226
3227         if (ae_dev->ops->handle_hw_ras_error)
3228                 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
3229         else
3230                 return PCI_ERS_RESULT_NONE;
3231
3232         return ret;
3233 }
3234
3235 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
3236 {
3237         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3238         const struct hnae3_ae_ops *ops;
3239         enum hnae3_reset_type reset_type;
3240         struct device *dev = &pdev->dev;
3241
3242         if (!ae_dev || !ae_dev->ops)
3243                 return PCI_ERS_RESULT_NONE;
3244
3245         ops = ae_dev->ops;
3246         /* request the reset */
3247         if (ops->reset_event && ops->get_reset_level &&
3248             ops->set_default_reset_request) {
3249                 if (ae_dev->hw_err_reset_req) {
3250                         reset_type = ops->get_reset_level(ae_dev,
3251                                                 &ae_dev->hw_err_reset_req);
3252                         ops->set_default_reset_request(ae_dev, reset_type);
3253                         dev_info(dev, "requesting reset due to PCI error\n");
3254                         ops->reset_event(pdev, NULL);
3255                 }
3256
3257                 return PCI_ERS_RESULT_RECOVERED;
3258         }
3259
3260         return PCI_ERS_RESULT_DISCONNECT;
3261 }
3262
3263 static void hns3_reset_prepare(struct pci_dev *pdev)
3264 {
3265         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3266
3267         dev_info(&pdev->dev, "FLR prepare\n");
3268         if (ae_dev && ae_dev->ops && ae_dev->ops->reset_prepare)
3269                 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FLR_RESET);
3270 }
3271
3272 static void hns3_reset_done(struct pci_dev *pdev)
3273 {
3274         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3275
3276         dev_info(&pdev->dev, "FLR done\n");
3277         if (ae_dev && ae_dev->ops && ae_dev->ops->reset_done)
3278                 ae_dev->ops->reset_done(ae_dev);
3279 }
3280
3281 static const struct pci_error_handlers hns3_err_handler = {
3282         .error_detected = hns3_error_detected,
3283         .slot_reset     = hns3_slot_reset,
3284         .reset_prepare  = hns3_reset_prepare,
3285         .reset_done     = hns3_reset_done,
3286 };
3287
3288 static SIMPLE_DEV_PM_OPS(hns3_pm_ops, hns3_suspend, hns3_resume);
3289
3290 static struct pci_driver hns3_driver = {
3291         .name     = hns3_driver_name,
3292         .id_table = hns3_pci_tbl,
3293         .probe    = hns3_probe,
3294         .remove   = hns3_remove,
3295         .shutdown = hns3_shutdown,
3296         .driver.pm  = &hns3_pm_ops,
3297         .sriov_configure = hns3_pci_sriov_configure,
3298         .err_handler    = &hns3_err_handler,
3299 };
3300
3301 /* set default feature to hns3 */
3302 static void hns3_set_default_feature(struct net_device *netdev)
3303 {
3304         struct hnae3_handle *h = hns3_get_handle(netdev);
3305         struct pci_dev *pdev = h->pdev;
3306         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3307
3308         netdev->priv_flags |= IFF_UNICAST_FLT;
3309
3310         netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
3311
3312         netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
3313                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
3314                 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
3315                 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
3316                 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
3317                 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST;
3318
3319         if (hnae3_ae_dev_gro_supported(ae_dev))
3320                 netdev->features |= NETIF_F_GRO_HW;
3321
3322         if (hnae3_ae_dev_fd_supported(ae_dev))
3323                 netdev->features |= NETIF_F_NTUPLE;
3324
3325         if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps))
3326                 netdev->features |= NETIF_F_GSO_UDP_L4;
3327
3328         if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
3329                 netdev->features |= NETIF_F_HW_CSUM;
3330         else
3331                 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
3332
3333         if (test_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, ae_dev->caps))
3334                 netdev->features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
3335
3336         if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps))
3337                 netdev->features |= NETIF_F_HW_TC;
3338
3339         netdev->hw_features |= netdev->features;
3340         if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps))
3341                 netdev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
3342
3343         netdev->vlan_features |= netdev->features &
3344                 ~(NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX |
3345                   NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_GRO_HW | NETIF_F_NTUPLE |
3346                   NETIF_F_HW_TC);
3347
3348         netdev->hw_enc_features |= netdev->vlan_features | NETIF_F_TSO_MANGLEID;
3349 }
3350
3351 static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
3352                              struct hns3_desc_cb *cb)
3353 {
3354         unsigned int order = hns3_page_order(ring);
3355         struct page *p;
3356
3357         if (ring->page_pool) {
3358                 p = page_pool_dev_alloc_frag(ring->page_pool,
3359                                              &cb->page_offset,
3360                                              hns3_buf_size(ring));
3361                 if (unlikely(!p))
3362                         return -ENOMEM;
3363
3364                 cb->priv = p;
3365                 cb->buf = page_address(p);
3366                 cb->dma = page_pool_get_dma_addr(p);
3367                 cb->type = DESC_TYPE_PP_FRAG;
3368                 cb->reuse_flag = 0;
3369                 return 0;
3370         }
3371
3372         p = dev_alloc_pages(order);
3373         if (!p)
3374                 return -ENOMEM;
3375
3376         cb->priv = p;
3377         cb->page_offset = 0;
3378         cb->reuse_flag = 0;
3379         cb->buf  = page_address(p);
3380         cb->length = hns3_page_size(ring);
3381         cb->type = DESC_TYPE_PAGE;
3382         page_ref_add(p, USHRT_MAX - 1);
3383         cb->pagecnt_bias = USHRT_MAX;
3384
3385         return 0;
3386 }
3387
3388 static void hns3_free_buffer(struct hns3_enet_ring *ring,
3389                              struct hns3_desc_cb *cb, int budget)
3390 {
3391         if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_HEAD |
3392                         DESC_TYPE_BOUNCE_ALL | DESC_TYPE_SGL_SKB))
3393                 napi_consume_skb(cb->priv, budget);
3394         else if (!HNAE3_IS_TX_RING(ring)) {
3395                 if (cb->type & DESC_TYPE_PAGE && cb->pagecnt_bias)
3396                         __page_frag_cache_drain(cb->priv, cb->pagecnt_bias);
3397                 else if (cb->type & DESC_TYPE_PP_FRAG)
3398                         page_pool_put_full_page(ring->page_pool, cb->priv,
3399                                                 false);
3400         }
3401         memset(cb, 0, sizeof(*cb));
3402 }
3403
3404 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
3405 {
3406         cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
3407                                cb->length, ring_to_dma_dir(ring));
3408
3409         if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
3410                 return -EIO;
3411
3412         return 0;
3413 }
3414
3415 static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
3416                               struct hns3_desc_cb *cb)
3417 {
3418         if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
3419                 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
3420                                  ring_to_dma_dir(ring));
3421         else if ((cb->type & DESC_TYPE_PAGE) && cb->length)
3422                 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
3423                                ring_to_dma_dir(ring));
3424         else if (cb->type & (DESC_TYPE_BOUNCE_ALL | DESC_TYPE_BOUNCE_HEAD |
3425                              DESC_TYPE_SGL_SKB))
3426                 hns3_tx_spare_reclaim_cb(ring, cb);
3427 }
3428
3429 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
3430 {
3431         hns3_unmap_buffer(ring, &ring->desc_cb[i]);
3432         ring->desc[i].addr = 0;
3433         ring->desc_cb[i].refill = 0;
3434 }
3435
3436 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i,
3437                                     int budget)
3438 {
3439         struct hns3_desc_cb *cb = &ring->desc_cb[i];
3440
3441         if (!ring->desc_cb[i].dma)
3442                 return;
3443
3444         hns3_buffer_detach(ring, i);
3445         hns3_free_buffer(ring, cb, budget);
3446 }
3447
3448 static void hns3_free_buffers(struct hns3_enet_ring *ring)
3449 {
3450         int i;
3451
3452         for (i = 0; i < ring->desc_num; i++)
3453                 hns3_free_buffer_detach(ring, i, 0);
3454 }
3455
3456 /* free desc along with its attached buffer */
3457 static void hns3_free_desc(struct hns3_enet_ring *ring)
3458 {
3459         int size = ring->desc_num * sizeof(ring->desc[0]);
3460
3461         hns3_free_buffers(ring);
3462
3463         if (ring->desc) {
3464                 dma_free_coherent(ring_to_dev(ring), size,
3465                                   ring->desc, ring->desc_dma_addr);
3466                 ring->desc = NULL;
3467         }
3468 }
3469
3470 static int hns3_alloc_desc(struct hns3_enet_ring *ring)
3471 {
3472         int size = ring->desc_num * sizeof(ring->desc[0]);
3473
3474         ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
3475                                         &ring->desc_dma_addr, GFP_KERNEL);
3476         if (!ring->desc)
3477                 return -ENOMEM;
3478
3479         return 0;
3480 }
3481
3482 static int hns3_alloc_and_map_buffer(struct hns3_enet_ring *ring,
3483                                    struct hns3_desc_cb *cb)
3484 {
3485         int ret;
3486
3487         ret = hns3_alloc_buffer(ring, cb);
3488         if (ret || ring->page_pool)
3489                 goto out;
3490
3491         ret = hns3_map_buffer(ring, cb);
3492         if (ret)
3493                 goto out_with_buf;
3494
3495         return 0;
3496
3497 out_with_buf:
3498         hns3_free_buffer(ring, cb, 0);
3499 out:
3500         return ret;
3501 }
3502
3503 static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i)
3504 {
3505         int ret = hns3_alloc_and_map_buffer(ring, &ring->desc_cb[i]);
3506
3507         if (ret)
3508                 return ret;
3509
3510         ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3511                                          ring->desc_cb[i].page_offset);
3512         ring->desc_cb[i].refill = 1;
3513
3514         return 0;
3515 }
3516
3517 /* Allocate memory for raw pkg, and map with dma */
3518 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
3519 {
3520         int i, j, ret;
3521
3522         for (i = 0; i < ring->desc_num; i++) {
3523                 ret = hns3_alloc_and_attach_buffer(ring, i);
3524                 if (ret)
3525                         goto out_buffer_fail;
3526         }
3527
3528         return 0;
3529
3530 out_buffer_fail:
3531         for (j = i - 1; j >= 0; j--)
3532                 hns3_free_buffer_detach(ring, j, 0);
3533         return ret;
3534 }
3535
3536 /* detach a in-used buffer and replace with a reserved one */
3537 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
3538                                 struct hns3_desc_cb *res_cb)
3539 {
3540         hns3_unmap_buffer(ring, &ring->desc_cb[i]);
3541         ring->desc_cb[i] = *res_cb;
3542         ring->desc_cb[i].refill = 1;
3543         ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3544                                          ring->desc_cb[i].page_offset);
3545         ring->desc[i].rx.bd_base_info = 0;
3546 }
3547
3548 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
3549 {
3550         ring->desc_cb[i].reuse_flag = 0;
3551         ring->desc_cb[i].refill = 1;
3552         ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3553                                          ring->desc_cb[i].page_offset);
3554         ring->desc[i].rx.bd_base_info = 0;
3555
3556         dma_sync_single_for_device(ring_to_dev(ring),
3557                         ring->desc_cb[i].dma + ring->desc_cb[i].page_offset,
3558                         hns3_buf_size(ring),
3559                         DMA_FROM_DEVICE);
3560 }
3561
3562 static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring,
3563                                   int *bytes, int *pkts, int budget)
3564 {
3565         /* pair with ring->last_to_use update in hns3_tx_doorbell(),
3566          * smp_store_release() is not used in hns3_tx_doorbell() because
3567          * the doorbell operation already have the needed barrier operation.
3568          */
3569         int ltu = smp_load_acquire(&ring->last_to_use);
3570         int ntc = ring->next_to_clean;
3571         struct hns3_desc_cb *desc_cb;
3572         bool reclaimed = false;
3573         struct hns3_desc *desc;
3574
3575         while (ltu != ntc) {
3576                 desc = &ring->desc[ntc];
3577
3578                 if (le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri) &
3579                                 BIT(HNS3_TXD_VLD_B))
3580                         break;
3581
3582                 desc_cb = &ring->desc_cb[ntc];
3583
3584                 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_ALL |
3585                                      DESC_TYPE_BOUNCE_HEAD |
3586                                      DESC_TYPE_SGL_SKB)) {
3587                         (*pkts)++;
3588                         (*bytes) += desc_cb->send_bytes;
3589                 }
3590
3591                 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */
3592                 hns3_free_buffer_detach(ring, ntc, budget);
3593
3594                 if (++ntc == ring->desc_num)
3595                         ntc = 0;
3596
3597                 /* Issue prefetch for next Tx descriptor */
3598                 prefetch(&ring->desc_cb[ntc]);
3599                 reclaimed = true;
3600         }
3601
3602         if (unlikely(!reclaimed))
3603                 return false;
3604
3605         /* This smp_store_release() pairs with smp_load_acquire() in
3606          * ring_space called by hns3_nic_net_xmit.
3607          */
3608         smp_store_release(&ring->next_to_clean, ntc);
3609
3610         hns3_tx_spare_update(ring);
3611
3612         return true;
3613 }
3614
3615 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget)
3616 {
3617         struct net_device *netdev = ring_to_netdev(ring);
3618         struct hns3_nic_priv *priv = netdev_priv(netdev);
3619         struct netdev_queue *dev_queue;
3620         int bytes, pkts;
3621
3622         bytes = 0;
3623         pkts = 0;
3624
3625         if (unlikely(!hns3_nic_reclaim_desc(ring, &bytes, &pkts, budget)))
3626                 return;
3627
3628         ring->tqp_vector->tx_group.total_bytes += bytes;
3629         ring->tqp_vector->tx_group.total_packets += pkts;
3630
3631         u64_stats_update_begin(&ring->syncp);
3632         ring->stats.tx_bytes += bytes;
3633         ring->stats.tx_pkts += pkts;
3634         u64_stats_update_end(&ring->syncp);
3635
3636         dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
3637         netdev_tx_completed_queue(dev_queue, pkts, bytes);
3638
3639         if (unlikely(netif_carrier_ok(netdev) &&
3640                      ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) {
3641                 /* Make sure that anybody stopping the queue after this
3642                  * sees the new next_to_clean.
3643                  */
3644                 smp_mb();
3645                 if (netif_tx_queue_stopped(dev_queue) &&
3646                     !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
3647                         netif_tx_wake_queue(dev_queue);
3648                         ring->stats.restart_queue++;
3649                 }
3650         }
3651 }
3652
3653 static int hns3_desc_unused(struct hns3_enet_ring *ring)
3654 {
3655         int ntc = ring->next_to_clean;
3656         int ntu = ring->next_to_use;
3657
3658         if (unlikely(ntc == ntu && !ring->desc_cb[ntc].refill))
3659                 return ring->desc_num;
3660
3661         return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
3662 }
3663
3664 /* Return true if there is any allocation failure */
3665 static bool hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
3666                                       int cleand_count)
3667 {
3668         struct hns3_desc_cb *desc_cb;
3669         struct hns3_desc_cb res_cbs;
3670         int i, ret;
3671
3672         for (i = 0; i < cleand_count; i++) {
3673                 desc_cb = &ring->desc_cb[ring->next_to_use];
3674                 if (desc_cb->reuse_flag) {
3675                         hns3_ring_stats_update(ring, reuse_pg_cnt);
3676
3677                         hns3_reuse_buffer(ring, ring->next_to_use);
3678                 } else {
3679                         ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
3680                         if (ret) {
3681                                 hns3_ring_stats_update(ring, sw_err_cnt);
3682
3683                                 hns3_rl_err(ring_to_netdev(ring),
3684                                             "alloc rx buffer failed: %d\n",
3685                                             ret);
3686
3687                                 writel(i, ring->tqp->io_base +
3688                                        HNS3_RING_RX_RING_HEAD_REG);
3689                                 return true;
3690                         }
3691                         hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
3692
3693                         hns3_ring_stats_update(ring, non_reuse_pg);
3694                 }
3695
3696                 ring_ptr_move_fw(ring, next_to_use);
3697         }
3698
3699         writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
3700         return false;
3701 }
3702
3703 static bool hns3_can_reuse_page(struct hns3_desc_cb *cb)
3704 {
3705         return page_count(cb->priv) == cb->pagecnt_bias;
3706 }
3707
3708 static int hns3_handle_rx_copybreak(struct sk_buff *skb, int i,
3709                                     struct hns3_enet_ring *ring,
3710                                     int pull_len,
3711                                     struct hns3_desc_cb *desc_cb)
3712 {
3713         struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
3714         u32 frag_offset = desc_cb->page_offset + pull_len;
3715         int size = le16_to_cpu(desc->rx.size);
3716         u32 frag_size = size - pull_len;
3717         void *frag = napi_alloc_frag(frag_size);
3718
3719         if (unlikely(!frag)) {
3720                 hns3_ring_stats_update(ring, frag_alloc_err);
3721
3722                 hns3_rl_err(ring_to_netdev(ring),
3723                             "failed to allocate rx frag\n");
3724                 return -ENOMEM;
3725         }
3726
3727         desc_cb->reuse_flag = 1;
3728         memcpy(frag, desc_cb->buf + frag_offset, frag_size);
3729         skb_add_rx_frag(skb, i, virt_to_page(frag),
3730                         offset_in_page(frag), frag_size, frag_size);
3731
3732         hns3_ring_stats_update(ring, frag_alloc);
3733         return 0;
3734 }
3735
3736 static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
3737                                 struct hns3_enet_ring *ring, int pull_len,
3738                                 struct hns3_desc_cb *desc_cb)
3739 {
3740         struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
3741         u32 frag_offset = desc_cb->page_offset + pull_len;
3742         int size = le16_to_cpu(desc->rx.size);
3743         u32 truesize = hns3_buf_size(ring);
3744         u32 frag_size = size - pull_len;
3745         int ret = 0;
3746         bool reused;
3747
3748         if (ring->page_pool) {
3749                 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset,
3750                                 frag_size, truesize);
3751                 return;
3752         }
3753
3754         /* Avoid re-using remote or pfmem page */
3755         if (unlikely(!dev_page_is_reusable(desc_cb->priv)))
3756                 goto out;
3757
3758         reused = hns3_can_reuse_page(desc_cb);
3759
3760         /* Rx page can be reused when:
3761          * 1. Rx page is only owned by the driver when page_offset
3762          *    is zero, which means 0 @ truesize will be used by
3763          *    stack after skb_add_rx_frag() is called, and the rest
3764          *    of rx page can be reused by driver.
3765          * Or
3766          * 2. Rx page is only owned by the driver when page_offset
3767          *    is non-zero, which means page_offset @ truesize will
3768          *    be used by stack after skb_add_rx_frag() is called,
3769          *    and 0 @ truesize can be reused by driver.
3770          */
3771         if ((!desc_cb->page_offset && reused) ||
3772             ((desc_cb->page_offset + truesize + truesize) <=
3773              hns3_page_size(ring) && desc_cb->page_offset)) {
3774                 desc_cb->page_offset += truesize;
3775                 desc_cb->reuse_flag = 1;
3776         } else if (desc_cb->page_offset && reused) {
3777                 desc_cb->page_offset = 0;
3778                 desc_cb->reuse_flag = 1;
3779         } else if (frag_size <= ring->rx_copybreak) {
3780                 ret = hns3_handle_rx_copybreak(skb, i, ring, pull_len, desc_cb);
3781                 if (!ret)
3782                         return;
3783         }
3784
3785 out:
3786         desc_cb->pagecnt_bias--;
3787
3788         if (unlikely(!desc_cb->pagecnt_bias)) {
3789                 page_ref_add(desc_cb->priv, USHRT_MAX);
3790                 desc_cb->pagecnt_bias = USHRT_MAX;
3791         }
3792
3793         skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset,
3794                         frag_size, truesize);
3795
3796         if (unlikely(!desc_cb->reuse_flag))
3797                 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias);
3798 }
3799
3800 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info)
3801 {
3802         __be16 type = skb->protocol;
3803         struct tcphdr *th;
3804         int depth = 0;
3805
3806         while (eth_type_vlan(type)) {
3807                 struct vlan_hdr *vh;
3808
3809                 if ((depth + VLAN_HLEN) > skb_headlen(skb))
3810                         return -EFAULT;
3811
3812                 vh = (struct vlan_hdr *)(skb->data + depth);
3813                 type = vh->h_vlan_encapsulated_proto;
3814                 depth += VLAN_HLEN;
3815         }
3816
3817         skb_set_network_header(skb, depth);
3818
3819         if (type == htons(ETH_P_IP)) {
3820                 const struct iphdr *iph = ip_hdr(skb);
3821
3822                 depth += sizeof(struct iphdr);
3823                 skb_set_transport_header(skb, depth);
3824                 th = tcp_hdr(skb);
3825                 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr,
3826                                           iph->daddr, 0);
3827         } else if (type == htons(ETH_P_IPV6)) {
3828                 const struct ipv6hdr *iph = ipv6_hdr(skb);
3829
3830                 depth += sizeof(struct ipv6hdr);
3831                 skb_set_transport_header(skb, depth);
3832                 th = tcp_hdr(skb);
3833                 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr,
3834                                           &iph->daddr, 0);
3835         } else {
3836                 hns3_rl_err(skb->dev,
3837                             "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n",
3838                             be16_to_cpu(type), depth);
3839                 return -EFAULT;
3840         }
3841
3842         skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
3843         if (th->cwr)
3844                 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
3845
3846         if (l234info & BIT(HNS3_RXD_GRO_FIXID_B))
3847                 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID;
3848
3849         skb->csum_start = (unsigned char *)th - skb->head;
3850         skb->csum_offset = offsetof(struct tcphdr, check);
3851         skb->ip_summed = CHECKSUM_PARTIAL;
3852
3853         trace_hns3_gro(skb);
3854
3855         return 0;
3856 }
3857
3858 static void hns3_checksum_complete(struct hns3_enet_ring *ring,
3859                                    struct sk_buff *skb, u32 ptype, u16 csum)
3860 {
3861         if (ptype == HNS3_INVALID_PTYPE ||
3862             hns3_rx_ptype_tbl[ptype].ip_summed != CHECKSUM_COMPLETE)
3863                 return;
3864
3865         hns3_ring_stats_update(ring, csum_complete);
3866         skb->ip_summed = CHECKSUM_COMPLETE;
3867         skb->csum = csum_unfold((__force __sum16)csum);
3868 }
3869
3870 static void hns3_rx_handle_csum(struct sk_buff *skb, u32 l234info,
3871                                 u32 ol_info, u32 ptype)
3872 {
3873         int l3_type, l4_type;
3874         int ol4_type;
3875
3876         if (ptype != HNS3_INVALID_PTYPE) {
3877                 skb->csum_level = hns3_rx_ptype_tbl[ptype].csum_level;
3878                 skb->ip_summed = hns3_rx_ptype_tbl[ptype].ip_summed;
3879
3880                 return;
3881         }
3882
3883         ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M,
3884                                    HNS3_RXD_OL4ID_S);
3885         switch (ol4_type) {
3886         case HNS3_OL4_TYPE_MAC_IN_UDP:
3887         case HNS3_OL4_TYPE_NVGRE:
3888                 skb->csum_level = 1;
3889                 fallthrough;
3890         case HNS3_OL4_TYPE_NO_TUN:
3891                 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
3892                                           HNS3_RXD_L3ID_S);
3893                 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
3894                                           HNS3_RXD_L4ID_S);
3895                 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
3896                 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
3897                      l3_type == HNS3_L3_TYPE_IPV6) &&
3898                     (l4_type == HNS3_L4_TYPE_UDP ||
3899                      l4_type == HNS3_L4_TYPE_TCP ||
3900                      l4_type == HNS3_L4_TYPE_SCTP))
3901                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3902                 break;
3903         default:
3904                 break;
3905         }
3906 }
3907
3908 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
3909                              u32 l234info, u32 bd_base_info, u32 ol_info,
3910                              u16 csum)
3911 {
3912         struct net_device *netdev = ring_to_netdev(ring);
3913         struct hns3_nic_priv *priv = netdev_priv(netdev);
3914         u32 ptype = HNS3_INVALID_PTYPE;
3915
3916         skb->ip_summed = CHECKSUM_NONE;
3917
3918         skb_checksum_none_assert(skb);
3919
3920         if (!(netdev->features & NETIF_F_RXCSUM))
3921                 return;
3922
3923         if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state))
3924                 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
3925                                         HNS3_RXD_PTYPE_S);
3926
3927         hns3_checksum_complete(ring, skb, ptype, csum);
3928
3929         /* check if hardware has done checksum */
3930         if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
3931                 return;
3932
3933         if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
3934                                  BIT(HNS3_RXD_OL3E_B) |
3935                                  BIT(HNS3_RXD_OL4E_B)))) {
3936                 skb->ip_summed = CHECKSUM_NONE;
3937                 hns3_ring_stats_update(ring, l3l4_csum_err);
3938
3939                 return;
3940         }
3941
3942         hns3_rx_handle_csum(skb, l234info, ol_info, ptype);
3943 }
3944
3945 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
3946 {
3947         if (skb_has_frag_list(skb))
3948                 napi_gro_flush(&ring->tqp_vector->napi, false);
3949
3950         napi_gro_receive(&ring->tqp_vector->napi, skb);
3951 }
3952
3953 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
3954                                 struct hns3_desc *desc, u32 l234info,
3955                                 u16 *vlan_tag)
3956 {
3957         struct hnae3_handle *handle = ring->tqp->handle;
3958         struct pci_dev *pdev = ring->tqp->handle->pdev;
3959         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3960
3961         if (unlikely(ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)) {
3962                 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
3963                 if (!(*vlan_tag & VLAN_VID_MASK))
3964                         *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
3965
3966                 return (*vlan_tag != 0);
3967         }
3968
3969 #define HNS3_STRP_OUTER_VLAN    0x1
3970 #define HNS3_STRP_INNER_VLAN    0x2
3971 #define HNS3_STRP_BOTH          0x3
3972
3973         /* Hardware always insert VLAN tag into RX descriptor when
3974          * remove the tag from packet, driver needs to determine
3975          * reporting which tag to stack.
3976          */
3977         switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
3978                                 HNS3_RXD_STRP_TAGP_S)) {
3979         case HNS3_STRP_OUTER_VLAN:
3980                 if (handle->port_base_vlan_state !=
3981                                 HNAE3_PORT_BASE_VLAN_DISABLE)
3982                         return false;
3983
3984                 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
3985                 return true;
3986         case HNS3_STRP_INNER_VLAN:
3987                 if (handle->port_base_vlan_state !=
3988                                 HNAE3_PORT_BASE_VLAN_DISABLE)
3989                         return false;
3990
3991                 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
3992                 return true;
3993         case HNS3_STRP_BOTH:
3994                 if (handle->port_base_vlan_state ==
3995                                 HNAE3_PORT_BASE_VLAN_DISABLE)
3996                         *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
3997                 else
3998                         *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
3999
4000                 return true;
4001         default:
4002                 return false;
4003         }
4004 }
4005
4006 static void hns3_rx_ring_move_fw(struct hns3_enet_ring *ring)
4007 {
4008         ring->desc[ring->next_to_clean].rx.bd_base_info &=
4009                 cpu_to_le32(~BIT(HNS3_RXD_VLD_B));
4010         ring->desc_cb[ring->next_to_clean].refill = 0;
4011         ring->next_to_clean += 1;
4012
4013         if (unlikely(ring->next_to_clean == ring->desc_num))
4014                 ring->next_to_clean = 0;
4015 }
4016
4017 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length,
4018                           unsigned char *va)
4019 {
4020         struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
4021         struct net_device *netdev = ring_to_netdev(ring);
4022         struct sk_buff *skb;
4023
4024         ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
4025         skb = ring->skb;
4026         if (unlikely(!skb)) {
4027                 hns3_rl_err(netdev, "alloc rx skb fail\n");
4028                 hns3_ring_stats_update(ring, sw_err_cnt);
4029
4030                 return -ENOMEM;
4031         }
4032
4033         trace_hns3_rx_desc(ring);
4034         prefetchw(skb->data);
4035
4036         ring->pending_buf = 1;
4037         ring->frag_num = 0;
4038         ring->tail_skb = NULL;
4039         if (length <= HNS3_RX_HEAD_SIZE) {
4040                 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
4041
4042                 /* We can reuse buffer as-is, just make sure it is reusable */
4043                 if (dev_page_is_reusable(desc_cb->priv))
4044                         desc_cb->reuse_flag = 1;
4045                 else if (desc_cb->type & DESC_TYPE_PP_FRAG)
4046                         page_pool_put_full_page(ring->page_pool, desc_cb->priv,
4047                                                 false);
4048                 else /* This page cannot be reused so discard it */
4049                         __page_frag_cache_drain(desc_cb->priv,
4050                                                 desc_cb->pagecnt_bias);
4051
4052                 hns3_rx_ring_move_fw(ring);
4053                 return 0;
4054         }
4055
4056         if (ring->page_pool)
4057                 skb_mark_for_recycle(skb);
4058
4059         hns3_ring_stats_update(ring, seg_pkt_cnt);
4060
4061         ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE);
4062         __skb_put(skb, ring->pull_len);
4063         hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
4064                             desc_cb);
4065         hns3_rx_ring_move_fw(ring);
4066
4067         return 0;
4068 }
4069
4070 static int hns3_add_frag(struct hns3_enet_ring *ring)
4071 {
4072         struct sk_buff *skb = ring->skb;
4073         struct sk_buff *head_skb = skb;
4074         struct sk_buff *new_skb;
4075         struct hns3_desc_cb *desc_cb;
4076         struct hns3_desc *desc;
4077         u32 bd_base_info;
4078
4079         do {
4080                 desc = &ring->desc[ring->next_to_clean];
4081                 desc_cb = &ring->desc_cb[ring->next_to_clean];
4082                 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4083                 /* make sure HW write desc complete */
4084                 dma_rmb();
4085                 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
4086                         return -ENXIO;
4087
4088                 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
4089                         new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0);
4090                         if (unlikely(!new_skb)) {
4091                                 hns3_rl_err(ring_to_netdev(ring),
4092                                             "alloc rx fraglist skb fail\n");
4093                                 return -ENXIO;
4094                         }
4095
4096                         if (ring->page_pool)
4097                                 skb_mark_for_recycle(new_skb);
4098
4099                         ring->frag_num = 0;
4100
4101                         if (ring->tail_skb) {
4102                                 ring->tail_skb->next = new_skb;
4103                                 ring->tail_skb = new_skb;
4104                         } else {
4105                                 skb_shinfo(skb)->frag_list = new_skb;
4106                                 ring->tail_skb = new_skb;
4107                         }
4108                 }
4109
4110                 if (ring->tail_skb) {
4111                         head_skb->truesize += hns3_buf_size(ring);
4112                         head_skb->data_len += le16_to_cpu(desc->rx.size);
4113                         head_skb->len += le16_to_cpu(desc->rx.size);
4114                         skb = ring->tail_skb;
4115                 }
4116
4117                 dma_sync_single_for_cpu(ring_to_dev(ring),
4118                                 desc_cb->dma + desc_cb->page_offset,
4119                                 hns3_buf_size(ring),
4120                                 DMA_FROM_DEVICE);
4121
4122                 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
4123                 trace_hns3_rx_desc(ring);
4124                 hns3_rx_ring_move_fw(ring);
4125                 ring->pending_buf++;
4126         } while (!(bd_base_info & BIT(HNS3_RXD_FE_B)));
4127
4128         return 0;
4129 }
4130
4131 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring,
4132                                      struct sk_buff *skb, u32 l234info,
4133                                      u32 bd_base_info, u32 ol_info, u16 csum)
4134 {
4135         struct net_device *netdev = ring_to_netdev(ring);
4136         struct hns3_nic_priv *priv = netdev_priv(netdev);
4137         u32 l3_type;
4138
4139         skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
4140                                                     HNS3_RXD_GRO_SIZE_M,
4141                                                     HNS3_RXD_GRO_SIZE_S);
4142         /* if there is no HW GRO, do not set gro params */
4143         if (!skb_shinfo(skb)->gso_size) {
4144                 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info,
4145                                  csum);
4146                 return 0;
4147         }
4148
4149         NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info,
4150                                                   HNS3_RXD_GRO_COUNT_M,
4151                                                   HNS3_RXD_GRO_COUNT_S);
4152
4153         if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) {
4154                 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
4155                                             HNS3_RXD_PTYPE_S);
4156
4157                 l3_type = hns3_rx_ptype_tbl[ptype].l3_type;
4158         } else {
4159                 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
4160                                           HNS3_RXD_L3ID_S);
4161         }
4162
4163         if (l3_type == HNS3_L3_TYPE_IPV4)
4164                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
4165         else if (l3_type == HNS3_L3_TYPE_IPV6)
4166                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
4167         else
4168                 return -EFAULT;
4169
4170         return  hns3_gro_complete(skb, l234info);
4171 }
4172
4173 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
4174                                      struct sk_buff *skb, u32 rss_hash,
4175                                      u32 l234info, u32 ol_info)
4176 {
4177         enum pkt_hash_types rss_type = PKT_HASH_TYPE_NONE;
4178         struct net_device *netdev = ring_to_netdev(ring);
4179         struct hns3_nic_priv *priv = netdev_priv(netdev);
4180
4181         if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) {
4182                 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
4183                                             HNS3_RXD_PTYPE_S);
4184
4185                 rss_type = hns3_rx_ptype_tbl[ptype].hash_type;
4186         } else {
4187                 int l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
4188                                               HNS3_RXD_L3ID_S);
4189                 int l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
4190                                               HNS3_RXD_L4ID_S);
4191
4192                 if (l3_type == HNS3_L3_TYPE_IPV4 ||
4193                     l3_type == HNS3_L3_TYPE_IPV6) {
4194                         if (l4_type == HNS3_L4_TYPE_UDP ||
4195                             l4_type == HNS3_L4_TYPE_TCP ||
4196                             l4_type == HNS3_L4_TYPE_SCTP)
4197                                 rss_type = PKT_HASH_TYPE_L4;
4198                         else if (l4_type == HNS3_L4_TYPE_IGMP ||
4199                                  l4_type == HNS3_L4_TYPE_ICMP)
4200                                 rss_type = PKT_HASH_TYPE_L3;
4201                 }
4202         }
4203
4204         skb_set_hash(skb, rss_hash, rss_type);
4205 }
4206
4207 static void hns3_handle_rx_ts_info(struct net_device *netdev,
4208                                    struct hns3_desc *desc, struct sk_buff *skb,
4209                                    u32 bd_base_info)
4210 {
4211         if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) {
4212                 struct hnae3_handle *h = hns3_get_handle(netdev);
4213                 u32 nsec = le32_to_cpu(desc->ts_nsec);
4214                 u32 sec = le32_to_cpu(desc->ts_sec);
4215
4216                 if (h->ae_algo->ops->get_rx_hwts)
4217                         h->ae_algo->ops->get_rx_hwts(h, skb, nsec, sec);
4218         }
4219 }
4220
4221 static void hns3_handle_rx_vlan_tag(struct hns3_enet_ring *ring,
4222                                     struct hns3_desc *desc, struct sk_buff *skb,
4223                                     u32 l234info)
4224 {
4225         struct net_device *netdev = ring_to_netdev(ring);
4226
4227         /* Based on hw strategy, the tag offloaded will be stored at
4228          * ot_vlan_tag in two layer tag case, and stored at vlan_tag
4229          * in one layer tag case.
4230          */
4231         if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
4232                 u16 vlan_tag;
4233
4234                 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
4235                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
4236                                                vlan_tag);
4237         }
4238 }
4239
4240 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb)
4241 {
4242         struct net_device *netdev = ring_to_netdev(ring);
4243         enum hns3_pkt_l2t_type l2_frame_type;
4244         u32 bd_base_info, l234info, ol_info;
4245         struct hns3_desc *desc;
4246         unsigned int len;
4247         int pre_ntc, ret;
4248         u16 csum;
4249
4250         /* bdinfo handled below is only valid on the last BD of the
4251          * current packet, and ring->next_to_clean indicates the first
4252          * descriptor of next packet, so need - 1 below.
4253          */
4254         pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) :
4255                                         (ring->desc_num - 1);
4256         desc = &ring->desc[pre_ntc];
4257         bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4258         l234info = le32_to_cpu(desc->rx.l234_info);
4259         ol_info = le32_to_cpu(desc->rx.ol_info);
4260         csum = le16_to_cpu(desc->csum);
4261
4262         hns3_handle_rx_ts_info(netdev, desc, skb, bd_base_info);
4263
4264         hns3_handle_rx_vlan_tag(ring, desc, skb, l234info);
4265
4266         if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) |
4267                                   BIT(HNS3_RXD_L2E_B))))) {
4268                 u64_stats_update_begin(&ring->syncp);
4269                 if (l234info & BIT(HNS3_RXD_L2E_B))
4270                         ring->stats.l2_err++;
4271                 else
4272                         ring->stats.err_pkt_len++;
4273                 u64_stats_update_end(&ring->syncp);
4274
4275                 return -EFAULT;
4276         }
4277
4278         len = skb->len;
4279
4280         /* Do update ip stack process */
4281         skb->protocol = eth_type_trans(skb, netdev);
4282
4283         /* This is needed in order to enable forwarding support */
4284         ret = hns3_set_gro_and_checksum(ring, skb, l234info,
4285                                         bd_base_info, ol_info, csum);
4286         if (unlikely(ret)) {
4287                 hns3_ring_stats_update(ring, rx_err_cnt);
4288                 return ret;
4289         }
4290
4291         l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
4292                                         HNS3_RXD_DMAC_S);
4293
4294         u64_stats_update_begin(&ring->syncp);
4295         ring->stats.rx_pkts++;
4296         ring->stats.rx_bytes += len;
4297
4298         if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
4299                 ring->stats.rx_multicast++;
4300
4301         u64_stats_update_end(&ring->syncp);
4302
4303         ring->tqp_vector->rx_group.total_bytes += len;
4304
4305         hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash),
4306                                  l234info, ol_info);
4307         return 0;
4308 }
4309
4310 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring)
4311 {
4312         struct sk_buff *skb = ring->skb;
4313         struct hns3_desc_cb *desc_cb;
4314         struct hns3_desc *desc;
4315         unsigned int length;
4316         u32 bd_base_info;
4317         int ret;
4318
4319         desc = &ring->desc[ring->next_to_clean];
4320         desc_cb = &ring->desc_cb[ring->next_to_clean];
4321
4322         prefetch(desc);
4323
4324         if (!skb) {
4325                 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4326                 /* Check valid BD */
4327                 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
4328                         return -ENXIO;
4329
4330                 dma_rmb();
4331                 length = le16_to_cpu(desc->rx.size);
4332
4333                 ring->va = desc_cb->buf + desc_cb->page_offset;
4334
4335                 dma_sync_single_for_cpu(ring_to_dev(ring),
4336                                 desc_cb->dma + desc_cb->page_offset,
4337                                 hns3_buf_size(ring),
4338                                 DMA_FROM_DEVICE);
4339
4340                 /* Prefetch first cache line of first page.
4341                  * Idea is to cache few bytes of the header of the packet.
4342                  * Our L1 Cache line size is 64B so need to prefetch twice to make
4343                  * it 128B. But in actual we can have greater size of caches with
4344                  * 128B Level 1 cache lines. In such a case, single fetch would
4345                  * suffice to cache in the relevant part of the header.
4346                  */
4347                 net_prefetch(ring->va);
4348
4349                 ret = hns3_alloc_skb(ring, length, ring->va);
4350                 skb = ring->skb;
4351
4352                 if (ret < 0) /* alloc buffer fail */
4353                         return ret;
4354                 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */
4355                         ret = hns3_add_frag(ring);
4356                         if (ret)
4357                                 return ret;
4358                 }
4359         } else {
4360                 ret = hns3_add_frag(ring);
4361                 if (ret)
4362                         return ret;
4363         }
4364
4365         /* As the head data may be changed when GRO enable, copy
4366          * the head data in after other data rx completed
4367          */
4368         if (skb->len > HNS3_RX_HEAD_SIZE)
4369                 memcpy(skb->data, ring->va,
4370                        ALIGN(ring->pull_len, sizeof(long)));
4371
4372         ret = hns3_handle_bdinfo(ring, skb);
4373         if (unlikely(ret)) {
4374                 dev_kfree_skb_any(skb);
4375                 return ret;
4376         }
4377
4378         skb_record_rx_queue(skb, ring->tqp->tqp_index);
4379         return 0;
4380 }
4381
4382 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
4383                        void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
4384 {
4385 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
4386         int unused_count = hns3_desc_unused(ring);
4387         bool failure = false;
4388         int recv_pkts = 0;
4389         int err;
4390
4391         unused_count -= ring->pending_buf;
4392
4393         while (recv_pkts < budget) {
4394                 /* Reuse or realloc buffers */
4395                 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
4396                         failure = failure ||
4397                                 hns3_nic_alloc_rx_buffers(ring, unused_count);
4398                         unused_count = 0;
4399                 }
4400
4401                 /* Poll one pkt */
4402                 err = hns3_handle_rx_bd(ring);
4403                 /* Do not get FE for the packet or failed to alloc skb */
4404                 if (unlikely(!ring->skb || err == -ENXIO)) {
4405                         goto out;
4406                 } else if (likely(!err)) {
4407                         rx_fn(ring, ring->skb);
4408                         recv_pkts++;
4409                 }
4410
4411                 unused_count += ring->pending_buf;
4412                 ring->skb = NULL;
4413                 ring->pending_buf = 0;
4414         }
4415
4416 out:
4417         /* sync head pointer before exiting, since hardware will calculate
4418          * FBD number with head pointer
4419          */
4420         if (unused_count > 0)
4421                 failure = failure ||
4422                           hns3_nic_alloc_rx_buffers(ring, unused_count);
4423
4424         return failure ? budget : recv_pkts;
4425 }
4426
4427 static void hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector)
4428 {
4429         struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
4430         struct dim_sample sample = {};
4431
4432         if (!rx_group->coal.adapt_enable)
4433                 return;
4434
4435         dim_update_sample(tqp_vector->event_cnt, rx_group->total_packets,
4436                           rx_group->total_bytes, &sample);
4437         net_dim(&rx_group->dim, sample);
4438 }
4439
4440 static void hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector)
4441 {
4442         struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
4443         struct dim_sample sample = {};
4444
4445         if (!tx_group->coal.adapt_enable)
4446                 return;
4447
4448         dim_update_sample(tqp_vector->event_cnt, tx_group->total_packets,
4449                           tx_group->total_bytes, &sample);
4450         net_dim(&tx_group->dim, sample);
4451 }
4452
4453 static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
4454 {
4455         struct hns3_nic_priv *priv = netdev_priv(napi->dev);
4456         struct hns3_enet_ring *ring;
4457         int rx_pkt_total = 0;
4458
4459         struct hns3_enet_tqp_vector *tqp_vector =
4460                 container_of(napi, struct hns3_enet_tqp_vector, napi);
4461         bool clean_complete = true;
4462         int rx_budget = budget;
4463
4464         if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
4465                 napi_complete(napi);
4466                 return 0;
4467         }
4468
4469         /* Since the actual Tx work is minimal, we can give the Tx a larger
4470          * budget and be more aggressive about cleaning up the Tx descriptors.
4471          */
4472         hns3_for_each_ring(ring, tqp_vector->tx_group)
4473                 hns3_clean_tx_ring(ring, budget);
4474
4475         /* make sure rx ring budget not smaller than 1 */
4476         if (tqp_vector->num_tqps > 1)
4477                 rx_budget = max(budget / tqp_vector->num_tqps, 1);
4478
4479         hns3_for_each_ring(ring, tqp_vector->rx_group) {
4480                 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
4481                                                     hns3_rx_skb);
4482                 if (rx_cleaned >= rx_budget)
4483                         clean_complete = false;
4484
4485                 rx_pkt_total += rx_cleaned;
4486         }
4487
4488         tqp_vector->rx_group.total_packets += rx_pkt_total;
4489
4490         if (!clean_complete)
4491                 return budget;
4492
4493         if (napi_complete(napi) &&
4494             likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
4495                 hns3_update_rx_int_coalesce(tqp_vector);
4496                 hns3_update_tx_int_coalesce(tqp_vector);
4497
4498                 hns3_mask_vector_irq(tqp_vector, 1);
4499         }
4500
4501         return rx_pkt_total;
4502 }
4503
4504 static int hns3_create_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
4505                                   struct hnae3_ring_chain_node **head,
4506                                   bool is_tx)
4507 {
4508         u32 bit_value = is_tx ? HNAE3_RING_TYPE_TX : HNAE3_RING_TYPE_RX;
4509         u32 field_value = is_tx ? HNAE3_RING_GL_TX : HNAE3_RING_GL_RX;
4510         struct hnae3_ring_chain_node *cur_chain = *head;
4511         struct pci_dev *pdev = tqp_vector->handle->pdev;
4512         struct hnae3_ring_chain_node *chain;
4513         struct hns3_enet_ring *ring;
4514
4515         ring = is_tx ? tqp_vector->tx_group.ring : tqp_vector->rx_group.ring;
4516
4517         if (cur_chain) {
4518                 while (cur_chain->next)
4519                         cur_chain = cur_chain->next;
4520         }
4521
4522         while (ring) {
4523                 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
4524                 if (!chain)
4525                         return -ENOMEM;
4526                 if (cur_chain)
4527                         cur_chain->next = chain;
4528                 else
4529                         *head = chain;
4530                 chain->tqp_index = ring->tqp->tqp_index;
4531                 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
4532                                 bit_value);
4533                 hnae3_set_field(chain->int_gl_idx,
4534                                 HNAE3_RING_GL_IDX_M,
4535                                 HNAE3_RING_GL_IDX_S, field_value);
4536
4537                 cur_chain = chain;
4538
4539                 ring = ring->next;
4540         }
4541
4542         return 0;
4543 }
4544
4545 static struct hnae3_ring_chain_node *
4546 hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector)
4547 {
4548         struct pci_dev *pdev = tqp_vector->handle->pdev;
4549         struct hnae3_ring_chain_node *cur_chain = NULL;
4550         struct hnae3_ring_chain_node *chain;
4551
4552         if (hns3_create_ring_chain(tqp_vector, &cur_chain, true))
4553                 goto err_free_chain;
4554
4555         if (hns3_create_ring_chain(tqp_vector, &cur_chain, false))
4556                 goto err_free_chain;
4557
4558         return cur_chain;
4559
4560 err_free_chain:
4561         while (cur_chain) {
4562                 chain = cur_chain->next;
4563                 devm_kfree(&pdev->dev, cur_chain);
4564                 cur_chain = chain;
4565         }
4566
4567         return NULL;
4568 }
4569
4570 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
4571                                         struct hnae3_ring_chain_node *head)
4572 {
4573         struct pci_dev *pdev = tqp_vector->handle->pdev;
4574         struct hnae3_ring_chain_node *chain_tmp, *chain;
4575
4576         chain = head;
4577
4578         while (chain) {
4579                 chain_tmp = chain->next;
4580                 devm_kfree(&pdev->dev, chain);
4581                 chain = chain_tmp;
4582         }
4583 }
4584
4585 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
4586                                    struct hns3_enet_ring *ring)
4587 {
4588         ring->next = group->ring;
4589         group->ring = ring;
4590
4591         group->count++;
4592 }
4593
4594 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
4595 {
4596         struct pci_dev *pdev = priv->ae_handle->pdev;
4597         struct hns3_enet_tqp_vector *tqp_vector;
4598         int num_vectors = priv->vector_num;
4599         int numa_node;
4600         int vector_i;
4601
4602         numa_node = dev_to_node(&pdev->dev);
4603
4604         for (vector_i = 0; vector_i < num_vectors; vector_i++) {
4605                 tqp_vector = &priv->tqp_vector[vector_i];
4606                 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
4607                                 &tqp_vector->affinity_mask);
4608         }
4609 }
4610
4611 static void hns3_rx_dim_work(struct work_struct *work)
4612 {
4613         struct dim *dim = container_of(work, struct dim, work);
4614         struct hns3_enet_ring_group *group = container_of(dim,
4615                 struct hns3_enet_ring_group, dim);
4616         struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector;
4617         struct dim_cq_moder cur_moder =
4618                 net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
4619
4620         hns3_set_vector_coalesce_rx_gl(group->ring->tqp_vector, cur_moder.usec);
4621         tqp_vector->rx_group.coal.int_gl = cur_moder.usec;
4622
4623         if (cur_moder.pkts < tqp_vector->rx_group.coal.int_ql_max) {
4624                 hns3_set_vector_coalesce_rx_ql(tqp_vector, cur_moder.pkts);
4625                 tqp_vector->rx_group.coal.int_ql = cur_moder.pkts;
4626         }
4627
4628         dim->state = DIM_START_MEASURE;
4629 }
4630
4631 static void hns3_tx_dim_work(struct work_struct *work)
4632 {
4633         struct dim *dim = container_of(work, struct dim, work);
4634         struct hns3_enet_ring_group *group = container_of(dim,
4635                 struct hns3_enet_ring_group, dim);
4636         struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector;
4637         struct dim_cq_moder cur_moder =
4638                 net_dim_get_tx_moderation(dim->mode, dim->profile_ix);
4639
4640         hns3_set_vector_coalesce_tx_gl(tqp_vector, cur_moder.usec);
4641         tqp_vector->tx_group.coal.int_gl = cur_moder.usec;
4642
4643         if (cur_moder.pkts < tqp_vector->tx_group.coal.int_ql_max) {
4644                 hns3_set_vector_coalesce_tx_ql(tqp_vector, cur_moder.pkts);
4645                 tqp_vector->tx_group.coal.int_ql = cur_moder.pkts;
4646         }
4647
4648         dim->state = DIM_START_MEASURE;
4649 }
4650
4651 static void hns3_nic_init_dim(struct hns3_enet_tqp_vector *tqp_vector)
4652 {
4653         INIT_WORK(&tqp_vector->rx_group.dim.work, hns3_rx_dim_work);
4654         INIT_WORK(&tqp_vector->tx_group.dim.work, hns3_tx_dim_work);
4655 }
4656
4657 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
4658 {
4659         struct hnae3_handle *h = priv->ae_handle;
4660         struct hns3_enet_tqp_vector *tqp_vector;
4661         int ret;
4662         int i;
4663
4664         hns3_nic_set_cpumask(priv);
4665
4666         for (i = 0; i < priv->vector_num; i++) {
4667                 tqp_vector = &priv->tqp_vector[i];
4668                 hns3_vector_coalesce_init_hw(tqp_vector, priv);
4669                 tqp_vector->num_tqps = 0;
4670                 hns3_nic_init_dim(tqp_vector);
4671         }
4672
4673         for (i = 0; i < h->kinfo.num_tqps; i++) {
4674                 u16 vector_i = i % priv->vector_num;
4675                 u16 tqp_num = h->kinfo.num_tqps;
4676
4677                 tqp_vector = &priv->tqp_vector[vector_i];
4678
4679                 hns3_add_ring_to_group(&tqp_vector->tx_group,
4680                                        &priv->ring[i]);
4681
4682                 hns3_add_ring_to_group(&tqp_vector->rx_group,
4683                                        &priv->ring[i + tqp_num]);
4684
4685                 priv->ring[i].tqp_vector = tqp_vector;
4686                 priv->ring[i + tqp_num].tqp_vector = tqp_vector;
4687                 tqp_vector->num_tqps++;
4688         }
4689
4690         for (i = 0; i < priv->vector_num; i++) {
4691                 struct hnae3_ring_chain_node *vector_ring_chain;
4692
4693                 tqp_vector = &priv->tqp_vector[i];
4694
4695                 tqp_vector->rx_group.total_bytes = 0;
4696                 tqp_vector->rx_group.total_packets = 0;
4697                 tqp_vector->tx_group.total_bytes = 0;
4698                 tqp_vector->tx_group.total_packets = 0;
4699                 tqp_vector->handle = h;
4700
4701                 vector_ring_chain = hns3_get_vector_ring_chain(tqp_vector);
4702                 if (!vector_ring_chain) {
4703                         ret = -ENOMEM;
4704                         goto map_ring_fail;
4705                 }
4706
4707                 ret = h->ae_algo->ops->map_ring_to_vector(h,
4708                         tqp_vector->vector_irq, vector_ring_chain);
4709
4710                 hns3_free_vector_ring_chain(tqp_vector, vector_ring_chain);
4711
4712                 if (ret)
4713                         goto map_ring_fail;
4714
4715                 netif_napi_add(priv->netdev, &tqp_vector->napi,
4716                                hns3_nic_common_poll);
4717         }
4718
4719         return 0;
4720
4721 map_ring_fail:
4722         while (i--)
4723                 netif_napi_del(&priv->tqp_vector[i].napi);
4724
4725         return ret;
4726 }
4727
4728 static void hns3_nic_init_coal_cfg(struct hns3_nic_priv *priv)
4729 {
4730         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
4731         struct hns3_enet_coalesce *tx_coal = &priv->tx_coal;
4732         struct hns3_enet_coalesce *rx_coal = &priv->rx_coal;
4733
4734         /* initialize the configuration for interrupt coalescing.
4735          * 1. GL (Interrupt Gap Limiter)
4736          * 2. RL (Interrupt Rate Limiter)
4737          * 3. QL (Interrupt Quantity Limiter)
4738          *
4739          * Default: enable interrupt coalescing self-adaptive and GL
4740          */
4741         tx_coal->adapt_enable = 1;
4742         rx_coal->adapt_enable = 1;
4743
4744         tx_coal->int_gl = HNS3_INT_GL_50K;
4745         rx_coal->int_gl = HNS3_INT_GL_50K;
4746
4747         rx_coal->flow_level = HNS3_FLOW_LOW;
4748         tx_coal->flow_level = HNS3_FLOW_LOW;
4749
4750         if (ae_dev->dev_specs.int_ql_max) {
4751                 tx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
4752                 rx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
4753         }
4754 }
4755
4756 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
4757 {
4758         struct hnae3_handle *h = priv->ae_handle;
4759         struct hns3_enet_tqp_vector *tqp_vector;
4760         struct hnae3_vector_info *vector;
4761         struct pci_dev *pdev = h->pdev;
4762         u16 tqp_num = h->kinfo.num_tqps;
4763         u16 vector_num;
4764         int ret = 0;
4765         u16 i;
4766
4767         /* RSS size, cpu online and vector_num should be the same */
4768         /* Should consider 2p/4p later */
4769         vector_num = min_t(u16, num_online_cpus(), tqp_num);
4770
4771         vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
4772                               GFP_KERNEL);
4773         if (!vector)
4774                 return -ENOMEM;
4775
4776         /* save the actual available vector number */
4777         vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
4778
4779         priv->vector_num = vector_num;
4780         priv->tqp_vector = (struct hns3_enet_tqp_vector *)
4781                 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
4782                              GFP_KERNEL);
4783         if (!priv->tqp_vector) {
4784                 ret = -ENOMEM;
4785                 goto out;
4786         }
4787
4788         for (i = 0; i < priv->vector_num; i++) {
4789                 tqp_vector = &priv->tqp_vector[i];
4790                 tqp_vector->idx = i;
4791                 tqp_vector->mask_addr = vector[i].io_addr;
4792                 tqp_vector->vector_irq = vector[i].vector;
4793                 hns3_vector_coalesce_init(tqp_vector, priv);
4794         }
4795
4796 out:
4797         devm_kfree(&pdev->dev, vector);
4798         return ret;
4799 }
4800
4801 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
4802 {
4803         group->ring = NULL;
4804         group->count = 0;
4805 }
4806
4807 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
4808 {
4809         struct hnae3_ring_chain_node *vector_ring_chain;
4810         struct hnae3_handle *h = priv->ae_handle;
4811         struct hns3_enet_tqp_vector *tqp_vector;
4812         int i;
4813
4814         for (i = 0; i < priv->vector_num; i++) {
4815                 tqp_vector = &priv->tqp_vector[i];
4816
4817                 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
4818                         continue;
4819
4820                 /* Since the mapping can be overwritten, when fail to get the
4821                  * chain between vector and ring, we should go on to deal with
4822                  * the remaining options.
4823                  */
4824                 vector_ring_chain = hns3_get_vector_ring_chain(tqp_vector);
4825                 if (!vector_ring_chain)
4826                         dev_warn(priv->dev, "failed to get ring chain\n");
4827
4828                 h->ae_algo->ops->unmap_ring_from_vector(h,
4829                         tqp_vector->vector_irq, vector_ring_chain);
4830
4831                 hns3_free_vector_ring_chain(tqp_vector, vector_ring_chain);
4832
4833                 hns3_clear_ring_group(&tqp_vector->rx_group);
4834                 hns3_clear_ring_group(&tqp_vector->tx_group);
4835                 netif_napi_del(&priv->tqp_vector[i].napi);
4836         }
4837 }
4838
4839 static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
4840 {
4841         struct hnae3_handle *h = priv->ae_handle;
4842         struct pci_dev *pdev = h->pdev;
4843         int i, ret;
4844
4845         for (i = 0; i < priv->vector_num; i++) {
4846                 struct hns3_enet_tqp_vector *tqp_vector;
4847
4848                 tqp_vector = &priv->tqp_vector[i];
4849                 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
4850                 if (ret)
4851                         return;
4852         }
4853
4854         devm_kfree(&pdev->dev, priv->tqp_vector);
4855 }
4856
4857 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
4858                               unsigned int ring_type)
4859 {
4860         int queue_num = priv->ae_handle->kinfo.num_tqps;
4861         struct hns3_enet_ring *ring;
4862         int desc_num;
4863
4864         if (ring_type == HNAE3_RING_TYPE_TX) {
4865                 ring = &priv->ring[q->tqp_index];
4866                 desc_num = priv->ae_handle->kinfo.num_tx_desc;
4867                 ring->queue_index = q->tqp_index;
4868                 ring->tx_copybreak = priv->tx_copybreak;
4869                 ring->last_to_use = 0;
4870         } else {
4871                 ring = &priv->ring[q->tqp_index + queue_num];
4872                 desc_num = priv->ae_handle->kinfo.num_rx_desc;
4873                 ring->queue_index = q->tqp_index;
4874                 ring->rx_copybreak = priv->rx_copybreak;
4875         }
4876
4877         hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
4878
4879         ring->tqp = q;
4880         ring->desc = NULL;
4881         ring->desc_cb = NULL;
4882         ring->dev = priv->dev;
4883         ring->desc_dma_addr = 0;
4884         ring->buf_size = q->buf_size;
4885         ring->desc_num = desc_num;
4886         ring->next_to_use = 0;
4887         ring->next_to_clean = 0;
4888 }
4889
4890 static void hns3_queue_to_ring(struct hnae3_queue *tqp,
4891                                struct hns3_nic_priv *priv)
4892 {
4893         hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
4894         hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
4895 }
4896
4897 static int hns3_get_ring_config(struct hns3_nic_priv *priv)
4898 {
4899         struct hnae3_handle *h = priv->ae_handle;
4900         struct pci_dev *pdev = h->pdev;
4901         int i;
4902
4903         priv->ring = devm_kzalloc(&pdev->dev,
4904                                   array3_size(h->kinfo.num_tqps,
4905                                               sizeof(*priv->ring), 2),
4906                                   GFP_KERNEL);
4907         if (!priv->ring)
4908                 return -ENOMEM;
4909
4910         for (i = 0; i < h->kinfo.num_tqps; i++)
4911                 hns3_queue_to_ring(h->kinfo.tqp[i], priv);
4912
4913         return 0;
4914 }
4915
4916 static void hns3_put_ring_config(struct hns3_nic_priv *priv)
4917 {
4918         if (!priv->ring)
4919                 return;
4920
4921         devm_kfree(priv->dev, priv->ring);
4922         priv->ring = NULL;
4923 }
4924
4925 static void hns3_alloc_page_pool(struct hns3_enet_ring *ring)
4926 {
4927         struct page_pool_params pp_params = {
4928                 .flags = PP_FLAG_DMA_MAP | PP_FLAG_PAGE_FRAG |
4929                                 PP_FLAG_DMA_SYNC_DEV,
4930                 .order = hns3_page_order(ring),
4931                 .pool_size = ring->desc_num * hns3_buf_size(ring) /
4932                                 (PAGE_SIZE << hns3_page_order(ring)),
4933                 .nid = dev_to_node(ring_to_dev(ring)),
4934                 .dev = ring_to_dev(ring),
4935                 .dma_dir = DMA_FROM_DEVICE,
4936                 .offset = 0,
4937                 .max_len = PAGE_SIZE << hns3_page_order(ring),
4938         };
4939
4940         ring->page_pool = page_pool_create(&pp_params);
4941         if (IS_ERR(ring->page_pool)) {
4942                 dev_warn(ring_to_dev(ring), "page pool creation failed: %ld\n",
4943                          PTR_ERR(ring->page_pool));
4944                 ring->page_pool = NULL;
4945         }
4946 }
4947
4948 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
4949 {
4950         int ret;
4951
4952         if (ring->desc_num <= 0 || ring->buf_size <= 0)
4953                 return -EINVAL;
4954
4955         ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num,
4956                                      sizeof(ring->desc_cb[0]), GFP_KERNEL);
4957         if (!ring->desc_cb) {
4958                 ret = -ENOMEM;
4959                 goto out;
4960         }
4961
4962         ret = hns3_alloc_desc(ring);
4963         if (ret)
4964                 goto out_with_desc_cb;
4965
4966         if (!HNAE3_IS_TX_RING(ring)) {
4967                 if (page_pool_enabled)
4968                         hns3_alloc_page_pool(ring);
4969
4970                 ret = hns3_alloc_ring_buffers(ring);
4971                 if (ret)
4972                         goto out_with_desc;
4973         } else {
4974                 hns3_init_tx_spare_buffer(ring);
4975         }
4976
4977         return 0;
4978
4979 out_with_desc:
4980         hns3_free_desc(ring);
4981 out_with_desc_cb:
4982         devm_kfree(ring_to_dev(ring), ring->desc_cb);
4983         ring->desc_cb = NULL;
4984 out:
4985         return ret;
4986 }
4987
4988 void hns3_fini_ring(struct hns3_enet_ring *ring)
4989 {
4990         hns3_free_desc(ring);
4991         devm_kfree(ring_to_dev(ring), ring->desc_cb);
4992         ring->desc_cb = NULL;
4993         ring->next_to_clean = 0;
4994         ring->next_to_use = 0;
4995         ring->last_to_use = 0;
4996         ring->pending_buf = 0;
4997         if (!HNAE3_IS_TX_RING(ring) && ring->skb) {
4998                 dev_kfree_skb_any(ring->skb);
4999                 ring->skb = NULL;
5000         } else if (HNAE3_IS_TX_RING(ring) && ring->tx_spare) {
5001                 struct hns3_tx_spare *tx_spare = ring->tx_spare;
5002
5003                 dma_unmap_page(ring_to_dev(ring), tx_spare->dma, tx_spare->len,
5004                                DMA_TO_DEVICE);
5005                 free_pages((unsigned long)tx_spare->buf,
5006                            get_order(tx_spare->len));
5007                 devm_kfree(ring_to_dev(ring), tx_spare);
5008                 ring->tx_spare = NULL;
5009         }
5010
5011         if (!HNAE3_IS_TX_RING(ring) && ring->page_pool) {
5012                 page_pool_destroy(ring->page_pool);
5013                 ring->page_pool = NULL;
5014         }
5015 }
5016
5017 static int hns3_buf_size2type(u32 buf_size)
5018 {
5019         int bd_size_type;
5020
5021         switch (buf_size) {
5022         case 512:
5023                 bd_size_type = HNS3_BD_SIZE_512_TYPE;
5024                 break;
5025         case 1024:
5026                 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
5027                 break;
5028         case 2048:
5029                 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
5030                 break;
5031         case 4096:
5032                 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
5033                 break;
5034         default:
5035                 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
5036         }
5037
5038         return bd_size_type;
5039 }
5040
5041 static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
5042 {
5043         dma_addr_t dma = ring->desc_dma_addr;
5044         struct hnae3_queue *q = ring->tqp;
5045
5046         if (!HNAE3_IS_TX_RING(ring)) {
5047                 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma);
5048                 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
5049                                (u32)((dma >> 31) >> 1));
5050
5051                 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
5052                                hns3_buf_size2type(ring->buf_size));
5053                 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
5054                                ring->desc_num / 8 - 1);
5055         } else {
5056                 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
5057                                (u32)dma);
5058                 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
5059                                (u32)((dma >> 31) >> 1));
5060
5061                 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
5062                                ring->desc_num / 8 - 1);
5063         }
5064 }
5065
5066 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
5067 {
5068         struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
5069         struct hnae3_tc_info *tc_info = &kinfo->tc_info;
5070         int i;
5071
5072         for (i = 0; i < tc_info->num_tc; i++) {
5073                 int j;
5074
5075                 for (j = 0; j < tc_info->tqp_count[i]; j++) {
5076                         struct hnae3_queue *q;
5077
5078                         q = priv->ring[tc_info->tqp_offset[i] + j].tqp;
5079                         hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, i);
5080                 }
5081         }
5082 }
5083
5084 int hns3_init_all_ring(struct hns3_nic_priv *priv)
5085 {
5086         struct hnae3_handle *h = priv->ae_handle;
5087         int ring_num = h->kinfo.num_tqps * 2;
5088         int i, j;
5089         int ret;
5090
5091         for (i = 0; i < ring_num; i++) {
5092                 ret = hns3_alloc_ring_memory(&priv->ring[i]);
5093                 if (ret) {
5094                         dev_err(priv->dev,
5095                                 "Alloc ring memory fail! ret=%d\n", ret);
5096                         goto out_when_alloc_ring_memory;
5097                 }
5098
5099                 u64_stats_init(&priv->ring[i].syncp);
5100         }
5101
5102         return 0;
5103
5104 out_when_alloc_ring_memory:
5105         for (j = i - 1; j >= 0; j--)
5106                 hns3_fini_ring(&priv->ring[j]);
5107
5108         return -ENOMEM;
5109 }
5110
5111 static void hns3_uninit_all_ring(struct hns3_nic_priv *priv)
5112 {
5113         struct hnae3_handle *h = priv->ae_handle;
5114         int i;
5115
5116         for (i = 0; i < h->kinfo.num_tqps; i++) {
5117                 hns3_fini_ring(&priv->ring[i]);
5118                 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]);
5119         }
5120 }
5121
5122 /* Set mac addr if it is configured. or leave it to the AE driver */
5123 static int hns3_init_mac_addr(struct net_device *netdev)
5124 {
5125         struct hns3_nic_priv *priv = netdev_priv(netdev);
5126         char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
5127         struct hnae3_handle *h = priv->ae_handle;
5128         u8 mac_addr_temp[ETH_ALEN];
5129         int ret = 0;
5130
5131         if (h->ae_algo->ops->get_mac_addr)
5132                 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
5133
5134         /* Check if the MAC address is valid, if not get a random one */
5135         if (!is_valid_ether_addr(mac_addr_temp)) {
5136                 eth_hw_addr_random(netdev);
5137                 hnae3_format_mac_addr(format_mac_addr, netdev->dev_addr);
5138                 dev_warn(priv->dev, "using random MAC address %s\n",
5139                          format_mac_addr);
5140         } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) {
5141                 eth_hw_addr_set(netdev, mac_addr_temp);
5142                 ether_addr_copy(netdev->perm_addr, mac_addr_temp);
5143         } else {
5144                 return 0;
5145         }
5146
5147         if (h->ae_algo->ops->set_mac_addr)
5148                 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
5149
5150         return ret;
5151 }
5152
5153 static int hns3_init_phy(struct net_device *netdev)
5154 {
5155         struct hnae3_handle *h = hns3_get_handle(netdev);
5156         int ret = 0;
5157
5158         if (h->ae_algo->ops->mac_connect_phy)
5159                 ret = h->ae_algo->ops->mac_connect_phy(h);
5160
5161         return ret;
5162 }
5163
5164 static void hns3_uninit_phy(struct net_device *netdev)
5165 {
5166         struct hnae3_handle *h = hns3_get_handle(netdev);
5167
5168         if (h->ae_algo->ops->mac_disconnect_phy)
5169                 h->ae_algo->ops->mac_disconnect_phy(h);
5170 }
5171
5172 static int hns3_client_start(struct hnae3_handle *handle)
5173 {
5174         if (!handle->ae_algo->ops->client_start)
5175                 return 0;
5176
5177         return handle->ae_algo->ops->client_start(handle);
5178 }
5179
5180 static void hns3_client_stop(struct hnae3_handle *handle)
5181 {
5182         if (!handle->ae_algo->ops->client_stop)
5183                 return;
5184
5185         handle->ae_algo->ops->client_stop(handle);
5186 }
5187
5188 static void hns3_info_show(struct hns3_nic_priv *priv)
5189 {
5190         struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
5191         char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
5192
5193         hnae3_format_mac_addr(format_mac_addr, priv->netdev->dev_addr);
5194         dev_info(priv->dev, "MAC address: %s\n", format_mac_addr);
5195         dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps);
5196         dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size);
5197         dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size);
5198         dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len);
5199         dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc);
5200         dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc);
5201         dev_info(priv->dev, "Total number of enabled TCs: %u\n",
5202                  kinfo->tc_info.num_tc);
5203         dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu);
5204 }
5205
5206 static void hns3_set_cq_period_mode(struct hns3_nic_priv *priv,
5207                                     enum dim_cq_period_mode mode, bool is_tx)
5208 {
5209         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
5210         struct hnae3_handle *handle = priv->ae_handle;
5211         int i;
5212
5213         if (is_tx) {
5214                 priv->tx_cqe_mode = mode;
5215
5216                 for (i = 0; i < priv->vector_num; i++)
5217                         priv->tqp_vector[i].tx_group.dim.mode = mode;
5218         } else {
5219                 priv->rx_cqe_mode = mode;
5220
5221                 for (i = 0; i < priv->vector_num; i++)
5222                         priv->tqp_vector[i].rx_group.dim.mode = mode;
5223         }
5224
5225         if (hnae3_ae_dev_cq_supported(ae_dev)) {
5226                 u32 new_mode;
5227                 u64 reg;
5228
5229                 new_mode = (mode == DIM_CQ_PERIOD_MODE_START_FROM_CQE) ?
5230                         HNS3_CQ_MODE_CQE : HNS3_CQ_MODE_EQE;
5231                 reg = is_tx ? HNS3_GL1_CQ_MODE_REG : HNS3_GL0_CQ_MODE_REG;
5232
5233                 writel(new_mode, handle->kinfo.io_base + reg);
5234         }
5235 }
5236
5237 void hns3_cq_period_mode_init(struct hns3_nic_priv *priv,
5238                               enum dim_cq_period_mode tx_mode,
5239                               enum dim_cq_period_mode rx_mode)
5240 {
5241         hns3_set_cq_period_mode(priv, tx_mode, true);
5242         hns3_set_cq_period_mode(priv, rx_mode, false);
5243 }
5244
5245 static void hns3_state_init(struct hnae3_handle *handle)
5246 {
5247         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
5248         struct net_device *netdev = handle->kinfo.netdev;
5249         struct hns3_nic_priv *priv = netdev_priv(netdev);
5250
5251         set_bit(HNS3_NIC_STATE_INITED, &priv->state);
5252
5253         if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps))
5254                 set_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state);
5255
5256         if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
5257                 set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->supported_pflags);
5258
5259         if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
5260                 set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state);
5261
5262         if (hnae3_ae_dev_rxd_adv_layout_supported(ae_dev))
5263                 set_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state);
5264 }
5265
5266 static void hns3_state_uninit(struct hnae3_handle *handle)
5267 {
5268         struct hns3_nic_priv *priv  = handle->priv;
5269
5270         clear_bit(HNS3_NIC_STATE_INITED, &priv->state);
5271 }
5272
5273 static int hns3_client_init(struct hnae3_handle *handle)
5274 {
5275         struct pci_dev *pdev = handle->pdev;
5276         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
5277         u16 alloc_tqps, max_rss_size;
5278         struct hns3_nic_priv *priv;
5279         struct net_device *netdev;
5280         int ret;
5281
5282         handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
5283                                                     &max_rss_size);
5284         netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
5285         if (!netdev)
5286                 return -ENOMEM;
5287
5288         priv = netdev_priv(netdev);
5289         priv->dev = &pdev->dev;
5290         priv->netdev = netdev;
5291         priv->ae_handle = handle;
5292         priv->tx_timeout_count = 0;
5293         priv->max_non_tso_bd_num = ae_dev->dev_specs.max_non_tso_bd_num;
5294         set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
5295
5296         handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL);
5297
5298         handle->kinfo.netdev = netdev;
5299         handle->priv = (void *)priv;
5300
5301         hns3_init_mac_addr(netdev);
5302
5303         hns3_set_default_feature(netdev);
5304
5305         netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
5306         netdev->priv_flags |= IFF_UNICAST_FLT;
5307         netdev->netdev_ops = &hns3_nic_netdev_ops;
5308         SET_NETDEV_DEV(netdev, &pdev->dev);
5309         hns3_ethtool_set_ops(netdev);
5310
5311         /* Carrier off reporting is important to ethtool even BEFORE open */
5312         netif_carrier_off(netdev);
5313
5314         ret = hns3_get_ring_config(priv);
5315         if (ret) {
5316                 ret = -ENOMEM;
5317                 goto out_get_ring_cfg;
5318         }
5319
5320         hns3_nic_init_coal_cfg(priv);
5321
5322         ret = hns3_nic_alloc_vector_data(priv);
5323         if (ret) {
5324                 ret = -ENOMEM;
5325                 goto out_alloc_vector_data;
5326         }
5327
5328         ret = hns3_nic_init_vector_data(priv);
5329         if (ret) {
5330                 ret = -ENOMEM;
5331                 goto out_init_vector_data;
5332         }
5333
5334         ret = hns3_init_all_ring(priv);
5335         if (ret) {
5336                 ret = -ENOMEM;
5337                 goto out_init_ring;
5338         }
5339
5340         hns3_cq_period_mode_init(priv, DIM_CQ_PERIOD_MODE_START_FROM_EQE,
5341                                  DIM_CQ_PERIOD_MODE_START_FROM_EQE);
5342
5343         ret = hns3_init_phy(netdev);
5344         if (ret)
5345                 goto out_init_phy;
5346
5347         /* the device can work without cpu rmap, only aRFS needs it */
5348         ret = hns3_set_rx_cpu_rmap(netdev);
5349         if (ret)
5350                 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
5351
5352         ret = hns3_nic_init_irq(priv);
5353         if (ret) {
5354                 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
5355                 hns3_free_rx_cpu_rmap(netdev);
5356                 goto out_init_irq_fail;
5357         }
5358
5359         ret = hns3_client_start(handle);
5360         if (ret) {
5361                 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
5362                 goto out_client_start;
5363         }
5364
5365         hns3_dcbnl_setup(handle);
5366
5367         ret = hns3_dbg_init(handle);
5368         if (ret) {
5369                 dev_err(priv->dev, "failed to init debugfs, ret = %d\n",
5370                         ret);
5371                 goto out_client_start;
5372         }
5373
5374         netdev->max_mtu = HNS3_MAX_MTU(ae_dev->dev_specs.max_frm_size);
5375
5376         hns3_state_init(handle);
5377
5378         ret = register_netdev(netdev);
5379         if (ret) {
5380                 dev_err(priv->dev, "probe register netdev fail!\n");
5381                 goto out_reg_netdev_fail;
5382         }
5383
5384         if (netif_msg_drv(handle))
5385                 hns3_info_show(priv);
5386
5387         return ret;
5388
5389 out_reg_netdev_fail:
5390         hns3_state_uninit(handle);
5391         hns3_dbg_uninit(handle);
5392         hns3_client_stop(handle);
5393 out_client_start:
5394         hns3_free_rx_cpu_rmap(netdev);
5395         hns3_nic_uninit_irq(priv);
5396 out_init_irq_fail:
5397         hns3_uninit_phy(netdev);
5398 out_init_phy:
5399         hns3_uninit_all_ring(priv);
5400 out_init_ring:
5401         hns3_nic_uninit_vector_data(priv);
5402 out_init_vector_data:
5403         hns3_nic_dealloc_vector_data(priv);
5404 out_alloc_vector_data:
5405         priv->ring = NULL;
5406 out_get_ring_cfg:
5407         priv->ae_handle = NULL;
5408         free_netdev(netdev);
5409         return ret;
5410 }
5411
5412 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
5413 {
5414         struct net_device *netdev = handle->kinfo.netdev;
5415         struct hns3_nic_priv *priv = netdev_priv(netdev);
5416
5417         if (netdev->reg_state != NETREG_UNINITIALIZED)
5418                 unregister_netdev(netdev);
5419
5420         hns3_client_stop(handle);
5421
5422         hns3_uninit_phy(netdev);
5423
5424         if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5425                 netdev_warn(netdev, "already uninitialized\n");
5426                 goto out_netdev_free;
5427         }
5428
5429         hns3_free_rx_cpu_rmap(netdev);
5430
5431         hns3_nic_uninit_irq(priv);
5432
5433         hns3_clear_all_ring(handle, true);
5434
5435         hns3_nic_uninit_vector_data(priv);
5436
5437         hns3_nic_dealloc_vector_data(priv);
5438
5439         hns3_uninit_all_ring(priv);
5440
5441         hns3_put_ring_config(priv);
5442
5443 out_netdev_free:
5444         hns3_dbg_uninit(handle);
5445         free_netdev(netdev);
5446 }
5447
5448 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
5449 {
5450         struct net_device *netdev = handle->kinfo.netdev;
5451
5452         if (!netdev)
5453                 return;
5454
5455         if (linkup) {
5456                 netif_tx_wake_all_queues(netdev);
5457                 netif_carrier_on(netdev);
5458                 if (netif_msg_link(handle))
5459                         netdev_info(netdev, "link up\n");
5460         } else {
5461                 netif_carrier_off(netdev);
5462                 netif_tx_stop_all_queues(netdev);
5463                 if (netif_msg_link(handle))
5464                         netdev_info(netdev, "link down\n");
5465         }
5466 }
5467
5468 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
5469 {
5470         while (ring->next_to_clean != ring->next_to_use) {
5471                 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
5472                 hns3_free_buffer_detach(ring, ring->next_to_clean, 0);
5473                 ring_ptr_move_fw(ring, next_to_clean);
5474         }
5475
5476         ring->pending_buf = 0;
5477 }
5478
5479 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
5480 {
5481         struct hns3_desc_cb res_cbs;
5482         int ret;
5483
5484         while (ring->next_to_use != ring->next_to_clean) {
5485                 /* When a buffer is not reused, it's memory has been
5486                  * freed in hns3_handle_rx_bd or will be freed by
5487                  * stack, so we need to replace the buffer here.
5488                  */
5489                 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
5490                         ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
5491                         if (ret) {
5492                                 hns3_ring_stats_update(ring, sw_err_cnt);
5493                                 /* if alloc new buffer fail, exit directly
5494                                  * and reclear in up flow.
5495                                  */
5496                                 netdev_warn(ring_to_netdev(ring),
5497                                             "reserve buffer map failed, ret = %d\n",
5498                                             ret);
5499                                 return ret;
5500                         }
5501                         hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
5502                 }
5503                 ring_ptr_move_fw(ring, next_to_use);
5504         }
5505
5506         /* Free the pending skb in rx ring */
5507         if (ring->skb) {
5508                 dev_kfree_skb_any(ring->skb);
5509                 ring->skb = NULL;
5510                 ring->pending_buf = 0;
5511         }
5512
5513         return 0;
5514 }
5515
5516 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
5517 {
5518         while (ring->next_to_use != ring->next_to_clean) {
5519                 /* When a buffer is not reused, it's memory has been
5520                  * freed in hns3_handle_rx_bd or will be freed by
5521                  * stack, so only need to unmap the buffer here.
5522                  */
5523                 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
5524                         hns3_unmap_buffer(ring,
5525                                           &ring->desc_cb[ring->next_to_use]);
5526                         ring->desc_cb[ring->next_to_use].dma = 0;
5527                 }
5528
5529                 ring_ptr_move_fw(ring, next_to_use);
5530         }
5531 }
5532
5533 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force)
5534 {
5535         struct net_device *ndev = h->kinfo.netdev;
5536         struct hns3_nic_priv *priv = netdev_priv(ndev);
5537         u32 i;
5538
5539         for (i = 0; i < h->kinfo.num_tqps; i++) {
5540                 struct hns3_enet_ring *ring;
5541
5542                 ring = &priv->ring[i];
5543                 hns3_clear_tx_ring(ring);
5544
5545                 ring = &priv->ring[i + h->kinfo.num_tqps];
5546                 /* Continue to clear other rings even if clearing some
5547                  * rings failed.
5548                  */
5549                 if (force)
5550                         hns3_force_clear_rx_ring(ring);
5551                 else
5552                         hns3_clear_rx_ring(ring);
5553         }
5554 }
5555
5556 int hns3_nic_reset_all_ring(struct hnae3_handle *h)
5557 {
5558         struct net_device *ndev = h->kinfo.netdev;
5559         struct hns3_nic_priv *priv = netdev_priv(ndev);
5560         struct hns3_enet_ring *rx_ring;
5561         int i, j;
5562         int ret;
5563
5564         ret = h->ae_algo->ops->reset_queue(h);
5565         if (ret)
5566                 return ret;
5567
5568         for (i = 0; i < h->kinfo.num_tqps; i++) {
5569                 hns3_init_ring_hw(&priv->ring[i]);
5570
5571                 /* We need to clear tx ring here because self test will
5572                  * use the ring and will not run down before up
5573                  */
5574                 hns3_clear_tx_ring(&priv->ring[i]);
5575                 priv->ring[i].next_to_clean = 0;
5576                 priv->ring[i].next_to_use = 0;
5577                 priv->ring[i].last_to_use = 0;
5578
5579                 rx_ring = &priv->ring[i + h->kinfo.num_tqps];
5580                 hns3_init_ring_hw(rx_ring);
5581                 ret = hns3_clear_rx_ring(rx_ring);
5582                 if (ret)
5583                         return ret;
5584
5585                 /* We can not know the hardware head and tail when this
5586                  * function is called in reset flow, so we reuse all desc.
5587                  */
5588                 for (j = 0; j < rx_ring->desc_num; j++)
5589                         hns3_reuse_buffer(rx_ring, j);
5590
5591                 rx_ring->next_to_clean = 0;
5592                 rx_ring->next_to_use = 0;
5593         }
5594
5595         hns3_init_tx_ring_tc(priv);
5596
5597         return 0;
5598 }
5599
5600 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
5601 {
5602         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5603         struct net_device *ndev = kinfo->netdev;
5604         struct hns3_nic_priv *priv = netdev_priv(ndev);
5605
5606         if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
5607                 return 0;
5608
5609         if (!netif_running(ndev))
5610                 return 0;
5611
5612         return hns3_nic_net_stop(ndev);
5613 }
5614
5615 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
5616 {
5617         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5618         struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
5619         int ret = 0;
5620
5621         if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5622                 netdev_err(kinfo->netdev, "device is not initialized yet\n");
5623                 return -EFAULT;
5624         }
5625
5626         clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
5627
5628         if (netif_running(kinfo->netdev)) {
5629                 ret = hns3_nic_net_open(kinfo->netdev);
5630                 if (ret) {
5631                         set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
5632                         netdev_err(kinfo->netdev,
5633                                    "net up fail, ret=%d!\n", ret);
5634                         return ret;
5635                 }
5636         }
5637
5638         return ret;
5639 }
5640
5641 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
5642 {
5643         struct net_device *netdev = handle->kinfo.netdev;
5644         struct hns3_nic_priv *priv = netdev_priv(netdev);
5645         int ret;
5646
5647         /* Carrier off reporting is important to ethtool even BEFORE open */
5648         netif_carrier_off(netdev);
5649
5650         ret = hns3_get_ring_config(priv);
5651         if (ret)
5652                 return ret;
5653
5654         ret = hns3_nic_alloc_vector_data(priv);
5655         if (ret)
5656                 goto err_put_ring;
5657
5658         ret = hns3_nic_init_vector_data(priv);
5659         if (ret)
5660                 goto err_dealloc_vector;
5661
5662         ret = hns3_init_all_ring(priv);
5663         if (ret)
5664                 goto err_uninit_vector;
5665
5666         hns3_cq_period_mode_init(priv, priv->tx_cqe_mode, priv->rx_cqe_mode);
5667
5668         /* the device can work without cpu rmap, only aRFS needs it */
5669         ret = hns3_set_rx_cpu_rmap(netdev);
5670         if (ret)
5671                 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
5672
5673         ret = hns3_nic_init_irq(priv);
5674         if (ret) {
5675                 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
5676                 hns3_free_rx_cpu_rmap(netdev);
5677                 goto err_init_irq_fail;
5678         }
5679
5680         if (!hns3_is_phys_func(handle->pdev))
5681                 hns3_init_mac_addr(netdev);
5682
5683         ret = hns3_client_start(handle);
5684         if (ret) {
5685                 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
5686                 goto err_client_start_fail;
5687         }
5688
5689         set_bit(HNS3_NIC_STATE_INITED, &priv->state);
5690
5691         return ret;
5692
5693 err_client_start_fail:
5694         hns3_free_rx_cpu_rmap(netdev);
5695         hns3_nic_uninit_irq(priv);
5696 err_init_irq_fail:
5697         hns3_uninit_all_ring(priv);
5698 err_uninit_vector:
5699         hns3_nic_uninit_vector_data(priv);
5700 err_dealloc_vector:
5701         hns3_nic_dealloc_vector_data(priv);
5702 err_put_ring:
5703         hns3_put_ring_config(priv);
5704
5705         return ret;
5706 }
5707
5708 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
5709 {
5710         struct net_device *netdev = handle->kinfo.netdev;
5711         struct hns3_nic_priv *priv = netdev_priv(netdev);
5712
5713         if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5714                 netdev_warn(netdev, "already uninitialized\n");
5715                 return 0;
5716         }
5717
5718         hns3_free_rx_cpu_rmap(netdev);
5719         hns3_nic_uninit_irq(priv);
5720         hns3_clear_all_ring(handle, true);
5721         hns3_reset_tx_queue(priv->ae_handle);
5722
5723         hns3_nic_uninit_vector_data(priv);
5724
5725         hns3_nic_dealloc_vector_data(priv);
5726
5727         hns3_uninit_all_ring(priv);
5728
5729         hns3_put_ring_config(priv);
5730
5731         return 0;
5732 }
5733
5734 int hns3_reset_notify(struct hnae3_handle *handle,
5735                       enum hnae3_reset_notify_type type)
5736 {
5737         int ret = 0;
5738
5739         switch (type) {
5740         case HNAE3_UP_CLIENT:
5741                 ret = hns3_reset_notify_up_enet(handle);
5742                 break;
5743         case HNAE3_DOWN_CLIENT:
5744                 ret = hns3_reset_notify_down_enet(handle);
5745                 break;
5746         case HNAE3_INIT_CLIENT:
5747                 ret = hns3_reset_notify_init_enet(handle);
5748                 break;
5749         case HNAE3_UNINIT_CLIENT:
5750                 ret = hns3_reset_notify_uninit_enet(handle);
5751                 break;
5752         default:
5753                 break;
5754         }
5755
5756         return ret;
5757 }
5758
5759 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num,
5760                                 bool rxfh_configured)
5761 {
5762         int ret;
5763
5764         ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num,
5765                                                  rxfh_configured);
5766         if (ret) {
5767                 dev_err(&handle->pdev->dev,
5768                         "Change tqp num(%u) fail.\n", new_tqp_num);
5769                 return ret;
5770         }
5771
5772         ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT);
5773         if (ret)
5774                 return ret;
5775
5776         ret =  hns3_reset_notify(handle, HNAE3_UP_CLIENT);
5777         if (ret)
5778                 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT);
5779
5780         return ret;
5781 }
5782
5783 int hns3_set_channels(struct net_device *netdev,
5784                       struct ethtool_channels *ch)
5785 {
5786         struct hnae3_handle *h = hns3_get_handle(netdev);
5787         struct hnae3_knic_private_info *kinfo = &h->kinfo;
5788         bool rxfh_configured = netif_is_rxfh_configured(netdev);
5789         u32 new_tqp_num = ch->combined_count;
5790         u16 org_tqp_num;
5791         int ret;
5792
5793         if (hns3_nic_resetting(netdev))
5794                 return -EBUSY;
5795
5796         if (ch->rx_count || ch->tx_count)
5797                 return -EINVAL;
5798
5799         if (kinfo->tc_info.mqprio_active) {
5800                 dev_err(&netdev->dev,
5801                         "it's not allowed to set channels via ethtool when MQPRIO mode is on\n");
5802                 return -EINVAL;
5803         }
5804
5805         if (new_tqp_num > hns3_get_max_available_channels(h) ||
5806             new_tqp_num < 1) {
5807                 dev_err(&netdev->dev,
5808                         "Change tqps fail, the tqp range is from 1 to %u",
5809                         hns3_get_max_available_channels(h));
5810                 return -EINVAL;
5811         }
5812
5813         if (kinfo->rss_size == new_tqp_num)
5814                 return 0;
5815
5816         netif_dbg(h, drv, netdev,
5817                   "set channels: tqp_num=%u, rxfh=%d\n",
5818                   new_tqp_num, rxfh_configured);
5819
5820         ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
5821         if (ret)
5822                 return ret;
5823
5824         ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
5825         if (ret)
5826                 return ret;
5827
5828         org_tqp_num = h->kinfo.num_tqps;
5829         ret = hns3_change_channels(h, new_tqp_num, rxfh_configured);
5830         if (ret) {
5831                 int ret1;
5832
5833                 netdev_warn(netdev,
5834                             "Change channels fail, revert to old value\n");
5835                 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured);
5836                 if (ret1) {
5837                         netdev_err(netdev,
5838                                    "revert to old channel fail\n");
5839                         return ret1;
5840                 }
5841
5842                 return ret;
5843         }
5844
5845         return 0;
5846 }
5847
5848 void hns3_external_lb_prepare(struct net_device *ndev, bool if_running)
5849 {
5850         struct hns3_nic_priv *priv = netdev_priv(ndev);
5851         struct hnae3_handle *h = priv->ae_handle;
5852         int i;
5853
5854         if (!if_running)
5855                 return;
5856
5857         netif_carrier_off(ndev);
5858         netif_tx_disable(ndev);
5859
5860         for (i = 0; i < priv->vector_num; i++)
5861                 hns3_vector_disable(&priv->tqp_vector[i]);
5862
5863         for (i = 0; i < h->kinfo.num_tqps; i++)
5864                 hns3_tqp_disable(h->kinfo.tqp[i]);
5865
5866         /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
5867          * during reset process, because driver may not be able
5868          * to disable the ring through firmware when downing the netdev.
5869          */
5870         if (!hns3_nic_resetting(ndev))
5871                 hns3_nic_reset_all_ring(priv->ae_handle);
5872
5873         hns3_reset_tx_queue(priv->ae_handle);
5874 }
5875
5876 void hns3_external_lb_restore(struct net_device *ndev, bool if_running)
5877 {
5878         struct hns3_nic_priv *priv = netdev_priv(ndev);
5879         struct hnae3_handle *h = priv->ae_handle;
5880         int i;
5881
5882         if (!if_running)
5883                 return;
5884
5885         hns3_nic_reset_all_ring(priv->ae_handle);
5886
5887         for (i = 0; i < priv->vector_num; i++)
5888                 hns3_vector_enable(&priv->tqp_vector[i]);
5889
5890         for (i = 0; i < h->kinfo.num_tqps; i++)
5891                 hns3_tqp_enable(h->kinfo.tqp[i]);
5892
5893         netif_tx_wake_all_queues(ndev);
5894
5895         if (h->ae_algo->ops->get_status(h))
5896                 netif_carrier_on(ndev);
5897 }
5898
5899 static const struct hns3_hw_error_info hns3_hw_err[] = {
5900         { .type = HNAE3_PPU_POISON_ERROR,
5901           .msg = "PPU poison" },
5902         { .type = HNAE3_CMDQ_ECC_ERROR,
5903           .msg = "IMP CMDQ error" },
5904         { .type = HNAE3_IMP_RD_POISON_ERROR,
5905           .msg = "IMP RD poison" },
5906         { .type = HNAE3_ROCEE_AXI_RESP_ERROR,
5907           .msg = "ROCEE AXI RESP error" },
5908 };
5909
5910 static void hns3_process_hw_error(struct hnae3_handle *handle,
5911                                   enum hnae3_hw_error_type type)
5912 {
5913         int i;
5914
5915         for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) {
5916                 if (hns3_hw_err[i].type == type) {
5917                         dev_err(&handle->pdev->dev, "Detected %s!\n",
5918                                 hns3_hw_err[i].msg);
5919                         break;
5920                 }
5921         }
5922 }
5923
5924 static const struct hnae3_client_ops client_ops = {
5925         .init_instance = hns3_client_init,
5926         .uninit_instance = hns3_client_uninit,
5927         .link_status_change = hns3_link_status_change,
5928         .reset_notify = hns3_reset_notify,
5929         .process_hw_error = hns3_process_hw_error,
5930 };
5931
5932 /* hns3_init_module - Driver registration routine
5933  * hns3_init_module is the first routine called when the driver is
5934  * loaded. All it does is register with the PCI subsystem.
5935  */
5936 static int __init hns3_init_module(void)
5937 {
5938         int ret;
5939
5940         pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
5941         pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
5942
5943         client.type = HNAE3_CLIENT_KNIC;
5944         snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s",
5945                  hns3_driver_name);
5946
5947         client.ops = &client_ops;
5948
5949         INIT_LIST_HEAD(&client.node);
5950
5951         hns3_dbg_register_debugfs(hns3_driver_name);
5952
5953         ret = hnae3_register_client(&client);
5954         if (ret)
5955                 goto err_reg_client;
5956
5957         ret = pci_register_driver(&hns3_driver);
5958         if (ret)
5959                 goto err_reg_driver;
5960
5961         return ret;
5962
5963 err_reg_driver:
5964         hnae3_unregister_client(&client);
5965 err_reg_client:
5966         hns3_dbg_unregister_debugfs();
5967         return ret;
5968 }
5969 module_init(hns3_init_module);
5970
5971 /* hns3_exit_module - Driver exit cleanup routine
5972  * hns3_exit_module is called just before the driver is removed
5973  * from memory.
5974  */
5975 static void __exit hns3_exit_module(void)
5976 {
5977         pci_unregister_driver(&hns3_driver);
5978         hnae3_unregister_client(&client);
5979         hns3_dbg_unregister_debugfs();
5980 }
5981 module_exit(hns3_exit_module);
5982
5983 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
5984 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
5985 MODULE_LICENSE("GPL");
5986 MODULE_ALIAS("pci:hns-nic");