1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
4 #include <linux/dma-mapping.h>
5 #include <linux/etherdevice.h>
6 #include <linux/interrupt.h>
7 #ifdef CONFIG_RFS_ACCEL
8 #include <linux/cpu_rmap.h>
10 #include <linux/if_vlan.h>
12 #include <linux/ipv6.h>
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/aer.h>
16 #include <linux/skbuff.h>
17 #include <linux/sctp.h>
18 #include <linux/vermagic.h>
20 #include <net/ip6_checksum.h>
21 #include <net/pkt_cls.h>
23 #include <net/vxlan.h>
26 #include "hns3_enet.h"
28 #define hns3_set_field(origin, shift, val) ((origin) |= ((val) << (shift)))
29 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
31 #define hns3_rl_err(fmt, ...) \
33 if (net_ratelimit()) \
34 netdev_err(fmt, ##__VA_ARGS__); \
37 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force);
38 static void hns3_remove_hw_addr(struct net_device *netdev);
40 static const char hns3_driver_name[] = "hns3";
41 const char hns3_driver_version[] = VERMAGIC_STRING;
42 static const char hns3_driver_string[] =
43 "Hisilicon Ethernet Network Driver for Hip08 Family";
44 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
45 static struct hnae3_client client;
47 static int debug = -1;
48 module_param(debug, int, 0);
49 MODULE_PARM_DESC(debug, " Network interface message level setting");
51 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
52 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
54 #define HNS3_INNER_VLAN_TAG 1
55 #define HNS3_OUTER_VLAN_TAG 2
57 /* hns3_pci_tbl - PCI Device ID Table
59 * Last entry must be all 0s
61 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
62 * Class, Class Mask, private data (not used) }
64 static const struct pci_device_id hns3_pci_tbl[] = {
65 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
66 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
67 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
68 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
69 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
70 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
71 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
72 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
73 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
74 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
75 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
76 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
77 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
78 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
79 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
80 /* required last entry */
83 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
85 static irqreturn_t hns3_irq_handle(int irq, void *vector)
87 struct hns3_enet_tqp_vector *tqp_vector = vector;
89 napi_schedule_irqoff(&tqp_vector->napi);
94 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
96 struct hns3_enet_tqp_vector *tqp_vectors;
99 for (i = 0; i < priv->vector_num; i++) {
100 tqp_vectors = &priv->tqp_vector[i];
102 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
105 /* clear the affinity mask */
106 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
108 /* release the irq resource */
109 free_irq(tqp_vectors->vector_irq, tqp_vectors);
110 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
114 static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
116 struct hns3_enet_tqp_vector *tqp_vectors;
117 int txrx_int_idx = 0;
123 for (i = 0; i < priv->vector_num; i++) {
124 tqp_vectors = &priv->tqp_vector[i];
126 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
129 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
130 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
131 "%s-%s-%d", priv->netdev->name, "TxRx",
134 } else if (tqp_vectors->rx_group.ring) {
135 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
136 "%s-%s-%d", priv->netdev->name, "Rx",
138 } else if (tqp_vectors->tx_group.ring) {
139 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
140 "%s-%s-%d", priv->netdev->name, "Tx",
143 /* Skip this unused q_vector */
147 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
149 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
150 tqp_vectors->name, tqp_vectors);
152 netdev_err(priv->netdev, "request irq(%d) fail\n",
153 tqp_vectors->vector_irq);
154 hns3_nic_uninit_irq(priv);
158 irq_set_affinity_hint(tqp_vectors->vector_irq,
159 &tqp_vectors->affinity_mask);
161 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
167 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
170 writel(mask_en, tqp_vector->mask_addr);
173 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
175 napi_enable(&tqp_vector->napi);
178 hns3_mask_vector_irq(tqp_vector, 1);
181 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
184 hns3_mask_vector_irq(tqp_vector, 0);
186 disable_irq(tqp_vector->vector_irq);
187 napi_disable(&tqp_vector->napi);
190 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
193 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
195 /* this defines the configuration for RL (Interrupt Rate Limiter).
196 * Rl defines rate of interrupts i.e. number of interrupts-per-second
197 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
200 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
201 !tqp_vector->rx_group.coal.gl_adapt_enable)
202 /* According to the hardware, the range of rl_reg is
203 * 0-59 and the unit is 4.
205 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
207 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
210 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
213 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);
215 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
218 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
221 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);
223 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
226 static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
227 struct hns3_nic_priv *priv)
229 /* initialize the configuration for interrupt coalescing.
230 * 1. GL (Interrupt Gap Limiter)
231 * 2. RL (Interrupt Rate Limiter)
233 * Default: enable interrupt coalescing self-adaptive and GL
235 tqp_vector->tx_group.coal.gl_adapt_enable = 1;
236 tqp_vector->rx_group.coal.gl_adapt_enable = 1;
238 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;
239 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;
241 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;
242 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;
245 static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
246 struct hns3_nic_priv *priv)
248 struct hnae3_handle *h = priv->ae_handle;
250 hns3_set_vector_coalesce_tx_gl(tqp_vector,
251 tqp_vector->tx_group.coal.int_gl);
252 hns3_set_vector_coalesce_rx_gl(tqp_vector,
253 tqp_vector->rx_group.coal.int_gl);
254 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
257 static int hns3_nic_set_real_num_queue(struct net_device *netdev)
259 struct hnae3_handle *h = hns3_get_handle(netdev);
260 struct hnae3_knic_private_info *kinfo = &h->kinfo;
261 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc;
264 if (kinfo->num_tc <= 1) {
265 netdev_reset_tc(netdev);
267 ret = netdev_set_num_tc(netdev, kinfo->num_tc);
270 "netdev_set_num_tc fail, ret=%d!\n", ret);
274 for (i = 0; i < HNAE3_MAX_TC; i++) {
275 if (!kinfo->tc_info[i].enable)
278 netdev_set_tc_queue(netdev,
279 kinfo->tc_info[i].tc,
280 kinfo->tc_info[i].tqp_count,
281 kinfo->tc_info[i].tqp_offset);
285 ret = netif_set_real_num_tx_queues(netdev, queue_size);
288 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret);
292 ret = netif_set_real_num_rx_queues(netdev, queue_size);
295 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
302 static u16 hns3_get_max_available_channels(struct hnae3_handle *h)
304 u16 alloc_tqps, max_rss_size, rss_size;
306 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
307 rss_size = alloc_tqps / h->kinfo.num_tc;
309 return min_t(u16, rss_size, max_rss_size);
312 static void hns3_tqp_enable(struct hnae3_queue *tqp)
316 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
317 rcb_reg |= BIT(HNS3_RING_EN_B);
318 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
321 static void hns3_tqp_disable(struct hnae3_queue *tqp)
325 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
326 rcb_reg &= ~BIT(HNS3_RING_EN_B);
327 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
330 static void hns3_free_rx_cpu_rmap(struct net_device *netdev)
332 #ifdef CONFIG_RFS_ACCEL
333 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
334 netdev->rx_cpu_rmap = NULL;
338 static int hns3_set_rx_cpu_rmap(struct net_device *netdev)
340 #ifdef CONFIG_RFS_ACCEL
341 struct hns3_nic_priv *priv = netdev_priv(netdev);
342 struct hns3_enet_tqp_vector *tqp_vector;
345 if (!netdev->rx_cpu_rmap) {
346 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num);
347 if (!netdev->rx_cpu_rmap)
351 for (i = 0; i < priv->vector_num; i++) {
352 tqp_vector = &priv->tqp_vector[i];
353 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap,
354 tqp_vector->vector_irq);
356 hns3_free_rx_cpu_rmap(netdev);
364 static int hns3_nic_net_up(struct net_device *netdev)
366 struct hns3_nic_priv *priv = netdev_priv(netdev);
367 struct hnae3_handle *h = priv->ae_handle;
371 ret = hns3_nic_reset_all_ring(h);
375 /* the device can work without cpu rmap, only aRFS needs it */
376 ret = hns3_set_rx_cpu_rmap(netdev);
378 netdev_warn(netdev, "set rx cpu rmap fail, ret=%d!\n", ret);
380 /* get irq resource for all vectors */
381 ret = hns3_nic_init_irq(priv);
383 netdev_err(netdev, "init irq failed! ret=%d\n", ret);
387 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
389 /* enable the vectors */
390 for (i = 0; i < priv->vector_num; i++)
391 hns3_vector_enable(&priv->tqp_vector[i]);
394 for (j = 0; j < h->kinfo.num_tqps; j++)
395 hns3_tqp_enable(h->kinfo.tqp[j]);
397 /* start the ae_dev */
398 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
405 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
407 hns3_tqp_disable(h->kinfo.tqp[j]);
409 for (j = i - 1; j >= 0; j--)
410 hns3_vector_disable(&priv->tqp_vector[j]);
412 hns3_nic_uninit_irq(priv);
414 hns3_free_rx_cpu_rmap(netdev);
418 static void hns3_config_xps(struct hns3_nic_priv *priv)
422 for (i = 0; i < priv->vector_num; i++) {
423 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
424 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
429 ret = netif_set_xps_queue(priv->netdev,
430 &tqp_vector->affinity_mask,
431 ring->tqp->tqp_index);
433 netdev_warn(priv->netdev,
434 "set xps queue failed: %d", ret);
441 static int hns3_nic_net_open(struct net_device *netdev)
443 struct hns3_nic_priv *priv = netdev_priv(netdev);
444 struct hnae3_handle *h = hns3_get_handle(netdev);
445 struct hnae3_knic_private_info *kinfo;
448 if (hns3_nic_resetting(netdev))
451 netif_carrier_off(netdev);
453 ret = hns3_nic_set_real_num_queue(netdev);
457 ret = hns3_nic_net_up(netdev);
459 netdev_err(netdev, "net up fail, ret=%d!\n", ret);
464 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
465 netdev_set_prio_tc_map(netdev, i, kinfo->prio_tc[i]);
467 if (h->ae_algo->ops->set_timer_task)
468 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
470 hns3_config_xps(priv);
472 netif_dbg(h, drv, netdev, "net open\n");
477 static void hns3_reset_tx_queue(struct hnae3_handle *h)
479 struct net_device *ndev = h->kinfo.netdev;
480 struct hns3_nic_priv *priv = netdev_priv(ndev);
481 struct netdev_queue *dev_queue;
484 for (i = 0; i < h->kinfo.num_tqps; i++) {
485 dev_queue = netdev_get_tx_queue(ndev,
486 priv->ring_data[i].queue_index);
487 netdev_tx_reset_queue(dev_queue);
491 static void hns3_nic_net_down(struct net_device *netdev)
493 struct hns3_nic_priv *priv = netdev_priv(netdev);
494 struct hnae3_handle *h = hns3_get_handle(netdev);
495 const struct hnae3_ae_ops *ops;
498 /* disable vectors */
499 for (i = 0; i < priv->vector_num; i++)
500 hns3_vector_disable(&priv->tqp_vector[i]);
503 for (i = 0; i < h->kinfo.num_tqps; i++)
504 hns3_tqp_disable(h->kinfo.tqp[i]);
507 ops = priv->ae_handle->ae_algo->ops;
509 ops->stop(priv->ae_handle);
511 hns3_free_rx_cpu_rmap(netdev);
513 /* free irq resources */
514 hns3_nic_uninit_irq(priv);
516 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
517 * during reset process, because driver may not be able
518 * to disable the ring through firmware when downing the netdev.
520 if (!hns3_nic_resetting(netdev))
521 hns3_clear_all_ring(priv->ae_handle, false);
523 hns3_reset_tx_queue(priv->ae_handle);
526 static int hns3_nic_net_stop(struct net_device *netdev)
528 struct hns3_nic_priv *priv = netdev_priv(netdev);
529 struct hnae3_handle *h = hns3_get_handle(netdev);
531 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
534 netif_dbg(h, drv, netdev, "net stop\n");
536 if (h->ae_algo->ops->set_timer_task)
537 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
539 netif_tx_stop_all_queues(netdev);
540 netif_carrier_off(netdev);
542 hns3_nic_net_down(netdev);
547 static int hns3_nic_uc_sync(struct net_device *netdev,
548 const unsigned char *addr)
550 struct hnae3_handle *h = hns3_get_handle(netdev);
552 if (h->ae_algo->ops->add_uc_addr)
553 return h->ae_algo->ops->add_uc_addr(h, addr);
558 static int hns3_nic_uc_unsync(struct net_device *netdev,
559 const unsigned char *addr)
561 struct hnae3_handle *h = hns3_get_handle(netdev);
563 if (h->ae_algo->ops->rm_uc_addr)
564 return h->ae_algo->ops->rm_uc_addr(h, addr);
569 static int hns3_nic_mc_sync(struct net_device *netdev,
570 const unsigned char *addr)
572 struct hnae3_handle *h = hns3_get_handle(netdev);
574 if (h->ae_algo->ops->add_mc_addr)
575 return h->ae_algo->ops->add_mc_addr(h, addr);
580 static int hns3_nic_mc_unsync(struct net_device *netdev,
581 const unsigned char *addr)
583 struct hnae3_handle *h = hns3_get_handle(netdev);
585 if (h->ae_algo->ops->rm_mc_addr)
586 return h->ae_algo->ops->rm_mc_addr(h, addr);
591 static u8 hns3_get_netdev_flags(struct net_device *netdev)
595 if (netdev->flags & IFF_PROMISC) {
596 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
598 flags |= HNAE3_VLAN_FLTR;
599 if (netdev->flags & IFF_ALLMULTI)
600 flags |= HNAE3_USER_MPE;
606 static void hns3_nic_set_rx_mode(struct net_device *netdev)
608 struct hnae3_handle *h = hns3_get_handle(netdev);
612 new_flags = hns3_get_netdev_flags(netdev);
614 ret = __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
616 netdev_err(netdev, "sync uc address fail\n");
618 new_flags |= HNAE3_OVERFLOW_UPE;
621 if (netdev->flags & IFF_MULTICAST) {
622 ret = __dev_mc_sync(netdev, hns3_nic_mc_sync,
625 netdev_err(netdev, "sync mc address fail\n");
627 new_flags |= HNAE3_OVERFLOW_MPE;
631 /* User mode Promisc mode enable and vlan filtering is disabled to
632 * let all packets in. MAC-VLAN Table overflow Promisc enabled and
633 * vlan fitering is enabled
635 hns3_enable_vlan_filter(netdev, new_flags & HNAE3_VLAN_FLTR);
636 h->netdev_flags = new_flags;
637 hns3_update_promisc_mode(netdev, new_flags);
640 int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags)
642 struct hns3_nic_priv *priv = netdev_priv(netdev);
643 struct hnae3_handle *h = priv->ae_handle;
645 if (h->ae_algo->ops->set_promisc_mode) {
646 return h->ae_algo->ops->set_promisc_mode(h,
647 promisc_flags & HNAE3_UPE,
648 promisc_flags & HNAE3_MPE);
654 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable)
656 struct hns3_nic_priv *priv = netdev_priv(netdev);
657 struct hnae3_handle *h = priv->ae_handle;
660 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) {
661 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false;
662 if (enable != last_state) {
665 enable ? "enable" : "disable");
666 h->ae_algo->ops->enable_vlan_filter(h, enable);
671 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
672 u16 *mss, u32 *type_cs_vlan_tso)
674 u32 l4_offset, hdr_len;
675 union l3_hdr_info l3;
676 union l4_hdr_info l4;
680 if (!skb_is_gso(skb))
683 ret = skb_cow_head(skb, 0);
684 if (unlikely(ret < 0))
687 l3.hdr = skb_network_header(skb);
688 l4.hdr = skb_transport_header(skb);
690 /* Software should clear the IPv4's checksum field when tso is
693 if (l3.v4->version == 4)
697 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
700 SKB_GSO_UDP_TUNNEL_CSUM)) {
701 if ((!(skb_shinfo(skb)->gso_type &
703 (skb_shinfo(skb)->gso_type &
704 SKB_GSO_UDP_TUNNEL_CSUM)) {
705 /* Software should clear the udp's checksum
706 * field when tso is needed.
710 /* reset l3&l4 pointers from outer to inner headers */
711 l3.hdr = skb_inner_network_header(skb);
712 l4.hdr = skb_inner_transport_header(skb);
714 /* Software should clear the IPv4's checksum field when
717 if (l3.v4->version == 4)
721 /* normal or tunnel packet */
722 l4_offset = l4.hdr - skb->data;
723 hdr_len = (l4.tcp->doff << 2) + l4_offset;
725 /* remove payload length from inner pseudo checksum when tso */
726 l4_paylen = skb->len - l4_offset;
727 csum_replace_by_diff(&l4.tcp->check,
728 (__force __wsum)htonl(l4_paylen));
730 /* find the txbd field values */
731 *paylen = skb->len - hdr_len;
732 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
734 /* get MSS for TSO */
735 *mss = skb_shinfo(skb)->gso_size;
740 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
743 union l3_hdr_info l3;
744 unsigned char *l4_hdr;
745 unsigned char *exthdr;
749 /* find outer header point */
750 l3.hdr = skb_network_header(skb);
751 l4_hdr = skb_transport_header(skb);
753 if (skb->protocol == htons(ETH_P_IPV6)) {
754 exthdr = l3.hdr + sizeof(*l3.v6);
755 l4_proto_tmp = l3.v6->nexthdr;
756 if (l4_hdr != exthdr)
757 ipv6_skip_exthdr(skb, exthdr - skb->data,
758 &l4_proto_tmp, &frag_off);
759 } else if (skb->protocol == htons(ETH_P_IP)) {
760 l4_proto_tmp = l3.v4->protocol;
765 *ol4_proto = l4_proto_tmp;
768 if (!skb->encapsulation) {
773 /* find inner header point */
774 l3.hdr = skb_inner_network_header(skb);
775 l4_hdr = skb_inner_transport_header(skb);
777 if (l3.v6->version == 6) {
778 exthdr = l3.hdr + sizeof(*l3.v6);
779 l4_proto_tmp = l3.v6->nexthdr;
780 if (l4_hdr != exthdr)
781 ipv6_skip_exthdr(skb, exthdr - skb->data,
782 &l4_proto_tmp, &frag_off);
783 } else if (l3.v4->version == 4) {
784 l4_proto_tmp = l3.v4->protocol;
787 *il4_proto = l4_proto_tmp;
792 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
793 * and it is udp packet, which has a dest port as the IANA assigned.
794 * the hardware is expected to do the checksum offload, but the
795 * hardware will not do the checksum offload when udp dest port is
798 static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
800 union l4_hdr_info l4;
802 l4.hdr = skb_transport_header(skb);
804 if (!(!skb->encapsulation &&
805 l4.udp->dest == htons(IANA_VXLAN_UDP_PORT)))
808 skb_checksum_help(skb);
813 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
814 u32 *ol_type_vlan_len_msec)
816 u32 l2_len, l3_len, l4_len;
817 unsigned char *il2_hdr;
818 union l3_hdr_info l3;
819 union l4_hdr_info l4;
821 l3.hdr = skb_network_header(skb);
822 l4.hdr = skb_transport_header(skb);
824 /* compute OL2 header size, defined in 2 Bytes */
825 l2_len = l3.hdr - skb->data;
826 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1);
828 /* compute OL3 header size, defined in 4 Bytes */
829 l3_len = l4.hdr - l3.hdr;
830 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2);
832 il2_hdr = skb_inner_mac_header(skb);
833 /* compute OL4 header size, defined in 4 Bytes */
834 l4_len = il2_hdr - l4.hdr;
835 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2);
837 /* define outer network header type */
838 if (skb->protocol == htons(ETH_P_IP)) {
840 hns3_set_field(*ol_type_vlan_len_msec,
842 HNS3_OL3T_IPV4_CSUM);
844 hns3_set_field(*ol_type_vlan_len_msec,
846 HNS3_OL3T_IPV4_NO_CSUM);
848 } else if (skb->protocol == htons(ETH_P_IPV6)) {
849 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S,
853 if (ol4_proto == IPPROTO_UDP)
854 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
855 HNS3_TUN_MAC_IN_UDP);
856 else if (ol4_proto == IPPROTO_GRE)
857 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
861 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
862 u8 il4_proto, u32 *type_cs_vlan_tso,
863 u32 *ol_type_vlan_len_msec)
865 unsigned char *l2_hdr = skb->data;
866 u32 l4_proto = ol4_proto;
867 union l4_hdr_info l4;
868 union l3_hdr_info l3;
871 l4.hdr = skb_transport_header(skb);
872 l3.hdr = skb_network_header(skb);
874 /* handle encapsulation skb */
875 if (skb->encapsulation) {
876 /* If this is a not UDP/GRE encapsulation skb */
877 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) {
878 /* drop the skb tunnel packet if hardware don't support,
879 * because hardware can't calculate csum when TSO.
884 /* the stack computes the IP header already,
885 * driver calculate l4 checksum when not TSO.
887 skb_checksum_help(skb);
891 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec);
893 /* switch to inner header */
894 l2_hdr = skb_inner_mac_header(skb);
895 l3.hdr = skb_inner_network_header(skb);
896 l4.hdr = skb_inner_transport_header(skb);
897 l4_proto = il4_proto;
900 if (l3.v4->version == 4) {
901 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
904 /* the stack computes the IP header already, the only time we
905 * need the hardware to recompute it is in the case of TSO.
908 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
909 } else if (l3.v6->version == 6) {
910 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
914 /* compute inner(/normal) L2 header size, defined in 2 Bytes */
915 l2_len = l3.hdr - l2_hdr;
916 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1);
918 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
919 l3_len = l4.hdr - l3.hdr;
920 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2);
922 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
925 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
926 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
928 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
932 if (hns3_tunnel_csum_bug(skb))
935 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
936 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
938 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
939 (sizeof(struct udphdr) >> 2));
942 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
943 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
945 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
946 (sizeof(struct sctphdr) >> 2));
949 /* drop the skb tunnel packet if hardware don't support,
950 * because hardware can't calculate csum when TSO.
955 /* the stack computes the IP header already,
956 * driver calculate l4 checksum when not TSO.
958 skb_checksum_help(skb);
965 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring,
968 struct hnae3_handle *handle = tx_ring->tqp->handle;
969 struct vlan_ethhdr *vhdr;
972 if (!(skb->protocol == htons(ETH_P_8021Q) ||
973 skb_vlan_tag_present(skb)))
976 /* Since HW limitation, if port based insert VLAN enabled, only one VLAN
977 * header is allowed in skb, otherwise it will cause RAS error.
979 if (unlikely(skb_vlan_tagged_multi(skb) &&
980 handle->port_base_vlan_state ==
981 HNAE3_PORT_BASE_VLAN_ENABLE))
984 if (skb->protocol == htons(ETH_P_8021Q) &&
985 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
986 /* When HW VLAN acceleration is turned off, and the stack
987 * sets the protocol to 802.1q, the driver just need to
988 * set the protocol to the encapsulated ethertype.
990 skb->protocol = vlan_get_protocol(skb);
994 if (skb_vlan_tag_present(skb)) {
995 /* Based on hw strategy, use out_vtag in two layer tag case,
996 * and use inner_vtag in one tag case.
998 if (skb->protocol == htons(ETH_P_8021Q) &&
999 handle->port_base_vlan_state ==
1000 HNAE3_PORT_BASE_VLAN_DISABLE)
1001 rc = HNS3_OUTER_VLAN_TAG;
1003 rc = HNS3_INNER_VLAN_TAG;
1005 skb->protocol = vlan_get_protocol(skb);
1009 rc = skb_cow_head(skb, 0);
1010 if (unlikely(rc < 0))
1013 vhdr = (struct vlan_ethhdr *)skb->data;
1014 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT)
1017 skb->protocol = vlan_get_protocol(skb);
1021 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
1022 struct sk_buff *skb, struct hns3_desc *desc)
1024 u32 ol_type_vlan_len_msec = 0;
1025 u32 type_cs_vlan_tso = 0;
1026 u32 paylen = skb->len;
1032 ret = hns3_handle_vtags(ring, skb);
1033 if (unlikely(ret < 0)) {
1034 u64_stats_update_begin(&ring->syncp);
1035 ring->stats.tx_vlan_err++;
1036 u64_stats_update_end(&ring->syncp);
1038 } else if (ret == HNS3_INNER_VLAN_TAG) {
1039 inner_vtag = skb_vlan_tag_get(skb);
1040 inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1042 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1);
1043 } else if (ret == HNS3_OUTER_VLAN_TAG) {
1044 out_vtag = skb_vlan_tag_get(skb);
1045 out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1047 hns3_set_field(ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B,
1051 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1052 u8 ol4_proto, il4_proto;
1054 skb_reset_mac_len(skb);
1056 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
1057 if (unlikely(ret < 0)) {
1058 u64_stats_update_begin(&ring->syncp);
1059 ring->stats.tx_l4_proto_err++;
1060 u64_stats_update_end(&ring->syncp);
1064 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
1066 &ol_type_vlan_len_msec);
1067 if (unlikely(ret < 0)) {
1068 u64_stats_update_begin(&ring->syncp);
1069 ring->stats.tx_l2l3l4_err++;
1070 u64_stats_update_end(&ring->syncp);
1074 ret = hns3_set_tso(skb, &paylen, &mss,
1076 if (unlikely(ret < 0)) {
1077 u64_stats_update_begin(&ring->syncp);
1078 ring->stats.tx_tso_err++;
1079 u64_stats_update_end(&ring->syncp);
1085 desc->tx.ol_type_vlan_len_msec =
1086 cpu_to_le32(ol_type_vlan_len_msec);
1087 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso);
1088 desc->tx.paylen = cpu_to_le32(paylen);
1089 desc->tx.mss = cpu_to_le16(mss);
1090 desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
1091 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
1096 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
1097 unsigned int size, enum hns_desc_type type)
1099 #define HNS3_LIKELY_BD_NUM 1
1101 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1102 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1103 struct device *dev = ring_to_dev(ring);
1105 unsigned int frag_buf_num;
1109 if (type == DESC_TYPE_SKB) {
1110 struct sk_buff *skb = (struct sk_buff *)priv;
1113 ret = hns3_fill_skb_desc(ring, skb, desc);
1114 if (unlikely(ret < 0))
1117 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1119 frag = (skb_frag_t *)priv;
1120 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1123 if (unlikely(dma_mapping_error(dev, dma))) {
1124 u64_stats_update_begin(&ring->syncp);
1125 ring->stats.sw_err_cnt++;
1126 u64_stats_update_end(&ring->syncp);
1130 desc_cb->length = size;
1132 if (likely(size <= HNS3_MAX_BD_SIZE)) {
1133 desc_cb->priv = priv;
1135 desc_cb->type = type;
1136 desc->addr = cpu_to_le64(dma);
1137 desc->tx.send_size = cpu_to_le16(size);
1138 desc->tx.bdtp_fe_sc_vld_ra_ri =
1139 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1141 ring_ptr_move_fw(ring, next_to_use);
1142 return HNS3_LIKELY_BD_NUM;
1145 frag_buf_num = hns3_tx_bd_count(size);
1146 sizeoflast = size & HNS3_TX_LAST_SIZE_M;
1147 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1149 /* When frag size is bigger than hardware limit, split this frag */
1150 for (k = 0; k < frag_buf_num; k++) {
1151 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */
1152 desc_cb->priv = priv;
1153 desc_cb->dma = dma + HNS3_MAX_BD_SIZE * k;
1154 desc_cb->type = (type == DESC_TYPE_SKB && !k) ?
1155 DESC_TYPE_SKB : DESC_TYPE_PAGE;
1157 /* now, fill the descriptor */
1158 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
1159 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
1160 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1161 desc->tx.bdtp_fe_sc_vld_ra_ri =
1162 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1164 /* move ring pointer to next */
1165 ring_ptr_move_fw(ring, next_to_use);
1167 desc_cb = &ring->desc_cb[ring->next_to_use];
1168 desc = &ring->desc[ring->next_to_use];
1171 return frag_buf_num;
1174 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1175 unsigned int bd_num)
1180 size = skb_headlen(skb);
1181 while (size > HNS3_MAX_BD_SIZE) {
1182 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1183 size -= HNS3_MAX_BD_SIZE;
1185 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1190 bd_size[bd_num++] = size;
1191 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1195 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1196 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1197 size = skb_frag_size(frag);
1201 while (size > HNS3_MAX_BD_SIZE) {
1202 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1203 size -= HNS3_MAX_BD_SIZE;
1205 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1209 bd_size[bd_num++] = size;
1210 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1217 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size)
1219 struct sk_buff *frag_skb;
1220 unsigned int bd_num = 0;
1222 /* If the total len is within the max bd limit */
1223 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !skb_has_frag_list(skb) &&
1224 skb_shinfo(skb)->nr_frags < HNS3_MAX_NON_TSO_BD_NUM))
1225 return skb_shinfo(skb)->nr_frags + 1U;
1227 /* The below case will always be linearized, return
1228 * HNS3_MAX_BD_NUM_TSO + 1U to make sure it is linearized.
1230 if (unlikely(skb->len > HNS3_MAX_TSO_SIZE ||
1231 (!skb_is_gso(skb) && skb->len > HNS3_MAX_NON_TSO_SIZE)))
1232 return HNS3_MAX_TSO_BD_NUM + 1U;
1234 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num);
1236 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM)
1239 skb_walk_frags(skb, frag_skb) {
1240 bd_num = hns3_skb_bd_num(frag_skb, bd_size, bd_num);
1241 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1248 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb)
1250 if (!skb->encapsulation)
1251 return skb_transport_offset(skb) + tcp_hdrlen(skb);
1253 return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
1256 /* HW need every continuous 8 buffer data to be larger than MSS,
1257 * we simplify it by ensuring skb_headlen + the first continuous
1258 * 7 frags to to be larger than gso header len + mss, and the remaining
1259 * continuous 7 frags to be larger than MSS except the last 7 frags.
1261 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size,
1262 unsigned int bd_num)
1264 unsigned int tot_len = 0;
1267 for (i = 0; i < HNS3_MAX_NON_TSO_BD_NUM - 1U; i++)
1268 tot_len += bd_size[i];
1270 /* ensure the first 8 frags is greater than mss + header */
1271 if (tot_len + bd_size[HNS3_MAX_NON_TSO_BD_NUM - 1U] <
1272 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb))
1275 /* ensure every continuous 7 buffer is greater than mss
1276 * except the last one.
1278 for (i = 0; i < bd_num - HNS3_MAX_NON_TSO_BD_NUM; i++) {
1279 tot_len -= bd_size[i];
1280 tot_len += bd_size[i + HNS3_MAX_NON_TSO_BD_NUM - 1U];
1282 if (tot_len < skb_shinfo(skb)->gso_size)
1289 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring,
1290 struct sk_buff **out_skb)
1292 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U];
1293 struct sk_buff *skb = *out_skb;
1294 unsigned int bd_num;
1296 bd_num = hns3_tx_bd_num(skb, bd_size);
1297 if (unlikely(bd_num > HNS3_MAX_NON_TSO_BD_NUM)) {
1298 struct sk_buff *new_skb;
1300 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) &&
1301 !hns3_skb_need_linearized(skb, bd_size, bd_num))
1304 /* manual split the send packet */
1305 new_skb = skb_copy(skb, GFP_ATOMIC);
1308 dev_kfree_skb_any(skb);
1311 bd_num = hns3_tx_bd_count(new_skb->len);
1312 if ((skb_is_gso(new_skb) && bd_num > HNS3_MAX_TSO_BD_NUM) ||
1313 (!skb_is_gso(new_skb) &&
1314 bd_num > HNS3_MAX_NON_TSO_BD_NUM))
1317 u64_stats_update_begin(&ring->syncp);
1318 ring->stats.tx_copy++;
1319 u64_stats_update_end(&ring->syncp);
1323 if (unlikely(ring_space(ring) < bd_num))
1329 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
1331 struct device *dev = ring_to_dev(ring);
1334 for (i = 0; i < ring->desc_num; i++) {
1335 /* check if this is where we started */
1336 if (ring->next_to_use == next_to_use_orig)
1340 ring_ptr_move_bw(ring, next_to_use);
1342 /* unmap the descriptor dma address */
1343 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB)
1344 dma_unmap_single(dev,
1345 ring->desc_cb[ring->next_to_use].dma,
1346 ring->desc_cb[ring->next_to_use].length,
1348 else if (ring->desc_cb[ring->next_to_use].length)
1350 ring->desc_cb[ring->next_to_use].dma,
1351 ring->desc_cb[ring->next_to_use].length,
1354 ring->desc_cb[ring->next_to_use].length = 0;
1355 ring->desc_cb[ring->next_to_use].dma = 0;
1359 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring,
1360 struct sk_buff *skb, enum hns_desc_type type)
1362 unsigned int size = skb_headlen(skb);
1363 int i, ret, bd_num = 0;
1366 ret = hns3_fill_desc(ring, skb, size, type);
1367 if (unlikely(ret < 0))
1373 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1374 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1376 size = skb_frag_size(frag);
1380 ret = hns3_fill_desc(ring, frag, size, DESC_TYPE_PAGE);
1381 if (unlikely(ret < 0))
1390 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
1392 struct hns3_nic_priv *priv = netdev_priv(netdev);
1393 struct hns3_nic_ring_data *ring_data =
1394 &tx_ring_data(priv, skb->queue_mapping);
1395 struct hns3_enet_ring *ring = ring_data->ring;
1396 struct netdev_queue *dev_queue;
1397 int pre_ntu, next_to_use_head;
1398 struct sk_buff *frag_skb;
1402 /* Prefetch the data used later */
1403 prefetch(skb->data);
1405 ret = hns3_nic_maybe_stop_tx(ring, &skb);
1406 if (unlikely(ret <= 0)) {
1407 if (ret == -EBUSY) {
1408 u64_stats_update_begin(&ring->syncp);
1409 ring->stats.tx_busy++;
1410 u64_stats_update_end(&ring->syncp);
1411 goto out_net_tx_busy;
1412 } else if (ret == -ENOMEM) {
1413 u64_stats_update_begin(&ring->syncp);
1414 ring->stats.sw_err_cnt++;
1415 u64_stats_update_end(&ring->syncp);
1418 hns3_rl_err(netdev, "xmit error: %d!\n", ret);
1422 next_to_use_head = ring->next_to_use;
1424 ret = hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB);
1425 if (unlikely(ret < 0))
1430 if (!skb_has_frag_list(skb))
1433 skb_walk_frags(skb, frag_skb) {
1434 ret = hns3_fill_skb_to_desc(ring, frag_skb, DESC_TYPE_PAGE);
1435 if (unlikely(ret < 0))
1441 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) :
1442 (ring->desc_num - 1);
1443 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |=
1444 cpu_to_le16(BIT(HNS3_TXD_FE_B));
1446 /* Complete translate all packets */
1447 dev_queue = netdev_get_tx_queue(netdev, ring_data->queue_index);
1448 netdev_tx_sent_queue(dev_queue, skb->len);
1450 wmb(); /* Commit all data before submit */
1452 hnae3_queue_xmit(ring->tqp, bd_num);
1454 return NETDEV_TX_OK;
1457 hns3_clear_desc(ring, next_to_use_head);
1460 dev_kfree_skb_any(skb);
1461 return NETDEV_TX_OK;
1464 netif_stop_subqueue(netdev, ring_data->queue_index);
1465 smp_mb(); /* Commit all data before submit */
1467 return NETDEV_TX_BUSY;
1470 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
1472 struct hnae3_handle *h = hns3_get_handle(netdev);
1473 struct sockaddr *mac_addr = p;
1476 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
1477 return -EADDRNOTAVAIL;
1479 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
1480 netdev_info(netdev, "already using mac address %pM\n",
1485 /* For VF device, if there is a perm_addr, then the user will not
1486 * be allowed to change the address.
1488 if (!hns3_is_phys_func(h->pdev) &&
1489 !is_zero_ether_addr(netdev->perm_addr)) {
1490 netdev_err(netdev, "has permanent MAC %pM, user MAC %pM not allow\n",
1491 netdev->perm_addr, mac_addr->sa_data);
1495 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
1497 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
1501 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
1506 static int hns3_nic_do_ioctl(struct net_device *netdev,
1507 struct ifreq *ifr, int cmd)
1509 struct hnae3_handle *h = hns3_get_handle(netdev);
1511 if (!netif_running(netdev))
1514 if (!h->ae_algo->ops->do_ioctl)
1517 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
1520 static int hns3_nic_set_features(struct net_device *netdev,
1521 netdev_features_t features)
1523 netdev_features_t changed = netdev->features ^ features;
1524 struct hns3_nic_priv *priv = netdev_priv(netdev);
1525 struct hnae3_handle *h = priv->ae_handle;
1529 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
1530 enable = !!(features & NETIF_F_GRO_HW);
1531 ret = h->ae_algo->ops->set_gro_en(h, enable);
1536 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
1537 h->ae_algo->ops->enable_vlan_filter) {
1538 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER);
1539 h->ae_algo->ops->enable_vlan_filter(h, enable);
1542 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
1543 h->ae_algo->ops->enable_hw_strip_rxvtag) {
1544 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
1545 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
1550 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
1551 enable = !!(features & NETIF_F_NTUPLE);
1552 h->ae_algo->ops->enable_fd(h, enable);
1555 netdev->features = features;
1559 static void hns3_nic_get_stats64(struct net_device *netdev,
1560 struct rtnl_link_stats64 *stats)
1562 struct hns3_nic_priv *priv = netdev_priv(netdev);
1563 int queue_num = priv->ae_handle->kinfo.num_tqps;
1564 struct hnae3_handle *handle = priv->ae_handle;
1565 struct hns3_enet_ring *ring;
1566 u64 rx_length_errors = 0;
1567 u64 rx_crc_errors = 0;
1568 u64 rx_multicast = 0;
1580 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
1583 handle->ae_algo->ops->update_stats(handle, &netdev->stats);
1585 for (idx = 0; idx < queue_num; idx++) {
1586 /* fetch the tx stats */
1587 ring = priv->ring_data[idx].ring;
1589 start = u64_stats_fetch_begin_irq(&ring->syncp);
1590 tx_bytes += ring->stats.tx_bytes;
1591 tx_pkts += ring->stats.tx_pkts;
1592 tx_drop += ring->stats.sw_err_cnt;
1593 tx_drop += ring->stats.tx_vlan_err;
1594 tx_drop += ring->stats.tx_l4_proto_err;
1595 tx_drop += ring->stats.tx_l2l3l4_err;
1596 tx_drop += ring->stats.tx_tso_err;
1597 tx_errors += ring->stats.sw_err_cnt;
1598 tx_errors += ring->stats.tx_vlan_err;
1599 tx_errors += ring->stats.tx_l4_proto_err;
1600 tx_errors += ring->stats.tx_l2l3l4_err;
1601 tx_errors += ring->stats.tx_tso_err;
1602 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1604 /* fetch the rx stats */
1605 ring = priv->ring_data[idx + queue_num].ring;
1607 start = u64_stats_fetch_begin_irq(&ring->syncp);
1608 rx_bytes += ring->stats.rx_bytes;
1609 rx_pkts += ring->stats.rx_pkts;
1610 rx_drop += ring->stats.l2_err;
1611 rx_errors += ring->stats.l2_err;
1612 rx_errors += ring->stats.l3l4_csum_err;
1613 rx_crc_errors += ring->stats.l2_err;
1614 rx_multicast += ring->stats.rx_multicast;
1615 rx_length_errors += ring->stats.err_pkt_len;
1616 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1619 stats->tx_bytes = tx_bytes;
1620 stats->tx_packets = tx_pkts;
1621 stats->rx_bytes = rx_bytes;
1622 stats->rx_packets = rx_pkts;
1624 stats->rx_errors = rx_errors;
1625 stats->multicast = rx_multicast;
1626 stats->rx_length_errors = rx_length_errors;
1627 stats->rx_crc_errors = rx_crc_errors;
1628 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
1630 stats->tx_errors = tx_errors;
1631 stats->rx_dropped = rx_drop;
1632 stats->tx_dropped = tx_drop;
1633 stats->collisions = netdev->stats.collisions;
1634 stats->rx_over_errors = netdev->stats.rx_over_errors;
1635 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
1636 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
1637 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
1638 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
1639 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
1640 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
1641 stats->tx_window_errors = netdev->stats.tx_window_errors;
1642 stats->rx_compressed = netdev->stats.rx_compressed;
1643 stats->tx_compressed = netdev->stats.tx_compressed;
1646 static int hns3_setup_tc(struct net_device *netdev, void *type_data)
1648 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
1649 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map;
1650 struct hnae3_knic_private_info *kinfo;
1651 u8 tc = mqprio_qopt->qopt.num_tc;
1652 u16 mode = mqprio_qopt->mode;
1653 u8 hw = mqprio_qopt->qopt.hw;
1654 struct hnae3_handle *h;
1656 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
1657 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
1660 if (tc > HNAE3_MAX_TC)
1666 h = hns3_get_handle(netdev);
1669 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc);
1671 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
1672 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP;
1675 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
1678 if (type != TC_SETUP_QDISC_MQPRIO)
1681 return hns3_setup_tc(dev, type_data);
1684 static int hns3_vlan_rx_add_vid(struct net_device *netdev,
1685 __be16 proto, u16 vid)
1687 struct hnae3_handle *h = hns3_get_handle(netdev);
1690 if (h->ae_algo->ops->set_vlan_filter)
1691 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
1696 static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
1697 __be16 proto, u16 vid)
1699 struct hnae3_handle *h = hns3_get_handle(netdev);
1702 if (h->ae_algo->ops->set_vlan_filter)
1703 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
1708 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
1709 u8 qos, __be16 vlan_proto)
1711 struct hnae3_handle *h = hns3_get_handle(netdev);
1714 netif_dbg(h, drv, netdev,
1715 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=%u\n",
1716 vf, vlan, qos, vlan_proto);
1718 if (h->ae_algo->ops->set_vf_vlan_filter)
1719 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
1725 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable)
1727 struct hnae3_handle *handle = hns3_get_handle(netdev);
1729 if (hns3_nic_resetting(netdev))
1732 if (!handle->ae_algo->ops->set_vf_spoofchk)
1735 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable);
1738 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable)
1740 struct hnae3_handle *handle = hns3_get_handle(netdev);
1742 if (!handle->ae_algo->ops->set_vf_trust)
1745 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable);
1748 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
1750 struct hnae3_handle *h = hns3_get_handle(netdev);
1753 if (hns3_nic_resetting(netdev))
1756 if (!h->ae_algo->ops->set_mtu)
1759 netif_dbg(h, drv, netdev,
1760 "change mtu from %u to %d\n", netdev->mtu, new_mtu);
1762 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
1764 netdev_err(netdev, "failed to change MTU in hardware %d\n",
1767 netdev->mtu = new_mtu;
1772 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
1774 struct hns3_nic_priv *priv = netdev_priv(ndev);
1775 struct hnae3_handle *h = hns3_get_handle(ndev);
1776 struct hns3_enet_ring *tx_ring = NULL;
1777 struct napi_struct *napi;
1778 int timeout_queue = 0;
1779 int hw_head, hw_tail;
1780 int fbd_num, fbd_oft;
1781 int ebd_num, ebd_oft;
1786 /* Find the stopped queue the same way the stack does */
1787 for (i = 0; i < ndev->num_tx_queues; i++) {
1788 struct netdev_queue *q;
1789 unsigned long trans_start;
1791 q = netdev_get_tx_queue(ndev, i);
1792 trans_start = q->trans_start;
1793 if (netif_xmit_stopped(q) &&
1795 (trans_start + ndev->watchdog_timeo))) {
1801 if (i == ndev->num_tx_queues) {
1803 "no netdev TX timeout queue found, timeout count: %llu\n",
1804 priv->tx_timeout_count);
1808 priv->tx_timeout_count++;
1810 tx_ring = priv->ring_data[timeout_queue].ring;
1811 napi = &tx_ring->tqp_vector->napi;
1814 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n",
1815 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use,
1816 tx_ring->next_to_clean, napi->state);
1819 "tx_pkts: %llu, tx_bytes: %llu, io_err_cnt: %llu, sw_err_cnt: %llu\n",
1820 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes,
1821 tx_ring->stats.io_err_cnt, tx_ring->stats.sw_err_cnt);
1824 "seg_pkt_cnt: %llu, tx_err_cnt: %llu, restart_queue: %llu, tx_busy: %llu\n",
1825 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_err_cnt,
1826 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy);
1828 /* When mac received many pause frames continuous, it's unable to send
1829 * packets, which may cause tx timeout
1831 if (h->ae_algo->ops->get_mac_stats) {
1832 struct hns3_mac_stats mac_stats;
1834 h->ae_algo->ops->get_mac_stats(h, &mac_stats);
1835 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
1836 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt);
1839 hw_head = readl_relaxed(tx_ring->tqp->io_base +
1840 HNS3_RING_TX_RING_HEAD_REG);
1841 hw_tail = readl_relaxed(tx_ring->tqp->io_base +
1842 HNS3_RING_TX_RING_TAIL_REG);
1843 fbd_num = readl_relaxed(tx_ring->tqp->io_base +
1844 HNS3_RING_TX_RING_FBDNUM_REG);
1845 fbd_oft = readl_relaxed(tx_ring->tqp->io_base +
1846 HNS3_RING_TX_RING_OFFSET_REG);
1847 ebd_num = readl_relaxed(tx_ring->tqp->io_base +
1848 HNS3_RING_TX_RING_EBDNUM_REG);
1849 ebd_oft = readl_relaxed(tx_ring->tqp->io_base +
1850 HNS3_RING_TX_RING_EBD_OFFSET_REG);
1851 bd_num = readl_relaxed(tx_ring->tqp->io_base +
1852 HNS3_RING_TX_RING_BD_NUM_REG);
1853 bd_err = readl_relaxed(tx_ring->tqp->io_base +
1854 HNS3_RING_TX_RING_BD_ERR_REG);
1855 ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG);
1856 tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG);
1859 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n",
1860 bd_num, hw_head, hw_tail, bd_err,
1861 readl(tx_ring->tqp_vector->mask_addr));
1863 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n",
1864 ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft);
1869 static void hns3_nic_net_timeout(struct net_device *ndev)
1871 struct hns3_nic_priv *priv = netdev_priv(ndev);
1872 struct hnae3_handle *h = priv->ae_handle;
1874 if (!hns3_get_tx_timeo_queue_info(ndev))
1877 /* request the reset, and let the hclge to determine
1878 * which reset level should be done
1880 if (h->ae_algo->ops->reset_event)
1881 h->ae_algo->ops->reset_event(h->pdev, h);
1884 #ifdef CONFIG_RFS_ACCEL
1885 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
1886 u16 rxq_index, u32 flow_id)
1888 struct hnae3_handle *h = hns3_get_handle(dev);
1889 struct flow_keys fkeys;
1891 if (!h->ae_algo->ops->add_arfs_entry)
1894 if (skb->encapsulation)
1895 return -EPROTONOSUPPORT;
1897 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0))
1898 return -EPROTONOSUPPORT;
1900 if ((fkeys.basic.n_proto != htons(ETH_P_IP) &&
1901 fkeys.basic.n_proto != htons(ETH_P_IPV6)) ||
1902 (fkeys.basic.ip_proto != IPPROTO_TCP &&
1903 fkeys.basic.ip_proto != IPPROTO_UDP))
1904 return -EPROTONOSUPPORT;
1906 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys);
1910 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf,
1911 struct ifla_vf_info *ivf)
1913 struct hnae3_handle *h = hns3_get_handle(ndev);
1915 if (!h->ae_algo->ops->get_vf_config)
1918 return h->ae_algo->ops->get_vf_config(h, vf, ivf);
1921 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf,
1924 struct hnae3_handle *h = hns3_get_handle(ndev);
1926 if (!h->ae_algo->ops->set_vf_link_state)
1929 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state);
1932 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf,
1933 int min_tx_rate, int max_tx_rate)
1935 struct hnae3_handle *h = hns3_get_handle(ndev);
1937 if (!h->ae_algo->ops->set_vf_rate)
1940 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate,
1944 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
1946 struct hnae3_handle *h = hns3_get_handle(netdev);
1948 if (!h->ae_algo->ops->set_vf_mac)
1951 if (is_multicast_ether_addr(mac)) {
1953 "Invalid MAC:%pM specified. Could not set MAC\n",
1958 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac);
1961 static const struct net_device_ops hns3_nic_netdev_ops = {
1962 .ndo_open = hns3_nic_net_open,
1963 .ndo_stop = hns3_nic_net_stop,
1964 .ndo_start_xmit = hns3_nic_net_xmit,
1965 .ndo_tx_timeout = hns3_nic_net_timeout,
1966 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
1967 .ndo_do_ioctl = hns3_nic_do_ioctl,
1968 .ndo_change_mtu = hns3_nic_change_mtu,
1969 .ndo_set_features = hns3_nic_set_features,
1970 .ndo_get_stats64 = hns3_nic_get_stats64,
1971 .ndo_setup_tc = hns3_nic_setup_tc,
1972 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
1973 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
1974 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
1975 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
1976 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk,
1977 .ndo_set_vf_trust = hns3_set_vf_trust,
1978 #ifdef CONFIG_RFS_ACCEL
1979 .ndo_rx_flow_steer = hns3_rx_flow_steer,
1981 .ndo_get_vf_config = hns3_nic_get_vf_config,
1982 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state,
1983 .ndo_set_vf_rate = hns3_nic_set_vf_rate,
1984 .ndo_set_vf_mac = hns3_nic_set_vf_mac,
1987 bool hns3_is_phys_func(struct pci_dev *pdev)
1989 u32 dev_id = pdev->device;
1992 case HNAE3_DEV_ID_GE:
1993 case HNAE3_DEV_ID_25GE:
1994 case HNAE3_DEV_ID_25GE_RDMA:
1995 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
1996 case HNAE3_DEV_ID_50GE_RDMA:
1997 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
1998 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
2000 case HNAE3_DEV_ID_100G_VF:
2001 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:
2004 dev_warn(&pdev->dev, "un-recognized pci device-id %d",
2011 static void hns3_disable_sriov(struct pci_dev *pdev)
2013 /* If our VFs are assigned we cannot shut down SR-IOV
2014 * without causing issues, so just leave the hardware
2015 * available but disabled
2017 if (pci_vfs_assigned(pdev)) {
2018 dev_warn(&pdev->dev,
2019 "disabling driver while VFs are assigned\n");
2023 pci_disable_sriov(pdev);
2026 static void hns3_get_dev_capability(struct pci_dev *pdev,
2027 struct hnae3_ae_dev *ae_dev)
2029 if (pdev->revision >= 0x21) {
2030 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);
2031 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);
2035 /* hns3_probe - Device initialization routine
2036 * @pdev: PCI device information struct
2037 * @ent: entry in hns3_pci_tbl
2039 * hns3_probe initializes a PF identified by a pci_dev structure.
2040 * The OS initialization, configuring of the PF private structure,
2041 * and a hardware reset occur.
2043 * Returns 0 on success, negative on failure
2045 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2047 struct hnae3_ae_dev *ae_dev;
2050 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL);
2056 ae_dev->pdev = pdev;
2057 ae_dev->flag = ent->driver_data;
2058 ae_dev->reset_type = HNAE3_NONE_RESET;
2059 hns3_get_dev_capability(pdev, ae_dev);
2060 pci_set_drvdata(pdev, ae_dev);
2062 ret = hnae3_register_ae_dev(ae_dev);
2064 devm_kfree(&pdev->dev, ae_dev);
2065 pci_set_drvdata(pdev, NULL);
2071 /* hns3_remove - Device removal routine
2072 * @pdev: PCI device information struct
2074 static void hns3_remove(struct pci_dev *pdev)
2076 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2078 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
2079 hns3_disable_sriov(pdev);
2081 hnae3_unregister_ae_dev(ae_dev);
2082 pci_set_drvdata(pdev, NULL);
2086 * hns3_pci_sriov_configure
2087 * @pdev: pointer to a pci_dev structure
2088 * @num_vfs: number of VFs to allocate
2090 * Enable or change the number of VFs. Called when the user updates the number
2093 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
2097 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
2098 dev_warn(&pdev->dev, "Can not config SRIOV\n");
2103 ret = pci_enable_sriov(pdev, num_vfs);
2105 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
2108 } else if (!pci_vfs_assigned(pdev)) {
2109 pci_disable_sriov(pdev);
2111 dev_warn(&pdev->dev,
2112 "Unable to free VFs because some are assigned to VMs.\n");
2118 static void hns3_shutdown(struct pci_dev *pdev)
2120 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2122 hnae3_unregister_ae_dev(ae_dev);
2123 devm_kfree(&pdev->dev, ae_dev);
2124 pci_set_drvdata(pdev, NULL);
2126 if (system_state == SYSTEM_POWER_OFF)
2127 pci_set_power_state(pdev, PCI_D3hot);
2130 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
2131 pci_channel_state_t state)
2133 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2134 pci_ers_result_t ret;
2136 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state);
2138 if (state == pci_channel_io_perm_failure)
2139 return PCI_ERS_RESULT_DISCONNECT;
2141 if (!ae_dev || !ae_dev->ops) {
2143 "Can't recover - error happened before device initialized\n");
2144 return PCI_ERS_RESULT_NONE;
2147 if (ae_dev->ops->handle_hw_ras_error)
2148 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
2150 return PCI_ERS_RESULT_NONE;
2155 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
2157 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2158 const struct hnae3_ae_ops *ops;
2159 enum hnae3_reset_type reset_type;
2160 struct device *dev = &pdev->dev;
2162 if (!ae_dev || !ae_dev->ops)
2163 return PCI_ERS_RESULT_NONE;
2166 /* request the reset */
2167 if (ops->reset_event && ops->get_reset_level &&
2168 ops->set_default_reset_request) {
2169 if (ae_dev->hw_err_reset_req) {
2170 reset_type = ops->get_reset_level(ae_dev,
2171 &ae_dev->hw_err_reset_req);
2172 ops->set_default_reset_request(ae_dev, reset_type);
2173 dev_info(dev, "requesting reset due to PCI error\n");
2174 ops->reset_event(pdev, NULL);
2177 return PCI_ERS_RESULT_RECOVERED;
2180 return PCI_ERS_RESULT_DISCONNECT;
2183 static void hns3_reset_prepare(struct pci_dev *pdev)
2185 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2187 dev_info(&pdev->dev, "hns3 flr prepare\n");
2188 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare)
2189 ae_dev->ops->flr_prepare(ae_dev);
2192 static void hns3_reset_done(struct pci_dev *pdev)
2194 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2196 dev_info(&pdev->dev, "hns3 flr done\n");
2197 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done)
2198 ae_dev->ops->flr_done(ae_dev);
2201 static const struct pci_error_handlers hns3_err_handler = {
2202 .error_detected = hns3_error_detected,
2203 .slot_reset = hns3_slot_reset,
2204 .reset_prepare = hns3_reset_prepare,
2205 .reset_done = hns3_reset_done,
2208 static struct pci_driver hns3_driver = {
2209 .name = hns3_driver_name,
2210 .id_table = hns3_pci_tbl,
2211 .probe = hns3_probe,
2212 .remove = hns3_remove,
2213 .shutdown = hns3_shutdown,
2214 .sriov_configure = hns3_pci_sriov_configure,
2215 .err_handler = &hns3_err_handler,
2218 /* set default feature to hns3 */
2219 static void hns3_set_default_feature(struct net_device *netdev)
2221 struct hnae3_handle *h = hns3_get_handle(netdev);
2222 struct pci_dev *pdev = h->pdev;
2224 netdev->priv_flags |= IFF_UNICAST_FLT;
2226 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2227 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2228 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2229 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
2230 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2231 NETIF_F_TSO_MANGLEID | NETIF_F_FRAGLIST;
2233 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
2235 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2236 NETIF_F_HW_VLAN_CTAG_FILTER |
2237 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
2238 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2239 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2240 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
2241 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2244 netdev->vlan_features |=
2245 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
2246 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
2247 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2248 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
2249 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2252 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2253 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
2254 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2255 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2256 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
2257 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2260 if (pdev->revision >= 0x21) {
2261 netdev->hw_features |= NETIF_F_GRO_HW;
2262 netdev->features |= NETIF_F_GRO_HW;
2264 if (!(h->flags & HNAE3_SUPPORT_VF)) {
2265 netdev->hw_features |= NETIF_F_NTUPLE;
2266 netdev->features |= NETIF_F_NTUPLE;
2271 static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
2272 struct hns3_desc_cb *cb)
2274 unsigned int order = hns3_page_order(ring);
2277 p = dev_alloc_pages(order);
2282 cb->page_offset = 0;
2284 cb->buf = page_address(p);
2285 cb->length = hns3_page_size(ring);
2286 cb->type = DESC_TYPE_PAGE;
2291 static void hns3_free_buffer(struct hns3_enet_ring *ring,
2292 struct hns3_desc_cb *cb)
2294 if (cb->type == DESC_TYPE_SKB)
2295 dev_kfree_skb_any((struct sk_buff *)cb->priv);
2296 else if (!HNAE3_IS_TX_RING(ring))
2297 put_page((struct page *)cb->priv);
2298 memset(cb, 0, sizeof(*cb));
2301 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
2303 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
2304 cb->length, ring_to_dma_dir(ring));
2306 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
2312 static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
2313 struct hns3_desc_cb *cb)
2315 if (cb->type == DESC_TYPE_SKB)
2316 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
2317 ring_to_dma_dir(ring));
2318 else if (cb->length)
2319 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
2320 ring_to_dma_dir(ring));
2323 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
2325 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
2326 ring->desc[i].addr = 0;
2329 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i)
2331 struct hns3_desc_cb *cb = &ring->desc_cb[i];
2333 if (!ring->desc_cb[i].dma)
2336 hns3_buffer_detach(ring, i);
2337 hns3_free_buffer(ring, cb);
2340 static void hns3_free_buffers(struct hns3_enet_ring *ring)
2344 for (i = 0; i < ring->desc_num; i++)
2345 hns3_free_buffer_detach(ring, i);
2348 /* free desc along with its attached buffer */
2349 static void hns3_free_desc(struct hns3_enet_ring *ring)
2351 int size = ring->desc_num * sizeof(ring->desc[0]);
2353 hns3_free_buffers(ring);
2356 dma_free_coherent(ring_to_dev(ring), size,
2357 ring->desc, ring->desc_dma_addr);
2362 static int hns3_alloc_desc(struct hns3_enet_ring *ring)
2364 int size = ring->desc_num * sizeof(ring->desc[0]);
2366 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
2367 &ring->desc_dma_addr, GFP_KERNEL);
2374 static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring,
2375 struct hns3_desc_cb *cb)
2379 ret = hns3_alloc_buffer(ring, cb);
2383 ret = hns3_map_buffer(ring, cb);
2390 hns3_free_buffer(ring, cb);
2395 static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i)
2397 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]);
2402 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2407 /* Allocate memory for raw pkg, and map with dma */
2408 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
2412 for (i = 0; i < ring->desc_num; i++) {
2413 ret = hns3_alloc_buffer_attach(ring, i);
2415 goto out_buffer_fail;
2421 for (j = i - 1; j >= 0; j--)
2422 hns3_free_buffer_detach(ring, j);
2426 /* detach a in-used buffer and replace with a reserved one */
2427 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
2428 struct hns3_desc_cb *res_cb)
2430 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
2431 ring->desc_cb[i] = *res_cb;
2432 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2433 ring->desc[i].rx.bd_base_info = 0;
2436 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
2438 ring->desc_cb[i].reuse_flag = 0;
2439 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
2440 ring->desc_cb[i].page_offset);
2441 ring->desc[i].rx.bd_base_info = 0;
2444 static void hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, int head,
2445 int *bytes, int *pkts)
2447 int ntc = ring->next_to_clean;
2448 struct hns3_desc_cb *desc_cb;
2450 while (head != ntc) {
2451 desc_cb = &ring->desc_cb[ntc];
2452 (*pkts) += (desc_cb->type == DESC_TYPE_SKB);
2453 (*bytes) += desc_cb->length;
2454 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */
2455 hns3_free_buffer_detach(ring, ntc);
2457 if (++ntc == ring->desc_num)
2460 /* Issue prefetch for next Tx descriptor */
2461 prefetch(&ring->desc_cb[ntc]);
2464 /* This smp_store_release() pairs with smp_load_acquire() in
2465 * ring_space called by hns3_nic_net_xmit.
2467 smp_store_release(&ring->next_to_clean, ntc);
2470 static int is_valid_clean_head(struct hns3_enet_ring *ring, int h)
2472 int u = ring->next_to_use;
2473 int c = ring->next_to_clean;
2475 if (unlikely(h > ring->desc_num))
2478 return u > c ? (h > c && h <= u) : (h > c || h <= u);
2481 void hns3_clean_tx_ring(struct hns3_enet_ring *ring)
2483 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2484 struct hns3_nic_priv *priv = netdev_priv(netdev);
2485 struct netdev_queue *dev_queue;
2489 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG);
2490 rmb(); /* Make sure head is ready before touch any data */
2492 if (is_ring_empty(ring) || head == ring->next_to_clean)
2493 return; /* no data to poll */
2495 if (unlikely(!is_valid_clean_head(ring, head))) {
2496 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head,
2497 ring->next_to_use, ring->next_to_clean);
2499 u64_stats_update_begin(&ring->syncp);
2500 ring->stats.io_err_cnt++;
2501 u64_stats_update_end(&ring->syncp);
2507 hns3_nic_reclaim_desc(ring, head, &bytes, &pkts);
2509 ring->tqp_vector->tx_group.total_bytes += bytes;
2510 ring->tqp_vector->tx_group.total_packets += pkts;
2512 u64_stats_update_begin(&ring->syncp);
2513 ring->stats.tx_bytes += bytes;
2514 ring->stats.tx_pkts += pkts;
2515 u64_stats_update_end(&ring->syncp);
2517 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
2518 netdev_tx_completed_queue(dev_queue, pkts, bytes);
2520 if (unlikely(pkts && netif_carrier_ok(netdev) &&
2521 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) {
2522 /* Make sure that anybody stopping the queue after this
2523 * sees the new next_to_clean.
2526 if (netif_tx_queue_stopped(dev_queue) &&
2527 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
2528 netif_tx_wake_queue(dev_queue);
2529 ring->stats.restart_queue++;
2534 static int hns3_desc_unused(struct hns3_enet_ring *ring)
2536 int ntc = ring->next_to_clean;
2537 int ntu = ring->next_to_use;
2539 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
2542 static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
2545 struct hns3_desc_cb *desc_cb;
2546 struct hns3_desc_cb res_cbs;
2549 for (i = 0; i < cleand_count; i++) {
2550 desc_cb = &ring->desc_cb[ring->next_to_use];
2551 if (desc_cb->reuse_flag) {
2552 u64_stats_update_begin(&ring->syncp);
2553 ring->stats.reuse_pg_cnt++;
2554 u64_stats_update_end(&ring->syncp);
2556 hns3_reuse_buffer(ring, ring->next_to_use);
2558 ret = hns3_reserve_buffer_map(ring, &res_cbs);
2560 u64_stats_update_begin(&ring->syncp);
2561 ring->stats.sw_err_cnt++;
2562 u64_stats_update_end(&ring->syncp);
2564 hns3_rl_err(ring->tqp_vector->napi.dev,
2565 "alloc rx buffer failed: %d\n",
2569 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
2571 u64_stats_update_begin(&ring->syncp);
2572 ring->stats.non_reuse_pg++;
2573 u64_stats_update_end(&ring->syncp);
2576 ring_ptr_move_fw(ring, next_to_use);
2579 wmb(); /* Make all data has been write before submit */
2580 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
2583 static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
2584 struct hns3_enet_ring *ring, int pull_len,
2585 struct hns3_desc_cb *desc_cb)
2587 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
2588 int size = le16_to_cpu(desc->rx.size);
2589 u32 truesize = hns3_buf_size(ring);
2591 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
2592 size - pull_len, truesize);
2594 /* Avoid re-using remote pages, or the stack is still using the page
2595 * when page_offset rollback to zero, flag default unreuse
2597 if (unlikely(page_to_nid(desc_cb->priv) != numa_mem_id()) ||
2598 (!desc_cb->page_offset && page_count(desc_cb->priv) > 1))
2601 /* Move offset up to the next cache line */
2602 desc_cb->page_offset += truesize;
2604 if (desc_cb->page_offset + truesize <= hns3_page_size(ring)) {
2605 desc_cb->reuse_flag = 1;
2606 /* Bump ref count on page before it is given */
2607 get_page(desc_cb->priv);
2608 } else if (page_count(desc_cb->priv) == 1) {
2609 desc_cb->reuse_flag = 1;
2610 desc_cb->page_offset = 0;
2611 get_page(desc_cb->priv);
2615 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info)
2617 __be16 type = skb->protocol;
2621 while (eth_type_vlan(type)) {
2622 struct vlan_hdr *vh;
2624 if ((depth + VLAN_HLEN) > skb_headlen(skb))
2627 vh = (struct vlan_hdr *)(skb->data + depth);
2628 type = vh->h_vlan_encapsulated_proto;
2632 skb_set_network_header(skb, depth);
2634 if (type == htons(ETH_P_IP)) {
2635 const struct iphdr *iph = ip_hdr(skb);
2637 depth += sizeof(struct iphdr);
2638 skb_set_transport_header(skb, depth);
2640 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr,
2642 } else if (type == htons(ETH_P_IPV6)) {
2643 const struct ipv6hdr *iph = ipv6_hdr(skb);
2645 depth += sizeof(struct ipv6hdr);
2646 skb_set_transport_header(skb, depth);
2648 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr,
2651 hns3_rl_err(skb->dev,
2652 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n",
2653 be16_to_cpu(type), depth);
2657 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
2659 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
2661 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B))
2662 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID;
2664 skb->csum_start = (unsigned char *)th - skb->head;
2665 skb->csum_offset = offsetof(struct tcphdr, check);
2666 skb->ip_summed = CHECKSUM_PARTIAL;
2670 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
2671 u32 l234info, u32 bd_base_info, u32 ol_info)
2673 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2674 int l3_type, l4_type;
2677 skb->ip_summed = CHECKSUM_NONE;
2679 skb_checksum_none_assert(skb);
2681 if (!(netdev->features & NETIF_F_RXCSUM))
2684 /* check if hardware has done checksum */
2685 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
2688 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
2689 BIT(HNS3_RXD_OL3E_B) |
2690 BIT(HNS3_RXD_OL4E_B)))) {
2691 u64_stats_update_begin(&ring->syncp);
2692 ring->stats.l3l4_csum_err++;
2693 u64_stats_update_end(&ring->syncp);
2698 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M,
2701 case HNS3_OL4_TYPE_MAC_IN_UDP:
2702 case HNS3_OL4_TYPE_NVGRE:
2703 skb->csum_level = 1;
2705 case HNS3_OL4_TYPE_NO_TUN:
2706 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2708 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
2711 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
2712 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
2713 l3_type == HNS3_L3_TYPE_IPV6) &&
2714 (l4_type == HNS3_L4_TYPE_UDP ||
2715 l4_type == HNS3_L4_TYPE_TCP ||
2716 l4_type == HNS3_L4_TYPE_SCTP))
2717 skb->ip_summed = CHECKSUM_UNNECESSARY;
2724 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
2726 if (skb_has_frag_list(skb))
2727 napi_gro_flush(&ring->tqp_vector->napi, false);
2729 napi_gro_receive(&ring->tqp_vector->napi, skb);
2732 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
2733 struct hns3_desc *desc, u32 l234info,
2736 struct hnae3_handle *handle = ring->tqp->handle;
2737 struct pci_dev *pdev = ring->tqp->handle->pdev;
2739 if (pdev->revision == 0x20) {
2740 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2741 if (!(*vlan_tag & VLAN_VID_MASK))
2742 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2744 return (*vlan_tag != 0);
2747 #define HNS3_STRP_OUTER_VLAN 0x1
2748 #define HNS3_STRP_INNER_VLAN 0x2
2749 #define HNS3_STRP_BOTH 0x3
2751 /* Hardware always insert VLAN tag into RX descriptor when
2752 * remove the tag from packet, driver needs to determine
2753 * reporting which tag to stack.
2755 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
2756 HNS3_RXD_STRP_TAGP_S)) {
2757 case HNS3_STRP_OUTER_VLAN:
2758 if (handle->port_base_vlan_state !=
2759 HNAE3_PORT_BASE_VLAN_DISABLE)
2762 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2764 case HNS3_STRP_INNER_VLAN:
2765 if (handle->port_base_vlan_state !=
2766 HNAE3_PORT_BASE_VLAN_DISABLE)
2769 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2771 case HNS3_STRP_BOTH:
2772 if (handle->port_base_vlan_state ==
2773 HNAE3_PORT_BASE_VLAN_DISABLE)
2774 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2776 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2784 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length,
2787 #define HNS3_NEED_ADD_FRAG 1
2788 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
2789 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2790 struct sk_buff *skb;
2792 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
2794 if (unlikely(!skb)) {
2795 hns3_rl_err(netdev, "alloc rx skb fail\n");
2797 u64_stats_update_begin(&ring->syncp);
2798 ring->stats.sw_err_cnt++;
2799 u64_stats_update_end(&ring->syncp);
2804 prefetchw(skb->data);
2806 ring->pending_buf = 1;
2808 ring->tail_skb = NULL;
2809 if (length <= HNS3_RX_HEAD_SIZE) {
2810 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
2812 /* We can reuse buffer as-is, just make sure it is local */
2813 if (likely(page_to_nid(desc_cb->priv) == numa_mem_id()))
2814 desc_cb->reuse_flag = 1;
2815 else /* This page cannot be reused so discard it */
2816 put_page(desc_cb->priv);
2818 ring_ptr_move_fw(ring, next_to_clean);
2821 u64_stats_update_begin(&ring->syncp);
2822 ring->stats.seg_pkt_cnt++;
2823 u64_stats_update_end(&ring->syncp);
2825 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE);
2826 __skb_put(skb, ring->pull_len);
2827 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
2829 ring_ptr_move_fw(ring, next_to_clean);
2831 return HNS3_NEED_ADD_FRAG;
2834 static int hns3_add_frag(struct hns3_enet_ring *ring, struct hns3_desc *desc,
2835 struct sk_buff **out_skb, bool pending)
2837 struct sk_buff *skb = *out_skb;
2838 struct sk_buff *head_skb = *out_skb;
2839 struct sk_buff *new_skb;
2840 struct hns3_desc_cb *desc_cb;
2841 struct hns3_desc *pre_desc;
2845 /* if there is pending bd, the SW param next_to_clean has moved
2846 * to next and the next is NULL
2849 pre_bd = (ring->next_to_clean - 1 + ring->desc_num) %
2851 pre_desc = &ring->desc[pre_bd];
2852 bd_base_info = le32_to_cpu(pre_desc->rx.bd_base_info);
2854 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2857 while (!(bd_base_info & BIT(HNS3_RXD_FE_B))) {
2858 desc = &ring->desc[ring->next_to_clean];
2859 desc_cb = &ring->desc_cb[ring->next_to_clean];
2860 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2861 /* make sure HW write desc complete */
2863 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
2866 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
2867 new_skb = napi_alloc_skb(&ring->tqp_vector->napi,
2869 if (unlikely(!new_skb)) {
2870 hns3_rl_err(ring->tqp_vector->napi.dev,
2871 "alloc rx fraglist skb fail\n");
2876 if (ring->tail_skb) {
2877 ring->tail_skb->next = new_skb;
2878 ring->tail_skb = new_skb;
2880 skb_shinfo(skb)->frag_list = new_skb;
2881 ring->tail_skb = new_skb;
2885 if (ring->tail_skb) {
2886 head_skb->truesize += hns3_buf_size(ring);
2887 head_skb->data_len += le16_to_cpu(desc->rx.size);
2888 head_skb->len += le16_to_cpu(desc->rx.size);
2889 skb = ring->tail_skb;
2892 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
2893 ring_ptr_move_fw(ring, next_to_clean);
2894 ring->pending_buf++;
2900 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring,
2901 struct sk_buff *skb, u32 l234info,
2902 u32 bd_base_info, u32 ol_info)
2906 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
2907 HNS3_RXD_GRO_SIZE_M,
2908 HNS3_RXD_GRO_SIZE_S);
2909 /* if there is no HW GRO, do not set gro params */
2910 if (!skb_shinfo(skb)->gso_size) {
2911 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info);
2915 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info,
2916 HNS3_RXD_GRO_COUNT_M,
2917 HNS3_RXD_GRO_COUNT_S);
2919 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S);
2920 if (l3_type == HNS3_L3_TYPE_IPV4)
2921 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
2922 else if (l3_type == HNS3_L3_TYPE_IPV6)
2923 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
2927 return hns3_gro_complete(skb, l234info);
2930 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
2931 struct sk_buff *skb, u32 rss_hash)
2933 struct hnae3_handle *handle = ring->tqp->handle;
2934 enum pkt_hash_types rss_type;
2937 rss_type = handle->kinfo.rss_type;
2939 rss_type = PKT_HASH_TYPE_NONE;
2941 skb_set_hash(skb, rss_hash, rss_type);
2944 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb)
2946 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2947 enum hns3_pkt_l2t_type l2_frame_type;
2948 u32 bd_base_info, l234info, ol_info;
2949 struct hns3_desc *desc;
2953 /* bdinfo handled below is only valid on the last BD of the
2954 * current packet, and ring->next_to_clean indicates the first
2955 * descriptor of next packet, so need - 1 below.
2957 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) :
2958 (ring->desc_num - 1);
2959 desc = &ring->desc[pre_ntc];
2960 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2961 l234info = le32_to_cpu(desc->rx.l234_info);
2962 ol_info = le32_to_cpu(desc->rx.ol_info);
2964 /* Based on hw strategy, the tag offloaded will be stored at
2965 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
2966 * in one layer tag case.
2968 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
2971 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
2972 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2976 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) |
2977 BIT(HNS3_RXD_L2E_B))))) {
2978 u64_stats_update_begin(&ring->syncp);
2979 if (l234info & BIT(HNS3_RXD_L2E_B))
2980 ring->stats.l2_err++;
2982 ring->stats.err_pkt_len++;
2983 u64_stats_update_end(&ring->syncp);
2990 /* Do update ip stack process */
2991 skb->protocol = eth_type_trans(skb, netdev);
2993 /* This is needed in order to enable forwarding support */
2994 ret = hns3_set_gro_and_checksum(ring, skb, l234info,
2995 bd_base_info, ol_info);
2996 if (unlikely(ret)) {
2997 u64_stats_update_begin(&ring->syncp);
2998 ring->stats.rx_err_cnt++;
2999 u64_stats_update_end(&ring->syncp);
3003 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
3006 u64_stats_update_begin(&ring->syncp);
3007 ring->stats.rx_pkts++;
3008 ring->stats.rx_bytes += len;
3010 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
3011 ring->stats.rx_multicast++;
3013 u64_stats_update_end(&ring->syncp);
3015 ring->tqp_vector->rx_group.total_bytes += len;
3017 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash));
3021 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring,
3022 struct sk_buff **out_skb)
3024 struct sk_buff *skb = ring->skb;
3025 struct hns3_desc_cb *desc_cb;
3026 struct hns3_desc *desc;
3027 unsigned int length;
3031 desc = &ring->desc[ring->next_to_clean];
3032 desc_cb = &ring->desc_cb[ring->next_to_clean];
3036 length = le16_to_cpu(desc->rx.size);
3037 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
3039 /* Check valid BD */
3040 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
3044 ring->va = (unsigned char *)desc_cb->buf + desc_cb->page_offset;
3046 /* Prefetch first cache line of first page
3047 * Idea is to cache few bytes of the header of the packet. Our L1 Cache
3048 * line size is 64B so need to prefetch twice to make it 128B. But in
3049 * actual we can have greater size of caches with 128B Level 1 cache
3050 * lines. In such a case, single fetch would suffice to cache in the
3051 * relevant part of the header.
3054 #if L1_CACHE_BYTES < 128
3055 prefetch(ring->va + L1_CACHE_BYTES);
3059 ret = hns3_alloc_skb(ring, length, ring->va);
3060 *out_skb = skb = ring->skb;
3062 if (ret < 0) /* alloc buffer fail */
3064 if (ret > 0) { /* need add frag */
3065 ret = hns3_add_frag(ring, desc, &skb, false);
3069 /* As the head data may be changed when GRO enable, copy
3070 * the head data in after other data rx completed
3072 memcpy(skb->data, ring->va,
3073 ALIGN(ring->pull_len, sizeof(long)));
3076 ret = hns3_add_frag(ring, desc, &skb, true);
3080 /* As the head data may be changed when GRO enable, copy
3081 * the head data in after other data rx completed
3083 memcpy(skb->data, ring->va,
3084 ALIGN(ring->pull_len, sizeof(long)));
3087 ret = hns3_handle_bdinfo(ring, skb);
3088 if (unlikely(ret)) {
3089 dev_kfree_skb_any(skb);
3093 skb_record_rx_queue(skb, ring->tqp->tqp_index);
3099 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
3100 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
3102 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
3103 int unused_count = hns3_desc_unused(ring);
3104 struct sk_buff *skb = ring->skb;
3109 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG);
3110 rmb(); /* Make sure num taken effect before the other data is touched */
3112 num -= unused_count;
3113 unused_count -= ring->pending_buf;
3115 while (recv_pkts < budget && recv_bds < num) {
3116 /* Reuse or realloc buffers */
3117 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
3118 hns3_nic_alloc_rx_buffers(ring, unused_count);
3119 unused_count = hns3_desc_unused(ring) -
3124 err = hns3_handle_rx_bd(ring, &skb);
3125 if (unlikely(!skb)) /* This fault cannot be repaired */
3128 if (err == -ENXIO) { /* Do not get FE for the packet */
3130 } else if (unlikely(err)) { /* Do jump the err */
3131 recv_bds += ring->pending_buf;
3132 unused_count += ring->pending_buf;
3134 ring->pending_buf = 0;
3139 recv_bds += ring->pending_buf;
3140 unused_count += ring->pending_buf;
3142 ring->pending_buf = 0;
3148 /* Make all data has been write before submit */
3149 if (unused_count > 0)
3150 hns3_nic_alloc_rx_buffers(ring, unused_count);
3155 static bool hns3_get_new_flow_lvl(struct hns3_enet_ring_group *ring_group)
3157 #define HNS3_RX_LOW_BYTE_RATE 10000
3158 #define HNS3_RX_MID_BYTE_RATE 20000
3159 #define HNS3_RX_ULTRA_PACKET_RATE 40
3161 enum hns3_flow_level_range new_flow_level;
3162 struct hns3_enet_tqp_vector *tqp_vector;
3163 int packets_per_msecs, bytes_per_msecs;
3166 tqp_vector = ring_group->ring->tqp_vector;
3168 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies);
3169 if (!time_passed_ms)
3172 do_div(ring_group->total_packets, time_passed_ms);
3173 packets_per_msecs = ring_group->total_packets;
3175 do_div(ring_group->total_bytes, time_passed_ms);
3176 bytes_per_msecs = ring_group->total_bytes;
3178 new_flow_level = ring_group->coal.flow_level;
3180 /* Simple throttlerate management
3181 * 0-10MB/s lower (50000 ints/s)
3182 * 10-20MB/s middle (20000 ints/s)
3183 * 20-1249MB/s high (18000 ints/s)
3184 * > 40000pps ultra (8000 ints/s)
3186 switch (new_flow_level) {
3188 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE)
3189 new_flow_level = HNS3_FLOW_MID;
3192 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE)
3193 new_flow_level = HNS3_FLOW_HIGH;
3194 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE)
3195 new_flow_level = HNS3_FLOW_LOW;
3197 case HNS3_FLOW_HIGH:
3198 case HNS3_FLOW_ULTRA:
3200 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE)
3201 new_flow_level = HNS3_FLOW_MID;
3205 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE &&
3206 &tqp_vector->rx_group == ring_group)
3207 new_flow_level = HNS3_FLOW_ULTRA;
3209 ring_group->total_bytes = 0;
3210 ring_group->total_packets = 0;
3211 ring_group->coal.flow_level = new_flow_level;
3216 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group)
3218 struct hns3_enet_tqp_vector *tqp_vector;
3221 if (!ring_group->ring)
3224 tqp_vector = ring_group->ring->tqp_vector;
3225 if (!tqp_vector->last_jiffies)
3228 if (ring_group->total_packets == 0) {
3229 ring_group->coal.int_gl = HNS3_INT_GL_50K;
3230 ring_group->coal.flow_level = HNS3_FLOW_LOW;
3234 if (!hns3_get_new_flow_lvl(ring_group))
3237 new_int_gl = ring_group->coal.int_gl;
3238 switch (ring_group->coal.flow_level) {
3240 new_int_gl = HNS3_INT_GL_50K;
3243 new_int_gl = HNS3_INT_GL_20K;
3245 case HNS3_FLOW_HIGH:
3246 new_int_gl = HNS3_INT_GL_18K;
3248 case HNS3_FLOW_ULTRA:
3249 new_int_gl = HNS3_INT_GL_8K;
3255 if (new_int_gl != ring_group->coal.int_gl) {
3256 ring_group->coal.int_gl = new_int_gl;
3262 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
3264 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
3265 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
3266 bool rx_update, tx_update;
3268 /* update param every 1000ms */
3269 if (time_before(jiffies,
3270 tqp_vector->last_jiffies + msecs_to_jiffies(1000)))
3273 if (rx_group->coal.gl_adapt_enable) {
3274 rx_update = hns3_get_new_int_gl(rx_group);
3276 hns3_set_vector_coalesce_rx_gl(tqp_vector,
3277 rx_group->coal.int_gl);
3280 if (tx_group->coal.gl_adapt_enable) {
3281 tx_update = hns3_get_new_int_gl(tx_group);
3283 hns3_set_vector_coalesce_tx_gl(tqp_vector,
3284 tx_group->coal.int_gl);
3287 tqp_vector->last_jiffies = jiffies;
3290 static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
3292 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
3293 struct hns3_enet_ring *ring;
3294 int rx_pkt_total = 0;
3296 struct hns3_enet_tqp_vector *tqp_vector =
3297 container_of(napi, struct hns3_enet_tqp_vector, napi);
3298 bool clean_complete = true;
3299 int rx_budget = budget;
3301 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
3302 napi_complete(napi);
3306 /* Since the actual Tx work is minimal, we can give the Tx a larger
3307 * budget and be more aggressive about cleaning up the Tx descriptors.
3309 hns3_for_each_ring(ring, tqp_vector->tx_group)
3310 hns3_clean_tx_ring(ring);
3312 /* make sure rx ring budget not smaller than 1 */
3313 if (tqp_vector->num_tqps > 1)
3314 rx_budget = max(budget / tqp_vector->num_tqps, 1);
3316 hns3_for_each_ring(ring, tqp_vector->rx_group) {
3317 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
3320 if (rx_cleaned >= rx_budget)
3321 clean_complete = false;
3323 rx_pkt_total += rx_cleaned;
3326 tqp_vector->rx_group.total_packets += rx_pkt_total;
3328 if (!clean_complete)
3331 if (napi_complete(napi) &&
3332 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
3333 hns3_update_new_int_gl(tqp_vector);
3334 hns3_mask_vector_irq(tqp_vector, 1);
3337 return rx_pkt_total;
3340 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3341 struct hnae3_ring_chain_node *head)
3343 struct pci_dev *pdev = tqp_vector->handle->pdev;
3344 struct hnae3_ring_chain_node *cur_chain = head;
3345 struct hnae3_ring_chain_node *chain;
3346 struct hns3_enet_ring *tx_ring;
3347 struct hns3_enet_ring *rx_ring;
3349 tx_ring = tqp_vector->tx_group.ring;
3351 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
3352 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3353 HNAE3_RING_TYPE_TX);
3354 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3355 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
3357 cur_chain->next = NULL;
3359 while (tx_ring->next) {
3360 tx_ring = tx_ring->next;
3362 chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
3365 goto err_free_chain;
3367 cur_chain->next = chain;
3368 chain->tqp_index = tx_ring->tqp->tqp_index;
3369 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3370 HNAE3_RING_TYPE_TX);
3371 hnae3_set_field(chain->int_gl_idx,
3372 HNAE3_RING_GL_IDX_M,
3373 HNAE3_RING_GL_IDX_S,
3380 rx_ring = tqp_vector->rx_group.ring;
3381 if (!tx_ring && rx_ring) {
3382 cur_chain->next = NULL;
3383 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
3384 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3385 HNAE3_RING_TYPE_RX);
3386 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3387 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
3389 rx_ring = rx_ring->next;
3393 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
3395 goto err_free_chain;
3397 cur_chain->next = chain;
3398 chain->tqp_index = rx_ring->tqp->tqp_index;
3399 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3400 HNAE3_RING_TYPE_RX);
3401 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3402 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
3406 rx_ring = rx_ring->next;
3412 cur_chain = head->next;
3414 chain = cur_chain->next;
3415 devm_kfree(&pdev->dev, cur_chain);
3423 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3424 struct hnae3_ring_chain_node *head)
3426 struct pci_dev *pdev = tqp_vector->handle->pdev;
3427 struct hnae3_ring_chain_node *chain_tmp, *chain;
3432 chain_tmp = chain->next;
3433 devm_kfree(&pdev->dev, chain);
3438 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
3439 struct hns3_enet_ring *ring)
3441 ring->next = group->ring;
3447 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
3449 struct pci_dev *pdev = priv->ae_handle->pdev;
3450 struct hns3_enet_tqp_vector *tqp_vector;
3451 int num_vectors = priv->vector_num;
3455 numa_node = dev_to_node(&pdev->dev);
3457 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
3458 tqp_vector = &priv->tqp_vector[vector_i];
3459 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
3460 &tqp_vector->affinity_mask);
3464 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
3466 struct hnae3_ring_chain_node vector_ring_chain;
3467 struct hnae3_handle *h = priv->ae_handle;
3468 struct hns3_enet_tqp_vector *tqp_vector;
3472 hns3_nic_set_cpumask(priv);
3474 for (i = 0; i < priv->vector_num; i++) {
3475 tqp_vector = &priv->tqp_vector[i];
3476 hns3_vector_gl_rl_init_hw(tqp_vector, priv);
3477 tqp_vector->num_tqps = 0;
3480 for (i = 0; i < h->kinfo.num_tqps; i++) {
3481 u16 vector_i = i % priv->vector_num;
3482 u16 tqp_num = h->kinfo.num_tqps;
3484 tqp_vector = &priv->tqp_vector[vector_i];
3486 hns3_add_ring_to_group(&tqp_vector->tx_group,
3487 priv->ring_data[i].ring);
3489 hns3_add_ring_to_group(&tqp_vector->rx_group,
3490 priv->ring_data[i + tqp_num].ring);
3492 priv->ring_data[i].ring->tqp_vector = tqp_vector;
3493 priv->ring_data[i + tqp_num].ring->tqp_vector = tqp_vector;
3494 tqp_vector->num_tqps++;
3497 for (i = 0; i < priv->vector_num; i++) {
3498 tqp_vector = &priv->tqp_vector[i];
3500 tqp_vector->rx_group.total_bytes = 0;
3501 tqp_vector->rx_group.total_packets = 0;
3502 tqp_vector->tx_group.total_bytes = 0;
3503 tqp_vector->tx_group.total_packets = 0;
3504 tqp_vector->handle = h;
3506 ret = hns3_get_vector_ring_chain(tqp_vector,
3507 &vector_ring_chain);
3511 ret = h->ae_algo->ops->map_ring_to_vector(h,
3512 tqp_vector->vector_irq, &vector_ring_chain);
3514 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3519 netif_napi_add(priv->netdev, &tqp_vector->napi,
3520 hns3_nic_common_poll, NAPI_POLL_WEIGHT);
3527 netif_napi_del(&priv->tqp_vector[i].napi);
3532 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
3534 #define HNS3_VECTOR_PF_MAX_NUM 64
3536 struct hnae3_handle *h = priv->ae_handle;
3537 struct hns3_enet_tqp_vector *tqp_vector;
3538 struct hnae3_vector_info *vector;
3539 struct pci_dev *pdev = h->pdev;
3540 u16 tqp_num = h->kinfo.num_tqps;
3545 /* RSS size, cpu online and vector_num should be the same */
3546 /* Should consider 2p/4p later */
3547 vector_num = min_t(u16, num_online_cpus(), tqp_num);
3548 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM);
3550 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
3555 /* save the actual available vector number */
3556 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
3558 priv->vector_num = vector_num;
3559 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
3560 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
3562 if (!priv->tqp_vector) {
3567 for (i = 0; i < priv->vector_num; i++) {
3568 tqp_vector = &priv->tqp_vector[i];
3569 tqp_vector->idx = i;
3570 tqp_vector->mask_addr = vector[i].io_addr;
3571 tqp_vector->vector_irq = vector[i].vector;
3572 hns3_vector_gl_rl_init(tqp_vector, priv);
3576 devm_kfree(&pdev->dev, vector);
3580 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
3586 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
3588 struct hnae3_ring_chain_node vector_ring_chain;
3589 struct hnae3_handle *h = priv->ae_handle;
3590 struct hns3_enet_tqp_vector *tqp_vector;
3593 for (i = 0; i < priv->vector_num; i++) {
3594 tqp_vector = &priv->tqp_vector[i];
3596 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
3599 hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain);
3601 h->ae_algo->ops->unmap_ring_from_vector(h,
3602 tqp_vector->vector_irq, &vector_ring_chain);
3604 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3606 if (tqp_vector->irq_init_flag == HNS3_VECTOR_INITED) {
3607 irq_set_affinity_hint(tqp_vector->vector_irq, NULL);
3608 free_irq(tqp_vector->vector_irq, tqp_vector);
3609 tqp_vector->irq_init_flag = HNS3_VECTOR_NOT_INITED;
3612 hns3_clear_ring_group(&tqp_vector->rx_group);
3613 hns3_clear_ring_group(&tqp_vector->tx_group);
3614 netif_napi_del(&priv->tqp_vector[i].napi);
3618 static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
3620 struct hnae3_handle *h = priv->ae_handle;
3621 struct pci_dev *pdev = h->pdev;
3624 for (i = 0; i < priv->vector_num; i++) {
3625 struct hns3_enet_tqp_vector *tqp_vector;
3627 tqp_vector = &priv->tqp_vector[i];
3628 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
3633 devm_kfree(&pdev->dev, priv->tqp_vector);
3637 static int hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
3638 unsigned int ring_type)
3640 struct hns3_nic_ring_data *ring_data = priv->ring_data;
3641 int queue_num = priv->ae_handle->kinfo.num_tqps;
3642 struct pci_dev *pdev = priv->ae_handle->pdev;
3643 struct hns3_enet_ring *ring;
3646 ring = devm_kzalloc(&pdev->dev, sizeof(*ring), GFP_KERNEL);
3650 if (ring_type == HNAE3_RING_TYPE_TX) {
3651 desc_num = priv->ae_handle->kinfo.num_tx_desc;
3652 ring_data[q->tqp_index].ring = ring;
3653 ring_data[q->tqp_index].queue_index = q->tqp_index;
3654 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET;
3656 desc_num = priv->ae_handle->kinfo.num_rx_desc;
3657 ring_data[q->tqp_index + queue_num].ring = ring;
3658 ring_data[q->tqp_index + queue_num].queue_index = q->tqp_index;
3659 ring->io_base = q->io_base;
3662 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
3666 ring->desc_cb = NULL;
3667 ring->dev = priv->dev;
3668 ring->desc_dma_addr = 0;
3669 ring->buf_size = q->buf_size;
3670 ring->desc_num = desc_num;
3671 ring->next_to_use = 0;
3672 ring->next_to_clean = 0;
3677 static int hns3_queue_to_ring(struct hnae3_queue *tqp,
3678 struct hns3_nic_priv *priv)
3682 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
3686 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
3688 devm_kfree(priv->dev, priv->ring_data[tqp->tqp_index].ring);
3695 static int hns3_get_ring_config(struct hns3_nic_priv *priv)
3697 struct hnae3_handle *h = priv->ae_handle;
3698 struct pci_dev *pdev = h->pdev;
3701 priv->ring_data = devm_kzalloc(&pdev->dev,
3702 array3_size(h->kinfo.num_tqps,
3703 sizeof(*priv->ring_data),
3706 if (!priv->ring_data)
3709 for (i = 0; i < h->kinfo.num_tqps; i++) {
3710 ret = hns3_queue_to_ring(h->kinfo.tqp[i], priv);
3718 devm_kfree(priv->dev, priv->ring_data[i].ring);
3719 devm_kfree(priv->dev,
3720 priv->ring_data[i + h->kinfo.num_tqps].ring);
3723 devm_kfree(&pdev->dev, priv->ring_data);
3724 priv->ring_data = NULL;
3728 static void hns3_put_ring_config(struct hns3_nic_priv *priv)
3730 struct hnae3_handle *h = priv->ae_handle;
3733 if (!priv->ring_data)
3736 for (i = 0; i < h->kinfo.num_tqps; i++) {
3737 devm_kfree(priv->dev, priv->ring_data[i].ring);
3738 devm_kfree(priv->dev,
3739 priv->ring_data[i + h->kinfo.num_tqps].ring);
3741 devm_kfree(priv->dev, priv->ring_data);
3742 priv->ring_data = NULL;
3745 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
3749 if (ring->desc_num <= 0 || ring->buf_size <= 0)
3752 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num,
3753 sizeof(ring->desc_cb[0]), GFP_KERNEL);
3754 if (!ring->desc_cb) {
3759 ret = hns3_alloc_desc(ring);
3761 goto out_with_desc_cb;
3763 if (!HNAE3_IS_TX_RING(ring)) {
3764 ret = hns3_alloc_ring_buffers(ring);
3772 hns3_free_desc(ring);
3774 devm_kfree(ring_to_dev(ring), ring->desc_cb);
3775 ring->desc_cb = NULL;
3780 void hns3_fini_ring(struct hns3_enet_ring *ring)
3782 hns3_free_desc(ring);
3783 devm_kfree(ring_to_dev(ring), ring->desc_cb);
3784 ring->desc_cb = NULL;
3785 ring->next_to_clean = 0;
3786 ring->next_to_use = 0;
3787 ring->pending_buf = 0;
3789 dev_kfree_skb_any(ring->skb);
3794 static int hns3_buf_size2type(u32 buf_size)
3800 bd_size_type = HNS3_BD_SIZE_512_TYPE;
3803 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
3806 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3809 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
3812 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3815 return bd_size_type;
3818 static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
3820 dma_addr_t dma = ring->desc_dma_addr;
3821 struct hnae3_queue *q = ring->tqp;
3823 if (!HNAE3_IS_TX_RING(ring)) {
3824 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma);
3825 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
3826 (u32)((dma >> 31) >> 1));
3828 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
3829 hns3_buf_size2type(ring->buf_size));
3830 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
3831 ring->desc_num / 8 - 1);
3834 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
3836 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
3837 (u32)((dma >> 31) >> 1));
3839 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
3840 ring->desc_num / 8 - 1);
3844 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
3846 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3849 for (i = 0; i < HNAE3_MAX_TC; i++) {
3850 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
3853 if (!tc_info->enable)
3856 for (j = 0; j < tc_info->tqp_count; j++) {
3857 struct hnae3_queue *q;
3859 q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp;
3860 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
3866 int hns3_init_all_ring(struct hns3_nic_priv *priv)
3868 struct hnae3_handle *h = priv->ae_handle;
3869 int ring_num = h->kinfo.num_tqps * 2;
3873 for (i = 0; i < ring_num; i++) {
3874 ret = hns3_alloc_ring_memory(priv->ring_data[i].ring);
3877 "Alloc ring memory fail! ret=%d\n", ret);
3878 goto out_when_alloc_ring_memory;
3881 u64_stats_init(&priv->ring_data[i].ring->syncp);
3886 out_when_alloc_ring_memory:
3887 for (j = i - 1; j >= 0; j--)
3888 hns3_fini_ring(priv->ring_data[j].ring);
3893 int hns3_uninit_all_ring(struct hns3_nic_priv *priv)
3895 struct hnae3_handle *h = priv->ae_handle;
3898 for (i = 0; i < h->kinfo.num_tqps; i++) {
3899 hns3_fini_ring(priv->ring_data[i].ring);
3900 hns3_fini_ring(priv->ring_data[i + h->kinfo.num_tqps].ring);
3905 /* Set mac addr if it is configured. or leave it to the AE driver */
3906 static int hns3_init_mac_addr(struct net_device *netdev)
3908 struct hns3_nic_priv *priv = netdev_priv(netdev);
3909 struct hnae3_handle *h = priv->ae_handle;
3910 u8 mac_addr_temp[ETH_ALEN];
3913 if (h->ae_algo->ops->get_mac_addr)
3914 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
3916 /* Check if the MAC address is valid, if not get a random one */
3917 if (!is_valid_ether_addr(mac_addr_temp)) {
3918 eth_hw_addr_random(netdev);
3919 dev_warn(priv->dev, "using random MAC address %pM\n",
3922 ether_addr_copy(netdev->dev_addr, mac_addr_temp);
3923 ether_addr_copy(netdev->perm_addr, mac_addr_temp);
3926 if (h->ae_algo->ops->set_mac_addr)
3927 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
3932 static int hns3_init_phy(struct net_device *netdev)
3934 struct hnae3_handle *h = hns3_get_handle(netdev);
3937 if (h->ae_algo->ops->mac_connect_phy)
3938 ret = h->ae_algo->ops->mac_connect_phy(h);
3943 static void hns3_uninit_phy(struct net_device *netdev)
3945 struct hnae3_handle *h = hns3_get_handle(netdev);
3947 if (h->ae_algo->ops->mac_disconnect_phy)
3948 h->ae_algo->ops->mac_disconnect_phy(h);
3951 static int hns3_restore_fd_rules(struct net_device *netdev)
3953 struct hnae3_handle *h = hns3_get_handle(netdev);
3956 if (h->ae_algo->ops->restore_fd_rules)
3957 ret = h->ae_algo->ops->restore_fd_rules(h);
3962 static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list)
3964 struct hnae3_handle *h = hns3_get_handle(netdev);
3966 if (h->ae_algo->ops->del_all_fd_entries)
3967 h->ae_algo->ops->del_all_fd_entries(h, clear_list);
3970 static int hns3_client_start(struct hnae3_handle *handle)
3972 if (!handle->ae_algo->ops->client_start)
3975 return handle->ae_algo->ops->client_start(handle);
3978 static void hns3_client_stop(struct hnae3_handle *handle)
3980 if (!handle->ae_algo->ops->client_stop)
3983 handle->ae_algo->ops->client_stop(handle);
3986 static void hns3_info_show(struct hns3_nic_priv *priv)
3988 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3990 dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr);
3991 dev_info(priv->dev, "Task queue pairs numbers: %d\n", kinfo->num_tqps);
3992 dev_info(priv->dev, "RSS size: %d\n", kinfo->rss_size);
3993 dev_info(priv->dev, "Allocated RSS size: %d\n", kinfo->req_rss_size);
3994 dev_info(priv->dev, "RX buffer length: %d\n", kinfo->rx_buf_len);
3995 dev_info(priv->dev, "Desc num per TX queue: %d\n", kinfo->num_tx_desc);
3996 dev_info(priv->dev, "Desc num per RX queue: %d\n", kinfo->num_rx_desc);
3997 dev_info(priv->dev, "Total number of enabled TCs: %d\n", kinfo->num_tc);
3998 dev_info(priv->dev, "Max mtu size: %d\n", priv->netdev->max_mtu);
4001 static int hns3_client_init(struct hnae3_handle *handle)
4003 struct pci_dev *pdev = handle->pdev;
4004 u16 alloc_tqps, max_rss_size;
4005 struct hns3_nic_priv *priv;
4006 struct net_device *netdev;
4009 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
4011 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
4015 priv = netdev_priv(netdev);
4016 priv->dev = &pdev->dev;
4017 priv->netdev = netdev;
4018 priv->ae_handle = handle;
4019 priv->tx_timeout_count = 0;
4020 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
4022 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL);
4024 handle->kinfo.netdev = netdev;
4025 handle->priv = (void *)priv;
4027 hns3_init_mac_addr(netdev);
4029 hns3_set_default_feature(netdev);
4031 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
4032 netdev->priv_flags |= IFF_UNICAST_FLT;
4033 netdev->netdev_ops = &hns3_nic_netdev_ops;
4034 SET_NETDEV_DEV(netdev, &pdev->dev);
4035 hns3_ethtool_set_ops(netdev);
4037 /* Carrier off reporting is important to ethtool even BEFORE open */
4038 netif_carrier_off(netdev);
4040 ret = hns3_get_ring_config(priv);
4043 goto out_get_ring_cfg;
4046 ret = hns3_nic_alloc_vector_data(priv);
4049 goto out_alloc_vector_data;
4052 ret = hns3_nic_init_vector_data(priv);
4055 goto out_init_vector_data;
4058 ret = hns3_init_all_ring(priv);
4061 goto out_init_ring_data;
4064 ret = hns3_init_phy(netdev);
4068 ret = register_netdev(netdev);
4070 dev_err(priv->dev, "probe register netdev fail!\n");
4071 goto out_reg_netdev_fail;
4074 ret = hns3_client_start(handle);
4076 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
4077 goto out_client_start;
4080 hns3_dcbnl_setup(handle);
4082 hns3_dbg_init(handle);
4084 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */
4085 netdev->max_mtu = HNS3_MAX_MTU;
4087 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4089 if (netif_msg_drv(handle))
4090 hns3_info_show(priv);
4095 unregister_netdev(netdev);
4096 out_reg_netdev_fail:
4097 hns3_uninit_phy(netdev);
4099 hns3_uninit_all_ring(priv);
4101 hns3_nic_uninit_vector_data(priv);
4102 out_init_vector_data:
4103 hns3_nic_dealloc_vector_data(priv);
4104 out_alloc_vector_data:
4105 priv->ring_data = NULL;
4107 priv->ae_handle = NULL;
4108 free_netdev(netdev);
4112 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
4114 struct net_device *netdev = handle->kinfo.netdev;
4115 struct hns3_nic_priv *priv = netdev_priv(netdev);
4118 hns3_remove_hw_addr(netdev);
4120 if (netdev->reg_state != NETREG_UNINITIALIZED)
4121 unregister_netdev(netdev);
4123 hns3_client_stop(handle);
4125 hns3_uninit_phy(netdev);
4127 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
4128 netdev_warn(netdev, "already uninitialized\n");
4129 goto out_netdev_free;
4132 hns3_del_all_fd_rules(netdev, true);
4134 hns3_clear_all_ring(handle, true);
4136 hns3_nic_uninit_vector_data(priv);
4138 ret = hns3_nic_dealloc_vector_data(priv);
4140 netdev_err(netdev, "dealloc vector error\n");
4142 ret = hns3_uninit_all_ring(priv);
4144 netdev_err(netdev, "uninit ring error\n");
4146 hns3_put_ring_config(priv);
4148 hns3_dbg_uninit(handle);
4151 free_netdev(netdev);
4154 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
4156 struct net_device *netdev = handle->kinfo.netdev;
4162 netif_carrier_on(netdev);
4163 netif_tx_wake_all_queues(netdev);
4164 if (netif_msg_link(handle))
4165 netdev_info(netdev, "link up\n");
4167 netif_carrier_off(netdev);
4168 netif_tx_stop_all_queues(netdev);
4169 if (netif_msg_link(handle))
4170 netdev_info(netdev, "link down\n");
4174 static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
4176 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4177 struct net_device *ndev = kinfo->netdev;
4179 if (tc > HNAE3_MAX_TC)
4185 return hns3_nic_set_real_num_queue(ndev);
4188 static int hns3_recover_hw_addr(struct net_device *ndev)
4190 struct netdev_hw_addr_list *list;
4191 struct netdev_hw_addr *ha, *tmp;
4194 netif_addr_lock_bh(ndev);
4195 /* go through and sync uc_addr entries to the device */
4197 list_for_each_entry_safe(ha, tmp, &list->list, list) {
4198 ret = hns3_nic_uc_sync(ndev, ha->addr);
4203 /* go through and sync mc_addr entries to the device */
4205 list_for_each_entry_safe(ha, tmp, &list->list, list) {
4206 ret = hns3_nic_mc_sync(ndev, ha->addr);
4212 netif_addr_unlock_bh(ndev);
4216 static void hns3_remove_hw_addr(struct net_device *netdev)
4218 struct netdev_hw_addr_list *list;
4219 struct netdev_hw_addr *ha, *tmp;
4221 hns3_nic_uc_unsync(netdev, netdev->dev_addr);
4223 netif_addr_lock_bh(netdev);
4224 /* go through and unsync uc_addr entries to the device */
4226 list_for_each_entry_safe(ha, tmp, &list->list, list)
4227 hns3_nic_uc_unsync(netdev, ha->addr);
4229 /* go through and unsync mc_addr entries to the device */
4231 list_for_each_entry_safe(ha, tmp, &list->list, list)
4232 if (ha->refcount > 1)
4233 hns3_nic_mc_unsync(netdev, ha->addr);
4235 netif_addr_unlock_bh(netdev);
4238 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
4240 while (ring->next_to_clean != ring->next_to_use) {
4241 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
4242 hns3_free_buffer_detach(ring, ring->next_to_clean);
4243 ring_ptr_move_fw(ring, next_to_clean);
4247 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
4249 struct hns3_desc_cb res_cbs;
4252 while (ring->next_to_use != ring->next_to_clean) {
4253 /* When a buffer is not reused, it's memory has been
4254 * freed in hns3_handle_rx_bd or will be freed by
4255 * stack, so we need to replace the buffer here.
4257 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4258 ret = hns3_reserve_buffer_map(ring, &res_cbs);
4260 u64_stats_update_begin(&ring->syncp);
4261 ring->stats.sw_err_cnt++;
4262 u64_stats_update_end(&ring->syncp);
4263 /* if alloc new buffer fail, exit directly
4264 * and reclear in up flow.
4266 netdev_warn(ring->tqp->handle->kinfo.netdev,
4267 "reserve buffer map failed, ret = %d\n",
4271 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
4273 ring_ptr_move_fw(ring, next_to_use);
4276 /* Free the pending skb in rx ring */
4278 dev_kfree_skb_any(ring->skb);
4280 ring->pending_buf = 0;
4286 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
4288 while (ring->next_to_use != ring->next_to_clean) {
4289 /* When a buffer is not reused, it's memory has been
4290 * freed in hns3_handle_rx_bd or will be freed by
4291 * stack, so only need to unmap the buffer here.
4293 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4294 hns3_unmap_buffer(ring,
4295 &ring->desc_cb[ring->next_to_use]);
4296 ring->desc_cb[ring->next_to_use].dma = 0;
4299 ring_ptr_move_fw(ring, next_to_use);
4303 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force)
4305 struct net_device *ndev = h->kinfo.netdev;
4306 struct hns3_nic_priv *priv = netdev_priv(ndev);
4309 for (i = 0; i < h->kinfo.num_tqps; i++) {
4310 struct hns3_enet_ring *ring;
4312 ring = priv->ring_data[i].ring;
4313 hns3_clear_tx_ring(ring);
4315 ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
4316 /* Continue to clear other rings even if clearing some
4320 hns3_force_clear_rx_ring(ring);
4322 hns3_clear_rx_ring(ring);
4326 int hns3_nic_reset_all_ring(struct hnae3_handle *h)
4328 struct net_device *ndev = h->kinfo.netdev;
4329 struct hns3_nic_priv *priv = netdev_priv(ndev);
4330 struct hns3_enet_ring *rx_ring;
4334 for (i = 0; i < h->kinfo.num_tqps; i++) {
4335 ret = h->ae_algo->ops->reset_queue(h, i);
4339 hns3_init_ring_hw(priv->ring_data[i].ring);
4341 /* We need to clear tx ring here because self test will
4342 * use the ring and will not run down before up
4344 hns3_clear_tx_ring(priv->ring_data[i].ring);
4345 priv->ring_data[i].ring->next_to_clean = 0;
4346 priv->ring_data[i].ring->next_to_use = 0;
4348 rx_ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
4349 hns3_init_ring_hw(rx_ring);
4350 ret = hns3_clear_rx_ring(rx_ring);
4354 /* We can not know the hardware head and tail when this
4355 * function is called in reset flow, so we reuse all desc.
4357 for (j = 0; j < rx_ring->desc_num; j++)
4358 hns3_reuse_buffer(rx_ring, j);
4360 rx_ring->next_to_clean = 0;
4361 rx_ring->next_to_use = 0;
4364 hns3_init_tx_ring_tc(priv);
4369 static void hns3_store_coal(struct hns3_nic_priv *priv)
4371 /* ethtool only support setting and querying one coal
4372 * configuration for now, so save the vector 0' coal
4373 * configuration here in order to restore it.
4375 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal,
4376 sizeof(struct hns3_enet_coalesce));
4377 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal,
4378 sizeof(struct hns3_enet_coalesce));
4381 static void hns3_restore_coal(struct hns3_nic_priv *priv)
4383 u16 vector_num = priv->vector_num;
4386 for (i = 0; i < vector_num; i++) {
4387 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal,
4388 sizeof(struct hns3_enet_coalesce));
4389 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal,
4390 sizeof(struct hns3_enet_coalesce));
4394 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
4396 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
4397 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4398 struct net_device *ndev = kinfo->netdev;
4399 struct hns3_nic_priv *priv = netdev_priv(ndev);
4401 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
4404 /* it is cumbersome for hardware to pick-and-choose entries for deletion
4405 * from table space. Hence, for function reset software intervention is
4406 * required to delete the entries
4408 if (hns3_dev_ongoing_func_reset(ae_dev)) {
4409 hns3_remove_hw_addr(ndev);
4410 hns3_del_all_fd_rules(ndev, false);
4413 if (!netif_running(ndev))
4416 return hns3_nic_net_stop(ndev);
4419 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
4421 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4422 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
4425 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
4427 if (netif_running(kinfo->netdev)) {
4428 ret = hns3_nic_net_open(kinfo->netdev);
4430 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
4431 netdev_err(kinfo->netdev,
4432 "net up fail, ret=%d!\n", ret);
4440 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
4442 struct net_device *netdev = handle->kinfo.netdev;
4443 struct hns3_nic_priv *priv = netdev_priv(netdev);
4446 /* Carrier off reporting is important to ethtool even BEFORE open */
4447 netif_carrier_off(netdev);
4449 ret = hns3_get_ring_config(priv);
4453 ret = hns3_nic_alloc_vector_data(priv);
4457 hns3_restore_coal(priv);
4459 ret = hns3_nic_init_vector_data(priv);
4461 goto err_dealloc_vector;
4463 ret = hns3_init_all_ring(priv);
4465 goto err_uninit_vector;
4467 ret = hns3_client_start(handle);
4469 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
4470 goto err_uninit_ring;
4473 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4478 hns3_uninit_all_ring(priv);
4480 hns3_nic_uninit_vector_data(priv);
4482 hns3_nic_dealloc_vector_data(priv);
4484 hns3_put_ring_config(priv);
4489 static int hns3_reset_notify_restore_enet(struct hnae3_handle *handle)
4491 struct net_device *netdev = handle->kinfo.netdev;
4492 bool vlan_filter_enable;
4495 ret = hns3_init_mac_addr(netdev);
4499 ret = hns3_recover_hw_addr(netdev);
4503 ret = hns3_update_promisc_mode(netdev, handle->netdev_flags);
4507 vlan_filter_enable = netdev->flags & IFF_PROMISC ? false : true;
4508 hns3_enable_vlan_filter(netdev, vlan_filter_enable);
4510 if (handle->ae_algo->ops->restore_vlan_table)
4511 handle->ae_algo->ops->restore_vlan_table(handle);
4513 return hns3_restore_fd_rules(netdev);
4516 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
4518 struct net_device *netdev = handle->kinfo.netdev;
4519 struct hns3_nic_priv *priv = netdev_priv(netdev);
4522 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
4523 netdev_warn(netdev, "already uninitialized\n");
4527 hns3_clear_all_ring(handle, true);
4528 hns3_reset_tx_queue(priv->ae_handle);
4530 hns3_nic_uninit_vector_data(priv);
4532 hns3_store_coal(priv);
4534 ret = hns3_nic_dealloc_vector_data(priv);
4536 netdev_err(netdev, "dealloc vector error\n");
4538 ret = hns3_uninit_all_ring(priv);
4540 netdev_err(netdev, "uninit ring error\n");
4542 hns3_put_ring_config(priv);
4547 static int hns3_reset_notify(struct hnae3_handle *handle,
4548 enum hnae3_reset_notify_type type)
4553 case HNAE3_UP_CLIENT:
4554 ret = hns3_reset_notify_up_enet(handle);
4556 case HNAE3_DOWN_CLIENT:
4557 ret = hns3_reset_notify_down_enet(handle);
4559 case HNAE3_INIT_CLIENT:
4560 ret = hns3_reset_notify_init_enet(handle);
4562 case HNAE3_UNINIT_CLIENT:
4563 ret = hns3_reset_notify_uninit_enet(handle);
4565 case HNAE3_RESTORE_CLIENT:
4566 ret = hns3_reset_notify_restore_enet(handle);
4575 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num,
4576 bool rxfh_configured)
4580 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num,
4583 dev_err(&handle->pdev->dev,
4584 "Change tqp num(%u) fail.\n", new_tqp_num);
4588 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT);
4592 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT);
4594 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT);
4599 int hns3_set_channels(struct net_device *netdev,
4600 struct ethtool_channels *ch)
4602 struct hnae3_handle *h = hns3_get_handle(netdev);
4603 struct hnae3_knic_private_info *kinfo = &h->kinfo;
4604 bool rxfh_configured = netif_is_rxfh_configured(netdev);
4605 u32 new_tqp_num = ch->combined_count;
4609 if (hns3_nic_resetting(netdev))
4612 if (ch->rx_count || ch->tx_count)
4615 if (new_tqp_num > hns3_get_max_available_channels(h) ||
4617 dev_err(&netdev->dev,
4618 "Change tqps fail, the tqp range is from 1 to %d",
4619 hns3_get_max_available_channels(h));
4623 if (kinfo->rss_size == new_tqp_num)
4626 netif_dbg(h, drv, netdev,
4627 "set channels: tqp_num=%u, rxfh=%d\n",
4628 new_tqp_num, rxfh_configured);
4630 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
4634 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
4638 org_tqp_num = h->kinfo.num_tqps;
4639 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured);
4644 "Change channels fail, revert to old value\n");
4645 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured);
4648 "revert to old channel fail\n");
4658 static const struct hns3_hw_error_info hns3_hw_err[] = {
4659 { .type = HNAE3_PPU_POISON_ERROR,
4660 .msg = "PPU poison" },
4661 { .type = HNAE3_CMDQ_ECC_ERROR,
4662 .msg = "IMP CMDQ error" },
4663 { .type = HNAE3_IMP_RD_POISON_ERROR,
4664 .msg = "IMP RD poison" },
4667 static void hns3_process_hw_error(struct hnae3_handle *handle,
4668 enum hnae3_hw_error_type type)
4672 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) {
4673 if (hns3_hw_err[i].type == type) {
4674 dev_err(&handle->pdev->dev, "Detected %s!\n",
4675 hns3_hw_err[i].msg);
4681 static const struct hnae3_client_ops client_ops = {
4682 .init_instance = hns3_client_init,
4683 .uninit_instance = hns3_client_uninit,
4684 .link_status_change = hns3_link_status_change,
4685 .setup_tc = hns3_client_setup_tc,
4686 .reset_notify = hns3_reset_notify,
4687 .process_hw_error = hns3_process_hw_error,
4690 /* hns3_init_module - Driver registration routine
4691 * hns3_init_module is the first routine called when the driver is
4692 * loaded. All it does is register with the PCI subsystem.
4694 static int __init hns3_init_module(void)
4698 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
4699 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
4701 client.type = HNAE3_CLIENT_KNIC;
4702 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s",
4705 client.ops = &client_ops;
4707 INIT_LIST_HEAD(&client.node);
4709 hns3_dbg_register_debugfs(hns3_driver_name);
4711 ret = hnae3_register_client(&client);
4713 goto err_reg_client;
4715 ret = pci_register_driver(&hns3_driver);
4717 goto err_reg_driver;
4722 hnae3_unregister_client(&client);
4724 hns3_dbg_unregister_debugfs();
4727 module_init(hns3_init_module);
4729 /* hns3_exit_module - Driver exit cleanup routine
4730 * hns3_exit_module is called just before the driver is removed
4733 static void __exit hns3_exit_module(void)
4735 pci_unregister_driver(&hns3_driver);
4736 hnae3_unregister_client(&client);
4737 hns3_dbg_unregister_debugfs();
4739 module_exit(hns3_exit_module);
4741 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
4742 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
4743 MODULE_LICENSE("GPL");
4744 MODULE_ALIAS("pci:hns-nic");
4745 MODULE_VERSION(HNS3_MOD_VERSION);