drivers/net/ethernet/hisilicon/hns3/hns3_enet.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4 #include <linux/dma-mapping.h>
   5 #include <linux/etherdevice.h>
   6 #include <linux/interrupt.h>
   7 #ifdef CONFIG_RFS_ACCEL
   8 #include <linux/cpu_rmap.h>
   9 #endif
  10 #include <linux/if_vlan.h>
  11 #include <linux/irq.h>
  12 #include <linux/ip.h>
  13 #include <linux/ipv6.h>
  14 #include <linux/module.h>
  15 #include <linux/pci.h>
  16 #include <linux/aer.h>
  17 #include <linux/skbuff.h>
  18 #include <linux/sctp.h>
  19 #include <net/gre.h>
  20 #include <net/ip6_checksum.h>
  21 #include <net/pkt_cls.h>
  22 #include <net/tcp.h>
  23 #include <net/vxlan.h>
  24 #include <net/geneve.h>
  25
  26 #include "hnae3.h"
  27 #include "hns3_enet.h"
  28 /* All hns3 tracepoints are defined by the include below, which
  29  * must be included exactly once across the whole kernel with
  30  * CREATE_TRACE_POINTS defined
  31  */
  32 #define CREATE_TRACE_POINTS
  33 #include "hns3_trace.h"
  34
  35 #define hns3_set_field(origin, shift, val)      ((origin) |= (val) << (shift))
  36 #define hns3_tx_bd_count(S)     DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
  37
  38 #define hns3_rl_err(fmt, ...)                                           \
  39         do {                                                            \
  40                 if (net_ratelimit())                                    \
  41                         netdev_err(fmt, ##__VA_ARGS__);                 \
  42         } while (0)
  43
  44 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force);
  45
  46 static const char hns3_driver_name[] = "hns3";
  47 static const char hns3_driver_string[] =
  48                         "Hisilicon Ethernet Network Driver for Hip08 Family";
  49 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
  50 static struct hnae3_client client;
  51
  52 static int debug = -1;
  53 module_param(debug, int, 0);
  54 MODULE_PARM_DESC(debug, " Network interface message level setting");
  55
  56 static unsigned int tx_spare_buf_size;
  57 module_param(tx_spare_buf_size, uint, 0400);
  58 MODULE_PARM_DESC(tx_spare_buf_size, "Size used to allocate tx spare buffer");
  59
  60 static unsigned int tx_sgl = 1;
  61 module_param(tx_sgl, uint, 0600);
  62 MODULE_PARM_DESC(tx_sgl, "Minimum number of frags when using dma_map_sg() to optimize the IOMMU mapping");
  63
  64 static bool page_pool_enabled = true;
  65 module_param(page_pool_enabled, bool, 0400);
  66
  67 #define HNS3_SGL_SIZE(nfrag)    (sizeof(struct scatterlist) * (nfrag) + \
  68                                  sizeof(struct sg_table))
  69 #define HNS3_MAX_SGL_SIZE       ALIGN(HNS3_SGL_SIZE(HNS3_MAX_TSO_BD_NUM), \
  70                                       dma_get_cache_alignment())
  71
  72 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
  73                            NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
  74
  75 #define HNS3_INNER_VLAN_TAG     1
  76 #define HNS3_OUTER_VLAN_TAG     2
  77
  78 #define HNS3_MIN_TX_LEN         33U
  79
  80 /* hns3_pci_tbl - PCI Device ID Table
  81  *
  82  * Last entry must be all 0s
  83  *
  84  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  85  *   Class, Class Mask, private data (not used) }
  86  */
  87 static const struct pci_device_id hns3_pci_tbl[] = {
  88         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
  89         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
  90         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
  91          HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
  92         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
  93          HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
  94         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
  95          HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
  96         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
  97          HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
  98         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
  99          HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
 100         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA),
 101          HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
 102         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0},
 103         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
 104          HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
 105         /* required last entry */
 106         {0,}
 107 };
 108 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
 109
 110 #define HNS3_RX_PTYPE_ENTRY(ptype, l, s, t) \
 111         {       ptype, \
 112                 l, \
 113                 CHECKSUM_##s, \
 114                 HNS3_L3_TYPE_##t, \
 115                 1 }
 116
 117 #define HNS3_RX_PTYPE_UNUSED_ENTRY(ptype) \
 118                 { ptype, 0, CHECKSUM_NONE, HNS3_L3_TYPE_PARSE_FAIL, 0 }
 119
 120 static const struct hns3_rx_ptype hns3_rx_ptype_tbl[] = {
 121         HNS3_RX_PTYPE_UNUSED_ENTRY(0),
 122         HNS3_RX_PTYPE_ENTRY(1, 0, COMPLETE, ARP),
 123         HNS3_RX_PTYPE_ENTRY(2, 0, COMPLETE, RARP),
 124         HNS3_RX_PTYPE_ENTRY(3, 0, COMPLETE, LLDP),
 125         HNS3_RX_PTYPE_ENTRY(4, 0, COMPLETE, PARSE_FAIL),
 126         HNS3_RX_PTYPE_ENTRY(5, 0, COMPLETE, PARSE_FAIL),
 127         HNS3_RX_PTYPE_ENTRY(6, 0, COMPLETE, PARSE_FAIL),
 128         HNS3_RX_PTYPE_ENTRY(7, 0, COMPLETE, CNM),
 129         HNS3_RX_PTYPE_ENTRY(8, 0, NONE, PARSE_FAIL),
 130         HNS3_RX_PTYPE_UNUSED_ENTRY(9),
 131         HNS3_RX_PTYPE_UNUSED_ENTRY(10),
 132         HNS3_RX_PTYPE_UNUSED_ENTRY(11),
 133         HNS3_RX_PTYPE_UNUSED_ENTRY(12),
 134         HNS3_RX_PTYPE_UNUSED_ENTRY(13),
 135         HNS3_RX_PTYPE_UNUSED_ENTRY(14),
 136         HNS3_RX_PTYPE_UNUSED_ENTRY(15),
 137         HNS3_RX_PTYPE_ENTRY(16, 0, COMPLETE, PARSE_FAIL),
 138         HNS3_RX_PTYPE_ENTRY(17, 0, COMPLETE, IPV4),
 139         HNS3_RX_PTYPE_ENTRY(18, 0, COMPLETE, IPV4),
 140         HNS3_RX_PTYPE_ENTRY(19, 0, UNNECESSARY, IPV4),
 141         HNS3_RX_PTYPE_ENTRY(20, 0, UNNECESSARY, IPV4),
 142         HNS3_RX_PTYPE_ENTRY(21, 0, NONE, IPV4),
 143         HNS3_RX_PTYPE_ENTRY(22, 0, UNNECESSARY, IPV4),
 144         HNS3_RX_PTYPE_ENTRY(23, 0, NONE, IPV4),
 145         HNS3_RX_PTYPE_ENTRY(24, 0, NONE, IPV4),
 146         HNS3_RX_PTYPE_ENTRY(25, 0, UNNECESSARY, IPV4),
 147         HNS3_RX_PTYPE_UNUSED_ENTRY(26),
 148         HNS3_RX_PTYPE_UNUSED_ENTRY(27),
 149         HNS3_RX_PTYPE_UNUSED_ENTRY(28),
 150         HNS3_RX_PTYPE_ENTRY(29, 0, COMPLETE, PARSE_FAIL),
 151         HNS3_RX_PTYPE_ENTRY(30, 0, COMPLETE, PARSE_FAIL),
 152         HNS3_RX_PTYPE_ENTRY(31, 0, COMPLETE, IPV4),
 153         HNS3_RX_PTYPE_ENTRY(32, 0, COMPLETE, IPV4),
 154         HNS3_RX_PTYPE_ENTRY(33, 1, UNNECESSARY, IPV4),
 155         HNS3_RX_PTYPE_ENTRY(34, 1, UNNECESSARY, IPV4),
 156         HNS3_RX_PTYPE_ENTRY(35, 1, UNNECESSARY, IPV4),
 157         HNS3_RX_PTYPE_ENTRY(36, 0, COMPLETE, IPV4),
 158         HNS3_RX_PTYPE_ENTRY(37, 0, COMPLETE, IPV4),
 159         HNS3_RX_PTYPE_UNUSED_ENTRY(38),
 160         HNS3_RX_PTYPE_ENTRY(39, 0, COMPLETE, IPV6),
 161         HNS3_RX_PTYPE_ENTRY(40, 0, COMPLETE, IPV6),
 162         HNS3_RX_PTYPE_ENTRY(41, 1, UNNECESSARY, IPV6),
 163         HNS3_RX_PTYPE_ENTRY(42, 1, UNNECESSARY, IPV6),
 164         HNS3_RX_PTYPE_ENTRY(43, 1, UNNECESSARY, IPV6),
 165         HNS3_RX_PTYPE_ENTRY(44, 0, COMPLETE, IPV6),
 166         HNS3_RX_PTYPE_ENTRY(45, 0, COMPLETE, IPV6),
 167         HNS3_RX_PTYPE_UNUSED_ENTRY(46),
 168         HNS3_RX_PTYPE_UNUSED_ENTRY(47),
 169         HNS3_RX_PTYPE_UNUSED_ENTRY(48),
 170         HNS3_RX_PTYPE_UNUSED_ENTRY(49),
 171         HNS3_RX_PTYPE_UNUSED_ENTRY(50),
 172         HNS3_RX_PTYPE_UNUSED_ENTRY(51),
 173         HNS3_RX_PTYPE_UNUSED_ENTRY(52),
 174         HNS3_RX_PTYPE_UNUSED_ENTRY(53),
 175         HNS3_RX_PTYPE_UNUSED_ENTRY(54),
 176         HNS3_RX_PTYPE_UNUSED_ENTRY(55),
 177         HNS3_RX_PTYPE_UNUSED_ENTRY(56),
 178         HNS3_RX_PTYPE_UNUSED_ENTRY(57),
 179         HNS3_RX_PTYPE_UNUSED_ENTRY(58),
 180         HNS3_RX_PTYPE_UNUSED_ENTRY(59),
 181         HNS3_RX_PTYPE_UNUSED_ENTRY(60),
 182         HNS3_RX_PTYPE_UNUSED_ENTRY(61),
 183         HNS3_RX_PTYPE_UNUSED_ENTRY(62),
 184         HNS3_RX_PTYPE_UNUSED_ENTRY(63),
 185         HNS3_RX_PTYPE_UNUSED_ENTRY(64),
 186         HNS3_RX_PTYPE_UNUSED_ENTRY(65),
 187         HNS3_RX_PTYPE_UNUSED_ENTRY(66),
 188         HNS3_RX_PTYPE_UNUSED_ENTRY(67),
 189         HNS3_RX_PTYPE_UNUSED_ENTRY(68),
 190         HNS3_RX_PTYPE_UNUSED_ENTRY(69),
 191         HNS3_RX_PTYPE_UNUSED_ENTRY(70),
 192         HNS3_RX_PTYPE_UNUSED_ENTRY(71),
 193         HNS3_RX_PTYPE_UNUSED_ENTRY(72),
 194         HNS3_RX_PTYPE_UNUSED_ENTRY(73),
 195         HNS3_RX_PTYPE_UNUSED_ENTRY(74),
 196         HNS3_RX_PTYPE_UNUSED_ENTRY(75),
 197         HNS3_RX_PTYPE_UNUSED_ENTRY(76),
 198         HNS3_RX_PTYPE_UNUSED_ENTRY(77),
 199         HNS3_RX_PTYPE_UNUSED_ENTRY(78),
 200         HNS3_RX_PTYPE_UNUSED_ENTRY(79),
 201         HNS3_RX_PTYPE_UNUSED_ENTRY(80),
 202         HNS3_RX_PTYPE_UNUSED_ENTRY(81),
 203         HNS3_RX_PTYPE_UNUSED_ENTRY(82),
 204         HNS3_RX_PTYPE_UNUSED_ENTRY(83),
 205         HNS3_RX_PTYPE_UNUSED_ENTRY(84),
 206         HNS3_RX_PTYPE_UNUSED_ENTRY(85),
 207         HNS3_RX_PTYPE_UNUSED_ENTRY(86),
 208         HNS3_RX_PTYPE_UNUSED_ENTRY(87),
 209         HNS3_RX_PTYPE_UNUSED_ENTRY(88),
 210         HNS3_RX_PTYPE_UNUSED_ENTRY(89),
 211         HNS3_RX_PTYPE_UNUSED_ENTRY(90),
 212         HNS3_RX_PTYPE_UNUSED_ENTRY(91),
 213         HNS3_RX_PTYPE_UNUSED_ENTRY(92),
 214         HNS3_RX_PTYPE_UNUSED_ENTRY(93),
 215         HNS3_RX_PTYPE_UNUSED_ENTRY(94),
 216         HNS3_RX_PTYPE_UNUSED_ENTRY(95),
 217         HNS3_RX_PTYPE_UNUSED_ENTRY(96),
 218         HNS3_RX_PTYPE_UNUSED_ENTRY(97),
 219         HNS3_RX_PTYPE_UNUSED_ENTRY(98),
 220         HNS3_RX_PTYPE_UNUSED_ENTRY(99),
 221         HNS3_RX_PTYPE_UNUSED_ENTRY(100),
 222         HNS3_RX_PTYPE_UNUSED_ENTRY(101),
 223         HNS3_RX_PTYPE_UNUSED_ENTRY(102),
 224         HNS3_RX_PTYPE_UNUSED_ENTRY(103),
 225         HNS3_RX_PTYPE_UNUSED_ENTRY(104),
 226         HNS3_RX_PTYPE_UNUSED_ENTRY(105),
 227         HNS3_RX_PTYPE_UNUSED_ENTRY(106),
 228         HNS3_RX_PTYPE_UNUSED_ENTRY(107),
 229         HNS3_RX_PTYPE_UNUSED_ENTRY(108),
 230         HNS3_RX_PTYPE_UNUSED_ENTRY(109),
 231         HNS3_RX_PTYPE_UNUSED_ENTRY(110),
 232         HNS3_RX_PTYPE_ENTRY(111, 0, COMPLETE, IPV6),
 233         HNS3_RX_PTYPE_ENTRY(112, 0, COMPLETE, IPV6),
 234         HNS3_RX_PTYPE_ENTRY(113, 0, UNNECESSARY, IPV6),
 235         HNS3_RX_PTYPE_ENTRY(114, 0, UNNECESSARY, IPV6),
 236         HNS3_RX_PTYPE_ENTRY(115, 0, NONE, IPV6),
 237         HNS3_RX_PTYPE_ENTRY(116, 0, UNNECESSARY, IPV6),
 238         HNS3_RX_PTYPE_ENTRY(117, 0, NONE, IPV6),
 239         HNS3_RX_PTYPE_ENTRY(118, 0, NONE, IPV6),
 240         HNS3_RX_PTYPE_ENTRY(119, 0, UNNECESSARY, IPV6),
 241         HNS3_RX_PTYPE_UNUSED_ENTRY(120),
 242         HNS3_RX_PTYPE_UNUSED_ENTRY(121),
 243         HNS3_RX_PTYPE_UNUSED_ENTRY(122),
 244         HNS3_RX_PTYPE_ENTRY(123, 0, COMPLETE, PARSE_FAIL),
 245         HNS3_RX_PTYPE_ENTRY(124, 0, COMPLETE, PARSE_FAIL),
 246         HNS3_RX_PTYPE_ENTRY(125, 0, COMPLETE, IPV4),
 247         HNS3_RX_PTYPE_ENTRY(126, 0, COMPLETE, IPV4),
 248         HNS3_RX_PTYPE_ENTRY(127, 1, UNNECESSARY, IPV4),
 249         HNS3_RX_PTYPE_ENTRY(128, 1, UNNECESSARY, IPV4),
 250         HNS3_RX_PTYPE_ENTRY(129, 1, UNNECESSARY, IPV4),
 251         HNS3_RX_PTYPE_ENTRY(130, 0, COMPLETE, IPV4),
 252         HNS3_RX_PTYPE_ENTRY(131, 0, COMPLETE, IPV4),
 253         HNS3_RX_PTYPE_UNUSED_ENTRY(132),
 254         HNS3_RX_PTYPE_ENTRY(133, 0, COMPLETE, IPV6),
 255         HNS3_RX_PTYPE_ENTRY(134, 0, COMPLETE, IPV6),
 256         HNS3_RX_PTYPE_ENTRY(135, 1, UNNECESSARY, IPV6),
 257         HNS3_RX_PTYPE_ENTRY(136, 1, UNNECESSARY, IPV6),
 258         HNS3_RX_PTYPE_ENTRY(137, 1, UNNECESSARY, IPV6),
 259         HNS3_RX_PTYPE_ENTRY(138, 0, COMPLETE, IPV6),
 260         HNS3_RX_PTYPE_ENTRY(139, 0, COMPLETE, IPV6),
 261         HNS3_RX_PTYPE_UNUSED_ENTRY(140),
 262         HNS3_RX_PTYPE_UNUSED_ENTRY(141),
 263         HNS3_RX_PTYPE_UNUSED_ENTRY(142),
 264         HNS3_RX_PTYPE_UNUSED_ENTRY(143),
 265         HNS3_RX_PTYPE_UNUSED_ENTRY(144),
 266         HNS3_RX_PTYPE_UNUSED_ENTRY(145),
 267         HNS3_RX_PTYPE_UNUSED_ENTRY(146),
 268         HNS3_RX_PTYPE_UNUSED_ENTRY(147),
 269         HNS3_RX_PTYPE_UNUSED_ENTRY(148),
 270         HNS3_RX_PTYPE_UNUSED_ENTRY(149),
 271         HNS3_RX_PTYPE_UNUSED_ENTRY(150),
 272         HNS3_RX_PTYPE_UNUSED_ENTRY(151),
 273         HNS3_RX_PTYPE_UNUSED_ENTRY(152),
 274         HNS3_RX_PTYPE_UNUSED_ENTRY(153),
 275         HNS3_RX_PTYPE_UNUSED_ENTRY(154),
 276         HNS3_RX_PTYPE_UNUSED_ENTRY(155),
 277         HNS3_RX_PTYPE_UNUSED_ENTRY(156),
 278         HNS3_RX_PTYPE_UNUSED_ENTRY(157),
 279         HNS3_RX_PTYPE_UNUSED_ENTRY(158),
 280         HNS3_RX_PTYPE_UNUSED_ENTRY(159),
 281         HNS3_RX_PTYPE_UNUSED_ENTRY(160),
 282         HNS3_RX_PTYPE_UNUSED_ENTRY(161),
 283         HNS3_RX_PTYPE_UNUSED_ENTRY(162),
 284         HNS3_RX_PTYPE_UNUSED_ENTRY(163),
 285         HNS3_RX_PTYPE_UNUSED_ENTRY(164),
 286         HNS3_RX_PTYPE_UNUSED_ENTRY(165),
 287         HNS3_RX_PTYPE_UNUSED_ENTRY(166),
 288         HNS3_RX_PTYPE_UNUSED_ENTRY(167),
 289         HNS3_RX_PTYPE_UNUSED_ENTRY(168),
 290         HNS3_RX_PTYPE_UNUSED_ENTRY(169),
 291         HNS3_RX_PTYPE_UNUSED_ENTRY(170),
 292         HNS3_RX_PTYPE_UNUSED_ENTRY(171),
 293         HNS3_RX_PTYPE_UNUSED_ENTRY(172),
 294         HNS3_RX_PTYPE_UNUSED_ENTRY(173),
 295         HNS3_RX_PTYPE_UNUSED_ENTRY(174),
 296         HNS3_RX_PTYPE_UNUSED_ENTRY(175),
 297         HNS3_RX_PTYPE_UNUSED_ENTRY(176),
 298         HNS3_RX_PTYPE_UNUSED_ENTRY(177),
 299         HNS3_RX_PTYPE_UNUSED_ENTRY(178),
 300         HNS3_RX_PTYPE_UNUSED_ENTRY(179),
 301         HNS3_RX_PTYPE_UNUSED_ENTRY(180),
 302         HNS3_RX_PTYPE_UNUSED_ENTRY(181),
 303         HNS3_RX_PTYPE_UNUSED_ENTRY(182),
 304         HNS3_RX_PTYPE_UNUSED_ENTRY(183),
 305         HNS3_RX_PTYPE_UNUSED_ENTRY(184),
 306         HNS3_RX_PTYPE_UNUSED_ENTRY(185),
 307         HNS3_RX_PTYPE_UNUSED_ENTRY(186),
 308         HNS3_RX_PTYPE_UNUSED_ENTRY(187),
 309         HNS3_RX_PTYPE_UNUSED_ENTRY(188),
 310         HNS3_RX_PTYPE_UNUSED_ENTRY(189),
 311         HNS3_RX_PTYPE_UNUSED_ENTRY(190),
 312         HNS3_RX_PTYPE_UNUSED_ENTRY(191),
 313         HNS3_RX_PTYPE_UNUSED_ENTRY(192),
 314         HNS3_RX_PTYPE_UNUSED_ENTRY(193),
 315         HNS3_RX_PTYPE_UNUSED_ENTRY(194),
 316         HNS3_RX_PTYPE_UNUSED_ENTRY(195),
 317         HNS3_RX_PTYPE_UNUSED_ENTRY(196),
 318         HNS3_RX_PTYPE_UNUSED_ENTRY(197),
 319         HNS3_RX_PTYPE_UNUSED_ENTRY(198),
 320         HNS3_RX_PTYPE_UNUSED_ENTRY(199),
 321         HNS3_RX_PTYPE_UNUSED_ENTRY(200),
 322         HNS3_RX_PTYPE_UNUSED_ENTRY(201),
 323         HNS3_RX_PTYPE_UNUSED_ENTRY(202),
 324         HNS3_RX_PTYPE_UNUSED_ENTRY(203),
 325         HNS3_RX_PTYPE_UNUSED_ENTRY(204),
 326         HNS3_RX_PTYPE_UNUSED_ENTRY(205),
 327         HNS3_RX_PTYPE_UNUSED_ENTRY(206),
 328         HNS3_RX_PTYPE_UNUSED_ENTRY(207),
 329         HNS3_RX_PTYPE_UNUSED_ENTRY(208),
 330         HNS3_RX_PTYPE_UNUSED_ENTRY(209),
 331         HNS3_RX_PTYPE_UNUSED_ENTRY(210),
 332         HNS3_RX_PTYPE_UNUSED_ENTRY(211),
 333         HNS3_RX_PTYPE_UNUSED_ENTRY(212),
 334         HNS3_RX_PTYPE_UNUSED_ENTRY(213),
 335         HNS3_RX_PTYPE_UNUSED_ENTRY(214),
 336         HNS3_RX_PTYPE_UNUSED_ENTRY(215),
 337         HNS3_RX_PTYPE_UNUSED_ENTRY(216),
 338         HNS3_RX_PTYPE_UNUSED_ENTRY(217),
 339         HNS3_RX_PTYPE_UNUSED_ENTRY(218),
 340         HNS3_RX_PTYPE_UNUSED_ENTRY(219),
 341         HNS3_RX_PTYPE_UNUSED_ENTRY(220),
 342         HNS3_RX_PTYPE_UNUSED_ENTRY(221),
 343         HNS3_RX_PTYPE_UNUSED_ENTRY(222),
 344         HNS3_RX_PTYPE_UNUSED_ENTRY(223),
 345         HNS3_RX_PTYPE_UNUSED_ENTRY(224),
 346         HNS3_RX_PTYPE_UNUSED_ENTRY(225),
 347         HNS3_RX_PTYPE_UNUSED_ENTRY(226),
 348         HNS3_RX_PTYPE_UNUSED_ENTRY(227),
 349         HNS3_RX_PTYPE_UNUSED_ENTRY(228),
 350         HNS3_RX_PTYPE_UNUSED_ENTRY(229),
 351         HNS3_RX_PTYPE_UNUSED_ENTRY(230),
 352         HNS3_RX_PTYPE_UNUSED_ENTRY(231),
 353         HNS3_RX_PTYPE_UNUSED_ENTRY(232),
 354         HNS3_RX_PTYPE_UNUSED_ENTRY(233),
 355         HNS3_RX_PTYPE_UNUSED_ENTRY(234),
 356         HNS3_RX_PTYPE_UNUSED_ENTRY(235),
 357         HNS3_RX_PTYPE_UNUSED_ENTRY(236),
 358         HNS3_RX_PTYPE_UNUSED_ENTRY(237),
 359         HNS3_RX_PTYPE_UNUSED_ENTRY(238),
 360         HNS3_RX_PTYPE_UNUSED_ENTRY(239),
 361         HNS3_RX_PTYPE_UNUSED_ENTRY(240),
 362         HNS3_RX_PTYPE_UNUSED_ENTRY(241),
 363         HNS3_RX_PTYPE_UNUSED_ENTRY(242),
 364         HNS3_RX_PTYPE_UNUSED_ENTRY(243),
 365         HNS3_RX_PTYPE_UNUSED_ENTRY(244),
 366         HNS3_RX_PTYPE_UNUSED_ENTRY(245),
 367         HNS3_RX_PTYPE_UNUSED_ENTRY(246),
 368         HNS3_RX_PTYPE_UNUSED_ENTRY(247),
 369         HNS3_RX_PTYPE_UNUSED_ENTRY(248),
 370         HNS3_RX_PTYPE_UNUSED_ENTRY(249),
 371         HNS3_RX_PTYPE_UNUSED_ENTRY(250),
 372         HNS3_RX_PTYPE_UNUSED_ENTRY(251),
 373         HNS3_RX_PTYPE_UNUSED_ENTRY(252),
 374         HNS3_RX_PTYPE_UNUSED_ENTRY(253),
 375         HNS3_RX_PTYPE_UNUSED_ENTRY(254),
 376         HNS3_RX_PTYPE_UNUSED_ENTRY(255),
 377 };
 378
 379 #define HNS3_INVALID_PTYPE \
 380                 ARRAY_SIZE(hns3_rx_ptype_tbl)
 381
 382 static irqreturn_t hns3_irq_handle(int irq, void *vector)
 383 {
 384         struct hns3_enet_tqp_vector *tqp_vector = vector;
 385
 386         napi_schedule_irqoff(&tqp_vector->napi);
 387         tqp_vector->event_cnt++;
 388
 389         return IRQ_HANDLED;
 390 }
 391
 392 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
 393 {
 394         struct hns3_enet_tqp_vector *tqp_vectors;
 395         unsigned int i;
 396
 397         for (i = 0; i < priv->vector_num; i++) {
 398                 tqp_vectors = &priv->tqp_vector[i];
 399
 400                 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
 401                         continue;
 402
 403                 /* clear the affinity mask */
 404                 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
 405
 406                 /* release the irq resource */
 407                 free_irq(tqp_vectors->vector_irq, tqp_vectors);
 408                 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
 409         }
 410 }
 411
 412 static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
 413 {
 414         struct hns3_enet_tqp_vector *tqp_vectors;
 415         int txrx_int_idx = 0;
 416         int rx_int_idx = 0;
 417         int tx_int_idx = 0;
 418         unsigned int i;
 419         int ret;
 420
 421         for (i = 0; i < priv->vector_num; i++) {
 422                 tqp_vectors = &priv->tqp_vector[i];
 423
 424                 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
 425                         continue;
 426
 427                 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
 428                         snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
 429                                  "%s-%s-%s-%d", hns3_driver_name,
 430                                  pci_name(priv->ae_handle->pdev),
 431                                  "TxRx", txrx_int_idx++);
 432                         txrx_int_idx++;
 433                 } else if (tqp_vectors->rx_group.ring) {
 434                         snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
 435                                  "%s-%s-%s-%d", hns3_driver_name,
 436                                  pci_name(priv->ae_handle->pdev),
 437                                  "Rx", rx_int_idx++);
 438                 } else if (tqp_vectors->tx_group.ring) {
 439                         snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
 440                                  "%s-%s-%s-%d", hns3_driver_name,
 441                                  pci_name(priv->ae_handle->pdev),
 442                                  "Tx", tx_int_idx++);
 443                 } else {
 444                         /* Skip this unused q_vector */
 445                         continue;
 446                 }
 447
 448                 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
 449
 450                 irq_set_status_flags(tqp_vectors->vector_irq, IRQ_NOAUTOEN);
 451                 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
 452                                   tqp_vectors->name, tqp_vectors);
 453                 if (ret) {
 454                         netdev_err(priv->netdev, "request irq(%d) fail\n",
 455                                    tqp_vectors->vector_irq);
 456                         hns3_nic_uninit_irq(priv);
 457                         return ret;
 458                 }
 459
 460                 irq_set_affinity_hint(tqp_vectors->vector_irq,
 461                                       &tqp_vectors->affinity_mask);
 462
 463                 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
 464         }
 465
 466         return 0;
 467 }
 468
 469 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
 470                                  u32 mask_en)
 471 {
 472         writel(mask_en, tqp_vector->mask_addr);
 473 }
 474
 475 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
 476 {
 477         napi_enable(&tqp_vector->napi);
 478         enable_irq(tqp_vector->vector_irq);
 479
 480         /* enable vector */
 481         hns3_mask_vector_irq(tqp_vector, 1);
 482 }
 483
 484 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
 485 {
 486         /* disable vector */
 487         hns3_mask_vector_irq(tqp_vector, 0);
 488
 489         disable_irq(tqp_vector->vector_irq);
 490         napi_disable(&tqp_vector->napi);
 491         cancel_work_sync(&tqp_vector->rx_group.dim.work);
 492         cancel_work_sync(&tqp_vector->tx_group.dim.work);
 493 }
 494
 495 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
 496                                  u32 rl_value)
 497 {
 498         u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
 499
 500         /* this defines the configuration for RL (Interrupt Rate Limiter).
 501          * Rl defines rate of interrupts i.e. number of interrupts-per-second
 502          * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
 503          */
 504         if (rl_reg > 0 && !tqp_vector->tx_group.coal.adapt_enable &&
 505             !tqp_vector->rx_group.coal.adapt_enable)
 506                 /* According to the hardware, the range of rl_reg is
 507                  * 0-59 and the unit is 4.
 508                  */
 509                 rl_reg |=  HNS3_INT_RL_ENABLE_MASK;
 510
 511         writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
 512 }
 513
 514 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
 515                                     u32 gl_value)
 516 {
 517         u32 new_val;
 518
 519         if (tqp_vector->rx_group.coal.unit_1us)
 520                 new_val = gl_value | HNS3_INT_GL_1US;
 521         else
 522                 new_val = hns3_gl_usec_to_reg(gl_value);
 523
 524         writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
 525 }
 526
 527 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
 528                                     u32 gl_value)
 529 {
 530         u32 new_val;
 531
 532         if (tqp_vector->tx_group.coal.unit_1us)
 533                 new_val = gl_value | HNS3_INT_GL_1US;
 534         else
 535                 new_val = hns3_gl_usec_to_reg(gl_value);
 536
 537         writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
 538 }
 539
 540 void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector,
 541                                     u32 ql_value)
 542 {
 543         writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_TX_QL_OFFSET);
 544 }
 545
 546 void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector,
 547                                     u32 ql_value)
 548 {
 549         writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_RX_QL_OFFSET);
 550 }
 551
 552 static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector,
 553                                       struct hns3_nic_priv *priv)
 554 {
 555         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
 556         struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
 557         struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
 558         struct hns3_enet_coalesce *ptx_coal = &priv->tx_coal;
 559         struct hns3_enet_coalesce *prx_coal = &priv->rx_coal;
 560
 561         tx_coal->adapt_enable = ptx_coal->adapt_enable;
 562         rx_coal->adapt_enable = prx_coal->adapt_enable;
 563
 564         tx_coal->int_gl = ptx_coal->int_gl;
 565         rx_coal->int_gl = prx_coal->int_gl;
 566
 567         rx_coal->flow_level = prx_coal->flow_level;
 568         tx_coal->flow_level = ptx_coal->flow_level;
 569
 570         /* device version above V3(include V3), GL can configure 1us
 571          * unit, so uses 1us unit.
 572          */
 573         if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) {
 574                 tx_coal->unit_1us = 1;
 575                 rx_coal->unit_1us = 1;
 576         }
 577
 578         if (ae_dev->dev_specs.int_ql_max) {
 579                 tx_coal->ql_enable = 1;
 580                 rx_coal->ql_enable = 1;
 581                 tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
 582                 rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
 583                 tx_coal->int_ql = ptx_coal->int_ql;
 584                 rx_coal->int_ql = prx_coal->int_ql;
 585         }
 586 }
 587
 588 static void
 589 hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
 590                              struct hns3_nic_priv *priv)
 591 {
 592         struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
 593         struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
 594         struct hnae3_handle *h = priv->ae_handle;
 595
 596         hns3_set_vector_coalesce_tx_gl(tqp_vector, tx_coal->int_gl);
 597         hns3_set_vector_coalesce_rx_gl(tqp_vector, rx_coal->int_gl);
 598         hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
 599
 600         if (tx_coal->ql_enable)
 601                 hns3_set_vector_coalesce_tx_ql(tqp_vector, tx_coal->int_ql);
 602
 603         if (rx_coal->ql_enable)
 604                 hns3_set_vector_coalesce_rx_ql(tqp_vector, rx_coal->int_ql);
 605 }
 606
 607 static int hns3_nic_set_real_num_queue(struct net_device *netdev)
 608 {
 609         struct hnae3_handle *h = hns3_get_handle(netdev);
 610         struct hnae3_knic_private_info *kinfo = &h->kinfo;
 611         struct hnae3_tc_info *tc_info = &kinfo->tc_info;
 612         unsigned int queue_size = kinfo->num_tqps;
 613         int i, ret;
 614
 615         if (tc_info->num_tc <= 1 && !tc_info->mqprio_active) {
 616                 netdev_reset_tc(netdev);
 617         } else {
 618                 ret = netdev_set_num_tc(netdev, tc_info->num_tc);
 619                 if (ret) {
 620                         netdev_err(netdev,
 621                                    "netdev_set_num_tc fail, ret=%d!\n", ret);
 622                         return ret;
 623                 }
 624
 625                 for (i = 0; i < HNAE3_MAX_TC; i++) {
 626                         if (!test_bit(i, &tc_info->tc_en))
 627                                 continue;
 628
 629                         netdev_set_tc_queue(netdev, i, tc_info->tqp_count[i],
 630                                             tc_info->tqp_offset[i]);
 631                 }
 632         }
 633
 634         ret = netif_set_real_num_tx_queues(netdev, queue_size);
 635         if (ret) {
 636                 netdev_err(netdev,
 637                            "netif_set_real_num_tx_queues fail, ret=%d!\n", ret);
 638                 return ret;
 639         }
 640
 641         ret = netif_set_real_num_rx_queues(netdev, queue_size);
 642         if (ret) {
 643                 netdev_err(netdev,
 644                            "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
 645                 return ret;
 646         }
 647
 648         return 0;
 649 }
 650
 651 u16 hns3_get_max_available_channels(struct hnae3_handle *h)
 652 {
 653         u16 alloc_tqps, max_rss_size, rss_size;
 654
 655         h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
 656         rss_size = alloc_tqps / h->kinfo.tc_info.num_tc;
 657
 658         return min_t(u16, rss_size, max_rss_size);
 659 }
 660
 661 static void hns3_tqp_enable(struct hnae3_queue *tqp)
 662 {
 663         u32 rcb_reg;
 664
 665         rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
 666         rcb_reg |= BIT(HNS3_RING_EN_B);
 667         hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
 668 }
 669
 670 static void hns3_tqp_disable(struct hnae3_queue *tqp)
 671 {
 672         u32 rcb_reg;
 673
 674         rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
 675         rcb_reg &= ~BIT(HNS3_RING_EN_B);
 676         hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
 677 }
 678
 679 static void hns3_free_rx_cpu_rmap(struct net_device *netdev)
 680 {
 681 #ifdef CONFIG_RFS_ACCEL
 682         free_irq_cpu_rmap(netdev->rx_cpu_rmap);
 683         netdev->rx_cpu_rmap = NULL;
 684 #endif
 685 }
 686
 687 static int hns3_set_rx_cpu_rmap(struct net_device *netdev)
 688 {
 689 #ifdef CONFIG_RFS_ACCEL
 690         struct hns3_nic_priv *priv = netdev_priv(netdev);
 691         struct hns3_enet_tqp_vector *tqp_vector;
 692         int i, ret;
 693
 694         if (!netdev->rx_cpu_rmap) {
 695                 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num);
 696                 if (!netdev->rx_cpu_rmap)
 697                         return -ENOMEM;
 698         }
 699
 700         for (i = 0; i < priv->vector_num; i++) {
 701                 tqp_vector = &priv->tqp_vector[i];
 702                 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap,
 703                                        tqp_vector->vector_irq);
 704                 if (ret) {
 705                         hns3_free_rx_cpu_rmap(netdev);
 706                         return ret;
 707                 }
 708         }
 709 #endif
 710         return 0;
 711 }
 712
 713 static int hns3_nic_net_up(struct net_device *netdev)
 714 {
 715         struct hns3_nic_priv *priv = netdev_priv(netdev);
 716         struct hnae3_handle *h = priv->ae_handle;
 717         int i, j;
 718         int ret;
 719
 720         ret = hns3_nic_reset_all_ring(h);
 721         if (ret)
 722                 return ret;
 723
 724         clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
 725
 726         /* enable the vectors */
 727         for (i = 0; i < priv->vector_num; i++)
 728                 hns3_vector_enable(&priv->tqp_vector[i]);
 729
 730         /* enable rcb */
 731         for (j = 0; j < h->kinfo.num_tqps; j++)
 732                 hns3_tqp_enable(h->kinfo.tqp[j]);
 733
 734         /* start the ae_dev */
 735         ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
 736         if (ret) {
 737                 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
 738                 while (j--)
 739                         hns3_tqp_disable(h->kinfo.tqp[j]);
 740
 741                 for (j = i - 1; j >= 0; j--)
 742                         hns3_vector_disable(&priv->tqp_vector[j]);
 743         }
 744
 745         return ret;
 746 }
 747
 748 static void hns3_config_xps(struct hns3_nic_priv *priv)
 749 {
 750         int i;
 751
 752         for (i = 0; i < priv->vector_num; i++) {
 753                 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
 754                 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
 755
 756                 while (ring) {
 757                         int ret;
 758
 759                         ret = netif_set_xps_queue(priv->netdev,
 760                                                   &tqp_vector->affinity_mask,
 761                                                   ring->tqp->tqp_index);
 762                         if (ret)
 763                                 netdev_warn(priv->netdev,
 764                                             "set xps queue failed: %d", ret);
 765
 766                         ring = ring->next;
 767                 }
 768         }
 769 }
 770
 771 static int hns3_nic_net_open(struct net_device *netdev)
 772 {
 773         struct hns3_nic_priv *priv = netdev_priv(netdev);
 774         struct hnae3_handle *h = hns3_get_handle(netdev);
 775         struct hnae3_knic_private_info *kinfo;
 776         int i, ret;
 777
 778         if (hns3_nic_resetting(netdev))
 779                 return -EBUSY;
 780
 781         netif_carrier_off(netdev);
 782
 783         ret = hns3_nic_set_real_num_queue(netdev);
 784         if (ret)
 785                 return ret;
 786
 787         ret = hns3_nic_net_up(netdev);
 788         if (ret) {
 789                 netdev_err(netdev, "net up fail, ret=%d!\n", ret);
 790                 return ret;
 791         }
 792
 793         kinfo = &h->kinfo;
 794         for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
 795                 netdev_set_prio_tc_map(netdev, i, kinfo->tc_info.prio_tc[i]);
 796
 797         if (h->ae_algo->ops->set_timer_task)
 798                 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
 799
 800         hns3_config_xps(priv);
 801
 802         netif_dbg(h, drv, netdev, "net open\n");
 803
 804         return 0;
 805 }
 806
 807 static void hns3_reset_tx_queue(struct hnae3_handle *h)
 808 {
 809         struct net_device *ndev = h->kinfo.netdev;
 810         struct hns3_nic_priv *priv = netdev_priv(ndev);
 811         struct netdev_queue *dev_queue;
 812         u32 i;
 813
 814         for (i = 0; i < h->kinfo.num_tqps; i++) {
 815                 dev_queue = netdev_get_tx_queue(ndev,
 816                                                 priv->ring[i].queue_index);
 817                 netdev_tx_reset_queue(dev_queue);
 818         }
 819 }
 820
 821 static void hns3_nic_net_down(struct net_device *netdev)
 822 {
 823         struct hns3_nic_priv *priv = netdev_priv(netdev);
 824         struct hnae3_handle *h = hns3_get_handle(netdev);
 825         const struct hnae3_ae_ops *ops;
 826         int i;
 827
 828         /* disable vectors */
 829         for (i = 0; i < priv->vector_num; i++)
 830                 hns3_vector_disable(&priv->tqp_vector[i]);
 831
 832         /* disable rcb */
 833         for (i = 0; i < h->kinfo.num_tqps; i++)
 834                 hns3_tqp_disable(h->kinfo.tqp[i]);
 835
 836         /* stop ae_dev */
 837         ops = priv->ae_handle->ae_algo->ops;
 838         if (ops->stop)
 839                 ops->stop(priv->ae_handle);
 840
 841         /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
 842          * during reset process, because driver may not be able
 843          * to disable the ring through firmware when downing the netdev.
 844          */
 845         if (!hns3_nic_resetting(netdev))
 846                 hns3_clear_all_ring(priv->ae_handle, false);
 847
 848         hns3_reset_tx_queue(priv->ae_handle);
 849 }
 850
 851 static int hns3_nic_net_stop(struct net_device *netdev)
 852 {
 853         struct hns3_nic_priv *priv = netdev_priv(netdev);
 854         struct hnae3_handle *h = hns3_get_handle(netdev);
 855
 856         if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
 857                 return 0;
 858
 859         netif_dbg(h, drv, netdev, "net stop\n");
 860
 861         if (h->ae_algo->ops->set_timer_task)
 862                 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
 863
 864         netif_carrier_off(netdev);
 865         netif_tx_disable(netdev);
 866
 867         hns3_nic_net_down(netdev);
 868
 869         return 0;
 870 }
 871
 872 static int hns3_nic_uc_sync(struct net_device *netdev,
 873                             const unsigned char *addr)
 874 {
 875         struct hnae3_handle *h = hns3_get_handle(netdev);
 876
 877         if (h->ae_algo->ops->add_uc_addr)
 878                 return h->ae_algo->ops->add_uc_addr(h, addr);
 879
 880         return 0;
 881 }
 882
 883 static int hns3_nic_uc_unsync(struct net_device *netdev,
 884                               const unsigned char *addr)
 885 {
 886         struct hnae3_handle *h = hns3_get_handle(netdev);
 887
 888         /* need ignore the request of removing device address, because
 889          * we store the device address and other addresses of uc list
 890          * in the function's mac filter list.
 891          */
 892         if (ether_addr_equal(addr, netdev->dev_addr))
 893                 return 0;
 894
 895         if (h->ae_algo->ops->rm_uc_addr)
 896                 return h->ae_algo->ops->rm_uc_addr(h, addr);
 897
 898         return 0;
 899 }
 900
 901 static int hns3_nic_mc_sync(struct net_device *netdev,
 902                             const unsigned char *addr)
 903 {
 904         struct hnae3_handle *h = hns3_get_handle(netdev);
 905
 906         if (h->ae_algo->ops->add_mc_addr)
 907                 return h->ae_algo->ops->add_mc_addr(h, addr);
 908
 909         return 0;
 910 }
 911
 912 static int hns3_nic_mc_unsync(struct net_device *netdev,
 913                               const unsigned char *addr)
 914 {
 915         struct hnae3_handle *h = hns3_get_handle(netdev);
 916
 917         if (h->ae_algo->ops->rm_mc_addr)
 918                 return h->ae_algo->ops->rm_mc_addr(h, addr);
 919
 920         return 0;
 921 }
 922
 923 static u8 hns3_get_netdev_flags(struct net_device *netdev)
 924 {
 925         u8 flags = 0;
 926
 927         if (netdev->flags & IFF_PROMISC)
 928                 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
 929         else if (netdev->flags & IFF_ALLMULTI)
 930                 flags = HNAE3_USER_MPE;
 931
 932         return flags;
 933 }
 934
 935 static void hns3_nic_set_rx_mode(struct net_device *netdev)
 936 {
 937         struct hnae3_handle *h = hns3_get_handle(netdev);
 938         u8 new_flags;
 939
 940         new_flags = hns3_get_netdev_flags(netdev);
 941
 942         __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
 943         __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync);
 944
 945         /* User mode Promisc mode enable and vlan filtering is disabled to
 946          * let all packets in.
 947          */
 948         h->netdev_flags = new_flags;
 949         hns3_request_update_promisc_mode(h);
 950 }
 951
 952 void hns3_request_update_promisc_mode(struct hnae3_handle *handle)
 953 {
 954         const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
 955
 956         if (ops->request_update_promisc_mode)
 957                 ops->request_update_promisc_mode(handle);
 958 }
 959
 960 static u32 hns3_tx_spare_space(struct hns3_enet_ring *ring)
 961 {
 962         struct hns3_tx_spare *tx_spare = ring->tx_spare;
 963         u32 ntc, ntu;
 964
 965         /* This smp_load_acquire() pairs with smp_store_release() in
 966          * hns3_tx_spare_update() called in tx desc cleaning process.
 967          */
 968         ntc = smp_load_acquire(&tx_spare->last_to_clean);
 969         ntu = tx_spare->next_to_use;
 970
 971         if (ntc > ntu)
 972                 return ntc - ntu - 1;
 973
 974         /* The free tx buffer is divided into two part, so pick the
 975          * larger one.
 976          */
 977         return max(ntc, tx_spare->len - ntu) - 1;
 978 }
 979
 980 static void hns3_tx_spare_update(struct hns3_enet_ring *ring)
 981 {
 982         struct hns3_tx_spare *tx_spare = ring->tx_spare;
 983
 984         if (!tx_spare ||
 985             tx_spare->last_to_clean == tx_spare->next_to_clean)
 986                 return;
 987
 988         /* This smp_store_release() pairs with smp_load_acquire() in
 989          * hns3_tx_spare_space() called in xmit process.
 990          */
 991         smp_store_release(&tx_spare->last_to_clean,
 992                           tx_spare->next_to_clean);
 993 }
 994
 995 static bool hns3_can_use_tx_bounce(struct hns3_enet_ring *ring,
 996                                    struct sk_buff *skb,
 997                                    u32 space)
 998 {
 999         u32 len = skb->len <= ring->tx_copybreak ? skb->len :
1000                                 skb_headlen(skb);
1001
1002         if (len > ring->tx_copybreak)
1003                 return false;
1004
1005         if (ALIGN(len, dma_get_cache_alignment()) > space) {
1006                 u64_stats_update_begin(&ring->syncp);
1007                 ring->stats.tx_spare_full++;
1008                 u64_stats_update_end(&ring->syncp);
1009                 return false;
1010         }
1011
1012         return true;
1013 }
1014
1015 static bool hns3_can_use_tx_sgl(struct hns3_enet_ring *ring,
1016                                 struct sk_buff *skb,
1017                                 u32 space)
1018 {
1019         if (skb->len <= ring->tx_copybreak || !tx_sgl ||
1020             (!skb_has_frag_list(skb) &&
1021              skb_shinfo(skb)->nr_frags < tx_sgl))
1022                 return false;
1023
1024         if (space < HNS3_MAX_SGL_SIZE) {
1025                 u64_stats_update_begin(&ring->syncp);
1026                 ring->stats.tx_spare_full++;
1027                 u64_stats_update_end(&ring->syncp);
1028                 return false;
1029         }
1030
1031         return true;
1032 }
1033
1034 static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring)
1035 {
1036         struct hns3_tx_spare *tx_spare;
1037         struct page *page;
1038         u32 alloc_size;
1039         dma_addr_t dma;
1040         int order;
1041
1042         alloc_size = tx_spare_buf_size ? tx_spare_buf_size :
1043                      ring->tqp->handle->kinfo.tx_spare_buf_size;
1044         if (!alloc_size)
1045                 return;
1046
1047         order = get_order(alloc_size);
1048         tx_spare = devm_kzalloc(ring_to_dev(ring), sizeof(*tx_spare),
1049                                 GFP_KERNEL);
1050         if (!tx_spare) {
1051                 /* The driver still work without the tx spare buffer */
1052                 dev_warn(ring_to_dev(ring), "failed to allocate hns3_tx_spare\n");
1053                 return;
1054         }
1055
1056         page = alloc_pages_node(dev_to_node(ring_to_dev(ring)),
1057                                 GFP_KERNEL, order);
1058         if (!page) {
1059                 dev_warn(ring_to_dev(ring), "failed to allocate tx spare pages\n");
1060                 devm_kfree(ring_to_dev(ring), tx_spare);
1061                 return;
1062         }
1063
1064         dma = dma_map_page(ring_to_dev(ring), page, 0,
1065                            PAGE_SIZE << order, DMA_TO_DEVICE);
1066         if (dma_mapping_error(ring_to_dev(ring), dma)) {
1067                 dev_warn(ring_to_dev(ring), "failed to map pages for tx spare\n");
1068                 put_page(page);
1069                 devm_kfree(ring_to_dev(ring), tx_spare);
1070                 return;
1071         }
1072
1073         tx_spare->dma = dma;
1074         tx_spare->buf = page_address(page);
1075         tx_spare->len = PAGE_SIZE << order;
1076         ring->tx_spare = tx_spare;
1077 }
1078
1079 /* Use hns3_tx_spare_space() to make sure there is enough buffer
1080  * before calling below function to allocate tx buffer.
1081  */
1082 static void *hns3_tx_spare_alloc(struct hns3_enet_ring *ring,
1083                                  unsigned int size, dma_addr_t *dma,
1084                                  u32 *cb_len)
1085 {
1086         struct hns3_tx_spare *tx_spare = ring->tx_spare;
1087         u32 ntu = tx_spare->next_to_use;
1088
1089         size = ALIGN(size, dma_get_cache_alignment());
1090         *cb_len = size;
1091
1092         /* Tx spare buffer wraps back here because the end of
1093          * freed tx buffer is not enough.
1094          */
1095         if (ntu + size > tx_spare->len) {
1096                 *cb_len += (tx_spare->len - ntu);
1097                 ntu = 0;
1098         }
1099
1100         tx_spare->next_to_use = ntu + size;
1101         if (tx_spare->next_to_use == tx_spare->len)
1102                 tx_spare->next_to_use = 0;
1103
1104         *dma = tx_spare->dma + ntu;
1105
1106         return tx_spare->buf + ntu;
1107 }
1108
1109 static void hns3_tx_spare_rollback(struct hns3_enet_ring *ring, u32 len)
1110 {
1111         struct hns3_tx_spare *tx_spare = ring->tx_spare;
1112
1113         if (len > tx_spare->next_to_use) {
1114                 len -= tx_spare->next_to_use;
1115                 tx_spare->next_to_use = tx_spare->len - len;
1116         } else {
1117                 tx_spare->next_to_use -= len;
1118         }
1119 }
1120
1121 static void hns3_tx_spare_reclaim_cb(struct hns3_enet_ring *ring,
1122                                      struct hns3_desc_cb *cb)
1123 {
1124         struct hns3_tx_spare *tx_spare = ring->tx_spare;
1125         u32 ntc = tx_spare->next_to_clean;
1126         u32 len = cb->length;
1127
1128         tx_spare->next_to_clean += len;
1129
1130         if (tx_spare->next_to_clean >= tx_spare->len) {
1131                 tx_spare->next_to_clean -= tx_spare->len;
1132
1133                 if (tx_spare->next_to_clean) {
1134                         ntc = 0;
1135                         len = tx_spare->next_to_clean;
1136                 }
1137         }
1138
1139         /* This tx spare buffer is only really reclaimed after calling
1140          * hns3_tx_spare_update(), so it is still safe to use the info in
1141          * the tx buffer to do the dma sync or sg unmapping after
1142          * tx_spare->next_to_clean is moved forword.
1143          */
1144         if (cb->type & (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL)) {
1145                 dma_addr_t dma = tx_spare->dma + ntc;
1146
1147                 dma_sync_single_for_cpu(ring_to_dev(ring), dma, len,
1148                                         DMA_TO_DEVICE);
1149         } else {
1150                 struct sg_table *sgt = tx_spare->buf + ntc;
1151
1152                 dma_unmap_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
1153                              DMA_TO_DEVICE);
1154         }
1155 }
1156
1157 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen_fdop_ol4cs,
1158                         u16 *mss, u32 *type_cs_vlan_tso, u32 *send_bytes)
1159 {
1160         u32 l4_offset, hdr_len;
1161         union l3_hdr_info l3;
1162         union l4_hdr_info l4;
1163         u32 l4_paylen;
1164         int ret;
1165
1166         if (!skb_is_gso(skb))
1167                 return 0;
1168
1169         ret = skb_cow_head(skb, 0);
1170         if (unlikely(ret < 0))
1171                 return ret;
1172
1173         l3.hdr = skb_network_header(skb);
1174         l4.hdr = skb_transport_header(skb);
1175
1176         /* Software should clear the IPv4's checksum field when tso is
1177          * needed.
1178          */
1179         if (l3.v4->version == 4)
1180                 l3.v4->check = 0;
1181
1182         /* tunnel packet */
1183         if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
1184                                          SKB_GSO_GRE_CSUM |
1185                                          SKB_GSO_UDP_TUNNEL |
1186                                          SKB_GSO_UDP_TUNNEL_CSUM)) {
1187                 /* reset l3&l4 pointers from outer to inner headers */
1188                 l3.hdr = skb_inner_network_header(skb);
1189                 l4.hdr = skb_inner_transport_header(skb);
1190
1191                 /* Software should clear the IPv4's checksum field when
1192                  * tso is needed.
1193                  */
1194                 if (l3.v4->version == 4)
1195                         l3.v4->check = 0;
1196         }
1197
1198         /* normal or tunnel packet */
1199         l4_offset = l4.hdr - skb->data;
1200
1201         /* remove payload length from inner pseudo checksum when tso */
1202         l4_paylen = skb->len - l4_offset;
1203
1204         if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
1205                 hdr_len = sizeof(*l4.udp) + l4_offset;
1206                 csum_replace_by_diff(&l4.udp->check,
1207                                      (__force __wsum)htonl(l4_paylen));
1208         } else {
1209                 hdr_len = (l4.tcp->doff << 2) + l4_offset;
1210                 csum_replace_by_diff(&l4.tcp->check,
1211                                      (__force __wsum)htonl(l4_paylen));
1212         }
1213
1214         *send_bytes = (skb_shinfo(skb)->gso_segs - 1) * hdr_len + skb->len;
1215
1216         /* find the txbd field values */
1217         *paylen_fdop_ol4cs = skb->len - hdr_len;
1218         hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
1219
1220         /* offload outer UDP header checksum */
1221         if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)
1222                 hns3_set_field(*paylen_fdop_ol4cs, HNS3_TXD_OL4CS_B, 1);
1223
1224         /* get MSS for TSO */
1225         *mss = skb_shinfo(skb)->gso_size;
1226
1227         trace_hns3_tso(skb);
1228
1229         return 0;
1230 }
1231
1232 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
1233                                 u8 *il4_proto)
1234 {
1235         union l3_hdr_info l3;
1236         unsigned char *l4_hdr;
1237         unsigned char *exthdr;
1238         u8 l4_proto_tmp;
1239         __be16 frag_off;
1240
1241         /* find outer header point */
1242         l3.hdr = skb_network_header(skb);
1243         l4_hdr = skb_transport_header(skb);
1244
1245         if (skb->protocol == htons(ETH_P_IPV6)) {
1246                 exthdr = l3.hdr + sizeof(*l3.v6);
1247                 l4_proto_tmp = l3.v6->nexthdr;
1248                 if (l4_hdr != exthdr)
1249                         ipv6_skip_exthdr(skb, exthdr - skb->data,
1250                                          &l4_proto_tmp, &frag_off);
1251         } else if (skb->protocol == htons(ETH_P_IP)) {
1252                 l4_proto_tmp = l3.v4->protocol;
1253         } else {
1254                 return -EINVAL;
1255         }
1256
1257         *ol4_proto = l4_proto_tmp;
1258
1259         /* tunnel packet */
1260         if (!skb->encapsulation) {
1261                 *il4_proto = 0;
1262                 return 0;
1263         }
1264
1265         /* find inner header point */
1266         l3.hdr = skb_inner_network_header(skb);
1267         l4_hdr = skb_inner_transport_header(skb);
1268
1269         if (l3.v6->version == 6) {
1270                 exthdr = l3.hdr + sizeof(*l3.v6);
1271                 l4_proto_tmp = l3.v6->nexthdr;
1272                 if (l4_hdr != exthdr)
1273                         ipv6_skip_exthdr(skb, exthdr - skb->data,
1274                                          &l4_proto_tmp, &frag_off);
1275         } else if (l3.v4->version == 4) {
1276                 l4_proto_tmp = l3.v4->protocol;
1277         }
1278
1279         *il4_proto = l4_proto_tmp;
1280
1281         return 0;
1282 }
1283
1284 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
1285  * and it is udp packet, which has a dest port as the IANA assigned.
1286  * the hardware is expected to do the checksum offload, but the
1287  * hardware will not do the checksum offload when udp dest port is
1288  * 4789, 4790 or 6081.
1289  */
1290 static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
1291 {
1292         struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1293         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
1294         union l4_hdr_info l4;
1295
1296         /* device version above V3(include V3), the hardware can
1297          * do this checksum offload.
1298          */
1299         if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
1300                 return false;
1301
1302         l4.hdr = skb_transport_header(skb);
1303
1304         if (!(!skb->encapsulation &&
1305               (l4.udp->dest == htons(IANA_VXLAN_UDP_PORT) ||
1306               l4.udp->dest == htons(GENEVE_UDP_PORT) ||
1307               l4.udp->dest == htons(4790))))
1308                 return false;
1309
1310         return true;
1311 }
1312
1313 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
1314                                   u32 *ol_type_vlan_len_msec)
1315 {
1316         u32 l2_len, l3_len, l4_len;
1317         unsigned char *il2_hdr;
1318         union l3_hdr_info l3;
1319         union l4_hdr_info l4;
1320
1321         l3.hdr = skb_network_header(skb);
1322         l4.hdr = skb_transport_header(skb);
1323
1324         /* compute OL2 header size, defined in 2 Bytes */
1325         l2_len = l3.hdr - skb->data;
1326         hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1);
1327
1328         /* compute OL3 header size, defined in 4 Bytes */
1329         l3_len = l4.hdr - l3.hdr;
1330         hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2);
1331
1332         il2_hdr = skb_inner_mac_header(skb);
1333         /* compute OL4 header size, defined in 4 Bytes */
1334         l4_len = il2_hdr - l4.hdr;
1335         hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2);
1336
1337         /* define outer network header type */
1338         if (skb->protocol == htons(ETH_P_IP)) {
1339                 if (skb_is_gso(skb))
1340                         hns3_set_field(*ol_type_vlan_len_msec,
1341                                        HNS3_TXD_OL3T_S,
1342                                        HNS3_OL3T_IPV4_CSUM);
1343                 else
1344                         hns3_set_field(*ol_type_vlan_len_msec,
1345                                        HNS3_TXD_OL3T_S,
1346                                        HNS3_OL3T_IPV4_NO_CSUM);
1347         } else if (skb->protocol == htons(ETH_P_IPV6)) {
1348                 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S,
1349                                HNS3_OL3T_IPV6);
1350         }
1351
1352         if (ol4_proto == IPPROTO_UDP)
1353                 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
1354                                HNS3_TUN_MAC_IN_UDP);
1355         else if (ol4_proto == IPPROTO_GRE)
1356                 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
1357                                HNS3_TUN_NVGRE);
1358 }
1359
1360 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
1361                            u8 il4_proto, u32 *type_cs_vlan_tso,
1362                            u32 *ol_type_vlan_len_msec)
1363 {
1364         unsigned char *l2_hdr = skb->data;
1365         u32 l4_proto = ol4_proto;
1366         union l4_hdr_info l4;
1367         union l3_hdr_info l3;
1368         u32 l2_len, l3_len;
1369
1370         l4.hdr = skb_transport_header(skb);
1371         l3.hdr = skb_network_header(skb);
1372
1373         /* handle encapsulation skb */
1374         if (skb->encapsulation) {
1375                 /* If this is a not UDP/GRE encapsulation skb */
1376                 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) {
1377                         /* drop the skb tunnel packet if hardware don't support,
1378                          * because hardware can't calculate csum when TSO.
1379                          */
1380                         if (skb_is_gso(skb))
1381                                 return -EDOM;
1382
1383                         /* the stack computes the IP header already,
1384                          * driver calculate l4 checksum when not TSO.
1385                          */
1386                         return skb_checksum_help(skb);
1387                 }
1388
1389                 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec);
1390
1391                 /* switch to inner header */
1392                 l2_hdr = skb_inner_mac_header(skb);
1393                 l3.hdr = skb_inner_network_header(skb);
1394                 l4.hdr = skb_inner_transport_header(skb);
1395                 l4_proto = il4_proto;
1396         }
1397
1398         if (l3.v4->version == 4) {
1399                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
1400                                HNS3_L3T_IPV4);
1401
1402                 /* the stack computes the IP header already, the only time we
1403                  * need the hardware to recompute it is in the case of TSO.
1404                  */
1405                 if (skb_is_gso(skb))
1406                         hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
1407         } else if (l3.v6->version == 6) {
1408                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
1409                                HNS3_L3T_IPV6);
1410         }
1411
1412         /* compute inner(/normal) L2 header size, defined in 2 Bytes */
1413         l2_len = l3.hdr - l2_hdr;
1414         hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1);
1415
1416         /* compute inner(/normal) L3 header size, defined in 4 Bytes */
1417         l3_len = l4.hdr - l3.hdr;
1418         hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2);
1419
1420         /* compute inner(/normal) L4 header size, defined in 4 Bytes */
1421         switch (l4_proto) {
1422         case IPPROTO_TCP:
1423                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1424                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1425                                HNS3_L4T_TCP);
1426                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1427                                l4.tcp->doff);
1428                 break;
1429         case IPPROTO_UDP:
1430                 if (hns3_tunnel_csum_bug(skb))
1431                         return skb_checksum_help(skb);
1432
1433                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1434                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1435                                HNS3_L4T_UDP);
1436                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1437                                (sizeof(struct udphdr) >> 2));
1438                 break;
1439         case IPPROTO_SCTP:
1440                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1441                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1442                                HNS3_L4T_SCTP);
1443                 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1444                                (sizeof(struct sctphdr) >> 2));
1445                 break;
1446         default:
1447                 /* drop the skb tunnel packet if hardware don't support,
1448                  * because hardware can't calculate csum when TSO.
1449                  */
1450                 if (skb_is_gso(skb))
1451                         return -EDOM;
1452
1453                 /* the stack computes the IP header already,
1454                  * driver calculate l4 checksum when not TSO.
1455                  */
1456                 return skb_checksum_help(skb);
1457         }
1458
1459         return 0;
1460 }
1461
1462 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring,
1463                              struct sk_buff *skb)
1464 {
1465         struct hnae3_handle *handle = tx_ring->tqp->handle;
1466         struct hnae3_ae_dev *ae_dev;
1467         struct vlan_ethhdr *vhdr;
1468         int rc;
1469
1470         if (!(skb->protocol == htons(ETH_P_8021Q) ||
1471               skb_vlan_tag_present(skb)))
1472                 return 0;
1473
1474         /* For HW limitation on HNAE3_DEVICE_VERSION_V2, if port based insert
1475          * VLAN enabled, only one VLAN header is allowed in skb, otherwise it
1476          * will cause RAS error.
1477          */
1478         ae_dev = pci_get_drvdata(handle->pdev);
1479         if (unlikely(skb_vlan_tagged_multi(skb) &&
1480                      ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 &&
1481                      handle->port_base_vlan_state ==
1482                      HNAE3_PORT_BASE_VLAN_ENABLE))
1483                 return -EINVAL;
1484
1485         if (skb->protocol == htons(ETH_P_8021Q) &&
1486             !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1487                 /* When HW VLAN acceleration is turned off, and the stack
1488                  * sets the protocol to 802.1q, the driver just need to
1489                  * set the protocol to the encapsulated ethertype.
1490                  */
1491                 skb->protocol = vlan_get_protocol(skb);
1492                 return 0;
1493         }
1494
1495         if (skb_vlan_tag_present(skb)) {
1496                 /* Based on hw strategy, use out_vtag in two layer tag case,
1497                  * and use inner_vtag in one tag case.
1498                  */
1499                 if (skb->protocol == htons(ETH_P_8021Q) &&
1500                     handle->port_base_vlan_state ==
1501                     HNAE3_PORT_BASE_VLAN_DISABLE)
1502                         rc = HNS3_OUTER_VLAN_TAG;
1503                 else
1504                         rc = HNS3_INNER_VLAN_TAG;
1505
1506                 skb->protocol = vlan_get_protocol(skb);
1507                 return rc;
1508         }
1509
1510         rc = skb_cow_head(skb, 0);
1511         if (unlikely(rc < 0))
1512                 return rc;
1513
1514         vhdr = (struct vlan_ethhdr *)skb->data;
1515         vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT)
1516                                          & VLAN_PRIO_MASK);
1517
1518         skb->protocol = vlan_get_protocol(skb);
1519         return 0;
1520 }
1521
1522 /* check if the hardware is capable of checksum offloading */
1523 static bool hns3_check_hw_tx_csum(struct sk_buff *skb)
1524 {
1525         struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1526
1527         /* Kindly note, due to backward compatibility of the TX descriptor,
1528          * HW checksum of the non-IP packets and GSO packets is handled at
1529          * different place in the following code
1530          */
1531         if (skb_csum_is_sctp(skb) || skb_is_gso(skb) ||
1532             !test_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state))
1533                 return false;
1534
1535         return true;
1536 }
1537
1538 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
1539                               struct sk_buff *skb, struct hns3_desc *desc,
1540                               struct hns3_desc_cb *desc_cb)
1541 {
1542         u32 ol_type_vlan_len_msec = 0;
1543         u32 paylen_ol4cs = skb->len;
1544         u32 type_cs_vlan_tso = 0;
1545         u16 mss_hw_csum = 0;
1546         u16 inner_vtag = 0;
1547         u16 out_vtag = 0;
1548         int ret;
1549
1550         ret = hns3_handle_vtags(ring, skb);
1551         if (unlikely(ret < 0)) {
1552                 u64_stats_update_begin(&ring->syncp);
1553                 ring->stats.tx_vlan_err++;
1554                 u64_stats_update_end(&ring->syncp);
1555                 return ret;
1556         } else if (ret == HNS3_INNER_VLAN_TAG) {
1557                 inner_vtag = skb_vlan_tag_get(skb);
1558                 inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1559                                 VLAN_PRIO_MASK;
1560                 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1);
1561         } else if (ret == HNS3_OUTER_VLAN_TAG) {
1562                 out_vtag = skb_vlan_tag_get(skb);
1563                 out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1564                                 VLAN_PRIO_MASK;
1565                 hns3_set_field(ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B,
1566                                1);
1567         }
1568
1569         desc_cb->send_bytes = skb->len;
1570
1571         if (skb->ip_summed == CHECKSUM_PARTIAL) {
1572                 u8 ol4_proto, il4_proto;
1573
1574                 if (hns3_check_hw_tx_csum(skb)) {
1575                         /* set checksum start and offset, defined in 2 Bytes */
1576                         hns3_set_field(type_cs_vlan_tso, HNS3_TXD_CSUM_START_S,
1577                                        skb_checksum_start_offset(skb) >> 1);
1578                         hns3_set_field(ol_type_vlan_len_msec,
1579                                        HNS3_TXD_CSUM_OFFSET_S,
1580                                        skb->csum_offset >> 1);
1581                         mss_hw_csum |= BIT(HNS3_TXD_HW_CS_B);
1582                         goto out_hw_tx_csum;
1583                 }
1584
1585                 skb_reset_mac_len(skb);
1586
1587                 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
1588                 if (unlikely(ret < 0)) {
1589                         u64_stats_update_begin(&ring->syncp);
1590                         ring->stats.tx_l4_proto_err++;
1591                         u64_stats_update_end(&ring->syncp);
1592                         return ret;
1593                 }
1594
1595                 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
1596                                       &type_cs_vlan_tso,
1597                                       &ol_type_vlan_len_msec);
1598                 if (unlikely(ret < 0)) {
1599                         u64_stats_update_begin(&ring->syncp);
1600                         ring->stats.tx_l2l3l4_err++;
1601                         u64_stats_update_end(&ring->syncp);
1602                         return ret;
1603                 }
1604
1605                 ret = hns3_set_tso(skb, &paylen_ol4cs, &mss_hw_csum,
1606                                    &type_cs_vlan_tso, &desc_cb->send_bytes);
1607                 if (unlikely(ret < 0)) {
1608                         u64_stats_update_begin(&ring->syncp);
1609                         ring->stats.tx_tso_err++;
1610                         u64_stats_update_end(&ring->syncp);
1611                         return ret;
1612                 }
1613         }
1614
1615 out_hw_tx_csum:
1616         /* Set txbd */
1617         desc->tx.ol_type_vlan_len_msec =
1618                 cpu_to_le32(ol_type_vlan_len_msec);
1619         desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso);
1620         desc->tx.paylen_ol4cs = cpu_to_le32(paylen_ol4cs);
1621         desc->tx.mss_hw_csum = cpu_to_le16(mss_hw_csum);
1622         desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
1623         desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
1624
1625         return 0;
1626 }
1627
1628 static int hns3_fill_desc(struct hns3_enet_ring *ring, dma_addr_t dma,
1629                           unsigned int size)
1630 {
1631 #define HNS3_LIKELY_BD_NUM      1
1632
1633         struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1634         unsigned int frag_buf_num;
1635         int k, sizeoflast;
1636
1637         if (likely(size <= HNS3_MAX_BD_SIZE)) {
1638                 desc->addr = cpu_to_le64(dma);
1639                 desc->tx.send_size = cpu_to_le16(size);
1640                 desc->tx.bdtp_fe_sc_vld_ra_ri =
1641                         cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1642
1643                 trace_hns3_tx_desc(ring, ring->next_to_use);
1644                 ring_ptr_move_fw(ring, next_to_use);
1645                 return HNS3_LIKELY_BD_NUM;
1646         }
1647
1648         frag_buf_num = hns3_tx_bd_count(size);
1649         sizeoflast = size % HNS3_MAX_BD_SIZE;
1650         sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1651
1652         /* When frag size is bigger than hardware limit, split this frag */
1653         for (k = 0; k < frag_buf_num; k++) {
1654                 /* now, fill the descriptor */
1655                 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
1656                 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
1657                                      (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1658                 desc->tx.bdtp_fe_sc_vld_ra_ri =
1659                                 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1660
1661                 trace_hns3_tx_desc(ring, ring->next_to_use);
1662                 /* move ring pointer to next */
1663                 ring_ptr_move_fw(ring, next_to_use);
1664
1665                 desc = &ring->desc[ring->next_to_use];
1666         }
1667
1668         return frag_buf_num;
1669 }
1670
1671 static int hns3_map_and_fill_desc(struct hns3_enet_ring *ring, void *priv,
1672                                   unsigned int type)
1673 {
1674         struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1675         struct device *dev = ring_to_dev(ring);
1676         unsigned int size;
1677         dma_addr_t dma;
1678
1679         if (type & (DESC_TYPE_FRAGLIST_SKB | DESC_TYPE_SKB)) {
1680                 struct sk_buff *skb = (struct sk_buff *)priv;
1681
1682                 size = skb_headlen(skb);
1683                 if (!size)
1684                         return 0;
1685
1686                 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1687         } else if (type & DESC_TYPE_BOUNCE_HEAD) {
1688                 /* Head data has been filled in hns3_handle_tx_bounce(),
1689                  * just return 0 here.
1690                  */
1691                 return 0;
1692         } else {
1693                 skb_frag_t *frag = (skb_frag_t *)priv;
1694
1695                 size = skb_frag_size(frag);
1696                 if (!size)
1697                         return 0;
1698
1699                 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1700         }
1701
1702         if (unlikely(dma_mapping_error(dev, dma))) {
1703                 u64_stats_update_begin(&ring->syncp);
1704                 ring->stats.sw_err_cnt++;
1705                 u64_stats_update_end(&ring->syncp);
1706                 return -ENOMEM;
1707         }
1708
1709         desc_cb->priv = priv;
1710         desc_cb->length = size;
1711         desc_cb->dma = dma;
1712         desc_cb->type = type;
1713
1714         return hns3_fill_desc(ring, dma, size);
1715 }
1716
1717 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1718                                     unsigned int bd_num)
1719 {
1720         unsigned int size;
1721         int i;
1722
1723         size = skb_headlen(skb);
1724         while (size > HNS3_MAX_BD_SIZE) {
1725                 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1726                 size -= HNS3_MAX_BD_SIZE;
1727
1728                 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1729                         return bd_num;
1730         }
1731
1732         if (size) {
1733                 bd_size[bd_num++] = size;
1734                 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1735                         return bd_num;
1736         }
1737
1738         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1739                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1740                 size = skb_frag_size(frag);
1741                 if (!size)
1742                         continue;
1743
1744                 while (size > HNS3_MAX_BD_SIZE) {
1745                         bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1746                         size -= HNS3_MAX_BD_SIZE;
1747
1748                         if (bd_num > HNS3_MAX_TSO_BD_NUM)
1749                                 return bd_num;
1750                 }
1751
1752                 bd_size[bd_num++] = size;
1753                 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1754                         return bd_num;
1755         }
1756
1757         return bd_num;
1758 }
1759
1760 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1761                                    u8 max_non_tso_bd_num, unsigned int bd_num,
1762                                    unsigned int recursion_level)
1763 {
1764 #define HNS3_MAX_RECURSION_LEVEL        24
1765
1766         struct sk_buff *frag_skb;
1767
1768         /* If the total len is within the max bd limit */
1769         if (likely(skb->len <= HNS3_MAX_BD_SIZE && !recursion_level &&
1770                    !skb_has_frag_list(skb) &&
1771                    skb_shinfo(skb)->nr_frags < max_non_tso_bd_num))
1772                 return skb_shinfo(skb)->nr_frags + 1U;
1773
1774         if (unlikely(recursion_level >= HNS3_MAX_RECURSION_LEVEL))
1775                 return UINT_MAX;
1776
1777         bd_num = hns3_skb_bd_num(skb, bd_size, bd_num);
1778         if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM)
1779                 return bd_num;
1780
1781         skb_walk_frags(skb, frag_skb) {
1782                 bd_num = hns3_tx_bd_num(frag_skb, bd_size, max_non_tso_bd_num,
1783                                         bd_num, recursion_level + 1);
1784                 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1785                         return bd_num;
1786         }
1787
1788         return bd_num;
1789 }
1790
1791 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb)
1792 {
1793         if (!skb->encapsulation)
1794                 return skb_transport_offset(skb) + tcp_hdrlen(skb);
1795
1796         return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
1797 }
1798
1799 /* HW need every continuous max_non_tso_bd_num buffer data to be larger
1800  * than MSS, we simplify it by ensuring skb_headlen + the first continuous
1801  * max_non_tso_bd_num - 1 frags to be larger than gso header len + mss,
1802  * and the remaining continuous max_non_tso_bd_num - 1 frags to be larger
1803  * than MSS except the last max_non_tso_bd_num - 1 frags.
1804  */
1805 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size,
1806                                      unsigned int bd_num, u8 max_non_tso_bd_num)
1807 {
1808         unsigned int tot_len = 0;
1809         int i;
1810
1811         for (i = 0; i < max_non_tso_bd_num - 1U; i++)
1812                 tot_len += bd_size[i];
1813
1814         /* ensure the first max_non_tso_bd_num frags is greater than
1815          * mss + header
1816          */
1817         if (tot_len + bd_size[max_non_tso_bd_num - 1U] <
1818             skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb))
1819                 return true;
1820
1821         /* ensure every continuous max_non_tso_bd_num - 1 buffer is greater
1822          * than mss except the last one.
1823          */
1824         for (i = 0; i < bd_num - max_non_tso_bd_num; i++) {
1825                 tot_len -= bd_size[i];
1826                 tot_len += bd_size[i + max_non_tso_bd_num - 1U];
1827
1828                 if (tot_len < skb_shinfo(skb)->gso_size)
1829                         return true;
1830         }
1831
1832         return false;
1833 }
1834
1835 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size)
1836 {
1837         int i;
1838
1839         for (i = 0; i < MAX_SKB_FRAGS; i++)
1840                 size[i] = skb_frag_size(&shinfo->frags[i]);
1841 }
1842
1843 static int hns3_skb_linearize(struct hns3_enet_ring *ring,
1844                               struct sk_buff *skb,
1845                               u8 max_non_tso_bd_num,
1846                               unsigned int bd_num)
1847 {
1848         /* 'bd_num == UINT_MAX' means the skb' fraglist has a
1849          * recursion level of over HNS3_MAX_RECURSION_LEVEL.
1850          */
1851         if (bd_num == UINT_MAX) {
1852                 u64_stats_update_begin(&ring->syncp);
1853                 ring->stats.over_max_recursion++;
1854                 u64_stats_update_end(&ring->syncp);
1855                 return -ENOMEM;
1856         }
1857
1858         /* The skb->len has exceeded the hw limitation, linearization
1859          * will not help.
1860          */
1861         if (skb->len > HNS3_MAX_TSO_SIZE ||
1862             (!skb_is_gso(skb) && skb->len >
1863              HNS3_MAX_NON_TSO_SIZE(max_non_tso_bd_num))) {
1864                 u64_stats_update_begin(&ring->syncp);
1865                 ring->stats.hw_limitation++;
1866                 u64_stats_update_end(&ring->syncp);
1867                 return -ENOMEM;
1868         }
1869
1870         if (__skb_linearize(skb)) {
1871                 u64_stats_update_begin(&ring->syncp);
1872                 ring->stats.sw_err_cnt++;
1873                 u64_stats_update_end(&ring->syncp);
1874                 return -ENOMEM;
1875         }
1876
1877         return 0;
1878 }
1879
1880 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring,
1881                                   struct net_device *netdev,
1882                                   struct sk_buff *skb)
1883 {
1884         struct hns3_nic_priv *priv = netdev_priv(netdev);
1885         u8 max_non_tso_bd_num = priv->max_non_tso_bd_num;
1886         unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U];
1887         unsigned int bd_num;
1888
1889         bd_num = hns3_tx_bd_num(skb, bd_size, max_non_tso_bd_num, 0, 0);
1890         if (unlikely(bd_num > max_non_tso_bd_num)) {
1891                 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) &&
1892                     !hns3_skb_need_linearized(skb, bd_size, bd_num,
1893                                               max_non_tso_bd_num)) {
1894                         trace_hns3_over_max_bd(skb);
1895                         goto out;
1896                 }
1897
1898                 if (hns3_skb_linearize(ring, skb, max_non_tso_bd_num,
1899                                        bd_num))
1900                         return -ENOMEM;
1901
1902                 bd_num = hns3_tx_bd_count(skb->len);
1903
1904                 u64_stats_update_begin(&ring->syncp);
1905                 ring->stats.tx_copy++;
1906                 u64_stats_update_end(&ring->syncp);
1907         }
1908
1909 out:
1910         if (likely(ring_space(ring) >= bd_num))
1911                 return bd_num;
1912
1913         netif_stop_subqueue(netdev, ring->queue_index);
1914         smp_mb(); /* Memory barrier before checking ring_space */
1915
1916         /* Start queue in case hns3_clean_tx_ring has just made room
1917          * available and has not seen the queue stopped state performed
1918          * by netif_stop_subqueue above.
1919          */
1920         if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) &&
1921             !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
1922                 netif_start_subqueue(netdev, ring->queue_index);
1923                 return bd_num;
1924         }
1925
1926         u64_stats_update_begin(&ring->syncp);
1927         ring->stats.tx_busy++;
1928         u64_stats_update_end(&ring->syncp);
1929
1930         return -EBUSY;
1931 }
1932
1933 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
1934 {
1935         struct device *dev = ring_to_dev(ring);
1936         unsigned int i;
1937
1938         for (i = 0; i < ring->desc_num; i++) {
1939                 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1940                 struct hns3_desc_cb *desc_cb;
1941
1942                 memset(desc, 0, sizeof(*desc));
1943
1944                 /* check if this is where we started */
1945                 if (ring->next_to_use == next_to_use_orig)
1946                         break;
1947
1948                 /* rollback one */
1949                 ring_ptr_move_bw(ring, next_to_use);
1950
1951                 desc_cb = &ring->desc_cb[ring->next_to_use];
1952
1953                 if (!desc_cb->dma)
1954                         continue;
1955
1956                 /* unmap the descriptor dma address */
1957                 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
1958                         dma_unmap_single(dev, desc_cb->dma, desc_cb->length,
1959                                          DMA_TO_DEVICE);
1960                 else if (desc_cb->type &
1961                          (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL))
1962                         hns3_tx_spare_rollback(ring, desc_cb->length);
1963                 else if (desc_cb->length)
1964                         dma_unmap_page(dev, desc_cb->dma, desc_cb->length,
1965                                        DMA_TO_DEVICE);
1966
1967                 desc_cb->length = 0;
1968                 desc_cb->dma = 0;
1969                 desc_cb->type = DESC_TYPE_UNKNOWN;
1970         }
1971 }
1972
1973 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring,
1974                                  struct sk_buff *skb, unsigned int type)
1975 {
1976         struct sk_buff *frag_skb;
1977         int i, ret, bd_num = 0;
1978
1979         ret = hns3_map_and_fill_desc(ring, skb, type);
1980         if (unlikely(ret < 0))
1981                 return ret;
1982
1983         bd_num += ret;
1984
1985         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1986                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1987
1988                 ret = hns3_map_and_fill_desc(ring, frag, DESC_TYPE_PAGE);
1989                 if (unlikely(ret < 0))
1990                         return ret;
1991
1992                 bd_num += ret;
1993         }
1994
1995         skb_walk_frags(skb, frag_skb) {
1996                 ret = hns3_fill_skb_to_desc(ring, frag_skb,
1997                                             DESC_TYPE_FRAGLIST_SKB);
1998                 if (unlikely(ret < 0))
1999                         return ret;
2000
2001                 bd_num += ret;
2002         }
2003
2004         return bd_num;
2005 }
2006
2007 static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num,
2008                              bool doorbell)
2009 {
2010         ring->pending_buf += num;
2011
2012         if (!doorbell) {
2013                 u64_stats_update_begin(&ring->syncp);
2014                 ring->stats.tx_more++;
2015                 u64_stats_update_end(&ring->syncp);
2016                 return;
2017         }
2018
2019         if (!ring->pending_buf)
2020                 return;
2021
2022         writel(ring->pending_buf,
2023                ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG);
2024         ring->pending_buf = 0;
2025         WRITE_ONCE(ring->last_to_use, ring->next_to_use);
2026 }
2027
2028 static void hns3_tsyn(struct net_device *netdev, struct sk_buff *skb,
2029                       struct hns3_desc *desc)
2030 {
2031         struct hnae3_handle *h = hns3_get_handle(netdev);
2032
2033         if (!(h->ae_algo->ops->set_tx_hwts_info &&
2034               h->ae_algo->ops->set_tx_hwts_info(h, skb)))
2035                 return;
2036
2037         desc->tx.bdtp_fe_sc_vld_ra_ri |= cpu_to_le16(BIT(HNS3_TXD_TSYN_B));
2038 }
2039
2040 static int hns3_handle_tx_bounce(struct hns3_enet_ring *ring,
2041                                  struct sk_buff *skb)
2042 {
2043         struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2044         unsigned int type = DESC_TYPE_BOUNCE_HEAD;
2045         unsigned int size = skb_headlen(skb);
2046         dma_addr_t dma;
2047         int bd_num = 0;
2048         u32 cb_len;
2049         void *buf;
2050         int ret;
2051
2052         if (skb->len <= ring->tx_copybreak) {
2053                 size = skb->len;
2054                 type = DESC_TYPE_BOUNCE_ALL;
2055         }
2056
2057         /* hns3_can_use_tx_bounce() is called to ensure the below
2058          * function can always return the tx buffer.
2059          */
2060         buf = hns3_tx_spare_alloc(ring, size, &dma, &cb_len);
2061
2062         ret = skb_copy_bits(skb, 0, buf, size);
2063         if (unlikely(ret < 0)) {
2064                 hns3_tx_spare_rollback(ring, cb_len);
2065                 u64_stats_update_begin(&ring->syncp);
2066                 ring->stats.copy_bits_err++;
2067                 u64_stats_update_end(&ring->syncp);
2068                 return ret;
2069         }
2070
2071         desc_cb->priv = skb;
2072         desc_cb->length = cb_len;
2073         desc_cb->dma = dma;
2074         desc_cb->type = type;
2075
2076         bd_num += hns3_fill_desc(ring, dma, size);
2077
2078         if (type == DESC_TYPE_BOUNCE_HEAD) {
2079                 ret = hns3_fill_skb_to_desc(ring, skb,
2080                                             DESC_TYPE_BOUNCE_HEAD);
2081                 if (unlikely(ret < 0))
2082                         return ret;
2083
2084                 bd_num += ret;
2085         }
2086
2087         dma_sync_single_for_device(ring_to_dev(ring), dma, size,
2088                                    DMA_TO_DEVICE);
2089
2090         u64_stats_update_begin(&ring->syncp);
2091         ring->stats.tx_bounce++;
2092         u64_stats_update_end(&ring->syncp);
2093         return bd_num;
2094 }
2095
2096 static int hns3_handle_tx_sgl(struct hns3_enet_ring *ring,
2097                               struct sk_buff *skb)
2098 {
2099         struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2100         u32 nfrag = skb_shinfo(skb)->nr_frags + 1;
2101         struct sg_table *sgt;
2102         int i, bd_num = 0;
2103         dma_addr_t dma;
2104         u32 cb_len;
2105         int nents;
2106
2107         if (skb_has_frag_list(skb))
2108                 nfrag = HNS3_MAX_TSO_BD_NUM;
2109
2110         /* hns3_can_use_tx_sgl() is called to ensure the below
2111          * function can always return the tx buffer.
2112          */
2113         sgt = hns3_tx_spare_alloc(ring, HNS3_SGL_SIZE(nfrag),
2114                                   &dma, &cb_len);
2115
2116         /* scatterlist follows by the sg table */
2117         sgt->sgl = (struct scatterlist *)(sgt + 1);
2118         sg_init_table(sgt->sgl, nfrag);
2119         nents = skb_to_sgvec(skb, sgt->sgl, 0, skb->len);
2120         if (unlikely(nents < 0)) {
2121                 hns3_tx_spare_rollback(ring, cb_len);
2122                 u64_stats_update_begin(&ring->syncp);
2123                 ring->stats.skb2sgl_err++;
2124                 u64_stats_update_end(&ring->syncp);
2125                 return -ENOMEM;
2126         }
2127
2128         sgt->orig_nents = nents;
2129         sgt->nents = dma_map_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
2130                                 DMA_TO_DEVICE);
2131         if (unlikely(!sgt->nents)) {
2132                 hns3_tx_spare_rollback(ring, cb_len);
2133                 u64_stats_update_begin(&ring->syncp);
2134                 ring->stats.map_sg_err++;
2135                 u64_stats_update_end(&ring->syncp);
2136                 return -ENOMEM;
2137         }
2138
2139         desc_cb->priv = skb;
2140         desc_cb->length = cb_len;
2141         desc_cb->dma = dma;
2142         desc_cb->type = DESC_TYPE_SGL_SKB;
2143
2144         for (i = 0; i < sgt->nents; i++)
2145                 bd_num += hns3_fill_desc(ring, sg_dma_address(sgt->sgl + i),
2146                                          sg_dma_len(sgt->sgl + i));
2147
2148         u64_stats_update_begin(&ring->syncp);
2149         ring->stats.tx_sgl++;
2150         u64_stats_update_end(&ring->syncp);
2151
2152         return bd_num;
2153 }
2154
2155 static int hns3_handle_desc_filling(struct hns3_enet_ring *ring,
2156                                     struct sk_buff *skb)
2157 {
2158         u32 space;
2159
2160         if (!ring->tx_spare)
2161                 goto out;
2162
2163         space = hns3_tx_spare_space(ring);
2164
2165         if (hns3_can_use_tx_sgl(ring, skb, space))
2166                 return hns3_handle_tx_sgl(ring, skb);
2167
2168         if (hns3_can_use_tx_bounce(ring, skb, space))
2169                 return hns3_handle_tx_bounce(ring, skb);
2170
2171 out:
2172         return hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB);
2173 }
2174
2175 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
2176 {
2177         struct hns3_nic_priv *priv = netdev_priv(netdev);
2178         struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping];
2179         struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2180         struct netdev_queue *dev_queue;
2181         int pre_ntu, next_to_use_head;
2182         bool doorbell;
2183         int ret;
2184
2185         /* Hardware can only handle short frames above 32 bytes */
2186         if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) {
2187                 hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
2188
2189                 u64_stats_update_begin(&ring->syncp);
2190                 ring->stats.sw_err_cnt++;
2191                 u64_stats_update_end(&ring->syncp);
2192
2193                 return NETDEV_TX_OK;
2194         }
2195
2196         /* Prefetch the data used later */
2197         prefetch(skb->data);
2198
2199         ret = hns3_nic_maybe_stop_tx(ring, netdev, skb);
2200         if (unlikely(ret <= 0)) {
2201                 if (ret == -EBUSY) {
2202                         hns3_tx_doorbell(ring, 0, true);
2203                         return NETDEV_TX_BUSY;
2204                 }
2205
2206                 hns3_rl_err(netdev, "xmit error: %d!\n", ret);
2207                 goto out_err_tx_ok;
2208         }
2209
2210         next_to_use_head = ring->next_to_use;
2211
2212         ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use],
2213                                  desc_cb);
2214         if (unlikely(ret < 0))
2215                 goto fill_err;
2216
2217         /* 'ret < 0' means filling error, 'ret == 0' means skb->len is
2218          * zero, which is unlikely, and 'ret > 0' means how many tx desc
2219          * need to be notified to the hw.
2220          */
2221         ret = hns3_handle_desc_filling(ring, skb);
2222         if (unlikely(ret <= 0))
2223                 goto fill_err;
2224
2225         pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) :
2226                                         (ring->desc_num - 1);
2227
2228         if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
2229                 hns3_tsyn(netdev, skb, &ring->desc[pre_ntu]);
2230
2231         ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |=
2232                                 cpu_to_le16(BIT(HNS3_TXD_FE_B));
2233         trace_hns3_tx_desc(ring, pre_ntu);
2234
2235         skb_tx_timestamp(skb);
2236
2237         /* Complete translate all packets */
2238         dev_queue = netdev_get_tx_queue(netdev, ring->queue_index);
2239         doorbell = __netdev_tx_sent_queue(dev_queue, desc_cb->send_bytes,
2240                                           netdev_xmit_more());
2241         hns3_tx_doorbell(ring, ret, doorbell);
2242
2243         return NETDEV_TX_OK;
2244
2245 fill_err:
2246         hns3_clear_desc(ring, next_to_use_head);
2247
2248 out_err_tx_ok:
2249         dev_kfree_skb_any(skb);
2250         hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
2251         return NETDEV_TX_OK;
2252 }
2253
2254 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
2255 {
2256         struct hnae3_handle *h = hns3_get_handle(netdev);
2257         struct sockaddr *mac_addr = p;
2258         int ret;
2259
2260         if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
2261                 return -EADDRNOTAVAIL;
2262
2263         if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
2264                 netdev_info(netdev, "already using mac address %pM\n",
2265                             mac_addr->sa_data);
2266                 return 0;
2267         }
2268
2269         /* For VF device, if there is a perm_addr, then the user will not
2270          * be allowed to change the address.
2271          */
2272         if (!hns3_is_phys_func(h->pdev) &&
2273             !is_zero_ether_addr(netdev->perm_addr)) {
2274                 netdev_err(netdev, "has permanent MAC %pM, user MAC %pM not allow\n",
2275                            netdev->perm_addr, mac_addr->sa_data);
2276                 return -EPERM;
2277         }
2278
2279         ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
2280         if (ret) {
2281                 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
2282                 return ret;
2283         }
2284
2285         ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
2286
2287         return 0;
2288 }
2289
2290 static int hns3_nic_do_ioctl(struct net_device *netdev,
2291                              struct ifreq *ifr, int cmd)
2292 {
2293         struct hnae3_handle *h = hns3_get_handle(netdev);
2294
2295         if (!netif_running(netdev))
2296                 return -EINVAL;
2297
2298         if (!h->ae_algo->ops->do_ioctl)
2299                 return -EOPNOTSUPP;
2300
2301         return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
2302 }
2303
2304 static int hns3_nic_set_features(struct net_device *netdev,
2305                                  netdev_features_t features)
2306 {
2307         netdev_features_t changed = netdev->features ^ features;
2308         struct hns3_nic_priv *priv = netdev_priv(netdev);
2309         struct hnae3_handle *h = priv->ae_handle;
2310         bool enable;
2311         int ret;
2312
2313         if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
2314                 enable = !!(features & NETIF_F_GRO_HW);
2315                 ret = h->ae_algo->ops->set_gro_en(h, enable);
2316                 if (ret)
2317                         return ret;
2318         }
2319
2320         if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
2321             h->ae_algo->ops->enable_hw_strip_rxvtag) {
2322                 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
2323                 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
2324                 if (ret)
2325                         return ret;
2326         }
2327
2328         if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
2329                 enable = !!(features & NETIF_F_NTUPLE);
2330                 h->ae_algo->ops->enable_fd(h, enable);
2331         }
2332
2333         if ((netdev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) &&
2334             h->ae_algo->ops->cls_flower_active(h)) {
2335                 netdev_err(netdev,
2336                            "there are offloaded TC filters active, cannot disable HW TC offload");
2337                 return -EINVAL;
2338         }
2339
2340         if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
2341             h->ae_algo->ops->enable_vlan_filter) {
2342                 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER);
2343                 ret = h->ae_algo->ops->enable_vlan_filter(h, enable);
2344                 if (ret)
2345                         return ret;
2346         }
2347
2348         netdev->features = features;
2349         return 0;
2350 }
2351
2352 static netdev_features_t hns3_features_check(struct sk_buff *skb,
2353                                              struct net_device *dev,
2354                                              netdev_features_t features)
2355 {
2356 #define HNS3_MAX_HDR_LEN        480U
2357 #define HNS3_MAX_L4_HDR_LEN     60U
2358
2359         size_t len;
2360
2361         if (skb->ip_summed != CHECKSUM_PARTIAL)
2362                 return features;
2363
2364         if (skb->encapsulation)
2365                 len = skb_inner_transport_header(skb) - skb->data;
2366         else
2367                 len = skb_transport_header(skb) - skb->data;
2368
2369         /* Assume L4 is 60 byte as TCP is the only protocol with a
2370          * a flexible value, and it's max len is 60 bytes.
2371          */
2372         len += HNS3_MAX_L4_HDR_LEN;
2373
2374         /* Hardware only supports checksum on the skb with a max header
2375          * len of 480 bytes.
2376          */
2377         if (len > HNS3_MAX_HDR_LEN)
2378                 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2379
2380         return features;
2381 }
2382
2383 static void hns3_nic_get_stats64(struct net_device *netdev,
2384                                  struct rtnl_link_stats64 *stats)
2385 {
2386         struct hns3_nic_priv *priv = netdev_priv(netdev);
2387         int queue_num = priv->ae_handle->kinfo.num_tqps;
2388         struct hnae3_handle *handle = priv->ae_handle;
2389         struct hns3_enet_ring *ring;
2390         u64 rx_length_errors = 0;
2391         u64 rx_crc_errors = 0;
2392         u64 rx_multicast = 0;
2393         unsigned int start;
2394         u64 tx_errors = 0;
2395         u64 rx_errors = 0;
2396         unsigned int idx;
2397         u64 tx_bytes = 0;
2398         u64 rx_bytes = 0;
2399         u64 tx_pkts = 0;
2400         u64 rx_pkts = 0;
2401         u64 tx_drop = 0;
2402         u64 rx_drop = 0;
2403
2404         if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
2405                 return;
2406
2407         handle->ae_algo->ops->update_stats(handle, &netdev->stats);
2408
2409         for (idx = 0; idx < queue_num; idx++) {
2410                 /* fetch the tx stats */
2411                 ring = &priv->ring[idx];
2412                 do {
2413                         start = u64_stats_fetch_begin_irq(&ring->syncp);
2414                         tx_bytes += ring->stats.tx_bytes;
2415                         tx_pkts += ring->stats.tx_pkts;
2416                         tx_drop += ring->stats.sw_err_cnt;
2417                         tx_drop += ring->stats.tx_vlan_err;
2418                         tx_drop += ring->stats.tx_l4_proto_err;
2419                         tx_drop += ring->stats.tx_l2l3l4_err;
2420                         tx_drop += ring->stats.tx_tso_err;
2421                         tx_drop += ring->stats.over_max_recursion;
2422                         tx_drop += ring->stats.hw_limitation;
2423                         tx_drop += ring->stats.copy_bits_err;
2424                         tx_drop += ring->stats.skb2sgl_err;
2425                         tx_drop += ring->stats.map_sg_err;
2426                         tx_errors += ring->stats.sw_err_cnt;
2427                         tx_errors += ring->stats.tx_vlan_err;
2428                         tx_errors += ring->stats.tx_l4_proto_err;
2429                         tx_errors += ring->stats.tx_l2l3l4_err;
2430                         tx_errors += ring->stats.tx_tso_err;
2431                         tx_errors += ring->stats.over_max_recursion;
2432                         tx_errors += ring->stats.hw_limitation;
2433                         tx_errors += ring->stats.copy_bits_err;
2434                         tx_errors += ring->stats.skb2sgl_err;
2435                         tx_errors += ring->stats.map_sg_err;
2436                 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
2437
2438                 /* fetch the rx stats */
2439                 ring = &priv->ring[idx + queue_num];
2440                 do {
2441                         start = u64_stats_fetch_begin_irq(&ring->syncp);
2442                         rx_bytes += ring->stats.rx_bytes;
2443                         rx_pkts += ring->stats.rx_pkts;
2444                         rx_drop += ring->stats.l2_err;
2445                         rx_errors += ring->stats.l2_err;
2446                         rx_errors += ring->stats.l3l4_csum_err;
2447                         rx_crc_errors += ring->stats.l2_err;
2448                         rx_multicast += ring->stats.rx_multicast;
2449                         rx_length_errors += ring->stats.err_pkt_len;
2450                 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
2451         }
2452
2453         stats->tx_bytes = tx_bytes;
2454         stats->tx_packets = tx_pkts;
2455         stats->rx_bytes = rx_bytes;
2456         stats->rx_packets = rx_pkts;
2457
2458         stats->rx_errors = rx_errors;
2459         stats->multicast = rx_multicast;
2460         stats->rx_length_errors = rx_length_errors;
2461         stats->rx_crc_errors = rx_crc_errors;
2462         stats->rx_missed_errors = netdev->stats.rx_missed_errors;
2463
2464         stats->tx_errors = tx_errors;
2465         stats->rx_dropped = rx_drop;
2466         stats->tx_dropped = tx_drop;
2467         stats->collisions = netdev->stats.collisions;
2468         stats->rx_over_errors = netdev->stats.rx_over_errors;
2469         stats->rx_frame_errors = netdev->stats.rx_frame_errors;
2470         stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
2471         stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
2472         stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
2473         stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
2474         stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
2475         stats->tx_window_errors = netdev->stats.tx_window_errors;
2476         stats->rx_compressed = netdev->stats.rx_compressed;
2477         stats->tx_compressed = netdev->stats.tx_compressed;
2478 }
2479
2480 static int hns3_setup_tc(struct net_device *netdev, void *type_data)
2481 {
2482         struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
2483         struct hnae3_knic_private_info *kinfo;
2484         u8 tc = mqprio_qopt->qopt.num_tc;
2485         u16 mode = mqprio_qopt->mode;
2486         u8 hw = mqprio_qopt->qopt.hw;
2487         struct hnae3_handle *h;
2488
2489         if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
2490                mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
2491                 return -EOPNOTSUPP;
2492
2493         if (tc > HNAE3_MAX_TC)
2494                 return -EINVAL;
2495
2496         if (!netdev)
2497                 return -EINVAL;
2498
2499         h = hns3_get_handle(netdev);
2500         kinfo = &h->kinfo;
2501
2502         netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc);
2503
2504         return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
2505                 kinfo->dcb_ops->setup_tc(h, mqprio_qopt) : -EOPNOTSUPP;
2506 }
2507
2508 static int hns3_setup_tc_cls_flower(struct hns3_nic_priv *priv,
2509                                     struct flow_cls_offload *flow)
2510 {
2511         int tc = tc_classid_to_hwtc(priv->netdev, flow->classid);
2512         struct hnae3_handle *h = hns3_get_handle(priv->netdev);
2513
2514         switch (flow->command) {
2515         case FLOW_CLS_REPLACE:
2516                 if (h->ae_algo->ops->add_cls_flower)
2517                         return h->ae_algo->ops->add_cls_flower(h, flow, tc);
2518                 break;
2519         case FLOW_CLS_DESTROY:
2520                 if (h->ae_algo->ops->del_cls_flower)
2521                         return h->ae_algo->ops->del_cls_flower(h, flow);
2522                 break;
2523         default:
2524                 break;
2525         }
2526
2527         return -EOPNOTSUPP;
2528 }
2529
2530 static int hns3_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2531                                   void *cb_priv)
2532 {
2533         struct hns3_nic_priv *priv = cb_priv;
2534
2535         if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
2536                 return -EOPNOTSUPP;
2537
2538         switch (type) {
2539         case TC_SETUP_CLSFLOWER:
2540                 return hns3_setup_tc_cls_flower(priv, type_data);
2541         default:
2542                 return -EOPNOTSUPP;
2543         }
2544 }
2545
2546 static LIST_HEAD(hns3_block_cb_list);
2547
2548 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
2549                              void *type_data)
2550 {
2551         struct hns3_nic_priv *priv = netdev_priv(dev);
2552         int ret;
2553
2554         switch (type) {
2555         case TC_SETUP_QDISC_MQPRIO:
2556                 ret = hns3_setup_tc(dev, type_data);
2557                 break;
2558         case TC_SETUP_BLOCK:
2559                 ret = flow_block_cb_setup_simple(type_data,
2560                                                  &hns3_block_cb_list,
2561                                                  hns3_setup_tc_block_cb,
2562                                                  priv, priv, true);
2563                 break;
2564         default:
2565                 return -EOPNOTSUPP;
2566         }
2567
2568         return ret;
2569 }
2570
2571 static int hns3_vlan_rx_add_vid(struct net_device *netdev,
2572                                 __be16 proto, u16 vid)
2573 {
2574         struct hnae3_handle *h = hns3_get_handle(netdev);
2575         int ret = -EIO;
2576
2577         if (h->ae_algo->ops->set_vlan_filter)
2578                 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
2579
2580         return ret;
2581 }
2582
2583 static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
2584                                  __be16 proto, u16 vid)
2585 {
2586         struct hnae3_handle *h = hns3_get_handle(netdev);
2587         int ret = -EIO;
2588
2589         if (h->ae_algo->ops->set_vlan_filter)
2590                 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
2591
2592         return ret;
2593 }
2594
2595 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
2596                                 u8 qos, __be16 vlan_proto)
2597 {
2598         struct hnae3_handle *h = hns3_get_handle(netdev);
2599         int ret = -EIO;
2600
2601         netif_dbg(h, drv, netdev,
2602                   "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n",
2603                   vf, vlan, qos, ntohs(vlan_proto));
2604
2605         if (h->ae_algo->ops->set_vf_vlan_filter)
2606                 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
2607                                                           qos, vlan_proto);
2608
2609         return ret;
2610 }
2611
2612 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable)
2613 {
2614         struct hnae3_handle *handle = hns3_get_handle(netdev);
2615
2616         if (hns3_nic_resetting(netdev))
2617                 return -EBUSY;
2618
2619         if (!handle->ae_algo->ops->set_vf_spoofchk)
2620                 return -EOPNOTSUPP;
2621
2622         return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable);
2623 }
2624
2625 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable)
2626 {
2627         struct hnae3_handle *handle = hns3_get_handle(netdev);
2628
2629         if (!handle->ae_algo->ops->set_vf_trust)
2630                 return -EOPNOTSUPP;
2631
2632         return handle->ae_algo->ops->set_vf_trust(handle, vf, enable);
2633 }
2634
2635 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
2636 {
2637         struct hnae3_handle *h = hns3_get_handle(netdev);
2638         int ret;
2639
2640         if (hns3_nic_resetting(netdev))
2641                 return -EBUSY;
2642
2643         if (!h->ae_algo->ops->set_mtu)
2644                 return -EOPNOTSUPP;
2645
2646         netif_dbg(h, drv, netdev,
2647                   "change mtu from %u to %d\n", netdev->mtu, new_mtu);
2648
2649         ret = h->ae_algo->ops->set_mtu(h, new_mtu);
2650         if (ret)
2651                 netdev_err(netdev, "failed to change MTU in hardware %d\n",
2652                            ret);
2653         else
2654                 netdev->mtu = new_mtu;
2655
2656         return ret;
2657 }
2658
2659 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
2660 {
2661         struct hns3_nic_priv *priv = netdev_priv(ndev);
2662         struct hnae3_handle *h = hns3_get_handle(ndev);
2663         struct hns3_enet_ring *tx_ring;
2664         struct napi_struct *napi;
2665         int timeout_queue = 0;
2666         int hw_head, hw_tail;
2667         int fbd_num, fbd_oft;
2668         int ebd_num, ebd_oft;
2669         int bd_num, bd_err;
2670         int ring_en, tc;
2671         int i;
2672
2673         /* Find the stopped queue the same way the stack does */
2674         for (i = 0; i < ndev->num_tx_queues; i++) {
2675                 struct netdev_queue *q;
2676                 unsigned long trans_start;
2677
2678                 q = netdev_get_tx_queue(ndev, i);
2679                 trans_start = q->trans_start;
2680                 if (netif_xmit_stopped(q) &&
2681                     time_after(jiffies,
2682                                (trans_start + ndev->watchdog_timeo))) {
2683                         timeout_queue = i;
2684                         netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",
2685                                     q->state,
2686                                     jiffies_to_msecs(jiffies - trans_start));
2687                         break;
2688                 }
2689         }
2690
2691         if (i == ndev->num_tx_queues) {
2692                 netdev_info(ndev,
2693                             "no netdev TX timeout queue found, timeout count: %llu\n",
2694                             priv->tx_timeout_count);
2695                 return false;
2696         }
2697
2698         priv->tx_timeout_count++;
2699
2700         tx_ring = &priv->ring[timeout_queue];
2701         napi = &tx_ring->tqp_vector->napi;
2702
2703         netdev_info(ndev,
2704                     "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n",
2705                     priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use,
2706                     tx_ring->next_to_clean, napi->state);
2707
2708         netdev_info(ndev,
2709                     "tx_pkts: %llu, tx_bytes: %llu, sw_err_cnt: %llu, tx_pending: %d\n",
2710                     tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes,
2711                     tx_ring->stats.sw_err_cnt, tx_ring->pending_buf);
2712
2713         netdev_info(ndev,
2714                     "seg_pkt_cnt: %llu, tx_more: %llu, restart_queue: %llu, tx_busy: %llu\n",
2715                     tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_more,
2716                     tx_ring->stats.restart_queue, tx_ring->stats.tx_busy);
2717
2718         /* When mac received many pause frames continuous, it's unable to send
2719          * packets, which may cause tx timeout
2720          */
2721         if (h->ae_algo->ops->get_mac_stats) {
2722                 struct hns3_mac_stats mac_stats;
2723
2724                 h->ae_algo->ops->get_mac_stats(h, &mac_stats);
2725                 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
2726                             mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt);
2727         }
2728
2729         hw_head = readl_relaxed(tx_ring->tqp->io_base +
2730                                 HNS3_RING_TX_RING_HEAD_REG);
2731         hw_tail = readl_relaxed(tx_ring->tqp->io_base +
2732                                 HNS3_RING_TX_RING_TAIL_REG);
2733         fbd_num = readl_relaxed(tx_ring->tqp->io_base +
2734                                 HNS3_RING_TX_RING_FBDNUM_REG);
2735         fbd_oft = readl_relaxed(tx_ring->tqp->io_base +
2736                                 HNS3_RING_TX_RING_OFFSET_REG);
2737         ebd_num = readl_relaxed(tx_ring->tqp->io_base +
2738                                 HNS3_RING_TX_RING_EBDNUM_REG);
2739         ebd_oft = readl_relaxed(tx_ring->tqp->io_base +
2740                                 HNS3_RING_TX_RING_EBD_OFFSET_REG);
2741         bd_num = readl_relaxed(tx_ring->tqp->io_base +
2742                                HNS3_RING_TX_RING_BD_NUM_REG);
2743         bd_err = readl_relaxed(tx_ring->tqp->io_base +
2744                                HNS3_RING_TX_RING_BD_ERR_REG);
2745         ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG);
2746         tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG);
2747
2748         netdev_info(ndev,
2749                     "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n",
2750                     bd_num, hw_head, hw_tail, bd_err,
2751                     readl(tx_ring->tqp_vector->mask_addr));
2752         netdev_info(ndev,
2753                     "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n",
2754                     ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft);
2755
2756         return true;
2757 }
2758
2759 static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue)
2760 {
2761         struct hns3_nic_priv *priv = netdev_priv(ndev);
2762         struct hnae3_handle *h = priv->ae_handle;
2763
2764         if (!hns3_get_tx_timeo_queue_info(ndev))
2765                 return;
2766
2767         /* request the reset, and let the hclge to determine
2768          * which reset level should be done
2769          */
2770         if (h->ae_algo->ops->reset_event)
2771                 h->ae_algo->ops->reset_event(h->pdev, h);
2772 }
2773
2774 #ifdef CONFIG_RFS_ACCEL
2775 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
2776                               u16 rxq_index, u32 flow_id)
2777 {
2778         struct hnae3_handle *h = hns3_get_handle(dev);
2779         struct flow_keys fkeys;
2780
2781         if (!h->ae_algo->ops->add_arfs_entry)
2782                 return -EOPNOTSUPP;
2783
2784         if (skb->encapsulation)
2785                 return -EPROTONOSUPPORT;
2786
2787         if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0))
2788                 return -EPROTONOSUPPORT;
2789
2790         if ((fkeys.basic.n_proto != htons(ETH_P_IP) &&
2791              fkeys.basic.n_proto != htons(ETH_P_IPV6)) ||
2792             (fkeys.basic.ip_proto != IPPROTO_TCP &&
2793              fkeys.basic.ip_proto != IPPROTO_UDP))
2794                 return -EPROTONOSUPPORT;
2795
2796         return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys);
2797 }
2798 #endif
2799
2800 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf,
2801                                   struct ifla_vf_info *ivf)
2802 {
2803         struct hnae3_handle *h = hns3_get_handle(ndev);
2804
2805         if (!h->ae_algo->ops->get_vf_config)
2806                 return -EOPNOTSUPP;
2807
2808         return h->ae_algo->ops->get_vf_config(h, vf, ivf);
2809 }
2810
2811 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf,
2812                                       int link_state)
2813 {
2814         struct hnae3_handle *h = hns3_get_handle(ndev);
2815
2816         if (!h->ae_algo->ops->set_vf_link_state)
2817                 return -EOPNOTSUPP;
2818
2819         return h->ae_algo->ops->set_vf_link_state(h, vf, link_state);
2820 }
2821
2822 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf,
2823                                 int min_tx_rate, int max_tx_rate)
2824 {
2825         struct hnae3_handle *h = hns3_get_handle(ndev);
2826
2827         if (!h->ae_algo->ops->set_vf_rate)
2828                 return -EOPNOTSUPP;
2829
2830         return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate,
2831                                             false);
2832 }
2833
2834 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
2835 {
2836         struct hnae3_handle *h = hns3_get_handle(netdev);
2837
2838         if (!h->ae_algo->ops->set_vf_mac)
2839                 return -EOPNOTSUPP;
2840
2841         if (is_multicast_ether_addr(mac)) {
2842                 netdev_err(netdev,
2843                            "Invalid MAC:%pM specified. Could not set MAC\n",
2844                            mac);
2845                 return -EINVAL;
2846         }
2847
2848         return h->ae_algo->ops->set_vf_mac(h, vf_id, mac);
2849 }
2850
2851 static const struct net_device_ops hns3_nic_netdev_ops = {
2852         .ndo_open               = hns3_nic_net_open,
2853         .ndo_stop               = hns3_nic_net_stop,
2854         .ndo_start_xmit         = hns3_nic_net_xmit,
2855         .ndo_tx_timeout         = hns3_nic_net_timeout,
2856         .ndo_set_mac_address    = hns3_nic_net_set_mac_address,
2857         .ndo_eth_ioctl          = hns3_nic_do_ioctl,
2858         .ndo_change_mtu         = hns3_nic_change_mtu,
2859         .ndo_set_features       = hns3_nic_set_features,
2860         .ndo_features_check     = hns3_features_check,
2861         .ndo_get_stats64        = hns3_nic_get_stats64,
2862         .ndo_setup_tc           = hns3_nic_setup_tc,
2863         .ndo_set_rx_mode        = hns3_nic_set_rx_mode,
2864         .ndo_vlan_rx_add_vid    = hns3_vlan_rx_add_vid,
2865         .ndo_vlan_rx_kill_vid   = hns3_vlan_rx_kill_vid,
2866         .ndo_set_vf_vlan        = hns3_ndo_set_vf_vlan,
2867         .ndo_set_vf_spoofchk    = hns3_set_vf_spoofchk,
2868         .ndo_set_vf_trust       = hns3_set_vf_trust,
2869 #ifdef CONFIG_RFS_ACCEL
2870         .ndo_rx_flow_steer      = hns3_rx_flow_steer,
2871 #endif
2872         .ndo_get_vf_config      = hns3_nic_get_vf_config,
2873         .ndo_set_vf_link_state  = hns3_nic_set_vf_link_state,
2874         .ndo_set_vf_rate        = hns3_nic_set_vf_rate,
2875         .ndo_set_vf_mac         = hns3_nic_set_vf_mac,
2876 };
2877
2878 bool hns3_is_phys_func(struct pci_dev *pdev)
2879 {
2880         u32 dev_id = pdev->device;
2881
2882         switch (dev_id) {
2883         case HNAE3_DEV_ID_GE:
2884         case HNAE3_DEV_ID_25GE:
2885         case HNAE3_DEV_ID_25GE_RDMA:
2886         case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
2887         case HNAE3_DEV_ID_50GE_RDMA:
2888         case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
2889         case HNAE3_DEV_ID_100G_RDMA_MACSEC:
2890         case HNAE3_DEV_ID_200G_RDMA:
2891                 return true;
2892         case HNAE3_DEV_ID_VF:
2893         case HNAE3_DEV_ID_RDMA_DCB_PFC_VF:
2894                 return false;
2895         default:
2896                 dev_warn(&pdev->dev, "un-recognized pci device-id %u",
2897                          dev_id);
2898         }
2899
2900         return false;
2901 }
2902
2903 static void hns3_disable_sriov(struct pci_dev *pdev)
2904 {
2905         /* If our VFs are assigned we cannot shut down SR-IOV
2906          * without causing issues, so just leave the hardware
2907          * available but disabled
2908          */
2909         if (pci_vfs_assigned(pdev)) {
2910                 dev_warn(&pdev->dev,
2911                          "disabling driver while VFs are assigned\n");
2912                 return;
2913         }
2914
2915         pci_disable_sriov(pdev);
2916 }
2917
2918 /* hns3_probe - Device initialization routine
2919  * @pdev: PCI device information struct
2920  * @ent: entry in hns3_pci_tbl
2921  *
2922  * hns3_probe initializes a PF identified by a pci_dev structure.
2923  * The OS initialization, configuring of the PF private structure,
2924  * and a hardware reset occur.
2925  *
2926  * Returns 0 on success, negative on failure
2927  */
2928 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2929 {
2930         struct hnae3_ae_dev *ae_dev;
2931         int ret;
2932
2933         ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL);
2934         if (!ae_dev)
2935                 return -ENOMEM;
2936
2937         ae_dev->pdev = pdev;
2938         ae_dev->flag = ent->driver_data;
2939         pci_set_drvdata(pdev, ae_dev);
2940
2941         ret = hnae3_register_ae_dev(ae_dev);
2942         if (ret)
2943                 pci_set_drvdata(pdev, NULL);
2944
2945         return ret;
2946 }
2947
2948 /* hns3_remove - Device removal routine
2949  * @pdev: PCI device information struct
2950  */
2951 static void hns3_remove(struct pci_dev *pdev)
2952 {
2953         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2954
2955         if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
2956                 hns3_disable_sriov(pdev);
2957
2958         hnae3_unregister_ae_dev(ae_dev);
2959         pci_set_drvdata(pdev, NULL);
2960 }
2961
2962 /**
2963  * hns3_pci_sriov_configure
2964  * @pdev: pointer to a pci_dev structure
2965  * @num_vfs: number of VFs to allocate
2966  *
2967  * Enable or change the number of VFs. Called when the user updates the number
2968  * of VFs in sysfs.
2969  **/
2970 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
2971 {
2972         int ret;
2973
2974         if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
2975                 dev_warn(&pdev->dev, "Can not config SRIOV\n");
2976                 return -EINVAL;
2977         }
2978
2979         if (num_vfs) {
2980                 ret = pci_enable_sriov(pdev, num_vfs);
2981                 if (ret)
2982                         dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
2983                 else
2984                         return num_vfs;
2985         } else if (!pci_vfs_assigned(pdev)) {
2986                 pci_disable_sriov(pdev);
2987         } else {
2988                 dev_warn(&pdev->dev,
2989                          "Unable to free VFs because some are assigned to VMs.\n");
2990         }
2991
2992         return 0;
2993 }
2994
2995 static void hns3_shutdown(struct pci_dev *pdev)
2996 {
2997         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2998
2999         hnae3_unregister_ae_dev(ae_dev);
3000         pci_set_drvdata(pdev, NULL);
3001
3002         if (system_state == SYSTEM_POWER_OFF)
3003                 pci_set_power_state(pdev, PCI_D3hot);
3004 }
3005
3006 static int __maybe_unused hns3_suspend(struct device *dev)
3007 {
3008         struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev);
3009
3010         if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) {
3011                 dev_info(dev, "Begin to suspend.\n");
3012                 if (ae_dev->ops && ae_dev->ops->reset_prepare)
3013                         ae_dev->ops->reset_prepare(ae_dev, HNAE3_FUNC_RESET);
3014         }
3015
3016         return 0;
3017 }
3018
3019 static int __maybe_unused hns3_resume(struct device *dev)
3020 {
3021         struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev);
3022
3023         if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) {
3024                 dev_info(dev, "Begin to resume.\n");
3025                 if (ae_dev->ops && ae_dev->ops->reset_done)
3026                         ae_dev->ops->reset_done(ae_dev);
3027         }
3028
3029         return 0;
3030 }
3031
3032 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
3033                                             pci_channel_state_t state)
3034 {
3035         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3036         pci_ers_result_t ret;
3037
3038         dev_info(&pdev->dev, "PCI error detected, state(=%u)!!\n", state);
3039
3040         if (state == pci_channel_io_perm_failure)
3041                 return PCI_ERS_RESULT_DISCONNECT;
3042
3043         if (!ae_dev || !ae_dev->ops) {
3044                 dev_err(&pdev->dev,
3045                         "Can't recover - error happened before device initialized\n");
3046                 return PCI_ERS_RESULT_NONE;
3047         }
3048
3049         if (ae_dev->ops->handle_hw_ras_error)
3050                 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
3051         else
3052                 return PCI_ERS_RESULT_NONE;
3053
3054         return ret;
3055 }
3056
3057 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
3058 {
3059         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3060         const struct hnae3_ae_ops *ops;
3061         enum hnae3_reset_type reset_type;
3062         struct device *dev = &pdev->dev;
3063
3064         if (!ae_dev || !ae_dev->ops)
3065                 return PCI_ERS_RESULT_NONE;
3066
3067         ops = ae_dev->ops;
3068         /* request the reset */
3069         if (ops->reset_event && ops->get_reset_level &&
3070             ops->set_default_reset_request) {
3071                 if (ae_dev->hw_err_reset_req) {
3072                         reset_type = ops->get_reset_level(ae_dev,
3073                                                 &ae_dev->hw_err_reset_req);
3074                         ops->set_default_reset_request(ae_dev, reset_type);
3075                         dev_info(dev, "requesting reset due to PCI error\n");
3076                         ops->reset_event(pdev, NULL);
3077                 }
3078
3079                 return PCI_ERS_RESULT_RECOVERED;
3080         }
3081
3082         return PCI_ERS_RESULT_DISCONNECT;
3083 }
3084
3085 static void hns3_reset_prepare(struct pci_dev *pdev)
3086 {
3087         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3088
3089         dev_info(&pdev->dev, "FLR prepare\n");
3090         if (ae_dev && ae_dev->ops && ae_dev->ops->reset_prepare)
3091                 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FLR_RESET);
3092 }
3093
3094 static void hns3_reset_done(struct pci_dev *pdev)
3095 {
3096         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3097
3098         dev_info(&pdev->dev, "FLR done\n");
3099         if (ae_dev && ae_dev->ops && ae_dev->ops->reset_done)
3100                 ae_dev->ops->reset_done(ae_dev);
3101 }
3102
3103 static const struct pci_error_handlers hns3_err_handler = {
3104         .error_detected = hns3_error_detected,
3105         .slot_reset     = hns3_slot_reset,
3106         .reset_prepare  = hns3_reset_prepare,
3107         .reset_done     = hns3_reset_done,
3108 };
3109
3110 static SIMPLE_DEV_PM_OPS(hns3_pm_ops, hns3_suspend, hns3_resume);
3111
3112 static struct pci_driver hns3_driver = {
3113         .name     = hns3_driver_name,
3114         .id_table = hns3_pci_tbl,
3115         .probe    = hns3_probe,
3116         .remove   = hns3_remove,
3117         .shutdown = hns3_shutdown,
3118         .driver.pm  = &hns3_pm_ops,
3119         .sriov_configure = hns3_pci_sriov_configure,
3120         .err_handler    = &hns3_err_handler,
3121 };
3122
3123 /* set default feature to hns3 */
3124 static void hns3_set_default_feature(struct net_device *netdev)
3125 {
3126         struct hnae3_handle *h = hns3_get_handle(netdev);
3127         struct pci_dev *pdev = h->pdev;
3128         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3129
3130         netdev->priv_flags |= IFF_UNICAST_FLT;
3131
3132         netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
3133
3134         netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
3135                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
3136                 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
3137                 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
3138                 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
3139                 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST;
3140
3141         if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
3142                 netdev->features |= NETIF_F_GRO_HW;
3143
3144                 if (!(h->flags & HNAE3_SUPPORT_VF))
3145                         netdev->features |= NETIF_F_NTUPLE;
3146         }
3147
3148         if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps))
3149                 netdev->features |= NETIF_F_GSO_UDP_L4;
3150
3151         if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
3152                 netdev->features |= NETIF_F_HW_CSUM;
3153         else
3154                 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
3155
3156         if (test_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, ae_dev->caps))
3157                 netdev->features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
3158
3159         if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps))
3160                 netdev->features |= NETIF_F_HW_TC;
3161
3162         netdev->hw_features |= netdev->features;
3163         if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps))
3164                 netdev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
3165
3166         netdev->vlan_features |= netdev->features &
3167                 ~(NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX |
3168                   NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_GRO_HW | NETIF_F_NTUPLE |
3169                   NETIF_F_HW_TC);
3170
3171         netdev->hw_enc_features |= netdev->vlan_features | NETIF_F_TSO_MANGLEID;
3172 }
3173
3174 static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
3175                              struct hns3_desc_cb *cb)
3176 {
3177         unsigned int order = hns3_page_order(ring);
3178         struct page *p;
3179
3180         if (ring->page_pool) {
3181                 p = page_pool_dev_alloc_frag(ring->page_pool,
3182                                              &cb->page_offset,
3183                                              hns3_buf_size(ring));
3184                 if (unlikely(!p))
3185                         return -ENOMEM;
3186
3187                 cb->priv = p;
3188                 cb->buf = page_address(p);
3189                 cb->dma = page_pool_get_dma_addr(p);
3190                 cb->type = DESC_TYPE_PP_FRAG;
3191                 cb->reuse_flag = 0;
3192                 return 0;
3193         }
3194
3195         p = dev_alloc_pages(order);
3196         if (!p)
3197                 return -ENOMEM;
3198
3199         cb->priv = p;
3200         cb->page_offset = 0;
3201         cb->reuse_flag = 0;
3202         cb->buf  = page_address(p);
3203         cb->length = hns3_page_size(ring);
3204         cb->type = DESC_TYPE_PAGE;
3205         page_ref_add(p, USHRT_MAX - 1);
3206         cb->pagecnt_bias = USHRT_MAX;
3207
3208         return 0;
3209 }
3210
3211 static void hns3_free_buffer(struct hns3_enet_ring *ring,
3212                              struct hns3_desc_cb *cb, int budget)
3213 {
3214         if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_HEAD |
3215                         DESC_TYPE_BOUNCE_ALL | DESC_TYPE_SGL_SKB))
3216                 napi_consume_skb(cb->priv, budget);
3217         else if (!HNAE3_IS_TX_RING(ring)) {
3218                 if (cb->type & DESC_TYPE_PAGE && cb->pagecnt_bias)
3219                         __page_frag_cache_drain(cb->priv, cb->pagecnt_bias);
3220                 else if (cb->type & DESC_TYPE_PP_FRAG)
3221                         page_pool_put_full_page(ring->page_pool, cb->priv,
3222                                                 false);
3223         }
3224         memset(cb, 0, sizeof(*cb));
3225 }
3226
3227 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
3228 {
3229         cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
3230                                cb->length, ring_to_dma_dir(ring));
3231
3232         if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
3233                 return -EIO;
3234
3235         return 0;
3236 }
3237
3238 static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
3239                               struct hns3_desc_cb *cb)
3240 {
3241         if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
3242                 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
3243                                  ring_to_dma_dir(ring));
3244         else if ((cb->type & DESC_TYPE_PAGE) && cb->length)
3245                 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
3246                                ring_to_dma_dir(ring));
3247         else if (cb->type & (DESC_TYPE_BOUNCE_ALL | DESC_TYPE_BOUNCE_HEAD |
3248                              DESC_TYPE_SGL_SKB))
3249                 hns3_tx_spare_reclaim_cb(ring, cb);
3250 }
3251
3252 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
3253 {
3254         hns3_unmap_buffer(ring, &ring->desc_cb[i]);
3255         ring->desc[i].addr = 0;
3256 }
3257
3258 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i,
3259                                     int budget)
3260 {
3261         struct hns3_desc_cb *cb = &ring->desc_cb[i];
3262
3263         if (!ring->desc_cb[i].dma)
3264                 return;
3265
3266         hns3_buffer_detach(ring, i);
3267         hns3_free_buffer(ring, cb, budget);
3268 }
3269
3270 static void hns3_free_buffers(struct hns3_enet_ring *ring)
3271 {
3272         int i;
3273
3274         for (i = 0; i < ring->desc_num; i++)
3275                 hns3_free_buffer_detach(ring, i, 0);
3276 }
3277
3278 /* free desc along with its attached buffer */
3279 static void hns3_free_desc(struct hns3_enet_ring *ring)
3280 {
3281         int size = ring->desc_num * sizeof(ring->desc[0]);
3282
3283         hns3_free_buffers(ring);
3284
3285         if (ring->desc) {
3286                 dma_free_coherent(ring_to_dev(ring), size,
3287                                   ring->desc, ring->desc_dma_addr);
3288                 ring->desc = NULL;
3289         }
3290 }
3291
3292 static int hns3_alloc_desc(struct hns3_enet_ring *ring)
3293 {
3294         int size = ring->desc_num * sizeof(ring->desc[0]);
3295
3296         ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
3297                                         &ring->desc_dma_addr, GFP_KERNEL);
3298         if (!ring->desc)
3299                 return -ENOMEM;
3300
3301         return 0;
3302 }
3303
3304 static int hns3_alloc_and_map_buffer(struct hns3_enet_ring *ring,
3305                                    struct hns3_desc_cb *cb)
3306 {
3307         int ret;
3308
3309         ret = hns3_alloc_buffer(ring, cb);
3310         if (ret || ring->page_pool)
3311                 goto out;
3312
3313         ret = hns3_map_buffer(ring, cb);
3314         if (ret)
3315                 goto out_with_buf;
3316
3317         return 0;
3318
3319 out_with_buf:
3320         hns3_free_buffer(ring, cb, 0);
3321 out:
3322         return ret;
3323 }
3324
3325 static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i)
3326 {
3327         int ret = hns3_alloc_and_map_buffer(ring, &ring->desc_cb[i]);
3328
3329         if (ret)
3330                 return ret;
3331
3332         ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3333                                          ring->desc_cb[i].page_offset);
3334
3335         return 0;
3336 }
3337
3338 /* Allocate memory for raw pkg, and map with dma */
3339 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
3340 {
3341         int i, j, ret;
3342
3343         for (i = 0; i < ring->desc_num; i++) {
3344                 ret = hns3_alloc_and_attach_buffer(ring, i);
3345                 if (ret)
3346                         goto out_buffer_fail;
3347         }
3348
3349         return 0;
3350
3351 out_buffer_fail:
3352         for (j = i - 1; j >= 0; j--)
3353                 hns3_free_buffer_detach(ring, j, 0);
3354         return ret;
3355 }
3356
3357 /* detach a in-used buffer and replace with a reserved one */
3358 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
3359                                 struct hns3_desc_cb *res_cb)
3360 {
3361         hns3_unmap_buffer(ring, &ring->desc_cb[i]);
3362         ring->desc_cb[i] = *res_cb;
3363         ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3364                                          ring->desc_cb[i].page_offset);
3365         ring->desc[i].rx.bd_base_info = 0;
3366 }
3367
3368 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
3369 {
3370         ring->desc_cb[i].reuse_flag = 0;
3371         ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3372                                          ring->desc_cb[i].page_offset);
3373         ring->desc[i].rx.bd_base_info = 0;
3374
3375         dma_sync_single_for_device(ring_to_dev(ring),
3376                         ring->desc_cb[i].dma + ring->desc_cb[i].page_offset,
3377                         hns3_buf_size(ring),
3378                         DMA_FROM_DEVICE);
3379 }
3380
3381 static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring,
3382                                   int *bytes, int *pkts, int budget)
3383 {
3384         /* pair with ring->last_to_use update in hns3_tx_doorbell(),
3385          * smp_store_release() is not used in hns3_tx_doorbell() because
3386          * the doorbell operation already have the needed barrier operation.
3387          */
3388         int ltu = smp_load_acquire(&ring->last_to_use);
3389         int ntc = ring->next_to_clean;
3390         struct hns3_desc_cb *desc_cb;
3391         bool reclaimed = false;
3392         struct hns3_desc *desc;
3393
3394         while (ltu != ntc) {
3395                 desc = &ring->desc[ntc];
3396
3397                 if (le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri) &
3398                                 BIT(HNS3_TXD_VLD_B))
3399                         break;
3400
3401                 desc_cb = &ring->desc_cb[ntc];
3402
3403                 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_ALL |
3404                                      DESC_TYPE_BOUNCE_HEAD |
3405                                      DESC_TYPE_SGL_SKB)) {
3406                         (*pkts)++;
3407                         (*bytes) += desc_cb->send_bytes;
3408                 }
3409
3410                 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */
3411                 hns3_free_buffer_detach(ring, ntc, budget);
3412
3413                 if (++ntc == ring->desc_num)
3414                         ntc = 0;
3415
3416                 /* Issue prefetch for next Tx descriptor */
3417                 prefetch(&ring->desc_cb[ntc]);
3418                 reclaimed = true;
3419         }
3420
3421         if (unlikely(!reclaimed))
3422                 return false;
3423
3424         /* This smp_store_release() pairs with smp_load_acquire() in
3425          * ring_space called by hns3_nic_net_xmit.
3426          */
3427         smp_store_release(&ring->next_to_clean, ntc);
3428
3429         hns3_tx_spare_update(ring);
3430
3431         return true;
3432 }
3433
3434 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget)
3435 {
3436         struct net_device *netdev = ring_to_netdev(ring);
3437         struct hns3_nic_priv *priv = netdev_priv(netdev);
3438         struct netdev_queue *dev_queue;
3439         int bytes, pkts;
3440
3441         bytes = 0;
3442         pkts = 0;
3443
3444         if (unlikely(!hns3_nic_reclaim_desc(ring, &bytes, &pkts, budget)))
3445                 return;
3446
3447         ring->tqp_vector->tx_group.total_bytes += bytes;
3448         ring->tqp_vector->tx_group.total_packets += pkts;
3449
3450         u64_stats_update_begin(&ring->syncp);
3451         ring->stats.tx_bytes += bytes;
3452         ring->stats.tx_pkts += pkts;
3453         u64_stats_update_end(&ring->syncp);
3454
3455         dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
3456         netdev_tx_completed_queue(dev_queue, pkts, bytes);
3457
3458         if (unlikely(netif_carrier_ok(netdev) &&
3459                      ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) {
3460                 /* Make sure that anybody stopping the queue after this
3461                  * sees the new next_to_clean.
3462                  */
3463                 smp_mb();
3464                 if (netif_tx_queue_stopped(dev_queue) &&
3465                     !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
3466                         netif_tx_wake_queue(dev_queue);
3467                         ring->stats.restart_queue++;
3468                 }
3469         }
3470 }
3471
3472 static int hns3_desc_unused(struct hns3_enet_ring *ring)
3473 {
3474         int ntc = ring->next_to_clean;
3475         int ntu = ring->next_to_use;
3476
3477         return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
3478 }
3479
3480 static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
3481                                       int cleand_count)
3482 {
3483         struct hns3_desc_cb *desc_cb;
3484         struct hns3_desc_cb res_cbs;
3485         int i, ret;
3486
3487         for (i = 0; i < cleand_count; i++) {
3488                 desc_cb = &ring->desc_cb[ring->next_to_use];
3489                 if (desc_cb->reuse_flag) {
3490                         u64_stats_update_begin(&ring->syncp);
3491                         ring->stats.reuse_pg_cnt++;
3492                         u64_stats_update_end(&ring->syncp);
3493
3494                         hns3_reuse_buffer(ring, ring->next_to_use);
3495                 } else {
3496                         ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
3497                         if (ret) {
3498                                 u64_stats_update_begin(&ring->syncp);
3499                                 ring->stats.sw_err_cnt++;
3500                                 u64_stats_update_end(&ring->syncp);
3501
3502                                 hns3_rl_err(ring_to_netdev(ring),
3503                                             "alloc rx buffer failed: %d\n",
3504                                             ret);
3505                                 break;
3506                         }
3507                         hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
3508
3509                         u64_stats_update_begin(&ring->syncp);
3510                         ring->stats.non_reuse_pg++;
3511                         u64_stats_update_end(&ring->syncp);
3512                 }
3513
3514                 ring_ptr_move_fw(ring, next_to_use);
3515         }
3516
3517         writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
3518 }
3519
3520 static bool hns3_can_reuse_page(struct hns3_desc_cb *cb)
3521 {
3522         return page_count(cb->priv) == cb->pagecnt_bias;
3523 }
3524
3525 static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
3526                                 struct hns3_enet_ring *ring, int pull_len,
3527                                 struct hns3_desc_cb *desc_cb)
3528 {
3529         struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
3530         u32 frag_offset = desc_cb->page_offset + pull_len;
3531         int size = le16_to_cpu(desc->rx.size);
3532         u32 truesize = hns3_buf_size(ring);
3533         u32 frag_size = size - pull_len;
3534         bool reused;
3535
3536         if (ring->page_pool) {
3537                 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset,
3538                                 frag_size, truesize);
3539                 return;
3540         }
3541
3542         /* Avoid re-using remote or pfmem page */
3543         if (unlikely(!dev_page_is_reusable(desc_cb->priv)))
3544                 goto out;
3545
3546         reused = hns3_can_reuse_page(desc_cb);
3547
3548         /* Rx page can be reused when:
3549          * 1. Rx page is only owned by the driver when page_offset
3550          *    is zero, which means 0 @ truesize will be used by
3551          *    stack after skb_add_rx_frag() is called, and the rest
3552          *    of rx page can be reused by driver.
3553          * Or
3554          * 2. Rx page is only owned by the driver when page_offset
3555          *    is non-zero, which means page_offset @ truesize will
3556          *    be used by stack after skb_add_rx_frag() is called,
3557          *    and 0 @ truesize can be reused by driver.
3558          */
3559         if ((!desc_cb->page_offset && reused) ||
3560             ((desc_cb->page_offset + truesize + truesize) <=
3561              hns3_page_size(ring) && desc_cb->page_offset)) {
3562                 desc_cb->page_offset += truesize;
3563                 desc_cb->reuse_flag = 1;
3564         } else if (desc_cb->page_offset && reused) {
3565                 desc_cb->page_offset = 0;
3566                 desc_cb->reuse_flag = 1;
3567         } else if (frag_size <= ring->rx_copybreak) {
3568                 void *frag = napi_alloc_frag(frag_size);
3569
3570                 if (unlikely(!frag)) {
3571                         u64_stats_update_begin(&ring->syncp);
3572                         ring->stats.frag_alloc_err++;
3573                         u64_stats_update_end(&ring->syncp);
3574
3575                         hns3_rl_err(ring_to_netdev(ring),
3576                                     "failed to allocate rx frag\n");
3577                         goto out;
3578                 }
3579
3580                 desc_cb->reuse_flag = 1;
3581                 memcpy(frag, desc_cb->buf + frag_offset, frag_size);
3582                 skb_add_rx_frag(skb, i, virt_to_page(frag),
3583                                 offset_in_page(frag), frag_size, frag_size);
3584
3585                 u64_stats_update_begin(&ring->syncp);
3586                 ring->stats.frag_alloc++;
3587                 u64_stats_update_end(&ring->syncp);
3588                 return;
3589         }
3590
3591 out:
3592         desc_cb->pagecnt_bias--;
3593
3594         if (unlikely(!desc_cb->pagecnt_bias)) {
3595                 page_ref_add(desc_cb->priv, USHRT_MAX);
3596                 desc_cb->pagecnt_bias = USHRT_MAX;
3597         }
3598
3599         skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset,
3600                         frag_size, truesize);
3601
3602         if (unlikely(!desc_cb->reuse_flag))
3603                 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias);
3604 }
3605
3606 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info)
3607 {
3608         __be16 type = skb->protocol;
3609         struct tcphdr *th;
3610         int depth = 0;
3611
3612         while (eth_type_vlan(type)) {
3613                 struct vlan_hdr *vh;
3614
3615                 if ((depth + VLAN_HLEN) > skb_headlen(skb))
3616                         return -EFAULT;
3617
3618                 vh = (struct vlan_hdr *)(skb->data + depth);
3619                 type = vh->h_vlan_encapsulated_proto;
3620                 depth += VLAN_HLEN;
3621         }
3622
3623         skb_set_network_header(skb, depth);
3624
3625         if (type == htons(ETH_P_IP)) {
3626                 const struct iphdr *iph = ip_hdr(skb);
3627
3628                 depth += sizeof(struct iphdr);
3629                 skb_set_transport_header(skb, depth);
3630                 th = tcp_hdr(skb);
3631                 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr,
3632                                           iph->daddr, 0);
3633         } else if (type == htons(ETH_P_IPV6)) {
3634                 const struct ipv6hdr *iph = ipv6_hdr(skb);
3635
3636                 depth += sizeof(struct ipv6hdr);
3637                 skb_set_transport_header(skb, depth);
3638                 th = tcp_hdr(skb);
3639                 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr,
3640                                           &iph->daddr, 0);
3641         } else {
3642                 hns3_rl_err(skb->dev,
3643                             "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n",
3644                             be16_to_cpu(type), depth);
3645                 return -EFAULT;
3646         }
3647
3648         skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
3649         if (th->cwr)
3650                 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
3651
3652         if (l234info & BIT(HNS3_RXD_GRO_FIXID_B))
3653                 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID;
3654
3655         skb->csum_start = (unsigned char *)th - skb->head;
3656         skb->csum_offset = offsetof(struct tcphdr, check);
3657         skb->ip_summed = CHECKSUM_PARTIAL;
3658
3659         trace_hns3_gro(skb);
3660
3661         return 0;
3662 }
3663
3664 static bool hns3_checksum_complete(struct hns3_enet_ring *ring,
3665                                    struct sk_buff *skb, u32 ptype, u16 csum)
3666 {
3667         if (ptype == HNS3_INVALID_PTYPE ||
3668             hns3_rx_ptype_tbl[ptype].ip_summed != CHECKSUM_COMPLETE)
3669                 return false;
3670
3671         u64_stats_update_begin(&ring->syncp);
3672         ring->stats.csum_complete++;
3673         u64_stats_update_end(&ring->syncp);
3674         skb->ip_summed = CHECKSUM_COMPLETE;
3675         skb->csum = csum_unfold((__force __sum16)csum);
3676
3677         return true;
3678 }
3679
3680 static void hns3_rx_handle_csum(struct sk_buff *skb, u32 l234info,
3681                                 u32 ol_info, u32 ptype)
3682 {
3683         int l3_type, l4_type;
3684         int ol4_type;
3685
3686         if (ptype != HNS3_INVALID_PTYPE) {
3687                 skb->csum_level = hns3_rx_ptype_tbl[ptype].csum_level;
3688                 skb->ip_summed = hns3_rx_ptype_tbl[ptype].ip_summed;
3689
3690                 return;
3691         }
3692
3693         ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M,
3694                                    HNS3_RXD_OL4ID_S);
3695         switch (ol4_type) {
3696         case HNS3_OL4_TYPE_MAC_IN_UDP:
3697         case HNS3_OL4_TYPE_NVGRE:
3698                 skb->csum_level = 1;
3699                 fallthrough;
3700         case HNS3_OL4_TYPE_NO_TUN:
3701                 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
3702                                           HNS3_RXD_L3ID_S);
3703                 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
3704                                           HNS3_RXD_L4ID_S);
3705                 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
3706                 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
3707                      l3_type == HNS3_L3_TYPE_IPV6) &&
3708                     (l4_type == HNS3_L4_TYPE_UDP ||
3709                      l4_type == HNS3_L4_TYPE_TCP ||
3710                      l4_type == HNS3_L4_TYPE_SCTP))
3711                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3712                 break;
3713         default:
3714                 break;
3715         }
3716 }
3717
3718 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
3719                              u32 l234info, u32 bd_base_info, u32 ol_info,
3720                              u16 csum)
3721 {
3722         struct net_device *netdev = ring_to_netdev(ring);
3723         struct hns3_nic_priv *priv = netdev_priv(netdev);
3724         u32 ptype = HNS3_INVALID_PTYPE;
3725
3726         skb->ip_summed = CHECKSUM_NONE;
3727
3728         skb_checksum_none_assert(skb);
3729
3730         if (!(netdev->features & NETIF_F_RXCSUM))
3731                 return;
3732
3733         if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state))
3734                 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
3735                                         HNS3_RXD_PTYPE_S);
3736
3737         if (hns3_checksum_complete(ring, skb, ptype, csum))
3738                 return;
3739
3740         /* check if hardware has done checksum */
3741         if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
3742                 return;
3743
3744         if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
3745                                  BIT(HNS3_RXD_OL3E_B) |
3746                                  BIT(HNS3_RXD_OL4E_B)))) {
3747                 u64_stats_update_begin(&ring->syncp);
3748                 ring->stats.l3l4_csum_err++;
3749                 u64_stats_update_end(&ring->syncp);
3750
3751                 return;
3752         }
3753
3754         hns3_rx_handle_csum(skb, l234info, ol_info, ptype);
3755 }
3756
3757 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
3758 {
3759         if (skb_has_frag_list(skb))
3760                 napi_gro_flush(&ring->tqp_vector->napi, false);
3761
3762         napi_gro_receive(&ring->tqp_vector->napi, skb);
3763 }
3764
3765 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
3766                                 struct hns3_desc *desc, u32 l234info,
3767                                 u16 *vlan_tag)
3768 {
3769         struct hnae3_handle *handle = ring->tqp->handle;
3770         struct pci_dev *pdev = ring->tqp->handle->pdev;
3771         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3772
3773         if (unlikely(ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)) {
3774                 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
3775                 if (!(*vlan_tag & VLAN_VID_MASK))
3776                         *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
3777
3778                 return (*vlan_tag != 0);
3779         }
3780
3781 #define HNS3_STRP_OUTER_VLAN    0x1
3782 #define HNS3_STRP_INNER_VLAN    0x2
3783 #define HNS3_STRP_BOTH          0x3
3784
3785         /* Hardware always insert VLAN tag into RX descriptor when
3786          * remove the tag from packet, driver needs to determine
3787          * reporting which tag to stack.
3788          */
3789         switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
3790                                 HNS3_RXD_STRP_TAGP_S)) {
3791         case HNS3_STRP_OUTER_VLAN:
3792                 if (handle->port_base_vlan_state !=
3793                                 HNAE3_PORT_BASE_VLAN_DISABLE)
3794                         return false;
3795
3796                 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
3797                 return true;
3798         case HNS3_STRP_INNER_VLAN:
3799                 if (handle->port_base_vlan_state !=
3800                                 HNAE3_PORT_BASE_VLAN_DISABLE)
3801                         return false;
3802
3803                 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
3804                 return true;
3805         case HNS3_STRP_BOTH:
3806                 if (handle->port_base_vlan_state ==
3807                                 HNAE3_PORT_BASE_VLAN_DISABLE)
3808                         *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
3809                 else
3810                         *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
3811
3812                 return true;
3813         default:
3814                 return false;
3815         }
3816 }
3817
3818 static void hns3_rx_ring_move_fw(struct hns3_enet_ring *ring)
3819 {
3820         ring->desc[ring->next_to_clean].rx.bd_base_info &=
3821                 cpu_to_le32(~BIT(HNS3_RXD_VLD_B));
3822         ring->next_to_clean += 1;
3823
3824         if (unlikely(ring->next_to_clean == ring->desc_num))
3825                 ring->next_to_clean = 0;
3826 }
3827
3828 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length,
3829                           unsigned char *va)
3830 {
3831         struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
3832         struct net_device *netdev = ring_to_netdev(ring);
3833         struct sk_buff *skb;
3834
3835         ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
3836         skb = ring->skb;
3837         if (unlikely(!skb)) {
3838                 hns3_rl_err(netdev, "alloc rx skb fail\n");
3839
3840                 u64_stats_update_begin(&ring->syncp);
3841                 ring->stats.sw_err_cnt++;
3842                 u64_stats_update_end(&ring->syncp);
3843
3844                 return -ENOMEM;
3845         }
3846
3847         trace_hns3_rx_desc(ring);
3848         prefetchw(skb->data);
3849
3850         ring->pending_buf = 1;
3851         ring->frag_num = 0;
3852         ring->tail_skb = NULL;
3853         if (length <= HNS3_RX_HEAD_SIZE) {
3854                 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
3855
3856                 /* We can reuse buffer as-is, just make sure it is reusable */
3857                 if (dev_page_is_reusable(desc_cb->priv))
3858                         desc_cb->reuse_flag = 1;
3859                 else if (desc_cb->type & DESC_TYPE_PP_FRAG)
3860                         page_pool_put_full_page(ring->page_pool, desc_cb->priv,
3861                                                 false);
3862                 else /* This page cannot be reused so discard it */
3863                         __page_frag_cache_drain(desc_cb->priv,
3864                                                 desc_cb->pagecnt_bias);
3865
3866                 hns3_rx_ring_move_fw(ring);
3867                 return 0;
3868         }
3869
3870         if (ring->page_pool)
3871                 skb_mark_for_recycle(skb);
3872
3873         u64_stats_update_begin(&ring->syncp);
3874         ring->stats.seg_pkt_cnt++;
3875         u64_stats_update_end(&ring->syncp);
3876
3877         ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE);
3878         __skb_put(skb, ring->pull_len);
3879         hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
3880                             desc_cb);
3881         hns3_rx_ring_move_fw(ring);
3882
3883         return 0;
3884 }
3885
3886 static int hns3_add_frag(struct hns3_enet_ring *ring)
3887 {
3888         struct sk_buff *skb = ring->skb;
3889         struct sk_buff *head_skb = skb;
3890         struct sk_buff *new_skb;
3891         struct hns3_desc_cb *desc_cb;
3892         struct hns3_desc *desc;
3893         u32 bd_base_info;
3894
3895         do {
3896                 desc = &ring->desc[ring->next_to_clean];
3897                 desc_cb = &ring->desc_cb[ring->next_to_clean];
3898                 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
3899                 /* make sure HW write desc complete */
3900                 dma_rmb();
3901                 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
3902                         return -ENXIO;
3903
3904                 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
3905                         new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0);
3906                         if (unlikely(!new_skb)) {
3907                                 hns3_rl_err(ring_to_netdev(ring),
3908                                             "alloc rx fraglist skb fail\n");
3909                                 return -ENXIO;
3910                         }
3911
3912                         if (ring->page_pool)
3913                                 skb_mark_for_recycle(new_skb);
3914
3915                         ring->frag_num = 0;
3916
3917                         if (ring->tail_skb) {
3918                                 ring->tail_skb->next = new_skb;
3919                                 ring->tail_skb = new_skb;
3920                         } else {
3921                                 skb_shinfo(skb)->frag_list = new_skb;
3922                                 ring->tail_skb = new_skb;
3923                         }
3924                 }
3925
3926                 if (ring->tail_skb) {
3927                         head_skb->truesize += hns3_buf_size(ring);
3928                         head_skb->data_len += le16_to_cpu(desc->rx.size);
3929                         head_skb->len += le16_to_cpu(desc->rx.size);
3930                         skb = ring->tail_skb;
3931                 }
3932
3933                 dma_sync_single_for_cpu(ring_to_dev(ring),
3934                                 desc_cb->dma + desc_cb->page_offset,
3935                                 hns3_buf_size(ring),
3936                                 DMA_FROM_DEVICE);
3937
3938                 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
3939                 trace_hns3_rx_desc(ring);
3940                 hns3_rx_ring_move_fw(ring);
3941                 ring->pending_buf++;
3942         } while (!(bd_base_info & BIT(HNS3_RXD_FE_B)));
3943
3944         return 0;
3945 }
3946
3947 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring,
3948                                      struct sk_buff *skb, u32 l234info,
3949                                      u32 bd_base_info, u32 ol_info, u16 csum)
3950 {
3951         struct net_device *netdev = ring_to_netdev(ring);
3952         struct hns3_nic_priv *priv = netdev_priv(netdev);
3953         u32 l3_type;
3954
3955         skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
3956                                                     HNS3_RXD_GRO_SIZE_M,
3957                                                     HNS3_RXD_GRO_SIZE_S);
3958         /* if there is no HW GRO, do not set gro params */
3959         if (!skb_shinfo(skb)->gso_size) {
3960                 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info,
3961                                  csum);
3962                 return 0;
3963         }
3964
3965         NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info,
3966                                                   HNS3_RXD_GRO_COUNT_M,
3967                                                   HNS3_RXD_GRO_COUNT_S);
3968
3969         if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) {
3970                 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
3971                                             HNS3_RXD_PTYPE_S);
3972
3973                 l3_type = hns3_rx_ptype_tbl[ptype].l3_type;
3974         } else {
3975                 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
3976                                           HNS3_RXD_L3ID_S);
3977         }
3978
3979         if (l3_type == HNS3_L3_TYPE_IPV4)
3980                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
3981         else if (l3_type == HNS3_L3_TYPE_IPV6)
3982                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
3983         else
3984                 return -EFAULT;
3985
3986         return  hns3_gro_complete(skb, l234info);
3987 }
3988
3989 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
3990                                      struct sk_buff *skb, u32 rss_hash)
3991 {
3992         struct hnae3_handle *handle = ring->tqp->handle;
3993         enum pkt_hash_types rss_type;
3994
3995         if (rss_hash)
3996                 rss_type = handle->kinfo.rss_type;
3997         else
3998                 rss_type = PKT_HASH_TYPE_NONE;
3999
4000         skb_set_hash(skb, rss_hash, rss_type);
4001 }
4002
4003 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb)
4004 {
4005         struct net_device *netdev = ring_to_netdev(ring);
4006         enum hns3_pkt_l2t_type l2_frame_type;
4007         u32 bd_base_info, l234info, ol_info;
4008         struct hns3_desc *desc;
4009         unsigned int len;
4010         int pre_ntc, ret;
4011         u16 csum;
4012
4013         /* bdinfo handled below is only valid on the last BD of the
4014          * current packet, and ring->next_to_clean indicates the first
4015          * descriptor of next packet, so need - 1 below.
4016          */
4017         pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) :
4018                                         (ring->desc_num - 1);
4019         desc = &ring->desc[pre_ntc];
4020         bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4021         l234info = le32_to_cpu(desc->rx.l234_info);
4022         ol_info = le32_to_cpu(desc->rx.ol_info);
4023         csum = le16_to_cpu(desc->csum);
4024
4025         if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) {
4026                 struct hnae3_handle *h = hns3_get_handle(netdev);
4027                 u32 nsec = le32_to_cpu(desc->ts_nsec);
4028                 u32 sec = le32_to_cpu(desc->ts_sec);
4029
4030                 if (h->ae_algo->ops->get_rx_hwts)
4031                         h->ae_algo->ops->get_rx_hwts(h, skb, nsec, sec);
4032         }
4033
4034         /* Based on hw strategy, the tag offloaded will be stored at
4035          * ot_vlan_tag in two layer tag case, and stored at vlan_tag
4036          * in one layer tag case.
4037          */
4038         if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
4039                 u16 vlan_tag;
4040
4041                 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
4042                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
4043                                                vlan_tag);
4044         }
4045
4046         if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) |
4047                                   BIT(HNS3_RXD_L2E_B))))) {
4048                 u64_stats_update_begin(&ring->syncp);
4049                 if (l234info & BIT(HNS3_RXD_L2E_B))
4050                         ring->stats.l2_err++;
4051                 else
4052                         ring->stats.err_pkt_len++;
4053                 u64_stats_update_end(&ring->syncp);
4054
4055                 return -EFAULT;
4056         }
4057
4058         len = skb->len;
4059
4060         /* Do update ip stack process */
4061         skb->protocol = eth_type_trans(skb, netdev);
4062
4063         /* This is needed in order to enable forwarding support */
4064         ret = hns3_set_gro_and_checksum(ring, skb, l234info,
4065                                         bd_base_info, ol_info, csum);
4066         if (unlikely(ret)) {
4067                 u64_stats_update_begin(&ring->syncp);
4068                 ring->stats.rx_err_cnt++;
4069                 u64_stats_update_end(&ring->syncp);
4070                 return ret;
4071         }
4072
4073         l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
4074                                         HNS3_RXD_DMAC_S);
4075
4076         u64_stats_update_begin(&ring->syncp);
4077         ring->stats.rx_pkts++;
4078         ring->stats.rx_bytes += len;
4079
4080         if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
4081                 ring->stats.rx_multicast++;
4082
4083         u64_stats_update_end(&ring->syncp);
4084
4085         ring->tqp_vector->rx_group.total_bytes += len;
4086
4087         hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash));
4088         return 0;
4089 }
4090
4091 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring)
4092 {
4093         struct sk_buff *skb = ring->skb;
4094         struct hns3_desc_cb *desc_cb;
4095         struct hns3_desc *desc;
4096         unsigned int length;
4097         u32 bd_base_info;
4098         int ret;
4099
4100         desc = &ring->desc[ring->next_to_clean];
4101         desc_cb = &ring->desc_cb[ring->next_to_clean];
4102
4103         prefetch(desc);
4104
4105         if (!skb) {
4106                 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4107                 /* Check valid BD */
4108                 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
4109                         return -ENXIO;
4110
4111                 dma_rmb();
4112                 length = le16_to_cpu(desc->rx.size);
4113
4114                 ring->va = desc_cb->buf + desc_cb->page_offset;
4115
4116                 dma_sync_single_for_cpu(ring_to_dev(ring),
4117                                 desc_cb->dma + desc_cb->page_offset,
4118                                 hns3_buf_size(ring),
4119                                 DMA_FROM_DEVICE);
4120
4121                 /* Prefetch first cache line of first page.
4122                  * Idea is to cache few bytes of the header of the packet.
4123                  * Our L1 Cache line size is 64B so need to prefetch twice to make
4124                  * it 128B. But in actual we can have greater size of caches with
4125                  * 128B Level 1 cache lines. In such a case, single fetch would
4126                  * suffice to cache in the relevant part of the header.
4127                  */
4128                 net_prefetch(ring->va);
4129
4130                 ret = hns3_alloc_skb(ring, length, ring->va);
4131                 skb = ring->skb;
4132
4133                 if (ret < 0) /* alloc buffer fail */
4134                         return ret;
4135                 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */
4136                         ret = hns3_add_frag(ring);
4137                         if (ret)
4138                                 return ret;
4139                 }
4140         } else {
4141                 ret = hns3_add_frag(ring);
4142                 if (ret)
4143                         return ret;
4144         }
4145
4146         /* As the head data may be changed when GRO enable, copy
4147          * the head data in after other data rx completed
4148          */
4149         if (skb->len > HNS3_RX_HEAD_SIZE)
4150                 memcpy(skb->data, ring->va,
4151                        ALIGN(ring->pull_len, sizeof(long)));
4152
4153         ret = hns3_handle_bdinfo(ring, skb);
4154         if (unlikely(ret)) {
4155                 dev_kfree_skb_any(skb);
4156                 return ret;
4157         }
4158
4159         skb_record_rx_queue(skb, ring->tqp->tqp_index);
4160         return 0;
4161 }
4162
4163 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
4164                        void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
4165 {
4166 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
4167         int unused_count = hns3_desc_unused(ring);
4168         int recv_pkts = 0;
4169         int err;
4170
4171         unused_count -= ring->pending_buf;
4172
4173         while (recv_pkts < budget) {
4174                 /* Reuse or realloc buffers */
4175                 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
4176                         hns3_nic_alloc_rx_buffers(ring, unused_count);
4177                         unused_count = hns3_desc_unused(ring) -
4178                                         ring->pending_buf;
4179                 }
4180
4181                 /* Poll one pkt */
4182                 err = hns3_handle_rx_bd(ring);
4183                 /* Do not get FE for the packet or failed to alloc skb */
4184                 if (unlikely(!ring->skb || err == -ENXIO)) {
4185                         goto out;
4186                 } else if (likely(!err)) {
4187                         rx_fn(ring, ring->skb);
4188                         recv_pkts++;
4189                 }
4190
4191                 unused_count += ring->pending_buf;
4192                 ring->skb = NULL;
4193                 ring->pending_buf = 0;
4194         }
4195
4196 out:
4197         /* Make all data has been write before submit */
4198         if (unused_count > 0)
4199                 hns3_nic_alloc_rx_buffers(ring, unused_count);
4200
4201         return recv_pkts;
4202 }
4203
4204 static void hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector)
4205 {
4206         struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
4207         struct dim_sample sample = {};
4208
4209         if (!rx_group->coal.adapt_enable)
4210                 return;
4211
4212         dim_update_sample(tqp_vector->event_cnt, rx_group->total_packets,
4213                           rx_group->total_bytes, &sample);
4214         net_dim(&rx_group->dim, sample);
4215 }
4216
4217 static void hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector)
4218 {
4219         struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
4220         struct dim_sample sample = {};
4221
4222         if (!tx_group->coal.adapt_enable)
4223                 return;
4224
4225         dim_update_sample(tqp_vector->event_cnt, tx_group->total_packets,
4226                           tx_group->total_bytes, &sample);
4227         net_dim(&tx_group->dim, sample);
4228 }
4229
4230 static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
4231 {
4232         struct hns3_nic_priv *priv = netdev_priv(napi->dev);
4233         struct hns3_enet_ring *ring;
4234         int rx_pkt_total = 0;
4235
4236         struct hns3_enet_tqp_vector *tqp_vector =
4237                 container_of(napi, struct hns3_enet_tqp_vector, napi);
4238         bool clean_complete = true;
4239         int rx_budget = budget;
4240
4241         if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
4242                 napi_complete(napi);
4243                 return 0;
4244         }
4245
4246         /* Since the actual Tx work is minimal, we can give the Tx a larger
4247          * budget and be more aggressive about cleaning up the Tx descriptors.
4248          */
4249         hns3_for_each_ring(ring, tqp_vector->tx_group)
4250                 hns3_clean_tx_ring(ring, budget);
4251
4252         /* make sure rx ring budget not smaller than 1 */
4253         if (tqp_vector->num_tqps > 1)
4254                 rx_budget = max(budget / tqp_vector->num_tqps, 1);
4255
4256         hns3_for_each_ring(ring, tqp_vector->rx_group) {
4257                 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
4258                                                     hns3_rx_skb);
4259                 if (rx_cleaned >= rx_budget)
4260                         clean_complete = false;
4261
4262                 rx_pkt_total += rx_cleaned;
4263         }
4264
4265         tqp_vector->rx_group.total_packets += rx_pkt_total;
4266
4267         if (!clean_complete)
4268                 return budget;
4269
4270         if (napi_complete(napi) &&
4271             likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
4272                 hns3_update_rx_int_coalesce(tqp_vector);
4273                 hns3_update_tx_int_coalesce(tqp_vector);
4274
4275                 hns3_mask_vector_irq(tqp_vector, 1);
4276         }
4277
4278         return rx_pkt_total;
4279 }
4280
4281 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
4282                                       struct hnae3_ring_chain_node *head)
4283 {
4284         struct pci_dev *pdev = tqp_vector->handle->pdev;
4285         struct hnae3_ring_chain_node *cur_chain = head;
4286         struct hnae3_ring_chain_node *chain;
4287         struct hns3_enet_ring *tx_ring;
4288         struct hns3_enet_ring *rx_ring;
4289
4290         tx_ring = tqp_vector->tx_group.ring;
4291         if (tx_ring) {
4292                 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
4293                 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
4294                               HNAE3_RING_TYPE_TX);
4295                 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
4296                                 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
4297
4298                 cur_chain->next = NULL;
4299
4300                 while (tx_ring->next) {
4301                         tx_ring = tx_ring->next;
4302
4303                         chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
4304                                              GFP_KERNEL);
4305                         if (!chain)
4306                                 goto err_free_chain;
4307
4308                         cur_chain->next = chain;
4309                         chain->tqp_index = tx_ring->tqp->tqp_index;
4310                         hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
4311                                       HNAE3_RING_TYPE_TX);
4312                         hnae3_set_field(chain->int_gl_idx,
4313                                         HNAE3_RING_GL_IDX_M,
4314                                         HNAE3_RING_GL_IDX_S,
4315                                         HNAE3_RING_GL_TX);
4316
4317                         cur_chain = chain;
4318                 }
4319         }
4320
4321         rx_ring = tqp_vector->rx_group.ring;
4322         if (!tx_ring && rx_ring) {
4323                 cur_chain->next = NULL;
4324                 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
4325                 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
4326                               HNAE3_RING_TYPE_RX);
4327                 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
4328                                 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
4329
4330                 rx_ring = rx_ring->next;
4331         }
4332
4333         while (rx_ring) {
4334                 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
4335                 if (!chain)
4336                         goto err_free_chain;
4337
4338                 cur_chain->next = chain;
4339                 chain->tqp_index = rx_ring->tqp->tqp_index;
4340                 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
4341                               HNAE3_RING_TYPE_RX);
4342                 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
4343                                 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
4344
4345                 cur_chain = chain;
4346
4347                 rx_ring = rx_ring->next;
4348         }
4349
4350         return 0;
4351
4352 err_free_chain:
4353         cur_chain = head->next;
4354         while (cur_chain) {
4355                 chain = cur_chain->next;
4356                 devm_kfree(&pdev->dev, cur_chain);
4357                 cur_chain = chain;
4358         }
4359         head->next = NULL;
4360
4361         return -ENOMEM;
4362 }
4363
4364 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
4365                                         struct hnae3_ring_chain_node *head)
4366 {
4367         struct pci_dev *pdev = tqp_vector->handle->pdev;
4368         struct hnae3_ring_chain_node *chain_tmp, *chain;
4369
4370         chain = head->next;
4371
4372         while (chain) {
4373                 chain_tmp = chain->next;
4374                 devm_kfree(&pdev->dev, chain);
4375                 chain = chain_tmp;
4376         }
4377 }
4378
4379 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
4380                                    struct hns3_enet_ring *ring)
4381 {
4382         ring->next = group->ring;
4383         group->ring = ring;
4384
4385         group->count++;
4386 }
4387
4388 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
4389 {
4390         struct pci_dev *pdev = priv->ae_handle->pdev;
4391         struct hns3_enet_tqp_vector *tqp_vector;
4392         int num_vectors = priv->vector_num;
4393         int numa_node;
4394         int vector_i;
4395
4396         numa_node = dev_to_node(&pdev->dev);
4397
4398         for (vector_i = 0; vector_i < num_vectors; vector_i++) {
4399                 tqp_vector = &priv->tqp_vector[vector_i];
4400                 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
4401                                 &tqp_vector->affinity_mask);
4402         }
4403 }
4404
4405 static void hns3_rx_dim_work(struct work_struct *work)
4406 {
4407         struct dim *dim = container_of(work, struct dim, work);
4408         struct hns3_enet_ring_group *group = container_of(dim,
4409                 struct hns3_enet_ring_group, dim);
4410         struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector;
4411         struct dim_cq_moder cur_moder =
4412                 net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
4413
4414         hns3_set_vector_coalesce_rx_gl(group->ring->tqp_vector, cur_moder.usec);
4415         tqp_vector->rx_group.coal.int_gl = cur_moder.usec;
4416
4417         if (cur_moder.pkts < tqp_vector->rx_group.coal.int_ql_max) {
4418                 hns3_set_vector_coalesce_rx_ql(tqp_vector, cur_moder.pkts);
4419                 tqp_vector->rx_group.coal.int_ql = cur_moder.pkts;
4420         }
4421
4422         dim->state = DIM_START_MEASURE;
4423 }
4424
4425 static void hns3_tx_dim_work(struct work_struct *work)
4426 {
4427         struct dim *dim = container_of(work, struct dim, work);
4428         struct hns3_enet_ring_group *group = container_of(dim,
4429                 struct hns3_enet_ring_group, dim);
4430         struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector;
4431         struct dim_cq_moder cur_moder =
4432                 net_dim_get_tx_moderation(dim->mode, dim->profile_ix);
4433
4434         hns3_set_vector_coalesce_tx_gl(tqp_vector, cur_moder.usec);
4435         tqp_vector->tx_group.coal.int_gl = cur_moder.usec;
4436
4437         if (cur_moder.pkts < tqp_vector->tx_group.coal.int_ql_max) {
4438                 hns3_set_vector_coalesce_tx_ql(tqp_vector, cur_moder.pkts);
4439                 tqp_vector->tx_group.coal.int_ql = cur_moder.pkts;
4440         }
4441
4442         dim->state = DIM_START_MEASURE;
4443 }
4444
4445 static void hns3_nic_init_dim(struct hns3_enet_tqp_vector *tqp_vector)
4446 {
4447         INIT_WORK(&tqp_vector->rx_group.dim.work, hns3_rx_dim_work);
4448         INIT_WORK(&tqp_vector->tx_group.dim.work, hns3_tx_dim_work);
4449 }
4450
4451 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
4452 {
4453         struct hnae3_handle *h = priv->ae_handle;
4454         struct hns3_enet_tqp_vector *tqp_vector;
4455         int ret;
4456         int i;
4457
4458         hns3_nic_set_cpumask(priv);
4459
4460         for (i = 0; i < priv->vector_num; i++) {
4461                 tqp_vector = &priv->tqp_vector[i];
4462                 hns3_vector_coalesce_init_hw(tqp_vector, priv);
4463                 tqp_vector->num_tqps = 0;
4464                 hns3_nic_init_dim(tqp_vector);
4465         }
4466
4467         for (i = 0; i < h->kinfo.num_tqps; i++) {
4468                 u16 vector_i = i % priv->vector_num;
4469                 u16 tqp_num = h->kinfo.num_tqps;
4470
4471                 tqp_vector = &priv->tqp_vector[vector_i];
4472
4473                 hns3_add_ring_to_group(&tqp_vector->tx_group,
4474                                        &priv->ring[i]);
4475
4476                 hns3_add_ring_to_group(&tqp_vector->rx_group,
4477                                        &priv->ring[i + tqp_num]);
4478
4479                 priv->ring[i].tqp_vector = tqp_vector;
4480                 priv->ring[i + tqp_num].tqp_vector = tqp_vector;
4481                 tqp_vector->num_tqps++;
4482         }
4483
4484         for (i = 0; i < priv->vector_num; i++) {
4485                 struct hnae3_ring_chain_node vector_ring_chain;
4486
4487                 tqp_vector = &priv->tqp_vector[i];
4488
4489                 tqp_vector->rx_group.total_bytes = 0;
4490                 tqp_vector->rx_group.total_packets = 0;
4491                 tqp_vector->tx_group.total_bytes = 0;
4492                 tqp_vector->tx_group.total_packets = 0;
4493                 tqp_vector->handle = h;
4494
4495                 ret = hns3_get_vector_ring_chain(tqp_vector,
4496                                                  &vector_ring_chain);
4497                 if (ret)
4498                         goto map_ring_fail;
4499
4500                 ret = h->ae_algo->ops->map_ring_to_vector(h,
4501                         tqp_vector->vector_irq, &vector_ring_chain);
4502
4503                 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
4504
4505                 if (ret)
4506                         goto map_ring_fail;
4507
4508                 netif_napi_add(priv->netdev, &tqp_vector->napi,
4509                                hns3_nic_common_poll, NAPI_POLL_WEIGHT);
4510         }
4511
4512         return 0;
4513
4514 map_ring_fail:
4515         while (i--)
4516                 netif_napi_del(&priv->tqp_vector[i].napi);
4517
4518         return ret;
4519 }
4520
4521 static void hns3_nic_init_coal_cfg(struct hns3_nic_priv *priv)
4522 {
4523         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
4524         struct hns3_enet_coalesce *tx_coal = &priv->tx_coal;
4525         struct hns3_enet_coalesce *rx_coal = &priv->rx_coal;
4526
4527         /* initialize the configuration for interrupt coalescing.
4528          * 1. GL (Interrupt Gap Limiter)
4529          * 2. RL (Interrupt Rate Limiter)
4530          * 3. QL (Interrupt Quantity Limiter)
4531          *
4532          * Default: enable interrupt coalescing self-adaptive and GL
4533          */
4534         tx_coal->adapt_enable = 1;
4535         rx_coal->adapt_enable = 1;
4536
4537         tx_coal->int_gl = HNS3_INT_GL_50K;
4538         rx_coal->int_gl = HNS3_INT_GL_50K;
4539
4540         rx_coal->flow_level = HNS3_FLOW_LOW;
4541         tx_coal->flow_level = HNS3_FLOW_LOW;
4542
4543         if (ae_dev->dev_specs.int_ql_max) {
4544                 tx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
4545                 rx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
4546         }
4547 }
4548
4549 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
4550 {
4551         struct hnae3_handle *h = priv->ae_handle;
4552         struct hns3_enet_tqp_vector *tqp_vector;
4553         struct hnae3_vector_info *vector;
4554         struct pci_dev *pdev = h->pdev;
4555         u16 tqp_num = h->kinfo.num_tqps;
4556         u16 vector_num;
4557         int ret = 0;
4558         u16 i;
4559
4560         /* RSS size, cpu online and vector_num should be the same */
4561         /* Should consider 2p/4p later */
4562         vector_num = min_t(u16, num_online_cpus(), tqp_num);
4563
4564         vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
4565                               GFP_KERNEL);
4566         if (!vector)
4567                 return -ENOMEM;
4568
4569         /* save the actual available vector number */
4570         vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
4571
4572         priv->vector_num = vector_num;
4573         priv->tqp_vector = (struct hns3_enet_tqp_vector *)
4574                 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
4575                              GFP_KERNEL);
4576         if (!priv->tqp_vector) {
4577                 ret = -ENOMEM;
4578                 goto out;
4579         }
4580
4581         for (i = 0; i < priv->vector_num; i++) {
4582                 tqp_vector = &priv->tqp_vector[i];
4583                 tqp_vector->idx = i;
4584                 tqp_vector->mask_addr = vector[i].io_addr;
4585                 tqp_vector->vector_irq = vector[i].vector;
4586                 hns3_vector_coalesce_init(tqp_vector, priv);
4587         }
4588
4589 out:
4590         devm_kfree(&pdev->dev, vector);
4591         return ret;
4592 }
4593
4594 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
4595 {
4596         group->ring = NULL;
4597         group->count = 0;
4598 }
4599
4600 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
4601 {
4602         struct hnae3_ring_chain_node vector_ring_chain;
4603         struct hnae3_handle *h = priv->ae_handle;
4604         struct hns3_enet_tqp_vector *tqp_vector;
4605         int i;
4606
4607         for (i = 0; i < priv->vector_num; i++) {
4608                 tqp_vector = &priv->tqp_vector[i];
4609
4610                 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
4611                         continue;
4612
4613                 /* Since the mapping can be overwritten, when fail to get the
4614                  * chain between vector and ring, we should go on to deal with
4615                  * the remaining options.
4616                  */
4617                 if (hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain))
4618                         dev_warn(priv->dev, "failed to get ring chain\n");
4619
4620                 h->ae_algo->ops->unmap_ring_from_vector(h,
4621                         tqp_vector->vector_irq, &vector_ring_chain);
4622
4623                 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
4624
4625                 hns3_clear_ring_group(&tqp_vector->rx_group);
4626                 hns3_clear_ring_group(&tqp_vector->tx_group);
4627                 netif_napi_del(&priv->tqp_vector[i].napi);
4628         }
4629 }
4630
4631 static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
4632 {
4633         struct hnae3_handle *h = priv->ae_handle;
4634         struct pci_dev *pdev = h->pdev;
4635         int i, ret;
4636
4637         for (i = 0; i < priv->vector_num; i++) {
4638                 struct hns3_enet_tqp_vector *tqp_vector;
4639
4640                 tqp_vector = &priv->tqp_vector[i];
4641                 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
4642                 if (ret)
4643                         return;
4644         }
4645
4646         devm_kfree(&pdev->dev, priv->tqp_vector);
4647 }
4648
4649 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
4650                               unsigned int ring_type)
4651 {
4652         int queue_num = priv->ae_handle->kinfo.num_tqps;
4653         struct hns3_enet_ring *ring;
4654         int desc_num;
4655
4656         if (ring_type == HNAE3_RING_TYPE_TX) {
4657                 ring = &priv->ring[q->tqp_index];
4658                 desc_num = priv->ae_handle->kinfo.num_tx_desc;
4659                 ring->queue_index = q->tqp_index;
4660                 ring->tx_copybreak = priv->tx_copybreak;
4661                 ring->last_to_use = 0;
4662         } else {
4663                 ring = &priv->ring[q->tqp_index + queue_num];
4664                 desc_num = priv->ae_handle->kinfo.num_rx_desc;
4665                 ring->queue_index = q->tqp_index;
4666                 ring->rx_copybreak = priv->rx_copybreak;
4667         }
4668
4669         hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
4670
4671         ring->tqp = q;
4672         ring->desc = NULL;
4673         ring->desc_cb = NULL;
4674         ring->dev = priv->dev;
4675         ring->desc_dma_addr = 0;
4676         ring->buf_size = q->buf_size;
4677         ring->desc_num = desc_num;
4678         ring->next_to_use = 0;
4679         ring->next_to_clean = 0;
4680 }
4681
4682 static void hns3_queue_to_ring(struct hnae3_queue *tqp,
4683                                struct hns3_nic_priv *priv)
4684 {
4685         hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
4686         hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
4687 }
4688
4689 static int hns3_get_ring_config(struct hns3_nic_priv *priv)
4690 {
4691         struct hnae3_handle *h = priv->ae_handle;
4692         struct pci_dev *pdev = h->pdev;
4693         int i;
4694
4695         priv->ring = devm_kzalloc(&pdev->dev,
4696                                   array3_size(h->kinfo.num_tqps,
4697                                               sizeof(*priv->ring), 2),
4698                                   GFP_KERNEL);
4699         if (!priv->ring)
4700                 return -ENOMEM;
4701
4702         for (i = 0; i < h->kinfo.num_tqps; i++)
4703                 hns3_queue_to_ring(h->kinfo.tqp[i], priv);
4704
4705         return 0;
4706 }
4707
4708 static void hns3_put_ring_config(struct hns3_nic_priv *priv)
4709 {
4710         if (!priv->ring)
4711                 return;
4712
4713         devm_kfree(priv->dev, priv->ring);
4714         priv->ring = NULL;
4715 }
4716
4717 static void hns3_alloc_page_pool(struct hns3_enet_ring *ring)
4718 {
4719         struct page_pool_params pp_params = {
4720                 .flags = PP_FLAG_DMA_MAP | PP_FLAG_PAGE_FRAG |
4721                                 PP_FLAG_DMA_SYNC_DEV,
4722                 .order = hns3_page_order(ring),
4723                 .pool_size = ring->desc_num * hns3_buf_size(ring) /
4724                                 (PAGE_SIZE << hns3_page_order(ring)),
4725                 .nid = dev_to_node(ring_to_dev(ring)),
4726                 .dev = ring_to_dev(ring),
4727                 .dma_dir = DMA_FROM_DEVICE,
4728                 .offset = 0,
4729                 .max_len = PAGE_SIZE << hns3_page_order(ring),
4730         };
4731
4732         ring->page_pool = page_pool_create(&pp_params);
4733         if (IS_ERR(ring->page_pool)) {
4734                 dev_warn(ring_to_dev(ring), "page pool creation failed: %ld\n",
4735                          PTR_ERR(ring->page_pool));
4736                 ring->page_pool = NULL;
4737         }
4738 }
4739
4740 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
4741 {
4742         int ret;
4743
4744         if (ring->desc_num <= 0 || ring->buf_size <= 0)
4745                 return -EINVAL;
4746
4747         ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num,
4748                                      sizeof(ring->desc_cb[0]), GFP_KERNEL);
4749         if (!ring->desc_cb) {
4750                 ret = -ENOMEM;
4751                 goto out;
4752         }
4753
4754         ret = hns3_alloc_desc(ring);
4755         if (ret)
4756                 goto out_with_desc_cb;
4757
4758         if (!HNAE3_IS_TX_RING(ring)) {
4759                 if (page_pool_enabled)
4760                         hns3_alloc_page_pool(ring);
4761
4762                 ret = hns3_alloc_ring_buffers(ring);
4763                 if (ret)
4764                         goto out_with_desc;
4765         } else {
4766                 hns3_init_tx_spare_buffer(ring);
4767         }
4768
4769         return 0;
4770
4771 out_with_desc:
4772         hns3_free_desc(ring);
4773 out_with_desc_cb:
4774         devm_kfree(ring_to_dev(ring), ring->desc_cb);
4775         ring->desc_cb = NULL;
4776 out:
4777         return ret;
4778 }
4779
4780 void hns3_fini_ring(struct hns3_enet_ring *ring)
4781 {
4782         hns3_free_desc(ring);
4783         devm_kfree(ring_to_dev(ring), ring->desc_cb);
4784         ring->desc_cb = NULL;
4785         ring->next_to_clean = 0;
4786         ring->next_to_use = 0;
4787         ring->last_to_use = 0;
4788         ring->pending_buf = 0;
4789         if (!HNAE3_IS_TX_RING(ring) && ring->skb) {
4790                 dev_kfree_skb_any(ring->skb);
4791                 ring->skb = NULL;
4792         } else if (HNAE3_IS_TX_RING(ring) && ring->tx_spare) {
4793                 struct hns3_tx_spare *tx_spare = ring->tx_spare;
4794
4795                 dma_unmap_page(ring_to_dev(ring), tx_spare->dma, tx_spare->len,
4796                                DMA_TO_DEVICE);
4797                 free_pages((unsigned long)tx_spare->buf,
4798                            get_order(tx_spare->len));
4799                 devm_kfree(ring_to_dev(ring), tx_spare);
4800                 ring->tx_spare = NULL;
4801         }
4802
4803         if (!HNAE3_IS_TX_RING(ring) && ring->page_pool) {
4804                 page_pool_destroy(ring->page_pool);
4805                 ring->page_pool = NULL;
4806         }
4807 }
4808
4809 static int hns3_buf_size2type(u32 buf_size)
4810 {
4811         int bd_size_type;
4812
4813         switch (buf_size) {
4814         case 512:
4815                 bd_size_type = HNS3_BD_SIZE_512_TYPE;
4816                 break;
4817         case 1024:
4818                 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
4819                 break;
4820         case 2048:
4821                 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
4822                 break;
4823         case 4096:
4824                 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
4825                 break;
4826         default:
4827                 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
4828         }
4829
4830         return bd_size_type;
4831 }
4832
4833 static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
4834 {
4835         dma_addr_t dma = ring->desc_dma_addr;
4836         struct hnae3_queue *q = ring->tqp;
4837
4838         if (!HNAE3_IS_TX_RING(ring)) {
4839                 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma);
4840                 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
4841                                (u32)((dma >> 31) >> 1));
4842
4843                 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
4844                                hns3_buf_size2type(ring->buf_size));
4845                 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
4846                                ring->desc_num / 8 - 1);
4847         } else {
4848                 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
4849                                (u32)dma);
4850                 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
4851                                (u32)((dma >> 31) >> 1));
4852
4853                 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
4854                                ring->desc_num / 8 - 1);
4855         }
4856 }
4857
4858 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
4859 {
4860         struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
4861         struct hnae3_tc_info *tc_info = &kinfo->tc_info;
4862         int i;
4863
4864         for (i = 0; i < HNAE3_MAX_TC; i++) {
4865                 int j;
4866
4867                 if (!test_bit(i, &tc_info->tc_en))
4868                         continue;
4869
4870                 for (j = 0; j < tc_info->tqp_count[i]; j++) {
4871                         struct hnae3_queue *q;
4872
4873                         q = priv->ring[tc_info->tqp_offset[i] + j].tqp;
4874                         hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, i);
4875                 }
4876         }
4877 }
4878
4879 int hns3_init_all_ring(struct hns3_nic_priv *priv)
4880 {
4881         struct hnae3_handle *h = priv->ae_handle;
4882         int ring_num = h->kinfo.num_tqps * 2;
4883         int i, j;
4884         int ret;
4885
4886         for (i = 0; i < ring_num; i++) {
4887                 ret = hns3_alloc_ring_memory(&priv->ring[i]);
4888                 if (ret) {
4889                         dev_err(priv->dev,
4890                                 "Alloc ring memory fail! ret=%d\n", ret);
4891                         goto out_when_alloc_ring_memory;
4892                 }
4893
4894                 u64_stats_init(&priv->ring[i].syncp);
4895         }
4896
4897         return 0;
4898
4899 out_when_alloc_ring_memory:
4900         for (j = i - 1; j >= 0; j--)
4901                 hns3_fini_ring(&priv->ring[j]);
4902
4903         return -ENOMEM;
4904 }
4905
4906 static void hns3_uninit_all_ring(struct hns3_nic_priv *priv)
4907 {
4908         struct hnae3_handle *h = priv->ae_handle;
4909         int i;
4910
4911         for (i = 0; i < h->kinfo.num_tqps; i++) {
4912                 hns3_fini_ring(&priv->ring[i]);
4913                 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]);
4914         }
4915 }
4916
4917 /* Set mac addr if it is configured. or leave it to the AE driver */
4918 static int hns3_init_mac_addr(struct net_device *netdev)
4919 {
4920         struct hns3_nic_priv *priv = netdev_priv(netdev);
4921         struct hnae3_handle *h = priv->ae_handle;
4922         u8 mac_addr_temp[ETH_ALEN];
4923         int ret = 0;
4924
4925         if (h->ae_algo->ops->get_mac_addr)
4926                 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
4927
4928         /* Check if the MAC address is valid, if not get a random one */
4929         if (!is_valid_ether_addr(mac_addr_temp)) {
4930                 eth_hw_addr_random(netdev);
4931                 dev_warn(priv->dev, "using random MAC address %pM\n",
4932                          netdev->dev_addr);
4933         } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) {
4934                 ether_addr_copy(netdev->dev_addr, mac_addr_temp);
4935                 ether_addr_copy(netdev->perm_addr, mac_addr_temp);
4936         } else {
4937                 return 0;
4938         }
4939
4940         if (h->ae_algo->ops->set_mac_addr)
4941                 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
4942
4943         return ret;
4944 }
4945
4946 static int hns3_init_phy(struct net_device *netdev)
4947 {
4948         struct hnae3_handle *h = hns3_get_handle(netdev);
4949         int ret = 0;
4950
4951         if (h->ae_algo->ops->mac_connect_phy)
4952                 ret = h->ae_algo->ops->mac_connect_phy(h);
4953
4954         return ret;
4955 }
4956
4957 static void hns3_uninit_phy(struct net_device *netdev)
4958 {
4959         struct hnae3_handle *h = hns3_get_handle(netdev);
4960
4961         if (h->ae_algo->ops->mac_disconnect_phy)
4962                 h->ae_algo->ops->mac_disconnect_phy(h);
4963 }
4964
4965 static int hns3_client_start(struct hnae3_handle *handle)
4966 {
4967         if (!handle->ae_algo->ops->client_start)
4968                 return 0;
4969
4970         return handle->ae_algo->ops->client_start(handle);
4971 }
4972
4973 static void hns3_client_stop(struct hnae3_handle *handle)
4974 {
4975         if (!handle->ae_algo->ops->client_stop)
4976                 return;
4977
4978         handle->ae_algo->ops->client_stop(handle);
4979 }
4980
4981 static void hns3_info_show(struct hns3_nic_priv *priv)
4982 {
4983         struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
4984
4985         dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr);
4986         dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps);
4987         dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size);
4988         dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size);
4989         dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len);
4990         dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc);
4991         dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc);
4992         dev_info(priv->dev, "Total number of enabled TCs: %u\n",
4993                  kinfo->tc_info.num_tc);
4994         dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu);
4995 }
4996
4997 static void hns3_set_cq_period_mode(struct hns3_nic_priv *priv,
4998                                     enum dim_cq_period_mode mode, bool is_tx)
4999 {
5000         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
5001         struct hnae3_handle *handle = priv->ae_handle;
5002         int i;
5003
5004         if (is_tx) {
5005                 priv->tx_cqe_mode = mode;
5006
5007                 for (i = 0; i < priv->vector_num; i++)
5008                         priv->tqp_vector[i].tx_group.dim.mode = mode;
5009         } else {
5010                 priv->rx_cqe_mode = mode;
5011
5012                 for (i = 0; i < priv->vector_num; i++)
5013                         priv->tqp_vector[i].rx_group.dim.mode = mode;
5014         }
5015
5016         /* only device version above V3(include V3), GL can switch CQ/EQ
5017          * period mode.
5018          */
5019         if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) {
5020                 u32 new_mode;
5021                 u64 reg;
5022
5023                 new_mode = (mode == DIM_CQ_PERIOD_MODE_START_FROM_CQE) ?
5024                         HNS3_CQ_MODE_CQE : HNS3_CQ_MODE_EQE;
5025                 reg = is_tx ? HNS3_GL1_CQ_MODE_REG : HNS3_GL0_CQ_MODE_REG;
5026
5027                 writel(new_mode, handle->kinfo.io_base + reg);
5028         }
5029 }
5030
5031 void hns3_cq_period_mode_init(struct hns3_nic_priv *priv,
5032                               enum dim_cq_period_mode tx_mode,
5033                               enum dim_cq_period_mode rx_mode)
5034 {
5035         hns3_set_cq_period_mode(priv, tx_mode, true);
5036         hns3_set_cq_period_mode(priv, rx_mode, false);
5037 }
5038
5039 static void hns3_state_init(struct hnae3_handle *handle)
5040 {
5041         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
5042         struct net_device *netdev = handle->kinfo.netdev;
5043         struct hns3_nic_priv *priv = netdev_priv(netdev);
5044
5045         set_bit(HNS3_NIC_STATE_INITED, &priv->state);
5046
5047         if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
5048                 set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->supported_pflags);
5049
5050         if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
5051                 set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state);
5052
5053         if (hnae3_ae_dev_rxd_adv_layout_supported(ae_dev))
5054                 set_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state);
5055 }
5056
5057 static int hns3_client_init(struct hnae3_handle *handle)
5058 {
5059         struct pci_dev *pdev = handle->pdev;
5060         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
5061         u16 alloc_tqps, max_rss_size;
5062         struct hns3_nic_priv *priv;
5063         struct net_device *netdev;
5064         int ret;
5065
5066         handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
5067                                                     &max_rss_size);
5068         netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
5069         if (!netdev)
5070                 return -ENOMEM;
5071
5072         priv = netdev_priv(netdev);
5073         priv->dev = &pdev->dev;
5074         priv->netdev = netdev;
5075         priv->ae_handle = handle;
5076         priv->tx_timeout_count = 0;
5077         priv->max_non_tso_bd_num = ae_dev->dev_specs.max_non_tso_bd_num;
5078         set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
5079
5080         handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL);
5081
5082         handle->kinfo.netdev = netdev;
5083         handle->priv = (void *)priv;
5084
5085         hns3_init_mac_addr(netdev);
5086
5087         hns3_set_default_feature(netdev);
5088
5089         netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
5090         netdev->priv_flags |= IFF_UNICAST_FLT;
5091         netdev->netdev_ops = &hns3_nic_netdev_ops;
5092         SET_NETDEV_DEV(netdev, &pdev->dev);
5093         hns3_ethtool_set_ops(netdev);
5094
5095         /* Carrier off reporting is important to ethtool even BEFORE open */
5096         netif_carrier_off(netdev);
5097
5098         ret = hns3_get_ring_config(priv);
5099         if (ret) {
5100                 ret = -ENOMEM;
5101                 goto out_get_ring_cfg;
5102         }
5103
5104         hns3_nic_init_coal_cfg(priv);
5105
5106         ret = hns3_nic_alloc_vector_data(priv);
5107         if (ret) {
5108                 ret = -ENOMEM;
5109                 goto out_alloc_vector_data;
5110         }
5111
5112         ret = hns3_nic_init_vector_data(priv);
5113         if (ret) {
5114                 ret = -ENOMEM;
5115                 goto out_init_vector_data;
5116         }
5117
5118         ret = hns3_init_all_ring(priv);
5119         if (ret) {
5120                 ret = -ENOMEM;
5121                 goto out_init_ring;
5122         }
5123
5124         hns3_cq_period_mode_init(priv, DIM_CQ_PERIOD_MODE_START_FROM_EQE,
5125                                  DIM_CQ_PERIOD_MODE_START_FROM_EQE);
5126
5127         ret = hns3_init_phy(netdev);
5128         if (ret)
5129                 goto out_init_phy;
5130
5131         /* the device can work without cpu rmap, only aRFS needs it */
5132         ret = hns3_set_rx_cpu_rmap(netdev);
5133         if (ret)
5134                 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
5135
5136         ret = hns3_nic_init_irq(priv);
5137         if (ret) {
5138                 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
5139                 hns3_free_rx_cpu_rmap(netdev);
5140                 goto out_init_irq_fail;
5141         }
5142
5143         ret = hns3_client_start(handle);
5144         if (ret) {
5145                 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
5146                 goto out_client_start;
5147         }
5148
5149         hns3_dcbnl_setup(handle);
5150
5151         ret = hns3_dbg_init(handle);
5152         if (ret) {
5153                 dev_err(priv->dev, "failed to init debugfs, ret = %d\n",
5154                         ret);
5155                 goto out_client_start;
5156         }
5157
5158         netdev->max_mtu = HNS3_MAX_MTU(ae_dev->dev_specs.max_frm_size);
5159
5160         hns3_state_init(handle);
5161
5162         ret = register_netdev(netdev);
5163         if (ret) {
5164                 dev_err(priv->dev, "probe register netdev fail!\n");
5165                 goto out_reg_netdev_fail;
5166         }
5167
5168         if (netif_msg_drv(handle))
5169                 hns3_info_show(priv);
5170
5171         return ret;
5172
5173 out_reg_netdev_fail:
5174         hns3_dbg_uninit(handle);
5175 out_client_start:
5176         hns3_free_rx_cpu_rmap(netdev);
5177         hns3_nic_uninit_irq(priv);
5178 out_init_irq_fail:
5179         hns3_uninit_phy(netdev);
5180 out_init_phy:
5181         hns3_uninit_all_ring(priv);
5182 out_init_ring:
5183         hns3_nic_uninit_vector_data(priv);
5184 out_init_vector_data:
5185         hns3_nic_dealloc_vector_data(priv);
5186 out_alloc_vector_data:
5187         priv->ring = NULL;
5188 out_get_ring_cfg:
5189         priv->ae_handle = NULL;
5190         free_netdev(netdev);
5191         return ret;
5192 }
5193
5194 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
5195 {
5196         struct net_device *netdev = handle->kinfo.netdev;
5197         struct hns3_nic_priv *priv = netdev_priv(netdev);
5198
5199         if (netdev->reg_state != NETREG_UNINITIALIZED)
5200                 unregister_netdev(netdev);
5201
5202         hns3_client_stop(handle);
5203
5204         hns3_uninit_phy(netdev);
5205
5206         if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5207                 netdev_warn(netdev, "already uninitialized\n");
5208                 goto out_netdev_free;
5209         }
5210
5211         hns3_free_rx_cpu_rmap(netdev);
5212
5213         hns3_nic_uninit_irq(priv);
5214
5215         hns3_clear_all_ring(handle, true);
5216
5217         hns3_nic_uninit_vector_data(priv);
5218
5219         hns3_nic_dealloc_vector_data(priv);
5220
5221         hns3_uninit_all_ring(priv);
5222
5223         hns3_put_ring_config(priv);
5224
5225 out_netdev_free:
5226         hns3_dbg_uninit(handle);
5227         free_netdev(netdev);
5228 }
5229
5230 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
5231 {
5232         struct net_device *netdev = handle->kinfo.netdev;
5233
5234         if (!netdev)
5235                 return;
5236
5237         if (linkup) {
5238                 netif_tx_wake_all_queues(netdev);
5239                 netif_carrier_on(netdev);
5240                 if (netif_msg_link(handle))
5241                         netdev_info(netdev, "link up\n");
5242         } else {
5243                 netif_carrier_off(netdev);
5244                 netif_tx_stop_all_queues(netdev);
5245                 if (netif_msg_link(handle))
5246                         netdev_info(netdev, "link down\n");
5247         }
5248 }
5249
5250 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
5251 {
5252         while (ring->next_to_clean != ring->next_to_use) {
5253                 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
5254                 hns3_free_buffer_detach(ring, ring->next_to_clean, 0);
5255                 ring_ptr_move_fw(ring, next_to_clean);
5256         }
5257
5258         ring->pending_buf = 0;
5259 }
5260
5261 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
5262 {
5263         struct hns3_desc_cb res_cbs;
5264         int ret;
5265
5266         while (ring->next_to_use != ring->next_to_clean) {
5267                 /* When a buffer is not reused, it's memory has been
5268                  * freed in hns3_handle_rx_bd or will be freed by
5269                  * stack, so we need to replace the buffer here.
5270                  */
5271                 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
5272                         ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
5273                         if (ret) {
5274                                 u64_stats_update_begin(&ring->syncp);
5275                                 ring->stats.sw_err_cnt++;
5276                                 u64_stats_update_end(&ring->syncp);
5277                                 /* if alloc new buffer fail, exit directly
5278                                  * and reclear in up flow.
5279                                  */
5280                                 netdev_warn(ring_to_netdev(ring),
5281                                             "reserve buffer map failed, ret = %d\n",
5282                                             ret);
5283                                 return ret;
5284                         }
5285                         hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
5286                 }
5287                 ring_ptr_move_fw(ring, next_to_use);
5288         }
5289
5290         /* Free the pending skb in rx ring */
5291         if (ring->skb) {
5292                 dev_kfree_skb_any(ring->skb);
5293                 ring->skb = NULL;
5294                 ring->pending_buf = 0;
5295         }
5296
5297         return 0;
5298 }
5299
5300 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
5301 {
5302         while (ring->next_to_use != ring->next_to_clean) {
5303                 /* When a buffer is not reused, it's memory has been
5304                  * freed in hns3_handle_rx_bd or will be freed by
5305                  * stack, so only need to unmap the buffer here.
5306                  */
5307                 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
5308                         hns3_unmap_buffer(ring,
5309                                           &ring->desc_cb[ring->next_to_use]);
5310                         ring->desc_cb[ring->next_to_use].dma = 0;
5311                 }
5312
5313                 ring_ptr_move_fw(ring, next_to_use);
5314         }
5315 }
5316
5317 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force)
5318 {
5319         struct net_device *ndev = h->kinfo.netdev;
5320         struct hns3_nic_priv *priv = netdev_priv(ndev);
5321         u32 i;
5322
5323         for (i = 0; i < h->kinfo.num_tqps; i++) {
5324                 struct hns3_enet_ring *ring;
5325
5326                 ring = &priv->ring[i];
5327                 hns3_clear_tx_ring(ring);
5328
5329                 ring = &priv->ring[i + h->kinfo.num_tqps];
5330                 /* Continue to clear other rings even if clearing some
5331                  * rings failed.
5332                  */
5333                 if (force)
5334                         hns3_force_clear_rx_ring(ring);
5335                 else
5336                         hns3_clear_rx_ring(ring);
5337         }
5338 }
5339
5340 int hns3_nic_reset_all_ring(struct hnae3_handle *h)
5341 {
5342         struct net_device *ndev = h->kinfo.netdev;
5343         struct hns3_nic_priv *priv = netdev_priv(ndev);
5344         struct hns3_enet_ring *rx_ring;
5345         int i, j;
5346         int ret;
5347
5348         ret = h->ae_algo->ops->reset_queue(h);
5349         if (ret)
5350                 return ret;
5351
5352         for (i = 0; i < h->kinfo.num_tqps; i++) {
5353                 hns3_init_ring_hw(&priv->ring[i]);
5354
5355                 /* We need to clear tx ring here because self test will
5356                  * use the ring and will not run down before up
5357                  */
5358                 hns3_clear_tx_ring(&priv->ring[i]);
5359                 priv->ring[i].next_to_clean = 0;
5360                 priv->ring[i].next_to_use = 0;
5361                 priv->ring[i].last_to_use = 0;
5362
5363                 rx_ring = &priv->ring[i + h->kinfo.num_tqps];
5364                 hns3_init_ring_hw(rx_ring);
5365                 ret = hns3_clear_rx_ring(rx_ring);
5366                 if (ret)
5367                         return ret;
5368
5369                 /* We can not know the hardware head and tail when this
5370                  * function is called in reset flow, so we reuse all desc.
5371                  */
5372                 for (j = 0; j < rx_ring->desc_num; j++)
5373                         hns3_reuse_buffer(rx_ring, j);
5374
5375                 rx_ring->next_to_clean = 0;
5376                 rx_ring->next_to_use = 0;
5377         }
5378
5379         hns3_init_tx_ring_tc(priv);
5380
5381         return 0;
5382 }
5383
5384 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
5385 {
5386         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5387         struct net_device *ndev = kinfo->netdev;
5388         struct hns3_nic_priv *priv = netdev_priv(ndev);
5389
5390         if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
5391                 return 0;
5392
5393         if (!netif_running(ndev))
5394                 return 0;
5395
5396         return hns3_nic_net_stop(ndev);
5397 }
5398
5399 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
5400 {
5401         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5402         struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
5403         int ret = 0;
5404
5405         if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5406                 netdev_err(kinfo->netdev, "device is not initialized yet\n");
5407                 return -EFAULT;
5408         }
5409
5410         clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
5411
5412         if (netif_running(kinfo->netdev)) {
5413                 ret = hns3_nic_net_open(kinfo->netdev);
5414                 if (ret) {
5415                         set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
5416                         netdev_err(kinfo->netdev,
5417                                    "net up fail, ret=%d!\n", ret);
5418                         return ret;
5419                 }
5420         }
5421
5422         return ret;
5423 }
5424
5425 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
5426 {
5427         struct net_device *netdev = handle->kinfo.netdev;
5428         struct hns3_nic_priv *priv = netdev_priv(netdev);
5429         int ret;
5430
5431         /* Carrier off reporting is important to ethtool even BEFORE open */
5432         netif_carrier_off(netdev);
5433
5434         ret = hns3_get_ring_config(priv);
5435         if (ret)
5436                 return ret;
5437
5438         ret = hns3_nic_alloc_vector_data(priv);
5439         if (ret)
5440                 goto err_put_ring;
5441
5442         ret = hns3_nic_init_vector_data(priv);
5443         if (ret)
5444                 goto err_dealloc_vector;
5445
5446         ret = hns3_init_all_ring(priv);
5447         if (ret)
5448                 goto err_uninit_vector;
5449
5450         hns3_cq_period_mode_init(priv, priv->tx_cqe_mode, priv->rx_cqe_mode);
5451
5452         /* the device can work without cpu rmap, only aRFS needs it */
5453         ret = hns3_set_rx_cpu_rmap(netdev);
5454         if (ret)
5455                 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
5456
5457         ret = hns3_nic_init_irq(priv);
5458         if (ret) {
5459                 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
5460                 hns3_free_rx_cpu_rmap(netdev);
5461                 goto err_init_irq_fail;
5462         }
5463
5464         if (!hns3_is_phys_func(handle->pdev))
5465                 hns3_init_mac_addr(netdev);
5466
5467         ret = hns3_client_start(handle);
5468         if (ret) {
5469                 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
5470                 goto err_client_start_fail;
5471         }
5472
5473         set_bit(HNS3_NIC_STATE_INITED, &priv->state);
5474
5475         return ret;
5476
5477 err_client_start_fail:
5478         hns3_free_rx_cpu_rmap(netdev);
5479         hns3_nic_uninit_irq(priv);
5480 err_init_irq_fail:
5481         hns3_uninit_all_ring(priv);
5482 err_uninit_vector:
5483         hns3_nic_uninit_vector_data(priv);
5484 err_dealloc_vector:
5485         hns3_nic_dealloc_vector_data(priv);
5486 err_put_ring:
5487         hns3_put_ring_config(priv);
5488
5489         return ret;
5490 }
5491
5492 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
5493 {
5494         struct net_device *netdev = handle->kinfo.netdev;
5495         struct hns3_nic_priv *priv = netdev_priv(netdev);
5496
5497         if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5498                 netdev_warn(netdev, "already uninitialized\n");
5499                 return 0;
5500         }
5501
5502         hns3_free_rx_cpu_rmap(netdev);
5503         hns3_nic_uninit_irq(priv);
5504         hns3_clear_all_ring(handle, true);
5505         hns3_reset_tx_queue(priv->ae_handle);
5506
5507         hns3_nic_uninit_vector_data(priv);
5508
5509         hns3_nic_dealloc_vector_data(priv);
5510
5511         hns3_uninit_all_ring(priv);
5512
5513         hns3_put_ring_config(priv);
5514
5515         return 0;
5516 }
5517
5518 static int hns3_reset_notify(struct hnae3_handle *handle,
5519                              enum hnae3_reset_notify_type type)
5520 {
5521         int ret = 0;
5522
5523         switch (type) {
5524         case HNAE3_UP_CLIENT:
5525                 ret = hns3_reset_notify_up_enet(handle);
5526                 break;
5527         case HNAE3_DOWN_CLIENT:
5528                 ret = hns3_reset_notify_down_enet(handle);
5529                 break;
5530         case HNAE3_INIT_CLIENT:
5531                 ret = hns3_reset_notify_init_enet(handle);
5532                 break;
5533         case HNAE3_UNINIT_CLIENT:
5534                 ret = hns3_reset_notify_uninit_enet(handle);
5535                 break;
5536         default:
5537                 break;
5538         }
5539
5540         return ret;
5541 }
5542
5543 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num,
5544                                 bool rxfh_configured)
5545 {
5546         int ret;
5547
5548         ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num,
5549                                                  rxfh_configured);
5550         if (ret) {
5551                 dev_err(&handle->pdev->dev,
5552                         "Change tqp num(%u) fail.\n", new_tqp_num);
5553                 return ret;
5554         }
5555
5556         ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT);
5557         if (ret)
5558                 return ret;
5559
5560         ret =  hns3_reset_notify(handle, HNAE3_UP_CLIENT);
5561         if (ret)
5562                 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT);
5563
5564         return ret;
5565 }
5566
5567 int hns3_set_channels(struct net_device *netdev,
5568                       struct ethtool_channels *ch)
5569 {
5570         struct hnae3_handle *h = hns3_get_handle(netdev);
5571         struct hnae3_knic_private_info *kinfo = &h->kinfo;
5572         bool rxfh_configured = netif_is_rxfh_configured(netdev);
5573         u32 new_tqp_num = ch->combined_count;
5574         u16 org_tqp_num;
5575         int ret;
5576
5577         if (hns3_nic_resetting(netdev))
5578                 return -EBUSY;
5579
5580         if (ch->rx_count || ch->tx_count)
5581                 return -EINVAL;
5582
5583         if (kinfo->tc_info.mqprio_active) {
5584                 dev_err(&netdev->dev,
5585                         "it's not allowed to set channels via ethtool when MQPRIO mode is on\n");
5586                 return -EINVAL;
5587         }
5588
5589         if (new_tqp_num > hns3_get_max_available_channels(h) ||
5590             new_tqp_num < 1) {
5591                 dev_err(&netdev->dev,
5592                         "Change tqps fail, the tqp range is from 1 to %u",
5593                         hns3_get_max_available_channels(h));
5594                 return -EINVAL;
5595         }
5596
5597         if (kinfo->rss_size == new_tqp_num)
5598                 return 0;
5599
5600         netif_dbg(h, drv, netdev,
5601                   "set channels: tqp_num=%u, rxfh=%d\n",
5602                   new_tqp_num, rxfh_configured);
5603
5604         ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
5605         if (ret)
5606                 return ret;
5607
5608         ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
5609         if (ret)
5610                 return ret;
5611
5612         org_tqp_num = h->kinfo.num_tqps;
5613         ret = hns3_change_channels(h, new_tqp_num, rxfh_configured);
5614         if (ret) {
5615                 int ret1;
5616
5617                 netdev_warn(netdev,
5618                             "Change channels fail, revert to old value\n");
5619                 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured);
5620                 if (ret1) {
5621                         netdev_err(netdev,
5622                                    "revert to old channel fail\n");
5623                         return ret1;
5624                 }
5625
5626                 return ret;
5627         }
5628
5629         return 0;
5630 }
5631
5632 static const struct hns3_hw_error_info hns3_hw_err[] = {
5633         { .type = HNAE3_PPU_POISON_ERROR,
5634           .msg = "PPU poison" },
5635         { .type = HNAE3_CMDQ_ECC_ERROR,
5636           .msg = "IMP CMDQ error" },
5637         { .type = HNAE3_IMP_RD_POISON_ERROR,
5638           .msg = "IMP RD poison" },
5639         { .type = HNAE3_ROCEE_AXI_RESP_ERROR,
5640           .msg = "ROCEE AXI RESP error" },
5641 };
5642
5643 static void hns3_process_hw_error(struct hnae3_handle *handle,
5644                                   enum hnae3_hw_error_type type)
5645 {
5646         int i;
5647
5648         for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) {
5649                 if (hns3_hw_err[i].type == type) {
5650                         dev_err(&handle->pdev->dev, "Detected %s!\n",
5651                                 hns3_hw_err[i].msg);
5652                         break;
5653                 }
5654         }
5655 }
5656
5657 static const struct hnae3_client_ops client_ops = {
5658         .init_instance = hns3_client_init,
5659         .uninit_instance = hns3_client_uninit,
5660         .link_status_change = hns3_link_status_change,
5661         .reset_notify = hns3_reset_notify,
5662         .process_hw_error = hns3_process_hw_error,
5663 };
5664
5665 /* hns3_init_module - Driver registration routine
5666  * hns3_init_module is the first routine called when the driver is
5667  * loaded. All it does is register with the PCI subsystem.
5668  */
5669 static int __init hns3_init_module(void)
5670 {
5671         int ret;
5672
5673         pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
5674         pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
5675
5676         client.type = HNAE3_CLIENT_KNIC;
5677         snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s",
5678                  hns3_driver_name);
5679
5680         client.ops = &client_ops;
5681
5682         INIT_LIST_HEAD(&client.node);
5683
5684         hns3_dbg_register_debugfs(hns3_driver_name);
5685
5686         ret = hnae3_register_client(&client);
5687         if (ret)
5688                 goto err_reg_client;
5689
5690         ret = pci_register_driver(&hns3_driver);
5691         if (ret)
5692                 goto err_reg_driver;
5693
5694         return ret;
5695
5696 err_reg_driver:
5697         hnae3_unregister_client(&client);
5698 err_reg_client:
5699         hns3_dbg_unregister_debugfs();
5700         return ret;
5701 }
5702 module_init(hns3_init_module);
5703
5704 /* hns3_exit_module - Driver exit cleanup routine
5705  * hns3_exit_module is called just before the driver is removed
5706  * from memory.
5707  */
5708 static void __exit hns3_exit_module(void)
5709 {
5710         pci_unregister_driver(&hns3_driver);
5711         hnae3_unregister_client(&client);
5712         hns3_dbg_unregister_debugfs();
5713 }
5714 module_exit(hns3_exit_module);
5715
5716 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
5717 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
5718 MODULE_LICENSE("GPL");
5719 MODULE_ALIAS("pci:hns-nic");